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Delta Tau ACC-65M User's Manual

1. I O node 16 bit Register 2 16 bit Register 3 31 23 15 7 0 Data Inputs Outputs Inputs Outputs Register Gate3 i MacroInB j 0 Gate3 MacroOutB j 0 Gate3 MacroInA j 0 Gate3 i MacroOutA 0 24 bit Where i is the card index and j is the I O node number Example Digital I O mapping at MACRO IC 0 Bank A I O node 2 Digital Outputs Bitwise Digital Inputs Bitwise PTR Outputl Gate3 0 MacroOutA 2 0 13 PTR Inputl Gate3 0 MacroInA 2 0 Output2 gt Gate3 0 MacroOutA 2 0 12 PTR Input2 gt Gate3 0 MacroInA 2 0 PTR Output3 gt Gate3 0 MacroOutA 2 0 PTR Input3 gt Gate3 0 MacroInA 2 0 PTR Output4 gt Gate3 0 MacroOutA 2 0 di PTR Input4 gt Gate3 0 MacroInA 2 0 PTR Output5 gt Gate3 0 MacroOutA 2 0 2 1 PTR Input5 gt Gate3 0 MacroInA 2 0 2 PTR Output6 Gate3 0 MacroOutA 2 0 2412 PTR Input6 gt Gate3 0 MacroInA 2 0 5 PTR Output7 Gate3 0 MacroOutA 2 0 4 1 Input7 Gate3 0 MacroInA 2 0 4 PTR Output8 Gate3 0 MacroOutA 2 0 5 12 Input8 gt Gate3 0 MacroInA 2 0 5 PTR Output9 Gate3 0 MacroOutA 2 0 16 1 PTR Input9 gt Gate3 0 MacroInA 2 0 16 PTR Output1l0 gt Gate3 0 MacroOutA 2 0 Ag PTR Input10 gt Gate3 0 MacroInA Z2 0 Js PTR Outputll Gate3 0 MacroOutA 2 0 8 1 Inputll
2. EG commandis prior to establishing Master Slave communication This will latch a MACRO communication error MACRO Status window It may be more practical to place it in a MACRO ring all by itself with the ring controller Set up and save all the necessary parameters and Note then place it back into the system with the other devices If the ACC 65M is to be inserted into an existing MACRO ring system If the ACC 65M has been initialized and set up previously then it may E have a station number saved to it If you know that number e g 11 1 then you would address it with the command MacroStation1 ote If the ACC65M is at factory default settings then the user needs to issue a MacroStation255 This command searches the MACRO ring for new and unassigned devices If successful the AsciiCom status bit is highlighted in the MACRO status window Terminal Online 192 168 0 200 SS Status Online 192 168 0 200 SSH 1 Motor Status Coordinate Status Global Status MACRO Status ECAT Status Ring 0 Station No 0 Type N A x Description Active BrkDetected False 0 BrkReceivd AsciiCmdRdy ErrorsFault Fase AsciiRespRdy SynchFault BrkMsgSent RingError False 0 MacroServoSync TestEnabled False PwrOnErrCntr SynchMaster Tue 00 RingBrkStationNum None Master Fase 00 Now you talking directly to
3. 1 1 0 vag VBB MMBZ33VALT BTS711 L1 075 076 _ 9 O24VRET 1 E o cso ces VBB Otuf 2 GND1 2 VBB OUTOB IN1 OUTI 5 1 4 17 50105 UE J i GND3 4 ves 55 OUTIO 3 OUT3 43 5 OUTIT x do 573 4 H3 1 1 al IN4 VBB 1 10 11 1 VBB VBB MMBZ33VAI MMBZ33VALTI BTS711 L1 D78 AHAAA HAHAAHA HO OU OO O OU OO O0 fos coroBi e oxvoooBi cows Bi coro o D77 m h NE 9 O24VRET W ces VBB VBB otut 24 GND 1 2 vee 91 OUTI2 N1 OUT 17 5 00773 x29 sT1 2 OUT He IN2 VBB 6 ves I5 4 s sq OUT3 mi 50 ST3 4 OUTA 19 1 IN4 VBB VBB VBB MMBZ33VAI MNBZ33VALTI 5711 11 Lj joss AUF O24VRET ves 5 GND1 2 VBB iN OUT X 59 ST1 2 OUT2 2 VBB 5 GND3 4 VBB OUT3 90 ST3 4 OUTA 124 VBB VBB VBB MMBZ33VALTI 5711 11 jea AUF 1 Th O24VRET i Uoo 35 ces coa T VBB VBB otut 2 1 GND1 2 vee 219 4 OUT20 4 OUT 17 1 00721 50 511 2 OUT IN2 VBB
4. MACRO structure elements require Power PMAC firmware version 1 5 8 305 or newer Note Using the ACC 65M with Power 17 Accessory 65M AN Power PMAC firmware versions older than 1 5 8 305 must use explicit address offsets found in the memory map appendix section Note Below are example tables showing I O Node numbers of the first 4 PMAC3 Style MACRO ICs Gate3 0 Bank A Bank B ACC 65M Node 6 7 10 11 2 3 6 7 11 12 Ring Controller I O Node 617110 11 18 19 22 23 26 27 Gate3 1 Bank A Bank B ACC 65M Node 2 3 6 7 10 11 2 3 6 7 11 12 Ring Controller I O Node 7 34 35 38 39 42 43 50 51 54 55 58 59 Gate3 2 Bank A Bank B Ring Controller I O Node 7 66 ACC 65M Node 2 3 6 7 10 11 2 3 6 7 11 12 Ring Controller I O Node 7 98 99 102 103 106 107 114 115 118 119 122 123 Using the ACC 65M with Power 18 Accessory 65M Digital Inputs and Outputs The ACC 65M firmware transfers automatically the digitals inputs and outputs into from the upper 24 bits of the 24 bit data register of the chosen Style Node ACC 65M Digital Inputs Outputs 16 bit Register 1
5. ACC 65M revision 101 and older 5 24 0 RET Connector 2 Female Pind Mating Molex 2 pin Male Pn29 _ ___ 24 0 __ Pin Symbol Function 1 24 VDC RET Logic power return 2 24 VDC PWR 24 logic and outputs power supply Molex Mating Connector p n 0444412002 Molex Crimper tool p n 63811 0400 Molex Pins p n 0433751001 Delta Tau Mating Connector p n 014 000F02 HSG Delta Tau Pins p n 014 043375 001 Connector Pinouts and Wiring 59 Accessory 65M Digital Inputs Connector Phoenix Contact MSTB 2 5 5 08 15 Positions female Mating Phoenix Contact LR13631 male 1 INPUT 2 INPUT 4 1 4 I I IN IN IN IN RET N N 10 N N N N RET N N N RET INPUT 9 12 1 14 RETURN FOR INPUTS O12 16 INPUT 13 17 INPUT 15 15 19 RETURNFORINPUISIMI 21 NIS IN19 INPUT 19 INDO RET N21 IN22 IN23 IN24 RET N the inputs return lines are internally tied together They are labeled for each set of four inputs for wiring convenience Note Connector Pinouts and Wiring 60 Accessory 65M Wiring the digital Inputs The inputs can be wired to be either sinking into or sourcing out of the ACC 65M For sourcing connect the 24V side of the power supply to the individual input switches a
6. ves CE ouT22 8 INS OUTS 13 OUT23 0 ST3 4 INA VBB Hf VBB VBB MNBZ33VALTI BTS711 L1 F1424V ceo 4 D83 D84 AUF e e 1 Appendix Schematics Accessory 65M ADC DAC Relays Connector OPT 1 Only C186 0 4 A 12V Aut 2190 R18 4 1 Ninei3daim 200 0 s 1 1 2 C188 6 uL M6134AIM Te U25A it RP18C gt i amsled 1 BP2IA 2 6014 peice 5 47KSIPBI m Y ki eng S014 22051 8 47KSIPBI 4 RP20A 2 RP20B 4 C187 E 47KSIP8I 47KSIPBI o ma pe E 13 4 s 21 4 1 Rig 12 2 S014 220SIP8I 0191 195 R20 4 1 FS1LM8134AIM 200 0K mm 1 1 BPIBA 2 C193 6 U26A 19 e NO 5 268 S 6 5 BPAIC 6 S014 5 47KSIPBI 10 10260 RP19B 014 2208IP8l 47KSIPBI 5 RP20C 6 7 RP20D g 0192 eii AUSSI 47KSIPBI 47KSIPBI 13 FS LM6134AIM ADC1 di cidem 34 7 RP2ID ADCT 12 0269 PLANE udis c DGND PLANE wo _ CO 14 WDO gt 4 1 i 2 CTRL2 20 097 ED 1K
7. 2 0 2 0 2 Inputi3 2Gate2 0 Macro 2 0 12 1 PTR Input14 gt Gate2 0 Macro 2 0 13 1 PTR Input15 gt Gate2 0 Macro 2 0 14 1 PTR Input16 gt Gate2 0 Macro 2 0 15 1 PTR Input17 gt Gate2 0 Macro 2 0 16 1 PTR Input18 gt Gate2 0 Macro 2 0 17 1 Input19 gt Gate2 0 2 0 18 1 PTR Input20 gt Gate2 0 Macro 2 0 19 1 PTR Input21 gt Gate2 0 Macro 2 0 20 1 PTR 22 gt 2 0 2 0 21 1 PTR Input23 gt Gate2 0 Macro 2 0 22 1 PTR Input24 gt Gate2 0 Macro 2 0 23 1 Bitwise mapping into the PMAC2 Style MACRO structure elements require Power firmware version 1 5 8 305 or newer Note Using the ACC 65M with Power PMAC2 Accessory 65M Digital Outputs The outputs can be written to using the structure element s full word Example PMAC2 MACRO IC 0 Node 2 PTR Outputs Gate2 0 Macro 2 0 Structure Address However with the PMAC2 Style MACRO IC the outputs require an image Element word to report the state of each output and allow bitwise mapping Sys Udata 4 U USER 16 This can be done a simple PLC and using one of the unsigned user sys Udata 8 U USER 32 shared memory data elements Sys Udata i The table to the right shows 4 of the possible 65K registers available Sys Udata 12 U USER 48 Sys Udata
8. 16 bit Register 1 4 4 4 4 4 4 Ro I O data register 16 bit Register 2 GP Relays Bits 27 and 28 31 23 15 Bank B Bank A Data Inputs Outputs Inputs Outputs Register Gate3 i MacroInB j 3 Gate3 i MacroOutB j 3 Gate3 MacroInA j 3 Gate3 i MacroOutA j 3 3 16 bit Example General purpose relay outputs mapping at MACRO IC 0 both banks and all nodes GP Relay 1 GP Relay 2 2 GpRelayl gt Gate3 0 MacroOutA 2 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutA 2 3 28 1 3 PTR GpRelayl gt Gate3 0 MacroOutA 3 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutA 3 3 28 1 6 GpRelayl gt Gate3 0 MacroOutA 6 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutA 6 3 28 1 7 GpRelayl Gate3 0 MacroOutA 7 3 27 1 PTR GpRelay2 Gate3 0 MacroOutA 7 3 28 1 10 PTR GpRelayl gt Gate3 0 MacroOutA 10 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutA 10 3 28 1 11 PTR GpRelayl gt Gate3 0 MacroOutA 11 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutA 11 3 28 1 2 PTR GpRelayl gt Gate3 0 MacroOutB 2 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutB 2 3 28 1 3 PTR GpRelayl gt Gate3 0 MacroOutB 3 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutB 3 3 28 1 6 GpRelayl 5Gate3 0 MacroOutB 6 3 27 1 GpRelay2 Gate3 0 MacroOutB 6 3 28 1 7 GpRelayl gt Gate3
9. 75202 5 MMBD301LT1 GRN SOT23 5 SOT23 ip 1 12 x a AGND PLANE 2 DGND PLANE 1 0126 R61 2 a l nine 2 pe 1 CTRL3 20 ED 1K NC7SZO2NB MMBD301LT1 GRN SOT23 5 50723 amp ip 1 8 FBR12ND0S GND Appendix C Schematics
10. Accessory 65M APPENDIX C SCHEMATICS Digital Inputs BS RP25 2 1KDIP10C D7A 2 1_571 01 D8A AA D9A di 571 01XX 26 2 EANN D10A 4 VN 571 01XX 2 bU 1 D11A A 1 571 01 012 574 01 _2 1KDIP10C 2 1 571 01 16 AA 571 01XX 2 D17A 571 01XX AA 1 1KDIP10C GND 2 1 571 01 D24A AA 1 571 01 2 571 01 Appendix Schematics Accessory 65M Digital Inputs continued NO PLANES HERE RP41 NO PLANES HERE U40A_ SMT4 C1 M L ACHB El 1 027 2 MMBZ33VALT1 MMBZ33VALT1 2 MMBZ33VALT1 tuf MMBESVGALT 5 1 5 1 al o 049 050 C13 1uf 2 051 052 RP42 2 2KSIP8l 4 3 SZ50SL INE SMT4 hol El 525051 1 U40C 5 4 2 3 ACHB 1 525051 1 U40D SMT4 Gi ACHB El PS2505L INEC 1 RP46 U42A 5 4 gt M 3 5 YYW ACHB El lo co o gt 1 2KSIP8I 031 1 029 2 MMBZ33VALT1
11. a MMBZ33VALT1 2 MMBZ33VALT1 tuf cis l all o 4 M 4 4 C18 1uf MMBESVGALT 5 1 MMBESVRALTt D53 D54 D55 D56 RP48 2 2KSIP8l PS2505L INEC U42B SMTA acna ciH ho ACHB 1 525051 1 U42C 5 4 1 Hacna c1 H ACB El 1 525051 1 0420 5 4 ACHA C Hj ACHB El 525051 1 52 RP53 5 4 27 ACHB El Njoo 1 2 51 8 1 1 3 33 2 MMBZ33VALT1 1 IMBZ33VALT1 1 amp Da4 D36 2 HHB AAA AB HHHHH HHHH 22022220 2222022220 2222 MMBZ33VALT1 MMBZ33VALT1 1 MMBZ5VGALT1 MMBZ5VGALT1 sun 4 M 4 4 cos 1 2KSIP8I 057 058 059 060 RP54 2 2KSIP8l 525051 1 U44B 5 4 ACHA TIN 1 ACHB 1 525051 1 U44C 5 4 21 1 525051 1440 5 4 ACHA 5 ACHB El 525051 1 4 RP59 U46A 5 4 ii d S58 84 PIBOOdYT OOOOrt C
12. 7 Enyir nmental Specifications Da amp El ctrica Specifications 8 Physical layout Rn 9 USING THE 65 WITH POWER 00 4 400 001 40000000 0 10 Step 1 Preparing Ring Controller cube Rad oet 11 Step 2 MACRO ASCII 13 Step 3 Finishing up ACC 65M Setup Sed hax tuac ade 15 sem ah u 16 Step 5 Using the Data 17 Digital Inputs and QuIDW1S 19 Analog Inputs ADCs and Outputs DACGs 20 Using the ADCs for Servo 4 22 General Purpose 23 USING THE 65 WITH POWER PMAC 2 25 Step 1 Preparing the Ring Controller n 26 Step 2 MACRO ASCII Communication 27 Step 3 Finishing up ACC 65M 29 Step d VO Data u U au 30 Steps Using the ACC 65M Data 31 Digital Inputs a
13. ACC 65M You should be able to issue commands such type version VERS etc Using the ACC 65M with Power PMAC2 27 Accessory 65M The goal of MACRO ASCII communication is to enable a selected I O node over which Master Slave communication can be used to set up the rest of the necessary parameters of the ACC 65M Choosing I O node 2 as an example enabling it is done through 1996 Terminal Online 192 168 0 200 SSH Now communicating to MACRO station 255 8 One node is sufficient for transferring all data available on E ACC 65M Note Issue a MacroStationClose to terminate MACRO ASCII communication Terminal Online 192 168 0 200 SSH 8 Macro Station Closed Using the ACC 65M with Power PMAC2 Accessory 65M Step 3 Finishing up the ACC 65M Setup Having enabled a selected I O node on ACC 65M through MACRO ASCII i e node 2 the corresponding I O node should be enabled on the ring controller side For example at MACRO IC 0 Gate2 0 MacroEnable Gate2 0 MacroEnable 4 Master Slave communication should be now available over I O node 2 And the following parameters can be downloaded from the project editor For example station number 1 and I O node 2 52 111 1 Station number assignment user configurable for future MACRO ASCII communication e g MACSTA1 52 1992 6527 See below 52 1997 0 See below MS2 1995
14. The base address is typically stated in hardware reference manual of E the MACRO hardware device i e ACC 5E3 It can be found by CUm subtracting Gate3 i a from Sys piom And the data registers offsets for each I O node Data Register VO 24 bit 1 16 bit 274 16 bit 3 16 bit Node In Out In Out In Out In Out 430 530 434 534 438 538 43C 53C N 460 560 464 564 468 568 46C 56C E 470 570 474 574 478 578 47 57 10 4A0 5A0 4A4 5A4 4A8 5A8 4AC 5AC 11 5480 5580 5484 584 8 5588 4 5 620 720 624 724 628 728 62 72 630 730 634 734 638 738 63 73 660 760 664 764 668 768 66 76 5 670 770 674 774 678 778 67 77 10 6A0 7A0 6A4 7A4 6A8 7A8 6AC 7AC 11 6B0 5780 684 5784 5688 5788 6 7 The data registers offsets are found by subtracting Gate3 i MacroInA j k a In or Out from Gate3 i a Appendix A Memory Map 73 Accessory 65M Using the ACC 65M with Address Offsets With the PMAC3 Style MACRO IC the MACRO data is found in the upper fields Style 1 Node 3 24 bit Register 16 bit Register 1 16 bit Register 2 16 bit Register 3 23 1 5 7 0 Example mapping the ACC 65M data with address offsets into PMAC3 Style MACRO IC 0 Bank A node 2 requires adding the base addres
15. 3079429 8 16 8 M5018 gt x 07942A 8 16 S 54 M5041 gt x 07B429 8 16 S M5042 gt x 07B42A 8 16 S 23 5019 gt 3079420 8 16 8 5020 gt 507942 8 16 5 55 M5043 gt x 07B42D 8 16 S 5044 gt 507 42 8 16 5 26 5021 gt 5079431 8 16 5 5022 gt 5079432 8 16 5 58 M5045 gt x 07B431 8 16 S 5046 gt 507 432 8 16 5 27 5023 gt 3079435 8 16 8 5024 gt 5079436 8 16 5 59 M5047 gt x 07B435 8 16 S 5048 gt 507 436 8 16 5 The ADCs on the older revision of the 65 2 pin Molex logic connector are 12 bits Note Older revision of the ACC 65M 2 pin Molex logic connector ADC 1 ADC 2 ADC 1 ADC 2 2 5001 gt 5078421 12 12 5 5002 gt 5078422 12 12 6 34 M5025 gt x 07A421 12 12 S M5026 gt x 07A422 12 12 S 3 5003 gt 5078425 12 12 8 5004 gt 5078426 12 12 6 35 5027 gt 07 425 12 12 5 M5028 gt x 07A426 12 12 S 6 5005 gt 5078429 12 12 5 M5006 2X 07842A 12 12 8 38 M5029 gt x 07A429 12 12 S M5030 gt x 07A42A 12 12 S 7 M5007 gt x 07842D 12 12 S M5008 gt x 07842E 12 12 S 39 M5031 gt x 07A42D 12 12 S M5032 gt x 07A42E 12 12 S 10 5009 gt 5078431 12 12 5 M5010 2X 078432 12 12 8 42 5033 gt 5074431 12 12 5 5034 gt 507 432 12 12 5 11 5011 gt 5078435 12 12 5 5012 gt 5078436 12 12 5 43 M5035 gt x 07A435 12 12 S 5036 gt 507
16. M6037 gt X 07B421 8 16 S 6038 gt 507 422 8 16 5 19 6015 gt 5079425 8 16 5 6016 gt 5079426 8 16 5 51 M6039 gt X 07B425 8 16 S 6040 gt 507 426 8 16 5 22 6017 gt 5079429 8 16 5 M6018 gt X 07942A 8 16 S 54 M6041 gt X 07B429 8 16 S M6042 gt X 07B42A 8 16 S 23 M6019 gt x 07942D 8 16 S 6020 gt 507942 8 16 5 55 M6043 X 07B42D 8 16 8 M6044 X 907B42E 8 16 8 26 6021 gt 5079431 8 16 5 M6022 gt x 079432 8 16 S 58 M6045 gt x 07B431 8 16 S 6046 gt 5078432 8 16 5 27 6023 gt 5079435 8 16 5 6024 gt 5079436 8 16 5 59 6047 gt 507 435 8 16 5 M6048 gt X 07B436 8 16 S Note Although the DACS are 12 bit filtered PWM they are mapped to the upper 16 bits Using the ACC 65M with Turbo PMAC2 55 Accessory 65M Image Word Since these are read write registers and in order for the user to report the value of the analog output s in software a simple image word PLC must be written For creating an image word it is suggested to use one of the open memory registers in Turbo 10FO 10FF which can be either X or Y For example using Y 10FE and X 10FE to mirror image DAC 1 and DAC 2 respectively at Node 2 define N2Firstl6 M6001 define N2Secondl6 M6002 N2Firstl6 5X 078421 8 16 5 Node 2 1st 16 bit register N2Second16 gt X 078422 8 16 S Node 2 2nd 16 bit register define D
17. 3264 _5 _10 register or suggested pointer the user should see 0 0 0 3264 5 10 6527 10 20 Using the ACC 65M with Power 2 37 Accessory 65M Using the ADCs for Servo Feedback Using an analog ADC input for servo requires bringing it into the encoder conversion table ECT Using the automatic ECT utility in the IDE software Type Single 32 bit register read Source Address I O node structure element address i e Gate2 i Macro j 1 LSB starting bit of ADC data typically 16 of Bits Used ADC data number of bits 16 or 12 Result Units set to 1 to shift data 16 bits for proper scaling v v v v v ECT entry number Download V Display All ECT Entries Type ECT entry input 1 Single 32 bit register read ECT entry output Detailed ECT Setup PowerPMAC Structure EncoderPlot _ ECT entry 1 details Source Address Acc5E 0 Macro 2 1 a LSB Bit 16 Integrate of Bits Used 16 Integrator Bias Term Result Units per LSB 1 Limited Quantity Limit Magnitude of Cycles to Limit Alternately using the ECT structure elements 1 Gate2 0 Macro 2 1 a 16 16 0 EncTable 1 type EncTable 1 pEnc 1 1 1 1 1 2 EncTable 1 index3 EncTable 1 index4 0 EncTable 1 index5 0 EncTable 1 ScaleFactor 1 EXP2 16 The ADC data is now processed in the encoder conversion table A motor element structure can
18. 436 12 12 5 18 5013 gt 5079421 12 12 5 M5014 2X 079422 12 12 8 50 M5037 gt x 07B421 12 12 S 5038 gt 507 422 12 12 6 19 5015 gt 5079425 12 12 5 M5016 2X 079426 12 12 8 51 5039 gt 507 425 12 12 5 5040 gt 5078426 12 12 5 22 5017 gt 5079429 12 12 5 5018 gt 507942 12 12 8 54 M5041 gt x 07B429 12 12 S M5042 gt x 07B42A 12 12 S 23 M5019 gt x 07942D 12 12 S 5020 gt 507942 12 12 6 55 M5043 gt x 07B42D 12 12 S 5044 gt 507842 12 12 8 26 M5021 gt x 079431 12 12 S 5022 gt 5079432 12 12 8 58 5045 gt 507 431 12 12 5 5046 gt 5078432 12 12 8 27 M5023 gt x 079435 12 12 S 5024 gt 5079436 12 12 8 59 M5047 gt x 07B435 12 12 S 5048 gt 507 436 12 12 5 Using the ACC 65M with Turbo PMAC2 52 Accessory 65M Testing the Analog Inputs The ADC input data is typically signed bipolar If the ACC 65M is set by jumpers to read unsigned unipolar data then the M Variable definitions should be changed to gt 16 16 0 With the 16 bit ADCs the user should expect to see Single Ended Signal VDC Differential Signal VDC Software Counts Unipolar Bipolar 10 5 32768 0 0 0 10 5 32768 With the 12 bit 5 the user should expect to see Single Ended Signal VDC Differential Signal VDC Software Counts Uni
19. Accessory 65M INTRODUCTION The accessory 65M ACC 65M is a boxed MACRO peripheral I O module with 24 isolated self protected digital inputs and 24 isolated self protected digital outputs The ACC 65M is typically configured as a slave in a MACRO ring via either fiber optic or RJ 45 connection The inputs can be either sinking or sourcing depending on the user s wiring The outputs are strictly sourcing up to 600 mA per channel 2 Optional sets of two analog inputs two analog outputs and two general purpose relay contacts are available The ACC 65M is compatible with the following Delta Tau controllers All Turbo PMAC2 board level MACRO cards Turbo PMAC2 Ethernet Ultralite Power or Turbo UMAC with ACC 5E Power or Turbo Brick family equipped with the MACRO option Power UMAC with ACC 5E3 Power PMAC EtherLite vy v V VV V Introduction 6 Accessory 65M SPECIFICATIONS Part Number 2 ACC 65M 4 3 7 4 0 0 0 0 0 0 0 Fiber Optic MACRO Transceiver 0 No Option 00 No Additional Options XX Factory assigned digits C RJ 45 MACRO Connector 2 Two relay contact outputs for Additional Options Two 12 bit bipolar DAC outputs 10 Volts Fact Assi d Opti aues staat tst eM Two 16 bit bipolar inputs 32767 Counts MACRO Node Options The possibl
20. Ring Controller I O Node 2 3 6 7 10 11 24 bit X 78420 578424 78428 X 7842C 78430 78434 16 bit X 78421 X 78425 X 78429 X 7842D X 78431 X 78435 16 bit 78422 X 78426 X 7842A X 7842E 78432 X 78436 16 bit X 78423 X 78427 7842 X 7842F X 78433 X 78437 Ring Controller MACRO IC 1 Node Registers ACC 65M Node 2 3 6 7 10 11 Ring Controller I O Node 18 19 22 23 26 27 24 bit X 79420 X 79424 79428 X 7942C 79430 79434 16 bit X 79421 X 79425 X 79429 X 7942D 79431 X 79435 16 bit X 79422 79426 X 7942A X 7942E 79432 X 79436 16 bit 79423 X 79427 579428 X 7942F 79433 X 79437 Ring Controller MACRO IC 2 Node Registers ACC 65M Node 2 3 6 7 10 11 Ring Controller 1 Node 34 35 38 39 42 43 24 bit X 7A420 X 7A424 X 7A428 X 7A42C K 7A430 K 7A434 16 bit X 7A421 X 7A425 X 7A429 X 7A42D K 7A431 X 7A435 16 bit X 7A422 X 7A426 X 7A42A X 7A42E K 7A432 K 7A436 16 bit X 7A423 X 7A427 X 7A42B X 7A42F K 7A433 K 7A437 Ring Controller MACRO IC 3 Node Registers ACC 65M I O Node 2 3 6 7 10 11 Ring Controller I O Node 50 51 54 55 58 59 24 bit X 7B420 X 7B424 X 7B428 X 7B42C X 7B430 X 7B434 16 bit X 7B421 X 7B425 X 7B429 X 7B42D X 7B431 7 435 16 bit X 7B422 X 7B426 X 7B42A X 7B42E X 7B432 X 7B43
21. connected Ring Controller The MACRO LED must be green on all the devices in the MACRO ring for the software setup to work properly Note Using the ACC 65M with Power PMAC3 10 Accessory 65M Step 1 Preparing the Ring Controller The Power PMAC used to control MACRO ring must be configured as a ring controller in order to establish communication and transfer data over the ring Following is a summary list of the relevant parameters which need to be set properly on the Ring Controller side to allow proper functionality of the MACRO ring and configuration of the ACC 65M Structure Element Typical Setting Sys ClockSource Set by Firmware 48 Gate3 i PhaseFreq 9000 Gate3 i ServoClockDiv 3 Sys ServoPeriod 1000 Gate3 i ServoClockDiv 1 Gate3 i PhaseFreq 0 442 Sys PhaseOverServoPeriod 1 Gate3 i ServoClockDiv 1 0 250 Sys RtIntPeriod 0 Macro TestPeriod 20 Macro TestMaxErrors Macro TestPeriod 10 2 Macro TestReqdSynchs Macro TestPeriod Macro TestMaxErrors 18 Gate3 i MacroModeA 403000 Gate3 i MacroModeB 1000 Gate3 i MacroEnableA iFC00000 Gate3 i MacroEnableB i 1 F800000 The Power PMAC can interface to up to 16 PMAC3 Style MACRO ICs Note Detailed description of these parameters can be found in the pertaining Ring Controller Hardware Reference User manual or in the Power SRM Software Reference Manual These setti
22. 0 MacroOutB 7 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutb 7 3 28 1 10 PTR GpRelayl gt Gate3 0 MacroOutB 10 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutB 10 3 28 1 11 PTR GpRelayl gt Gate3 0 MacroOutB 11 3 27 1 PTR GpRelay2 gt Gate3 0 MacroOutB 11 3 28 1 Using the ACC 65M with Power PMAC3 23 Accessory 65M Testing the General Purpose Relays The following table summarizes the relay functions That is the relationship between the common line and the normally open normally closed lines GP Relay 1 Connection between Connection between pins 13 COM and 14 NO pins 13 COM and 6 NC Software bit 0 Open Closed Software bit 1 Closed Open GP Relay 2 Connection between Connection between pins 7 COM and 8 NO pins 7 COM and 15 NC Software bit 0 Open Closed Software bit 1 Closed Open Using the ACC 65M with Power 24 Accessory 65M USING THE ACC 65M WITH POWER PMAC2 A Power PMAC2 Style MACRO Ring Controller is comprised of a Power UMAC with one or more ACC 5Es in the rack The first step into setting up ACC 65M 15 to make sure that the MACRO cables are plugged in in the correct manner The OUT from the Ring Controller or previous device goes into the IN of the ACC 65M The IN of the ACC 65M goes into the OUT of the ring controller or the next device on the ring For example the illustration below shows ho
23. 24 AN The inputs and outputs data registers are the same These are read write registers Note Using the ACC 65M with Turbo PMAC2 49 Accessory 65M Inputs The inputs can be simply mapped into the corresponding 24 bit register and queried at will Direct bitwise mapping is possible for single I O point access For example using I O node 2 ACC 65M Digital Inputs node 2 define define define define define define define define define define define define define define define define define define define define define define define define nputl nput2 nput3 nput4 nput5 nput6 nput7 nput8 nput9 nput nput nput nput nput nput nput nput nput nput19 nput20 nput21 nput22 nput23 nput24 lt J Gy Cn Ps M7001 M7002 M7003 M7004 M7005 M7006 M7007 M7008 M7009 70 70 70 70 70 70 70 70 70 7019 7020 7021 7022 7023 7024 ON 1 S nputl X nput2 gt X nput3 X nput4 X nput5 X nput6 gt X nput7 gt X nput8 gt X nput9 gt X nput nput nput nput nput nput nput nput nput nput nput20 gt X nput21 gt X 22 gt nput23 gt X nput24 gt X 078420 0 078420 1 5078420 2 5078420 3 078420 4 078420 5 078420 6 078420 7 078420 8 0 gt 1 gt 2 gt 3 gt 4 gt 5 gt 6 gt Parks
24. 35 38 39 42 43 Gate2 3 65 Nodes 2 3 6 7 11 12 Ring Controller I O Node 50 51 54 55 58 59 AN A Power PMAC CPU can interface with up to 32 PMAC2 Style MACRO ICs ICs present are reported by the variable Macro ICs Note 32 Using the ACC 65M with Power 2 Accessory 65M Digital Inputs and Outputs PMAC2 Style I O Node ACC 65M Digital Inputs Outputs The ACC 65M firmware transfers automatically the i digitals inputs and outputs into from the lower 24 bit data 16 bit Register 1 register of the chosen I O node 16 bit Register 2 16 bit Register 3 23 15 7 The PMAC2 Style MACRO IC structure element for this register is Structure Element Data Register Gate2 i Macro j 0 24 bit Where gt iis the PMAC2 Style MACRO IC index gt jis the node number Digital Inputs Example Digital inputs mapping at PMAC2 MACRO IC 0 I O node 2 Digital Inputs Bitwise Inputl gt Gate2 0 Macro 2 0 0 1 PTR Input2 gt Gate2 0 Macro 2 0 1 1 PTR Input3 gt Gatez2 0 121101 2 1 PTR Input4 gt Gate2 0 Macro 2 0 3 1 PTR Input5 gt Gate2 0 Macro 2 0 4 1 PTR Input6 gt Gate2 0 Macro 2 0 5 1 PTR Input7 gt Gate2 0 Macro 2 0 6 1 PTR Input8 gt Gate2 0 Macro 2 0 7 1 PTR Input9 gt Gate2 0 Macro 2 0 8 1 PTR Input10 gt Gate2 0 Macro 2 0 9 1 PTR Input11 gt Gate2 0 Macro 2 0 12 gt
25. 4 H acna Ht ACHB Et 1 70 71 US0A 5 4 C1 SN pa 3 5 ACHB 1 colon gt gt v 1 2KSIP8I mE E 5 a MMBZ33VALT1 ro SI MMBZ33VALT1 tuf cas 1 MMBESVGALTi 5 1 sur 1 res Sp Saye CI pA T Y C38 1 2KSIP8I 2 RP72 2 2KSIP8l 4 3 SZ505L INE USOB SMTA hol ACHB 1 525051 1 USOC 5 4 1 14 acna H 1 24 ACHB Ei 1 525051 1 U50D 5 4 JACHA Ct P El 525051 1 4444 PLANES HERE NO PLANES HERE Appendix C Schematics 79 Accessory 65M Digital Outputs D1B 4 AA 3 2 28 477 D2B 571 01 4 b 3 D3B 4 7KSIP8l 4 8 571 01 2 29 4 D4B 6 I 571 01 4 3 4 7KSIP8l DSB 571 01 4 AA 3 2 RP30 4 D6B 6 VN 4 y 3 18 D7B 4 7KSIP8l 4 ME 8 571 01XX 1 RPI D8B j AA 571 01 4 b 3 Lu 4 7KSIP8I D9B 571 01XX AA 3 2 RP32 2 0108 6 OUTO4 571 01 4 y M D11B 4 7KSIP8l MT 8 571 01XX 1 2 gu 4 0128 B 01XX 4 3
26. 8 gt 571 01XX VE 322 1 3 BAA D15B 4 7KSIP8l 4 AA 3 571 01XX 2 RP35 4 D16B OUT20 6 AS 571 01 4 3 18 4 7KSIP8I D17B 571 01XX AA RP36 4 LA D18B 6 AA NH 571 01XX 4 3 18 By D19B 4 7KSIP8I z RP37 4 EAA D20B 6 j AA 571 01 4 gt 3 8 4 7KSIP8I 021 571 01 4 AA 3 2 RP38 D22B 0 f AA 571 01 4 gt 3 18 A D23B 4 7KSIP8I AA 9 4 gt 3 571 01 2 2 0248 571 01 4 y 3 J8 4 7KSIP8I 571 01XX YOu Co _ Co Nooo YOu Co _ J O1c2 GND Appendix C Schematics 80 Accessory 65M Digital Outputs continued W a 4 ves E outi H 511 2 OUT2 Hie 1 IN2 VBB GND3 4 VBB His 4 Aline 8 INS OUTS 43 T OUTOS 573 4 1 INA VBB 1 i 9 vag VBB TUE MMBZ33VALT BTS711 L1 44 D73 D74 ADF 9 O24VRET 75 24 GND1 2 I 1 Wi OUTI 20 511 2 OUT S VBB GND3 4 VBB 00706 Ns outs Hs 00707 x o 573 4 1 INA VBB
27. 8 gt 9 gt 50784 50784 50784 50784 0784 0784 0784 0784 0784 0784 50784 50784 50784 50784 50784 20 9 20 10 20 20 20 20 20 20 20 20 20 20 20 20 21 20 22 20 23 1 iS Using the 65 with Turbo 2 50 Accessory 65M Outputs The outputs require gt Writing to the whole 24 bit register gt An image word for reporting the status to the user This will be done in a simple PLC logic It is possible to write to the I O node register bits individually but not more than one at the time Thus the use of an image word Note For creating an image word it is suggested to use one of the open memory registers in Turbo 10F0 10FF which can be either X or Y For example using X 10FF with I O node 2 ACC 65M Digital Outputs Mapping define Outputl M7025 Outputl 2X 10FF 0 define Output2 M7026 Output2 gt X S10FF 1 define Output3 M7027 Output3 gt X S10FF 2 define Output4 M7028 Output4 gt X S10FF 3 define Output5 M7029 Output5 gt X S10FF 4 define Output6 M7030 Output6 gt X S10FF 5 define Output7 M7031 Output7 gt X S10FF 6 define Output8 M7032 Output8 gt X S10FF 7 define Output9 M7033 Output9 gt X S10FF 8 define Output10 M7034 Outputl0 2X 10FF 9 1 define Outputl11 M7035 Output11 gt X S10FF 10 define Out
28. CLOSE Using the ACC 65M with Power PMAC2 34 Accessory 65M Analog Inputs ADCs and Outputs DACs 2 Style I O Node 24 bit Register The ACC 65M firmware transfers automatically the analog inputs and outputs from to the 1 and 2 16 bit data registers of the chosen I O node ACC 65M ADC 1 DAC 1 ACC 65M ADC 2 DAC2 16 bit Register 3 M Ww 15 7 The PMAC2 Style MACRO structure elements for these registers are Structure Element Data Register Gate2 i Macro j 1 1 16 bit Gate2 i Macro j 2 279 16 bit Where gt iisthe PMAC2 Style MACRO IC index gt jis the I O node number Analog Input ADCs The ADC inputs can be mapped directly into the node s structure elements and read directly without further processing Typically the ACC 65M 18 configured by the factory for signed ADC inputs Example Signed ADC inputs at PMAC2 Style MACRO IC 0 Node 2 ADC1 gt Gate2 0 Macro 2 1 8 16S 0 Node 2 ADC 1 signed ADC2 gt Gate2 0 Macro 2 2 8 16S 0 Node 2 ADC 2 signed Example Unsigned ADC inputs at PMAC2 Style MACRO IC 0 Node 2 ADC1 gt Gate2 0 Macro 2 1 8 16 IC 0 Node 2 ADC 1 unsigned ADC2 gt Gate2 0 Macro 2 2 8 16 IC 0 Node 2 ADC 2 unsigned logic connector are 12 bits The suffix of the address mapping should The ADC inputs on the older revision of the ACC 65M 2 p
29. E 63 64 Wiring the Analog ADC sene etes t ci Ead 65 Wiring the Analog DAC Outputs sous itisssate e sasad 66 Wiring the General Purpose Relays us ete ROI QE XE UNA 66 MACRO Comme Chom P 68 Universal Serial Bus USB iicet eerta 69 TROUBLESHOOTING u u u INDE ER EUM QE MEO bU Mob 70 Initializing the ACC 65M Clearing usus 70 Error Codes 7 Segment LED iS vata ia Sen ptu a UR tu E TIU S RES QU MU S 71 LED 72 Input and Output LED Indicators P 72 Satis LED ien ER pe e a ieee 72 Re elay Statns PT 72 MACRO LEmnk TD oso 22 APPENDIX A MEMORY 8 73 Style 73 Using the ACC 65M with Address Offsets 74 PMAQ Style A SIC UAM n 75 Using the ACC 65M with PMAC2 Address Offsets 76 APPENDIX B E POINT JUMPERS 77 APPENDIX CO SCHEMATICS 78 Introduction 5
30. Gate3 0 MacroInA 2 0 Bs PTR Outputl12 Gate3 0 MacroOutA 2 0 19 1 PTR Input12 gt Gate3 0 MacroInA 2 0 19 PTR Output13 gt Gate3 0 MacroOutA 2 0 20 1 PTR Input13 gt Gate3 0 MacroInA 2 0 20 PTR Output14 gt Gate3 0 MacroOutA 2 0 21 1 PTR Input14 gt Gate3 0 MacroInA 2 0 21 PTR Output15 gt Gate3 0 MacroOutA 2 0 22 1 PTR Input15 gt Gate3 0 MacroInA 2 0 22 PTR Outputl6 gt Gate3 0 MacroOutA 2 0 23 1 PTR Input16 gt Gate3 0 MacroInA 2 0 23 PTR Outputl17 gt Gate3 0 MacroOutA 2 0 24 1 PTR Inputl17 gt Gate3 0 MacroInA 2 0 24 PTR Output18 gt Gate3 0 MacroOutA 2 0 25 1 PTR Input18 gt Gate3 0 MacroInA 2 0 25 PTR Output19 gt Gate3 0 MacroOutA 2 0 26 1 PTR Input19 gt Gate3 0 MacroInA 2 0 26 PTR Output20 gt Gate3 0 MacroOutA 2 0 27 1 PTR Input20 gt Gate3 0 MacroInA 2 0 27 PTR Output21 gt Gate3 0 MacroOutA 2 0 28 1 PTR Input21 gt Gate3 0 MacroInA 2 0 28 PTR Output22 gt Gate3 0 MacroOutA 2 0 29 1 PTR Input22 gt Gate3 0 MacroInA 2 0 29 PTR Output23 gt Gate3 0 MacroOutA 2 0 30 1 PTR Input23 gt Gate3 0 MacroInA 2 0 30 PTR Output24 gt Gate3 0 MacroOutA 2 0 31 1 PTR Input24 gt Gate3 0 MacroInA 2 0 31 Using the ACC 65M with Power PMAC3 19 Accessory 65M Analog Inputs ADCs and Outputs DACs The ACC 65M firmware transfers automatically the analog inputs and outputs from to upper 16 bits of the 1 and 274 16 bit data regis
31. Open Closed Software bit 1 Closed Open GP Relay 2 Connection between Connection between pins 7 COM and 8 NO pins 7 COM and 15 NC Software bit 0 Open Closed Software bit 1 Closed Open Using the ACC 65M with Turbo PMAC2 58 Accessory 65M CONNECTOR PINOUTS AND WIRING 24 VDC Input This connector is used to bring in the 24 VDC logic power supply It must be able to provide an instantaneous current of about 2 amperes With the new revision of the ACC 65M using the Phoenix PCB edge connector the power supply for the digital and analog outputs is brought in separately through pin 3 This allows the logic power to stay on in the case of a fuse trip too much current draw out of the outputs This connection can be made using a 16 AWG wire directly from a protected power supply In situations where the power supply is shared with other devices it may be desirable to insert a filter in this connection Also it is highly recommended that each device be wired back to the power supply terminals independently Phoenix PCB Edge Connector 3 pin connector Pin Symbol Function Description Notes 1 24 VDC RET Common Logic power return 2 24 VDC Control Input Logic power supply 24 VDC 10 2A 3 24 VDC PWR Input Digital Analog outputs power supply 12 24 VDC Phoenix part ZEC 1 5 3 ST 5 0 C2 R1 3 18883051 Delta Tau part 014 188305 001 For Internal Use
32. This will latch a MACRO communication error MACRO Status window It may be more practical to place it in a MACRO ring all by itself with the ring controller Set up and save all the necessary parameters and Note then place it back into the system with the other devices If the ACC 65M is to be inserted into an existing MACRO ring system If the ACC 65M has been initialized and set up previously then it may E have a station number saved to it If you know that number e g 11 1 then you would address it with the command MacroStation1 ote If the ACC65M is at factory default settings then the user needs to issue a MacroStation255 This command searches the MACRO ring for new and unassigned devices If successful the AsciiCom status bit is highlighted in the MACRO status window Terminal Online 192 168 0 200 SS Status Online 192 168 0 200 SSH n X m Motor Status Coordinate Status Global Status MACRO Status ECAT Status Ring 0 Station No 0 Type N A x Description Active BrkDetected False 0 BrkReceivd AsciiCmdRdy ErrorsFault Fase AsciiRespRdy SynchFault BrkMsgSent RingError False 0 MacroServoSync TestEnabled False PwrOnErrCntr SynchMaster Tue 00 RingBrkStationNum None Master False 00 Now you are talking directly to the ACC 65M You should be able to issue commands such as type TYPE version VERS e
33. an image word to report the written values gt relay outputs can be read and written to separately An image word is required to allow writing to both outputs simultaneously Explicit address offsets mapping is useful for older Power PMAC firmware versions Note Power PMAC users with firmware versions 1 5 8 305 or newer are E highly encouraged to use the structure element addressing aforementioned in this manual Note Appendix A Memory Map 76 Accessory 65M APPENDIX B E POINT JUMPERS The ACC 65M jumpers are for internal use and set by the factory Jumper Configuration Default gt Remove jumper to enable watchdog timer NOT gt Install jumper to disable watchdog timer not advised Installed F2 2 e Jump pins 1 and 2 for firmware download through USB port 2 3 gt Jump pins 2 and 3 for normal operation E3 Jump pins 1 and 2 for 9600 baud serial port operation NOT gt Remove jumper for 38400 baud serial port operation Installed F4 2 3 Jump pins 1 and 2 for RJ 45 connection Factory gt Jump pins 2 and 3 for fiber optic connection Set gt Remove jumper for ACC 65M NOT gt nstall jumper for 68 Installed JP2 JP7 Reserved for Future Use N A gt Jump pins 1 and 2 for re initialization power up reset NOT gt Remove jumper for normal operation Installed Appendix B E Point Jumpers 77
34. any of the following is true gt over clocked In this mode the CPU indicates that is has been overloaded with computation and cannot accomplish tasks in timely manner The only possible culprit with the ACC 65M 15 the user programmable code locally stored on the ACC 65M PLCC gt Incorrect clock settings The phase clock setting on the 65 does not match the ring controller s phase clock gt Hardware 5V failure internal or short In this mode the internal 5 logic circuitry has failed Check PWR Led Status Relay Status LED RLY1 when lit this LED indicates that the first amplifier enable relay is activated RLY2 when lit this LED indicates that the second amplifier enable relay is activated MACRO Link LED Green Indicates that the MACRO ring is properly wired Red Indicates a ring break or MACRO ring cables not connected in the correct order IN OUT Troubleshooting 72 Accessory 65M APPENDIX A MEMORY MAP Style ASIC The Power PMAC CPU can interface with up to 16 Style ASICs which base addresses are Index cud Index Address Address Gate3 8 920000 Gate3 1 904000 Gate3 9 924000 Gate3 2 908000 Gate3 10 928000 Gate3 3 90C000 Gate3 11 92C000 Gate3 4 910000 Gate3 12 930000 Gate3 5 914000 Gate3 13 934000 Gate3 6 918000 Gate3 14 938000 Gate3 7 91C000 Gate3 15 93C000
35. existing MACRO ring system It may be more practical to place it in a MACRO ring all by itself with the ring controller Set up and save all the necessary parameters and Note then place it back into the system with the other devices If the ACC 65M has been initialized and set up previously then it may have a station number saved to it If you know that number e g 11 1 then you would address it with the command Note If the ACC65M is at factory default settings then the user needs to issue a MACSTA255 This command searches the MACRO ring for new and unassigned station devices The following message appears the Pewin32Pro2 software and a notification yellow ribbon appears in the bottom of the window indicating that MACRO ASCII communication is now active g PEWIN32PRO2 C PROGRAM FILES X86 DELTA TAU PMAC EXECUTIVE PRO2 SUITE PEWIN32PRO2 PEWIN32PRO2_Defaultx64INI Vindow 42 Global Status Device 0 QMAC TURBO V1 94872 06 06 201 0 x to a MACRO Station with ID 603740 minal Watch and MACRO Ring CTRL T to come out of MACRO in msecs gt Witing APROGRAM FILES X86 DELTA TAUNPMAC EXECUTIVE PRO2 SUITE PEWIN32PRO2 D ownloadT emporaryFik ri yy table C PROGRAM FILES 86 DELTA EXECUTIVE PR02 SUITENPEWIN32PRO2Do vente pies Change Monitor Interrupt Monitor UnSolicte
36. full 16 bit word However due to the read write nature of the I O node register they cannot be written to simultaneously using two independent bits e g terminal command 6051 1 6052 1 Two mirror image bits can be used to make this possible For creating an image word it is suggested to use one of the open memory registers in Turbo 10FO 10FF which can be either X or Y For example using bits 19 and 20 of Y 10FF to mirror image Relay 1 and Relay 2 at Node 2 define N2Thirdl6Bitl19 M6099 define N2Third16Bit20 M6100 N2Third16Bit19 gt X 078423 19 N2Third16Bit20 gt X 078423 20 define Relayl M6101 define Relay2 M6102 1 gt 510 19 Relay2 gt Y S10FF 20 Relayl 0 Relay2 0 Open PLC 1 Clear N21 21 rhirdl16Bit19 Relayl rhirdl16Bit20 Relay2 Close Node 2 Node 2 Mirror Bit Relay 1 Mirror Bit Relay 2 third 16 bit register third 16 bit register bit 19 bit 20 Save Initialize to zero or desired state Save Initialize to zero or desired state Using the ACC 65M with Turbo PMAC2 57 Accessory 65M Testing the General Purpose Relays The following table summarizes the relay functions That is the relationship between the common line and the normally open normally closed lines GP Relay 1 Connection between Connection between pins 13 COM and 14 NO pins 13 COM and 6 NC Software bit 0
37. which base addresses Card Card Index T O Address Address 588000000 Gate2l16 840000 Gate2 1 804000 Gate2 17 844000 Gate2 2 808000 Gate2 18 848000 Gate2 3 80C000 Gate2 19 84C000 Gate2 4 810000 Gate2 20 850000 Gate2 5 814000 Gate2 21 854000 Gate2 6 818000 Gate2 22 858000 Gate2 7 81C000 Gate2 23 85C000 Gate2 8 820000 Gate2 24 860000 Gate2 9 824000 Gate2 25 864000 Gate2 10 828000 Gate2 26 868000 Gate2 11 82C000 Gate2 27 86C000 Gate2 12 830000 Gate2 28 870000 Gate2 13 834000 Gate2 29 874000 Gate2 14 838000 Gate2 30 878000 Gate2 15 83C000 Gate2 31 87C000 The base address is typically stated in the hardware reference manual of E the MACRO hardware device i e ACC 5E It can be found by subtracting Gate2 i a from Sys piom Note And the data registers offsets for each I O node 3 6 7 10 11 24 bit 130 160 170 1A0 1 0 1 16 bit 134 164 174 1 4 5184 2 16 bit 138 168 178 1 8 1B8 3 16 bit 13C 16C 17C 1AC 1BC The data registers offsets are found by subtracting C7 qate2 i Macroljl k a from Gate2 i a Note Appendix A Memory Map 75 Accessory 65M Using the ACC 65M with PMAC2 Address Offsets When using explicit address offsets the MACRO I O data is found in the upper fields 3 Accessing PMAC2 Style
38. y Power Supply B NC 424V GND E in High True Output to Logic Device C pe el y E b oe _ 4 gt Gy A C 12 24 VDC Power Supply SS A GND 24V D 12 24 VDC Logic Device GND 24V Input Sourcing Low True Output to Logic Device A cm I Ga 12 24 VDC Power Supply WC 424V GND L 2 lt uy 324V Zz d 12 24VDC Input p Logic Device GND k Sinking Low True Output to Logic Device 4 a _ _ di b SN 12 24 VDC Power Supply Ww WC GND 24V GS 12 2 4 GND Logic Device 24V Input Connector Pinouts and Wiring 67 Accessory 65M MACRO Connection These connections are used to connect the MACRO cables to the ACC 65M OUT IN Fiber Connector lol Pin Symbol Function 1 IN MACRO Ring Receiver 2 OUT MACRO Ring Transmitter The fiber optic cables typically acquired from Delta Tau are 62 5 125 multi mode glass fiber terminated in an SC style connector with an optical wavelength of 1 300 nm OUT IN RJ45 CATSe LALA L r L r Pin Symbol Function Description 1 DATA Data Differential MACRO Signal 2 DATA Data Differential MACRO Signal 3 8 Unused Unused terminated pins The RJ 45 cable used for
39. 16 U USER 64 A large number of self addressed default Sys pushm pointers in Power PMAC use Sys Udata 0 therefore it is highly advised NOT to use it as a general purpose user shared memory Note Example using Sys Udata 4 Digital Outputs Bitwise PTR Output1 gt U USER 16 0 1 PTR Output2 gt U USER 16 1 1 PTR Output3 gt U USER 16 2 1 PTR Output4 gt U USER 16 3 1 PTR Output5 gt U USER 16 4 1 PTR Output6 gt U USER 16 5 1 PTR Output7 gt U USER 16 6 1 PTR Output8 gt U USER 16 7 1 PTR Output9 gt U USER 16 8 1 PTR Output10 gt U USER 16 9 1 PTR Output11 gt U USER 16 10 1 PTR Output12 U USER 16 PTR Output13 gt U USER 16 12 1 PTR Output14 gt U USER 16 13 1 PTR Output15 gt U USER 16 14 1 PTR Output16 gt U USER 16 15 1 PTR Output17 gt U USER 16 16 1 PTR Output18 gt U USER 16 17 1 PTR Output19 gt U USER 16 18 1 PTR Output20 gt U USER 16 19 1 PTR Output21 gt U USER 16 20 PTR Output22 gt U USER 16 21 PTR Output23 gt U USER 16 22 1 PTR Output24 gt U USER 16 23 1 And the mirror PLC which should be executing constantly PTR ICO N2Twenty4 gt Gate2 0 Macro 2 0 0 Node 2 24 bit register PTR OutputsMirror gt U USER 16 Sys Udata 4 mirror word OutputsMirror 0 Save Initialize to zero or desired state OPEN PLC 1 ICO N2Twenty4 OutputsMirror Update data register
40. 16891 16941 16991 MACRO IC node activation 50 00 1F8000 2F8000 3F8000 170 172 174 176 MACRO IC Auxiliary register enable 0 71 73 75 177 MACRO IC Protocol node control 0 Detailed description of these parameters can be found in the pertaining Ring Controller Hardware Reference User manual or in the Turbo SRM Software Reference Manual These settings require a SAVE followed by a reset to take effect Note Using the ACC 65M with Turbo PMAC2 42 Accessory 65M Once implemented these settings should ensure that the Turbo PMAC is now a MACRO ring Controller And the global status in the Pewin32Pro2 software should look like Using the ACC 65M with Turbo PMAC2 43 Accessory 65M Step 2 MACRO ASCII Communication There are two possible MACRO communication methods between the ring controller and the ACC 65M MACRO ASCII communication Direct communication to the 65 it is useful for initial setup troubleshooting and allows to eventually establish Master Slave MS communication Master Slave MS communication Establishing MS commands through an I O node is ultimately what we want commandis prior to establishing Master Slave communication This will Make sure that the watch window does not contain any MS latch MACRO communication error in Global Status Note 2 If the ACC 65M is to be inserted into an
41. 2 gt 078423 20 34 M6075 gt x 07A423 19 6076 gt 5074423 20 3 6053 gt 5078427 19 6054 gt 078427 20 35 6077 gt 5074427 19 6078 gt 5074427 20 6 6055 gt 507842 19 M6056 gt x 07842B 20 38 6079 gt 507442 19 6080 gt 507442 20 7 6057 gt 07842 19 6058 gt 07842 20 39 M6081 gt x 07A42F 19 6082 gt 507 42 20 10 6059 gt 5078433 19 M6060 gt x 078433 20 42 M6083 gt x 07A433 19 6084 gt 5074433 20 11 6061 gt 5078437 19 6062 gt 5078437 20 43 6085 gt 5074437 19 M6086 gt x 07A437 20 18 6063 gt 5079423 19 6064 gt 5079423 20 50 M6087 gt x 07B423 19 M6088 gt x 07B423 20 19 6065 gt 5079427 19 M6066 gt x 079427 20 51 6089 gt 507 427 19 M6090 gt x 07B427 20 22 m6067 gt x 07942B 19 M6068 gt x 07942B 20 54 6091 gt 507 42 19 M6092 gt x 07B42B 20 23 6069 gt 07942 19 M6070 gt x 07942F 20 55 6093 gt 507 42 19 M6094 gt x 07B42F 20 26 M6071 gt x 079433 19 6072 gt 5079433 20 58 6095 gt 507 433 19 6096 gt 5078433 20 27 6073 gt 079437 19 M6074 gt x 079437 20 59 M6097 gt x 07B437 19 M6098 gt x 07B437 20 It is possible to toggle these relay outputs separately or simultaneously software by writing to the
42. 4 Nodes enabling e g I O node 2 MS2 18 181 Ring check period see equation below MS2 19 28 Maximum ring error count see equation below 52 110 153 Minimum synch packet count see equation below 5 1992 and 1997 are set so that the phase frequency is the same as the ring controller 117964 8 x1000 Gate3 i PhaseFra MS2 1992 3 Where is rounding to the higher integer MS2 1997 Gate3 i PhaseClo ckDiv If the clock settings not at default MS 18 I9 and 110 can be calculated using the following equations Assuming a typical ring check period RingCheckPeriod of 20 milliseconds and a fatal packet error MaxErrorPercent of 15 percent MS2 I8 INT Ringcheck Period 117964 8 x MS2 1997 1 M 2x MS2 1992 3 MS2 I9 mf 52 18 e rcent 52 MS2 I8 MS2 I9 These equations must be computed ahead of time expressions cannot be written directly into MS variables Note These settings must be retained on the ACC 65M This is done by issuing a save e g 55 2 followed by a reset e g MS 2 to take effect jun Using the ACC 65M with Power PMAC3 15 Accessory 65M Step 4 Data Registers A single I O node is sufficient for transferring the data to from the ACC 65M This is handled automatically in the firmware The user s responsibility is choosing an available node enabling it per t
43. 4080 Typical setting for MACRO slave device MS2 1996 0F8004 Nodes enabling e g I O node 2 MS2 18 181 Ring check period see equation below MS2 19 28 Maximum ring error count see equation below 52 110 153 Minimum synch packet count see equation below 5 1992 and 1997 are set so that the phase frequency is the same as the ring controller MS2 1992 Gate2 0 PwmPeriod MS2 1997 Gate2 0 PhaseClockD iv If the clock settings are not at default MS 18 I9 and 110 can be calculated using the following equations Assuming a typical ring check period RingCheckPeriod of 20 milliseconds and a fatal packet error MaxErrorPercent of 15 percent MS2 I8 INT Ringcheck Period 117964 8 x MS2 1997 1 2x MS2 1992 3 MS2 19 52 18 rent 52 10 MS2 I8 MS2 I9 These equations must be computed explicitly ahead of time expressions cannot be written directly into MS variables Note These settings must be retained on the ACC 65M This is done by issuing a save e g MSSAVE2 followed by a reset e g MS 2 to take effect Using the ACC 65M with Power PMAC2 29 Accessory 65M Step 4 Data Registers A single I O node is sufficient for transferring the data to from the ACC 65M This is handled automatically in the firmware The user s responsibility is choosing an available I O node enabling it per the example above and find
44. 6 16 bit X 7B423 X 7B427 X 7B42B X 7B42F X 7B433 X 7B437 Using the ACC 65M with Turbo PMAC2 48 Accessory 65M Step 5 Using the ACC 65M Data Having configured the following gt Set up the MACRO ring controller VV Set up the phase clock to be the same across the ring Enabled a selected I O node on the ACC 65M Enabled the corresponding I O node on the ring controller side Saved and reset both the ACC 65M and the ring controller The ACC 65M data should now be available to access from the ring controller side Digital Inputs and Outputs The ACC 65M firmware transfers automatically the digitals inputs and outputs into from the 24 bit register of the chosen I O node This is a read write register thus it is the same for both inputs and outputs Node Suggested M Variable 6988 gt 5079434 0 24 node 34 35 38 39 42 43 50 51 54 55 58 59 Suggested M Variable 6989 gt 50784 6999 gt 7000 gt 6990 gt 6991 gt 6992 gt 6993 gt 6994 gt 6995 gt 6996 gt 6997 gt 6998 gt 507 4 507 4 507 4 507 4 507 4 507 4 507 4 507 4 50784 50784 50784 20 0 24 24 0 24 28 0 24 2 0 24 30 0 24 34 0 24 20 0 24 24 0 24 28 0 24 2 0 24 30 0 24 34 0
45. AC1 M5091 Node 2 DAC 1 define DAC2 M5092 Node 2 DAC 2 DAC1 gt Y S10FF 8 16 S Image word using open memory DAC2 gt X S10FE 8 16 S Image word using open memory 0 Save Initialize to zero or desired state DAC2 0 Save Initialize to zero or desired state Open plc 1 clear N2Firstl6 DAC1 Update data register DAC 1 25 16 DAC2 Update data register DAC 2 Close With this PLC executing constantly the user now writes to DACI DAC2 M Variables to manipulate the voltage outputs of the analog outputs Testing the Analog Outputs These are 10V outputs where 10 volts corresponds to the value of MS2 I992 Remember that this is dictated by the ring phase clock do not attempt to change it in this section With the default clock setting e g 52 1992 6527 and by writing to the analog output data register e g using the suggested M Variable the user should see Suggested M Variable Single Ended VDC Differential VDC 6527 10 20 3264 5 10 0 0 0 3264 5 10 6527 10 20 Using the ACC 65M with Turbo PMAC2 56 cessory 65M General Purpose Relay Outputs The relay outputs are mapped into bits 19 and 20 of the 3 16 bit register of the I O node ACC 65M GP Relays Data Registers UO GP Relay 1 GP Relay 2 1 2 2 m6051 gt x 078423 19 605
46. Accessory 65M DELTA TAU Data Systems Inc NEW IDEAS IN MOTION Single Source Machine Control BaRSESSASEASAREESASHARRESSAESSESSASSERSSSSSASSSSASESASSETARSSSESASAOSSSEHESSSHESEMHEES Power Flexibility 21314 Lassen St Chatsworth 91311 Tel 818 998 2095 Fax 818 998 7807 www deltatau com Copyright Information 2013 Delta Tau Data Systems Inc rights reserved This document is furnished for the customers of Delta Tau Data Systems Inc Other uses are unauthorized without written permission of Delta Tau Data Systems Inc Information contained in this manual may be updated from time to time due to product improvements etc and may not conform in every respect to former issues To report errors or inconsistencies call or email Delta Tau Data Systems Inc Technical Support Phone 818 717 5656 Fax 818 998 7807 Email support deltatau com Website http www deltatau com Operating Conditions All Delta Tau Data Systems Inc motion controller products accessories and amplifiers contain static sensitive components that can be damaged by incorrect handling When installing or handling Delta Tau Data Systems Inc products avoid contact with highly insulated materials Only qualified personnel should be allowed to handle this equipment In the case of industrial applications we expect our products to be protected from hazardous or conductive materials and or en
47. C which should be executing constantly for PMAC2 MACRO IC 0 node 2 N2Third16 gt Gate 2 Macro 2 2 Node 2 354 16 bit data register OPEN PLC 1 N2Third16 GPRelayl 2 19 Update bit place in bit 19 N2Third16 GPRelay2 2 20 Update bit place in bit 20 CLOSE Using the ACC 65M with Power PMAC2 39 Accessory 65M Testing the General Purpose Relays The following table summarizes the relay functions That is the relationship between the common line and the normally open normally closed lines GP Relay 1 Connection between Connection between pins 13 COM and 14 NO pins 13 COM and 6 NC Software bit 0 Open Closed Software bit 1 Closed Open GP Relay 2 Connection between Connection between pins 7 COM and 8 NO pins 7 COM and 15 NC Software bit 0 Open Closed Software bit 1 Closed Open Using the ACC 65M with Power 2 40 Accessory 65M USING THE ACC 65M WITH TURBO PMAC2 The first step into setting up the ACC 65M is to make sure that the MACRO cables are plugged in in the correct manner The OUT from the Ring Controller or previous device goes into the IN of the ACC 65M The IN of the ACC 65M goes into the OUT of the ring controller or the next device on the ring A Turbo PMAC Ring Controller can be one of the following gt Any Turbo 2 Ultralite board level e g PCI gt T
48. DOUIDSUIBWNIWHOCOVIATIBHONHO S m z 3 4 C1 TN m z gt ACHB 1 colo 2 ret6 39 L 4 TERMBLK 30 NO MMBZ3 IMBZ3 Ha SI MMBZ33VALT1 RSS MMBZ33VALT1 1 MMBZ5VGALT1 MMBZ5VgALT1 2 sn all coa 1 2KSIP8I 061 062 063 064 RP60 2 2KSIP8l PS2505L INEC U46B_ SMT4 ACHA Ci i TN P1 ACHB El 525051 U46C 5 4 4 ct cB 2 525051 U46D 5 4 ACHA Ci E ACHB Et 525051 1 1_ 64 4 RP65 U48A 5 4 3 3 C1 TN YN 5 ACHB 1 o colon 7 1 2KSIP8I SES Fj 8 Io S amp MMBZ33VALT1 E MMBZ33VALT1 tuf cao 1 MMBE5V8ALT1 MMBZ5VgALT1 mgs da ii xus k M 4 1 2KSIP8I RP66 2 2KSIP8l 525051 1 4 3 SZ505L INE U48B SMT4 Ci TN ACHB 1 525051 U48C 5 4 1 Hacna ciHi ACIB 1 525051 1 U48D 5
49. Example 05 53502 Otherwise it can be accessed manually using an M Variable pointer Note that you would need to divide by 32 or 2 5 for proper scaling Example M1000 gt X 3502 0 24 S Using the ACC 65M with Turbo PMAC2 54 Accessory 65M Analog Outputs DACs The analog outputs DACs map out to the same registers as the analog inputs ADCs These are read write registers The ACC 65M firmware handles automatically the transfer of this data ACC 65M Analog Output Data Registers DAC 1 DAC 2 DAC 1 DAC 2 2 M6001 gt x 078421 8 16 S M6002 gt x 078422 8 16 S 34 6025 gt 507 421 8 16 5 M6026 gt X 07A422 8 16 S 3 M6003 gt x 078425 8 16 S M6004 gt x 078426 8 16 S 35 6027 gt 07 425 8 16 5 6028 gt 07 426 8 16 5 6 M6005 gt x 078429 8 16 S M6006 gt x 07842A 8 16 S 38 6029 gt 07 429 8 16 5 6030 gt 507 42 8 16 5 7 M6007 gt xX 07842D 8 16 S M6008 gt x 07842E 8 16 S 39 6031 gt 507 420 8 16 5 6032 gt 07 42 8 16 5 10 6009 gt 5078431 8 16 5 6010 gt 5078432 8 16 5 42 M6033 gt X 07A431 8 16 S 6034 gt 5074432 8 16 5 11 6011 gt 5078435 8 16 5 6012 gt 5078436 8 16 5 43 M6035 gt X 07A435 8 16 S 6036 gt 5074436 8 16 5 18 6013 gt 5079421 8 16 5 6014 gt 5079422 8 16 5 50
50. I O Node with Address Offsets 24 bit Register 16 bit Register 1 16 bit Register 2 16 bit Register 3 23 5 7 Example mapping the 65 data with address offsets into PMAC2 Style MACRO IC 0 node 2 requires adding the base address to the offset 800000 offset of the desired data register Knowing that the general purpose inputs and outputs are in the 24 bit data register the analog ADC inputs and DAC outputs in the 1 and 2 16 bit data registers and the general purpose relays in the 3 16 bit data register bits 27 and 28 Inputs gt U 10 800120 8 24 GP Inputs Outputs gt U 10 800120 8 24 GP Outputs ADC1 gt S 10 800124 16 16 Analog ADC 1 Input ADC2 gt S 10 800128 16 16 Analog ADC 2 Input DAC1 gt S 10 800124 16 16 Analog DAC 1 Output DAC2 gt S 10 800128 16 16 Analog DAC 2 Output GPRelayl gt U 10 80012C 27 1 GP Relay Output 1 GPRelay2 gt U 10 80012C 28 1 GP Relay Output 2 gt general purpose inputs can be bitwise mapping directly and read at will gt The general purpose outputs can be mapped directly and written to However they do require an image word to allow writing to multiple bits simultaneously and reporting the state of each output gt The analog ADC inputs can be read at will they do not require further processing gt The analog DAC outputs require
51. I communication e g 5 1 MS2 1992 6527 Must be equal to the value of the ring controller s 16800 52 1997 0 Must be equal to the value of the ring controller s 16801 52 1995 54080 Typical setting for MACRO slave device 52 1996 50 8004 Nodes enabling e g I O node 2 MS2 18 181 Ring check period see equation below MS2 19 28 Maximum ring error count see equation below 52 110 153 Minimum synch packet count see equation below These settings must be saved e g MSSave2 or MSSAV2 on the ACC 65M and followed by a reset e g MS 2 to take effect Please wait while PMAC writes to the EEPROM mssav2 command completed successfully If the clock settings are not at default 18 I9 and can be calculated using the following equations Assuming a typical ring check period RingCheckPeriod of 20 milliseconds and a fatal packet error MaxErrorPercent of 15 percent MS2 I8 INT Ringcheck Period 117964 8 x MS2 1997 1 2x MS2 1992 4 3 2 19 MS2 18x MaxErrorPe rcent 100 52 110 MS2 I8 MS2 19 These must be computed explicitly ahead of time expressions cannot be written directly into 5 variables Using the ACC 65M with Turbo PMAC2 46 Accessory 65M Step 4 Data Registers A single I O node is sufficient for transferring the data to from the ACC 65M This is handled automatically in the firmware The u
52. MACRO is CATS verified straight through 8 conductor The input IN connector of the ACC 65M is inserted into the MACRO output OUT connector of the previous device on the MACRO ring The output OUT connector of the ACC 65M is inserted into the input IN MACRO connector of the next device on the MACRO ring Connector Pinouts and Wiring 68 Accessory 65M Universal Serial Bus USB The USB port is used to change reload the operational firmware of the ACC Pin Symbol 65M It utilizes a USB A B type cable to make the connection between the ACC 65M and a host PC vee 2 This connection appears in the hardware device manager of the PC under the 3 DATA serial communication port s Typically the firmware is downloaded using 4 GND 5 6 Delta Tau s MACRO firmware utility SHELL SHIELD SHELL SHIELD The serial port settings should be as follows Baud Rate 9600 if jumper E3 is installed 38400 if jumper E3 is not installed default Data Bits 8 Parity None Stop Bits 1 Flow Control Xon Xoff PeWin32PRO2 software must be installed for the PC to recognize the serial communication connection Note Connector Pinouts and Wiring 69 Accessory 65M TROUBLESHOOTING Initializing the ACC 65M Clearing Faults Typically peripherals such as the ACC 65M are powered up first before the ring controller in a MACRO ring configuration So that when the rin
53. d Response Using the ACC 65M with Turbo 2 Accessory 65M Now you are talking directly to the ACC 65M You should be able to issue commands such as type TYP version VER etc The goal of MACRO ASCII communication is to enable a selected I O node to allow Master Slave communication from the master which then can be used to set up the rest of the necessary parameters on the ACC 65M Choosing I O node 2 as an example enabling it is done through 1996 0FA000 One node is sufficient for transferring all the data available on the E 65 Note Press CTRL T T to exit MACRO ASCII communication Please wait while PMAC terminates MACRO Ring ASCII communication MACRO Ring ASCII communication terminated The yellow notification should now disappear And communication is re established with the ring controller Note Using the ACC 65M with Turbo PMAC2 45 Accessory 65M Step 3 Finishing up the ACC 65M Setup Having enabled a selected I O node on ACC 65M the corresponding I O node should be enabled on the ring controller side For example at MACRO IC 0 node 2 16841 168411 4 Master Slave communication should be now available over I O node 2 And the following parameters can be downloaded from the editor window 52 111 1 Station number assignment user configurable for future MACRO ASCI
54. e part number configurations are Options Part Number Fiber optic connectors 4 3740 00 A000 00000 RJ 45 connectors 4 3740 00 000 00000 Fiber optic connectors 2 x 16 bit bipolar analog inputs 10 VDC 2 x 12 bit bipolar DAC analog outputs 10 VDC 2 x general purpose relay contacts 4 3740 00 A002 00000 RJ 45 connectors 2 x 16 bit bipolar analog inputs 10 VDC 2 x 12 bit bipolar DAC analog outputs 10 VDC 2 x general purpose relay contacts 4 3740 00 002 00000 Revisions 101 and older of the 65 could only support the 12 E bit ADC inputs which allowed the user to have 2047 counts of resolution The 16 bit ADCs provide 32767 counts Note Specifications Accessory 65M Environmental Specifications Description Specification Notes Operating Temperature 0 C to 50 Storage Temperature 25 C to 70 C Humidity 596 to 9596 Non Condensing Relative Humidity Electrical Specifications Logic Power Required Voltage 24 Vpc Current Requirements 1 5A Permitted Time at Peak Current 2 seconds Digital Inputs Voltage Range 12 24 Vpc Continuous Current Rating Amp per channel Peak Current Rating 2 Amps per channel Permitted Time at Peak Current 2 seconds Direction Sourcing or Sinking see wiring samples Digi
55. e phase clock to be the same across the ring Enabled a selected I O node on the 65 Enabled the corresponding I O node on the ring controller side Saved and reset both the ACC 65M and the ring controller The ACC 65M data should now be available to access from the ring controller side The ACC 65M firmware places the data automatically in the following data registers of a selected I O node Digital Analog I O GP Relays 16 bit Register 3 T l 4 a m 3 16 bit Register 1 16 bit Register 2 Style Node 24 bit Register 23 15 7 And each I O node possesses data structure elements for inputs and outputs separately for either bank Bank B Bank A Data Inputs Outputs Inputs Outputs Register Gate3 i MacroInB j 0 Gate3 i MacroOutB j 0 Gate3 MacroInA j 0 Gate3 i MacroOutA j 0 24 bit Gate3 i MacroInB j 1 Gate3 i MacroOutB j 1 7 MacroInA j 1 Gate3 MacroOutA j 1 1 16 bit Gate3 i MacroInB j 2 Gate3 i MacroOutB j 2 Gate3 i MacroInA j 2 Gate3 i MacroOutA j 2 274 16 bit Gate3 i MacroInB j 3 Gate3 i MacroOutB j 3 7 MacroInA j 3 Gate3 i MacroOutA j 3 3 16 bit Where gt iis the PMAC3 Style MACRO IC index gt jis the I O node number Bitwise mapping and signed assignments into the PMAC3 Style
56. e ring controller side at the specified I O node with the data residing is in the following fields 2 Style I O Node Digital I O gt 24 bit Register 16 bit Register 1 Analog 1 0 16 bit Register 2 GP Relays 16 bit Register 3 23 15 7 0 The PMAC2 Style MACRO structure elements for these registers Structure Element Data Register Gate2 i Macro j 0 24 bit Gate2 i Macro j 0 16 bit Gate2 i Macro j 0 16 bit Gate2 i Macro j 0 16 bit Where gt iisthe PMAC2 Style MACRO IC index gt jis the node number MACRO structure elements require Power PMAC firmware version Bitwise mapping and signed assignments into the PMAC2 Style 7 1 5 8 305 or newer Note AN Power PMAC firmware versions older than 1 5 8 305 must use explicit address offsets found in the memory map appendix section Note Using the ACC 65M with Power 2 31 Accessory 65M Below are example tables showing I O Node numbers of the first 4 PMAC2 Style MACRO ICs Gate2 0 65 Nodes 6 7 10 11 Ring Controller I O Node 3 6 7 10 11 Gate2 1 65 Nodes 2 3 6 7 11 12 Ring Controller Node 7 18 19 22 23 26 27 Gate2 2 65 Nodes 2 3 6 7 10 11 Ring Controller I O Node 34
57. eak B Ring Break MACRO cables on are unplugged or broken MACRO cables not connected in the correct order In Out Indicates that the software settings do not match physical hardware C Configuration e Enabled node on the ACC 65M not enabled on the ring controller side Check node settings on both ACC 65M and ring controller Indicates a packet loss or other MACRO data loss D Data Error Verify the setting of 180 181 and 182 on the ring controller Verify the setting of MS 18 I9 and on the ACC 65M E N A 3 Indicates that a momentary MACRO ring fault has occurred F Ring Fault Verify the setting of 180 181 182 on the ring controller Troubleshooting 71 Accessory 65M LED Status Input and Output LED Indicators Each of the 24 input and 24 output lines has an associated LED on the front panel of the unit that displays its current state either active a Green or Red state or inactive darkened no light Status LED 24V when lit this LED indicates that the 24V power is applied Fuse when lit this LED indicates that the internal fuse protecting the external 24V is properly functional PWR when lit this LED indicates that the 24V logic power is applied WD whenlit this LED indicates that the watchdog safety circuit is activated This indicates a failure condition and interrupts MACRO communication Also turns off all outputs Digital and Analog It occurs if
58. ertaining Ring Controller Hardware Reference User manual or in the Power SRM Software Reference Manual The Power PMAC can interface with up to 32 PMAC2 Style MACRO ICs or up to 8 fully populated ACC 5Es Note These settings require a SAVE followed by a reset to take effect Note Ststus Online 192 168 0 200 5SH Motor Status Coordinate Status Global Status MACRO Status ECAT Status Ring No 0 Station 0 Once implemented these settings should ensure that the Power PMAC is now a MACRO ring Controller And the MACRO mue Status window the Power PMAC IDE software should look sas Emo like ErrorsFault AsciiRespRdy SynchFault False 0 BrkMsgSent False 2 RingError MacroServoSync Fase TestEnabled Tue PwrOnErrCntr 0 SynchMaster Tue 00 RingBrkStationNum None Master False 2 Using the 65 with Power 2 26 Accessory 65M Step 2 MACRO ASCII Communication There are two possible MACRO communication methods between the ring controller and the ACC 65M MACRO ASCII communication Direct communication to the 65 it is useful for initial setup troubleshooting and allows to eventually establish Master Slave MS communication Master Slave MS communication Establishing MS commands through an I O node is ultimately what we want Make sure that the watch window does not contain
59. g controller comes up it clears any MACRO faults and initializes the ring This would be equivalent to a ring controller reset If the ACC 65M is powered up at the same time or after the ring controller has been turned on then it is advised to implement a reset mechanism in software flag or hardware e g push button to clear any MACRO ring faults and initialize the ring Essentially the ring controller must issue gt MSCRLF any slave enabled node CLRF The simplest implementation can be done in the startup PLC which is enabled or released using a conditional flag when all the hardware is powered up and ready For example P8000 0 Flag to clear MACRO ring faults Open plc 1 Clear If P8000 1 Clear faults 15111 250 8388608 10 While 15111 gt 0 EndW 250 msec delay CMD MSCLRF15 Broadcast a clear faults on all enabled nodes of MACRO IC 0 15111 50 8388608 110 While 15111 gt 0 EndW 50 msec delay CMD CLRF Clear ring controller MACRO ring faults 15111 50 8388608 110 While 15111 gt 0 EndW 50 msec delay P8000 0 Reset flag EndIF Close Troubleshooting 70 Accessory 65M Error Codes 7 Segment LED This 7 Segment LED Indicator reports the error and MACRO status of the ACC 65M Code Fault Notes 0 Ring Active No errors Normal operation mode 1 9 N A A 24V Input Check the 24V logic power input Indicates a MACRO ring br
60. he example above and finding the corresponding register or data element structure listed in the tables below for reading writing to the data A MACRO IC consists of a number of auxiliary servo and I O nodes Auxiliary nodes are Master Control registers and for internal firmware use gt Servo nodes carry information such as feedback commands and flags for motor control gt I O nodes are by default unoccupied and are configurable for transferring miscellaneous data Each PMAC3 style MACRO IC consists of 32 nodes 4 auxiliary 16 servo and 12 I O nodes 1 0 Nodes Nodes 15 14 14 RE I LI Auxiliary Auxiliary Nodes Servo Nodes Nodes Servo Nodes te re Bank B Bank A Each node consists of 1 x 24 bit 3 x 16 bit data registers residing in the following fields PMACS Style Node 24 bit Register 4 4 1 16 bit Register 1 16 bit Register 2 16 bit Register 3 M 4 4 4 4 1 21 23 The Power can interface with up to 16 Style MACRO ICs ICs present are reported by the variable Macro IC3s Note Using the ACC 65M with Power PMAC3 16 Accessory 65M Step 5 Using the ACC 65M Data Having configured the following gt Set up the MACRO ring controller v v Set up th
61. igned DACs simply replace the S in the prefix of the assignment with a U Note And the mirror PLC which should be executing constantly N2Firstl6 Gate 2 Macro 2 1 Node 2 17 16 bit data register PTR N2Second16 gt Gate 2 Macro 2 2 Node 2 279 16 bit data register OPEN PLC 1 N2Firstl16 1 256 Update data register upper 16 N2Second16 DAC2 256 Update data register upper 16 CLOSE Using the ACC 65M with Power PMAC2 36 Accessory 65M Testing the Analog Inputs Applying a voltage into the physical input pins and reading the above referenced pointers for unsigned unipolar or signed bipolar data the user should see the following With the 16 bit ADCs Single Ended Signal VDC Differential Signal VDC Software Counts 10 5 32768 Bipolar 0 0 0 Unipolar 10 5 32768 With the 12 bit ADCs Single Ended Signal VDC Differential Signal VDC Software Counts 10 5 2048 Bipolar 0 0 Unipolar 10 5 2048 Testing the Analog Outputs These are 10V outputs where 10 volts corresponds to the value of MS2 1992 Remember that this is dictated by the ring phase clock do not attempt to change it in this section Point Single Ended Differential TES VDC VDC For example with the default clock setting e g 6527 10 20 52 1992 6527 and by writing to the analog output data
62. in Molex Ey be 12 128 AN Bitwise and signed mapping into the PMAC2 Style MACRO structure elements require Power PMAC firmware version 1 5 8 305 or newer Note Using the ACC 65M with Power 2 3 Accessory 65M Analog Output DACs The analog output DACS can be written to using the structure element s full word Example PMAC2 MACRO IC 0 Node 2 DAC 1 PTR paci 6ate2 0 Macro 2 1 Structure Address Element Offset However with the PMAC2 Style MACRO IC the DAC outputs require an Sys Udata 4 U USER 16 ens word to report the value of each output and allow byte wise mapping Sys Udata 8 U USER 32 or proper scaling This can be done in a simple PLC and using of the unsigned user Sys Udata 12 U USER 48 shared memory data elements Sys Udata i The table to the right shows 4 of the possible 65K registers available eye large number of self addressed default Sys pushm pointers in E Power PMAC use Sys Udata 0 therefore it is highly advised NOT to use it as a general purpose user shared memory Note Example Using Sys Udata 8 for both DACs 1 and 2 DAC1 5S USER 32 0 16 DAC 1 pointing to signed user shared memory DAC2 gt S USER 32 8 16 DAC 2 pointing to signed user shared memory Typically the ACC 65M is configured by the factory for signed DAC outputs For uns
63. ing the corresponding register or data element structure listed in the tables below for reading writing to the data A MACRO IC consists of a number of auxiliary servo and I O nodes Auxiliary nodes are Master Control registers and for internal firmware use gt Servo nodes carry information such as feedback commands and flags for motor control gt I O nodes are by default unoccupied and are configurable for transferring miscellaneous data Each PMAC2 Style MACRO IC consists of 16 nodes 2 auxiliary 8 servo and 6 I O nodes Nodes Auxiliary Nodes Servo Nodes Each I O node register consists of one 24 bit and three 16 bit data registers placed in the following fields PMAC2 Style Node 24 bit Register 16 bit Register 1 16 bit Register 2 16 bit Register 3 N 15 Power CPU interface with up to 32 2 Style MACRO ICs ICs present are reported by the variable Macro ICs Note Using the ACC 65M with Power PMAC2 30 Accessory 65M Step 5 Using the ACC 65M Data Having configured the following gt Setup the MACRO ring controller Setup the phase clock to be the same across the ring gt Enabled a selected I O node on the ACC 65M gt Enabled the corresponding I O node on the ring controller side gt Saved and reset both the ACC 65M and the ring controller The ACC 65M data should now be available to access from th
64. is not to exceed 600 mA 24VDC Caution The return lines pins 5 10 15 20 25 and 30 are all internally connected The diagram shows them in sets of four for wiring convenience RET 9 12 RET 21 24 12 24 Output 24 11 23 Output 23 10 22 9 21 RET 5 8 RET 17 20 8 20 7 19 6 18 5 17 RET 1 4 RET 13 16 4 16 C Output H8 TEENS 4 Output 7 Output 6 5 Output 5 4 s Output 4 Output 3 3 15 Q Output 2 2 14 Output 1 1 13 Outputs 1 12 Outputs 13 24 Connector and Wiring 63 Accessory 65M Analog Connector This optional connector provides connections to the analog outputs and inputs as well as the general purpose relays Connector D sub DA 15F Q 5 5 4 3 2 Mating D sub DA 15M 15 13 12 41 9 s o o Cnr Connector Pinouts and Wiring 64 Accessory 65M Wiring the Analog ADC Inputs Differential Analog Input Signals Single Ended Analog Input Signals ADC 1 ADC 1 ADC 2 ADC 2 2 For single ended connections tie the negative ADC pin to ground Note a The analog inputs use the ADS8321 Converter device gt Note Full 16 bit resolution is available for bipolar signals only Half of the EG range of the full resolution i
65. log inputs into from the 1 and 2 16 bit registers of the chosen I O node These are read write registers Newer revision of the ACC 65M 3 pin edge logic connector ADC 1 ADC 2 ADC 1 ADC 2 2 5001 gt 5078421 8 16 5 5002 gt 5078422 8 16 5 34 M5025 gt x 07A421 8 16 S M5026 gt x 07A422 8 16 S 3 5003 gt 5078425 8 16 8 5004 gt 5078426 8 16 5 35 M5027 gt x 07A425 8 16 S 5028 gt 5074426 8 16 5 6 5005 gt 5078429 8 16 5 5006 gt 507842 8 16 5 38 M5029 gt x 07A429 8 16 S 5030 gt 507 42 8 16 5 7 M5007 gt X 07842D 8 16 S 5008 gt 507842 8 16 5 39 M5031 2X 07A42D 8 16 8 5032 gt 507 42 8 16 5 10 5009 gt 5078431 8 16 5 5010 gt 5078432 8 16 5 42 M5033 gt x 07A431 8 16 S 5034 gt 5074432 8 16 5 11 5011 gt 5078435 8 16 5 5012 gt 5078436 8 16 5 43 5035 gt 5074435 8 16 5 5036 gt 5074436 8 16 5 18 5013 gt 5079421 8 16 5 M5014 gt x 079422 8 16 S 50 5037 gt 507 421 8 16 5 5038 gt 507 422 8 16 5 19 5015 gt 5079425 8 16 5 5016 gt 5079426 8 16 5 51 M5039 gt x 07B425 8 16 S 5040 gt 507 426 8 16 5 22 5017 gt
66. nd OHIDHIS 33 Analog Inputs ADCs and Outputs CGs 35 Using the ADCs for Servo Feedback a a 38 General Purpose Relays petri Rapt nedara EER A E REVELE anita nea 39 USING THE 65 WITH 2 0 0 41 Step 1 Preparing Ring 42 Step 2 MACRO ASCII Communication n 44 Step 3 Finishing up the ACC 65M 46 Step 4 VO D ta dt tado d place ae Na ee ea 47 Nodes and Addressing mE 47 Turbo Ring Controller I O Node REGS CTS 48 Usima he AGC 65M eeu eina str dan de ER 49 Digital Inputs and E 49 Analog Tnp ts ADCS NT 52 Introduction 4 Accessory 65M Using the ADCS for Servo Feedback is de 54 MERE RERBA 55 General Purpose Relay 57 CONNECTOR PINOUTS AND WIRING FERME M MH 59 24 V DC Input er 59 M 60 Wiring the digital 61 ac 62 Wiring th digital RP
67. nd the GND side to the corresponding return line For sinking connect the GND side of the power supply to the individual input switches and the 24V side to the corresponding return line Sourcing Inputs Sinking Inputs 12 24 VDC 12 24 VDC Power Supply Power Supply 24 VDC 24 VDC 9 12 21 24 E 12 24 11 23 L2 11 23 dl 10 22 10 22 9 21 5 9 21 st 5 8 17 20 1 19 9 12 21 24 Inputs 1 12 Inputs 13 24 Inputs 1 12 Inputs 13 24 Connector Pinouts and Wiring 61 Accessory 65M Digital Outputs Connector Phoenix Contact MSTB 2 5 5 08 15 Positions female Mating Phoenix Contact LR13631 male o 05 OUT 06 U U U U RET U U 10 ll 12 U 13 U 14 U 15 16 U 17 U 18 U 19 U 20 RET 21 U OUT 10 11 RET RET OUT 18 OUT 19 OUT 20 RET OUT 21 OUT 22 OUT 23 OUT 24 RET 1 Function OUTPUT 3 OUTPUT 7 OUTPUT 11 OUTPUT 15 OUTPUT 19 OUTPUT 23 Note All the outputs return lines are internally tied together They are labeled for each set of four outputs for wiring convenience Connector Pinouts and Wiring 62 Accessory 65M Wiring the digital outputs The outputs are always sourcing in the ACC 65M The maximum current draw out of each output load
68. ngs require a SAVE followed by a reset to take effect Note Status Online 192 168 0 200 SSH Motor Status Coordinate Status Global Status MACRO Status ECAT Status Ring No 0 Station 0 2 Once implemented these settings should ensure that the Description Status _ Status Power PMAC is now a MACRO ring Controller And the CESS Ascicom Fase MACRO Status window in the Power PMAC IDE 59e supe N BrkReceivd False 0 AsciiCmdRdy Fase 0 software should look like ErrorsFault SynchFault False BrkMsgSent False 2 RingError False MacroServoSync False TestEnabled Tue 00 PwrOnErrCntr 0 SynchMaster Tue RingBrkStationNum None Master Fase Using the ACC 65M with Power 1 Accessory 65M Using the ACC 65M with Power 12 Accessory 65M Step 2 MACRO ASCII Communication There are two possible MACRO communication methods between the ring controller and the ACC 65M MACRO ASCII communication Direct communication to the 65 it is useful for initial setup troubleshooting and allows to eventually establish Master Slave MS communication Master Slave MS communication Establishing MS commands through an I O node is ultimately what we want Make sure that the watch window does not contain E commandis prior to establishing Master Slave communication
69. point to it Example Motor 1 pMasterEnc EncTable 1 a Or it can be accessed manually using a pointer Note that you would need to multiply by the scale factor or divide by 2 16 in this example for proper scaling Example PTR ECTIResult EncTable 1 PrevEnc Using the ACC 65M with Power PMAC2 38 Accessory 65M General Purpose Relays The general purpose relays 1 and 2 are transferred respectively into bits 19 and 20 of the 3 16 bit data register of the I O node The PMAC2 Style MACRO IC structure element for this register is Structure Element Data Register Gate2 i Macro j 3 16 bit middle Where gt iisthe PMAC2 Style MACRO IC index gt jis the node number With the PMAC2 Style MACRO IC the GP relay outputs require an image Structure Address word to report the value of each output and allow byte wise mapping Element Offset This can be done in a simple PLC and using one of the unsigned user Sys Udata 4 U USER 16 shared memory data elements Sys Udata i The table to the right shows 4 of the possible 65K registers available Sys Udata 8 U USER 32 Sys Udata 12 U USER 48 Sys Udata 16 U USER 64 Example Using Sys Udata 4 bits 27 and 28 respectively as mirror bits for GP Relays 1 and 2 1 1 gt 0 05 16 27 1 GP Relay 1 mirror bit GPRelay2 gt U USER 16 28 1 GP Relay 2 mirror bit And the mirror PL
70. polar Bipolar 10 5 2048 0 0 0 10 3 2048 Using the ACC 65M with Turbo PMAC2 53 Accessory 65M Using the ADCs for Servo Feedback Using an analog ADC input for servo requires bringing it into the encoder conversion table ECT Using the automatic ECT utility in the PeWin32Pro2 software Type Parallel position from Y X Source Address I O node data register i e 78421 Width in bits 16 16 bit ADC Offset of LSB 32 because it is an X register Normal shift v v v v v Turbo Encoder Conversion Table Device 0 UMAC TURBO VL947 11 01 20 x Select a table entry to vowed guum End of Table Download Entry Entry 1 i First Entry of Table Done Ent y 3501 Processed Data x 3502 Address Address View All Entries of T able Viewing Conversion Parallel pos from Y X word with no filtering bd Source Address 378421 gt Width in Bits 16 Offset Location of LSB at Source Address 0 Based Index 32 Conversion Shifting of Parallel Data Normal shift 5 bits to the left No Shifting Alternately using the equivalent 18000 parameters 18000 18001 5678421 853501 510020 853502 The ADC data is now processed in the encoder conversion table A motor can use it for position velocity feedback Example 1 03 3502 Ixx04 3502 Or as a master position
71. put12 M7036 Output12 gt X S10FF 11 define Output13 M7037 Output13 gt X S10FF 12 define Outputl4 M7038 Output14 gt X S10FF 13 define Output15 M7039 Output15 gt X S10FF 14 define Outputl6 M7040 Outputl6 2X S 10FF 15 define Output17 M7041 Output17 gt X S10FF 16 define Output18 M7042 Output18 gt X S10FF 17 define Output19 M7043 Output19 gt X S10FF 18 define Output20 M7044 Output20 gt X S10FF 19 define Output21 M7045 Output21 gt X S10FF 20 define Output22 M7046 Output22 gt X S10FF 21 define Output23 M7047 Output23 gt X S10FF 22 define Output24 M7048 Output24 gt X S10FF 23 The following PLC will then copy the outputs from the open memory register into the 24 bit I O node register A simple latch is used to prevent the PLC from overwhelming the I O register define N2Twenty4 M6977 Node 2 24 bit data register define OutMirror M7049 Outputs Mirror register N2Twenty4 gt X 078420 0 24 Node 2 24 bit data register OutMirror gt X S10FF 0 24 Open memory register user configurable OutMirror 0 Initialize save to zero or desired state Open plc 1 clear N2Twenty4 OutMirror Update data register Close With this PLC executing constantly the user now writes to M4051 through M4074 to toggle the digital outputs on the ACC 65M Using the ACC 65M with Turbo PMAC2 Accessory 65M Analog Inputs ADCS The ACC 65M firmware transfers automatically the ana
72. s to the offset 900000 offset of the desired data register Knowing that the general purpose inputs and outputs are in the 24 bit data register the analog ADC inputs and DAC outputs in the 1 and 274 16 bit data registers and the general purpose relays the 3 16 bit data register bits 27 and 28 PT PT j 3 AX 3 F3 3 ps R 2 is Inputs gt U 10 900420 8 24 Outputs gt U 10 900520 8 24 ADC1 gt S 10 900424 16 16 77 2 gt 5 10 5900428 16 16 77 DAC1 gt S 10 900524 16 16 DAC2 gt S 10 900528 16 16 pil GPRelayl gt U 10 90052C 27 1 GPRelay2 gt U 10 90052C 28 1 GP Inputs GP Outputs Analog ADC Analog ADC Analog DAC Analog DAC 1 2 1 2 Input Input Output Output GP Relay Output 1 GP Relay Output 2 With the PMAC3 Style MACRO IC all the data can be read and written to at will without further processing No image word s shifting or scaling required Note Explicit address offsets mapping 15 useful for older Power PMAC firmware versions Note Power PMAC users with firmware versions 1 5 8 305 or newer are highly encouraged to use the structure element addressing aforementioned in this manual Appendix A Memory Map 74 Accessory 65M 2 Style ASIC The Power can interface with up to 32 PMAC2 Style ASICs
73. s used for unipolar 0 5V or 0 10V signals 2 Note Connector Pinouts and Wiring 65 Accessory 65M Wiring the Analog DAC Outputs Differential DAC Output Signals Single Ended DAC Output Signal Wiring the General Purpose Relays The general purpose relays provide a signal which can be either e High true using the normally open contact pins 14 and 8 respectively e Low true using the normally closed contact pin 6 and 15 respectively Also they can be either sourcing or sinking depending on the wiring scheme common line The following table summarizes the relay functions That is the relationship between the common line and the normally open normally closed lines GP Relay 1 Connection between Connection between pins 13 COM and 14 NO pins 413 COM and 6 NC Software bit 0 Open Closed Software bit 1 Closed Open GP Relay 2 Connection between Connection between pins 7 COM and 8 NO pins 7 COM and 15 NC Software bit 0 Open Closed Software bit 1 Closed Open Below are wiring samples using general purpose relay 1 Connector Pinouts and Wiring 66 Accessory 65M High True Output to Logic Device 24V G 12 24VDC Input 9 Logic Device GND p gt Ww any a 12 24 VDC
74. ser s responsibility is choosing an available I O node enabling it per the example above and finding the corresponding register listed in the table below for picking up the data Nodes and Addressing A Turbo PMAC as a MACRO ring controller can be populated with up to 4 MACRO ICs This is reported by parameter 14902 0 NoMACRO ICs cannot be a ring controller 1 MACROICO 3 MACRO ICs 0 and 1 7 MACRO ICs 0 1 and 2 F MACRO ICs 0 1 2 and 3 Each MACRO IC consists of 16 nodes 2 auxiliary 8 servo and 6 I O nodes Auxiliary nodes are Master Control registers and internal firmware use gt Servo nodes carry information such as feedback commands and flags for motor control gt I O nodes are by default unoccupied and are user configurable for transferring miscellaneous data Nodes Auxiliary Nodes Servo Nodes Each I O node consists of 4 registers one 24 bit and three 16 bit registers for a total of 72 bits of data Using the ACC 65M with Turbo PMAC2 47 Accessory 65M Turbo Ring Controller Node Registers With the ACC 65M we are only interested in the I O data registers The following is a table of all the I O node addresses of the ring controller for each MACRO IC Ring Controller MACRO IC 0 Node Registers ACC 65M Node 2 3 6 7 10 11
75. sult Units set to 1 to shift data 16 bits for proper scaling v v v v v ECT entry number Download Display All ECT Entries Type ECT entry input 3 014 656 1 Single 32 bit register read Stop ECT entry ouput 95 000 Detailed ECT Setup PowerPMAC Structure Encoder Plot ECT entry 1 details Source Address AccSEP3 0 MacroInAD 1 LSB Bit 16 Integrate of Bits Used 16 x Integrator Bias Term Result Units per LSB 1 Limited Quantity Limit Magnitude of Cycles to Limit Alternately using the ECT structure elements 1 Gate3 0 MacroInA 2 1 a 16 16 0 EncTable 1 type EncTable 1 pEnc 1 1 1 1 1 2 EncTable 1 index3 EncTable 1 index4 0 EncTable 1 index5 0 EncTable 1 ScaleFactor 1 EXP2 16 The ADC data is now processed in the encoder conversion table A motor element structure can point to it Example Motor 1 pMasterEnc EncTable 1 a Or it can be accessed manually using a pointer Note that you would need to multiply by the scale factor or divide by 2 16 in this example for proper scaling Example PTR ECTIResult EncTable 1 PrevEnc Using the ACC 65M with Power PMAC3 22 Accessory 65M General Purpose Relay Outputs The ACC 65M firmware transfers automatically the general purpose relay outputs 1 and 2 into bits 27 and 28 respectively of the 3 16 bit PMACS Style 1 0 Node 24 bit Register
76. tal Outputs Voltage Range 0 24 Vpc Continuous Current Rating 600 mA per channel Peak Current Rating 1 2 Amps per channel Permitted Time at Peak Current 2 seconds Analog Inputs Maximum Input Voltage Range 10V Resolution 16 bits 16 bit ADC Chip Burr Brown ADS8361E 12 bit ADC Chip Rev 1 and older Burr Brown ADS7861E Analog Outputs Maximum Output Voltage Range 10V Output Polarity Bipolar Resolution 12 bits DAC Type Filtered PWM Specifications Accessory 65M Physical layout Mounting 6 50 2 00 50 8 100 0 188 165 1 25 4 4277 6 25 158 75 9 l Sinan iniret 0 9 375 9 75 8 625 238 13 247 65 219 075 N 1 25 R 31 75 Specifications Accessory 65M USING THE ACC 65M WITH POWER PMAC3 A Power PMAC3 Style MACRO Ring Controller can be one of the following hardware gt Power UMAC with ACC 5E3 gt Power EtherLite gt Power Brick equipped with MACRO Power Brick AC Power Brick LV Power Brick Controller The first step into setting up the ACC 65M is to make sure that the MACRO cables are plugged in in the correct manner The OUT from the Ring Controller or previous device goes into the IN of the ACC 65M The IN of the ACC 65M goes into the OUT of the ring controller or the next device on the ring For example the illustration below shows how a MACRO ring with three ACC 65Ms is typically
77. tc Using the ACC 65M with Power PMAC3 13 Accessory 65M The goal of MACRO ASCII communication is to enable a selected I O node over which Master Slave communication can then be used to set up the rest of the necessary parameters of the ACC 65M Choosing I O node 2 as an example enabling it is done through 1996 Terminal Online 192 168 0 200 SSH Now communicating to MACRO station 255 8 One node is sufficient for transferring all data available on E ACC 65M Note Issue a MacroStationClose to terminate MACRO ASCII communication Terminal Online 192 168 0 200 SSH 8 Macro Station Closed Using the ACC 65M with Power PHA C3 Accessory 65M Step 3 Finishing up the ACC 65M Setup Having enabled a selected I O node on ACC 65M i e node 2 the corresponding I O node should be enabled on the ring controller side For example at MACRO IC 0 Bank A node 2 Gate3 0 MacroEnableA Gate3 0 MacroEnableA 400 Master Slave communication should be now available over I O node 2 And the following parameters can be downloaded from the project editor For example station number 1 and I O node 2 52 111 1 Station number assignment user configurable for future MACRO ASCII communication e g MACSTA1 52 1992 6527 See euqation below 52 1997 0 See equation below MS2 1995 4080 Typical setting for MACRO slave device MS2 1996 0F800
78. ters of the chosen I O node Ro ACC 65M ADC 1 DAC 1 ACC 65M ADC 2 DAC2 PMACS Style 1 0 Node 24 bit Register 16 bit Register 3 31 23 15 Bank B Bank A Data Inputs Outputs Inputs Outputs Register Gate3 i MacroInB j 1 Gate3 i MacroOutB j 1 Gate3 MacroInA j 1 Gate3 MacroOutA j 1 1 16 bit Gate3 i MacroInB j 2 Gate3 i MacroOutB j 2 Gate3 i MacroInA j 2 Gate3 i MacroOutA j 2 27 16 bit Where i is the card index andj is I O node number Example Analog Input ADCs and output DACs mapping at MACRO IC 0 Bank A I O node 2 ADC1 gt Gate3 0 2 1 16 165 ADC2 gt Gate3 0 2 2 16 165 DAC1 gt Gate3 0 MacroOutA 2 1 16 165 PTR DAC2 gt Gate3 0 MacroOutA 2 2 16 165 BDC 1 ADC 2 DAC 1 DAC 1 N 12 12S Note The ADCs on older revisions of the ACC 65M 2 pin Molex logic connector are 12 bits The suffix of the address mapping should be Typically the ACC 65M is configured by the factory for unsigned data Occasionally it is ordered in the unsigned data format Remove the S in the suffix for proper unsigned addressing Note Using the ACC 65M with Power 20 Accessory 65M Testing the Analog Inputs Applying a voltage into the physical input pins and reading the abo
79. urbo UMAC with ACC 5E gt Turbo 2 Ultralite gt Turbo Brick equipped with MACRO Geo Brick Drive Geo Brick LV Brick Controller Turbo Ring Controller IN OUT The MACRO link LED must be green on all the devices in the MACRO ring for the software setup to work properly Note Using the ACC 65M with Turbo PMAC2 41 Accessory 65M Step 1 Preparing the Ring Controller The Turbo PMAC used to control the MACRO ring must be configured as a ring controller in order to establish communication and transfer data over the MACRO ring Following is a summary list of the relevant parameters which need to be set properly on the Ring Controller side to allow proper functionality of the MACRO ring and configuration of the ACC 65M Parameter MACRO MACRO MACRO MACRO Description Typical Setting IC 0 IC1 2 103 9 Clock Source 6807 16800 16850 16900 16950 MACRO IC Max Phase 6527 16801 16851 16901 16951 MACRO IC Phase Clock Divider 0 16802 16852 16902 16952 MACRO IC Servo Clock Divider 3 18 Real time interrupt 2 I10 Servo Interrupt Time 3713991 I78 Enable MS MSR MSW commands 32 179 Enable MMR MMW commands 32 180 Ring check period 45 181 Maximum ring error count 2 182 Minimum synch packet count 13 16840 16890 16940 16990 MACRO IC Ring configuration Status 4030 10 10 10 16841
80. ve referenced pointers for unsigned unipolar or signed bipolar data the user should see the following With the 16 bit ADCs Single Ended Signal VDC Differential Signal VDC Software Counts Unipolar Bipolar 10 5 32768 0 0 10 5 32768 With the 12 bit ADCs Single Ended Signal VDC Differential Signal VDC Software Counts Unipolar Bipolar 10 5 2048 0 0 0 10 5 2048 Testing the Analog Outputs These are 10V outputs where 10 volts corresponds to the value of MS2 I992 Remember that this is dictated by the ring phase clock do not attempt to change it in this section For example with the default clock setting e g 6527 52 1992 6527 and by writing to the analog output data 3264 register or suggested pointer the user should see Pointer Single Ended Differential VDC VDC 10 20 5 10 0 0 0 3264 5 10 6527 10 20 Using the ACC 65M with Power 21 Accessory 65M Using the ADCs for Servo Feedback Using an analog ADC input for servo requires bringing it into the encoder conversion table ECT Using the automatic ECT utility in the IDE software Type Single 32 bit register read Source Address I O node structure element address i e Gate3 i MacroInA j 1 LSB Bit starting bit of ADC data typically 16 of Bits Used ADC data number of bits 16 or 12 Re
81. vironments that could cause harm to the controller by damaging components or causing electrical shorts When our products are used in an industrial environment install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture abnormal ambient temperatures and conductive materials If Delta Tau Data Systems Inc products are directly exposed to hazardous or conductive materials and or environments we cannot guarantee their operation A Warning identifies hazards that could result in personal injury or death It precedes the discussion of interest WARNING A Caution identifies hazards that could result in equipment damage It precedes the discussion of interest Caution AN A Note identifies information critical to the understanding or use of the equipment It follows the discussion of interest Note Accessory 65M REVISION HISTORY REV DESCRIPTION DATE CHG APPVD 1 Update manual for new release new 24 V connector 2 20 07 C P R N 2 Updated 16 bit ADC option 12 9 09 C P S F 3 Completely revised manual 12 17 12 DCDP R N 4 Reformatted entire manual 11 15 2013 RN RN Added Power PMAC3 PMAC2 Accessory 65M Table of Contents INTRODUCTION 6 SFECIFR ATION uu u 7 Part
82. w a MACRO ring with three ACC 65Ms is typically connected Nx I Ring Controller The MACRO link LED must be green on all the devices in the MACRO ring for the software setup to work properly Note The Power UMAC with 5 is the only configuration in which Power PMAC interfaces to a PMAC2 Style MACRO IC gt Note Using the ACC 65M with Power 2 25 Accessory 65M Step 1 Preparing the Ring Controller The Power PMAC used to control a MACRO ring must be configured as a ring controller in order to establish communication and transfer data over the ring Following is a summary list of the relevant structure elements which need to be set properly on the Ring Controller side to allow proper functionality of the MACRO ring and configuration of the ACC 65M Typical Structure element Setting Sys ClockSource Set by Firmware 32 Gate2 i PwmPeriod 6527 Gate2 i PhaseClockDiv 0 Gate2 i ServoClockDiv 3 Sys ServoPeriod 2 Gate2 i PwmPeriod 3 Gate2 Z PhaseClockDiv 1 Gate2 Z ServoClockDiv 1 117964 8 0 442 Sys PhaseOverServoPeriod 1 Gate2 i ServoClockDiv 1 0 250 Sys RtIntPeriod 0 Macro TestPeriod 20 Macro TestMaxErrors Macro TestPeriod 10 2 Gate2 i MacroMode 4030 Gate2 i MacroEnable iFC000 Where i is the 5 Gate2 i index Detailed description of these parameters can be found in the p

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