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Colorado Dallas DS80C390 User's Manual

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1. 2 2 2 ct cs ca es 2 42 of 58 110199 DS80C390 MULTIPLEXED 9 CYCLE DATA MEMORY CE0 3 WRITE ARST FOURTH CYCLE OF INSTRUCTION MACH ING woes 4 previous gt B Long poa gt Macrae gt m pit acre gt MACHINE gt 4 Movx INSTRUCTION 1 2 c4 c1 ca c3 ca c1 ca cs cs cs c2 cs c4 1 2 e 64 ca c1 c2 cs ca ronr lt nooness Cm THE 1 1 ELECTRICAL CHARACTERISTICS Non multiplexed address data bus 40 MHz VARIABLE CLOCK PARAMETER SYMBOL MIN MAX MIN MAX UNITS Oscillator Freq Ext Osc Haa f o fof 0 f o MHz Ext CrystaD 4f 1 40 PSEN Pulse Width PSEN Low to Valid Instruction In Bf 0 5 tucs 20 D M Input Instruction Hold after PSEN xx 9 characteristics Port 1 Address Port 4 CE to tAVIVI 0 75 tucs 20 Saar Instruction NOTES FOR ELECTRICAL CHARACTERISTICS 1 All parameters apply to both commercial and industrial temperature operation unless otherwise noted 2 The value tycs is a function of the machine cycle clock in terms of the processor s input clock frequency These relationships are described in the Stretch Value Timing table 3 All signals characterized with load capa
2. P3 7 RD External Data Memory Read Strobe 34 27 45 44 42 37 P4 0 P4 7 Port 4 I O Port 4 can function as an 8 bit bi directional I O port and as the source for external address and chip enable signals for program and data memory Port pins are configured as I O or memory signals via the PACNT register The reset condition of Port 1 is all bits at logic 1 via a weak pullup The logic 1 state also serves as an input mode since external circuits writing to the port can overdrive the weak pullup When software clears any port pin to 0 the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs Writing a 1 after the port has been at 0 will activate a strong transition driver followed by a weaker sustaining pullup Once the momentary strong driver turns off the port once again becomes the output and input high state Port Alternate Function P4 0 CEO Program Memory Chip Enable 0 P4 1 CEI Program Memory Chip Enable 1 P4 2 CE2 Program Memory Chip Enable 2 P4 3 Program Memory Chip Enable 3 P4 4 A16 Program Data Memory Address 16 P4 5 A17 Program Data Memory Address 17 P4 6 A18 Program Data Memory Address 18 P4 7 A19 Program Data Memory Address 19 5 0 5 7 Port 5 I O Port 5 can function as 8 bit bi directional I O port the CAN interface or as peripheral enable signals Setting the SPIEC bit will relocate the RXD1 and TXDI functions
3. e c1 ca CLK MOVX READ wien MOVX WRITE DATA PORT 2 40 of 58 110199 DS80C390 MULTIPLEXED CYCLE DATA MEMORY CEO 3 READ LAST CYCLE SECOND THIRD NEXT PREVIOUS PH4 MACHINE 4 MACHINE bPi MACHINE 4 INSTRUCTION 9 INSTRUCTION CYCLE CYCLE CYCLE MACHINE I4 MOVX INSTRUCTION CYCLE c2 c2 c1 LAST CYCLE FIRST THIRD INSTRUCTION PREVIOUS 4 MACHINE bi MACHINE macHne Pi INSTRUCTION CYCLE CYCLE CYCLE CYCLE MOVX INSTRUCTION c1 c1 ca 41 of 58 110199 DS80C390 MULTIPLEXED 9 CYCLE DATA MEMORY PCEO 3 READ OR WRITE 08 pje FK MOVX INSTRUCTION 9 2 ca c1 ca ca 2 ca 2 ea c4 et ca ca 2 MULTIPLEXED 9 CYCLE DATA MEMORY CEO 3 READ LAST NEXT M rc Rp pe GUE M d 4 MOVX INSTRUCTION i
4. SW as MAST Mas bn Menti e Re ou Da 1 4 ___ _ __ ___ ____ _ _ CIRMSI WDCON 1 POR PFI WDF WTRF EWT RWT 0 TE Jie ee ee O SC ERE SIE f PDE SIESTA CRST LAUTOB FRCS SWINT Pa CR INTINT INTING INTINS NNa Eh pee eec dece cite gt ciE 9 of 58 110199 DS80C390 EIE CANBIE COIE EWDI EX5 4 EX2 E8h MXAX lll E da c d 2 MSRDY ETI ERI CIM4C NTRQ EXTRQ MTRQ DTUP ECh EDh EEh Eg Ls Er F3h I TUP F4h F5h F h CANBIP CUP P F8h MSRDY INTRQ CIMI2C MSRDY ETI ERI INTRQ EXTRQ MTRQ DTUP FCh FDh ETI INTRQ DTUP FEh 11 MSRDY ETI INTRQ Shaded bits are Timed Access protected ON CHIP ARITHMETIC ACCELERATOR An on chip math accelerator allows the microcontroller to perform 32 and 16 bit multiplication division shifting and normalization using dedicated hardware Math operations are performed by sequentially loading three special registers The mathematical operation is determined by the sequence in which three dedicated SFRs MA MB and MC are a
5. MOVX INSTRUCTION c2 48 of 58 110199 DS80C390 NON MULTIPLEXED 2 CYCLE DATA MEMORY 3 WRITE LAST CYCLE FIRST SECOND OF PREVIOUS 44 MACHINE JM MACHINE gt 4 INSTRUCTION CYCLE MACHINE CYCLE CYCLE MOVX INSTRUCTION cr ca ca c1 ca i MOVX INSTR ADDRESS NEXT INSTR ADDR MOVX DATA ADDR PORT 2 T t PORT 4 ER it porr aaooress OK XC meno X meno MEAS _ Pori K NON MULTIPLEXED 3 CYCLE DATA MEMORY PCE0 3 READ OR WRITE bid MACHINE MACHINE Did MACHINE piq NSTRUCTION INSTRUCTION CYCLE CYCLE CYCLE CYCLE 49 of 58 110199 DS80C390 NON MULTIPLEXED CYCLE DATA MEMORY CE0 3 READ NEXT LAST CYCLE FIRST SECOND THIRD INSTRUCTION or PREVIOUS P 4 MACHINE PHE MACHINE gt 6 MACHINE PH MACHINE gt INSTRUCTION CYCLE CYCLE CYCLE CYCLE K MOVX INSTRUCTION _ _ _ c2 c1 ca NON MULTIPLEXED 3 CYCLE DATA MEMORY CE0 3 WRITE NEXT LAST CYCLE FIRST SECOND THIRD INSTRUCTION
6. e c2 TLLOV2 e tius F o TRLAZ Tim 2047 eee Multiplexed Address Data 0 3 MOVX Write Operation 9 cycle shown for reference instruction Fetch Mei Second Machine Third Machine Cycle Fourth Machine Cycle 4 eo Ninth Machine Cycle es et et es es et 110199 37 of 58 DS80C390 Multiplexed Address Data PCEO 3 MOVX Read Operation 9 cycle shown for reference instruction Fetch Second Machine PPf Third Machine Cycle Fourth Machine Cycle 2 Macnee pid Ninth Machine Cycle 0 c1 es et c2 ei e c1 es ca Multiplexed Address Data PCEO 3 MOVX Write Operation 9 cycle shown for reference Instruction Fetch Second Machine 0 gt Third Machine Cycle Fourth Machine Cycle aoe Ninth Machine gt c4 2 c1 ca c1
7. et 110199 38 of 58 DS80C390 MULTIPLEXED 2 CYCLE DATA MEMORY PCEO 3 READ OR WRITE LAST CYCLE FIRST SECOND I4 OF PREVIOUS P 4 MACHINE JMj MACHINE gt 4 INSTRUCTION INSTRUCTION CYCLE CYCLE MACHINE CYCLE 4 INSTRUCTION cr ca MULTIPLEXED 2 CYCLE DATA MEMORY CE0 3 READ LAST CYCLE FIRST SECOND NEXT 4 OF PREVIOUS P 4 MACHINE gt lt 4 MACHINE 0 6 INSTRUCTION INSTRUCTION CYCLE CYCLE MACHINE CYCLE MOVX INSTRUCTION ce ca ca 39 of 58 110199 DS80C390 MULTIPLEXED 2 CYCLE DATA MEMORY CE0 3 WRITE LAST CYCLE SECOND M OF PREVIOUS Pid MACHINE Pi MACHINE INSTRUCTION P4 INSTRUCTION CYCLE CYCL MACHINE CYCLE fe C MOVX INSTRUCTION MULTIPLEXED 3 CYCLE DATA MEMORY PCEO 3 READ WRITE NEXT LAST CYCLE FIRST SECOND THIRD INSTRUCTION OF PREVIOUS P4 MACHINE PI 4 MACHINE Pi MACHINE MACHINE gt j INSTRUCTION CYCLE CYCLE CYCLE CYCLE K4 INSTRUCTION c1 c1 et
8. Poll the CKRDY bit EXIF 4 waiting until it is set to 1 This will take approximately 65536 cycles of the external crystal or clock source Set CD1 to 00 The frequency multiplier will be engaged on the machine cycle following the write to these bits Uo e OSCILLATOR FAIL DETECT The microprocessor contains a safety mechanism called an on chip Oscillator Fail Detect circuit When enabled this circuit causes the processor to be held in reset if the oscillator frequency falls below TBD kHz In operation this circuit complements the Watchdog timer Normally the watchdog timer is initialized so that it will time out and will cause a processor reset in the event that the processor loses control In the event of a crystal or external oscillator failure however the watchdog timer will not function and there is the potential for the processor to fail in an uncontrolled state The use of the oscillator fail detect circuit forces the processor to a known state 1 e reset even if the oscillator stops The oscillator fail detect circuitry is enabled when software sets the enable bit OFDE PCON 4 to a 1 Please note that software must use a Timed Access procedure described later to write this bit The OFDF PCON 5 bit will also be set to a 1 when the circuitry detects an oscillator failure and the processor is forced into a reset state This bit can only be cleared to a 0 by a power fail reset or by software The oscillator fail
9. 4Bh 9 5 EX3 EIE 1 PX3 EIP 1 INT4 External Interrupt 4 IE4 EXIF 6 EX4 EIE 2 PX4 EIP 2 5 External Interrupt 5 5Bh 1 TES EXIF 7 5 EIE 3 PX5 EIP 3 1 CANO Interrupt COIE EIE 6 COIP 6 CANI Interrupt EIE 5 5 WDTI Watchdog Timer 63h 14 WDIF WDCON 3 EWDI EIE 4 PWDI 4 CANO 1 Bus Activity CANBIE EIE 7 CANBIP EIP 7 Unless marked all flags must be cleared by the application software Cleared automatically by hardware when the service routine is entered Tf edge triggered flag is cleared automatically by hardware when the service routine is entered If level triggered flag follows the state of the interrupt pin 24 of 58 110199 DS80C390 CONTROLLER AREA NETWORK CAN MODULE The DS80C390 incorporates two CAN controllers that are fully compliant with the CAN 2 0B specification is a highly robust high performance communication protocol for serial communications Popular in a wide range of applications including automotive medical heating ventilation and industrial control the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware The CAN controllers support the use of 11 bit standard or 29 bit extended acceptance identifiers for up to 15 messages with the standard 8 byte data field in each message Fourteen of the fifteen message centers are p
10. 9 cycle shown for reference 4E wovx instruction Fetch Second Machine Cycle Third Machine Cycle Fourth Machine Cycle 4 Ninth Machine Cycle c1 c1 c2 e Non Multiplexed Address Data PCEO 3 MOVX Write Operation 9 cycle shown for reference ovx instruction Feich 4 Second Machine We E Third Machine Cycle 9 4 Fourth Machine Cycle pi Machine c2 ca c2 ca c1 c2 ca et es ca c1 et PPP PPL RMDP DNS TPHPL TPLPH 4 TWHCEH mat i it 110199 47 of 58 DS80C390 NON MULTIPLEXED 2 CYCLE DATA MEMORY PCE0 3 READ OR WRITE LAST CYCLE FIRST SECOND NEXT I amp OF PREVIOUS P 4 MACHINE Pi MACHINE gt INSTRUCTION INSTRUCTION CYCLE CYCLE MACHINE CYCLE I4 MOVX INSTRUCTION ct NON MULTIPLEXED 2 CYCLE DATA MEMORY CEO 3 READ LAST CYCLE FIRST SECOND NEXT 4 OF PREVIOUS 9 4 MACHINE gt 4 MACHINE gt 4 INSTRUCTION gt INSTRUCTION CYCLE CYCLE MACHINE CYCLE 4
11. DALLAS SEMICONDUCTOR PRELIMINARY DS80C390 Dual CAN High Speed Microprocessor www dalsemi com PEATONES PIN ASSIGNMENT 80C52 compatible 48 33 8051 instruction set compatible Four 8 bit I O ports Three 16 bit timer counters 256 bytes scratchpad RAM High Speed Architecture 4clocks machine cycle 8051 12 Runs DC to 40 MHz clock rates Frequency multiplier reduces EMI Single cycle instruction in 100 ns 16 32 bit math coprocessor 4 kB internal SRAM usable as program data stack memory Enhanced memory architecture Addresses up to 4 MB external Defaults to true 8051 memory compatibility User enabled 22 bit program data counter 16 Bit 22 bit paged 22 bit contiguous modes User selectable multiplexed non multiplexed memory interface Optional 10 bit stack pointer Two full function CAN 2 0B controllers 15 message centers per controller Standard 11 bit or extended 29 bit identification modes Supports DeviceNet SDS and higher layer CAN protocols Disables transmitter during autobaud SIESTA low power mode Two full duplex hardware serial ports Programmable IrDA clock High integration controller includes Power fail reset Early warning power fail interrupt Programmable watchdog timer Oscillator fail detection 16 total interrupt sources with 6 external Available in 64 pin QFP 68 pin PLCC 1 of 58 DS80C390 DS
12. DS80C390 QNR 68 pin PLCC 40 MHz 40 C to 85 C DS80C390 FNR 64 pin LQFP 40 MHz 40 C to 85 C 2 of 58 110199 DS80C390 DS80C390 BLOCK DIAGRAM Figure 1 P2 0 P2 7 0 0 0 7 GND gt amp B lt ma IA 2OOHO2 LVM 193139 280 WYHS 435 66320 3448 952 aani YALNIOd WOVLS TI TT uaisio3s 8 io1vanwnoov 91907 1 1 1031405 35015 O3H HNOV Od L HEH woe uod E UTE ny oe UL 1 08 Xtal1 SERIAL PORT 1 Port Latch SERIAL PORT 0 PORT 1 1 0 1 7 S318VN3 0 P3 0 P3 7 110199 3 of 58 DS80C390 PIN DESCRIPTION Table 1 NAME 8 22 17 32 Vcc 5V m 41 57 35 52 46 57 Address Latch Enable Output When the MUX pin is low this pin outputs a clock to latch the external address LSB from the multiplexed address data bus on Port 0 This signal is commonly connected to the latch enable of an external transparent latch ALE has a pulse width of 1 5 cycles and a period of four XTALI cycles When the MUX pin is high the pin will toggle continuously if the ALEOFF bit is cleared ALE is forced high when the device is in a Reset condition or if the ALEOFF bit is set while the MUX pin is high PSEN Program Store
13. It is important to note the distinction between these two clock signals as they are sometimes confused creating errors in timing calculations Setting CDI CDO to 0 enables the frequency multiplier either doubling or quadrupling the frequency of the crystal oscillator or external clock source The 4X 2X bit controls the multiplying factor selecting twice or four times the frequency when set to 0 or 1 respectively Enabling the frequency multiplier results in apparent instruction execution speeds of 2 or 1 clocks Regardless of the configuration of the frequency multiplier the system clock of the microcontroller can never be operated faster than 40 MHz This means that the maximum crystal oscillator or external clock source is 10 MHz when using the 4X setting and 20 MHz when using the 2X setting The primary advantage of the clock multiplier is that it allows the microcontroller to use slower crystals to achieve the same performance level This reduces EMI and cost as slower crystals are generally more available and thus less expensive 17 of 58 110199 DS80C390 SYSTEM CLOCK CONFIGURATION Table 10 O 0 Frequency Multiplier 2X 20 MHz 0 0 1 Frequency Multiplier 4X 1 10 MHz O 1 NA Reserved yq 5 Eek 1 0 NA _ Divide by four Default 4 OM Power Management Mode 1024 40 MHz The system clock and machine cycle rate changes one machine cycle after the instruction changing the con
14. Kt or PREVIQUEPE bi MACHINE gt 6 MACHINE gt i INSTRUCTION CYCLE CYCLE CYCLE CYCLE K4 MOVX INSTRUCTION PoRTAADORESS OK Aare Ki MAS OO mens Xi moms PORT 50 of 58 110199 DS80C390 NON MULTIPLEXED 9 CYCLE DATA MEMORY PCE0 3 READ OR WRITE I ae Ee pe ll tle mye iy MOVX INSTRUCTION NON MULTIPLEXED 9 CYCLE DATA MEMORY CE0 3 READ C Roi Roi Ro Roi Rod c Ro Ec pee 4 MOVX INSTRUCTION 9 2 1 1 2 1 2 1 3 64 c1 c2 c3 64 2 64 PORT 4 ADORESS PORT 1 ADORESS 51 of 58 110199 DS80C390 NON MULTIPLEXED 9 CYCLE DATA MEMORY CE0 3 WRITE LAST FIFTH THRU NEXT CYCLE OF FIRST SECOND THIRD FOURTH EIGHTH NINTH INSTRUCTION 35 MACHINE pje MACHINE pje oot Pje MACHINE Pi 35 MACHINE ed gt Mes JCTION CYCLE CYCLE CYCLE CYCLE CYCLE ying MOVX INSTRUCTION c1 c2 ca es c1 c2 c3 c4 c1 c2 c3 ca c1 c2 c3 cs 1 2 4 c1 c3 c1 c2 c3 ca c1 ca cs cs E System Clock Selection wi 1 0 0 1 0 ee ___ 4 X 0 1024 terc EXTERNAL CLOCK CHARACTERISTICS 8 ns Clock high time Clock low tax 8 ms Clock rise time 4 ms
15. MAX Oscillator Freq Ext Osc 1 0 40 0 40 MHz Ext Crystal 1 40 1 40 ALE Pulse Width tLHLL 0 375 tucs 5 ns Port O Instruction Address or tavLL 0 125 tucs 5 ns CE0 4 Valid to ALE Low Address Hold after ALE Low LLAXI 0 125 tucs 5 ALE Low to Valid Instruction In O 0 625 20 m ALE Low to PSEN Low um 0125 5 PSEN Pulse Width 95 5 PSEN Low to Valid Instruction In E 0 5 tucs 20 1 Input Instruction Hold after PSEN Ec Input Instruction Float after PSEN 8 6 8 gt gt Port 2 4 Address to Valid Instruction In PSEN Low to Address Float NOTES FOR AC ELECTRICAL CHARACTERISTICS 1 All parameters apply to both commercial and industrial temperature operation unless otherwise noted 2 The value is a function of the machine cycle clock in terms of the processor s input clock frequency These relationships are described in the Stretch Value Timing table 3 All signals characterized with load capacitance of 80 pF except Port 0 ALE PSEN RD and WR with 100 pF 4 Interfacing to memory devices with float times turn off times over 25 ns may cause bus contention This will not damage the parts but will cause an increase in operating current 5 Specifications assume a 50 duty cycle for the oscillator Port 2 and ALE timing will change in relation to duty cycle variation 6 Some AC timing characteristic drawings contain references to the CLK si
16. feature is enabled by setting the Ring Oscillator Select bit RGSL EXIF 1 If enabled the microcontroller uses the ring oscillator as the clock source to exit Stop mode resuming operation in less than 100 ns After 65536 oscillations of the external clock source not the ring oscillator the device will clear the Ring Oscillator Mode bit RGMD EXIF 2 to indicate that the device has switched from the ring oscillator to the external clock source The ring oscillator runs at approximately 10 MHz but varies over temperature and voltage As a result no serial communication or precision timing should be attempted while running from the ring oscillator since the operating frequency is not precise The default state exits Stop mode without using the ring oscillator TIMED ACCESS PROTECTION Selected SFR bits are critical to operation making it desirable to protect them against an accidental write operation The Timed Access procedure prevents an errant processor from accidentally altering bits that would seriously affect processor operation The Timed Access procedure requires that the write of a protected bit be immediately preceded by the following two instructions MOV 0C7h 0AAh MOV 0OC7h 55h Writing an AAh followed by a 55h to the Timed Access register location C7h opens a three cycle window that allows software to modify one of the protected bits If the instruction that seeks to modify the protected bit is not immediately preceded by
17. Clock falltime 24 EXTERNAL DRIVE XTAL1 52 of 58 110199 DS80C390 SERIAL PORT MODE 0 TIMING CHARACTERISTICS Serial port clock cycle time SM2 0 2 clocks per cycle 12 tac ns SM2 1 4 clocks per cycle 4 ns Output data setup to clock rising 5 2 0 12 clocks per cycle 10 tac ns SM2 1 4 clocks per cycle 3 taa ns Output data hold from clock rising SM2 1 4 clocks per cycle ns Input data hold after clock rising ar SM2 0 12 clocks per cycle ns SM2 1 4 clocks per cycle Clock rising edge to input data valid 5 2 0 12 clocks per cycle 11 tac ns SM2 1 4 clocks per cycle 3 taa ns 53 of 58 110199 DS80C390 SERIAL PORT 0 SYNCHRONOUS MODE WRITE TO SBUF RXD DATA OUT TXD CLOCK T WRITE TO SCON TO CLEAR RI RXD DATAIN je IA RECEIVE TXD CLOCK RI TRADITIONAL 8051 OPERATION TXD CLOCK XTAL 12 SM2 0 54 of 58 110199 DS80C390 EXPLANATION OF AC SYMBOLS This microcontroller uses timing parameters and symbols similar to the original 8051 family The following list of timing symbols is provided as an aid to understanding the timing diagrams t Time P PSEN A Address Q Output data C Clock R RD signal CE Chip Enable V Valid D Input data W wR signal H Logic level high X No longer a valid logic level L Logic level low Z Tristate I Instruction POWER CYCLE TIMING CH
18. Enable Output This signal is the chip enable for external ROM memory PSEN provides an active low pulse and is driven high when external ROM is not being accessed This pin selects if the bus operates in 0 demultiplexed MUX 1 mode Reset Input The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs The pin also employs an internal pulldown resistor to allow for a combination of wired OR external Reset sources An RC circuit is not required for power up as the device provides this function internally Reset Output Low Output This active low signal will be asserted When the processor has entered reset via the RST pin During crystal warm up period following power on or Stop mode During a watchdog timer reset 2 cycles duration During an oscillator failure Gf OFDE 1 Whenever XTALI1 XTAL2 Crystal oscillator pins support fundamental mode parallel resonant AT cut crystals is the input if an external clock source is used in place of a crystal XTAL2 is the output of the crystal amplifier ADO 7 Port 0 I O When the MUX pin is tied low Port 0 is the multiplexed address data bus While ALE is high the LSB of a memory address is presented While ALE falls the port transitions to a bi directional data bus When the MUX pin is tied high Port 0 functions as the bi directional data bus Port 0 cannot be modified by software The rese
19. Registers 0 1 Located in each CAN Control Status Mask Register bank MOVX Extended Global Mask Registers 0 3 Located in each CAN Control Status Mask Register bank MOVX memory Media ID Mask Registers 0 1 Located in each CAN Control Status Mask Register bank MOVX EX ST 0 0 Mask register ignored ID and arbitration register must match exactly MEME 1I Only bits corresponding to 1 in mask register are compared in ID and arbitration registers EX ST 1 0 Mask register ignored ID and arbitration register must match exactly MEME 1I Only bits corresponding to 1 in mask register are compared in ID and arbitration registers MDME 0 Media byte arbitration disabled MDME 1 Only bits corresponding to 1 in Media ID mask register are compared between data bytes 1 and 2 and Media arbitration registers memory Message Center 15 Arbitration Registers 0 1 Located in Message Center 15 MOVX memory Message Center 15 Standard 11 bit arbitration CAN 2 0A Message Center 15 Arbitration Registers 0 3 Located in Message Center 15 MOVX memory Message Center 15 Extended 29 bit arbitration CAN 2 0B memory Message Center 15 Mask Registers 0 1 Located in each CAN Control Status Mask Register bank MOVX memory Message Center 15 Mask Registers 0 3 Located in each CAN Control Status Mask Register bank MOVX memory MESSAGE BUFFERING OVERWRITE If a messag
20. functions in microcomputer based systems New functions include a second serial port power fail reset power fail interrupt flag and a programmable watchdog timer In addition the microcontroller contains two Controller Area Network CAN modules for industrial communication applications Each of these peripherals is described below and more details are available in the User s Guide SERIAL PORTS The microcontroller provides a serial port UART that is identical to the 80C52 In addition it includes a second hardware serial port that is a full duplicate of the standard one This second port optionally uses pins P1 2 RXD1 and P1 3 TXD1 It has duplicate control functions included in new SFR locations The second serial port can alternately be mapped to P5 2 and P5 3 to allow use of both serial ports in non multiplexed mode Both ports can operate simultaneously but can be at different baud rates or even in different modes The second serial port has similar control registers SCONI SBUFI to the original The new serial port can only use Timer 1 for baud rate generation The SCONO register provides control for serial port 0 while its I O buffer is SBUFO The registers SCONI and SBUF provide the same functions for the second serial port A full description on the use and operation of both serial ports may be found in the User s Guide WATCHDOG TIMER The Watchdog is a free running programmable timer that can set a flag cause an inte
21. in MOVX memory controls the PHASE SEGI and PHASE SEG2 time segments as well as the Baud Rate Pre scaler BPR5 BPRO The CAN 0 1 Bus Timing Register One and CIBTI contains the controls for the sampling rate and the number of clock cycles assigned to the Phase Segment 1 and 2 portions of the Nominal Bit Time The values of both of the Bus Timing registers are automatically loaded into the CAN Processor following each software change of the SWINT bit from a 1 to a 0 by the microcontroller The bit timing parameters must be set before starting operation of the CAN Processor These registers are only modifiable during a software initialization SWINT 1 when the CAN Processor is NOT in a bus off mode and after the removal of a system reset or a CAN reset To avoid unpredictable behavior of the CAN Processor the software cannot clear the SWINT bit when TSEGI and TSEG2 are both cleared to 0 31 of 58 110199 DS80C390 ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground 0 3 V to VCC 0 5 V Voltage on VCC relative to ground 0 3 V to 6 0 V Operating Temperature 40 C to 85 C Storage Temperature 55 C to 125 C Soldering Temperature 160 C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods
22. these instructions the write will be ignored The protected bits are WDCON 6 POR Power On Reset Flag WDCON 3 WDIF Watchdog Interrupt Flag WDCON 1 EWT Watchdog Reset Enable WDCON 0 RWT Reset Watchdog Timer RCON 0 BGS Band Gap Select ACON 2 SA Stack Address Mode ACON 1 0 AM1 AMO Address Mode Select bits MCON 7 6 IDM1 IDMO Internal Memory Configuration and Location bits MCON 5 CMA CAN Data Memory Assignment MCON 3 0 PDCE3 PDCE 0 Program Data Chip Enables COC 3 CRST CAN 0 Reset C1C 3 CRST CAN 1 Reset P4CNT 6 SBCAN Single Bus CAN P4CNT 5 0 Port 4 Pin Configuration Control Bits PSCNT 2 0 5 7 5 5 Configuration Control Bits COR 7 IRDACK IRDA Clock Output Enable COR 6 5 7 CAN 1 Baud Rate Pre scale Bits COR 4 3 COBPR7 COBPR6 CAN 0 Baud Rate Pre scale Bits COR 2 1 COD1 CODO CAN Clock Output Divide Bit 1 and Bit 0 0 CAN Clock Output Enable 21 of 58 110199 DS80C390 EMI REDUCTION One of the major contributors to radiated noise in an 8051 based system is the toggling of ALE The microcontroller allows software to disable ALE when not used by setting the ALEOFF PMR 2 bit to a 1 When ALEOFF 1 ALE will automatically toggle during an off chip MOVX However ALE will remain static when performing on chip memory access The default state of ALEOFF is 0 so ALE normally toggles at a frequency of XTAL 4 PERIPHERAL OVERVIEW The DS80C390 provides several of the most commonly needed peripheral
23. two data pointers and DPTRI designed to improve performance in applications that require high data throughput Incorporating a second data pointer allows the software to greatly speed up block data MOV X moves by using one data pointer as a source register and the other as the destination register DPTRO is located at the same address as the original 8051 data pointer allowing the DS80C390 to execute standard 8051 code with no modifications The second data pointer DPTRI is split between the DPHI and SFRs similar to the configuration The active data pointer is selected with the data pointer select bit SEL DPS 0 Any instructions that reference the DPTR 1 MOVX A DPTR will select if SEL 0 and DPTRI if SEL 1 Because the bits adjacent to SEL are not implemented the state of SEL and thus the active data pointer can be quickly toggled by the INC DPS instruction without disturbing other bits in the DPS register Unlike the standard 8051 the DS80C390 has the ability to decrement as well as increment the data pointers without additional instructions When the INC DPTR instruction is executed the active DPTR increments or decrements according to IDO DPS 7 6 and SEL DPS 0 bits as shown inactive DPTR is not affected DATA POINTER AUTOINCREMENT DECREMENT CONFIGURATION Table 9 ID1 IDO SEL Result of INC DPTR xX 0 0 ___ X 1 0 Decremen
24. using Ri MXAX EAh 2 Addressing program memory in AP 9Ch 22 bit paged mode 10 bit stack pointer mode ESP 9Bh SP 81h 12 of 58 110199 DS80C390 INTERNAL MOVX SRAM The DS80C390 contains 4 of SRAM that can be configured as user accessible MOVX memory program memory or optional stack memory The specific configuration and locations are governed by the Internal Data Memory Configuration bits IDMI IDMO in the Memory Control Register MCON C6h Note that when the SA bit ACON 2 is set the first IKB of the MOVX data memory is reserved for use by the 10 bit expanded stack Internal memory accesses will not generate WR RD or PSEN strobes The DS80C390 can configure its 4 of internal SRAM as combined program and data memory This allows the application software to execute self modifiable code The technique loads the 4kB SRAM with bootstrap loader software and then modifies the IDM1 and bits to map the 4kB starting at memory location 40000h This allows the system to run the bootstrap loader without disturbing the 4 MB external memory bus making the device in system reprogrammable for Flash or NV RAM INTERNAL MOVX SRAM CONFIGURATION Table 4 CMA MOVX Data Memory CAN Message Shared Program Data Memory Memory 0 OOFO00h O0FFFFh OO0EEO0h O0EFFFh KARRERA QOF000h 0OFFFFh 401000h 4011FFh 0 1 0 000000h 000FFFh 000000h 000
25. will be loaded into a message center Each enabled message center see the MSRDY bit in the CAN Message Control Register is tested in order from 1 15 The first message center to successfully pass the test will receive the incoming message and end the testing The use of masking registers allows the use of more complex identification schemes as tests can be made based on bit patterns rather than an exact match between all bits in the identification field and arbitration values Each CAN processor also incorporates a set of five masks to allow messages with different IDs to be grouped and successfully loaded into a message center Note that some of these masks are optional as per the bits shown in the Arbitration Masking Feature Summary table There are several possible arbitration tests varying according to which message center is involved If all of the enabled tests succeed the message is loaded into the respective message center The most basic test performed on all messages compares either 11 CAN 2 0A or 29 CAN 2 0B bits of the identification field to the appropriate arbitration register based the bit in the CAN 0 1 Format Register The MEME bit COMxF 1 or 1 controls whether the arbitration and ID registers are 29 of 58 110199 DS80C390 compared directly or via a mask register A special set of arbitration registers dedicated to Message center 15 allow added flexibility in filtering this location If desi
26. with software executing at higher speed Timers optionally can run at the faster 4 clocks per increment to take advantage of faster processor operation The relative time of two DS80C390 instructions might differ from the traditional 8051 For example in the original architecture the MOVX A DPTR instruction and the MOV direct direct instruction 7 of 58 110199 DS80C390 required the same amount of time two machine cycles or 24 oscillator cycles In the DS80C390 the MOVxX instruction takes as little as two machine cycles or 8 oscillator cycles but the MOV direct direct uses three machine cycles or 12 oscillator cycles While both are faster than their original counterparts they now have different execution times This is because the device usually uses one instruction cycle for each instruction byte Examine the timing of each instruction for familiarity with the changes Note that a machine cycle now requires just 4 clocks and provides one ALE pulse per cycle Many instructions require only one cycle but some require five Refer to the user s guide for details and individual instruction timing SPECIAL FUNCTION REGISTERS Special Function Registers SFRs control most special features of the microcontroller This allows the device to have many new features but use the same instruction set as the 8051 When writing software to use a new feature an equate statement defines the SFR to an assembler or compiler This is the onl
27. 2 Output Port 2 serves as the MSB for external addressing The port automatically asserts the address MSB during external ROM and RAM access Although the Port 2 SFR exists the SFR value will never appear on the pins due to memory access Therefore accessing the Port 2 SFR is only useful for MOVX A Ri or MOVX A instructions which use the Port 2 SFR as the external address MSB Port 3 I O Port 3 functions as an 8 bit bi directional I O port and as an alternate interface for several resources found on the traditional 8051 The reset condition of Port 1 is all bits at logic 1 via a weak pullup The logic 1 state also serves as an input mode since external circuits writing to the port can overdrive the weak pullup When software clears any port pin to 0 the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs Writing a 1 after the port has been at 0 will activate a strong transition driver followed by a weaker sustaining pullup Once the momentary strong driver turns off the port once again becomes the output and input high state Port Alternate Function P3 0 RXDO Serial Port 0 Input P3 1 TXDO Serial Port 0 Output P3 2 INTO External Interrupt 0 P3 3 INTI External Interrupt 1 P3 4 TO Timer 0 External Input P3 5 TI XCLK Timer 1 External Input External Clock Output P3 6 WR External Data Memory Write Strobe 5 of 58 110199 DS80C390
28. 20 1 lt Csr lt 3 lt 2 625 5 20 4 lt lt 7 Port 0 Address Port 4 CE Port tAVWLI 0 25 tucs 5 5 PCE to RD or WR Low 0 5 5 2 5 10 Port 2 4 Address to RD or WR tavwr2 0 375 tmcs 5 Low 0 625tmcs 5 2 625 tmcs 10 Data Valid to WR Transition Data hold after WR high twuox 0 25 tmcs 5 0 5tmcs 5 1 5 10 RD or WR High to ALE Port4 0 CE or Port 5 PCE High 0 25 tmcs 5 0 25 tmcs 5 1 25 twcs 5 1 25 twcs 5 45 of 58 110199 DS80C390 XTAL Non Multiplexed Address Data CEQ 3 MOVX Read Operation 9 cycle shown for reference 6 instruction Fetch P gt Second Machine Cycle Third Machine Cycle Fourn Machine PH Wace cys pt Ninth Machine es ca et c2 ca c2 ca et 1 es Non Multiplexed Address Data 0 3 MOVX Write Operation 9 cycle shown for reference instruction Fetch Second Machine Third Machine Cycle 94 Fourth Machine Cycle HIE pjd Ninth Machine Cycle c2 ei c1 c2 1 110199 46 of 58 DS80C390 Non Multiplexed Address Data 0 3 MOVX Read Operation
29. 7FFFFh 80000h BFFFFh C0000h FFFFFh 110 Oh 7FFFFh 80000h FFFFFh 100000h 17FFFFh 180000h 1FFFFFh 111 default 0 FFFFFh 100000h 1FFFFFh 200000h 2FFFFFh 300000h 3FFFFFh The DS80C390 incorporates a feature allowing PCE and CE signals to be combined This is useful when incorporating modifiable code memory as part of a bootstrap loader or for in system reprogrammability Setting the PDCE3 0 MCON 3 0 bits causes the corresponding chip enable signal to function for both MOVC and MOVX operations Write access to combined program and data memory blocks is controlled by the WR signal and read access is controlled by the PSEN signal This feature is especially useful if the design achieves in system reprogrammability via external Flash memory in which a single device 1s accessed via both MOVC instructions program fetch and MOVX Write operations updates to code memory In this case the internal SRAM is placed in the program data configuration and loaded with a small bootstrap loader program stored in the external Flash memory The device then executes the internal bootstrap loader routine to modify update the program memory located in the external Flash memory STRETCH MEMORY CYCLES The DS80C390 allows user application software to select the number of machine cycles it takes to execute a MOVX instruction allowing access to both fast and slow off chip data memory and or peripherals without glue logic High speed systems often include memory m
30. 80C390 68 PIN PLCC 110199 DS80C390 DESCRIPTION The DS80C390 is a fast 8051 compatible microprocessor The redesigned processor core executes 8051 instructions up to 3 times faster than the original for the same crystal speed The DS80C390 supports a maximum crystal speed of 40 MHz resulting in apparent execution speeds of 100 MHz approximately 2 5X An optional internal frequency multiplier allows the microprocessor to operate at full speed with a reduced crystal frequency reducing EMI A hardware math accelerator further increases the speed of 32 and 16 bit multiply and divide operations as well as high speed shift normalization and accumulate functions The DS80C390 features two full function Controller Area Network CAN 2 0B controllers Status and control registers are distributed between SFRs and 512 bytes of internal MOVX memory for maximum flexibility In addition to standard 11 bit or 29 extended message identifiers the device supports two separate 8 bit media masks and media arbitration fields to support the use of higher level CAN protocols such as DeviceNet and SDS All of the standard 8051 resources such as three timer counters serial port and four 8 bit I O ports plus two 8 bit ports dedicated to memory interfacing are included in the DS80C390 In addition it includes a second hardware serial port seven additional interrupts programmable watchdog timer brown out monitor power fail reset and a programmable output c
31. 99 DS80C390 during the debug process to determine where watchdog reset commands must be located in the application software The interrupt also can serve as a convenient time base generator or can wake up the processor from power saving modes The Watchdog timer is controlled by the Clock Control CKCON and the Watchdog Control WDCON SFRs CKCON 7 and CKCON 6 are WD and WDO respectively and they select the Watchdog time out period Of course the 4X 2X PMR 3 and CDI 0 PMR 7 6 system clock control bits also affect the time out period Selection of time out is shown below WATCHDOG TIME OUT VALUES Table 11 WATCHDOG INTERRUPT TIME OUT WATCHDOG RESET TIME OUT n m 00 DA 01 baie 10 ae 11 WD1 0 00 WD1 0 01 WD1 0 10 WD1 0 11 251512 2 512 714512 253519 IRSE 2 25 2 9 26 2 7 512 2 512 2 2 512 SS cele rss rum The table demonstrates that for 33 MHz crystal frequency the Watchdog timer is capable of producing time out periods from 3 97 ms 27 1 33 MHz to over two seconds 2 034 226 1 33 MHz with the default setting of CD1 0 10 This wide variation in time out periods allows very flexible system implementation In a typical initialization the user selects one of the possible counter values to determine the time out Once the counter
32. A 0 00 CMA 1 4011 CAN INTERRUPTS The DS80C390 supports 3 interrupts associated with the CAN controllers One interrupt is dedicated to each CAN controller providing receive transmit acknowledgments from each of its 15 message centers The remaining interrupt the Can Bus Activity Interrupt is used to detect CAN bus activity on the CORX or CIRX pins The message center interrupts are enabled disabled by individual ETI transmit and ERI receive enable bits in the corresponding Message Control Register located in SFR memory for each message center All of the message center interrupts of each CAN module are ORed together into their respective CAN interrupt The successful transmission or receipt of a message will set the INTRQ bit in the corresponding Message Control Register located in SFR memory This bit can only be cleared via software In addition the Global Interrupt Enable bit IE 7 and the specific CAN Interrupt Enable bit EIE 6 CANO or EIE 5 CANI must be correctly set to acknowledge a message center interrupt Interrupt assertion of error and status conditions associated with the CAN modules is controlled by the ERIE and STIE bits located in the CAN Control registers COC and ARBITRATION AND MASKING After a CAN module has ascertained that an incoming message is bit error free the identification field of that message is then compared against one or more arbitration values to determine if they
33. AND El 2 DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED 3 ALLOWABLE DAMBAR PROTRUSION IS 0 08 MM TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION PROTRUSION NOT TO BE LOCATED ON LOWER RADIUS OR FOOT OF LEAD 0 MIN GUAGE PLANE ze DIMENSIONS ARE IN MILLIMETERS DETAIL A 57 of 58 110199 DS80C390 DATA SHEET REVISION SUMMARY The following represent the key differences between the 092499 and the 101999 version of the DS80C390 data sheet Please review this summary carefully Corrected P5 2 and P5 3 pin descriptions Corrected description of sequence to activate the crystal frequency multiplier Corrected references to PQFP to read LQFP Added RSTOL timing information duc The following represent the key differences between the 062299 and the 090799 version of the DS80C390 data sheet Please review this summary carefully 1 Clarifies that unused unimplemented bits in the CAN MOVX SRAM will read 0 2 Corrected the tics time periods tables 3 Corrected multiplexed 2 cycle date memory CEO 3 read figure to show RD and WR inactive 58 of 58 110199
34. ARACTERISTICS PARAMETER SYMBOL TYP MAX UNITS NOTE Crystal start up time tw 18 ms 1 Power on reset delay 1 165536 NOTES FOR POWER CYCLE TIMING CHARACTERISTICS 1 Start up time for crystals varies with load capacitance and manufacturer Time shown is for an 11 0592 MHz crystal manufactured by Fox Electronics 2 Reset delay is a synchronous counter of crystal oscillations during crystal start up Counting begins when the level on the XTALI input meets the Vigo criteria At 40 MHz this time is approximately 1 64 ms POWER CYCLE TIMING Voc mun an om a wp om am SERVICE come 4 tron Ph INTERNAL RESET 1 55 of 58 110199 DS80C390 68 PIN PLCC NOTE PIN 1 IDENTIFIER BE LOCATED IN ZONE INDICATED 2 DIMENSIONS ARE IN INCH UNITS SEE DETAIL A DIM MIN 090 120_ 020 b 026 032 D 1 985 995 E DETAIL A 56 of 58 110199 64 PIN LQFP ait No SEE DETAIL MAX o T o o CA gt olo NIN N N o P e MIPS NIO e o N Q N o Se e o o 0 45 0 75 DS80C390 NOTES 1 DIMENSIONS 01 AND E INCLUDE MOLO MISMATCH BUT DO NOT INCLUDE MOLO PROTRUSION ALLOWABLE PROTRUSION IS 0 25 01
35. Csr 1 25 tmcs 40 4 lt lt 7 35 of 58 110199 DS80C390 Port 0 Address Port 4 CE tAVDVI 0 75 tmcs 20 ns Csr 0 Port 5 PCE to Valid Data In Csr40 375 tyucs 20 I lt Csr lt 3 1 375 20 Port 2 4 Address to Valid 0 875 20 Data In Csr40 5 etycs 20 1 5 20 ALE Low to RD or WR 0 125 5 0 125 5 Low 0 251 5 0 25tmcs 5 1 25 tmcs 10 1 25 tucs 10 Port 0 Address Port 4 CE tAVWLI 0 25 5 ns Csr 0 p 5 to RD or WR 0 5tmcs 5 1 lt Csr 3 Low 2 5 tmcs 10 4 lt Csr lt 7 tavwi2 0 375 tmcs 5 0 625 5 5 RD or WR High to ALE twHLH 0 10 ns Csr 0 Port 4 CE Port 5 PCE 0 25 tmcs 5 0 25 tmcs 5 1 lt Csr lt 3 High 1 25 tmcs 10 1 25 10 4 lt Csr lt 7 NOTES FOR MOVX CHARACTERISTICS 1 All parameters apply to both commercial and industrial temperature operation unless otherwise noted 2 CST is the stretch cycle value as determined by the MD2 MD1 amp MDO bits of the CKCON register tmcs is a time period determined by the stretch cycle value shown in the following table tucs TIME PERIODS 1 0 0 0 ter k X 1 0 4 1024 torc 1 tercer 36 of 58 110199 DS80C390 Multiplexed Address Data 0 3 MOVX Read Operation 9 cycle shown for reference c1 e et XTAL1 ca ct c2
36. EA IE 7 Setting EA to a 1 allows individual interrupts to be enabled Clearing EA disables all interrupts regardless of their individual enable settings The three available priority levels are low high and highest The highest priority level is reserved for the Power Fail Interrupt only other interrupt priority levels have individual priority bits that when set to 1 establish the particular interrupt as high priority In addition to the user selectable priorities each interrupt also has an inherent natural priority used to determine the priority of simultaneously occurring interrupts The available interrupt sources their flags their enables their natural priority and their available priority selection bits are identified in the following table INTERRUPT SUMMARY Table 12 NAME DESCRIPTION VECTOR NATURAL FLAG BIT ENABLE BIT PRIORITY PRIORITY CONTROL BIT Power Fail Interrupt 0 PFKWDCONA4 EPFI WDCON 5 NA INTO External Interrupt 0 03h 1 IEO TCON 1 EXO IE 0 PXO IP 0 TFO TCON 5 ETO IE 1 PTO P 1 INTI External Interrupt 1 IEI TCON 3 EX1 IE 2 PX1 IP 2 TF1 Timer 1 1Bh 4 TF1 TCON 7 ETI TE 3 PTI IP 3 port 0 O SCONO 1 TF2 Timer 2 2Bh 6 TF2 T2CON 7 ET2 IE 5 PT2 IP 7 SCONI or RII from serial 3Bh 7 1 SCONI 0 ES1 IE 6 PS1 IP 6 Hugh INT2 External Interrupt 2 43h 8 TE2 EXIF 4 EX2 EIE 0 PX2 EIP 0 INT3 External Interrupt3
37. FFFh 401000h 4011FFh 400000h 400FFFh OOEEO0h DOEFFFh 10 bit expanded stack not available in Shared Program Data Memory mode EXTERNAL MEMORY ADDRESSING The enabling and mapping of the chip enable signals is done via the Port 4 Control Register PACNT 92h and Memory Control Register MCON 96h The Extended Address and Chip Enable Generation Table shows which chip enable and address line signals are active on Port 4 Following reset the device will be configured with P4 7 P4 4 as address lines and P4 3 P4 0 configured as CE3 0 with the first program fetch being performed from 00000h with CEO active The following tables illustrate which memory ranges are controlled by each chip enable as a function of which address lines are enabled EXTERNAL MEMORY ADDRESSING PIN ASSIGNMENTS Table 5 Address Data Bus 19 16 Addr 15 8 Addr 7 0 Multiplexed P4 3 P4 0 P5 7 P5 4 P4 7 P4 4 Demuliplexed 957954 gt P m EXTENDED ADDRESS AND CHIP ENABLE GENERATION Table 6 Port4PinFunctin Port4 Pin Function P4CNT 5 3 P4 7 P4 6 P4 5 P4 4 PACNT2 0 P4 3 P4 2 P4 1 P4 000 vo 00 WO VO 10 10 101 AIS AI8 13 of 58 110199 DS80C390 PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table 7 CEO CES 000 Oh 7FFFh 8000h FFFFh 10000h 17FFFh 18000h 1FFFFh Oh 1FFFFh 20000h 3FFFFh 40000h 5FFFFh 60000h 7FFFFh Oh 3FFFFh 40000h
38. R 11 REGISTERS similar to Message Center 1 xxxxBOh BFh MESSAGE CENTER 12 REGISTERS similar to Message Center 1 xxxxCOh MESSAGE CENTER 13 REGISTERS similar to Message Center 1 xxxxDOh MESSAGE CENTER 14 REGISTERS similar to Message Center 1 EFh CAN 0 MESSAGE CENTER 15 COMISARO COMISARI COMISAR COMISAR3 COMISE 0 MEME COM15D0 COMI5D7 CAN 0 MESSAGE 15 DATA BYTE 0 7 xxxxF7h FEh Reserved Notes The first two bytes of the CAN 0 MOVX memory address are dependent on the setting of the CMA bit MCON 5 CMA 0 00 CMA 1 xxxx 4010 27 of 58 110199 DS80C390 MOVX MESSAGE CENTERS FOR CAN 1 CAN 1 CONTROL STATUS MASK REGISTERS 7 6 a 3 x o CIMAO 7 MOAA6 5 MOAA4 MOAA2 1 xxxxOlh C1SGMO xxxx06h CISGMI m iio ipis o o 0 0 xh CIEGM2 1012 1011 1010 9 108 ID7 ID6 ID5 xxxxOAh CIEGMS m ms i pi wo 0 0 O xea0Bh CIMISM2 IDI2 D11 IDIO 1 9 ws ID7 We Ws IDA ID3 ID2 IDI IDO 0 0 CIM15MG3 0 xxxxOFh CAN 1 MESSAGE CENTER 1 ae Reserved xxxxlOh 11h CIMIARO CAN 1 MESSAGE 1 ARBITRATION REGISTER 0 CIMIARI CAN 1 MESSAGE 1 ARBITRATION REGISTER 1 CIMIAR2 CAN 1 MESSAGE 1 ARBITRATION
39. REGISTER 2 CAN 1 MESSAGE CENTERS 2 14 MESSAGE CENTER 2 REGISTERS similar to Message Center 1 xxxx20h 2Fh MESSAGE CENTER 3 REGISTERS similar to Message Center 1 xxxx30h 3Fh MESSAGE CENTER 4 REGISTERS similar to Message Center 1 xxxx4Oh 4Fh MESSAGE CENTER 7 REGISTERS similar to Message Center 1 xxxx7Oh 7Fh MESSAGE CENTER 8 REGISTERS similar to Message Center 1 xxxx80h 8Fh MESSAGE CENTER 9 REGISTERS similar to Message Center 1 Xxxx90h 9Fh MESSAGE CENTER 10 REGISTERS similar to Message Center 1 xxxxAOh AFh MESSAGE CENTER 11 REGISTERS similar to Message Center 1 xxxxBOh BFh MESSAGE CENTER 12 REGISTERS similar to Message Center 1 xxxxCOh CFh MESSAGE CENTER 13 REGISTERS similar to Message Center 1 xxxxDOh MESSAGE CENTER 14 REGISTERS similar to Message Center 1 xxxxEOh EFh 28 of 58 110199 DS80C390 CAN 1 MESSAGE CENTER 15 ez xh Reserved xxxxFOh Flh CIMISARO CAN 1 MESSAGE 15 ARBITRATION REGISTER 0 CIMISARI CAN 1 MESSAGE 15 ARBITRATION REGISTER 1 xxxxF3h CIMISAR2 CAN 1 MESSAGE 15 ARBITRATION REGISTER 2 CIMISAR3 CAN 1 MESSAGE 15 ARBITRATION REGISTER 3 WTOE CIMISF DTBYC3IDTBYC2DDTBYCI 0 EX sr MEME MDME C1MI5DO CIMISD7 CAN 1 MESSAGE 15 DATA BYTE 0 7 xxxxF7h FEh Notes The first two bytes of the CAN 1 MOVX memory address are dependent on the setting of the CMA bit MCON 5 CM
40. apped peripherals such as LCDs or UARTSs with slow access times so it may not be necessary or desirable to access external devices at full speed The microprocessor can perform a MOVX instruction in as little as two machine cycles or as many as twelve machine cycles Accesses to internal MOVX SRAM always use two cycles Note that stretch cycle settings affect external MOV X memory operations only and that there is no way to slow the accesses to program memory other than to use a slower crystal or external clock External MOVX timing is governed by the selection of 0 to 7 Stretch cycles controlled by the MD2 MDO SFR bits in the Clock Control Register CKCON 2 0 A Stretch of zero will result in a two machine cycle MOVX instruction A Stretch of seven will result in a MOVX of twelve machine cycles Software can dynamically change the Stretch value depending on the particular memory or peripheral being accessed The default of one Stretch cycle allows the use of commonly available SRAMs without dramatically lengthening the memory access times Stretch cycle settings affect external MOVX timing in three gradations Changing the Stretch value from 0 to 1 adds an additional clock cycle each to the data setup and hold times When a Stretch value of 4 or above is selected the interface timing changes dramatically to allow for very slow peripherals First the ALE signal is lengthened by 1 machine cycle This increases the address setup time into the periphera
41. ccessed eliminating the need for a special step to choose the operation The normalize function facilitates the conversion of 4 byte unsigned binary integers into floating point format The following table shows the operations supported by the math accelerator and their time of execution ARITHMETIC ACCELERATOR EXECUTION TIMES Table 3 16 bit 16 bit divide 16 bit quotient 16 bit remainder 24 32 bit shift left right 32 bit result 36 The following table demonstrates the procedure to perform mathematical operations using the hardware math accelerator The MA and MB registers must be loaded and read in the order shown for proper operation although accesses to any other registers can be performed between access to the MA or MB registers An access to the MA MB or MC registers out of sequence will corrupt the operation requiring the software to clear the MST bit to restart the math accelerator state machine Consult the description of the MCNTO SER for details of how the shift and normalize functions operate 10 of 58 110199 DS80C390 ARITHMETIC ACCELERATOR SEQUENCING Load MA with dividend LSB Load MA with dividendLSB 1 Load MA with dividend LSB 2 Load MA with dividend MSB Load MB with divisor LSB Load MB with divisor MSB Poll the MST bit until cleared 9 machine cycles Read MA to retrieve the quotient MSB Read MA to retrieve the quotient LSB 2 Read MA to retrieve the quotient LSB 1 Read MA to
42. chain has completed a full count hardware will set the interrupt flag WDIF WDCON 3 Regardless of whether the software makes use of this flag there are then 512 clocks left until the reset flag WTRF WDCON 2 is set Software can enable 1 or disable 0 the reset using the Enable Watchdog Timer Reset EWT WDCON 1 bit POWER FAIL RESET The microcontroller incorporates an internal precision band gap voltage reference and comparator circuit which provide a power on and power fail reset function This circuit monitors the processor s incoming power supply voltage Vcc and holds the processor in reset while Vcc is below the minimum voltage level When power exceeds the reset threshold a full power on reset will be performed In this way this internal voltage monitoring circuitry handles both power up and power down conditions without the need for additional external components Once has risen above Vgsr the device will automatically restart the oscillator for the external crystal and count 65 536 clock cycles before program execution begins at location 0000h This helps the system maintain reliable operation by only permitting processor operation when the supply voltage is in a known good state Software can determine that a power on reset has occurred by checking the Power On Reset flag POR WDCON 6 Software should clear the POR bit after reading it POWER FAIL INTERRUPT The band gap voltage reference that sets a precise reset thresho
43. citance of 80 pF except Port 0 ALE PSEN RD and WR with 100 pF 4 Interfacing to memory devices with float times turn off times over 25 ns may cause bus contention This will not damage the parts but will cause an increase in operating current 5 Specifications assume a 50 duty cycle for the oscillator Port 2 timing will change in relation to duty cycle variation 43 of 58 110199 DS80C390 NON MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE m PSEN texiz 44 tavive pa PORT 2 ADDRESS 8 15 OUT ADDRESS A8 A15 OUT PORT 4 ADDRESS A16 A19 ADDRESS A16 A19 PORT 1 1 ADDRESS 0 7 OUT 4 3 44 of 58 110199 DS80C390 MOVX CHARACTERISTICS Non multiplexed address data bus PARAMETER SYMBOL MIN MAX UNITS STRETCH VALUES Input Instruction Float after 0 5 tmcs 5 2 75 tmcs 10 lt lt ae Port 4 CE Port 5 PCE Valid es etucs 10 Csr tycs 10 Csr 20 Data Hold after Read Data Float after Read 0 5 tcs 5 0 75twcs 5 1 75 5 PSEN High to WR Low 0 5 tucs 5 0 75twcs 5 2 75 tmcs 5 Data Float after Read tPHRL 0 5 tucs 5 ns Csr 0 0 75twcs 5 1 lt Csr lt 3 2 75 tmcs 5 4 lt Csr lt 7 Port 1 Address Port 4 CE Port 0 75 tmcs 20 5 PCE to Valid Data In 0 5 etucs 20 lt 2 5 20 Port 2 4 Address to Valid Data 0 875 tcs 20 ns Csr 0 In 0 625
44. detect circuitry will not be activated when the oscillator is stopped due to the processor entering Stop mode 18 of 58 110199 DS80C390 POWER MANAGEMENT MODE PMM Machine Cycle Rate Operating Current Estimates Full Operation PMM Full Operation PMM Crystal Speed 4 clocks per 1024 clocks per 4 clocks per 1024 clocks per machine cycle machine cycle machine cycle machine cycle 11 0592 MHz 2 765 MHz 10 8 kHz 13 1 ma 4 8 ma 16 MHz 4 0 MHz 15 6 kHz 17 2 ma 5 6 ma 25 MHz 6 25 MHz 24 4 kHz 25 7 ma 7 0 ma 33 MHz 8 25 MHz 32 2 kHz 32 8 ma 8 2 ma 40 MHz 10 0 MHz 39 1 kHz TBD TBD Note that power consumption in PMM is less than Idle mode While both modes leave the power hungry internal timers running PMM runs all clocked functions such as timers at the rate of crystal divided by 1024 rather than crystal divided by 4 Even though instruction execution continues in PMM albeit at a reduced speed it still consumes less power than Idle mode As a result there is little reason to use Idle mode in new designs SWITCHBACK When enabled the Switchback feature allows serial ports and interrupts to automatically switch back from divide by 1024 PMM to divide by 4 standard speed operation This feature makes it very convenient to use the Power Management Mode in real time applications Software can simply set the CD1 and CDO clock control bits to the 4 clocks per cycle mode to exit PMM However the microcontroller provides hardware alternatives f
45. e 8051 In the DS80C390 the same machine cycle takes 4 clocks Thus the fastest instruction 1 machine cycle executes 3 times faster for the same crystal frequency The majority of instructions on the DS80C390 will see the full 3 to 1 speed improvement while a few will execute between 1 5 and 2 4 times faster Regardless of specific performance improvements all instructions are faster than the original 8051 Improvement of individual programs will depend on the actual mix of instructions used Speed sensitive applications should make the most use of instructions that are 3 times faster However the large number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any arbitrary combination of instructions These architecture improvements and the sub micron CMOS design produce a peak instruction cycle in 100 ns 10 MIPs The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory INSTRUCTION SET SUMMARY All instructions perform exactly the same functions as their 8051 counterparts Their effect on bits flags and other status functions is identical However the timing of instructions is different both in absolute and relative number of clocks The absolute timing of software loops can be calculated using a table in the user s guide However counter timers default to run at the traditional 12 clocks per increment In this way timer based events occur at the standard intervals
46. e center is configured for reception 0 and the previous message has not been read DTUP 1 then the disposition of an incoming message to that message center will be controlled by the WTOE bit located in CAN Arbitration Register 3 of each message center EX ST 0 0 Mask register ignored ID and arbitration register must match exactly MEME 1 Message center 15 mask registers ANDed with Global Mask register Only bits corresponding to 1 in resulting value are compared in ID and arbitration registers EX ST 1 0 Mask register ignored ID and arbitration register must match exactly MEME 1 Message center 15 mask registers ANDed with Global Mask register Only bits corresponding to 1 in resulting value are compared in ID and arbitration registers When WTOE 0 the incoming message will be discarded and the current message untouched 30 of 58 110199 DS80C390 If the WTOE bit is set the incoming message will be received and written over the existing data bytes in that message center The Receiver Overwrite bit ROW will also be set in the corresponding Message Center Control Register located in SFR memory Message center 15 is unique in that it incorporates a buffer that can receive up to two messages without loss If a message is received by message center 15 while it contains an unread message the new incoming message is held in an internal buffer When the CAN processor reads th
47. e message center 15 memory location and then clears DTUP INTRQ EXTRQ 0 the contents of the internal buffer will automatically be loaded into the message center 15 MOVX memory location The message center 15 WTOE bit controls what happens if a third message is received when both the message center 15 MOVX memory location and the buffer contain unread messages If WTOE 0 the new message will be discarded leaving the message center 15 MOVX memory location and the buffer untouched If WTOE 1 then the third message will write over the buffered message but leave the message center 15 MOVX memory location untouched ERROR COUNTER INTERRUPT GENERATION Each CAN module can be independently configured to alert the microprocessor when either 96 or 128 errors have been detected by the transmit or receive error counters The Error Count Select bit ERCS COC 1 or 1 selects whether the limit is 96 ERCS 0 128 ERCS 1 errors When the error limit is exceeded the CAN Error Count Exceeded bit CECE 05 6 or C1S 6 bit is set If the ERIE COIE and EA SFR bits are configured an interrupt will be generated If the ERCS bit is set the device will generate an interrupt when the CECE bit is set or cleared if the interrupt is enabled BIT TIMING Bit timing of the CAN transmission can be adjusted per the CAN 2 0B specification The CAN 0 1 Bus Timing Register Zero COBTO and located in the Control Status Mask Register block
48. eference enabled during Stop mode The default or reset condition of the bit is logic 0 which disables the band gap during Stop mode This bit has no control of the reference during full power PMM or Idle modes With the band gap reference enabled the Power fail reset and interrupt are valid means for leaving Stop mode This allows software to detect and compensate for a power supply sag or brownout even when in Stop mode In Stop mode with the band gap enabled Icc will be approximately 100 uA compared with 1 with the band gap disabled If a user does not require a Power fail Reset or Interrupt while in Stop mode the band gap can remain disabled Only the most power sensitive applications should disable the band gap reference in Stop mode as this results in an uncontrolled power down condition RING OSCILLATOR The second enhancement to Stop mode reduces power consumption and allows the device to restart instantly when exiting Stop mode The ring oscillator is an internal clock that can optionally provide the clock source to the microcontroller when exiting Stop mode in response to an interrupt 20 of 58 110199 DS80C390 During Stop mode the crystal oscillator is halted to maximize power savings Typically 4 10 ms are required for an external crystal to begin oscillating again once the device receives the exit stimulus The ring oscillator by contrast is a free running digital oscillator that has no startup delay The ring oscillator
49. gnal This waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of signals relative to the external clock 0 875 tucs ns ae 5 Port O Address to Valid Instruction 0 75 20 In LE 34 of 58 110199 DS80C390 MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE tw ALE tavu uc lexix ADDRESS INSTRUCTIO ADDRESS PORTO bonas PORT 2 a ADDRESS A8 A15 OUT ADDRESS A8 A15 OUT PORT 4 ADDRESS A16 A19 ADDRESS A16 A19 PORT 4 CEO 3 MOVX CHARACTERISTICS Multiplexed address data bus PARAMETER SYMBOL MIN MAX UNITS STRETCH VALUES Cs1 MD2 0 ALE Pulse Width tLHLL2 0 375 tmcs 5 Csr 0 0 5 tucs 5 1 lt Csr lt 3 1 5 tmcs 10 Csr Port O MOVX Address tAVLL2 0 125 5 CE0 4 PCE0 4 Valid to 0 25twcs 5 ALE Low 1 25 10 Address Hold after MOVX tLLAX2 0 125 tmcs 5 ns Read Write 1 125 tmcs 5 Ex Csr tucs 10 1 lt lt 7 WR Pulse Width 0 5 tucs 5 Lil Csr 0 Csr tucs 10 1 lt Csr lt 7 RD Low to Valid Data In 0 5 tucs 20 Csr 0 Csr lt 20 1 lt 7 Data Hold after Read 0 et ox s Data Float after Read tRHDZ 0 25 tucs 5 ns Csr 0 0 5tmcs 5 1 lt lt 3 1 5 tucs 5 4 lt lt 7 ALE Low to Valid Data In 0 625 tmcs 20 Csr 0 lt 0 25 40 1 lt Csr lt 3
50. ith the message centers data identification identification arbitration masks format and data are located in MOVX data space The CMA bit MCON 5 allows the message centers to be mapped to either OOEE00h 00EEFFh CMA 0 or 401000h 4011FFh CMA 1 reducing the possibility of a memory conflict with application software Note that setting the CMA bit employs a special twenty third address bit that is only used for addressing CAN MOVX memory The internal architecture of the DS80C390 requires that the device be in one of the two 22 bit addressing modes when the CMA bit is set to correctly utilize the twenty third bit and access the CAN MOVX memory A special lockout feature prevents the accidental software corruption of the control status and mask registers while a CAN operation is in progress Each CAN processor utilizes a total of 15 message centers Each message center is composed of four specific areas These include 1 Four arbitration registers COMxARO 3 CIMxARO 3 which store either the 11 bit or 29 bit arbitration value These registers are located in the MOVX memory map 2 A Format Register COMxF and 1 which informs the CAN processor as to the direction transmit or receive the number of data bytes in the message the Identification Format standard or extended and the optional use of the Identification Mask or Media Mask during message evaluation This register is located in the MOVX memory map 3 Eight data bytes for s
51. l by this amount Next the address is held on the bus for one additional machine cycle increasing the address hold time by this amount The WR and RD signals are then lengthened by a machine cycle Finally during a MOVX write the data is held on the bus for one additional machine cycle thereby increasing the data hold time by this amount For every Stretch value greater than 4 the setup and hold times remain constant and only the width of the read or write signal is increased These three gradations are reflected in the AC Electrical characteristics where the eight MOVX timing specifications are represented by only three timing diagrams 14 of 58 110199 DS80C390 The reset default of one Stretch cycle results in a three cycle MOVX for any external access Therefore the default off chip RAM access is not at full speed This is a convenience to existing designs that utilize slower RAM When maximum speed is desired software should select a Stretch value of zero When using very slow RAM or peripherals the application software can select a larger Stretch value The specific timing of MOVX instructions as a function of Stretch settings is provided in the Electrical Specifications section of this data sheet As an example Table 8 shows the read and write strobe widths corresponding to each Stretch value DATA MEMORY CYCLE STRETCH VALUES Table 8 MD2 MD1 MD0 Stretch MOVX RD WR Pulse Width in oscillator clocks Cycle Machine Count Cycle
52. ld also generates an optional early warning Power fail Interrupt PFI When enabled by software the processor will vector to ROM address 0033h if Vcc drops below has the highest priority The PFI enable is in the Watchdog Control SFR EPFI WDCON 5 Setting this bit to logic 1 will enable the PFI Application software can also read the PFI flag at WDCON 4 A PFI condition sets this bit to a 1 The flag is independent of the interrupt enable and must be cleared by software 23 of 58 110199 DS80C390 EXTERNAL RESET PINS The DS80C390 has both reset input RST and reset output RSTOL pins The RSTOL pin supplies an active low Reset when the microprocessor is issued a Reset from either a high on the RST pin a time out of the watchdog timer a crystal oscillator fail or an internally detected power fail The timing of the RSTOL pin is dependent on the source of the reset Reset Type Source 65536 tcc as described in Power Cycle Timing Characteristics lt 1 25 machine cycles 65536 as described in Power Cycle Timing Characteristics Watchdog timer reset 2 machine cycles Oscillator fail detect 65536 as described in Power Cycle Timing Characteristics INTERRUPTS The microcontroller provides 16 interrupt sources with three priority levels All interrupts with the exception of the Power Fail interrupt are controlled by a series combination of individual enable bits and a global interrupt enable
53. lock that supports an IRDA interface The device provides dual data pointers with increment decrement features to speed block data memory moves It also can adjust the speed of MOVX data memory access from two to twelve machine cycles for flexibility in addressing external memory and peripherals The device incorporates a 4kB SRAM which can be configured as various combinations of MOVX memory program memory and optional stack memory A 22 bit program counter supports access to a maximum of 4 MB of external program memory and 4 MB of external data memory A 10 bit stack pointer addresses up to 1 of MOVX memory for increased code efficiency A new Power Management Mode PMM is useful for portable or power conscious applications This feature allows software to switch from the standard machine cycle rate of 4 clocks per cycle to 1024 clocks per cycle For example at 12 MHz standard operation has a machine cycle rate of 3 MHz In Power Management Mode at the same external clock speed software can select 11 7 kHz machine cycle rate There is a corresponding reduction in power consumption when the processor runs slower The EMI reduction feature allows software to select a reduced electromagnetic interference EMI mode by disabling the ALE signal when it is unneeded The device also incorporates active current control on the address and data buses reducing EMI by minimizing transients when interfacing to external circuitry ORDERING INFORMATION
54. of time may affect reliability DC ELECTRICAL CHARACTERISTICS Supply Voltage VnsT Power Fall Waning Ymw 425 33 as Min Operating Voltage Ver 40 4 13 4 25 _ Suppl Current Active Mode Spy Geen We Supply Current Stop Mode Isror LI SS Supply Current Stop Mode IspBG Band gap enabled nput Low Level d VoL Output Low Voltage for Port 0 2 1 2 4 3 RD WR RSTOL PSEN and ALE Io 23 2 mA Output High Voltage for Port Voui 1 3 4 5 50 WA Output High Voltage for Port 1 3 4 5 1 5 Output High Voltage for Port 0 1 2 4 3 RSTOL PSEN RD WR and ALE 2 8 mA Input Low Current for Port 1 3 4 5 0 45 Logic 1 to 0 Transition Current for Port 1 3 4 5 Input Leakage Current for Port wt 300 0 input mode only RST Pulldown Resistance Rer 50 32 of 58 110199 DS80C390 NOTES FOR DC ELECTRICAL CHARACTERISTICS 1 Active current measured with 40 MHz clock source on XTALI Vcc RST 5 5 V all other pins disconnected Idle mode current measured with 40 MHz clock source on XTALI 5 5 V RST EA all other pins disconnected Stop mode current measured with XTALI RST FA Vss 5 5 V all other pins disconnected This value is not guaranteed Users who are sensitive to this specification sho
55. ompatibility with the 8051 instruction set but adds one machine cycle to the ACALL LCALL RET and RETI instructions with respect to the Dallas Semiconductor High Speed Microcontroller family timing This is transparent to standard 8051 compilers Interrupt latency is also increased by one machine cycle In this mode interrupt vectors are fetched from 0000xxh 22 bit contiguous address mode The 22 bit contiguous addressing mode uses a full 22 bit program counter and all modified branching instructions automatically save and restore the entire program counter The 22 bit branching instructions such as ACALL AJMP LCALL LJMP MOV DPTR RET and RETI instructions require an assembler compiler and linker that specifically supports these features The INC DPTR is lengthened by one cycle but remains byte count compatible with the standard 8051 instruction set Internally the device uses a 22 bit program counter The lowest order 22 bits are used for memory addressing with a special 23 bit used to map 4KB SRAM above the 4 MB memory space in bootstrap loader applications Address bits 16 23 for the 22 bit addressing modes are generated via additional SFRs dependent on the type of instruction as shown below EXTENDED ADDRESS GENERATION Table 2 po Address bits 23 16 Address bits 15 8 Address bits 7 0 instructions using DPTR DPX 93h DPH 83h DPL 82h MOVX instructions using DPTRI DPX1 95h DPH1 85h e 84h instructions
56. or automatic Switchback to standard speed divide by 4 operation The Switchback feature is enabled by setting the SFR bit SWB PMR 5 to a 1 Once it is enabled and when PMM is selected two possible events can cause an automatic Switchback to divide by four mode First if an interrupt occurs and is acknowledged the system clock will revert from PMM to divide by four mode For example if INTO is enabled and the CPU is not servicing a higher priority interrupt then Switchback will occur on INTO However if INTO is not enabled or the CPU is servicing a higher priority interrupt then activity on INTO will not cause Switchback to occur A Switchback can also occur when an enabled UART detects the start bit indicating the beginning of an incoming serial character or when the SBUF register is loaded initiating a serial transmission Note that a serial character s start bit does not generate an interrupt The interrupt occurs only on reception of a complete serial word The automatic Switchback on detection of a start bit allows timer hardware to return to divide by 4 operation and the correct baud rate in time for a proper serial reception or transmission So with Switchback enabled and a serial port enabled the automatic switch to divide by 4 operation occurs in time to receive or transmit a complete serial character as if nothing special had happened STATUS The Status register STATUS C5h provides information about interrupt and serial por
57. r high level math operations The accumulator can be accessed any time the Multiply Accumulate Status Flag MCNT1 D2h is cleared The accumulator is initialized by performing five writes to the Multiplier C Register MC D5h LSB first The 40 bit accumulator can be read by performing five reads of the Multiplier C Register MSB first 11 of 58 110199 DS80C390 MEMORY ADDRESSING The DS80C390 incorporates three internal memory areas 256 bytes of scratchpad or direct RAM 4 of SRAM configurable as various combinations of MOVX data memory stack memory MOVC program memory 512 bytes of RAM reserved for the CAN message centers Up to 4 MB of external memory is addressed via a multiplexed or demultiplexed 20 bit address bus 8 bit data bus and four chip enable active during program memory access or four peripheral enable active during data memory access signals Three different addressing modes are supported as selected by the AM1 AMO bits in the ACON SFR 16 bit address mode 16 bit address mode accesses memory similarly to the traditional 8051 It is opcode compatible with the 8051 microprocessor and identical to the byte and cycle count of the Dallas Semiconductor High Speed Microcontroller family A device operating in this mode can access up to 64 KB of program and data memory The device defaults to this mode following any reset 22 bit paged address mode The 22 bit paged address mode retains binary code c
58. red further arbitration can be performed by comparing the first two bytes of the data field in each message against two 8 bit Media Arbitration register bytes The MDME bit in the CAN Message Center Format Registers COMxF 0 CIMxF 0 either disables MDME 0 arbitration or enables MDME 1 arbitration using the Media ID Mask Registers 0 1 If the 11 bit or 29 bit arbitration and the optional Media Byte arbitration are successful the message is loaded into the respective message center The Format Register also allows the microcontroller to program each message center to function in a receive or transmit mode via the T bit and to use from 0 to 8 data bytes within the data field of a message Note that Message Center 15 can only be used in a receive mode To avoid a priority inversion the DS80C390 CAN processors are configured to reload the transmit buffer with the message of the highest priority lowest message center number whenever an arbitration is lost or an error condition occurs ARBITRATION MASKING FEATURE SUMMARY Table 13 Message Center Arbitration Registers 0 1 Located in each Message Center MOVX memory Standard 11 bit arbitration CAN 2 0A Message Center Arbitration Registers 0 3 Located in each Message Center MOVX memory Extended 29 bit arbitration CAN 2 0B Media Arbitration Registers 0 3 Located in each CAN Control Status Mask Register bank MOVX Media byte arbitration Standard Global Mask
59. retrieve the quotient LSB Read MB to retrieve the remainder MSB Read MB to retrieve the remainder LSB Not performed for 16 bit numerator Shift Right Left Load MA with data LSB Load MA with data LSB 1 Load MA with data LSB 2 Load MA with data MSB Configure MCNTO register as required Poll the MST bit until cleared 9 machine cycles Read MA for result MSB Read MA for result LSB 2 Read MA for result LSB 1 Read MA for result LSB 40 BIT ACCUMULATOR Load MB with multiplier LSB Load MB with multiplier MSB Load MA with multiplicand LSB Load MA with multiplicand MSB Poll the MST bit until cleared 6 machine cycles Read MA for product MSB Read MA for product LSB 2 Read MA for product LSB 1 Read MA for product LSB Load MA with data LSB Load with data LSB 1 Load MA with data LSB 2 Load MA with data MSB Configure MCNTO register as required Poll the MST bit until cleared 9 machine cycles Read MA for mantissa MSB Read MA for mantissa LSB 2 Read MA for mantissa LSB 1 Read MA for mantissa LSB Read MCNT0 4 MCNTO0 0 for exponent The accelerator also incorporates an automatic accumulator function permitting the implementation of multiply and accumulate and divide and accumulate functions without any additional delay Each time the accelerator is used for a multiply or divide operation the result is transparently added to a 40 bit accumulator This can greatly increase speed of DSP and othe
60. rogrammable in either transmit or receive modes with the fifteenth designated as a FIFO buffered receive only message center to help prevent data overruns All message centers support two separate 8 bit media masks and media arbitration fields for incoming message verification This feature supports the use of higher level protocols which make use of the first and or second byte of data as a part of the acceptance layer for storing incoming messages Each message center can also be programmed independently to test incoming data with or without the use of the global masks Global controls and status registers in each CAN unit allow the microcontroller to evaluate error messages generate interrupts locate and validate new data establish the CAN Bus timing establish identification mask bits and verify the source of individual messages Each message center is individually equipped with the necessary status and control bits to establish direction identification mode standard or extended data field size data status automatic remote frame request and acknowledgment and perform masked or non masked identification acceptance testing COMMUNICATING WITH THE CAN MODULE The microcontroller interface to the CAN modules is divided into two groups of registers All of the global CAN status and control bits as well as the individual message center control status registers are located in the Special Function Register map The remaining registers associated w
61. rops because memory is not being accessed and instructions are not being executed Since clocks are running the Idle power consumption is a function of crystal frequency It should be approximately 1 2 of the operational power at a given frequency The CPU can exit Idle mode with any interrupt or a reset Because Power Management Mode PMM consumes less power than Idle mode as well as leaving timers and CPU operating Idle mode is no longer recommended for new designs and is included for backward software compatibility only STOP MODE Setting the STOP bit of the Power Control register PCON 1 invokes Stop mode Stop mode is the lowest power state besides power off since it turns off all internal clocking The Icc of a standard Stop mode is approximately 1 LA consult the Electrical Specifications section for full details All processor operation ceases at the end of the instruction that sets the STOP bit The CPU can exit Stop mode via an external interrupt if enabled or a reset condition Internally generated interrupts timer serial port watchdog cannot cause an exit from Stop mode because internal clocks are not active in Stop mode BAND GAP SELECT The DS80C390 provides two enhancements to Stop mode As described below the device provides a band gap reference to determine Power fail Interrupt and Reset thresholds The band gap reference is controlled by the Band Gap Select bit BGS RCON 0 Setting BGS to a 1 will keep the band gap r
62. rrupt and or reset the microcontroller if allowed to reach a preselected time out It can be restarted by software A typical application uses the watchdog timer as a reset source to prevent software from losing control The watchdog timer is initialized selecting the time out period and enabling the reset and or interrupt functions After enabling the reset function software must then restart the timer before its expiration or hardware will reset the CPU In this way if the code execution goes awry and software does not reset the watchdog as scheduled the processor is put in a known good state reset Software can select one of four time out values as controlled by the WD1 and WDO bits Time out values are precise since they are a function of the crystal frequency When the Watchdog times out it sets the Watchdog Timer Reset Flag WTRF WDCON 2 which generates a reset if enabled by the Enable Watchdog Timer Reset EWT WDCON 1 bit Both the Enable Watchdog Timer Reset and the Reset Watchdog Timer control bits are protected by Timed Access circuitry This prevents errant software from accidentally clearing or disabling the Watchdog The Watchdog interrupt is useful for systems that do not require a reset circuit It will set the WDIF Watchdog interrupt flag 512 clocks before setting the reset flag Software can optionally enable this interrupt source which is independent of the watchdog reset function The interrupt is common used 22 of 58 1101
63. s 2 1 4 2 0 4 2 IX CD1 0 00 CD1 0 00 CD1 0 10 CD1 0 11 ee eee 2 tcLcL 4 4096 tcr cr oppo ea taa Staa 3 6 12 12288 on ON CP 00 20480 12 24 24576 SS Sa Dosen omes internal MOVX operations execute at the 0 Stretch setting Default Stretch setting for external MOVX operations following reset EXTENDED STACK POINTER The DS80C390 supports both the traditional 8 bit and an extended 10 bit stack pointer that improves the performance of large programs written in high level languages such as C The 10 bit stack pointer feature is enabled by setting the Stack Address Mode bit SA ACON 2 The bit is cleared following a reset forcing the device to use an 8 bit stack located in the Scratchpad RAM area When the SA bit is set the device will address up to 1kB of stack memory in the first IKB of the internal MOVX memory The 10 bit stack pointer address is generated by concatenating the lower two bits of the Extended Stack Pointer ESP 9Bh and the traditional 8051 Stack Pointer SP 81h The 10 bit stack pointer cannot be enabled when the 4 of SRAM is mapped as both program and data memory 15 of 58 110199 DS80C390 ENHANCED DUAL DATA POINTERS The DS80C390 contains
64. speed to significantly reduce power consumption below even Idle mode The DS80C390 also features several enhancements to Stop mode that make this extremely low power mode more useful Each of these features is discussed in detail below SYSTEM CLOCK CONTROL As mentioned previously the microcontroller contains special clock control circuitry that simultaneously provides maximum timing flexibility and maximum availability and economy in crystal selection The logical operation of the system clock divide control function is shown in Figure 2 A 3 1 multiplexer controlled by PMR 7 6 selects one of three sources for the internal system clock Crystal oscillator or external clock source Crystal oscillator or external clock source divided by 256 Crystal oscillator or external clock source frequency multiplied by 2 or 4 times SYSTEM CLOCK CONTROL DIAGRAM Figure 2 MACHINE SYSTEM CYCLE FROM CLOCK LOCK CRYSTAL ed n OSCILLATOR EXTERNAL TAT STATE CLOCK SOURCE GENERATION DIVIDE BY 4 FREQUENCY MULTIPLIER CTM AXI2X CD1 CDO The system clock control circuitry generates two clock signals that are used by the microcontroller The internal system clock provides the timebase for timers and internal peripherals The system clock is run through a divide by 4 circuit to generate the machine cycle clock that provides the timebase for CPU operations All instructions execute in one to five machine cycles
65. t DPTRO oO X 1 InremntDPTRI Another useful feature of the device is its ability to automatically switch the active data pointer after a DPTR based instruction is executed This feature can greatly reduce the software overhead associated with data memory block moves which toggle between the source and destination registers When the Toggle Select bit TSL DPS 5 is set to 1 the SEL bit DPS 0 is automatically toggled every time one of the following DPTR related instructions is executed INC DPTR MOV DPTR datal6 MOVC A A DPTR MOVX A DPTR MOVX DPTR A As a brief example if TSL is set to 1 then both data pointers can be updated with two INC DPTR instructions Assume that SEL 0 making DPTR the active data pointer The first INC DPTR increments DPTR and toggles SEL to 1 The second instruction increments DPTR1 and toggles SEL back to 0 INC DPTR INC DPTR CLOCK CONTROL AND POWER MANAGEMENT The DS80C390 includes a number of unique features that allow flexibility in selecting system clock sources and operating frequencies To support the use of inexpensive crystals while allowing full speed operation a clock multiplier is included in the processor s clock circuit Also in addition to the standard 16 of 58 110199 DS80C390 80C32 Idle and power down Stop modes the DS80C390 provides a new Power Management Mode This mode allows the processor to continue instruction execution yet at a very low
66. t activity to assist in determining if it is possible to enter PMM The microprocessor supports three levels of interrupt priority Power fail High and Low The PIP Power fail Priority Interrupt Status STATUS 7 HIP High Priority Interrupt Status STATUS 6 and LIP Low Priority Interrupt Status STATUS 5 status bits when set to a logic one indicate the corresponding level is in service 19 of 58 110199 DS80C390 Software should not rely on a lower priority level interrupt source to remove PMM Switchback when a higher level is in service Check the current priority service level before entering PMM If the current service level locks out a desired Switchback source then it would be advisable to wait until this condition clears before entering PMM Alternately software can prevent an undesired exit from PMM by intentionally entering a low priority interrupt service level before entering PMM This will prevent other low priority interrupts from causing a Switchback Entering PMM during an ongoing serial port transmission or reception can corrupt the serial port activity To prevent this a hardware lockout feature ignores changes to the clock divisor bits while the serial ports are active Serial port activity can be monitored via the Serial Port Activity bits located in the Status register IDLE MODE Setting the IDLE bit PCON 0 invokes the Idle mode Idle will leave internal clocks serial ports and timers running Power consumption d
67. t condition of Port 0 pins is high No pullup resistors are needed 4 of 58 110199 13 14 15 16 19 20 21 1 0 1 7 A8 2 0 9 2 1 A10 2 2 A11 P2 3 12 2 4 A13 P2 5 14 P2 6 15 P2 7 P3 0 P3 7 DS80C390 Port 1 I O Port 1 can function as an 8 bit bi directional I O port the non multiplexed AO A7 signals when the MUX pin 1 and as an alternate interface for internal resources Setting the SPIEC bit relocates RXD1 and TXDI to Port 5 The reset condition of Port 1 is all bits at logic 1 via a weak pullup The logic 1 state also serves as an input mode since external circuits writing to the port can overdrive the weak pullup When software clears any port pin to 0 a strong pulldown is activated that remains on until either a 1 is written to the port pin or a reset occurs Writing a 1 after the port has been at O will activate a strong transition driver followed by a weaker sustaining pullup Once the momentary strong driver turns off the port once again becomes the output and input high state Port Alternate Function P1 0 T2 External I O for Timer Counter 2 1 1 T2EX Timer Counter 2 Capture Reload Trigger P1 2 RXDI Serial Port 1 Input P1 3 TXDI Serial Port 1 Output P1 4 INT2 External Interrupt 2 Pos Edge Detect P1 5 External Interrupt 3 Neg Edge Detect P1 6 INT4 External Interrupt 4 Pos Edge Detect P1 7 5 External Interrupt 5 Neg Edge Detect A15 A8 Port
68. to P5 3 P5 2 as described in the User s Guide The reset condition of Port 1 is all bits at logic 1 via a weak pullup The logic 1 state also serves as an input mode since external circuits writing to the port can overdrive the weak pullup When software clears any port pin to 0 the device activates a strong pulldown that remains on until either a 1 is written to the port pin or a reset occurs Writing a after the port has been at 0 will activate a strong transition driver followed by a weaker sustaining pullup Once the momentary strong driver turns off the port once again becomes the output and input high state Port Alternate Function P5 0 COTX CANO Transmit Output P5 1 CORX CANO Receive Input P5 2 CANI Receive Input optional RXD1 P5 3 CITX CANI Transmit Output optional TXD1 P5 4 PCEO Peripheral Chip Enable 0 P5 5 PCEI Peripheral Chip Enable 1 5 6 2 Peripheral Chip Enable 2 5 7 Peripheral Chip Enable 3 9 26 NC Reserved These pins are reserved for use with future 43 60 devices in this family and should not be connected 6 of 58 110199 DS80C390 80C32 COMPATIBILITY The DS80C390 is a CMOS 80C32 compatible microcontroller designed for high performance Every effort has been made to keep the core device familiar to 80C32 users while adding many new features Because the device runs the standard 8051 instruction set in general software written for existing 80C32 based systems will
69. torage of 0 8 bytes of data COMxDO 7 and CIMXxDO 7 are located in the MOVX memory map 4 Message Control Registers COMxC and are located in the SFR memory for fast access 25 of 58 110199 DS80C390 Each of the message centers is identical with the exception of message center 15 Message center 15 has been designed as a receive only center and is also buffered through the use of a two message FIFO to help prevent message loss in a message overrun situation The receipt of a third message before either of the first two are read will overwrite the second message leaving the first message undisturbed Modification of the CAN registers located in MOVX memory is protected via the SWINT bits with one bit protecting each respective CAN module Consult the description of this bit in the User s Guide for more information Each CAN Module contains a block of Control Status Mask registers 14 functionally identical message centers plus a fifteenth message center which is receive only and incorporates a buffered FIFO The following tables describe the organization of the message centers located in MOVX space MOVX MESSAGE CENTERS FOR CAN 0 CAN 0 CONTROL STATUS MASK REGISTERS MOVX Data Register 7 5 3 2 1 Address COMIDO MIDO7 MID06 MIDOS MID04 MIDO3 MIDO2 MIDOI MIDOO xxxx00h MIAAT7 MIAA6 MIAAS MIAA4 M1AA3 MIAA2 1 1 MIAAO xxxx03h 1028 1D27 1026 mos mos mo2 1021
70. trol bits Note that the change will affect all aspects of system operation including timers and baud rates The use of the switchback feature described later can eliminate many of the problems associated with the Power Management Mode Changing the system clock machine cycle clock frequency The microcontroller incorporates a special locking sequence to ensure glitch free switching of the internal clock signals All changes to the CD1 CDO bits must pass through the 10 divide by four state For example to change from 00 frequency multiplier to 11 PMM the software must change the bits in the following sequence 00 gt 10 gt 11 Attempts to switch between invalid states will fail leaving the CDI bits unchanged The following sequence must be followed when switching to the frequency multiplier as the internal time source This sequence can only be performed when the device is in divide by four operation The steps must be followed in this order although it is possible to have other instructions between them Any deviation from this order will cause the CD1 CDO bits to remain unchanged Switching from frequency multiplier to non multiplier mode requires no steps other than the changing of the CD1 CDO bits Ensure that CD1 bits set to 10 and the EXIF 2 bit 0 Clear the CTM Crystal Multiplier Enable bit Set the 4X 2X bit to the appropriate state Set the CTM Crystal Multiplier Enable bit
71. uld contact Dallas Semiconductor for more information When these pins are used to address external memory or as CAN interface signals This measurement reflects the port during a 0 to 1 transition in I O mode During this period a one shot circuit drives the ports hard for two clock cycles Port 3 pins 3 6 and 3 7 will have a stronger than normal pullup drive for one oscillator period following the transition of either the RD or WR from 0 to 1 transition This is the current required from an external circuit to hold a logic low level on an I O pin while the corresponding port latch bit is set to 1 This is only the current required to hold the low level transitions from 1 to 0 on an I O pin will also have to overcome the transition current Ports 1 in I O mode 3 4 and 5 source transition current when being pulled down externally It reaches its maximum at approximately 2V During the external addressing mode weak latches maintain the previously driven value from the processor on Port 0 until such time that Port 0 is driven by external memory source and on Port 1 2 4 for one XTAL 1 cycle prior to change in output address from Port 1 2 and 4 10 RST This condition mimics operation of pins in I O mode TYPICAL lcc VERSUS FREQUENCY 35 loc 30 mA 25 02 4 12 33 40 MHz XTAL FREQUENCY 33 of 58 110199 DS80C390 AC ELECTRICAL CHARACTERISTICS Multiplexed address data bus PARAMETER SYMBOL MIN MIN
72. work on the DS80C390 The primary exceptions are related to timing critical issues since the high performance core of the microcontroller executes instructions much faster than the original Memory interfacing is performed identically to the standard 80C32 The high speed nature of the DS80C390 core will slightly change the interface timing and designers are advised to consult the timing diagrams in this data sheet for more information The DS80C390 provides the same timer counter resources full duplex serial port 256 bytes of scratchpad RAM and I O ports as the standard 80C32 Timers will default to a 12 clocks per machine cycle operation to keep timing compatible with original 8051 systems but can be programmed to run at the faster 4 clocks per machine cycle if desired New hardware functions are accessed using Special Function Registers that do not overlap with standard 80C32 locations This data sheet provides only a summary and overview of the DS80C390 Detailed descriptions are available in the corresponding user s guide This data sheet assumes a familiarity with the architecture of the standard 80C32 In addition to the basic features of that device the DS80C390 incorporates many new features PERFORMANCE OVERVIEW The DS80C390 s higher performance comes not just from increasing the clock frequency but from a more efficient design This updated core removes the dummy memory cycles that are present in a standard 12 clocks per machine cycl
73. xxxx06h COSGMI IDO IDI9 Wis 0 O O xxxx07h COEGMO ID28 ID27 1026 1025 ID24 023 1022 10021 xxxx08h COEGM2 IDI2 IDIO 19 ws ID7 We Ws xxxx0Ah 1 COEGMG 104 103 102 ID IDO 0 xxxxOBh 0 0 COMISMI ID20 IDI9 wis 1016 1015 D14 IDI3 xxxxODh COMISM2 IDI2 IDIO 19 ID8 ID7 We Ws xxxxOEh COMISM3 4 I2 wi mo o o O xxxxOFh CAN 0 MESSAGE CENTER 1 Reserved Sef COMIAR3 CAN 0 MESSAGE 1 ARBITRATION REGISTER 3 WTOE COMIF DDTBYC3DTBYC2DTBYCI DTBYCO MEME MDME COMIDO 7 CAN 0 MESSAGE 1 DATA BYTES 0 7 xxxx17h 1Eh ooo 26 of 58 110199 DS80C390 CAN 0 MESSAGE CENTERS 2 14 MESSAGE CENTER 2 REGISTERS similar to Message Center 1 xxxx20h 2Fh MESSAGE CENTER 3 REGISTERS similar to Message Center 1 xxxx30h 3Fh MESSAGE CENTER 4 REGISTERS similar to Message Center 1 xxxx40h 4Fh MESSAGE CENTER 5 REGISTERS similar to Message Center 1 xxxx50h 5Fh MESSAGE CENTER 6 REGISTERS similar to Message Center 1 Xxxx60h 6Fh MESSAGE CENTER 7 REGISTERS similar to Message Center I 70 7Fh MESSAGE CENTER 8 REGISTERS similar to Message Center 1 xxxx80Oh 8Fh MESSAGE CENTER 9 REGISTERS similar to Message Center 1 xxxx90h MESSAGE CENTER 10 REGISTERS similar to Message Center 1 xxxxAOh MESSAGE CENTE
74. y change needed to access the new function The DS80C390 duplicates the SFRs contained in the standard 80C52 Table 2 shows the register addresses and bit locations Many are standard 80C52 registers The user s guide contains a full description of all SFRs SPECIAL FUNCTION REGISTER LOCATION Table 2 4 SP CKCON WDO T TIM TOM M MDI MDO 8 2M D2 Eh PACNT SBCAN P4CNT 5 PACNT 4 3 PACNT 2 PACNTO 9 9Ch ACON 028 ie ee ee EE P5 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 Alh 8 of 58 110199 DS80C390 COIR INTIN7 INTIN6 INTINS INTIN4 INTIN3 INTIN2 INTIN1 INTINO ASh IE EA ESO LSADDRO ui pec EAS SARI et tA COMI2C MSRDY INTRQ EXTRQ MTRQ ROW TIH DTUP COMISE INTRO EXTRO MTRO rowr DTUP Bo COME MSRDY ERI INTRO EXTRO MTRO ROWMIM DTUP COMISC AE ETI INTRQ EXTRQ MTRQ DTUP BFh SCONI SMO FE 1 5 1 5 2 1 TB amp 1 RBS 1 RII hk mer pxex mew mr om _ 1312 0g zum ae ee V E I RCAP2H PSW AC Rs Rso F j

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