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Analog Devices AD9912 User's Manual

1. 100 RMS JITTER 100Hz TO 100MHz 600MHz 585fs 800MHz 406fs 110 2 z 120 E j 130 lt ui a 5 140 150 2 2 100 1k 10k 100k 1M 10M 100M 3 250 375 500 625 750 875 1000 3 FREQUENCY OFFSET Hz SYSTEM CLOCK FREQUENCY MHz Figure 15 Absolute Phase Noise Using HSTL Driver Figure 18 Power Dissipation vs System Clock Frequency SYSCLK 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed SYSCLK PLL Bypassed four 5 Driver On CMOS Driver HSTL Output Doubler Enabled 5 Off 110 RMS JITTER 100Hz TO 20MHz 150MHz 308fs 50MHz 7375 120 D z 2 3 130 2 D u 140 TOTAL 2 ia 3 3V 150MHz 5 150 50MHz 10MHz 160 e 2 100 1k 10k 100k 1M 10M 100M 3 0 100 200 300 400 5 FREQUENCY OFFSET Hz OUTPUT FREQUENCY MHz 3 Figure 16 Absolute Phase Noise Using CMOS Driver at 3 3 V Figure 19 Power Dissipation vs Output Frequency SYSCLK 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed SYSCLK 1 GHz SYSCLK PLL Bypassed HSTL Driver On DDS Run at 200 MSPS for 10 M
2. Table 12 Addr Default Hex Type Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Serial port configuration and part identification 0x0000 Serial SDO LSB first Soft Long Long Soft reset LSB first SDO 0x18 config active buffered reset instruction instruction buffered active 0x0001 Reserved 0x00 0x0002 RO Part ID Part ID 0x02 0x0003 RO 0x09 0x0004 Serial Read buffer 0 00 options register 0x0005 AC Register 0x00 update Power down and reset 0x0010 Power PD HSTL Enable Enable PD Full PD Digital PD 0xC0 or down and driver CMOS output SYSCLK OxDO enable driver doubler PLL 0x0011 Reserved 0x00 0x0012 M AC Reset DDS reset 0x00 0x0013 M PD fund S div 2 S divider 0x00 DDS reset reset System clock 0x0020 N divider N divider Bits 4 0 0x12 0x0021 Reserved Boris 0x0022 PLL VCO auto 2x refer VCO range Charge pump current 0x04 parameters range ence Bits 1 0 CMOS output divider S divider 0x0100 Reserved 0x30 0x0101 Reserved to 0x0103 0x0104 S divider S divider Bits 15 0 0x00 and LSB Register 0x0104 0x0105 0x0106 Falling S divider 2 0x01 edge triggered Frequency tuning word 0x01A0 Reserved 0x00 to 0x01A5 0x01A6 M FTWO FTWO Bits 47 0 0x00 Ox01A7 M frequency LSB Register 0x01A6 Ox00 tuning ao Ox01A8 M word 0x00 0 01 M 0x00 Ox01AA M Start up
3. 115 115 RMS JITTER 100Hz TO 20MHz RMS JITTER 100Hz 100MHz 83fs 50MHz 62fs 200MHz 37fs 8 400MHz 3115 5 135 135 a a kJ 145 145 2 9 4 lt 155 lt 155 a n 165 165 175 5 175 100 1k 10k 100k 1M 10M 100M 3 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET Hz FREQUENCY OFFSET Hz 3 Figure 21 Absolute Phase Noise of Unfiltered DAC Output Figure 24 Absolute Phase Noise of Unfiltered DAC Output foyr 258 3 MHz four 50 MHz 200 MHz and 400 MHz SYSCLK Driven by SYSCLK Driven by a 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed a 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed 115 115 RMS JITTER 100Hz TO 20MHz 69fs 125 125 N 135 3 135 5 145 _145 2 2 o o lt 155 lt 155 i 165 165 175 x 175 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET Hz FREQUENCY OFFSET Hz 3 Figure 22 Absolute Phase Noise of Unfiltered DAC Output foyr 63 MHz Figure 25 Absolute Phase Noise of Unfiltered DAC Output foyr 311 6 MHz SYSCLK Driven by a 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed SYSCLK Driven by a 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed 115 110 RMS JITTER 100Hz TO 40MHz 6115 RMS JITTER 100Hz TO 100MHz 2215 125 120 135 130 3 145 D 140 2 2 o o
4. sees 39 7 09 Rev to Rev C Changes to Logic Outputs Parameter Table 1 3 Changes to AVDD Pin 25 Pin 26 Pin 29 and Pin 30 25 Power Supply Partitioning sse 25 3 3 V SUpplies een eee nen ne AUTE 25 1 8 V Supplies c a e E e EE p 25 Serial Control Port ete etes 26 Serial Control Port Pin 26 Operation of Serial Control Port sss 26 The Instruction Word 16 Bits 27 MSB LSB First Transfers seen 27 TO Register a ERR 30 Register Descriptionsu u a a aa ayasa 32 Serial Port Configuration Register 0x0000 to Register 0 0005 32 Power Down and Reset Register 0 0010 to Register 0x0013 ie RES System Clock Register 0x0020 to Register 0x0022 CMOS Output Divider S Divider Register 0x0100 to Register 0x0 106 tbe cepit e petant 34 Frequency Tuning Word Register 0x01A0 to Register incenso iei tede 34 Doubler and Output Drivers Register 0x0200 to Register OKOZO Terpener 36 Calibration User Accessible Trim Register 0x0400 to Register OX0410 koninin iinne 36 Harmonic Spur Reduction Register 0x0500 to Register 0x0509 cct eR RT REUS 36 Outline Dimensions 38 Ordering Guide sss 39
5. Parameter Min Typ Max Unit Test Conditions Comments SYSTEM CLOCK INPUT System clock inputs should always be ac coupled both single ended and differential SYSCLK PLL Bypassed Input Capacitance 1 5 pF Single ended each pin Input Resistance 2 4 2 6 2 9 kQ Differential Internally Generated DC Bias Voltage 0 93 1 17 1 38 V Differential Input Voltage Swing 632 mV p p Equivalent to 316 mV swing on each leg SYSCLK PLL Enabled Input Capacitance 3 pF Single ended each pin Input Resistance 24 2 6 2 9 kQ Differential Internally Generated DC Bias Voltage 0 93 1 17 1 38 V Differential Input Voltage Swing 632 mV p p Equivalent to 316 mV swing on each leg Crystal Resonator with SYSCLK PLL Enabled Motional Resistance 9 100 Q 25 MHz 3 2 mm x 2 5 mm AT cut CLOCK OUTPUT DRIVERS HSTL Output Driver Differential Output Voltage Swing 1080 1280 1480 mV Output driver static see Figure 27 for output swing vs frequency Common Mode Output Voltage 0 7 0 88 1 06 V CMOS Output Driver Output driver static see Figure 28 and Figure 29 for output swing vs frequency Output Voltage High 2 7 V 1 mA Pin 37 3 3 V Output Voltage Low Vo 0 4 V lo 1 mA Pin 37 3 3 V Output Voltage High 1 4 V 1 mA Pin 37 1 8V Output Voltage Low Vo 0 4 V lg 1 mA Pin 37 1 8V TOTAL POWER DISSIPATION DDS Only 637 765 mW Power on default except SYSCLK PLL by passed and CMOS driver off SYSCLK 1 GHz HSTL drive
6. Use the following equation to determine the junction tempera ture on the application PCB T Tease W x PD where T is the junction temperature C case is the case temperature C measured by customer at top center of package V is the value from Table 7 PD is the power dissipation see the Total Power Dissipation section in the Specifications section Values of 9 are provided for package comparison and PCB design considerations can be used for a first order approximation of T by the equation T T 04 x PD where T is the ambient temperature Values of are provided for package comparison and PCB design considerations when an external heat sink is required Values of are provided for package comparison and PCB design considerations The values in Table 7 apply to both 64 lead package options Rev D Page 23 of 40 09912 POWER UP POWER ON RESET On initial power up the AD9912 internally generates a 75 ns RESET pulse The pulse is initiated when both of the following two conditions are met The 3 3 V supply is greater than 2 35 V 0 1 V e The 1 8 V supply is greater than 1 4 V 0 05 V Less than 1 ns after RESET goes high the S1 to S4 configuration pins go high impedance and remain high impedance until RESET is deactivated This allows strapping and configuration during RESET Because of this reset sequence external power supply sequenc ing is no
7. lt 155 lt 150 amp amp 165 160 175 170 8 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M 3 FREQUENCY OFFSET Hz FREQUENCY OFFSET Hz Figure 23 Absolute Phase Noise of Unfiltered DAC Output foyr 171 MHz Figure 26 Absolute Phase Noise of 1 GHz Reference Used for Performance SYSCLK Driven by a 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed Plots Wenzel Components Used 100 MHz Oscillator LNBA 13 24 Amp 100 5 Multiplier LNNDD 500 14 Diode Doubler Rev D Page 13 of 40 AD9912 650 AMPLITUDE mV oa a 500 NOM SKEW 25 C 1 8V SUPPLY WORST CASE SLOW SKEW 90 1 7V SUPPLY 450 0 200 400 600 FREQUENCY MHz 800 06763 021 Figure 27 HSTL Output Driver Single Ended Peak to Peak Amplitude vs Toggle Rate 100 Across Differential Pair 2 5 2 0 a AMPLITUDE V 5 0 5 NOM SKEW 25 1 8V SUPPLY 20pF WORST CASE SLOW SKEW 90 C 1 7V SUPPLY 20pF 0 10 20 30 FREQUENCY MHz 40 06763 022 Figure 28 CMOS Output Driver Peak to Peak Amplitude vs Toggle Rate AVDD3 1 8 V with 20 pF Load 3 5 E Eee ses 2 5 2 0 2 E 1 5 i NOM SKEW 25 C 1 8V SUPPLY 20pF 4 9 WORST CASE SLOW SKEW 90 3 0V SUPPLY 20pF 0 5 0 0 50 100 FREQUENCY MHz 150 06763 023 Figure 29 CMOS Output D
8. 6 09 Rev A to Rev B Changes to Figure 40 and Direct Digital Synthesizer Section 17 Changes to Figure sss 22 Charges to Table LL aient tinte et ee es 30 Changes to Table 22 and Table 23 sss 34 1 08 Rev 0 to Rev A Changes to Table Le ERI DEREN DRE 3 Changes to Table 2 25 Changes to Table 4 ed 8 Changes to Typical Performance Characteristics 10 Changes to Functional Description 19 Changes to Single Ended CMOS Output Section 21 Changes to Harmonic Spur Reduction Section 21 Changes to Power Supply Partitioning Section 25 10 07 Revision 0 Initial Version Rev D Page 2 of 40 SPECIFICATIONS AD9912 DC SPECIFICATIONS AVDD 1 8 V 596 AVDD3 3 3 V 5 DVDD 1 8 V 5 DVDD_I O 3 3 V 5 AVSS 0 V DVSS 0 V unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments SUPPLY VOLTAGE DVDD 1 O Pin 1 3 135 3 30 3 465 V DVDD Pin 3 Pin 5 Pin 7 1 71 1 80 1 89 V AVDD3 Pin 14 Pin 46 Pin 47 Pin 49 3 135 3 30 3 465 V AVDD3 Pin 37 1 71 3 30 3 465 V Pin 37 is typically 3 3 V but can be set to 1 8 V AVDD Pin 11 Pin 19 Pin 23 to Pin 26 Pin 29 171 1 80 1 89 V Pin 30 Pin 36 Pin 42 Pin 44 Pin 45 Pin 53 SUPPLY CURRENT See also the Total Power Dissipation specif
9. This DDS output signal is routed off chip where it is passed through an analog filter and brought back on chip for buffering and if necessary frequency doubling Where possible for the best jitter performance it is recommended that the frequency doubler be bypassed The 1 8 V HSTL output should be ac coupled with 100 termi nation at the destination The driver design has low jitter injection for frequencies in the range of 50 MHz to 750 MHz Refer to the AC Specifications section for the exact frequency limits 2x Frequency Multiplier The AD9912 can be configured via the I O register map with an internal 2x delay locked loop DLL multiplier at the input of the primary clock driver The extra octave of frequency gain allows the AD9912 to provide output clock frequencies that exceed the range available from the DDS alone These settings are found in Register 0x0010 and Register 0x0200 The input to the DLL consists of the filtered DDS output signal after it has been squared up by an integrated clock receiver circuit The DLL can accept input frequencies in the range of 200 MHz to 400 MHz Single Ended CMOS Output In addition to the high speed differential output clock driver the AD9912 provides an independent single ended output CMOS clock driver that is very good for frequencies up to 150 MHz The signal path for the CMOS clock driver can either include or bypass the CMOS output divider If the CMOS output divider is byp
10. cond Ox01AB M Start up cond Ox01AC M Phase DDS phase word Bits 7 0 0x00 0x01AD M DDS phase word Bits 13 8 0x00 Doubler and output drivers 0x0200 HSTL driver OPOL HSTL output doubler 0x05 polarity Bits 1 0 0x0201 CMOS driver CMOS mux 0x00 Rev D Page 30 of 40 09912 Addr Default Hex Type Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Calibration user accessible trim 0x0400 Reserved 0x00 to 0x040A 0x040B DAC full DAC full scale current Bits 7 0 OxFF 0x040C scale DAC full scale current 0x01 current Bits 9 8 0x040D Reserved 0x00 0 040 Reserved 0x10 0 040 Reserved 0x00 and 0x0410 Harmonic spur reduction 0x0500 M Spur A HSR A Amplitude Spur A harmonic Bits 3 0 0x00 enable gain x 2 0x0501 M Spur A magnitude Bits 7 0 0x00 0 0503 M Spur A phase Bits 7 0 0x00 0x0504 M Spur 0x00 phase Bit 8 0x0505 M Spur B HSR B Amplitude Spur B harmonic Bits 3 0 0x00 enable gain x 2 0x0506 M Spur B magnitude Bits 7 0 0x00 0x0508 M Spur B phase Bits 7 0 0x00 0x0509 M Spur B 0x00 phase Bit 8 1 Types of registers mirrored also called buffered This type of register needs an I O update for the new value to take effect RO read only AC autoclear Rev D Page 31 of
11. if the DAC is sampled at 1 GHz and generates an output sinusoid of 170 MHz the fifth harmonic would normally be at 850 MHz However because of the sampling process this spur appears at 150 MHz only 20 MHz away from the fundamental Therefore when attempting to reduce DAC spurs it is important to know the actual location of the harmonic spur in the DAC output spectrum based on the DAC sample rate so that its harmonic number can be reduced The mechanics of performing harmonic spur reduction is shown in Figure 48 It essentially consists of two additional DDS cores operating in parallel with the original DDS This enables the user to reduce two different harmonic spurs from the second to the 15 with nine bits of phase offset control m and eight bits of amplitude control The dynamic range of the cancellation signal is further aug mented by a gain bit associated with each channel When this bit is set the magnitude of the cancellation signal is doubled by employing a 1 bit left shift of the data However the shift operation reduces the granularity of the cancellation signal magnitude The full scale amplitude of a cancellation spur is approximately 60 dBc when the gain bit is a Logic 0 and approximately 54 dBc when the gain bit is a Logic 1 DDS PHASE i 48 BIT ACCUMULATOR i 48 BIT FREQUENCY TURNING WORD FTW SYSCLK HARMONIC FREQUENCY GENERATOR CH1 HARMONIC NUMBER O CH1 CANCELLATION PHASE OF
12. serial configuration register and then issuing an I O update Immediately after the LSB first bit is set all serial control port operations are changed to LSB first order When MSB first mode is active the instruction and data bytes must be written from MSB to LSB Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte Subsequent data bytes must follow in order from high address to low address In MSB first mode the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle When LSB first 1 LSB first the instruction and data bytes must be written from LSB to MSB Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle The AD9912 serial control port register address decrements from the register address just written toward 0x0000 for multibyte I O operations if the MSB first mode is active default If the LSB first mode is active the serial control port register address increments from the address just written toward Ox1FFF for multibyte I O operations Unused addresses are not skipped during multibyte operations The user should write the default value to
13. 40 09912 1 0 REGISTER DESCRIPTIONS SERIAL PORT CONFIGURATION REGISTER 0x0000 TO REGISTER 0x0005 Register 0x0000 Serial Port Configuration Table 13 Bits Bit Name Description 7 4 These bits are the mirror image of Bits 3 0 3 Long instruction Read only the AD9912 supports only long instructions 2 Soft reset Resets register map except for Register 0x0000 Setting this bit forces a soft reset meaning that S1 to S4 are not tristated nor is their state read when this bit is cleared The AD9912 assumes the values of S1 to S4 that were present during the last hard reset This bit is not self clearing and all other registers are restored to their default values after a soft reset 1 LSB first Sets bit order for serial port 1 LSB first 0 MSB first update must occur for the MSB first to take effect 0 SDO active Enables SDO pin 1 SDO pin enabled 4 wire serial port mode 0 3 wire mode Register 0x0001 Reserved Register 0x0002 and Register 0x0003 Part ID Read Only Register 0x0004 Serial Options Table 14 Bits Bit Name Description 0 Read buffer register For buffered registers serial port readback reads from actual active registers instead of the buffer 1 reads the buffered values that take effect during the next I O update 0 reads values that are currently in effect Register 0x0005 Serial Options Self Clearing Table 15 Bits Bit Name Desc
14. 59dBc FREQ SPAN 500MHz RESOLUTION BW 3kHz VIDEO BW 10kHz 100 200 300 400 FREQUENCY MHz Figure 8 Wideband SFDR at 398 7 MHz SYSCLK 1 GHz SYSCLK PLL Bypassed 06763 006 06763 007 06763 008 09912 80 CARRIER 20 1MHz RMS JITTER 100Hz TO 40MHz SFDR 95dBc 99MHz 41315 FREQ SPAN 500kHz 399MHz 22215 RESOLUTION BW 300Hz VIDEO BW 1kHz 100 8 5 110 kJ 120 2 m z a 5 130 399MHz 140 150 99MHz 10 g 160 19 85 19 95 20 05 20 15 20 25 20 35 5 100 1k 10k 100k 1M 10M 100M FREQUENCY MHz 3 FREQUENCY OFFSET Hz 3 Figure 9 Narrow Band SFDR at 20 1 MHz Figure 12 Absolute Phase Noise Using HSTL Driver SYSCLK 1 GHz SYSCLK PLL Bypassed SYSCLK 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed 80 CARRIER 201 1M
15. DAC Output RECONSTRUCTION FILTER The origin of the output clock signal produced by the AD9912 is the combined DDS and DAC The DAC output signal appears as a sinusoid sampled at The frequency of the sinusoid is determined by the frequency tuning word FTW that appears at the input to the DDS The DAC output is typically passed through an external reconstruction filter that serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth If desired the signal can then be brought back on chip to be converted to a square wave that is routed internally to the output clock driver or the 2x DLL multiplier Rev D Page 17 of 40 09912 MAGNITUDE dB IMAGE 0 IMAGE 1 PRIMARY SIGNAL i FILTER RESPONSE 100 BASE BAND IMAGE 2 IMAGE 3 IMAGE 4 SIN x x NVELOPE 3f 2 2f 06763 034 Figure 42 DAC Spectrum vs Reconstruction Filter Response Because the DAC constitutes a sampled system its output must be filtered so that the analog waveform accurately represents the digital samples supplied to the DAC input The unfiltered DAC output contains the typically desired baseband signal which extends from dc to the Nyquist frequency f 2 It also contains images of the baseband signal that theoretically extend to infinity Notice that the odd images shown in Figure 42 are mirror images of the baseband signal Furthermore the entire DAC output spectrum is affected by
16. V analog Applications demanding the highest performance may require additional power supply isolation Important All power supply pins must receive power regardless of whether that block is used 3 3 V SUPPLIES 1 0 Pin 1 and AVDD3 Pin 14 Although one of these pins is analog and the other is digital these two 3 3 V supplies can be grouped together The power consumption on Pin 1 varies dynamically with serial port activity AVDD3 Pin 37 This is the CMOS driver supply It can be either 1 8 V or 3 3 V and its power consumption is a function of the output frequency and loading of OUT_CMOS Pin 38 If the CMOS driver is used at 3 3 V this supply should be isolated from other 3 3 V supplies with a ferrite bead to avoid a spur at the output frequency If the HSTL driver is not used AVDD3 Pin 37 can be connected using a ferrite bead to AVDD3 Pin 46 Pin 47 and Pin 49 If the HSTL driver is used connect AVDD3 Pin 37 to Pin 1 and Pin 14 using a ferrite bead If the CMOS driver is used at 1 8 V AVDD3 Pin 37 can be connected to AVDD Pin 36 If the CMOS driver is not used AVDD3 Pin 37 can be tied directly to the 1 8 V AVDD Pin 36 and the CMOS driver powered down using Register 0x0010 AVDD3 Pin 46 Pin 47 and Pin 49 These are 3 3 V DAC power supplies that typically consume about 25 mA At a minimum a ferrite bead should be used to isolate these from other 3 3 V supplies with a separate re
17. doubles the minimum step size 5 4 Reserved Reserved 3 0 Spur A harmonic Spur A Harmonic 1 to Spur A Harmonic 15 Allows user to choose which harmonic to eliminate Register 0x0501 Spur A Continued Table 37 Bits Bit Name Description 7 0 Spur A magnitude Linear multiplier for Spur A magnitude Rev D Page 36 of 40 Register 0x0503 Spur A Continued AD9912 Table 38 Bits Bit Name Description 7 0 Spur A phase Linear offset for Sour B phase Register 0x0504 Spur A Continued Table 39 Bits Bit Name Description 8 Spur A phase Linear offset for Spur A phase Register 0x0505 Spur B Table 40 Bits Bit Name Description 7 HSR B enable Harmonic Spur Reduction B enable 6 Amplitude gain x 2 Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size 5 4 Reserved Reserved 3 0 Spur B harmonic Spur B Harmonic 1 to Spur B Harmonic 15 Allows user to choose which harmonic to eliminate Register 0x0506 Spur B Continued Table 41 Bits Bit Name Description 7 0 Spur B magnitude Linear multiplier for Spur B magnitude Register 0x0508 Spur B Continued Table 42 Bits Bit Name Description 7 0 Spur B phase Linear offset for Spur B phase Register 0x0509 Spur B Continued Table 43 Bits Bit Name Description 8 Spur B phase Linear
18. edge triggered Setting this bit inverts the reference clock before S divider 6 1 Reserved Reserved 0 S divider 2 Setting this bit enables an additional 2 prescaler See the CMOS Output Divider S Divider section If the desired S divider setting is greater than 65 536 or if the signal on FDBK_IN is greater than 400 MHz this bit must be set FREQUENCY TUNING WORD REGISTER 0x01A0 TO REGISTER 0x01AD Register 0x01A0 to Register 0x01A5 Reserved Register 0x01A6 FTWO Frequency Tuning Word Table 24 Bits Bit Name Description 7 0 FTWO These registers contain the FTW frequency tuning word for the DDS The FTW determines the ratio of the AD9912 output frequency to its DAC system clock Register 0x01A6 is the least significant byte of the FTW Note that the power up default is defined by start up Pin S1 to Pin S4 Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity Register 0x01A7 FTWO Frequency Tuning Word Continued Table 25 Bits Bit Name Description 15 8 FTWO These registers contain the FTW frequency tuning word for the DDS The FTW determines the ratio of the AD9912 output frequency to its DAC system clock Register 0x01A6 is the least significant byte of the FTW Note that the power up default is defined by start up Pin S1 to Pin S4 Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity Register 0x01A
19. external loop filter must be constructed and attached to this pin This pin should be pulled down to ground with 1 resistor when the system clock PLL is bypassed See Figure 46 for a diagram of the system clock PLL loop filter Rev D Page 8 of 40 09912 Input Pin No Output PinType Mnemonic Description 32 1 8VCMOS CLKMODESEL Clock Mode Select Set to GND when connecting a crystal to the system clock input Pin 27 and Pin 28 Pull up to 1 8 V when using either an oscillator or an external clock source This pin can be left unconnected when the system clock PLL is bypassed See the SYSCLK Inputs section for details on the use of this pin 33 39 43 52 GND AVSS Analog Ground Connect to ground 34 1 8V HSTL OUTB Complementary HSTL Output See the Specifications and Primary 1 8 V Differential HSTL Driver sections for details 35 1 8V HSTL OUT HSTL Output See the Specifications and Primary 1 8 V Differential HSTL Driver sections for details 37 Power AVDD3 Analog Supply for CMOS Output Driver This pin is normally 3 3 V but can be 1 8V This pin should be powered even if the CMOS driver is not used See the Power Supply Partitioning section for power supply partitioning 38 3 3V CMOS OUT_CMOS CMOS Output See the Specifications section and the Output Clock Drivers and 2x Frequency Multiplier section This pin is 1 8 V CMOS if Pin 37 is set to 1 8 V 40 Differential FDBK INB Complementary Fee
20. falling edges of this regenerated signal The impetus for doubling the frequency at the input of the SYSCLK PLL multiplier is that an improvement in overall phase noise performance can be realized The main drawback is that the doubler output is not a rectangular pulse with a constant duty cycle even for a perfectly symmetric SYSCLK input signal This results in a subharmonic appearing at the same frequency as the SYSCLK input signal and the magnitude of the subharmonic can be quite large When employing the doubler care must be taken to ensure that the loop bandwidth of the SYSCLK PLL multiplier adequately suppresses the subharmonic The benefit offered by the doubler depends on the magnitude of the subharmonic the loop bandwidth of the SYSCLK PLL multiplier and the overall phase noise requirements of the specific application In many applications the AD9912 clock output is applied to the input of another PLL and the subhar monic is often suppressed by the relatively narrow bandwidth of the downstream PLL Note that generally the benefits of the SYSCLK PLL doubler are realized for SYSCLK input frequencies of 25 MHz and above BIPOLAR EDGE DETECTOR REGISTER 2 SAMPLE CLOCK BIPOLAR EDGE 06763 036 LOOP FILTER Figure 44 System Clock Generator Block Diagram Rev D Page 19 of 40 09912 SYSCLK PLL Multiplier When the SYSCLK PLL multiplier path is employed the frequency applied
21. if not used 60 3 3V CMOS IO UPDATE Update A logic transition from 0 to 1 on this pin transfers data from the port registers to the control registers see the Write section This pin has an internal 50 kO pull down resistor 61 3 3V CMOS CSB Chip Select Active low When programming a device this pin must be held low In systems where more than one AD9912 is present this pin enables individual programming of each AD9912 This pin has an internal 100 pull up resistor 62 O 3 3 V CMOS SDO Serial Data Output When the device is in 3 wire mode data is read on this pin There is no internal pull up pull down resistor on this pin 63 1 0 3 3VCMOS SDIO Serial Data Input Output When the device is in 3 wire mode data is written via this pin In 2 wire mode data reads and writes both occur on this pin There is no internal pull up pull down resistor on this pin 64 3 3VCMOS_ SCLK Serial Programming Clock Data clock for serial programming This pin has an internal 50 pull down resistor Exposed Die Pad O GND EPAD Analog Ground The exposed die pad on the bottom of the package provides the analog ground for the part this exposed pad must be connected to ground for proper operation Rev D Page 9 of 40 09912 TYPICAL PERFORMANCE CHARACTERISTICS AVDD AVDD3 DVDD at nominal supply voltage DAC Ry 10 unless otherwise noted See Figure 26 for 1 GHz reference phase noise used for
22. instruction word defines whether the upcoming data transfer is a read or a write the number of bytes in the data transfer and the starting register address for the first byte of the data transfer Write If the instruction word is for a write operation I15 0 the second part is the transfer of data into the serial control port buffer of the AD9912 The length of the transfer 1 2 or 3 bytes or streaming mode is indicated by two bits W1 W0 in the instruction byte The length of the transfer indicated by W1 W0 does not include the 2 byte instruction CSB can be raised after each sequence of eight bits to stall the bus except after the last byte where it ends the cycle When the bus is stalled the serial transfer resumes when CSB is lowered Stalling on nonbyte boundaries resets the serial control port There are three types of registers on the AD9912 buffered live and read only Buffered also referred to as mirrored registers require an I O update to transfer the new values from a temporary buffer on the chip to the actual register and are marked with an M in the Type column of the register map Toggling the IO UPDATE pin or writing a 1 to the register update bit Register 0x0005 Bit 0 causes the update to occur Because any number of bytes of data can be changed before issuing an update command the update simultaneously enables all register changes that have occurred since any previous update Live registers do not re
23. offset for Spur B phase Rev D Page 37 of 40 09912 OUTLINE DIMENSIONS INDICATOR TOP VIEW 8 75 BSC SQ PIN 1 INDICATOR EXPOSED PAD BOTTOM VIEW I 4 85 7 4 55 gt e SQ 100 12 000 0 85 0 65 FOR PROPER CONNECTION OF pw D THE EXPOSED PAD REFER 0 02 THE PIN CONFIGURATION AND L4 FUNCTION DESCRIPTIONS SEATING gt 0 50 Bsc a SECTION OF THIS DATA SHEET COMPLIANT TO JEDEC STANDARDS MO 220 VMMD 4 EXCEPT FOR EXPOSED PAD DIMENSION Figure 57 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 9 mm x 9 mm Body Very Thin Quad CP 64 1 Dimensions shown in millimeters 9 10 9 00 SQ 0 60 MAX 8 90 1 INDICATOR PIN1 INDICATOR 8 85 5 36 8 75 SQ 5 21 SQ 8 65 06 L TOP VIEW i BOTTOM VIEW 0 25 MIN igo 12 0 80 MAX 7 50 REF 085 0 65 y 0 05 MAX THE EXPOSED PAD REFER TO COMPLIANT TO JEDEC STANDARDS MO 220 VMMD 4 THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET Figure 58 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 9 mm x 9 mm Body Very Thin Quad CP 64 7 Dimensions shown in millimeters Rev D Page 38 of 40 082908 B 062209 A 09912 ORDERING GUIDE Model Temperature Range
24. the AD9912 SYSCLK pins is intended for 25 MHz 3 2 mm x 2 5 mm AT cut fundamental mode crystals with a maximum motional resistance of 100 The following crystals listed in alphabetical order meet these criteria as of the revision date of this data sheet e AVX Kyocera CX3225SB ECS ECX 32 TSX 3225 Fox FX3225BS e NDKNX3225SA PD SYSCLK PLL REGISTER BIT SYSCLK PLL ENABLED CLKMODESEL SYSCLK PLL BYPASSED WITH CRYSTAL RESONATOR DETECTOR Note that although these crystals meet the preceding criteria according to their data sheets Analog Devices Inc does not guarantee their operation with the AD9912 nor does Analog Devices endorse one supplier of crystals over another When the SYSCLK PLL multiplier path is disabled the AD9912 must be driven by a high frequency signal source 250 MHz to 1 GHz The signal thus applied to the SYSCLK input pins becomes the internal DAC sampling clock after passing through an internal buffer It is important to note that when bypassing the system clock PLL the LOOP_FILTER pin Pin 31 should be pulled down to the analog ground with a 1 resistor SYSCLK PLL Doubler The SYSCLK PLL multiplier path offers an optional SYSCLK PLL doubler This block comes before the SYSCLK PLL multiplier and acts as a frequency doubler by generating a pulse on each edge of the SYSCLK input signal The SYSCLK PLL multiplier locks to the
25. the FDBK_IN input pins are internally biased to a dc level of 1 V Care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance TO S DIVIDER AND CLOCK OUTPUT SECTION 15kQ FDBK_INB 06763 035 Figure 43 Differential FDBK_IN Inputs Rev D Page 18 of 40 09912 SYSCLK INPUTS Functional Description An external time base connects to the AD9912 at the SYSCLK pins to generate the internal high frequency system clock The SYSCLK inputs can be operated in one of the following three modes e SYSCLK PLL bypassed e SYSCLK PLL enabled with input signal generated externally e Crystal resonator with SYSCLK PLL enabled A functional diagram of the system clock generator is shown in Figure 44 The SYSCLK PLL multiplier path is enabled by a Logic 0 default in the PD SYSCLK PLL bit Register 0x0010 Bit 4 of the I O register map The SYSCLK PLL multiplier can be driven from the SYSCLK input pins by one of two means depending on the logic level applied to the 1 8 CMOS CLKMODESEL pin When CLKMODESEL 0 a crystal can be connected directly across the SYSCLK pins When CLKMODESEL 1 the maintaining amp is disabled and an external frequency source such as an oscillator or signal generator can be connected directly to the SYSCLK input pins Note that CLKMODESEL 1 does not disable the system clock PLL The maintaining amp on
26. 15 of 40 CLOCK AD9912 SOURCE SELF BIASING WITH DIFF 1000 SYSCLK OUTPUT INPUT 06763 030 Figure 36 SYSCLK Differential Input Non Xtal 0 01uF CLOCK SOURC AD9912 WITH SELF BIASING SINGLE ENDED SYSCLK 1 8V CMOS INPUT OUTPUT 0 01uF Figure 37 SYSCLK Single Ended Input Non Xtal 0 1 AD9912 OPTIONAL SELF BIASING FDBK INPUT 0 1 06763 050 Figure 38 FDBK_IN Input AD9912 06763 049 09912 THEORY OF OPERATION DIGITAL SYNTHESIS CORE FREQUENCY CONTROL 1 4 DIGITAL INTERFACE TUNING WORD y DAC gur EXTERNAL ix OUTB Low PASS gp _ LOW NOISE EXTERNAL T FILTER CONFIGURATION LOGIC II Ll QO O O O SYSCLKB 06763 031 Figure 39 Detailed Block Diagram OVERVIEW The AD9912 is a high performance low noise 14 bit DDS clock synthesizer with integrated comparators for applications desiring an agile finely tuned square or sinusoidal output signal A digitally controlled oscillator DCO is implemented using a direct digital synthesizer DDS with an integrated output DAC clocked by the system clock A bypassable PLL based frequency multiplier is present enabling use of an inexpensive low frequency source for the system clock For best jitter performance the system clock PLL should be bypassed and a low noise high frequency system clock should be provided directly Sampling theor
27. 8 FTWO Frequency Tuning Word Continued Table 26 Bits Bit Name Description 23 16 FTWO These registers contain the FTW frequency tuning word for the DDS The FTW determines the ratio of the AD9912 output frequency to its DAC system clock Register 0x01A6 is the least significant byte of the FTW Note that the power up default is defined by start up Pin S1 to Pin S4 Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity Rev D Page 34 of 40 09912 Register 0x01A9 FTWO Frequency Tuning Word Continued Table 27 Bits Bit Name Description 31 24 FTWO These registers contain the FTW frequency tuning word for the DDS The FTW determines the ratio of the AD9912 output frequency to its DAC system clock Register 0x01A6 is the least significant byte of the FTW Note that the power up default is defined by start up Pin S1 to Pin S4 Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity Register 0x01AA FTWO Frequency Tuning Word Continued Table 28 Bits Bit Name Description 39 32 FTWO These registers contain the FTW frequency tuning word for the DDS The FTW determines the ratio of the AD9912 output frequency to its DAC system clock Register 0x01A6 is the least significant byte of the FTW Note that the power up default is defined by start up Pin S1 to Pin S4 Updates to the FTW results in an instantane
28. 912 operates over an industrial temperature range 40 MHz offset 161 dBc Hz spanning 40 to 85 BASIC BLOCK DIAGRAM AD9912 DAC OUT cam STARTUP S CONFIGURATION LOGIC 1 4 DIRECT DIGITAL SYNTHESIS CORE db OUT DIGITAL SERIAL PORT OUTPUT INTERFACE VO LOGI Da p VO OGC DRIVERS OUT_cMos SYSTEM CLOCK MULTIPLIER E 06763 001 Figure 1 Rev D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2007 2009 Analog Devices Inc All rights reserved 09912 TABLE OF CONTENTS FO At res 1 Applications uuu 1 General Descriptions nitide tee 1 Basic Block Diagram 1 Revision History seen 2 Specifications sept tpe 3 DC Specifications teet ete eit e neis 3 AG Specifications a u need 5 Absolute Maximum Ratings sente
29. 912 uses Register 0x0000 to Register 0x0509 Although the AD9912 serial control port allows both 8 bit and 16 bit instructions the 8 bit instruction mode provides access to five address bits A4 to AO only which restricts its use to Address Space 0x00 to Address Space 0x31 The AD9912 defaults to 16 bit instruction mode on power up and the 8 bit instruction mode is not supported THE INSTRUCTION WORD 16 BITS The MSB of the instruction word is R W which indicates whether the instruction is a read or a write The next two bits W1 WO are the transfer length in bytes The final 13 bits are the address 12 0 at which to begin the read or write operation For a write the instruction word is followed by the number of bytes of data indicated by Bits W1 W0 which is interpreted according to Table 9 AD9912 Bits A12 A0 select the address within the register map that is written to or read from during the data transfer portion of the communications cycle The AD9912 uses all of the 13 bit address space For multibyte transfers this address is the starting byte address Table 9 Byte Transfer Count Bytes to Transfer W1 wo Excluding the 2 Byte Instruction 0 0 1 0 1 2 1 0 3 1 1 Streaming mode MSB LSB FIRST TRANSFERS The AD9912 instruction word and byte data can be MSB first or LSB first The default for the AD9912 is MSB first The LSB first mode can be enabled by writing a 1 to the LSB first bit in the
30. ANALOG 1 GSPS Direct Digital DEVICES Synthesizer with 14 Bit DAC AD9912 FEATURES APPLICATIONS 1 GSPS internal clock speed up to 400 MHz output directly Agile LO frequency synthesis Integrated 1 GSPS 14 bit DAC Low jitter fine tune clock generation 48 bit frequency tuning word with 4 Hz resolution Test and measurement equipment Differential HSTL comparator Wireless base stations and controllers Flexible system clock input accepts either crystal or external Secure communications reference clock Fast frequency hopping On chip low noise PLL REFCLK multiplier 2 SpurKiller channels GENERAL DESCRIPTION Low jitter clock doubler for frequencies up to 750 MHz The AD9912 is a direct digital synthesizer DDS that features Single ended CMOS comparator frequencies of lt 150 MHz Programmable output divider for CMOS output Serial I O control Excellent dynamic performance Software controlled power down an integrated 14 bit digital to analog converter DAC The AD9912 features a 48 bit frequency tuning word FTW that can synthesize frequencies in step sizes no larger than 4 uHz Absolute frequency accuracy can be achieved by adjusting the DAC system clock Available in two 64 lead LFCSP packages Residual phase noise 250 MHz The AD9912 also features an integrated system clock phase 10 Hz offset 113 dBc Hz locked loop PLL that allows for system clock inputs as low 1 kHz offset 133 dBc Hz as 25 MHz 100 kHz offset 153 dBc Hz The AD9
31. EGISTER N DATA REGISTER N DATA REGISTER 1 DATA REGISTER 1 DATA Figure 51 Serial Control Port Write MSB First 16 Bit Instruction Two Bytes Data REGISTER 2 DATA CSB SCLK tov i i ru DATA BIT N DATA BIT N 1 Figure 54 Timing Diagram for Serial Control Port Register Read Figure 52 Serial Control Port Read MSB First 16 Bit Instruction Four Bytes Data 06763 046 REGISTER N 1 DATA Figure 55 Serial Control Port Write LSB First 16 Bit Instruction Two Bytes Data DON T CARE DON T CARE 06763 045 DON T CARE REGISTER N 3 DATA poNT CARE 06763 043 06763 057 06763 047 CSB SCLK SDIO Figure 56 Serial Control Port Timing Write Table 11 Definitions of Terms Used in Serial Control Port Timing Diagrams AD9912 06763 048 Parameter Description ta Period of SCLK toy Read data valid time time from falling edge of SCLK to valid data on SDIO SDO tos Setup time between data and rising edge of SCLK ton Hold time between data and rising edge of SCLK ts Setup time between CSB and SCLK ty Hold time between CSB and SCLK tu Minimum period that SCLK should be in a logic high state tio Minimum period that SCLK should be in a logic low state Rev D Page 29 of 40 09912 1 0 REGISTER MAP All address and bit locations that are left blank in Table 12 are unused
32. FSET O CH2 HARMONIC NUMBER O CH2 CANCELLATION PHASE OFFSET O CH1 CANCELLATION MAGNITUDE O CH2 CANCELLATION MAGNITUDE O HARMONIC SPUR CANCELLATION The procedure for tuning the spur reduction is as follows 1 Determine which offending harmonic spur to reduce and its amplitude Enter that harmonic number into Bit 0 to Bit 3 of Register 0x0500 Register 0x0505 2 Turn off the fundamental by setting Bit 7 of Register 0x0013 and enable the SpurKiller channel by setting Bit 7 of Register 0x0500 Register 0x0505 3 Adjust the amplitude of the SpurKiller channel so that it matches the amplitude of the offending spur 4 Turn the fundamental on by clearing Bit 7 of Register 0x0013 5 Adjust the phase of the SpurKiller channel so that maximum interference is achieved Note that the setting is sensitive to the loading of the DAC output pins and that a DDS reset is required if a SpurKiller channel is turned off The DDS can be reset by setting Bit 0 of Register 0x0012 and resetting the part is not necessary The performance improvement offered by this technique varies widely and depends on the conditions used Given this extreme variability it is impossible to define a meaningful specification to guarantee SpurKiller performance Current data indicate that a 6 dB to 8 dB improvement is possible for a given output frequency using a common setting over process temperature and voltage There are frequencies howeve
33. Hz Plot CMOS Driver On SpurKiller Off 110 RMS JITTER 100Hz TO 20MHz CARRIER 399MHz 50MHz 790fs SFDR W O SPURKILLER 63 7dBc SFDR WITH SPURKILLER _69 3dBc 120 FREQUENCY SPAN 500MHz RESOLUTION BW 3kHz F VIDEO BW 30kHz a a s 130 o 9 THESE TWO SPURS z 3 ELIMINATED WITH E 180 5 SPURKILLER amp 50MHz 150 10MHz 160 z 8 100 1k 10k 100k 1M 10M 100M 3 0 100 200 300 400 500 FREQUENCY OFFSET Hz 3 FREQUENCY MHz 3 Figure 17 Absolute Phase Noise Using CMOS Driver at 1 8 V Figure 20 SFDR Comparison With and Without SpurKiller SYSCLK 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed SYSCLK 1 GHz foyr 400 MHz Rev D Page 12 of 40 09912
34. Hz RMS JITTER 12kHz TO 20MHz SFDR 9idBc B 99MHz 0 98 FREQ SPAN 500kHz 7 399MHz 0 99ps RESOLUTION BW 300Hz VIDEO BW 1kHz 100 8 110 s 120 2 o 5 8 130 399MHz 6 amp 140 99MHz 150 110 160 e 200 85 200 95 201 05 201 15 201 25 201 35 2 10 100 1k 10k 100k 1M 10 100M FREQUENCY MHz FREQUENCY OFFSET Hz 3 Figure 10 Narrow Band SFDR at 201 1 MHz Figure 13 Absolute Phase Noise Using HSTL Driver SYSCLK 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed SYSCLK 1 GHz SYSCLK PLL Driven by Rohde amp Schwarz SMA100 Signal Generator at 83 33 MHz 80 CARRIER 398 7MHz RMS JITTER 12kHz TO 20MHz SFDR 86dBe 99MHz 1 41 FREQ SPAN 500kHz 90 399MHz 1 46ps RESOLUTION BW 300Hz VIDEO BW 1kHz 100 3 5 110 tc 5 0 120 9 o 2 2 5 H 130 5 399MHz o a 140 99MHz 150 0 160 398 45 398 55 398 65 398 75 398 85 398 95 3 10 100 1k 10k 100k 1M 10M 100M 3 FREQUENCY MHz FREQUENCY OFFSET Hz E Figure 11 Narrow Band SFDR at 398 7 MHz Figure 14 Absolute Phase Noise Using HSTL Driver SYSCLK 1 GHz Wenzel Oscillator SYSCLK PLL Bypassed SYSCLK 1 GHz SYSCLK Driven by Rohde amp Schwarz SMA100 Signal Generator at 25 MHz Rev D Page 11 of 40 09912
35. ITH SYSCLK PLL ENABLED SYSCLK O INTERNAL SYSCLKB O INTERNAL CLOCK INTERNAL CLOCK 06763 039 Figure 47 Differential SYSCLK Inputs Rev D Page 20 of 40 09912 Note that the SYSCLK PLL bypassed and SYSCLK PLL enabled input paths are internally biased to a dc level of 1 V Care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance Generally it is recommended that the SYSCLK inputs be ac coupled except when using a crystal resonator OUTPUT CLOCK DRIVERS AND 2x FREQUENCY MULTIPLIER There are two output drivers provided by the AD9912 The primary output driver supports differential 1 8 V HSTL output levels while the secondary supports either 1 8 V or 3 3 CMOS levels depending on whether Pin 37 is driven at 1 8 V or 3 3 V The primary differential driver nominally provides an output voltage with 100 load applied differentially The source impedance of the driver is approximately 100 for most of the output clock period during transition between levels the source impedance reaches a maximum of about 500 The driver is designed to support output frequencies of up to and beyond the OC 12 network rate of 622 08 MHz The output clock can also be powered down by a control bit in the I O register map Primary 1 8 V Differential HSTL Driver The DDS produces a sinusoidal clock signal that is sampled at the system clock rate
36. LOGIC O DAC OUT 14 C O DAC OUTB fs DAC RSET ANGLE TO AMPLITUDE 06763 032 Figure 40 DDS Block Diagram The input to the DDS is a 48 bit FTW that provides the accu mulator with a seed value On each cycle of the accumulator adds the value of the FTW to the running total of its output For example given an FTW 5 the accumulator increments the count by 5 sec on each f cycle Over time the accumulator reaches the upper end of its capacity 2 in this case and then rolls over retaining the excess The average rate at which the accumulator rolls over establishes the frequency of the output sinusoid The following equation defines the average rollover rate of the accumulator and establishes the output frequency of the DDS FTW f DDS E Solving this equation for FTW yields FTW round 48 2 fs For example given that f 1 GHz and 19 44 MHz then FTW 5 471 873 547 255 0x04FA05143BF7 The relative phase of the sinusoid can be controlled numerically as well This is accomplished using the phase offset function of the DDS a programmable 14 bit value Aphase see the I O Register Map section The resulting phase offset A radians is given by da gt usd 14 DIGITAL TO ANALOG DAC OUTPUT The output of the digital core of the DDS is a time series of numbers representing a sinusoidal waveform This series is translated to an analog signal by mean
37. Package Description Package Option AD9912ABCPZ 40 C to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP VQ CP 64 7 AD9912ABCPZ REEL7 40 to 85 64 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 64 7 AD9912BCPZ 40 to 85 64 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 64 1 AD9912BCPZ REEL7 40 C to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 1 AD9912A PCBZ AD9912 PCBZ Evaluation Board Evaluation Board 17 RoHS Compliant Part Recommended for use in new designs reference PCN 09 0156 Rev D Page 39 of 40 09912 NOTES 2007 2009 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D06763 0 11 09 D DEVICES www analog com Rev D Page 40 of 40
38. a reserved register and should write only zeros to unmapped registers Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved or unmapped registers Rev D Page 27 of 40 09912 Table 10 Serial Control Port 16 Bit Instruction Word MSB First MSB LSB 115 114 113 112 111 110 19 18 17 16 15 14 13 12 10 R W w1 WO A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO CSB serk oont AS U U UVU KoT cae SDIO R W Wi 0 12 aro 9 as A7 A6 a5 A4 as 2 A1 ao D7 06 D5 63 D2 DO D7 06 05 03 02 D1 Do K DONT care 16 BIT INSTRUCTION HEADER cs DON T CARE suo ehh X spo DONT CARE oo 07 os os 04 os ve os ps pa oo va ee o7 os 0s o 16 BIT INSTRUCTION HEADER CSB SCLK DON T CARE SDIO DON T CARE CSB spio cane A2 moan mawo wi e ps ps pa ps 7 57 DONT CARE 16 BIT INSTRUCTION HEADER Figure 53 Serial Control Port Write MSB First 16 Bit Instruction Timing Measurements Rev D Page 28 of 40 REGISTER N DATA R
39. a sin x x response which is caused by the sample and hold nature of the DAC output signal For applications using the fundamental frequency of the DAC output the response of the reconstruction filter should preserve the baseband signal Image 0 while completely rejecting all other images However a practical filter implementation typically exhibits a relatively flat pass band that covers the desired output frequency plus 2096 rolls off as steeply as possible and then maintains significant though not complete rejection of the remaining images Depending on how close unwanted spurs are to the desired signal a third fifth or seventh order elliptic low pass filter is common Some applications operate off an image above the Nyquist frequency and those applications use a band pass filter instead of a low pass filter The design of the reconstruction filter has a significant impact on the overall signal performance Therefore good filter design and implementation techniques are important for obtaining the best possible jitter results FDBK_IN INPUTS The FDBK_IN pins serve as the input to the comparators and output drivers of the AD9912 Typically these pins are used to receive the signal generated by the DDS after it has been band limited by the external reconstruction filter A diagram of the FDBK_IN input pins is provided in Figure 43 which includes some of the internal components used to bias the input circuitry Note that
40. al Input Level 632 mV p p Equivalent to 316 mV swing on each leg SYSCLK PLL Enabled VCO Frequency Range Low Band 700 810 MHz When in the range use the low VCO band exclusively VCO Frequency Range Auto Band 810 900 MHz When in the range use the VCO auto band select VCO Frequency Range High Band 900 1000 MHz When in the range use the high VCO band exclusively Maximum Input Rate of System 100 MHz Clock PFD Without SYSCLK PLL Doubler Input Frequency Range 11 200 MHz Multiplication Range 4 66 Integer multiples of 2 maximum PFD rate and system clock frequency must be met Minimum Differential Input Level 632 mV p p Equivalent to 316 mV swing on each leg With SYSCLK PLL Doubler Input Frequency Range 6 100 MHz Multiplication Range 8 132 Integer multiples of 8 Input Duty Cycle 50 96 Deviating from 5096 duty cycle may adversely affect spurious performance Minimum Differential Input Level 632 mV p p Equivalent to 316 mV swing on each leg Crystal Resonator with SYSCLK PLL Enabled Crystal Resonator Frequency Range 10 50 MHz AT cut fundamental mode resonator Maximum Crystal Motional Resistance 100 Q See the SYSCLK Inputs section for recommendations CLOCK DRIVERS HSTL Output Driver Frequency Range 20 725 MHz See Figure 27 for maximum toggle rate Duty Cycle 48 52 Rise Time Fall Time 20 to 80 115 165 ps 100 termination across OUT OUTB 2 pF load Jitter 12 kHz to 20 MHz 1 5 ps four 155 52 MHz 50 MHz system clock input see Figure 12 through Figu
41. ame Description 4 OPOL Output polarity Setting this bit inverts the HSTL driver output polarity 3 2 Reserved Reserved 1 0 HSTL output doubler HSTL output doubler 01 doubler disabled 10 doubler enabled When using doubler Bit 5 in Register 0 0010 must also be set to 1 Register 0x0201 CMOS Driver Table 33 Bits Bit Name Description 0 CMOS mux This bit allows the user to select whether the CMOS driver output is divided by the S divider 0 S divider input sent to CMOS driver 1 S divider output sent to CMOS driver See Figure 39 CALIBRATION USER ACCESSIBLE TRIM REGISTER 0x0400 TO REGISTER 0x0410 Register 0x0400 to Register 0xX040A Reserved Register 0xX040B DAC Full Scale Current Table 34 Bits Bit Name Description 7 0 DAC full scale current DAC full scale current Bits 7 0 See the Digital to Analog DAC Output section Register 0x040C DAC Full Scale Current Continued Table 35 Bits Bit Name Description 9 8 DAC full scale current DAC full scale current Bits 9 8 See Register OxO40B Register 0x040D to Register 0x0410 Reserved HARMONIC SPUR REDUCTION REGISTER 0x0500 TO REGISTER 0x0509 See the Harmonic Spur Reduction section Register 0x0500 Spur A Table 36 Bits Bit Name Description 7 HSR A enable Harmonic Spur Reduction A enable 6 Amplitude gain x 2 Setting this bit doubles the gain of the cancelling circuit and also
42. are registered on the falling edge This pin has an internal pull down resistor SDIO serial data input output is a dual purpose pin and acts as input only or input output The AD9912 defaults to bidirectional pins for I O Alternatively SDIO can be used as a unidirectional I O pin by writing to the SDO active bit Register 0x0000 Bit 0 1 In this case SDIO is the input and SDO is the output SDO serial data out is used only in the unidirectional I O mode Register 0x0000 Bit 0 1 as a separate output pin for reading back data Bidirectional I O mode using SDIO as both input and output is active by default SDO active bit Register 0x0000 Bit 0 0 CSB chip select bar is an active low control that gates the read and write cycles When CSB is high SDO and SDIO are ina high impedance state This pin is internally pulled up by a 100 kO resistor to 3 3 V It should not be left floating See the Operation of Serial Control Port section on the use of the CSB a communication cycle SCLK PIN 64 AD9912 SDIO PIN 63 99 SDO PIN 62 CONTRE s CSB PIN 61 PORT Figure 49 Serial Control Port OPERATION OF SERIAL CONTROL PORT Framing a Communication Cycle with CSB A communication cycle a write or a read operation is gated by the CSB line CSB must be brought low to initiate a communica tion cycle CSB stall high is supported in modes where three or fewer bytes of data plus the instruction data are tra
43. assed the HSTL and CMOS drivers are the same frequency as the signal presented at the FDBK IN pins When using the CMOS output in this configu ration the DDS output frequency should be in the range of 30 MHz to 150 MHz At low output frequencies 30 MHz the low slew rate of the DAC results in a higher noise floor This can be remedied by running the DDS at 100 MHz or greater and using the CMOS divider At an output frequency of 50 MHz the best technique depends on the user s application Running the DDS at 200 MHz and using a CMOS divider of 4 results in a lower noise floor but at the expense of close in phase noise At frequencies greater than 150 MHz the HSTL output should be used CMOS Output Divider S Divider The CMOS output divider is 16 bits cascaded with an additional divide by two The divider is therefore capable of integer division from 1 to 65 535 index of 1 or from 2 to 131 070 index of 2 The divider is programmed via the I O register map to trigger on either the rising default or falling edge of the feedback signal The CMOS output divider is an integer divider capable of handling frequencies well above the Nyquist limit of the DDS The S divider 2 bit Register 0x0106 Bit 0 must be set when FDBK IN is greater than 400 MHz Note that the actual output divider values equal the value stored in the output divider register minus one Therefore to have an output divider of one the user writes zeros to the o
44. ce Range AVSS 0 5 AVSS V Outputs connected to a transformer whose center tap is 0 50 0 50 grounded Wideband SFDR See the Typical Performance Characteristics section 20 1 MHz Output 79 dBc 0 MHz to 500 MHz 98 6 MHz Output 67 dBc 0 MHz to 500 MHz 201 1 MHz Output 61 dBc 0 MHz to 500 MHz 398 7 MHz Output 59 dBc 0 MHz to 500 MHz Narrow Band SFDR See the Typical Performance Characteristics section 20 1 MHz Output 95 dBc 250 kHz 98 6 MHz Output 96 dBc 250 kHz 201 1 MHz Output 91 dBc 250 kHz 398 7 MHz Output 86 dBc 250 kHz DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power Down 15 us Time Required to Leave Power Down 18 us Reset Assert to High Z Time 60 ns Time from rising edge of RESET to high Z on the S1 S2 S3 for S1to S4 Configuration Pins S4 configuration pins SERIAL PORT TIMING SPECIFICATIONS SCLK Clock Rate 1 tax 25 50 MHz Refer to Figure 56 for all write related serial port parameters maximum SCLK rate for readback is governed by tpy SCLK Pulse Width High 8 ns SCLK Pulse Width Low tow 8 ns SDO SDIO to SCLK Setup Time tp 1 93 ns SDO SDIO to SCLK Hold Time tp 1 9 ns SCLK Falling Edge to Valid Data on 11 ns Refer to Figure 54 SDIO SDO tpy CSB to SCLK Setup Time t 1 34 ns CSB to SCLK Hold Time t 0 4 ns CSB Minimum Pulse Width High toy 3 ns IO UPDATE Pin Setup Time tak sec ta period of SCLK in Hz from SCLK Rising Edge of the Final Bit IO UPDATE Pin Hold Time tax sec tax period
45. dback Input When using the HSTL and CMOS outputs input this pin is connected to the filtered DAC OUTB output This internally biased input is typically ac coupled and when configured as such can accept any differential signal whose single ended swing is at least 400 mV 41 Differential FDBK_IN Feedback Input In standard operating mode this pin is connected to the input filtered DAC_OUT output 48 O Current set DAC_RSET DAC Output Current Setting Resistor Connect a resistor usually 10 resistor from this pin to GND See the Digital to Analog DAC Output section 50 Differential DAC_OUT DAC Output This signal should be filtered and sent back on chip through output the FDBK IN input This pin has an internal 50 pulkdown resistor 51 Differential DAC_OUTB Complementary DAC Output This signal should be filtered and sent back output on chip through the FDBK INB input This pin has an internal 50 down resistor 56 57 Power DVSS Digital Ground Connect to ground 58 3 3 V CMOS PWRDOWN Power Down When this active high pin is asserted the device becomes inactive and enters the full power down state This pin has an internal 50 kO pull down resistor 59 3 3V CMOS RESET Chip Reset When this active high pin is asserted the chip goes into reset Note that on power up a 10 us reset pulse is internally generated when the power supplies reach a threshold and stabilize This pin should be grounded with a 10 resistor
46. generating these plots SFDR dBc 0 100 200 300 400 500 OUTPUT FREQUENCY MHz 06763 003 SIGNAL POWER dBm Figure 3 Wideband SFDR vs Output Frequency at 40 C 25 C and 85 C SFDR dBc SYSCLK 1 GHz SYSCLK PLL Bypassed HIGH Vpp NORMAL Vpp LOW Vpp 0 100 200 300 400 500 OUTPUT FREQUENCY MHz 06763 004 SIGNAL POWER dBm Figure 4 Variation of Wideband SFDR vs Frequency over DAC Power Supply SIGNAL POWER dBm Voltage SYSCLK 1 GHz SYSCLK PLL Bypassed CARRIER 20 1MHz SFDR 79dBc FREQ SPAN 500MHz RESOLUTION BW 3kHz VIDEO BW 10kHz 0 100 200 300 400 500 FREQUENCY MHz Figure 5 Wideband SFDR at 20 1 MHz SYSCLK 1 GHz SYSCLK PLL Bypassed 06763 005 SIGNAL POWER dBm Rev D Page 10 of 40 CARRIER 98 6MHz SFDR 67dBe m FREQ SPAN 500MHz RESOLUTION BW 3kHz 20 VIDEO BW 10kHz 30 40 50 60 70 80 90 100 0 100 200 300 400 FREQUENCY MHz Figure 6 Wideband SFDR at 98 6 MHz SYSCLK 1 GHz SYSCLK PLL Bypassed CARRIER 201 1MHz SFDR 61dBc FREQ SPAN 500MHz RESOLUTION BW 3kHz VIDEO BW 10kHz 500 100 200 300 400 FREQUENCY MHz Figure 7 Wideband SFDR at 201 1 MHz SYSCLK 1 GHz SYSCLK PLL Bypassed CARRIER 398 7MHz 500 SFDR
47. gulator being ideal 1 8 V SUPPLIES DVDD Pin 3 Pin 5 and Pin 7 These pins should be grouped together and isolated from the 1 8 V AVDD supplies For most applications a ferrite bead provides sufficient isolation but a separate regulator may be necessary for applications demanding the highest performance The current consumption of this group increases from about 160 mA at a system clock of 700 MHz to about 205 mA at a system clock of 1 GHz There is also a slight 5 increase as four increases from 50 MHz to 400 MHz AVDD Pin 11 Pin 19 Pin 23 Pin 24 Pin 36 Pin 42 Pin 44 and Pin 45 These pins can be grouped together and should be isolated from other 1 8 V supplies A separate regulator is recommended At a minimum a ferrite bead should be used for isolation AVDD Pin 53 This 1 8 V supply consumes about 40 mA The supply can be run off the same regulator as the 1 8 V AVDD group with a ferrite bead to isolate Pin 53 from the rest of the 1 8 V AVDD group However for applications demanding the highest performance a separate regulator is recommended AVDD Pin 25 Pin 26 Pin 29 and Pin 30 These system clock PLL power pins should be grouped together and isolated from other 1 8 V AVDD supplies At a minimum it is recommended that Pin 25 and Pin 30 be tied together and isolated from the aggregate AVDD 1 8 V supply with a ferrite bead Likewise Pin 26 and Pin 29 can also be tied together with a ferrite bead is
48. ications Iavpps Pin 37 8 9 6 mA CMOS output driver at 3 3 V 50 MHz with 5 pF load lavpps Pin 46 Pin 47 Pin 49 26 31 mA DAC output current source f 1 GSPS Iaypp Pin 11 Pin 19 Pin 23 to Pin 26 Pin 29 113 136 mA Aggregate analog supply with system Pin 30 Pin 36 Pin 42 Pin 44 Pin 45 clock PLL HSTL output driver and S divider enabled Iavpp Pin 53 40 48 mA DAC power supply lovop Pin 3 Pin 5 Pin 7 205 246 mA Digital core SpurKiller off lovop vo Pin 1 Pin 14 2 3 mA Digital I O varies dynamically LOGIC INPUTS Except Pin 32 Pin 9 Pin 10 Pin 54 Pin 55 Pin 58 to Pin 61 Pin 63 Pin 64 Input High Voltage 2 0 DVDD_I O V Input Low Voltage V DVSS 0 8 V Input Current lu ly 60 200 At Vn DVDD_I O Maximum Input Capacitance Ci 3 pF CLKMODESEL Pin 32 LOGIC INPUT Pin 32 only Input High Voltage 1 4 AVDD V Input Low Voltage AVSS 0 4 V Input Current lu lii 18 50 At Vn O V and V AVDD Maximum Input Capacitance Cn 3 pF LOGIC OUTPUTS Pin 62 and the following bidirectional pins Pin 9 Pin 10 Pin 54 Pin 55 Pin 63 Output High Voltage Von 2 7 DVDD_I O V lg 1 mA Output Low Voltage Vo DVSS 0 4 V lg 1 mA FDBK IN INPUT Pin 40 Pin 41 Input Capacitance 3 pF Input Resistance 18 22 26 kQ Differential Differential Input Voltage Swing 225 mV p p Equivalent to 112 5 mV swing on each leg must be ac coupled Rev D Page 3 of 40 09912
49. k settings between 810 MHz and 900 MHz use the VCO auto range Bit 7 to set the correct VCO range automatically Charge pump current 00 250 pA 01 375 uA 10 off 11 125 Rev D Page 33 of 40 09912 CMOS OUTPUT DIVIDER S DIVIDER REGISTER 0x0100 TO REGISTER 0x0106 Register 0x0100 to Register 0 0103 Register 0x0104 S Divider Table 21 Bits Bit Name Description 7 0 S divider CMOS output divider Divide ratio 1 65 536 If the desired S divider setting is greater than 65 536 or if the signal on FDBK_IN is greater than 400 MHz then Bit 0 in Register 0x0106 must be set Note that the actual S divider is the value in this register plus 1 so to have an S divider of 1 Register 0x0104 and Register 0x0105 must both be 0x00 Register 0x0104 is the least significant byte Register 0x0105 S Divider Continued Table 22 Bits Bit Name Description 15 8 S divider CMOS output divider Divide ratio 1 65 536 If the desired S divider setting is greater than 65 536 or if the signal on FDBK_IN is greater than 400 MHz then Bit 0 in Register 0x0106 must be set Note that the actual S divider is the value in this register plus 1 so to have an S divider of 1 Register 0x0104 and Register 0x0105 must both be 0x00 Register 0x104 is the least significant byte Register 0x0106 S Divider Continued Table 23 Bits Bit Name Description 7 Falling
50. ling frequency is 1 GHz These frequencies scale 1 1 with f meaning that other start up frequencies are available by varying the SYSCLK frequency At startup the internal frequency multiplier defaults to 40x when the Xtal PLL mode is selected via the status pins Table 8 Default Power Up Frequency Options for 1 GHz System Clock Status Pin SYSCLK Output Frequency 4 3 52 S1 Input Mode MHz 0 0 0 0 Xtal PLL 0 0 0 0 1 Xtal PLL 38 87939 0 0 1 0 Xtal PLL 51 83411 0 0 1 1 Xtal PLL 61 43188 0 1 0 0 Xtal PLL 77 75879 0 1 0 1 Xtal PLL 92 14783 0 1 1 0 Xtal PLL 122 87903 0 1 1 1 Xtal PLL 155 51758 1 0 0 0 Direct 0 1 0 0 1 Direct 38 87939 1 0 1 0 Direct 51 83411 1 0 1 1 Direct 61 43188 1 1 0 0 Direct 77 75879 1 1 0 1 Direct 92 14783 1 1 1 0 Direct 122 87903 1 1 1 1 Direct 155 51758 09912 POWER SUPPLY PARTITIONING The AD9912 features multiple power supplies and their power consumption varies with its configuration This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency The numbers quoted here are for comparison only Refer to the Specifications section for exact numbers With each group use bypass capacitors of 1 uF in parallel with a 10 uF The recommendations here are for typical applications and for these applications there are four groups of power supplies 3 3 V digital 3 3 V analog 1 8 V digital and 1 8
51. nsferred W1 W0 must be set to 00 01 or 10 see Table 9 In these modes CSB can temporarily return high on any byte boundary allowing time for the system controller to process the next byte CSB can go high on byte boundaries only and can go high during either part instruction or data of the transfer During this period the serial control port state machine enters a wait state until all data has been sent If the system controller decides to abort the transfer before all of the data is sent the state machine must be reset by either completing the remaining transfer or by returning the CSB low for at least one complete SCLK cycle but fewer than eight SCLK cycles Raising the CSB on a nonbyte boundary terminates the serial transfer and flushes the buffer In the streaming mode W1 W0 11 any number of data bytes can be transferred in a continuous stream The register address is automatically incremented or decremented see the MSB LSB First Transfers section CSB must be raised at the end of the last byte to be transferred thereby ending the stream mode Communication Cycle Instruction Plus Data There are two parts to a communication cycle with the AD9912 The first writes a 16 bit instruction word into the AD9912 coin cident with the first 16 SCLK rising edges The instruction word provides the AD9912 serial control port with information regarding the data transfer which is the second part of the communication cycle The
52. nt 7 Thermal Resistance i RD naa BEA REPRE 7 ESD Cautions e E 7 Pin Configuration and Function 8 Typical Performance Characteristics sssss Input Output Termination Recommendations Theory of Operation atr rene ee eR 1 E 16 Direct Digital Synthesizer DDS sss 16 Digital to Analog DAC Output see 17 Reconstruction Filter seeeeeeteentn 17 EDBKEIN Inputs i ance 18 SYSCLEK Inputs eter RIO EEN 19 Output Clock Drivers and 2x Frequency Multiplier 21 Harmonic Spur Reduction eene 21 Thermal Performance ahay hiq aw as 23 POWer 24 Power On Reset essere 24 Default Output Frequency on 0 24 REVISION HISTORY 11 09 Rev C to Rev D Added 64 Lead LFCSP 64 7 Universal Changes to Serial Port Timing Specifications and Propagation Delay Parameters sse 6 Added Exposed Paddle Notation to Figure 2 8 Changes to Power Supply Partitioning Section 25 Change to Serial Control Port Section sss 26 Changes to FIgure 52 i eee ne uay EI RS 28 Added Exposed Paddle Notation to Outline Dimensions 38 Changes to Ordering Guide
53. o aos or oa 40 06763 002 Figure 2 Pin Configuration Input Pin No Output PinType Mnemonic Description 1 Power DVDD O I O Digital Supply 2 4 6 8 Power DVSS Digital Ground Connect to ground 3 5 7 DVDD Digital Supply 9 10 54 55 3 3 V CMOS 1 52 53 54 Start Up Configuration Pins These pins are configured under program control and do not have internal pull up pull down resistors 11 19 23 to 26 AVDD Analog Supply Connect to a nominal 1 8 V supply 29 30 36 42 44 45 53 12 13 15 16 17 NC No Connect These unused pins can be left unconnected 18 20 21 22 14 46 47 49 AVDD3 Analog Supply Connect to a nominal 3 3 V supply 27 Differential SYSCLK System Clock Input The system clock input has internal dc biasing and input should always be ac coupled except when using a crystal Single ended 1 8V CMOS can also be used but it may introduce a spur caused by an input duty cycle that is not 50 When using a crystal tie the CLKMODESEL pin to AVSS and connect crystal directly to this pin and Pin 28 28 Differential SYSCLKB Complementary System Clock Complementary signal to the input input provided on Pin 27 Use a 0 01 pF capacitor to ground on this pin if the signal provided on Pin 27 is single ended 31 LOOP_FILTER System Clock Multiplier Loop Filter When using the frequency multiplier to drive the system clock an
54. of SCLK in Hz PROPAGATION DELAY FDBK_IN to HSTL Output Driver 2 8 ns FDBK_IN to HSTL Output Driver with 2x 7 3 ns Frequency Multiplier Enabled FDBK_IN to CMOS Output Driver 8 0 ns S divider bypassed FDBK_IN Through S Divider to CMOS 8 6 ns Output Driver Frequency Tuning Word Update 60 fs ns fs system clock frequency in GHz IO_UPDATE Pin Rising Edge to DAC Output Rev D Page 6 of 40 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating Analog Supply Voltage AVDD 2V Digital Supply Voltage DVDD 2V Digital Supply Voltage 3 6V DVDD_I O DAC Supply Voltage AVDD3 Pins 3 6V Maximum Digital Input Voltage 0 5 V to DVDD_I O 0 5 V Storage Temperature 65 to 150 C Operating Temperature Range 40 C to 85 C Lead Temperature 300 C Soldering 10 sec Junction Temperature 150 C AD9912 THERMAL RESISTANCE 0 is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 4 Thermal Resistance Package Type 06 4 0 Unit 64 Lead LFCSP 25 2 13 9 1 7 C W typical Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating condi
55. olating them from the same aggregate 1 8 V supply The loop filter for the system clock PLL should directly connect to Pin 26 and Pin 29 see Figure 46 Applications demanding the highest performance may need to have these four pins powered by their on their own LDO If the system clock PLL is bypassed the loop filter pin Pin 31 should be pulled down to analog ground using a 1 resistor Pin 25 Pin 26 Pin 29 and Pin 30 should be included in the large 1 8 V AVDD power supply group In this mode isolation of these pins is not critical and these pins consume almost no power Rev D Page 25 of 40 09912 SERIAL CONTROL PORT The AD9912 serial control port is a flexible synchronous serial communications port that allows an easy interface with many industry standard microcontrollers and microprocessors Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats The AD9912 serial control port can be configured for a single bidirectional I O pin SDIO only or for two unidirectional I O pins SDIO and SDO Note that all serial port operations such as the frequency tuning word update depend on the presence of the DAC system clock SERIAL CONTROL PORT PIN DESCRIPTIONS SCLK serial clock is the serial shift clock This pin is an input SCLK is used to synchronize serial control port reads and writes Write data bits are registered on the rising edge of this clock and read data bits
56. ous frequency jump but no phase discontinuity Register 0x01AB FTWO Frequency Tuning Word Continued Table 29 Bits Bit Name Description 47 40 FTWO These registers contain the FTW frequency tuning word for the DDS The FTW determines the ratio of the AD9912 output frequency to its DAC system clock Register 0x01A6 is the least significant byte of the FTW Note that the power up default is defined by start up Pin S1 to Pin S4 Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity Register 0x01AC Phase Table 30 Bits Bit Name Description 7 0 DDS phase word Allows the user to vary the phase of the DDS output See the Direct Digital Synthesizer section Register 0x01AC is the least significant byte of the phase offset word POW Note that a momentary phase discontinuity may occur as the phase passes through 45 intervals Register 0x01AD Phase Continued Table 31 Bits Bit Name Description 13 8 DDS phase word Allows the user to vary the phase of the DDS output See the Direct Digital Synthesizer section Register 0x01AC is the least significant byte of the phase offset word POW Note that a momentary phase discontinuity may occur as the phase passes through 45 intervals Rev D Page 35 of 40 09912 DOUBLER AND OUTPUT DRIVERS REGISTER 0x0200 TO REGISTER 0x0201 Register 0x0200 HSTL Driver Table 32 Bits Bit N
57. quire I O update they update immediately after being written Read only registers ignore write commands and are marked RO in the Type column of the register map An AC in this column indicates that the register is autoclearing Rev D Page 26 of 40 If the instruction word is a read operation 115 1 the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word where N is 1 2 3 or 4 as determined by W1 W0 In this case 4 is used for streaming mode where four or more words are transferred per read The data readback is valid on the falling edge of SCLK The default mode of the AD9912 serial control port is bidirec tional mode and the data readback appears on the SDIO pin It is possible to set the AD9912 to unidirectional mode by writing to the SDO active bit Register 0x0000 Bit 0 1 and in that mode the requested data appears on the SDO pin By default a read request reads the register value that is cur rently in use by the AD9912 However setting Register 0x0004 Bit 0 1 causes the buffered registers to be read instead The buffered registers are the ones that take effect during the next I O update SCLK SDIO SDO CSB UPDATE REGISTERS TOGGLE IO UPDATE PIN REGISTER BUFFERS CONTROL REGISTERS AD9912 CORE 06763 042 Figure 50 Relationship Between Serial Control Port Register Buffers and Control Registers of the AD9912 The AD9
58. r where a common setting can result in much greater improvement Manually adjusting the SpurKiller settings on individual parts can result in more than 30 dB of spurious performance improvement SPUR CANCELLATION ENABLE DAC I SET DAC RSET REGISTERS AND LOGIC ANGLE TO DAC OUT AMPLITUDE DAC CONVERSION 14 BIT gt HEADROOM CORRECTION O CH1 GAIN O CH2 GAIN 06763 040 Figure 48 Spur Reduction Circuit Diagram Rev D Page 22 of 40 THERMAL PERFORMANCE Table 7 Thermal Parameters AD9912 Symbol Thermal Characteristic Using a JEDEC51 7 Plus JEDEC51 5 2S2P Test Board Value Unit SM Junction to ambient thermal resistance 0 0 m sec air flow per JEDEC JESD51 2 still air 25 2 C W Junction to ambient thermal resistance 1 0 m sec air flow JEDEC JESD51 6 moving air 22 0 C W O Junction to ambient thermal resistance 2 0 m sec air flow JEDEC JESD51 6 moving air 19 8 C W Junction to board thermal resistance 1 0 m sec air flow per JEDEC JESD51 8 moving air 13 9 C W Junction to case thermal resistance die to heat sink per MIL Std 883 Method 1012 1 1 7 C W Junction to top of package characterization parameter 0 m sec air flow JESD51 2 still air 0 1 C W The AD9912 is specified for a case temperature To ensure that Toas is not exceeded an airflow source can be used
59. r off spur reduction off four 200 MHz DDS with Spur Reduction On 686 823 mW Same as DDS Only case except both spur reduction channels on DDS with HSTL Driver Enabled 657 788 mW Same as DDS Only case except HSTL driver enabled DDS with CMOS Driver Enabled 729 875 mW Same as DDS Only case except CMOS driver and S divider enabled and at 3 3 V CMOS four 50 MHz S divider 4 DDS with HSTL and CMOS Drivers Enabled 747 897 mW Same as DDS Only case except both HSTL and CMOS drivers enabled S divider enabled and set to 4 CMOS four 50 MHz DDS with SYSCLK PLL Enabled 648 777 mW Same as DDS Only case except 25 MHz on SYCLK input and PLL multiplier 40 Power Down Mode 13 16 mW Using either the power down and enable register or the PWRDOWN pin 1 Pin 14 is in the AVDD3 group but it is recommended that Pin 14 be tied to Pin 1 AVSS 0 Rev D Page 4 of 40 09912 AC SPECIFICATIONS fs 1 GHz DAC 10 unless otherwise noted Power supply pins within the range specified in the DC Specifications section Table 2 Parameter Min Typ Max Unit Test Conditions Comments FDBK_IN INPUT Pin 40 Pin 41 Input Frequency Range 10 400 MHz Minimum Differential Input Level 225 mV p p 12 dBm into 50 must ac coupled 40 V us SYSTEM CLOCK INPUT Pin 27 Pin 28 SYSCLK PLL Bypassed Input Frequency Range 250 1000 MHz Maximum four is 0 4 x Duty Cycle 45 55 96 Minimum Differenti
60. re 14 for test conditions HSTL Output Driver with 2x Multiplier Frequency Range 400 725 MHz Duty Cycle 45 55 Rise Time Fall Time 20 to 80 115 165 ps 100 termination across OUT OUTB 2 pF load Subharmonic Spur Level 35 dBc Without correction Jitter 12 kHz to 20 MHz 1 6 ps four 622 08 MHz 50 MHz system clock input see Figure 15 for test conditions CMOS Output Driver AVDD3 Pin 37 3 3 V Frequency Range 0 008 150 MHz See Figure 29 for maximum toggle rate the S divider should be used for low frequencies because the FDBK_IN minimum frequency is 10 MHz Duty Cycle 45 55 65 With 20 pF load and up to 150 MHz Rise Time Fall Time 20 to 80 3 4 6 ns With 20 pF load Rev D Page 5 of 40 09912 Parameter Min Typ Max Unit Test Conditions Comments CMOS Output Driver AVDD3 Pin 37 1 8 V Frequency Range 0 008 40 MHz See Figure 28 for maximum toggle rate Duty Cycle 45 55 65 96 With 20 pF load and up to 40 MHz Rise Time Fall Time 20 to 80 5 6 8 ns With 20 pF load DAC OUTPUT CHARACTERISTICS DCO Frequency Range 1 Nyquist Zone 0 450 MHz DAC lower limit is O Hz however the minimum slew rate for FDBK IN dictates the lower limit if using CMOS or HSTL outputs Output Resistance 50 Q Single ended each pin internally terminated to AVSS Output Capacitance 5 pF Full Scale Output Current 20 31 7 mA Range depends on DAC Rsg resistor Gain Error 10 10 FS Output Offset 0 6 Voltage Complian
61. ription 0 Register update Software access to the register update pin function Writing a 1 to this bit is identical to performing an I O update POWER DOWN AND RESET REGISTER 0x0010 TO REGISTER 0x0013 Register 0x0010 Power Down and Enable Power up default is defined by the start up pins Table 16 Bits Bit Name Description 7 PD HSTL driver Powers down HSTL output driver 1 HSTL driver powered down 6 Enable CMOS driver Powers up CMOS output driver 1 CMOS driver on 5 Enable output doubler Powers up output clock generator doubler Output doubler must still be enabled in Register 0x0200 4 PD SYSCLK PLL System clock multiplier power down 1 system clock multiplier powered down If the S4 pin is tied high at power up or reset this bit is set and the default value for Register 0x0010 is DO not CO 1 Full PD Setting this bit is identical to activating the PD pin and puts all blocks except serial port into power down mode SYSCLK is turned off 0 Digital PD Removes clock from most of digital section leave serial port usable In contrast to full PD setting this bit does not debias inputs allowing for quick wake up Rev D Page 32 of 40 Register 0x0011 Reserved Register 0x0012 Reset Autoclearing AD9912 To reset the entire chip the user can use the non autoclearing soft reset bit in Register 0x0000 Table 17 Bits Bit Name Description 0 DDS reset Reset of the direct digi
62. river Peak to Peak Amplitude vs Toggle Rate AVDD3 3 3 V with 20 pF Load Rev D Page 14 of 40 AMPLITUDE V 0 4 0 6 Figure 30 Typical HSTL Output Waveform Nominal Conditions DC Coupled Differential Probe Across 100 O load AMPLITUDE V FREQUENCY 600MHz trise 20968096 104ps trALL 80 20 107ps V p p 1 17V DIFF DUTY CYCLE 50 0 0 5 1 0 1 TIME ns 5 2 0 2 5 FREQUENCY 20MHz trise 20 80 5 5ns trALL 80262096 5 9ns V 1 8V DUTY CYCLE 53 TIME ns Figure 31 Typical CMOS Output Driver Waveform 1 8 V AMPLITUDE V Nominal Conditions Estimated Capacitance 5 pF FREQUENCY 40MHz trise 20 80 2 25ns 80262096 2 6ns V p p 3 3V DUTY CYCLE 52 TIME ns Figure 32 CMOS Output Driver Waveform 3 3 V Nominal Conditions Estimated Capacitance 5 pF 06763 024 06763 025 06763 026 AD9912 OWNSTREAM 1 8V DEVICE HSTL HIGH Z OUTPUT Figure 33 AC Coupled HSTL Output Driver AD9912 1 8V HSTL OUTPUT Figure 34 DC Coupled HSTL Output Driver 10pF ul AD9912 SELF BIASING SYSCLK INPUT CRYSTAL 10pF MODE REFER TO CRYSTAL DATA SHEET Figure 35 SYSCLK Input Xtal 06763 029 06763 027 06763 028 INPUT OUTPUT TERMINATION RECOMMENDATIONS Rev D Page
63. s of a digital to analog converter DAC The DAC outputs its signal to two pins driven by a balanced current source architecture see the DAC output diagram in Figure 41 The peak output current derives from a combination of two factors The first is a reference current ppp that is established at the DAC_RSET pin and the second is a scale factor that is programmed into the I O register map The value of Ipc rrr is set by connecting a resistor between the DAC RSET pin and ground The DAC RSET pin is internally connected to a virtual voltage reference of 1 2 V nominal so the reference current can be calculated by 1 2 I DAC REF R DAC REF Note that the recommended value of Ipac rer is 120 uA which leads to a recommended value for rer of 10 The scale factor consists of a 10 bit binary number FSC programmed into the DAC full scale current register in the T O register map The full scale DAC output current Iy c ps is given by I 72 I DAC _FS 1024 Using the recommended value of Rr c ppp the full scale DAC output current can be set with 10 bit granularity over a range of approximately 8 6 mA to 31 7 mA 20 mA is the default value AVDD3 CURRENT SWITCH ARRAY CURRENT SWITCH ARRAY SWITCH CONTROL INTERNAL 500 1 5 2 IcopE pee lcopE DAC OUT 50 61 DAC OUTB INTERNAL 500 06763 033 AVSS Figure 41
64. t critical DEFAULT OUTPUT FREQUENCY ON POWER UP The four status pins S1 to 54 are used to define the output frequency of the DDS at power up even though the I O registers have not yet been programmed At power up internal logic initiates a reset pulse of about 10 ns During this time 51 to 54 briefly function as input pins and can be driven externally Any logic levels thus applied are transferred to a 4 bit register on the falling edge ofthe internally initiated pulse The same behavior occurs when the RESET pin is asserted manually Setting up 51 to S4 for default DDS startup is accomplished by connecting a resistor to each pin either pull up or pull down to produce the desired bit pattern yielding 16 possible states that are used both to address an internal 8 x 16 ROM and to select the SYSCLK mode see Table 8 The ROM contains eight 16 bit DDS frequency tuning words one of which is selected by the state of the S1 to 53 pins The selected FTW is transferred to the FTWO register in the I O register map without the need for an I O update This ensures that the DDS generates the selected frequency even if the I O registers have not been programmed The state of the 4 pin selects whether the internal system clock is generated by means of the internal SYSCLK PLL multiplier or not see the SYSCLK Inputs section for details Rev D Page 24 of 40 The DDS output frequency listed in Table 8 assumes that the internal DAC samp
65. tal synthesis block Reset of this block is very seldom needed Register 0x0013 Reset Continued Not Autoclearing Table 18 Bits Bit Name Description 7 PD fund DDS Setting this bit powers down the DDS fundamental output but not the spurs It is used during tuning of the circuit 3 S div 2 reset Asynchronous reset for S prescaler 1 S divider reset Synchronous to S divider prescaler output reset for integer divider SYSTEM CLOCK REGISTER 0x0020 TO REGISTER 0x0022 Register 0x0020 N Divider Table 19 Bits Bit Name Description 4 0 N divider These bits set the feedback divider for system clock PLL There is a fixed divide by 2 preceding this block as well as an offset of 2 added to this value Therefore setting this register to 00000 translates to an overall feedback divider ratio of 4 See Figure 45 Register 0x0021 Reserved Register 0x0022 PLL Parameters Table 20 Bits Bit Name Description 7 VCO auto range Automatic VCO range selection Enabling this bit allows Bit 2 of this register to be set automatically 6 4 Reserved Reserved 3 2x reference Enables a frequency doubler prior to the SYSCLK PLL and can be useful in reducing jitter induced by the SYSCLK PLL See Figure 44 2 VCO range Selects low range or high range VCO 1 0 Charge pump current 0 low range 700 MHz to 810 MHz 1 high range 900 MHz to 1000 MHZ For system cloc
66. tions for extended periods may affect device reliability Note that the exposed pad on the bottom of package must be soldered to ground to achieve the specified thermal performance See the Typical Performance Characteristics section for more information ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev D Page 7 of 40 09912 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD_I O DVSS DVDD DVSS DVDD DVSS DVDD DVSS 1 2 10 AVDD 11 12 13 AVDD3 14 NC 15 NC 16 OONOURWNH NOTES Ow INDICATOR DAC_RSET 4 47 AVDD3 4 4 44 43 AVSS 4 4 AD9912 FDBK_IN TOP VIEW 4 Not to Scale 3 2 1 0 FDBK_INB 9 AVSS 8 OUT_CMOS 7 AVDD3 6 AVDD 5 OUT 4 OUTB 3 AVSS 3 3 3 3 3 3 3 1 NC NO CONNECT 2 THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION Table 5 Pin Function Descriptions LT LI LI I O O t 10 O lt v7 CN ON QN QN ooaoooaaaaxmmanartu z da lt aaqqqnoqqiw gt 0 o gt l
67. to the SYSCLK input pins must be limited so as not to exceed the maximum input frequency of the SYSCLK PLL phase detector A block diagram of the SYSCLK generator appears in Figure 45 SYSCLK PLL MULTIPLIER 1250 250A 3754A HIGH LOW RANGE FROM PHASE DAC SYSCLK FREQUENCY CHARGE SAMPLE INPUT DETECTOR PUMP CLOCK 06763 037 LOOP FILTER Figure 45 Block Diagram of the SYSCLK PLL The SYSCLK PLL multiplier has a 1 GHz VCO at its core A phase frequency detector PFD and charge pump provide the steering signal to the VCO in typical PLL fashion The PFD operates on the falling edge transitions of the input signal which means that the loop locks on the negative edges of the reference signal The charge pump gain is controlled via the I O register map by selecting one of three possible constant current sources ranging from 125 uA to 375 uA in 125 uA steps The center frequency of the VCO is also adjustable via the I O register map and provides high low gain selection The feedback path from VCO to PFD consists of a fixed divide by 2 prescaler followed by a programmable divide by N block where 2 x N x 33 This limits the overall divider range to any even integer from 4 to 66 inclusive The value of N is programmed via the I O register map via a 5 bit word that spans a range of 0 to 31 but the internal logic automatically adds a bias of2 to the value entered extending the range to 33 Care should be taken when choosing these
68. utput divider register HARMONIC SPUR REDUCTION The most significant spurious signals produced by the DDS are harmonically related to the desired output frequency of the DDS The source of these harmonic spurs can usually be traced to the DAC and the spur level is in the 60 dBc range This ratio represents a level that is about 10 bits below the full scale output of the DAC 10 bits down is 2 or 1 1024 Such a spur can be reduced by combining the original signal with a replica of the spur but offset in phase by 180 This idea is the foundation of the technique used to reduce harmonic spurs in the AD9912 Because the DAC has 14 bit resolution a 60 dBc spur can be synthesized using only the lower 4 bits of the DAC full scale range That is the 4 LSBs can create an output level that is approximately 60 dB below the full scale level of the DAC commensurate with a 60 dBc spur This fact gives rise to a means of digitally reducing harmonic spurs or their aliased images in the DAC output spectrum by digitally adding a sinusoid at the input of the DAC with a similar magnitude as the offending spur but shifted in phase to produce destructive interference Rev D Page 21 of 40 09912 Although the worst spurs tend to be harmonic in origin the fact that the DAC is part of a sampled system results in the possibility of spurs appearing in the output spectrum that are not harmoni cally related to the fundamental For example
69. values so as not to exceed the maximum input frequency of the SYSCLK PLL phase detector or SYSCLK PLL doubler These values can be found in the AC Specifications section External Loop Filter SYSCLK PLL The loop bandwidth of the SYSCLK PLL multiplier can be adjusted by means of three external components as shown in Figure 46 The nominal gain of the VCO is 800 MHz V The recommended component values shown in Table 6 establish a loop bandwidth of approximately 1 6 MHz with the charge pump current set to 250 uA The default case is 40 and it assumes a 25 MHz SYSCLK input frequency and generates an internal DAC sampling frequency of 1 GHz EXTERNAL LOOP FILTER FERRITE BEAD CHARGE PUMP AD9912 06763 038 Figure 46 External Loop Filter for SYSCLK PLL Table 6 Recommended Loop Filter Values for a Nominal 1 5 MHz SYSCLK PLL Loop Bandwidth Multiplier R1 Series C1 Shunt C2 8 3900 1nF 82 pF 10 4700 820 pF 56 pF 20 390 pF 27 pF 40 default 2 2 180 pF 10 pF 60 27 120 5 pF Detail of SYSCLK Differential Inputs A diagram of the SYSCLK input pins is provided in Figure 47 Included are details of the internal components used to bias the input circuitry These components have a direct effect on the static levels at the SYSCLK input pins This information is intended to aid in determining how best to interface to the device for a given application CRYSTAL RESONATOR W
70. y sets an upper bound for the DDS output frequency at 50 of f where f is the DAC sample rate but a practical limitation of 40 of f is generally recommended to allow for the selectivity of the required off chip reconstruction filter The output signal from the reconstruction filter can be fed back to the AD9912 to be processed through the output circuitry The output circuitry includes HSTL and CMOS output buffers as well as a frequency doubler for applications that need frequencies above the Nyquist level of the DDS The AD9912 also offers preprogrammed frequency profiles that allow the user to generate frequencies without programming the part The individual functional blocks are described in the following sections DIRECT DIGITAL SYNTHESIZER DDS The frequency of the sinusoid generated by the DDS is determined by a frequency tuning word FTW which is a digital that is numeric value Unlike an analog sinusoidal generator a DDS uses digital building blocks and operates as a sampled system Thus it requires a sampling clock f that serves as the fundamental timing source of the DDS The accumulator behaves as a modulo 2 counter with a program mable step size that is determined by the frequency tuning word FTW A block diagram of the DDS is shown in Figure 40 Rev D Page 16 of 40 48 BIT ACCUMULATOR OFFSET FREQUENCY TUNING WORD FTW CONVERSION AD9912 DAC I SET REGISTERS AND

Analog Devices AD9912 User's Manual

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