Dataram 8GB DDR3-1333
Contents
1. RC OU UC GC ne Page 2 Document 06851 Revision A 14 May 13 Dataram Corporation 2013 ry DTM64316K Optimizing Value and Performance 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM IRS1 IRSO0 DQSRO O DQSR9 O DQSRO O DQSR9 O Vss O DQS DQS CS DM DOS DOS DQS DAS CS DM DOS DOS DQR 3 0 O 1 0 3 0 VO 3 0 DQR 74 VO 3 0 VO 3 0 DQSR1 DQSR10 NN DQS DAS CS DM DOS DOS DQR 11 8 DQR 15 12 O V O 3 0 V O 3 0 DQSR2 DQSR11 DQSR2 O DQSR11 DQS DAS CS DM IDOS DOS DQS DAS CS DM DOS DOS DQR 19 16 O 1 03 0 VO 3 0 DQR 23 20 VO 3 0 VO 3 0 100563 DQSR12 L DQSR3 O DQSR12 e 3 i IDOS DOS CS DOS DOS CS DQR 27 24 VO 3 0 DQR 31 28 VO 3 0 100568 DQSR17 00588 DQSR17 DQS DAS CS DM DOS DOS CS DM 4 DOS CS CBR 3 0 O l O 3 0 VO 3 0 CBR 74 VO 3 0 DQSR4 _ DQSR13 aa DASR4 DQSR13 O L T T DQS DAS CS DM DOS DOS CS DM IDAS DAS C DOS DOS CS DQR 35 32 O I O 3 0 VO 3 0 DQR 39 36 O VO 3 0 VO 3 0 DQSR5 1005814 DQSR5 DASR14 L DQS DAS CS DM IDOS DOS DQS DAS CS DM DOS DOS C DQR 43 40 VO 3 0 VO 3 0 DQRI47 44 VO 3 0 VO 3 0 ees or E DQSR6 DQSR15 1 IDOS DOS CS DQS DAS CS DM DOS DOS CS DQR 51 48 VO 3 0 DQR 55 52 VO 3 0 VO 3 0 DQSR7 IDQSR12. Bit 7 6 Reserved 0 Module Nominal Voltage VDD Bit 0 NOT 1 5 V operable Bit 1 1 35 V operable Bit 2 1 2X V operable 6 Bit 3 Reserved 0x00 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 4 Bits 0x08 Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit 0 Primary bus width in bits 64 Bits OxOB Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 2 0 52 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 8 nim DTM64316K WWW SGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM 10 i Medium Timebase Dividend 0 125ns 8 MTB H Medium Timebase MTB Divisor 0 125ns 0x08 12 SDRAM Minimum Cycle Time tCKmin 1 5ns 0x0C 13 Reserved UNUSED 0x00 CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 2 5 Bit 2 CL 6 X 14 Bit 3 CL 7 X 0x3C Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 19 Bit 3 CL 15 0x00 Bit 4 CL 16
3. 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage 1 425 1 5 1 575 V Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vrer 0 1 Logical Low Logic 0 Vss Vrer 0 1 V AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 175 V Logical Low Logic 0 Vrer 0 175 V RC SCRI PR Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 4 2 Optimizing Value and Performance DTM64316K 8GB 240 Pin 2Rx4 Reg
4. RC12 LS Nibble UNUSED 0x00 76 SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED 0x00 77 112 Module Specific Section UNUSED 0x00 113 Module Specific Section UNUSED 0x00 114 116 Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte 0x01 118 Module Manufacturer ID Code Most Significant Byte 0x91 119 Module Manufacturing Location 0x00 120 Module Manufacturing Date 0x11 121 Module Manufacturing Date 0x05 122 Module Serial Number 0x44 123 Module Serial Number OxOE 124 Module Serial Number OxE3 125 Module Serial Number OxF4 126 Cyclical Redundancy Code CRC CRC OxAE 127 Cyclical Redundancy Code CRC CRC 0x60 Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 11 nimm DTM64316K WWW SGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM 128 Module Part Number 0x20 129 Module Part Number 0x20 130 Module Part Number 0x20 131 Module Part Number 0x20 132 Module Part Number D 0x44 133 Module Part Number A 0x41 134 Module Part Number T 0x54 135 Module Part Number A 0x41 136 Module Part Number R 0x52 137 Module Part Number A 0x41 138 Module Part Number M Ox4D 139 Module Part Number 0x20 140 Module Part Number 6 0x36 141 Module Part Number 4 0x34 142 Module Part Number 3 0x33 143 Module Part Number 1 0x31 144 Module Part Number 6 0x36 146 147 Module Revision Code UNUSED 0x00 148 DRAM Manufacturer ID Code Least S
5. 6 F DQSR7 DQSR16 T 1 NN IDOS DOS CS DQS DAS CS DM DOS DOS CS DQR 59 56 O 1 013 0 VO 3 0 DQR 63 60 O V O 3 0 V O 3 0 All 15 OHMS TO SDRAMS DECOUPLING DQ 63 0 O O DQR 63 0 Xi VppsPp 4 Serial PD CB 7 0 O A O CBRI7 0 m 22 OHMS All Devices ee VREF_DQ All SDRAMs DQS 17 0 O VWA O__DASRI17 0 s81 Wr 51 V All Devi BA 2 0 A BA 2 0 R SS evices IDQS 17 0 O O DQSR 17 0 A 15 0 A 15 0 R VnEF All SDRAMs IRAS IRASR alll SDRAMs GLOBAL SDRAM CONNECTS Mec tegere ee All 36 OHMS 1 0 B AAA 36 OHMS T i cs CKERT1 0 LCLK 1 0 O O LCLK 1 0 2 0 R A 15 0 R ODT 1 0 A ODTR 1 0 IRCLK 1 0 O A O RCLK 1 0 RASR x PAR IN AAA ERR_OUT CASR ci VR CHOR EVENT IWER VTT 390 i i OHMS All 240 OHMS ICKO ILR CLK 1 0 TEMPERATURE MONITOR SDA SA0 SA1 SA2 CKE 1 0 R ODT 1 0 R owd IRS 1 0 VIT SDRAMS ZQ a Vss Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 3 DTM64316K 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM 2 Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE
6. Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 19 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least 36 0ns 0x20 Significant Byte 23 Minimum Active to Active Refresh Delay Time tRCmin Least 49 125ns Ox89 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant 160 0ns 24 Byte 0x00 25 E Refresh Recovery Delay Time tRFCmin Most Significant 160 0ns 0x05 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns O0x3C 27 Minimum Internal Read to Precharge Command Delay Time 7 5 s 0x3C tRTPmin Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 9 DTM64316K WWW SGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Upper Nibble for tFAW 28 Bit 3 Bit 0 tFAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 29 Four Activate Window Delay Time tFAWmin Least 30 0ns OxFO ignificant Byte SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZ
7. ECC DDR3 DIMM PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tccp 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width tct avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe 65 ps DQ Input Pulse Width tpipw 400 ps DQS Output Access Time from Clock tpasck 255 255 ps Write DQS High Level Width toasH 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tcu or tci ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time 4 DQ to DQS Hold 0 38 tck avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tease lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time terc 160 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time tR
8. PRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 ck avg Write DQS Postamble Time twPsT 0 3 ck avg Write Recovery Time twR 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 7 nimm DTM64316K Optimizing Value and Performance 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 1 0x11 DDR3 2 Key Byte DRAM Device Type spRAM 008 Key Byte Module Type 3 Bit 3 Bit 0 Module Type RDIMM 0x01 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 0 Total SDRAM capacity in megabits 2Gb 0x03 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit 0 Column Address Bits 11 Ox1A Bit 5 Bit Row Address Bits 15
9. Q 7 X 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR X 31 On die Thermal Sensor ODTS Readout 0x05 Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max in mm 29 h 30 OxOF Bit 7 Bitb Reserved 0 Module Maximum Thickness 61 Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 th 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 th 2 Reference Raw Card Used 62 Bit 4 Bit 0 Reference Raw Card R C E 0x44 Bit 6 Bit 5 Reference Raw Card Revision Rev 2 Bit 7 Reserved 0 Registered DIMM Module Attributes 63 Bit 1 Bit 0 of Registers used on RDIMM 1 Register o 99 Bit 3 Bit 2 of Rows of DRAMs on RDIMM 2 Rows Bit 7 Bit 4 Reserved 0 64 RDIMM Thermal Heat Spreader Solution 0x00 Bit 6 Bit 0 Heat Spreader Thermal Characteristics 0 Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 10 nimm DTM64316K Optimiz
10. S M04 Vss 134 DQS10 164 CB6 194 224 DQ54 SCL SPD Clock Input 15 DQS1 45 CB2 75 105 DQ50 135 DQS10 165 CB7 195 ODTO 225 DQ55 SDA SPD Data Input Output 16 DQS1 46 76 IS1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss EVENT Temperature Sensing 17 Vss 47 Vss 77 ODT1 M07 Vss 137 DQ14 167 NC TEST 197 Voo 227 DQ60 RESET Reset for register and DRAMs 18 DQ10 48 Vr 78 108 DQse 138 DQ15 168 RESET 198 S3 NC 228 DQ61 PAR_IN Parity bit for Addr Ctrl 19 DQ11 49 79 52 M09 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss ERR_OUT Error bit for Parity Error 20 Vss 50 CKEO 80 Vss 110 Vss 140 DQ20 170 Voo 200 DQ36 230 005106 A12 BC Combination input Addr12 Burst Chop 21 DQ16 51 Vos Do32 411 DQs7 141 Do21 171 15 201 DQ37 231 DQS16 A10 AP Combination input Addr10 Auto precharge 22 DQ17 52 BA2 82 DQ33 M12 DOS7 142 Vss 172 A14 202 Vss 232 Vss Vss Ground 23 Vss 53 Our 83 Vss 113 Vss 143 DQS11 173 Voo 203 DQS13 233 DQ62 Voo Power 24 IDQS2 54 Vpp 84 DQs4 114 DQ58 144 DQS11 174 A12 BC 204 DQS13 234 DQ63 Vopsep SPD EEPROM Power 25 DQS2 55 A11 85 DQS4 115 DQs9 145 Vss 175 A9 205 Vss 235 Vss Verba Reference Voltage for DQ s 26 Vas 56 7 86 Vss 116 Vss 146 DQ22 176 206 DQ38 236 Vposep VnerCA Reference Voltage for CA 27 DQ18 57 Voo 87 DQ34 117 SAO 147 DQ23 177 A8 207 DQ39 237 SA1 Vn Termination Voltage 28 DQ19 58 A5 88 DQ35 118 SCL 148 Vss 178 A6 208 Vss 238 SDA NC No Connection 29 Vss 59 4 89 Vs
11. ignificant Byte 0x00 149 DRAM Manufacturer ID Code Most Significant Byte 0x00 150 175 Manufacturer s Specific Data UNUSED 0x00 176 255 Open for customer use UNUSED 0x00 Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 12 Syl DTM64316K SGB 240 pin 2Rx4 Registered ECC DDR3 DIMM EygDATARAM Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 13
12. ing Value and Performance 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte Optional 0x00 66 Register Manufacturer ID Code Most Significant Byte Optional 0x00 67 Register Revision Number Optional OxFF Register Type 68 Bit 2 0 Support Device SSTE32882 9x00 Bit 7 3 Reserved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 0x00 SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address 70 Bit 1 Bit 0 RC2 DA3 4 Value RESERVED 0x50 Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs Moderate SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock 71 Bit 1 Bit 0 RC4 DA3 4 Control Signals Outputs Moderate 0x55 Bit 3 Bit 2 RCA4 DBAO 1 Control Signals B Outputs Moderate Bit 5 Bit 4 RC5 DA4 3 value 1 1 and Y3 Y 38 Clock Outputs Moderate Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Outputs Moderate 72 SSTE32882 RC7 MS Nibble RC6 LS Nibble UNUSED 0x00 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 74 SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED 0x00 75 SSTE32882 RC13 MS Nibble
13. istered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low VIL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 0 150 M Capacitance T4 25 C f 100 MHz PARAMETER Pin Symb Minimu Maximum Unit ol m Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 1 5 2 5 pF DQ 63 0 CB 7 0 DOS 17 0 Input Output Capacitance IDQS 17 0 Cio 3 5 pF DC Characteristics 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V VIN VDD Output Leakage Current lot 10 10 pA 2 3 OV lt VOUT VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 5 DTM64316K 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM lbo Specifications and Conditions 0 to 70 C Voltage referenced to Vss 0 V E Max PARAMETER Symbol Test Cond
14. ition Value Unit Operating One Bank Active IppO Operating current One bank ACTIVATE to PRECHARGE 1750 mA Precharge Current Operating One Bank Active Read Ipp1 Operating current One bank ACTIVATE to READ to 1930 mA PRECHARGE Precharge Current Precharge Power m Bown Current Ipp2P Precharge power down current Slow exit 1012 mA Precharge Power A Down Current Ipp2P Precharge power down current Fast exit 1120 mA Precharge Standby oe Current Ipp2N Precharge standby current 1370 mA Active Power Down Current Ipp3P Active power down current 1192 mA Active Standby Current Ipp3N Active standby current 1900 mA Operating Burst Write Current Ipp4W Burst write operating current 2300 mA Operating Burst Read Current Ipp4R Burst read operating current 2110 mA Burst Refresh Current Ipp5B Refresh current 3070 mA Self Refresh T Current Ipp6 Self refresh temperature current MAX Tc 85 462 mA Operating Bank Interleave Read Ipp7 All bank interleaved read current 3280 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation a a ERN UE M eqi Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 6 DTM64316K Eyg2DATARAM Optimizing Value and Performance AC Operating Conditions 8GB 240 Pin 2Rx4 Registered
15. nimm DTM64316K Optimizing Value and Performance 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 I O Type SSTL 15 On board temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 Identification DTM64316K 1Gx72 8GB 2Rx4 PC3 10600R 9 E2 Performance range Clock Module Speed CL tncp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64316K is a registered 1Gx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is Dual Rank Each Rank is comprised of eighteen 512Mx4 DDR3 1333 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Bi directional Differential Data St
16. robe signals SDRAM Addressing Row Col Bank 15 11 3 Fully RoHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 31 DQ25 61 A2 o1 DQ41 121 Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Voo 92 122 152 DQS12 182 Voo 212 DQS14 63 0 Data Bits 33 6 1 DQS5 123 Das 153 DQS12 183 Voo 213 DQS14 DQS 17 0 DOS 17 0 Differential Data Strobes 4 34 DQS3 64 CKt 94 Dass 124 vss 154 Vss 184 CKO 214 Vss CK 1 0 CK 1 0 Differential Clock Inputs 5 Vss 35 Vss 65 95 125 DQs9 155 DQ30 185 CKO 215 DQ46 CKE 1 0 Clock Enables 6 DQSO 36 DQ26 66 96 DQ42 126 Das9 156 DA31 186 216 DQ47 ICAS Column Address Strobe paso 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 EVENT 217 Vss IRAS Row Address Strobe 8 Vss 38 Vss 68 Parin 98 Vss 128 DQ6 158 CB4 188 A0 218 DQ52 IS 3 0 Chip Selects 9 DQ2 39 69 VDD o9 po48 29 Da7 159 CBS 189 219 DQ53 Write Enable 10 40 CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss A 15 0 Address Inputs 11 Vss 41 Vss 71 BAO 101 Vss 131 DQ12 161 DQS17 191 Voo 221 00515 2 0 Bank Addresses 12 DQ8 42 DQS8 72 102 DQS6 132 DQ13 162 00517 192 RAS 222 DQS15 ODT 1 0 On Die Termination Inputs 13 DQ9 43 Dass 73 WE 103 DQse 133 Vss 163 Vss 193 SO 223 Vss SA 2 0 SPD Address 14 Vss 44 Vss 74 ICA
17. s 119 SA2 149 DQ28 179 Voo 209 DQ44 239 Vss 30 DQ24 60 90 DQ40 120 Vr 150 DQ29 180 210 DQ45 240 Vz Not used Document 06851 Revision A 14 May 13 Dataram Corporation 2013 Page 1 yey DTM64316K WW SGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Front view 133 35 i 5 250 0 374 30 00 il 0 681 NNNnnn nnnm Y 5 00 med 6 099 5 175 47 00 p 204 1 850 oq Tn 123 00 4 843 g Back view Side view 3 94 Max 0 155 Max TI T m 0 157 Min fnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn f nnonnnnnnnnnnonnmnnnnnammmnmnnn 1 27 10 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches
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