Hynix 4GB PC3-12800
Contents
1. Z VDD VDD E Cterm Cterm wile 2e V t vt vt o gid U o o o wmebess see i a AM N N Lj HH III H DQS3 Wj Dos 240ohm LDQS 240ohm DQS 240ohm Das 240ohm w DQS4 DQS3 AAA lDQS L a l pngg 1 Dos 1 lpos 1 w DOS DM3 WDM Z2 inu Zw DM zwi Edom a DM4 DQ 24 31 AA DQ 0 7 D11 DQ 0 7 DQ 0 7 I DQ 0 7 D12 WWW DQ 32 39 D3 o o o o Ed k Ed z z BBEssEEBR aBBSEsSsHEBE aBBEssEBS oB8EBssEBRE l Bokek 8 Ie l 58k IB EE B E E BIE l Bots ae ttt T I d Hu T 240ohm L_ 240ohm 240ohm 240ohm DOS MM Bee 1 O 1 Dos 1 m 1 NW Bese DM1 AN DM 70 i Zo WT DM deal DM ONI DM6 DQ 8 15 AAA DQ 0 7 DQ 0 7 D9 DQ 0 7 DQ 0 7 D6 AAN DQ 48 55 D14 m E E 5 E4 amp ae m Em2. Symbol Parameter Rating Units Notes Toper Normal Operating Temperature Range 0 to 85 C 1 2 Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8ys in the Extended Temperature Range Please refer to the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 0b DDR3 SDRAMs support Auto Self Refresh and Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tR
3. Table 10 IDD7 Measurement Loop Pattern ATTENTION Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9 x E E SIE S mms gja 45 IIS IR IE 5 iglia amp rm o E 2 8 ao Z qa 4 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 2 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 0 aus repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 0 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 Assert and repeat above D Command until 2 nFAW 1 if necessary E z 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 B 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 z SAT Repeat above D C
4. 2 2 6 7 D D 1 1 1 1 1 0 00 0 0 F 0 a 9 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 g 5 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Sep 2012 43 De SK hynix Table 9 IDD5B Measurement Loop Pattern 3 S 5 E alalslelals Pgi S Pw ei 58 3 23 2 8 o O 3 8 x lt lt 0 0 REF 0 0 1 0 0 0 0 0 1 12 D D 1 0 0 0 0 00 O 0 3 4 D D 1 1 1 10 0 00 0 o 5 8 repeat cycles 1 4 but BA 2 0 1 2 9 12 repeat cycles 1 4 but BA 2 0 2 2 9 13 16 repeat cycles 1 4 but BA 2 0 3 2 amp 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 133 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL 44 Rev 1 0 Sep 2012 SK yi
5. 34 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 26 3 The ac peak noise on Vref may not allow Vney to deviate from VgercA pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH CA DC100 6 VIL dc is used as a simplified symbol for VIL CA DC100 7 VIH ac is used as simplified symbol for VIH CA AC175 VIH CA AC150 VIH CA AC135 and VIH CA AC125 VIH CA AC175 value is used when Vref 0 175V is referenced VIH CA AC150 value is used when Vref 0 150V is referenced VIH CA AC135 value is used when Vref 0 135V is referenced and VIH CA AC125 value is used when Vref 0 125V is referenced 8 VIL ac is used as simplified symbol for VIL CA AC175 VIL CA AC150 VIL CA AC135 and VIL CA AC125 VIL CA AC175 value is used when Vref 0 175V is referenced VIL CA AC150 value is used when Vref 0 150V is referenced VIL CA AC135 value is used when Vref 0 135V is referenced and VIL CA AC125 value is used when Vref 0 125V is referenced Rev 1 0 Sep 2012 13 SK yi AC and DC Input Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 43 and Table 51 in DDR3 Device Operation as well as deratin
6. 122 NC 173 Vss 174 DQ54 19 Vss 20 Vss 71 Vss 72 Vss 123 Vpp 124 Vpp 175 DQ50 176 DQ55 21 DQ8 22 DQ12 73 CKEO 74 CKEI 125 TEST 126 VgerCA 177 DQ51 178 Vss 23 DQ9 24 DQ13 75 Vpp 76 Vpp 1127 Vss 128 Vss H79 Vss 180 DQ60 25 Vss 26 Vss 77 NC 78 a152 129 DQ32 130 DQ36 181 DQ56 182 DQ61 27 DQS1 28 DM1 79 BA2 80 A142 131 DQ33 132 DQ37 183 DQ57 184 Vss 29 DQS1 30 RESET 81 Vpp 82 Vpp 133 Vss 1134 Vss 185 Vss 186 DQS7 31 Vss 32 Vss 83 A12 BC 84 Ali 135 DQS4 136 DM4 187 DM7 188 DQS7 33 DQ10 34 DQ14 85 A9 86 A7 137 DQS4 138 Vss H89 Vss 190 Vss 35 DQIi 36 DQ15 87 Vpp 88 Vpp 139 Vss 140 DQ38 191 DQ58 192 DQ62 37 Vss 38 Vss 89 A8 90 A6 1 141 DQ34 142 DQ39 193 DQ59 194 DQ63 39 DQ16 40 DQ20 91 A5 92 A4 143 DQ35 144 Vss 195 Vss 1196 Vss 41 DQ17 42 DQ21 93 Vpp 94 Vpp 145 Vss 146 DQ44 197 SAO 198 EVENT 43 Vss 44 Vss 95 A3 96 A2 147 DQ40 148 DQ45 199 VDDspp 200 SDA 45 DQS2 46 DM2 97 AI 98 A0 149 DQ41 150 Vss P01 SA1 202 SCL 47 DQS2 48 Vss 99 Vpp 100 Vpp 151 Vss 152 DQS5 203 Vm 204 Vr 49 Vss 50 DQ22 101 CKO 102 CKI 153 DM5 154 DQS5 51 DQ18 52 DQ23 103 CKO 104 CKI 155 Vss 156 Vss NC No Connect RFU R
7. CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Ipp7 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT Wr enable set MR2 A 10 9 10B C Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 0 Sep 2012 39 SK yi Table 3 IDDO Measurement Loop Pattern a o I X ERES re m Plu ge PSIG ISIE 8S 3 ER 6 3 vay XI l i amp a t zz z 7 lt 0 0 ACT 0 0 1 1 0 0 00 0 0 0 s 1 2 DD 1 0 0 0 0 0 00 0 0 0 3 4 DD 1 1 11 0 0 00 0 0 0 ies repeat pattern 1 4 until nRAS 1 truncate if necessary
8. HMT351S6CFR8C Front Side p 67 60mm 3 80mm max gt Ie T A 4 00 0 10 E E S amp o E o E S S Detail A etail B R 1 00 0 08 mm gt 4 A 3 00 Back O O SPD C Detail of Contacts A N eo pm LO E 5 o di 8 9 e N Y 0 45 0 03 amp 4 gt Ma 0 60 e e 1 00 0 05 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Sep 2012 48
9. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2 In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using one merged power layer in Module PCB For IDD and IDDQ measurements the following definitions apply 0 and LOW is defined as VIN lt Vr Ac max 1 and HIGH is defined as VIN gt ViHaccmax MID LEVEL is defined as inputs are VREF VDD 2 Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 Basic IDD and IDDQ Measurement Conditions are described in Table 2 Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Output Buffer enabled in MR1 RTT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 0 Sep 2012 34 Y lop Y lbDQ optional RESET DDR3 CK CK SDRAM CKE bas bas RTT 25 Ohm CS EN DQ DM O 1 gt Vppo 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Figure 1 Measure
10. nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 x EN repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 0 0 0 0 0 00 0 0 F 0 7 2 1 nRC 3 4 DD 1 1 1 1 0 0 000 0 F 0 2 9 repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary BIB 1 nRC nRAS PRE 0 0 1 0 0 0 0 ojlo Flo k repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 Sep 2012 40 SK yi Table 4 IDD1 Measurement Loop Pattern a D D Hd memm a S 53i e I9 l lE LB L3S 3SI3 Z R om S 98 08 2 e9s2z 99 o le lt 0 0 ACT 0 0 1 1 0 00 0 O 0 0 1 2 D D 1 0 0 0 0 00 0 0 0 0 3 4 Db a i a 4 0 00 0 0 0 iss repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 0 1 0 0 001010 0 0 00000000 m repeat pattern 1 4 until nRAS 1 truncate
11. CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 0 Sep 2012 37 SK yi Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS High between RD Command Address T Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS High between WR Command Address T Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DD4W data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode RegistersP ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock O
12. DC output mid measurement level for IV curve linearity 0 5 X Vppo V VoL DC DC output low measurement level for IV curve linearity 0 2 x Vppo V VoH AC AC output high measurement level for output SR Vrr 0 1 x Vppo V 1 VoL ac AC output low measurement level for output SR Vrr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppo is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 amp and an effective test load of 25 O to Vrr Vppo 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VoHdiff AC AC differential output high measurement level for output SR 0 2 x VDDQ V 1 VoLaiff AC AC differential output low measurement level for output SR 0 2 x Vppo V 1 Notes 1 The swing of 0 2 x Vppg is based on approximately 50 of the static differential output high or low swing with a driver impedance of 40 amp and an effective test load of 258 to Vrr Vppo 2 at each of the differential outputs Rev 1 0 Sep 2012 22 SK yi Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Voi ac and Voy Ac for single ended signals are shown in table and figure b
13. EVENT en Active L device The system should guarantee the electrical level requirement is met for the al ive LOW EVENT pin on TS SPD part No pull up resister is provided on DIMM V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector PH which supports from 3 0 Volt to 3 6 Volt nominal 3 3V operation nrecc The RESET pin is connected to the RESET pin on the register and to the RESET pin on RESET IN the DRAM TEST Used by memory bus analysis tools unused NC on memory DIMMs Rev 1 0 Sep 2012 SK yi Pin Assignments Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Side Side Side Side Side Side Side Side VreFDQ Vss 53 DQ19 54 Vss 105 Vpp 106 Vpp 157 DQ42 158 DQ46 DQO DQ5 57 DQ24 58 DQ29 109 BAO 110 RAS 161 Vss 162 Vss 2 Vs 4 DQ4 55 Vss 56 DQ28 107 A10 AP 108 Bai 159 DQ43 160 DQ47 6 8 DQ1 Vss 59 DQ25 60 Vss 111 Vpp 112 Vpp 163 DQ48 164 DQ52 Vss 10 DQSO 61 Vss 62 DQS3 113 WE 114 SO 165 DQ49 166 DQ53 m UU mlOlNi ao wie tz DMO 12 DQSO 63 DM3 64 DQS3 115 CAS 116 ODTO 167 Vss 168 Vss 13 Vss 14 Vss 65 Vss 66 Vss 117 Vpp 118 Vbo 169 DQS6 170 DM6 15 DQ2 16 DQ6 67 DQ26 68 DQ30 119 A132 120 ODTI 171 DQS6 172 Vss 17 DQ3 18 DQ7 69 DQ27 70 DQ31 121 S
14. LEVEL Rev 1 0 Sep 2012 42 SK yi Table 7 IDD4R and IDDQ4R Measurement Loop Pattern 9 E o H gt o Fla olala SE ii WEBE 8 amp 2 3 s s mm la 2 oZ 3 x EE EE M ME 0 0 RD 0 1 0 1 0 0 00 O 0 0 O 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 2 3 DD 1 1 11 0 0 000 0 0 0 4 RD 0 1 0 1 0 0 00 0 0 F O 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 S 6 7 DD 1 1 1 1 Q0 0 0 L0 0O F 0 a 2 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 8 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDD4W Measurement Loop Pattern a ao m m x o o9 o e ri m 8 i i fwli 8 8 8 s 3 mm 3 GZ 5 d FT TT az 0 10 WR O 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 O 0 0 0 z 2 3 DD 1 1 1 1 1 0 00 0o olo 0 4 WR O 1 0 0 1 0 00 0 0 F O 00110011 5 D 1 0 0 0 1 0 00 O 0 F 0
15. V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 26 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3 800 1066 1333 1600 tDVAC ps tDVAC ps tDVAC ps VIH Ldiff ac Slew Rate VIH Ldiff ac VIH Ldiff ac 270mV V ns 350mV 300mV DQS DQS only Optional min max min max min max gt 4 0 75 175 214 4 0 57 170 214 3 0 50 167 191 2 0 38 119 146 1 8 34 102 131 1 6 29 81 113 1 4 22 54 88 1 2 13 19 56 1 0 0 note 11 lt 1 0 0 note note note Rising input differential signal shall become equal to or greater than VIHdiff ac level and Falling input differential signal shall become equal to or less than VIL ac level Rev 1 0 Sep 2012 17 SK yi Single ended requirements for differential signals Each individual
16. amp x ave Reserved ns 4 CL 10 wier otav 1 5 onto lt 1 875 is 1 3 Supported CL Settings 5 6 8 7 9 10 cK Supported CWL Settings 5 6 7 fick Rev 1 0 Sep 2012 31 SK yi DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 33 Speed Bin DDR3 1600K CL nRCD nRP 11 11 11 pane mate Parameter Symbol min max Internal read tan 13 75 20 command to first data 13 125 ACT to internal read or co 13 75 write delay time 13 125 9 13 75 PRE command period lap 13 125 59 ns ACT to ACT or REF fac 48 75 _ E command period 48 125 5 BLT o bras 35 9 tREFI ns cag WE 5 iao 3 0 33 ns h A CWL 6 7 amp x ave Reserved ns 4 CWL 5 ve 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 amp xave Reserved ns 1 2 3 4 8 CWL 7 amp K AVG Reserved ns 4 CWL 5 Kk Ave Reserved ns 4 CWL 6 CK AVG eye S ns 1 2 3 4 8 CL 7 Optional gt s CWL 7 Kk Ave Reserved ns 1 2 3 4 8 CWL 8 k Ave Reserved ns 4 CWL 5 K AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 Kk Ave Reserved ns 1 2 3 4 8 CWL 8 favo Reserved ns 1 2 3 4 CWL 5 6 amp kave Reserved ns 4 1 5 lt 1 875 CL 9 CWL 7 K AVG 0 ns 1 2 3 4 8 Optional CWL 8 CK AVG Reserved ns 1 2 3 4 CWL 5 6 amp kave Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 lt 1 875
17. component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK VDD or VDDQ VSEHmin m a poe e a Di a e VDD 2 or VDDQ 2 Sete otis 4 ee cee 2s Ee CK or DQS VSELmax A t 1 VSEL VSS of VSSQ 2 22 So ee BC ee het ee he See a ee ee eee time Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearin
18. if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 o repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 D D 1 0 0 0 0 0 00 0 0 F 0 z 2 2 1 nRC 3 4 D D I1 1 1 1 0 L0 00 0 0 F 0 a 9 repeat pattern nRC 1 4 until NRC nRCE 1 truncate if necessary 8 g 1 nRC nRCD RD 0 1 0 1 0 0 00 0 O F O 00110011 at repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 00 0 O F 0 2 ET repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Sep 2012 41 SK yi Table 5 IDD2N and IDD3N Measurement Loop Pattern a o I Dl HA ea m m m ie 3
19. ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts V vss Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 0 Sep 2012 26 SK yi Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 V ns CK CK DQ DQS DQS DM See figure below for each parameter definition Maximum Amplitude Overshoot Area DD Volts 9 v VSSQ Undershoot Area Maximum Amplitude Time ns Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 0 Sep 2012 27 SK yi Refresh parameters by device density Refresh parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units REED CUL tRFC 90 110 160 260 350 ns REF comman
20. ns 1 2 3 8 CWL 8 amp xave Reserved ns 1 2 3 4 CL 11 CWL 5 6 7 k AvG Reserved ns 4 CWL 8 K AVG 1 25 1 5 ns 1 2 3 Supported CL Settings 5 6 7 8 9 10 11 ck Supported CWL Settings 5 6 7 8 Tick Rev 1 0 Sep 2012 32 De SK hynix Speed Bin Table Notes Absolute Specification Toper VDDQ Vpp 1 5V 0 075 V 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED 4 Reserved settings are not allowed User must program a different value 10 11 Optional settings allow certain devices in the industry to support this setting however i
21. on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 High SDRAM mode register RAS TAS WE IN Active When sampled at the cross point of the rising edge of CK signals CAS RAS and WE Low define the operation to be executed by the SDRAM V REFDQ Supply Reference voltage for SSTL15 inputs VREFCA BA 2 0 IN Selects which SDRAM internal bank of eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read of Write com mand cycle defines the column address when sampled at the cross point of the rising A 9 0 edge of CK and falling edge of CK In addition to the column address AP is used to A10 AP invoke autoprecharge operation at the end of the burst read or write cycle If AP is high A1l T IN autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low A12 JBC autoprecharge is disabled During a Precharge command cycle AP is used in conjunction A 15 13 with BA0 BAn to control which bank s to precharge If AP is high all banks will be pre charged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge A12 BC is samples during READ and WRITE com mands to determine if burst chop on the fly will be performed HIGH no burst chop LOW burst chopped DQ 63 0 1 O Data Input Output pins Active The data write ma
22. tREFI ag period Bios CWL 5 CK AVG 3 0 3 3 ns 1 2 3 4 6 10 7 CWL 6 CK AVG Reserved ns 4 ds6 CWL 5 CK AVG 2 5 3 3 ns 1 2 3 6 7 CWL 6 CK AVG Reserved ns 1 2 3 4 CWL 5 CK AVG Reserved ns 4 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 4 tien CWL 5 CK AVG Reserved ns 4 7 CWL 6 Kk vo 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 5 6 7 8 MK 10 Supported CWL Settings 5 6 NK 30 SK yi DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 33 Speed Bin DDR3 1333H CL nRCD nRP 9 9 9 unit mote Parameter Symbol min max Internal read ba 13 5 20 H command to first data 13 125 ACTtointernalreador 13 5 _ n write delay time 13 125 PRE command period lap a me ns ACT to ACT or REF fac 49 5 u n command period 49 125 gt 9 ACTH rt d leas 36 9 tREFI ns TENA CWL 5 Kk Ave 3 0 3 3 ns 1 2 3 4 7 10 CWL 6 7 lck avG Reserved ns 4 CWL 5 amp xave 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 ka Red n 142 3 4 7 CWL 7 amp xave Reserved ns 4 CWL 5 Kk Ave Reserved ns 4 Pane eel WEB 0 Se e Teas CL 7 CWL 6 CK AVG ns 1 2 3 4 7 Optional gt CWL 7 amp K AVG Reserved ns 1 2 3 4 CWL 5 amp K AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 7 MIT CWL 5 6 ck avG Reserved ns 4 CWL 7 K AVG 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6
23. time to which setup and hold is measured System timing and voltage budgets need to account for Vgerpc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vgcrac noise Timing and voltage effects due to ac noise on Vg up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 0 Sep 2012 15 SK yi AC and DC Logic Input Levels for Differential Signals Differential signal definition VILDIFFACMIN o cree e Be es ee kt Se Selle ere a ore hg VILDFEMN MERC ERES Oe ENE RECEN UNDER half cycle Mo SIM demde eem dEA Differential Input Voltage i e DQS DQS CK CK VILBIFEACMAK 4 4 tpvac Definition of differential ac swing and time above ac level tpyac Rev 1 0 Sep 2012 16 SK yi Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC Input Levels DDR3 800 1066 1333 amp 1600 Symbol Parameter Unit Notes Min Max V IHdiff Differential input high 0 200 Note 3 V 1 Vii dirt Differential input logic low Note 3 0 200 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 Vit diff ac Differential input low ac Note 3 2 x VIL ac Vref
24. used when Vref 0 150V is referenced and VIH DQ AC135 value is used when Vref 0 135V is referenced 8 VIL ac is used as simplified symbol for VIL DQ AC175 VIL DQ AC150 and VIL DQ AC135 VIL DQ AC175 value is used when Vref 0 175V is referenced VIL DQ AC150 value is used when Vref 0 150V is referenced and VIL DQ AC135 value is used when Vref 0 135V is referenced Rev 1 0 Sep 2012 14 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages yrefca and Vpefpg are illustrated in figure below It shows a valid reference voltage Vp t as a function of time Vref stands for Vperca and Vnerpo likewise Vref DC is the linear average of Vpe t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 21 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vrer t Vref ac noise VRef DC max _ VDD 2 VRef DC min Illustration of Vgerpc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Vyy acy Vra pc V acy and V pc are depen dent on Vger Vref shall be understood as Vgerpc as defined in figure above This clarifies that dc variations of Vper affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the
25. 0 w o m w o w w o DD jw wW 9 oBssEssSBE l lEBlEsw E wBeBbessesse B REESE T I L poso vnos 2w LD95 pura pos On BES xn DQSD Was zo s DQS DQS etl _ bos roe AM 0957 DMO WDM OM DM cum 1 DM TNI Inn DOS7 DQ 0 7 AMvipQ 0 7 DQ 0 7 DQ 0 7 DQ 0 7 W DM7 DO D15 LAW DQ 56 43 o e o o E El Ei El 2 yw wk 5 w wk 5 o c o ula webesesske e ese I 5 8 wBbEssesse week w be I I WwW 2400hm 2400h 240ohm 240ohm bi K 4 19 ee 1 EF 1 Dos 1 Dare 23 w et mo De A B m my W DQS5 d WV DQ 0 7 F DQ 0 7 DQ 0 7 1 DQ 0 7 Duas S5 D10 D13 D5 hw PO LWS DM5 E WA DQ 40 47 E S sj o Ej Ej Ed Ed z E M E u kh o wk io w w o w w e 6lI 58E lSBl E I lEl5l X 6b68E v k8 s L T The SPD may be integrated with the Temp ma j Sensor or may be Vi cmm BE d tt Dp SPD TS a separate component D9 D3 HAE D12 e D6 sa sa e VREFCA I gt VREFDQ D0 D15 mm a SPD gt SDA 3 v7 Vo i p os A2 WP gt v4 V5 V6 C Wilt du D0 D15 SPD Temp sensor D8 4 D10 D5 D7 q Qi p wos se S L GG pov sao A0 prd K pos SA1 N lt gt SDA Do V4 So NB D13 M D15 c xeo p 0007 EVENT 5 XE o wns i Sg p oe EVENT v3 Vtt We 3 bo NOTES T v2 Vi ve v8 opto Me w 1 DQ wiring may differ from that shown D
26. 1 D0 D7 SPD Temp sensor cko M D0 D7 a S S TKO p D0 D7 amp a CKi M9 1 Terminated near cea p 1 card edge OO w 5 Qo y w 5 e 8 Bl8 lE sess Bisse SE S1 ____ NC I ODT1 NC CKE1 pC EVENT Temp Sensor RESET gt D0 D7 DQS4 A DQS 240ohm DQS5 A LDOS 240ohm DQS4 AMDOS o MO DQS5 AM IDOS NER UNE DM4 v M re DMS AAALTLDM Senta 32 39 WA DQ 0 7 D2 DQ 40 47 DQ 0 7 D 6 V1 v2 v3 V4 z S e D Je 5 e D6 e D H z p 4 E 9l2 xxx B 2 ux y lll xwa l l52 zz 8 kE J t e DQS6 Das zonm DQS7 AWX LDQS Eon DQS6 AM DOS zs 1 DQS7 AA XDOS 25 1 DM6 AM DM Wa DM7 AM LDM Wa 3 48 55 VVW DQ 0 7 DQ 56 63 AAALDQ 0 7 D3 D7 Address and Control Lines II o 6 NOTES a amp 1 DQ wiring may differ from that me E w T E shown however DQ DM DQS and essBssEsE alsisisms5s8sm DQS relationships are maintained as shown P Rank 0 Rev 1 0 Sep 2012 S K nix 4GB 512Mx64 Module 2Rank of x8
27. 2Q 160 184 184 mA IDD3N 200 216 240 mA IDD3P 120 120 136 mA IDDAR 600 720 840 mA IDD4W 600 680 760 mA IDD5B 880 920 960 mA IDD6 96 96 96 mA IDDGET 112 112 112 mA IDD7 1160 1440 1480 mA 4GB 512M x 64 SO DIMM HMT351S6CFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 480 480 600 mA IDD1 560 560 680 mA IDD2N 320 320 400 mA IDD2NT 400 400 480 mA IDD2PO 192 192 192 mA IDD2P1 240 240 240 mA IDD2Q 320 368 368 mA IDD3N 400 432 480 mA IDD3P 240 240 272 mA IDDAR 760 880 1080 mA IDD4W 760 840 1000 mA IDD5B 1040 1080 1200 mA IDD6 192 192 192 mA IDDGET 224 224 224 mA IDD7 1320 1600 1720 mA Rev 1 0 Sep 2012 46 SK yi Module Dimensions 256Mx64 HMT325SGCFRSC Front Side 67 60mm lq gt 3 80mm max gt 4 2 0 gt 2 C M d E 8 E E e l 8 vv 1 00 0 08 mm gt l l4 Detail of Contacts A eo To F 5 2o B S e ci Y 0 45 0 03 9 A d 060 gt gt 1 00 0 05 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Sep 2012 47 SK yi 512Mx64
28. 4 256Mx8 H5TQ2G83CFR 8 1 HMT351S6CFR8C G7 H9 PB 4GB 512Mx64 2 256Mx8 H5TQ2G83CFR 16 SK yi Key Parameters CAS tCK tRCD tRP tRAS tRC MT s Grade ns Latency ns ns ns ns CL tRCD tRP tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3 1333 H9 1 5 9 13 125 13 125 36 49 125 9 9 9 13 75 13 75 48 75 DDR3 1600 PB 1 25 11 13 125 13 125 35 48 125 11 11 11 SK hynix DRAM devices support optional downbinning to CL11 CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade Remark CL5 CL6 CL7 CL8 CL9 CL10 CL11 G7 667 800 1066 1066 H9 667 800 1066 1066 1333 1333 PB 667 800 1066 1066 1333 1333 1600 Address Table 2GB 1Rx8 4GB 2Rx8 Refresh Method 8K 64ms 8K 64ms Row Address A0 A14 A0 A14 Column Address A0 A9 A0 A9 Bank Address BAO BA2 BAO BA2 Page Size 1KB 1KB Rev 1 0 Sep 2012 De SK hynix Pin Descriptions Rev 1 0 Sep 2012 Pin Name Description m Pin Name Description rant CK 1 0 Clock Input positive line 2 DQ 63 0 Data Input Output 64 CK 1 0 Clock Input negative line 2 DM 7 0 Data Masks 8 CKE 1 0 Clock Enables 2 DQS 7 0 Data strobes 8 RAS Row Address Strobe 1 DQS 7 0 Data strobes negative line 8 CAS Column Address Strobe 1 EVE
29. 82 f I 3 8IE B SERRE oah 6 3 Og E i Sle sie xx 7 Oo 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 42 1 1 90 0 0 0 0 F oO 3 D 1 1 1 1 0 0 0 00 F 0 m 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead 2 2 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead 2 B 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 128 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern x A o 9 E oct Biel e 2 iiss ele 3 3 83 a gia paa SP a og l i e 9sz2z2 o le mm lt a 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 00L0 0 L0 LF 0 3 D 1 1 1 1 Q0 0L0 L0L0 LF 0 D 1 4 7 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 D 9 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 2 j 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID
30. EFI requirements in the Extended Temperature Range Rev 1 0 Sep 2012 11 SK yi AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max VDD Supply Voltage 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Rev 1 0 Sep 2012 12 De SK hynix AC amp DC Input Measurement Levels AC and DC Logic Input Levels for Single Ended Signals AC and DC Input Levels for Single Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and ADDress DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD V 1 5 VIL CA DC100 DC input logic low VSS Vref 0 100 V 1 6 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL CA AC175 AC input logic low Note2 Vref 0 175 V 1 2 8 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 7 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high V 1 2 7 VIL CA AC135 AC input logic low V 1 2 8 VIH CA AC125 AC Input logic high V 1 2 7 VIL CA AC125 AC input logic low V 1 2 8 Vaan e a 0 49 VDD 0 51 VDD V
31. NT Temperature event pin 1 WE Write Enable 1 TEST ae E Vira PHI INO aj S 1 0 Chip Selects 2 RESET Reset Pin 1 pene Address Inputs 14 Vpp Core and I O Power 18 A10 AP Address Input Autoprecharge 1 Vss Ground 52 A12 BC Address Input Burst chop 1 BA 2 0 SDRAM Bank Addresses 3 VREFDQ 1 Input Output Reference ODT 1 0 On Die Termination Inputs 2 VREFCA 1 SCL bad m Detect PD 1 Vit Termination Voltage 2 SDA SPD Data Input Output 1 Vppspp SPD Power 1 SA 1 0 SPD Address Inputs 2 NC Reserved for future use 2 Total 204 5 SK yi Input Output Functional Descriptions Symbol Type Polarity Function uM The system clock inputs All address and command lines are sampled on the cross point CK0 CK0 IN Cross Point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is CK1 CK1 driven from the clock inputs and output timing for read operations is synchronized to the input clock Active Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when CKE 1 0 IN Hiah low By deactivating the clocks CKE low initiates the Power Down mode or the Self 9 Refresh mode Active Enables the associated DDR3 SDRAM command decoder when low and disables the S 1 0 IN Low command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by S0 Rank 1 is selected by S1 ODT 1 0 IN Active Asserts
32. SKE yi DDR3 SDRAM Unbuffered SODIMMs Based on 2Gb C die HMT325S6CFR8C HMT351S6CFR8C SK hynix reserves the right to change products or specifications without notice Rev 1 0 Sep 2011 1 SK yi Revision History Revision No History Draft Date Remark 0 1 Initial Release Mar 2011 Preliminary 0 2 IDD Update Aug 2011 0 3 JEDEC SPEC Update Feb 2012 0 4 JEDEC SPEC Update Jun 2012 Rev 1 0 Sep 2012 SK yi Description SK hynix Unbuffered Small Outline DDR3 SDRAM DIMMs Unbuffered Small Outline Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3 SDRAM devices These Unbuffered DDR3 SDRAM SODIMMs are intended for use as main memory when installed in systems such as mobile personal computers Fetures e VDD 1 5V 0 075V e VDDQ 1 5V 0 075V e VDDSPD 3 0V to 3 6V e Functionality and operations comply with the DDR3 SDRAM datasheet e 8 internal banks e Data transfer rates PC3 12800 PC3 10600 PC3 8500 or PC3 6400 e Bi directional Differential Data Strobe e 8 bit pre fetch e Burst Length BL switch on the fly BL 8 or BC Burst Chop 4 e On Die Termination ODT supported e This product is in Compliance with the RoHS directive Ordering Information Rev 1 0 Sep 2012 Part Number Density Organization Component Composition T HMT325S6CFR8C G7 H9 PB 2GB 256Mx6
33. d time verage periodic REN 0 C lt Tease lt 85 C 7 8 7 8 7 8 7 8 7 8 us p interval 85 C lt TcAse lt 95 C 3 9 3 9 3 9 3 9 3 9 us Rev 1 0 Sep 2012 28 SK yi Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 33 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tna 15 20 ns ACT to internal read or write delay time facp 15 ns PRE command period l p 15 ns ACT to ACT or REF command period fac 52 5 ns ACT to PRE command period fRas 37 5 9 tREFI ns CL 5 CWL 5 K AVG 3 0 3 3 nS 1 2 3 4 10 CL 6 CWL 5 K AVG 2 5 3 3 ns 1 2 3 Supported CL Settings 5 6 cK 10 Supported CWL Settings 5 cK Rev 1 0 Sep 2012 29 SK yi DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 33 Rev 1 0 Sep 2012 Speed Bin DDR3 1066F CL nRCD nRP 7 7 7 xni Dole Parameter Symbol min max Internal read command to first data tan 13 125 20 ns ACT to internal read or write delay time Rep 13 125 v es PRE command period trp 13 125 ns ACT to ACT or REF kc 50 625 _ fis command period ACT to PRE command ae 37 5 9
34. definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating in DDR3 Device Operation for single ended slew rate definition for data signals Rev 1 0 Sep 2012 20 SK yi Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential Input Slew Rate Definition Measured Description 5 F Defined by in ax Differential input slew rate for rising edge Voas sss EL CK CK and DQS DQS ILdiffmax IHdiffmin VIHdiffmin VILdiffmax Delta TRdiff Differential input slew rate for falling edge T RM Vi CK CK and DQS DQS IHdiffmin ILdiffmax VIHdiffmin VILdiffmax DeltaTFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential Input Voltage i e DQS DQS CK CK Vitdiffmin ViLdiffmax Differential Input Slew Rate Definition for DQS DQS and CK CK Rev 1 0 Sep 2012 21 SK yi AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VoH DC DC output high measurement level for IV curve linearity 0 8 x Vppo V VoM DO
35. e Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Joni Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 83 AL 0 CS High between ACT RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 0 Sep 2012 36 SK yi Symbol Description Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Jpp2N Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Ipp2nT Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 Prechar
36. elow Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VoL ac VoH AC Vouacy VoL ac l DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Vouacy VoL ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test me eene VoH Ac V Single Ended Output Voltage I e DQ Poe he SSS SSeS Se SS Voiac Delta TFse Single Ended Output slew Rate Definition Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Parameter Symbol Min Max Min Max Min Max Min Max Units Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 2 5 5 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either f
37. eserved Future Use 1 TEST pin 125 is reserved for bus analysis probes and is NC on normal memory modules 2 This address might be connected to NC balls of the DRAMs depending on density either way they will be con nected to the termination resistor Rev 1 0 Sep 2012 SK yi Functional Block Diagram 2GB 256Mx64 Module 1Rank of x8 ake Sis s LII HH L SCL SCL 240ohm 240ohm Temp Sensor Basa 7 DQS no DGS1 AA Dos NT SAO Ao Temp Senso pon v QS zQ wW WQS ZQ M SAL Al lt gt SDA VVV DM VV DM A2 DQ 0 7 A DQ 0 7 DQ 8 15 WA DQ 0 7 EVENT rhe SPD D0 D4 EVENT integrated with the Temp z Sensor or may be am 9 o a separate component Ej Z sasa Z _ S80 A0 spp Uu w uu e Uu w W e BeBe 5 8 I l l 5S8 5 oes E R T WP 4 Vet gt YVtt VppS PD gt SPD TS DQS2 VW Das neue DQS3 V DoS eye VECA p D0 D7 Le EO 6 TH Dos Z p ANN bos ZQ M _ VREFDQ D0 D7 VVV DM TDM 3 16 23 AAN 1DQ 0 7 DQ 24 31 WW4DQ 0 7 VDD 4 p D0 D7 D1 D5 Vss
38. g on timing but adds a restriction on the common mode characteristics of these signals Rev 1 0 Sep 2012 18 SK yi Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 amp 1600 Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 26 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the req
39. g tables in Table 46 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC Input Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 Symbol Parameter Unit Notes Min Max Min Max VIH DQ DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 1 5 VIL DQ DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH DQ AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL DQ AC175 AC input logic low Note2 Vref 0 175 V 11 2 8 VIH DQ AC150 AC Input logic high Vref 0 150 Note2 Vref 0 150 Note2 V 1 2 7 VIL DQ AC150 AC input logic low Note2 Vref 0 150 Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high V 1 2 7 VIL CA AC135 AC input logic low V 1 2 8 Vnerba c eee DAMTDUE 049 VDD 051 VDD 049 VDD 051 VDD V 3 4 Notes 1 Vref VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 26 3 The ac peak noise on Vref may not allow Vper to deviate from Vgerpo pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH DQ DC100 6 VIL dc is used as a simplified symbol for VIL DQ DC100 7 VIH ac is used as simplified symbol for VIH DQ AC175 VIH DQ AC150 and VIH DQ AC135 VIH DQ AC175 value is used when Vref 0 175V is referenced VIH DQ AC150 value is
40. ge Power Down Current Slow Exit Eso CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Precharge Power Down Current Fast Exit rm CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Precharge Quiet Standby Current Te CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank JppsN Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Active Power Down Current as CKE Low External clock On tCK
41. i L4 Dii D4 6 D14 opti penis however DQ DM DQS and DQS rela Rank 0 tionships are maintained as shown EVENT gt Temp sensor Rank 1 RESET gt 00515 Rev 1 0 Sep 2012 10 SK yi Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD voltage on VDD pin relative to Vss 04V 18V V 1 3 VDDQ voltage on VDDQ pin relative to Vss 0 4V 18V V 1 3 Vin Vout Voltage on any pin relative to Vss 04V 18V V 1 Tsra Storage Temperature 55 to 100 C 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mv DRAM Component Operating Temperature Range Temperature Range
42. ment Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul Channel IDDQ IDDQ IO Power Simulation Simulation Simulation X Correction Channel IO Power Number Figure 2 Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 0 Sep 2012 35 De SK hynix Table 1 Timings used for IDD and IDDQ Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 Symbol Unit 7 7 7 9 9 9 11 11 11 lex 1 875 1 5 1 25 ns CL 7 9 11 nCK Trcp 7 9 11 nCK IRC 27 33 39 nCK IRAS 20 24 28 nCK Tp 7 9 11 nCK 1KB page size 20 20 24 nCK MEAW 2KB page size 27 30 32 nCK 1KB page size 4 4 5 nCK ARRD 2KB page size 6 5 6 nCK Igrc 512Mb 48 60 72 nCK Rrc L Gb 59 74 88 nCK Igrc 2 Gb 86 107 128 nCK Igrc 4 Gb 139 174 208 nCK Igrc 8 Gb 187 234 280 nCK Table 2 Basic IDD and IDDQ Measurement Conditions Symbol Description Ippo Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 83 AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 se
43. n tCK CL nRFC see Table 1 BL 83 AL 0 CS High between REF Command JppsB Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Ippe Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range Tcase 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended DD6ET CKE Low External clock Off CK and CK LOW CL see Table 1 BL 83 AL 0 CS Command Address Bank Address Inputs Data IO MID_LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 1 0 Sep 2012 38 SK yi Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 8 AL CL 1
44. o DIMM SPD information DRAM is required to support CL5 CL5 is not manda tory in SPD coding DDR3 SDRAM devices supporting optional down binning to CL 11 CL 9 and CL 7 tAA tRCD tRPmin must be 13 125ns SPD setting must be programed to match For example DDR3 1866M devices sup porting down binning to DDR3 1600K or DDR3 1333H or 1066F should program 13 125ns in SPD bytes for tAAmin byte16 tRCDmin byte18 and tRPmin byte20 Once tRP byte20 is programmed to 13 125ns tRCmin byte 21 23 also should be programmed accordingly For example 47 125ns tRASmin tRPmin 34ns 13 125ns Rev 1 0 Sep 2012 33 De SK hynix IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure 1 shows the setup and test load for IDD and IDDQ measurements IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD currents IDDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM
45. ommand until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 T 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 7 seven eGR Me Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 Ee SL Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 l c aa i Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Sep 2012 45 SK yi IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec The actual measurements may vary according to DQ loading cap 2GB 256M x 64 SO DIMM HMT325S6CFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 320 320 360 mA IDD1 400 400 440 mA IDD2N 160 160 200 mA IDD2NT 200 200 240 mA IDD2PO 96 96 96 mA IDD2P1 120 120 120 mA IDD
46. rom high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DQ signal switching in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 0 Sep 2012 23 SK yi Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and Figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoL diff AC Vonadit AC Vonair ACy VoL ditt ac DeltaTRdi Differential output slew rate for falling edge Voudiff AC Vordit Ac VoHair acy Votaitt acyl DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test Vondifi AC Differential Output Voltage i e DQS DQS SSS SSS SS SS SS SS SS SS SSS Votdiff AC Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Parameter Symbol Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 5 12 Vins Description SR Slew Rate Q Query Output like in DQ which stand
47. s for Data in Query Output diff Differential Signals For Ron RZQ 7 setting Units Rev 1 0 Sep 2012 24 SK yi Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ 25 Ohm DUT VTT VDDQ 2 ag 8 Reference Load for AC Timing and Output Slew Rate Rev 1 0 Sep 2012 25 SK yi Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 V
48. sks associated with one data byte In Write mode DM operates as a DM 7 0 IN Hiah byte mask by allowing input data to be written if it is low but blocks the write operation 9 if it is high In Read mode DM lines have no effect Vom YoDSPD Suppi lies f Serial for th Vss upply Power supplies for core I O Serial Presence Detect and ground for the module The data strobes associated with one data byte sourced with data transfers In Write DOS 7 0 mode the data strobe is sourced by the controller and is centered in the data window DQS 7 0 I O Cross Point In Read mode the data strobe is sourced by the DDR3 SDRAMs and is sent at the lead ing edge of the data window DQS signals are complements and timing is relative to the crosspoint of respective DQS and DQS SA 1 0 IN _ These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range Rev 1 0 Sep 2012 SK yi Symbol Type Polarity Function This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor SDA I O must be connected from the SDA bus line to Vppspp on the system planar to act as a pullup SCL IN This signal is used to clock data into and out of the SPD EEPROM A resistor may be con nected from the SCL bus time to Vppspp on the system planar to act as a pullup OUT This signal indicates that a thermal event has been detected in the thermal sensing
49. t is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K For CL5 support refer t
50. uirements in the table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS y cml M K Vix acu uec qe um veros d osea tem olt j Vix N CENA d VSEH Vix Definition Rev 1 0 Sep 2012 VDD CK DQS VDD 2 CK DQS VSEL VSS 19 SK yi Cross point voltage for differential input signals CK DQS DDR3 800 1066 1333 1600 Parameter Unit Notes Min Max Vi CK Differential Input Cross Point Voltage 150 150 mV 2 IX relative to VDD 2 for CK CK 175 175 mV 1 Differential Input Cross Point Voltage f XS relative to VDD 2 for DQS DQS 130 130 BI 2 Notes 1 Extended range for Vry is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns Refer to the table Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU on page 19 for VSEL and VSEH standard values 2 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL 25mV VSEH VDD 2 Vix Max 25mV Slew Rate Definitions for Single Ended Input Signals See 7 5 Address Command Setup Hold and Derating in DDR3 Device Operation for single ended slew rate
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