Super Talent Technology 2GB DDR3-1333
Contents
1. 12 0 Physical Dimensions 256Mbx8 Based 256MBx64 1 Rank FRONT JUL Tolerances 0 005 13 unless otherwise specified http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 9 2006 Super Talent Tech Corporation2. Symbol Parameter Min Vpop Supply Voltage 1 425 Supply Voltage for Output 1 425 T O Reference Voltage DQ 0 49 VDpo T O Reference Voltage CMD Add 0 49 Vppo Vppg VreFDQc VrerCA po Ver Termination Voltage 0 49 V ppg 10 0 Capacitance Max Symbol Parameter Condition CCK Input capacitance CK and CK CII Input capacitance CKE and cs CI2 Input capacitance Addr RAS CAS WE CIO Input capacitance DQ DM DQS DQS 11 1 AC Timing Parameters amp Specifications AC operating conditions unless otherwise noted Parameter Symbol DDR3 1333 m n Minimum Clock Cycle Time DLL off mode tCK DLL_OFF 8 ns Average Clock Period tCK avg ps Clock Period tCK abs tCK avg min tJIT per min tCK avg max tJIT per max ps Average high pulse width tCH avg 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 tCK avg Clock Period Jitter tUlT per 80 80 ps Clock Period Jitter during DLL locking period tUlT per Ick 80 80 ps Cycle to Cycle Period Jitter tJIT cc 160 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc Ick 140 ps Cumulative error across 2 cycles tERR 2per 118 ps Cumulative error across 3 cycles tERR 3per ps Cumulative error ac
3. nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK AVG nCK http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 7 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 3 AC Timing Parameters amp Specifications con t Parameter Symbol DDR3 1333 m n Multi Purpose Register Recovery Time tMPRR 1 ACTIVE to PRECHARGE command period tRAS 36 ACTIVE to ACTIVE command period for 1KB page size tRRD max 4tCK 6ns ACTIVE to ACTIVE command period for 2KB page size tRRD max 4tCK 7 5ns Four activate window for 1KB page size tFAW 30 Four activate window for 2KB page size tFAW 45 Command and Address setup time to CK CK referenced to Vih ac Vil ac levels tIS base 65 Command and Address hold time from CK CK referenced to Vih ac Vil ac levels tlH base 140 Command and Address setup time to CK CK referenced to Vih ac Vil ac levels tlS base AC150 654125 Control amp Address Input pulse width for each input tIPW 620 Calibration Timing Power up and RESET calibration time tZQinitl Normal operation Full calibration time tZQoper Normal operation short calibration time tZQCS Reset Timing
4. tWRPDEN WL 2 tWR tCK avg http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 8 SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 4 AC Timing Parameters amp Specifications con t Parameter Symbol DDR3 1333 min Timing of WRA command to Power Down entry BL4MRS tWRAPDEN WL 2 WR 1 Timing of REF command to Power Down entry tREFPDEN 1 Timing of MRS command to Power Down entry tMRSPDEN tMOD min ODT Timing ODT high time without write command or with wirte commandand BC4 ODTH4 ODT high time with Write command and BL8 amp ODTH8 Asynchronous RTT tum on delay Power Down with DLL frozen tAONPD ns Asynchronous RTT tum off delay Power Down with DLL frozen tAOFPD ns ODT turn on tAON ps RTT_NOM and RTT_WR turn off time from ODTL off reference tAOF tCK avg RTT dynamic change skew tADC tCK avg Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed tWLMRD DQS DQS delay after tDQS margining mode is programmed tWLDQSEN Setup time for tDQSS latch tWLS Hold time of tDQSS latch tWLH Write leveling output delay tWLO Write leveling output error tWLOE
5. Exit Reset from CKE HIGH to a valid command max 5tCK tRFC 10ns Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL tXS max 5tCK tRFC 10ns Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min Minimum CKE low width for Self refresh entry to exit timing tCKESR iCKE min 1tCK Valid Clock Requirement after Self Refresh Entry SRE tCKSRE max 5tCK 10ns Valid Clock Requirement before Self Refresh Exit SRX tCKSRX max 5tCK 10ns Power Down Timing Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLLfrozen to commands not requiring a locked DLL tXP max 3tCK 6ns Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLL max 10tCK 24ns CKE minimum pulse width tCKE max 3tCK 5 625ns Command pass disable delay tCPDED 1 Power Down Entry to Exit Timing tPD tCKE min 9 tREFI iming of ACT command to Power Down entry tACTPDEN 1 Timing of PRE command to Power Down entry tPRPDEN 1 Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 Timing of WR command to Power Down entry BL8OTF BL8MRS BL4OTF tWRPDEN WL 4 tWR tCK Timing of WRA command to Power Down entry BL8OTF BL8MRS BL4OTF tWRAPDEN WL 4 WR 1 Timing of WR command to Power Down entry BL4MRS
6. levels tDS base ps Data hold time to DQS DQS referenced to Vih ac Vil ac levels tDH base ps DQ and DM Input pulse width for each input tDIPW ps Data Strobe Timing DQS DQS READ Preamble tRPRE 0 9 tCK DQS DQS differential READ Postamble tRPST 0 3 tCK DQS DQS output high time tQSH 0 4 tCK avg DQS DQS output low time tQSL 0 4 tCK avg DQS DQS WRITE Preamble tWPRE 0 9 tCK DQS DQS WRITE Postamble tWPST 0 3 tCK DQS DQS rising edge output access time from rising CK CK tDQSCK 255 ps DQS DQS low impedance time Referenced from RL 1 tLZ DQS 500 ps DQS DQS high impedance time Referenced from RL BL 2 tHZ DQS 250 ps DQS DQS differential input low pulse width tDQSL 0 45 tCK DQS DQS differential input high pulse width tDQSH 0 45 tCK DQS DQS rising edge to CK CK rising edge tDQSS 0 25 tCK avg DQS DQS faling edge setup time to CK CK rising edge tDSS 0 2 tCK avg DQS DQS faling edge hold time to CK CK rising edge tDSH 0 2 tCK avg DLL locking time tDLLK 512 nCK max 4tCK 7 5ns F j F max Delay from start of internal write transaction to internal read command tWTR 4tCK 7 5ns internal READ Command to PRECHARGE Command delay tRTP WRITE recovery time tWR 15 Mode Register Set command cycle time tMRD 4 max Mode Register Set command update delay tMOD 12tCK 15ns CAS to CAS command delay tCCD 4
7. 006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 8 0 Functional Block Diagram 2GB 256Mx64 Module Populated as 1 ranks of x8 Sog Balzo Aliaz RAS Case WEF CKEO opTo RESET Q g d Q Q Q Q Q Q Q Q zQ BA 2 0 DDR3 SDRAM 4 14 13 0 DDR3 SDRAM RASS DDR3 SORAM M CASE DDR3 SDRAM WE DDR3 SDRAM CKE DDR3 SORAM r OOTO DORI SDRAM r RESETE DOFS SORAM Address command comtrol and clock line terminations CKEO A 14 1320 DDR3 SDRAM RASS CASS WES 50 COTO BA 220 cKo che Note DDR3 SDRAM L w SPD EEPROM soa ame pj 02 SORA qea a a l Ve SAD SAI SAR Voose _ gt SPD EEPROM Vo gt DDR3 SDRAM Address command and control termination DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM 1 The ZQ ball on each DDR3 component is connected to an external 2400 1 resistor that is tied to ground It is used for the calibration of the component s ODT and output driver http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 5 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 9 0 AC amp DC Operating Conditions Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C
8. CKE1 DQ45 Vss DQ12 50 CKEO 170 Vpp Vss DQ8 DQ13 51 Vpop 171 A15 s DM5 DQS14_P DQ9 Vss 52 BA2 172 DQS14_N Vss DMI1 DQS10_P 53 NC Err Out 173 Vpp Vss DQSI_N DQSIO_N 54 Vopp 174 DQ46 DQS2_P Vss 55 All 175 A9 DQ47 Vss DQ14 56 A7 176 Vopp Vss DQ10 DQ15 57 Vpp 177 A8 s DQ52 DQI11 Vss 58 A5 178 A6 DQ53 Vss DQ20 59 A4 179 Vopp Vss DQ16 DQ21 60 Vpp 180 DM6_DQS15_P DQ17 Vss 61 A2 181 DQSI5_N Vss DQS11_P 62 Vpop 182 Vss DQS2_N DQSI1_N 63 CKI_P NC 183 s DQ54 DQS2_P Vss 64 CKI_N NC 184 CKO_P DQ55 Vss DQ22 65 Vpop 185 CKO_N Vss DQ18 DQ23 66 Vpop 186 VDD DQ60 DQ19 Vss 67 VrerCA 187 NC EVENT DQ61 Vss DQ28 68 NC Par_In 188 AO Vss DQ24 DQ29 69 Vpop 189 Vpop DM7 DQS16_P DQ25 Vss 70 A10 AP 190 DQSI6_N Vss DM3 DQS12_P 71 BAO 191 Vss DQ3_N 153 DQSI12_N 72 Vpop 192 DQ62 DQ3_P Vss 73 WE 193 DQ63 Vss 155 DQ30 74 CAS 194 Vss DQ26 156 DQ31 75 Vpop 195 s VppSPD DQ27 157 Vss 76 S1 196 SA1 Vss NC 77 ODT1 197 NC 159 NC 78 Vpp 198 Vss NC 160 Vss 79 S2 NC 199 S Vor 80 Vss 200 1 NC No Connect RFU Reserved for Future Use 2 Par_in and Err_out pins are intended for register control functions O oo NoU FWY ee o http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 3 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIM
9. M DDR3 SDRAM 6 0 DIMM Pin Description Pin Name Function Pin Name Function AO A15 Address input Multiplexed ODT0 ODT1 On Die Termination A10 AP Address Input Auto pre charge CBO CB7 ECC Data check bits Input Output BAO BA2 Bank Select DQ0 DQ63 Data Input Output CKO CK2 CK0 CK2 Clock input DQS0 DQS8 Data strobes negative line CKEO CKE1 Clock enable input DM 0 8 Data Masks Data strobes Read 0 S1 Chip select input DQS0 DQS8 Data Strobes RAS Row address strobe RFU Reserved for future used CAS Column address strobe Ver SDRAM I O termination power supply WE Write Enable Memory bus test tool SCL SPD Clock Input Core Power SDA SPD Data Input Output T O Power SA0 SA2 SPD Address Ground Par_In Parity bit for address amp Control bus SDRAM Input Output Reference Supply Err_Out Parity error found in the Address and Control bus Serial EEPROM Power Supply RESET Register and PLL control pin Command Address Reference Supply 7 0 Address Configuration Organization Row Address Column Address Bank Address Auto Pre charge 256Mx8 2Gb base A0 A14 A0 A9 BAO BA2 A10 AP http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 4 2
10. SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM DDR3 Unbuffered DIMM Module 2GB based on 2Gbit component TFBGA with Pb Free RoHS 2002 95 EC Revision 1 0 MAY 2007 Initial Release http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 1 0 Feature JEDEC standard 1 5V 0 075V Power Supply VDDQ 1 5V 0 075V Programmable CAS latencies 6 7 8 9 10 11 13 Programmable Additive Latency Posted CAS 0 CL 2 or CL 1 clock Programmable CAS Write Latency CWL 5 DDR3 800 6 DDR3 1066 7 DDR3 1333 8 DDR3 1600 and 9 DDR3 1866 400MHz fCK for 800Mb sec pin 533MHz fCK for 1066Mb sec pin 667MHz fCK for 1333Mb sec pin 300MHz fCK for 1600Mb sec pin 900MHz fCK for 1866Mb sec pin Bi directional Differential Data Strobe Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS On Die termination using ODT pin 8 independent internal bank Asynchronous Reset Average Refresh Period 7 8us at lower than a TCASE 85 C 3 9us at 85 C lt TCASE lt 95 C Serial presence detect with EEPROM DIMM Dimension Nominal 30 00 mm high 133 35 mm wide Based on JEDEC standard reference Raw Cards L
11. ay out RoHS compliant Gold plated contacts 2 0 Ordering Information Module Component Component Part number Density Organization composition PKG Description W1333UA2GV 2GB 256Mx64 256Mx8 8 TFBGA 2GB 1Rx8 PC3 10600U 3 0 Key Timing Parameters DDR3 1333 CL tRCD tRP 9 9 9 CAS Latency 9 tCK min 1 5 tRCD min 13 5 tRP min 13 5 tRAS min 36 tRC min 49 5 4 0 Absolute Maximum DC Rating Symbol Parameter Rating Vin Vout Voltage on any pin relative to Vss 0 4 1 975 Vop Voltage on Vpp amp Vppg supply relative to V 0 4 1 975 Vppe Short circuit current 0 4 1 975 VoppL Power dissipation 0 4 1 975 TstG Storage Temperature 55 100 http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 2 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 5 0 DIMM Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back i i Back VrerDQ 121 Vss 41 Vss 161 DM8 DQS17_P DQ37 Vss 122 DQ4 42 NC 162 DQSI7_N Vss DQO DQ5 43 NC 163 Vss s DM4 DQS13_P DQ1 124 Vss 44 Vss 164 NC DQS13_N Vss DM0 DQS9_P 45 NC 165 NC Vss DQSO_N NC DQS9_N 46 NC 166 Vss S DQ38 DQSO_P Vss 47 Vss 167 NC TEST DQ39 Vss DQ6 48 NC 168 RESET_N Vss DQ2 DQ7 KEY s DQ44 DQ3 Vss 49 NC 169
12. ross 4 cycles tERR 4per ps Cumulative error across 5 cycles tERR 5per ps Cumulative error across 6 cycles tERR 6per ps Cumulative error across 7 cycles tERR 7per ps Cumulative error across 8 cycles tERR 8per ps Cumulative error across 9 cycles tERR 9per ps Cumulative error across 10 cycles tERR 10per ps http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 6 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 2 AC Timing Parameters amp Specifications con t DDR3 1333 Parameter Symbol m n Cumulative error across 11 cycles tERR 11per 210 210 ps Cumulative error across 12 cycles tERR 12per 215 215 ps tERR nper min 1 0 68in n tJIT per min tERR nper max 1 0 1 0 68In n tJIT per max ps Absolute clock HIGH pulse width tCH abs 0 43 tCK avg Cumulative error across n 13 14 49 50 cycles tERR nper Absolute clock Low pulse width tCL abs 0 43 tCK avg Data Timing DQS DQS to DQ skew per group per access tDQSQ ps DQ output hold time from DQS DQS tQH tCK avg DQ low impedance time from CK CK tLZ DQ ps DQ high impedance time from CK CK tHZ DQ ps Data setup time to DQS DQS referenced to Vih ac Vil ac
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