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Intel Core i7-3920XM Extreme

1. 2 11 PCI Device 6 Extended Configuration Registers Table 2 14 PCI Device 6 Extended Configuration Register Address Map garg Symbol Register Name Reset Value Access 0 103h RSVD Reserved Oh RO 104 107h PVCCAP1 Port VC Capability Register 1 00000000h RO 108 10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO 10C 10Dh PVCCTL Port VC Control 0000h RW RO 10E 10Fh RSVD Reserved Oh RO 110 113h VCORCAP VCO Resource Capability 00000001h RO 114 117h VCORCTL VCO Resource Control 800000FFh RO RW 118 119h RSVD Reserved Oh RO 11A 11Bh VCORSTS VCO Resource Status 0002h RO V 11C 13Fh RSVD Reserved Oh RO 140 143h RCLDECH Root Complex Link Declaration Enhanced 00010005h RO V RO 144 147h ESD Element Self Description 05000100h RO RW O 148 14Fh RSVD Reserved Oh RO 150 153h LE1D Link Entry 1 Description 00000000h RO RW O 154 157h RSVD Reserved Oh RO 158 15Bh LE1A Link Entry 1 Address 00000000h RW O 15C 15Fh LE1AH Link Entry 1 Address 00000000h RW O 160 23Fh RSVD Reserved Oh RO 240 243h APICBASE APIC Base address 00000000h RW 244 247h APICLIMIT APIC Base address Limit 00000000h RW 248 C33h RSVD Reserved C34 C37h CMNRXERR Common Rx Error Register 00000000h RW1icS C38 DOBh RSVD Reserved Oh RO DOC DOFh PEGTST PCI Express Test Modes 00000000h ROTW D10 D33h RSVD Reserved Oh RO D34 D37h PEGUPDNCFG PEG UPconfig DNconfig Control 0000001Fh S D38 D6Bh
2. get sa a Register Name Reset Value Access 0 3FFFh RSVD Reserved Oh RO 4000 4003h TC_DBP_CO Timing of DDR bin parameters 00146666h RW L 4004 4007h TC_RAP_CO Timing of DDR regular access parameters 86104344h RW L 4008 4027h RSVD Reserved 4028 402Bh Dee IO Latency configuration 000E0000h RW L 402C 409Fh RSVD Reserved 40A0 40A3h ee Coe Power down configuration register 00000000h RW L 40A4 40B3h RSVD Reserved 40BC 40C7h RSVD Reserved Oh RO 40D0 4293h RSVD Reserved 4294 4297h TC_RFP_CO Refresh Parameters 0000980Fh RW L 4298 429Bh TC_RFTP_CO Refresh Timing Parameters 46B41004h RW L 429C 438Fh RSVD Reserved Datasheet Volume 2 239 intel Processor Configuration Registers 2 13 1 TC_DBP_CO Timing of DDR Bin Parameters Register This register defines the BIN timing parameters for safe logic tRCD tRP tCL tWCL and tRAS B D F Type 0 0 0 MCHBAR MCO Address Offset 4000 4003h Reset Value 00146666h Access RW L Size 32 bits BIOS Optimal Default 00h e Reset RST Se Bit Access Value PWR Description 31 24 RO Oh Reserved RSVD tRAS in DCLK cycles tRAS 231G Rw aah ZER Minimum ACT to PRE timing Range is 10 to 40 DCLK cycles Write CAS latency in DCLK cycles tWCL d Delay from CAS WR command to data valid on DDR pins Range 15 12 RW L 6h ZE is 5 15 The value 5 should not be programmed if the DEC_WRD bit in TC_RWP register i
3. B D F Type 0 0 0 MCHBAR PCU Address Offset 5888 588Bh Reset Value OOE4DADOh Access RW Size 32 bits BIOS Optimal Default OOEDADOh Reset RST er Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD Hot Threshold Enable HOT_THRESHOLD_ENABLE 1 RW 1 en 3 b Se This bit must be set to allow the hot threshold Hot Threshold HOT_THRESHOLD f This threshold defines what is the acceptable temperature SR SE 1910101b See limitation When this threshold is crossed severe throttling takes place The self refresh is also at double rate Warm Threshold Enable WARM_THRESHOLD_ENABLE on 1b EES This bit must be set to allow the warm threshold Warm Threshold WARM_THRESHOLD e The warm temperature threshold defines when the self refresh is 6 0 RW 1010 b 910999 ZPS at double rate Throttling can also be applied at this threshold based on the configuration in the memory controller Datasheet Volume 2 Processor Configuration Registers 2 19 3 MEM_TRML_STATUS_REPORT Memory Thermal Status Report Register This register reports the thermal status of DRAM intel B D F Type 0 0 0 MCHBAR PCU Address Offset 58A0 58A3h Reset Value 00000000h Access RO V Size 32 bits BIOS Optimal Default 00h Bit Access ere et Description 31 25 RO Oh Reserved RSVD Double Self refresh DSR 24 RO V Ob Uncore 0 Normal self refresh 1 Double self refresh 23 16 RO V 00h Uncore Re
4. B D F Type 0 0 0 DMIBAR Address Offset 5C 5Fh Reset Value 00000000h Access RW O Size 32 bits BIOS Optimal Default 000000h P Reset RST PRP Bit Access Value PWR Description 31 8 RO Oh Reserved RSVD Upper Link Address ULA 7 0 RW O 00h Uncore Memory mapped base address of the RCRB that is the target element egress port of PCH for this link entry Datasheet Volume 2 231 Processor Configuration Registers intel 2 12 22 DMILE2D DMI Link Entry 2 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 60 63h Reset Value 00000000h Access RO RW O Size 32 bits BIOS Optimal Default 0000h Reset RST Bit Access Value PWR Description Target Port Number TPN This field specifies the port number associated with the element 31 24 RO 00h Uncore targeted by this link entry Egress Port The target port number is with respect to the component that contains this element as specified by the target component ID Target Component ID TCID This field identifies the physical or logical component that is 23 16 RW O 00h Uncore targeted by ele link entry BIOS Requirement This field must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 RO Oh Reserved RS
5. 101 CAPPTR Capabilities Pointer Register 101 INTRLINE Interrupt Line Register 102 INTRPIN Interrupt Pin Register 102 BCTRL Bridge Control Register SNKEKEKNNKS NENNEN NENNEN e aa RNER ENN 103 PM_CAPID Power Management Capabilities Register 104 Datasheet Volume 2 2 6 26 PM_CS Power Management Control Status Register ccccseeeeeeaeeaeees 105 2 6 27 SS _CAPID Subsystem ID and Vendor ID Capabilities Register 107 2 6 28 SS Subsystem ID and Subsystem Vendor IDRegister cne 107 2 6 29 MSI_CAPID Message Signaled Interrupts Capability ID Register 108 2 6 30 MC Message Control Register 0 ceccceeseeeseeseeceeeececeeeaeeeeaeanasasaeeeeneees 109 2 6 31 MA Message Address Register 110 2 6 32 MD Me ssage Data REGISCED 2 29 eg s deed ANEN ca ted eee tear ceed 110 2 6 33 PEG_CAPL PCI Express G Capability List Register 110 2 6 34 PEG_CAP PCI Express G Capabilities Reolster eee ee eee 111 2 6 35 DCAP Device Capabilities Register 111 2 6 36 DCTL Device Control Register 112 2 6 37 DS1S Device Status Registers a siiidichie ege ana EE ccteeesaeheees 113 2 6 38 LCAP Link Capabilities Register 114 2 6 39 LCTL Link Control Registe incite SEENEN NENNEN ENNEN NS dee 116 2 6 40 LSTS LINK Status R glstet ue kt en ss ge ah SD NEE at NEEN ee A seu NEEN 118 2 6 41 SLOTCAP Slot Capabilities Register 119 2 6 42 SLOTCTL Slot Control Re
6. eeeeeeeeeeees 330 2 21 16 PLMLIMIT_REG Protected Low Memory Limit Register 331 2 21 17 PHMBASE_REG Protected High Memory Base Register 332 2 21 18 PHMLIMIT_REG Protected High Memory Limit Register assesseer 333 2 21 19 IQH_REG Invalidation Queue Head Register 334 2 21 20 IQT_REG Invalidation Queue Tail Register 334 2 21 21 IQA _REG Invalidation Queue Address Register 335 2 21 22 ICS_REG Invalidation Completion Status Register 336 2 21 23 IECTL_REG Invalidation Event Control Register 336 2 21 24 IEDATA_REG Invalidation Event Data Register 337 2 21 25 IEADDR_REG Invalidation Event Address Register 338 2 21 26 IEUADDR_REG Invalidation Event Upper Address Register 338 2 21 27 IRTA_REG Interrupt Remapping Table Address Register 339 2 21 28 IVA_REG Invalidate Address Register 340 2 21 29 IOTLB_REG IOTLB Invalidate Register 341 Datasheet Volume 2 9 Figures Tables 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 System Address Range EXaMple e Lou SKS EE NEE REENEN iaaa a EE aE 19 DOS L gacy Address RANGES ex ENNEN E NESE ASSEN RN nna a NEREEEN SNE NEE NENNEN 20 Main Memory Address Range 22 PCI Memory Address Rangen apegu g gegen ge AER EE E SEENEN 26 Case 1 Less than A GB of Physical Memory NO remap eect ee ee eee eee eeeaee 31 Case 2
7. RO Reserved for Attention Button Pressed Enable ABPE Ob Uncore When set to 1b this bit enables software notification on an attention button pressed event 122 Datasheet Volume 2 Processor Configuration Registers D 2 6 43 SLOTSTS Slot Status Register This is a PCI Express Slot related register B D F Type 0 1 0 2 PCI Address Offset BA BBh Reset Value 0000h Access RO RW1C RO V Size 16 bits BIOS Optimal Default 00h Reset RST SCH Bit Access Value PWR Description 15 9 RO Oh Reserved RSVD Reserved for Data Link Layer State Changed DLLSC This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed In response to 8 RO Ob Uncore a Data Link Layer State Changed event software must read the Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device Reserved for Electromechanical Interlock Status EIS If an Electromechanical Interlock is implemented this bit 7 RO Ob Uncore indicates the current status of the Electromechanical Interlock 0 Electromechanical Interlock Disengaged 1 Electromechanical Interlock Engaged Presence Detect State PDS In band presence detect state 0 Slot Empty 1 Card present in slot This bit indicates the presence of an adapter in the slot reflected by t
8. 6 4 3 0 RW RW Lane 0 Upstream Component Receiver Preset Hint UCRPHO Receiver Preset Hint for Upstream Component The upstream 000b Uncore dan g SE component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO Transmitter Preset for an Upstream Component See the PCIe 1000b U oo E Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 144 Datasheet Volume 2 Processor Configuration Registers intel 2 7 15 EQCTL14_15 Lane 14 15 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane B D F Type 0 1 0 MMR Address Offset DBC DBFh Reset Value 07080708h Access RW Size 32 bits BIOS Optimal Default Oh e Reset RST A Bit Access Value PWR Description 31 RO Oh Reserved RSVD Lane 1 Downstream Component Receiver Preset Hint DCRPH1 S Receiver Preset Hint for Downstream Component The Upstream 30 2 RW 000b U EES Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Downstream Component Transmitter Preset DCTP1 S Transmitter Preset for Downstream C
9. Datasheet Volume 2 Processor Configuration Registers intel 2 6 44 RCTL Root Control Register This register allows control of PCI Express Root Complex specific parameters The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register B D F Type 0 1 0 2 PCI Address Offset BC BDh Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 0000h 3 Reset RST Pare Bit Access Value PWR Description 15 5 RO Oh Reserved RSVD Reserved for CRS Software Visibility Enable CSVE This bit when set enables the Root Port to return Configuration 4 RO Ob Uncore Request Retry Status CRS Completion Status to software Root Ports that do not implement this capability must hardwire this bit to Ob PME Interrupt Enable PMEIE 0 No interrupts are generated as a result of receiving PME messages 1 Enables interrupt generation upon receipt of a PME message 3 RW Ob Uncore as reflected in the PME Status bit of the Root Status Register A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state If the bit change from 1 to 0 and interrupt is pending than
10. 3 2 RO Oh Reserved RSVD 1 0 RW 00b Uncore 0E8000 0EBFFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OE8000h to OEBFFFh 00 DRAM Disabled All reads are sent to DRAM All writes are forwarded to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 71 72 Processor Configuration Registers LAC Legacy Access Control Register This 8 bit register controls steering of MDA cycles and a fixed DRAM hole from 15 16 MB There can only be at most one MDA device in the system Access Size B D F Type Address Offset Reset Value 0 0 0 PCI 87h 00h RW 8 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description RW Ob Uncore Hole Enable HEN This field enables a memory hole in DRAM space The DRAM that lies behind this space is not remapped 0 No memory hole 1 Memory hole from 15 MB to 16 MB This bit is Intel TXT lockable 6 4 RO Oh Reserved RSVD RW Ob Uncore PEG60 MDA Present MDAP60 This bit works with the VGA Enable bits in the BCTRL register of Device 6 Funct
11. 6 4 3 0 RW RW Lane 0 Upstream Component Receiver Preset Hint UCRPHO Receiver Preset Hint for Upstream Component The upstream 000b Uncore dan g SE component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO Transmitter Preset for an Upstream Component See the PCIe 1000b U oo E Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 142 Datasheet Volume 2 Processor Configuration Registers intel 2 7 13 EQCTL10_11 Lane 10 11 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane B D F Type 0 1 0 MMR Address Offset DB4 DB7h Reset Value 07080708h Access RW Size 32 bits BIOS Optimal Default Oh p Reset RST Ge Bit Access Value PWR Description 31 RO Oh Reserved RSVD Lane 1 Downstream Component Receiver Preset Hint DCRPH1 S Receiver Preset Hint for Downstream Component The Upstream 30 2 RW 000b U EES Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Downstream Component Transmitter Preset DCTP1 S Transmitter Preset for Downstream C
12. 1 For security reasons the processor will now positively decode FFE0_0000h to FFFF_FFFFh to DMI This ensures the boot vector and BIOS execute off PCH ALL of these ranges MUST be unique and NON OVERLAPPING It is the BIOS or system designers responsibility to limit memory population so that adequate PCI PCI Express High BIOS PCI Express Memory Mapped space and APIC memory space can be allocated In the case of overlapping ranges with memory the memory decode will be given priority This is an Intel TXT requirement It is necessary to get Intel TXT protection checks avoiding potential attacks There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges 5 Accesses to overlapped ranges may produce indeterminate results 6 The only peer to peer cycles allowed below the Top of Low Usable memory register TOLUD are DMI Interface to PCI Express VGA range writes Note that peer to peer cycles to the Internal Graphics VGA range are not supported Figure 2 1 shows the system memory address map in a simplified form Datasheet Volume 2 Processor Configura Figure 2 1 tion Registers System Address Range Example intel Host System View Physical Memory DRAM Controller View 512 GB PCI Memory Add Range subtractively decoded to TOUUD BASE DMI TOM Reclaim Limit Reclaim Base x Ma 1 MB aligned Memory ME UMA Reclaim Recl
13. B D F Type 0 1 0 MMR Address Offset DD8 DDBh Reset Value F9404400h Access RW Size 32 bits BIOS Optimal Default Oh d Reset RST Pare Bit Access Value PWR Description Bypass Coefficients During Phase 3 BYPCOEFPH3 Bit 0 Controls the value of bit 7 in Symbol 6 of EQ TSis during Bypass Phase 3 Adaptation 1 use preset 0 use coefficients 5 2 RW Oh Uncore The preset is defined by the per lane DCTP field in EQCTL register Coefficient values are defined within the appropriate EQPRESET register using DCTP as an index Bits 3 1 Undefined Bypass Phase 3 Adaptation FSM BYPADFSM When set when Phase 3 is entered bypass coefficients will be sent to the link partner When the coefficients are accepted by 1 RW Db nears the link partner no adaptation will be done and Phase 3 will be complete This bit needs to be set before phase 3 start 0 RO Oh Reserved RSVD Datasheet Volume 2 147 Processor Configuration Registers intel 2 8 PCI Device 2 Configuration Space Registers Table 2 11 PCI Device 2 Configuration Space Register Address Map 148 ponies Ken Register Name Reset Value Access 0 1h VID2 Vendor Identification 8086h RO 2 3h DID2 Device Identification 0152h RO V RO FW 4 5h PCICMD2 PCI Command 0000h RW RO 6 7h PCISTS2 PCI Status 0090h RO RO V 8h RID2 Revision Identification 00h RO FW 9 Bh CC Class Code 030000h RO V
14. Clearing this bit has no effect The value returned on a read of this field is undefined RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D 2 18 5 GSTS_REG Global Status Register This register reports general remapping hardware status B D F Type 0 0 0 GFXVTBAR Address Offset 1C 1Fh Reset Value 00000000h Access RO V RO Size 32 bits BIOS Optimal Default 000000h e Reset RST Pare Bit Access Value PWR Description Translation Enable Status TES 31 RO V op Geer This field indicates the status of DMA remapping hardware 0 DMA remapping hardware is not enabled 1 DMA remapping hardware is enabled Root Table Pointer Status RTPS This field indicates the status of the root table pointer in hardware This field is 30 RO V Ob Uncore e cleared by hardware when software sets the SRTP field in the Global Command register e set by hardware when hardware completes the Set Root Table Pointer operation using the value provided in the Root Entry Table Address register Fault Log Status FLS This field is e cleared by hardware when software Sets the SFL field in the 29 RO Ob Uncore Global Command register e set by hardware when hardware completes the Set Fault Log Pointer operation using the value provided in the Advanced Fault Log register Advanced Fault Logging Status AFLS This field is valid only for implementations suppor
15. FLR Reserved for Memory Base Address RSVDRW 63 32 RW GC Uncore Must be set to 0 since addressing above 512 GB is not supported 38 29 RW 00000000 FLR Memory Base Address MBA 00b Uncore set by the OS these bits correspond to address signals 38 29 512 MB Address Mask ADMSK512 FLR This Bit is either part of the Memory Base Address RW or part 28 RW L 0b Uncore of the Address Mask RO depending on the value of MSAC 2 1 See Section 2 8 21 MSAC Multi Size Aperture Control Register on page 159 for details 256 MB Address Mask ADMSK256 FLR This bit is either part of the Memory Base Address RW or part of 27 RW L Ob Uncore the Address Mask RO depending on the value of MSAC 2 1 See Section 2 8 21 MSAC Multi Size Aperture Control Register on page 159 for details Address Mask ADM EES RO DESEN Uneore Hardwired to Os to indicate at least 128 MB address range 3 RO ib Uncor Prefetchable Memory PREFMEM Hardwired to 1 to enable prefetching Memory Type MEMTYP 2 1 RO 10b Uncore 00 32 bit address 10 64 bit address Memory IO Space MIOS 0 RO BH Uncore Hardwired to 0 to indicate memory space Datasheet Volume 2 155 DN t Processor Configuration Registers 2 8 13 156 IOBAR I O Base Address Register This register provides the Base offset of the I O registers within Device 2 Bits 15 6 are programmable allowing the I O Base to be lo
16. 301 2 19 8 RP_STATE_CAP RP State Capability Register 302 2 19 9 PCU_MMIO_FREQ_CLIPPING_CAUSE_STATUS Register 302 2 19 10 PCU_MMIO_FREQ_CLIPPING_CAUSE_LOG Register 304 2 19 11 SSKPD Sticky Scratchpad Data Register c cceseeeeeeeeeeeeeee eee ee eens 306 2 20 PXPEPBAR REGISUEIS 6 ii ccsccsices seer ice o dv eieed dened phe wad dee dE AE steed See 308 2 20 1 EPVCORCTL EP VC 0 Resource Control Register 308 2 21 Default PEG DMI VTd Remapping Engine Registers cceeeeeeeee tees eee eens eee eeeee ae 309 2 21 1 VER REG VersiOMn REOISb t Steeg Se EENN SCENE eeh 310 2 21 2 CAP _REG Capability Reglseber ceeiticcceticctcaninestendvcuniieits ciaeeedanee staat EENS 311 2 21 3 ECAP_REG Extended Capability Register 315 2 21 4 GCMD_REG Global Command Register 316 2 21 5 GSTS_REG Global Status Register 320 2 21 6 RTADDR_REG Root Entry Table Address Regleter nr 321 2 21 7 CCMD_REG Context Command Register 322 2 21 8 FSTS_REG Fault Status Register 324 2 21 9 FECTL_REG Fault Event Control Register 326 2 21 10 FEDATA_REG Fault Event Data Register 327 2 21 11 FEADDR_REG Fault Event Address Register 327 2 21 12 FEUADDR_REG Fault Event Upper Address Register 327 2 21 13 AFLOG_REG Advanced Fault Log Register c ececeeeee tees eeeeeeeeeeeenees 328 2 21 14 PMEN_REG Protected Memory Enable Register 329 2 21 15 PLMBASE_REG Protected Low Memory Base Register
17. Datasheet Volume 2 271 intel 2 18 6 272 Processor Configuration Registers RTADDR_REG Root Entry Table Address Register This register providing the base address of root entry table B D F Type 0 0 0 GFXVTBAR Address Offset 20 27h Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 0000000000h e Reset RST Aer Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Root Table Address RTA This field points to base of page aligned 4 KB sized root entry table in system memory Hardware ignores and not implements bits 63 HAW where HAW is the host address width 38 12 RW 0000000h Uncore Software specifies the base address of the root entry table through this register and programs it in hardware through the SRTP field in the Global Command register Reads of this register returns value that was last programmed to it 11 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers intel 2 18 7 CCMD_REG Context Command Register This register manages context cache The act of writing the uppermost byte of the CCMD_REG with the ICC field set causes the hardware to perform the context cache invalidation Access Size B D F Type Address Offset Reset Value 0 0 0 GFXVTBAR 28 2Fh 0800000000000000h RW RW V RO V 64 bits BIOS Optimal Default 000000000h Bit 63 Access RW V Reset RST Descript
18. Interrupt Connection INTCON This field is used to communicate interrupt line routing 7 0 RW 00h Uncore information POST software writes the routing information into this register as it initializes and configures the system The value in this register indicates to which input of the system interrupt controller the device s interrupt pin is connected INTRPIN Interrupt Pin Register This register tells which interrupt pin the device uses The Integrated Graphics Device uses INTA B D F Type 0 2 0 PCI Address Offset 3Dh Reset Value Oih Access RO Size 8 bits Reset RST Ge Bit Access Value PWR Description Interrupt Pin INTPIN 7 0 RO Oth Uncore As a single function device the IGD specifies INTA as its interrupt pin Oih INTA MINGNT Minimum Grant Register The Integrated Graphics Device has no requirement for the settings of Latency Timers B D F Type 0 2 0 PCI Address Offset 3Eh Reset Value 00h Access RO Size 8 bits e Reset RST se Bit Access Value PWR Description Minimum Grant Value MGV Zb e goh The IGD does not burst as a PCI compliant master Datasheet Volume 2 Processor Configuration Registers intel 2 8 20 MAXLAT Maximum Latency Register The Integrated Graphics Device has no requirement for the settings of Latency Timers B D F Type 0 2 0 PCI Address Offset 3Fh Reset Value 00h Access RO Size 8 bit
19. Master Data Parity Error SMDPE When set indicates that the processor received across the link Uncore upstream a Read Data Completion Poisoned TLP EP 1 This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set RO Ob Fast Back to Back FB2B U dch Not Applicable or Implemented Hardwired to 0 RO Oh Reserved RSVD RO Ob 66 60 MHz capability CAP66 U Gage Not Applicable or Implemented Hardwired to 0 4 0 RO Oh Reserved RSVD 96 Datasheet Volume 2 Processor Configuration Registers D t 2 6 15 MBASE Memory Base Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 2 PCI Address Offset 20 21h Reset Value FFFOh Access RW Size 16 bits BIOS Optimal Default Oh n Reset RST dadi Bit Access Value PWR Description Memor
20. Refresh high priority WM Refresh_HP_WM 11 8 RW L 8h Uncore tREFI count level that turns the refresh priority to high default is Rank idle timer for opportunistic refresh OREF_RI 7 0 RW L OFh Uncore Rank idle period that defines an opportunity for refresh in DCLK cycles Datasheet Volume 2 249 intel Processor Configuration Registers 2 14 6 TC_RFTP_C1i Refresh Timing Parameters Register Thie register provides refresh timing parameters B D F Type 0 0 0 MCHBAR MC1 Address Offset 4698 469Bh Reset Value 46B41004h Access RW L Size 32 bits 2 Reset RST Sat Bit Access Value PWR Description 9 tREFI tREFIx9 e Period of minimum between 9 tREFI and tRAS maximum 1 2 RW L 23h S RES normally 70 us in 1024 DCLK cycles default is 35h need to reduce 100 DCLK cycles uncertainty on timing of panic refresh Refresh Execution Time tRFC 24 16 RW L OB4h Uncore Time of refresh from beginning of refresh until next ACT or refresh is allowed in DCLK cycles default is 180h tREFI Period in DCLK Cycles tREFI 15 0 RW L 1004h Uncore Defines the average period between refreshes and the rate that tREFI counter is incremented in DCLK cycles default is 4100h 2 14 7 TC_SRFTP_Ci Self refresh Timing Parameters Register Thie register provides self refresh timing parameters B D F Type 0 0 0 MCHBAR MCL Address Offset
21. Software may setup the protected high memory region either above or below 4 GB Software must not modify this register when protected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 70 77h Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 000000000000h e Reset RST Saas Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Protected High Memory Base PHMB This register specifies the base of protected high memory 38 20 RW 00000h Uncore region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width 19 0 RO Oh Reserved RSVD Datasheet Volume 2 283 DN t Processor Configuration Registers 2 18 18 284 PHMLIMIT_REG Protected High Memory Limit Register This register sets up the limit address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region limit depends on the number of reserved bits N 0 of this register Software may determine the value of N by writing all 1s to this register and finding most s
22. This register allows software to limit the maximum base frequency for the Integrated Graphics Engine GT allowed during run time B D F Type 0 0 0 MCHBAR PCU Address Offset 5994 5997h Reset Value 000000FFh Access RW Size 32 bits BIOS Optimal Default 000000h 5 Reset RST TRE Bit Access Value PWR Description 31 8 RO Oh Reserved RSVD RP State Limit RPSTT_LIM 7 0 RW FFh Uncore This field indicates the maximum base frequency limit for the Integrated Graphics Engine GT allowed during run time Datasheet Volume 2 301 intel Processor Configuration Registers 2 19 8 RP_STATE_CAP RP State Capability Register This register contains the maximum base frequency capability for the Integrated Graphics Engine GT B D F Type 0 0 0 MCHBAR PCU Address Offset 5998 599Bh Reset Value 00000000h Access RO FW Size 32 bits BIOS Optimal Default 00h Bit Access eid df Description 31 24 RO Oh Reserved RSVD RPN Capability RPN_CAP z This field indicates the maximum RPN base frequency capability 23 16 SES gon creer for the Integrated Graphics Engine GT Values are in units of 100 MHz RP1 Capability RP1_CAP S This field indicates the maximum RP1 base frequency capability 13 8 ROPE oon ZE for the Integrated Graphics Engine GT Values are in units of 100 MHz RPO Capability RPO_CAP 8 This field indicates the maximum RPO base frequency capability 7 0 R
23. stolen from the top of the Host address map The Intel ME stolen memory base is calculated by subtracting the amount of memory stolen by the Intel Management Engine from TOM Only Intel ME can access this space it is not accessible by or coherent with any processor side accesses 2 3 2 PCI Memory Address Range TOLUD 4 GB This address range from the top of low usable DRAM TOLUD to 4 GB is normally mapped to the DMI Interface Device 0 exceptions are 1 Addresses decoded to the egress port registers PXPEPBAR 2 Addresses decoded to the memory mapped range for internal MCH registers MCHBAR 3 Addresses decoded to the registers associated with the MCH PCH Serial Interconnect DMI register memory range DMIBAR For each PCI Express port there are two exceptions to this rule 1 Addresses decoded to the PCI Express Memory Window defined by the MBASE MLIMIT registers are mapped to PCI Express 2 Addresses decoded to the PCI Express prefetchable Memory Window defined by the PMBASE PMLIMIT registers are mapped to PCI Express In integrated graphics configurations there are exceptions to this rule 1 Addresses decoded to the internal graphics translation window GMADR 2 Addresses decoded to the internal graphics translation table or IGD registers GTTMMADR In a VT enabled configuration there are exceptions to this rule 1 Addresses decoded to the memory mapped window to Graphics VT remap engine registers GFXVTB
24. B D F Type 0 0 0 DMIBAR Address Offset 8 Bh Reset Value 00000000h Access RO Size 32 bits BIOS Optimal Default 0000h j Reset RST zis Bit Access Value PWR Description 31 24 RO 00h Uncore Reserved for VC Arbitration Table Offset VCATO 23 8 RO Oh Reserved RSVD 7 0 RO 00h Uncore Reserved for VC Arbitration Capability VCAC Datasheet Volume 2 219 intel Processor Configuration Registers 2 12 4 DMIPVCCTL DMI Port VC Control Register B D F Type 0 0 0 DMIBAR Address Offset C Dh Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 0000h o Reset RST ae Bit Access Value PWR Description 15 4 RO Oh Reserved RSVD VC Arbitration Select VCAS This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field The value 000b when written to this field will indicate the VC arbitration scheme is hardware fixed in the root complex This 3 1 RW 000b Uncore field cannot be modified when more than one VC in the LPVC group is enabled 000 Hardware fixed arbitration scheme such as Round Robin Others Reserved See the PCI express specification for more details 0 RO Ob Uncore Reserved for Load VC Arbitration Table LVCAT 2 12 5 DMIVCORCAP DMI VCO Resource Capability Register B D F Type 0 0 0 DMIBAR Address Offset 10 13h Reset Value 00000001h Access RO Size
25. B D F Type 0 0 0 PCI Address Offset 68 6Fh Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 000000000h Reset RST SEN Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD DMI Base Address DMIBAR This field corresponds to bits 38 12 of the base address DMI configuration space BIOS will program this register resulting in a base address for a 4 KB block of contiguous memory address 38 12 RW 0000000h Uncore space This register ensures that a naturally aligned 4 KB space is allocated within the first 512 GB of addressable memory space System Software uses this base address to program the DMI register set All the bits in this register are locked in Intel TXT mode 11 1 RO Oh Reserved RSVD DMIBAR Enable DMIBAREN 0 Disable DMIBAR is disabled and does not claim any memory 0 RW Ob Uncore 1 Enable DMIBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers D t 2 5 19 Note MESEG_BASE Intel Management Engine Base Address Register This register determines the Base Address register of the memory range that is pre allocated to the Intel Management Engine Together with the MESEG_MASK register it controls the amount of memory allocated to the ME This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0
26. Link Declaration Capability Version LDCV Hardwired to 1 to indicate compliances with the 1 1 version of 19 16 RO Lh Uncore the PCI Express specification Note This version does not change for 2 0 compliance Extended Capability ID ECID 15 0 RO 0005h Uncore a value of 0005h identifies this linked list item capability structure as being for PCI Express Link Declaration Capability 228 Datasheet Volume 2 Processor Configuration Registers intel 2 12 18 DMIESD DMI Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability B D F Type 0 0 0 DMIBAR Address Offset 44 47h Reset Value 01000202h Access RO RW O Size 32 bits BIOS Optimal Default Oh Reset RST Value PWR Description Bit Access Port Number PORTNUM This field specifies the port number associated with this element 31 24 RO Oih Uncore with respect to the component that contains this element This port number value is utilized by the egress port of the component to provide arbitration to this Root Complex Element Component ID CID This field identifies the physical component that contains this Root Complex Element BIOS Requirement This field must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 23 16 RW O 00h Uncore Number of Link Entr
27. Memory Base Address Register ceeeeeeeeeeeee estate eeeeeaeaeees 172 2 10 16 MLIMIT Memory Limit Address Register 173 2 10 17 PMBASE Prefetchable Memory Base Address Register 174 2 10 18 PMLIMIT Prefetchable Memory Limit Address Register 175 2 10 19 PMBASEU Prefetchable Memory Base Address Upper Register 5 176 2 10 20 PMLIMITU Prefetchable Memory Limit Address Upper Register 177 2 10 21 CAPPTR Capabilities Pointer Register 178 2 10 22 INTRLINE Interrupt Line Register 178 2 10 23 INTRPIN Interrupt Pin Register 00 cece teeter ne enna e eee ees 179 2 10 24 BCTRL Bridge Control Register 179 2 10 25 PM_CAPID Power Management Capabilities Register 181 2 10 26 PM_CS Power Management Control Status Register 182 2 10 27 SS _CAPID Subsystem ID and Vendor ID Capabilities Register 184 2 10 28 SS Subsystem ID and Subsystem Vendor ID Register 184 2 10 29 MSI_CAPID Message Signaled Interrupts Capability ID Register 185 2 10 30 MC Message Control Register 185 2 10 31 MA Message Address Register 186 2 10 32 MD Message Data Register 187 2 10 33 PEG_CAPL PCI Express G Capability List Register 187 2 10 34 PEG_CAP PCI Express G Capabilities Register 188 2 10 35 DCAP Device Capabilities Register 188 2 10 36 DCTL Device Control REGiSter cceccceeseessee eens NENNEN NENNEN ENER NEN ENNEN NN 189 2 10 37 D
28. on DIMM B DDR width DBW 20 RW L Ob Uncore 0 X8 chips 1 X16 chips DIMM A DDR width DAW 19 RW L Ob Uncore 0 X8 chips 1 X16 chips DIMM B number of ranks DBNOR 18 RW L Ob Uncore 0 single rank 1 dual rank DIMM A number of ranks DANOR 17 RW L Ob Uncore 0 single rank 1 dual rank DIMM A select DAS Selects which of the DIMMs is DIMM A should be the larger 16 RW L Ob Uncore DIMM 0 DIMM O 1 DIMM 1 Size of DIMM B DIMM_B_Size 13 8 SC ath Uncore Size of DIMM B in 256 MB multiples Size of DIMM A DIMM_A_ Size 7 RUSE oot Uncore Size of DIMM A in 256 MB multiples Datasheet Volume 2 255 intel 2 16 4 256 Processor Configuration Registers PM_SREF_config Self Refresh Configuration Register This is a self refresh mode control register defines if and when DDR can go into SR B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5060 5063h Reset Value 000100FFh Access RW L Size 32 bits BIOS Optimal Default 0000h e Reset RST an Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD Idle timer init value Idle_timer This value is used when the SREF_enable field is set It defines 15 0 RW L OOFFh Uncore the number of cycles that there should not be any transaction in order to enter self refresh It is programmable 1 to 64K 1 In DCLK 800 it determines time of up to 82 us Datasheet Volume 2 Processor Configuration Reg
29. 23 20 RO 1111b IO the Handle Mask HM field in the interrupt entry cache invalidation descriptor iec_inv_dsc This field is valid only when the IR field in Extended Capability register is reported as set 19 18 RO Oh Reserved RSVD IOTLB Register Offset IRO This field specifies the offset to the IOTLB registers relative to the register base address of this remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first IOTLB invalidation register is calculated as X 16 Y 17 8 RO 010h Uncore Snoop Control SC 0 Hardware does not support 1 setting of the SNP field in the 7 RO V 1b Uncore page table entries 1 Hardware supports the 1 setting of the SNP field in the page table entries Pass Through PT 0 Hardware does not support pass through translation type in 6 RO V 1b Uncore context entries 1 Hardware supports pass through translation type in context entries Caching Hints CH 0 Hardware does not support IOTLB caching hints ALH and 5 RO Ob Uncore EH fields in context entries are treated as reserved 1 Hardware supports IOLTB caching hints through the ALH and EH fields in context entries 4 RO Oh Reserved RSVD Interrupt Remapping Support IR 0 Hardware does not support interrupt remapping 3 RO V 1b Uncore 1 Hardware supports interrupt remapping Implementations reporting this field as set must
30. 256 domains 2 0 RO 010b Uncore 011 Hardware supports 10 bit domain ids with support for up to 1024 domains 100 Hardware supports 12 bit domain ids with support for up to 4K domains 100 Hardware supports 14 bit domain ids with support for up to 16K domains 110 Hardware supports 16 bit domain ids with support for up to 64K domains 111 Reserved Datasheet Volume 2 265 intel 2 18 3 266 Processor Configuration Registers ECAP_REG Extended Capability Register This Register reports remapping hardware extended capabilities B D F Type 0 0 0 GFXVTBAR Address Offset 10 17h Reset Value 0000000000F0101Ah Access RO RO V Size 64 bits BIOS Optimal Default 00000000000h e Reset RST ES Bit Access Value PWR Description 63 24 RO Oh Reserved RSVD Maximum Handle Mask Value MHMV The value in this field indicates the maximum supported value for the Handle Mask HM field in the interrupt entry cache 23 20 RQ 1111b acne invalidation descriptor iec_inv_dsc This field is valid only when the IR field in Extended Capability register is reported as set 19 18 RO Oh Reserved RSVD IOTLB Register Offset IRO This field specifies the offset to the IOTLB registers relative to the 17 8 RO 010h Uncore register base address of this remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the fir
31. A 15 10 are not decoded When this bit is set to a 1 e Forwarding of these accesses issued by the processor is independent of the I O address and memory address ranges defined by the previously defined base and limit registers e Forwarding of these accesses is also independent of the settings of the ISA Enable settings if this bit is 1 e Accesses to I O address range x3BCh x3BFh are forwarded to DMI Interface When this bit is set to a 0 e Accesses to I O address range x3BCh x3BFh are treated just like any other I O accesses that is the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and ISA enable bit is not set otherwise they are forwarded to DMI Interface e VGA compatible memory and I O range accesses are not forwarded to PCI Express but rather they are mapped to DMI Interface unless they are mapped to PCI Express using I O and memory range registers defined above IOBASE IOLIMIT Table 2 7 shows the behavior for all combinations of MDA and VGA VGA and MDA 1 0 Transaction Mapping VGA_en MDAP Range Destination Exceptions Notes 0 0 VGA MDA DMI Interface 0 1 Illegal Undefined behavior results 1 0 VGA PCI Express 1 1 VGA PCI Express 1 1 MDA DMI Interface Note x3BCh x3BEh will also go to DMI Interface The same registers control mapping of VGA I O address ranges VGA I O range is defined as addresses where A 9 0 are in the ranges
32. B D F Type 0 2 0 PCI Address Offset Eh Reset Value 00h Access RO Size 8 bits e Reset RST oe ote Bit Access Value PWR Description Multi Function Status MFUNC This bit indicates if the device is a Multi Function Device The 7 R b o Uneore Value of this register is hardwired to 0 processor graphics is a single function Header Code H r This is a 7 bit value that indicates the Header Code for the IGD R Oh SP 2 9 SE This code has the value 00h indicating a type 0 configuration space format Datasheet Volume 2 153 154 Processor Configuration Registers GTTMMADR Graphics Translation Table Memory Mapped Range Address Register This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range The range requires 4 MB combined for MMIO and Global GTT aperture with 2 MB of that used by MMIO and 2 MB used by GTT GTTADR will begin at GTTMMADR 2 MB while the MMIO base address will be the same as GITMMADR For the Global GTT this range is defined as a memory BAR in graphics device configuration space It is an alias into which software is required to write Page Table Entry values PTEs Software may read PTE values from the global Graphics Translation Table GTT PTEs cannot be written directly into the global GTT memory area The device snoops writes to this region in order to invalidate any cached translations within the various TLBs i
33. BIOS Optimal Default 00h d Reset RST SOS Bit Access Value PWR Description 15 8 RO Oh Reserved RSVD 64 bit Address Capable B64AC Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is 7 BO op Uncore incapable of generating a 64 bit memory address This may need to change in future implementations when addressable system memory exceeds the 32b 4 GB limit Datasheet Volume 2 185 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 6 0 PCI 92 93h 0000h RO RW 16 bits 00h Bit Access Reset Value RST PWR Description 6 4 RW 000b Multiple Message Enable MME System software programs this field to indicate the actual number of messages allocated to this device This number will be equal to or less than the number actually requested The encoding is the same as for the MMC field below Uncore 3 1 RO 000b Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device 000 1 All of the following are reserved in this implementation 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved Uncore ll Ob MSI Enable MSIEN This bit controls the ability of this device to generate MSIs 0 MSI will not be generated 1
34. D1F2EN 0 Bus 0 Device 1 Function 2 is disabled and hidden 1 Bus 0 Device 1 Function 2 is enabled and visible l SH 19 SES This bit will be set to Ob and remain Ob if e PEGi2 capability is disabled by fuses OR e PEG12 is disabled by strap PEGOCFGSEL Host Bridge DOEN 0 RO 1b Uncore Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1 Datasheet Volume 2 Processor Configuration Registers intel 2 5 15 PAVPC Protected Audio Video Path Control Register All the bits in this register are locked by Intel TXT When locked the RW bits are RO B D F Type 0 0 0 PCI Address Offset 58 5Bh Reset Value 00000000h Access RW L RW KL Size 32 bits a Reset RST Se Bit Access Value PWR Description 31 3 RO Oh Reserved RSVD PAVP Lock PAVPLCK This bit will lock all writeable contents in this register when set 2 RW KL Ob Uncore including itself Only a hardware reset can unlock the register again For the processor this Lock bit needs to be set only if PAVP is enabled bit_PAVPE 1 1 0 RO Oh Reserved RSVD 2 5 16 DPR DMA Protected Range Register DMA protected range register B D F Type 0 0 0 PCI Address Offset 5C 5Fh Reset Value 00000000h Access RW L RO V RW KL Size 32 bits BIOS Optimal Default 0000h i Reset RST GL Bit Access Value PWR Description 31 3 RO Oh Reserved RSVD Enable Protected Memory EPM This field co
35. Graphics Mode Select GMS This field is used to select the amount of Main Memory that is pre allocated to support the Internal Graphics device in VGA non linear and Native linear modes The BIOS ensures that memory is pre allocated only when Internal graphics is enabled This register is also Intel TXT lockable Hardware does not clear or set any of these bits automatically based on IGD being disabled enabled BIOS Requirement BIOS must not set this field to Oh if IVD bit 1 of this register is 0 Note Itis recommended that the 1 GB pre allocated memory option be used for systems with at least 2 GB physical DRAM Encodings are as follows Oh 0 MB 7 3 RW L 05h Uncore ih 32 MB 2h 64 MB 3h 96 MB 4h 128 MB 5h 160 MB 6h 192 MB 7h 224 MB 8h 256 MB 9h 288 MB Ah 320 MB Bh 352 MB Ch 384 MB Dh 416 MB Eh 448 MB Fh 480 MB 10h 512 MB 1ih 1 GB Other Reserved Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 50 51h Reset Value 0028h Access RW L RW KL Size 16 bits BIOS Optimal Default 00h Reset RST PRA Bit Access Value PWR Description 2 RO Oh Reserved RSVD IGD VGA Disable IVD 0 Enable Device 2 IGD claims VGA memory and I O cycles the Sub Class Code within Device 2 Class Code register is 00 1 Disable Device 2 IGD does not claim VGA cycles Memory and I O and the Sub Class Code field
36. Power State PS This field indicates the current power state of this device and can be used to set the device into a new power state If software attempts to write an unsupported state to this field write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 01 Di Not supported in this device 10 D2 Not supported in this device 11 D3 Support of D3cold does not require any special action 1 0 RW 00b Uncore While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort that is not claim any downstream cycles with exception of type 0 configuration cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the processor logs as Master Aborts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States Datasheet Volume 2 183 intel Processor Configuration Registers 2 10 27 SS _CAPID Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides Because this device is an integrated part of the
37. Power down Configuration Register 258 2 17 2 PM_CMD_PWR Power Management Command Power Register 259 2 17 3 PM_BW_LIMIT_CONFIG BW Limit Configuration Register 259 Integrated Graphics VTd Remapping Engine Registers ceceeeceeeeeee tees eeeeeeeeneas 260 2 18 1 VER REG VeErsi0l REISTE seggt EENS NEE ENEE SEENEN ENNEN ge ge 261 2 18 2 CAP_REG Capability Register 262 2 18 3 ECAP_REG Extended Capability Register 266 2 18 4 GCMD_REG Global Command Register 267 2 18 5 GSTS_REG Global Status Register 271 2 18 6 RTADDR_REG Root Entry Table Address Register 272 2 18 7 CCMD_REG Context Command Register 273 2 18 8 FSTS_REG Fault Status Register cceeeee cece eee eee eee ee eee eee eee eeeaeaes 275 2 18 9 FECTL_REG Fault Event Control Register cceseeee eect eeeeee eee eeeeeaes 277 2 18 10 FEDATA_REG Fault Event Data Register 278 2 18 11 FEADDR_REG Fault Event Address Register 278 2 18 12 FEUADDR_REG Fault Event Upper Address Register 278 2 18 13 AFLOG_REG Advanced Fault Log Register 279 2 18 14 PMEN_REG Protected Memory Enable Register 280 2 18 15 PLMBASE_REG Protected Low Memory Base Register 281 2 18 16 PLMLIMIT_REG Protected Low Memory Limit Register 282 2 18 17 PHMBASE_REG Protected High Memory Base Register 283 2 18 18 PHMLIMIT_REG Protected High Memory Limit Register 284 2 18 19 IQH_REG Invalidation Queue Head Register 285 2 18
38. RO 00000000b PCI Express Completion Timeout PEG_TC This field determines the number of milliseconds the Transaction Layer will wait to receive an expected completion To avoid hang conditions the Transaction Layer will generate a dummy completion to the requestor if it does not receive the completion within this time period 14 12 RW 111b 000 Disable 001 Reserved 010 Reserved 100 Reserved 101 Reserved 110 Reserved x11 48 ms for normal operation 11 0 RO 000000000 Reserved RSVD Datasheet Volume 2 137 intel Processor Configuration Registers 2 7 8 EQCTLO_1i Lane 0 1 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane Access Size B D F Type Address Offset Reset Value 0 1 0 2 MMR DAO DA3h 07080708h RW 32 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 31 RO Oh Reserved RSVD 30 28 RW Lane 1 Downstream Component Receiver Preset Hint DCRPH1 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 27 24 RW Lane 1 Downstream Component Transmitter Preset DCTP1 0111b Uncore Transmitter
39. RO Ch CLS Cache Line Size 00h RO Dh MLT2 Master Latency Timer 00h RO Eh HDR2 Header Type 00h RO Fh RSVD Reserved Oh RO 10 17h GTTMMADR GE ea Memory Ce RO RW 18 1Fh GMADR Graphics Memory Range Address 00000000 RW RO 0000000Ch RW L 20 23h IOBAR I O Base Address 00000001h Rw RO 24 2Bh RSVD Reserved Oh RO 2C 2Dh SVID2 Subsystem Vendor Identification 0000h RW O 2E 2Fh SID2 Subsystem Identification 0000h RW O 30 33h ROMADR Video BIOS ROM Base Address 00000000h RO 34h CAPPOINT Capabilities Pointer 90h RO V 35 3Bh RSVD Reserved Oh RO 3Ch INTRLINE Interrupt Line 00h RW 3Dh INTRPIN Interrupt Pin Oih RO 3Eh MINGNT Minimum Grant 00h RO 3Fh MAXLAT Maximum Latency 00h RO 40 61h RSVD Reserved 62h MSAC Multi Size Aperture Control 02h RW RW K 63 FFh RSVD Reserved _ Datasheet Volume 2 Processor Configuration Registers intel 2 8 1 VID2 Vendor Identification Register This register combined with the Device Identification register uniquely identifies any PCI device B D F Type 0 2 0 PCI Address Offset O ih Reset Value 8086h Access RO Size 16 bits Reset RST Bit Access Value PWR Description R Vendor Identification Number VID 12 0 RO 8086h Ungore PCI standard identification for Intel 2 8 2 DID2 Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device This is a 16 bit value assigned to the
40. Reset RST Bit Access Value PWR Description TESG Memory base TSEGMB This register contains the base address of TSEG DRAM memory 31 20 RW L 000h Uncore BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory PCI Device 0 Offset B4h bits 31 20 19 1 RO Oh Reserved RSVD Lock LOCK 0 RW KL Ob Uncore This bit will lock all writeable settings in this register including itself TOLUD Top of Low Usable DRAM Register This 32 bit register defines the Top of Low Usable DRAM TSEG GTT Graphics memory and Graphics Stolen Memory are within the DRAM space defined From the top the Host optionally claims 1 to 64 MB of DRAM for internal graphics if enabled 1 or 2 MB of DRAM for GTT Graphics Stolen Memory if enabled and 1 2 or 8 MB of DRAM for TSEG if enabled Programming Example C1DRB3 is set to 4 GB TSEG is enabled and TSEG size is set to 1 MB Internal Graphics is enabled and Graphics Mode Select is set to 32 MB GTT Graphics Stolen Memory Size set to 2 MB BIOS knows the OS requires 1 GB of PCI space BIOS also knows the range from 0_FECO_0000h to 0_FFFF_FFFFh is not usable by the system This 20 MB range at the very top of addressable memory space is lost to APIC and Intel TXT According to the above equation TOLUD is originally calculated to 4 GB 1_0000_0000h The system memory requirements are 4 GB max addressable space 1G B PCI sp
41. Reset RST Value PWR Ob Ob Description Detected Parity Error DPE This bit is set by the Secondary Side for a Type 1 Configuration Uncore Space header device whenever it receives a Poisoned TLP regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register Received System Error RSE Uncore This bit is set when the Secondary Side for a Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL 13 RW1C Ob Received Master Abort RMA This bit is set when the Secondary Side for Type 1 Configuration Uncore Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status 12 RW1C Ob Received Target Abort RTA This bit is set when the Secondary Side for Type 1 Configuration Uncore Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status 11 RO Ob Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 The processor does not generate Target Aborts The root port will never Uncore complete a request using the Completer Abort Completion status UR detected inside the processor such as in iMPH MC will be reported in primary side status RO 00b DEVSELB Timing DEVT U wens Not Applicable or Implemented Hardwired to 0 RW1C Ob
42. This bit is set by the Secondary Side for a Type 1 Configuration Space header device whenever it receives a Poisoned TLP regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register Received System Error RSE This bit is set when the Secondary Side for a Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL 13 RW1C Ob Uncore Received Master Abort RMA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status 12 RW1C Ob Uncore Received Target Abort RTA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status 11 RO Ob Uncore Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 The processor does not generate Target Aborts The root port will never complete a request using the Completer Abort Completion status UR detected inside the processor such as in iMPH MC will be reported in primary side status 10 9 RO 00b Uncore DEVSELB Timing DEVT Not Applicable or Implemented Hardwired to 0 RW1C Ob Uncore Master Data Parity Error SMDPE When set indicates that the processor re
43. Write These bits can be read and written by software but a read causes the bits to be cleared Note Use of this attribute type is only allowed on legacy functions as side effects on reads are not desirable Datasheet Volume 2 15 intel Table 2 2 Register Attribute Modifiers Processor Configuration Registers Attribute Applicable Description Modifier Attribute P RO w V Sticky These bits are only re initialized to their Reset Value by a Power Good Reset RW S RW1C Note Does not apply to RO constant bits RWIS K RW Key These bits control the ability to write other bits identified with a Lock modifier RW Lock Hardware can make these bits Read Only using a separate L configuration bit or other logic W S Note Mutually exclusive with Once modifier RW Once After reset these bits can only be written by software once after which they become Read Only O WO Note Mutually exclusive with Lock modifier and does not make sense with Variant modifier FW RO Firmware Write The value of these bits can be updated by firmware PCU TAP and so on Variant The value of these bits can be updated by hardware v RO Note RW1C and RC bits are variant by definition and therefore do not need to be modified 2 2 PCI Devices and Functions Table 2 3 PCI Devices and Functions Description DID Device Function DRAM Controller 0154h 0 0
44. address the BIOS area from 0E4000h to OE7FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW 00b Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO Oh Reserved RSVD 0E0000 0E3FFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to OE3FFFh 00 DRAM Disabled All reads are sent to DRAM All writes are forwarded to DMI j 01 Read Only All reads are sent to DRAM All writes are 10 RW SE Seefe forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 70 Datasheet Volume 2 Processor Configuration Registers intel 2 5 27 PAM6 Programmable Attribute Map 6 Register This register controls the read write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are
45. bifurcation mode or not 19 0 RO Oh Reserved RSVD 2 11 16 PEGUPDNCFG PEG UPconfig DNconfig Control Register This register allows software to dynamically limit the port width The sequence to change width is 1 Write to this register the required width 2 Set Retrain link bit 5 in LCTL register 3 Wait till LSTS LTRN 11 is clear Note Actual width may be lower due to card limitation B D F Type 0 6 0 MMR Address Offset D34 D37h Reset Value 0000001Fh Access RW RW1icCS Size 32 bits BIOS Optimal Default 0000000h Reset RST Se Bit Access Value PWR Description 3137 RO Oh Reserved RSVD Advertise Upconfig Capability ADUPCFG 6 RW Ob Uncore 0 Do not advertise Upconfig support 1 Set the upconfig capable bit to 1 in our transmitted TS2s during Config Complete 5 0 RO Oh Reserved RSVD Datasheet Volume 2 213 intel Processor Configuration Registers 2 11 17 BGFCTL3 BGF Control 3 Register 214 B D F Type 0 6 0 MMR Address Offset D6C D6Fh Reset Value 400204E0h Access RW Size 32 bits BIOS Optimal Default 0000h o Reset RST ae Bit Access Value PWR Description Fclock Bubble Enable FBEN 31 RW Ob KEN This bit disable Bubble generator on Fclk side of BGF 0 Disabled 1 Enabled Lclock Bubble Enable LBEN This bit enable Bubble generator on Lclk side of BGF 30 RW 1b Uncore 0 Disabled 1 Enabled Bubble generation is
46. interrupt is deasserted System Error on Fatal Error Enable SEFEE Controls the Root Complex s response to fatal errors 2 RW 0b Uncore 0 No SERR generated on receipt of fatal error 1 Indicates that an SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Non Fatal Uncorrectable Error Enable SENFUEE Controls the Root Complex s response to non fatal errors 1 RW Ob Uncore 0 No SERR generated on receipt of non fatal error 1 Indicates that an SERR should be generated if a non fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Correctable Error Enable SECEE Controls the Root Complex s response to correctable errors 0 RW Ob Uncore 0 No SERR generated on receipt of correctable error 1 Indicates that an SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself ll ll Datasheet Volume 2 125 Processor Configuration Registers intel 2 6 45 RSTS Root Status Register This register provides information about PCI Express Root Complex specific parameters B D F Type 0 1 0 2 PCI Address Offset Co C3h Reset Value 00000000h Access RO RW1C RO V Size 32 bits BIOS Optimal
47. is required for a selected form factor or platform When the Link is operating at 2 5 GT s speed the setting of this bit has no effect Components that support only the 2 5 GT s speed are permitted to hardwire this bit to Ob 5 4 RO Oh Reserved RSVD 3 0 RWS 3h Powergood Target Link Speed TLS For Downstream ports this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences Defined encodings are 0001b 2 5 Gb s Target Link Speed 0010b 5 Gb s Target Link Speed 0011b 8 Gb s Target Link Speed All other encodings are reserved If a value is written to this field that does not correspond to a speed included in the Supported Link Speeds field the result is undefined The Reset Value of this field is the highest link speed supported by the component as reported in the Supported Link Speeds field of the Link Capabilities Register unless the corresponding platform form factor requires a different Reset Value For both Upstream and Downstream ports this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode Datasheet Volume 2 Processor Configuration Registers D 2 6 50 LSTS2 Link Status 2 Register B D F Type 0 1 0 2 PCI Address Offset D2 D3h Reset Value 0000h Access RO
48. or device functions that do not use an interrupt pin must put a 0 in this register The values 05h through FFh are reserved This register is write once BIOS must set this register to select the INTx to be used by this root port 102 Datasheet Volume 2 Processor Configuration Registers intel 2 6 24 BCTRL Bridge Control Register This register provides extensions to the PCICMD register that are specific to PCI PCI bridges The BCTRL provides additional control for the secondary interface that is PCI Express G as well as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within the processor such as VGA compatible address ranges mapping B D F Type 0 1 0 2 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh Bit Access sh KE Description 15 12 RO Oh Reserved RSVD ii mm op 1 Uncore Not applicable or Implemented Hardwired pn ER RO op SE SE to 0 SS ep uneorg o ne a oe So fe rdwired to 0 8 89 ob SR BCEE Hardwired to 0 7 RO ob Uncore Iw applicable or Implemented Hardwired to 0 Secondary Bus Reset SRESET Setting this bit triggers a hot reset on the corresponding PCI 6 RW b 2 EIER Express Port This will force the LTSSM to transition to the Hot Reset state using Recovery from LO LOs or L1 states Master Abort Mode MAMODE RO b Uneore Does not apply to PC
49. primary interface to the secondary interface RW Ob Uncore Memory Access Enable MAE 0 All of device s memory space is disabled 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE MLIMIT PMBASE and PMLIMIT registers RW Ob Uncore IO Access Enable IOAE 0 All of device s I O space is disabled 1 Enable the I O address range defined in the IOBASE and IOLIMIT registers Datasheet Volume 2 165 intel Processor Configuration Registers 2 10 4 PCISTS PCI Status Register This register reports the occurrence of error conditions associated with primary side of the virtual Host PCI Express bridge embedded within the Root port Access Size B D F Type Address Offset Reset Value 0 6 0 PCI 6 7h 0010h RWI1C RO RO V 16 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 15 RW1C Detected Parity Error DPE This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register On a Function with a Type 1 Configuration header the bit is set when the Poisoned TLP is received by its Ob Uncore Primary Side Reset Value of this bit is Ob This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned peer 2 peer posted forwarded will not set this bit They are reported at th
50. supported Bit definitions are Bit 1 2 5 GT s 7 1 RO V 07h Uncore Bit 2 5 0 GT s Bit 3 8 0 GT s Bits 7 4 Reserved Multi Function devices associated with an Upstream Port must report the same value in this field for all Functions DMI does not support this control register since it is Gen3 register 0 RO Oh Reserved RSVD 2 6 49 LCTL2 Link Control 2 Register B D F Type 0 1 0 2 PCI Address Offset DO Dih Reset Value 0003h Access RWS RWS V Size 16 bits a Reset RST Bae Bit Access Value PWR Description 15 11 RO Oh Reserved RSVD Enter Modified Compliance entermodcompliance When this bit is set to 1b the device transmits modified compliance pattern if the LTSSM enters Polling Compliance 10 RWS Ob Powergood state Components that support only the 2 5 GT s speed are permitted to hardwire this bit to Ob Reset Value of this field is Ob 9 7 RO Oh Reserved RSVD Datasheet Volume 2 129 130 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI DO Dih 0003h RWS RWS V 16 bits Bit Access Reset Value RST PWR Description RWS Ob Powergood Selectable De emphasis selectabledeemphasis When the Link is operating at 5 GT s speed selects the level of de emphasis Encodings 1 3 5dB 0 6dB Reset Value is implementation specific unless a specific value
51. unsupported d Peer writes can occur The SNR bit is ignored e MSI can occur These will route and be sent to the cores as Intlogical IntPhysical interrupts regardless of the SNR bit f VLW messages can occur These will route and be sent to the cores as VLW messages regardless of the SNR bit g MCTP messages can occur These are routed in a peer fashion 2 VCp Optionally enabled a Supports priority snoop traffic only This VC is given higher priority at the snoop VC arbiter Routed as an independent virtual channel and treated independently within the Cache module VCp snoops are indicated as high priority in the snoop priority field USB classic and USB2 traffic are expected to use this channel Note On prior chipsets this was termed snoop isochronous traffic Snoop isochronous is now termed priority snoop traffic SNR bit is ignored MSI on VCP is supported d Peer read and write requests are not supported Writes will route to address 000C_0000h with byte enables deasserted while reads will route to address 000C_0000h and an unsupported request completion e Internal Graphics GMADR writes are NOT supported These will route to address 000C_0000h with byte enables de asserted f Internal Graphics GMADR reads are not supported g See DMI2 TC mapping for expected TC to VCp mapping This has changed from DMI to DMI2 3 VC1 Optionally enabled a Supports non snoop transactions only Used fo
52. 0 RW Domain ID DID This field indicates the id of the domain whose context entries need to be selectively invalidated This field must be programmed by software for both domain selective and device selective invalidation requests The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware may ignore and not implement bitsi5 N where N is the supported domain id width reported in the Capability register 00h Uncore Datasheet Volume 2 Processor Configuration Registers 2 18 8 FSTS_REG Fault Status Register This register indicates the various error status B D F Type 0 0 0 GFXVTBAR Address Offset 34 37h Reset Value 00000000h Access RO ROS V RW1iCS Size 32 bits BIOS Optimal Default 00000h Bit Access Reset Value RST PWR Description 31 16 RO Oh Reserved RSVD 15 8 ROS V RO 00h Oh Powergood Fault Record Index FRI This field is valid only when the PPF field is set The FRI field indicates the index from base of the fault recording register to which the first pending fault was recorded when the PPF field was set by hardware The value read from this field is undefined when the PPF field is clear Reserved RSVD RO Ob Uncore Invalidation Time out Error ITE Hardware detected a Device IOTLB invalidation comple
53. 0 6 0 PCI Address Offset B2 B3h Reset Value 1001h Access RW1C RO V RO Size 16 bits BIOS Optimal Default Oh Reset RST SA Bit Access Value PWR Description Link Autonomous Bandwidth Status LABWS This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width without the port 15 RW1C Ob Uncore transitioning through DL_Down status for reasons other than to attempt to correct unreliable link operation This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change Link Bandwidth Management Status LBWMS This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status A link retraining initiated by a write of 1b to the Retrain Link bit has completed Note This bit is set following any write of 1b to the Retrain Link 14 RW1C Ob Uncore bit including when the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an LTSSM timeout or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change Data Link Layer Link Active Optional DLLLA This bit indicates
54. 0 6 0 PCI B8 B9h 0000h RO 16 bits Oh Bit Access Reset Value RST PWR Description 15 13 RO Oh Reserved RSVD 12 RO Ob Uncore Reserved for Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented when set to 1b this field enables software notification when Data Link Layer Link Active field is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to be read only with a value of Ob 11 RO Ob Uncore Reserved for Electromechanical Interlock Control EIC If an Electromechanical Interlock is implemented a write of 1b to this field causes the state of the interlock to toggle A write of Ob to this field has no effect A read to this register always returns a 0 10 RO Ob Uncore Reserved for Power Controller Control PCC If a Power Controller is implemented this field when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to the slot or within the adapter Note that in some cases the power controller may autonomously remove slot power or not
55. 000000h 5 Reset RST iias Bit Access Value PWR Description 31 8 RO Oh Reserved RSVD Link Address LA Memory mapped base address of the RCRB that is the target 7 0 RW O 00h Uncore element Egress Port for this link entry BIOS Requirement This field is inserted by BIOS such that it matches PXPEPBAR 2 11 12 APICBASE APIC Base Address Register B D F Type 0 6 0 MMR Address Offset 240 243h Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 000000h Bit Access ere e Description 31 12 RO Oh Reserved RSVD APIC Base Address APICBASE Bits 19 12 of the APIC Base 11 4 RW 00h Uncore Bits 31 20 are assumed to be FECh Bits 0 11 are don t care for address decode Address decoding to the APIC range is done as APIC_BASE 31 12 lt A 31 12 lt APIC_LIMIT 31 12 3 1 RO Oh Reserved RSVD APIC Range Enable APICRE Enables the decode of the APIC window 0 Disable 1 Enable 0 RW Ob Uncore Datasheet Volume 2 211 intel Processor Configuration Registers 2 11 13 APICLIMIT APIC Base Address Limit Register B D F Type 0 6 0 MMR Address Offset 244 247h Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 000000h o Reset RST ae Bit Access Value PWR Description 31 12 RO Reserved RSVD APIC Base Address APICLIMIT Bits 19 12 of the APIC Limit Bits 31 20 are assumed t
56. 1 Address Register 211 2 11 12 APICBASE APIC Base Address Register 211 2 11 13 APICLIMIT APIC Base Address Limit Register 212 2 11 14 CMNRXERR Common Rx Error Register 212 2 11 15 PEGTST PCI Express Test Modes Register 213 2 11 16 PEGUPDNCFG PEG UPconfig DNconfig Control Register 213 2 11 17 BGFCTL3 BGF Control 3 Register 214 2 11 18 EQPRESET1_2 Equalization Preset 1 2 Register c cceceeeeeeeeeeeeeee ees 215 2 11 19 EQPRESET2_3_4 Equalization Preset 2 3 4 Register 215 2 11 20 EQPRESET6_7 Equalization Preset 6 7 Register c sceeeeeeeeeeeeeeeee ees 216 2 11 21 EQCFG Equalization Configuration Register ccsceseeeeeeeeeeeeeeeeeeeees 216 2 12 Direct Media Interface Base Address Registers DMIBART 217 2 12 1 DMIVCECH DMI Virtual Channel Enhanced Capability Register 218 2 12 2 DMIPVCCAP1 DMI Port VC Capability Register 1 219 2 12 3 DMIPVCCAP2 DMI Port VC Capability Register 2 219 2 12 4 DMIPVCCTL DMI Port VC Control Register 220 2 12 5 DMIVCORCAP DMI VCO Resource Capability Register eeeeeeee eee 220 2 12 6 DMIVCORCTL DMI VCO Resource Control Register 221 2 12 7 DMIVCORSTS DMI VCO Resource Status Register 222 2 12 8 DMIVC1RCAP DMI VC1 Resource Capability Register eeeeeee eee 222 2 12 9 DMIVC1RCTL DMI VC1 Resource Control Register 223 2 12 10 DMIVC1RSTS DMI VC1 Resource Status Register 224 2 12 1
57. 1 Function 0 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set if Device 1 Function 0 VGA Enable bit is not set If Device 1 Function 0 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 1 Function 0 if the address is within the corresponding IOBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h 0B7FFFh 1 O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 0 All References to MDA and VGA space are not claimed by Device 1 Function 0 0 1 Illegal combination 1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 0 1 1 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 0 MDA references are not claimed by Device 1 Function 0 VGA and MDA memory cycles can only be routed across PEG10 when MA
58. 10Fh Reset Value 0200000000000000h Access RO V RW RW V Size 64 bits BIOS Optimal Default 0000000000000h Reset RST Bit Access Value PWR Description Invalidate IOTLB IVT Software requests IOTLB invalidation by setting this field Software must also set the requested invalidation granularity by programming the IIRG field Hardware clears the IVT field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field Software must not submit another invalidation request through this register while the IVT field is set nor update the associated Invalidate Address register Software must not submit IOTLB invalidation requests when there is a context cache invalidation request pending at this remapping hardware unit Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flushing before invalidating the IOTLB 63 RW V Oh Uncore 62 62 RO Oh Reserved RSVD IOTLB Invalidation Request Granularity IIRG When requesting hardware to invalidate the IOTLB by setting the IVT field software writes the requested invalidation granularity through this field The following are the encodings for the field 00 Reserved 01 Global invalidation request 10 Domain selective invalidation request The target domain id must be speci
59. 110 Datasheet Volume 2 Processor Configuration Registers D 2 6 34 DEG _CAP PCI Express G Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 1 0 2 PCI Address Offset A2 A3h Reset Value 0142h Access RO RW O Size 16 bits BIOS Optimal Default Oh S Reset RST SC Bit Access Value PWR Description 15 14 RO Oh Reserved RSVD Interrupt Message Number IMN 13 9 RO 00h 3 Uncore Not Applicable or Implemented Hardwired to 0 Slot Implemented SI 0 The PCI Express Link associated with this port is connected to an integrated component or is disabled 8 RW O 1b Uncore 1 The PCI Express Link associated with this port is connected to a slot BIOS Requirement This field must be initialized appropriately if a slot connection is not implemented Device Port Type DPT 7 4 RO 4h Uncore Hardwired to 4h to indicate root port of PCI Express Root Complex PCI Express Capability Version PCIECV 3 0 RO 2h Uncore Hardwired to 2h to indicate compliance to the PCI Express Capabilities Register Expansion ECN 2 6 35 DCAP Device Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 1 0 2 PCI Address Offset A4 A7h Reset Value 00008000h Access RO RW O Size 32 bits BIOS Optimal Default 0000000h r Reset RST SA Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD
60. 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A 31 20 of a memory address For the purpose of address decoding the processor assumes that address bits A 19 0 of the memory base are zero and that address bits A 19 0 of the memory limit address are F_FFFFh This forces each memory address range to be aligned to 1 MB boundary and to have a size granularity of 1 MB The processor positively decodes memory accesses to PCI Express memory address space as defined by the following equations Memory_Base_Address lt Address lt Memory_Limit_Address Prefetchable_Memory_Base_Address lt Address lt Prefetchable_Memory_Limit_Address The window size is programmed by the plug and play configuration software The window size depends on the size of memory claimed by the PCI Express device Normally these ranges will reside above the Top of Low Usable DRAM and below High BIOS and APIC address ranges They MUST reside above the top of low memory TOLUD if they reside below 4 GB and MUST reside above top of upper memory TOUUD if they reside above 4 GB or they will steal physical DRAM memory space It is essential to support a separate Pre fetchable range in order to apply USWC attribute from the processor point of view to that range The USWC attribute is used by the processor for write combining The processor memory range registers described above are used to allocate memory address space for any PCI
61. 2 0 RO 000b Uncore This field indicates the number of extended Virtual Channels in addition to the default VC supported by the device 2 7 2 PVCCAP2 Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 1 0 2 MMR Address Offset 108 10Bh Reset Value 00000000h Access RO Size 32 bits BIOS Optimal Default 0000h Reset RST Bit Access Value PWR Description VC Arbitration Table Offset VCATO This field indicates the location of the VC Arbitration Table This S field contains the zero based offset of the table in DQWORDS 31 24 RO ooh SE 16 bytes from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO Oh Reserved RSVD 7 0 RO 00h Uncore Reserved for VC Arbitration Capability VCAC Datasheet Volume 2 133 intel 2 7 3 134 Processor Configuration Registers PVCCTL Port VC Control Register B D F Type 0 1 0 2 MMR Address Offset 10C 10Dh Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 0000h o Reset RST ae Bit Access Value PWR Description 15 4 RO Oh Reserved RSVD VC Arbitration Select VCAS This field will be programmed by software to the only possible 3 1 RW 000b Uncore value as indicated in the VC Arb
62. 2 241 intel Processor Configuration Registers 2 13 3 SC_IO_LATENCY_CO IO Latency configuration Register This register identifies the I O latency per rank and I O compensation global B D F Type 0 0 0 MCHBAR MCO Address Offset 4028 402Bh Reset Value 000E0000h Access RW L Size 32 bits BIOS Optimal Default 00h e Reset RST eae Bit Access Value PWR Description 31 22 RO Oh Reserved RSVD 21 16 RW L OEh Uncore Round trip I O compensation RT_IOCOMP 15 12 RW L Oh Uncore IO latency Rank 1 DIMM 1 IOLAT_R1D1 11 8 RW L Oh Uncore IO latency Rank O DIMM 1 IOLAT_ROD1 7 4 RW L Oh Uncore IO latency Rank 1 DIMM O IOLAT_R1D0 3 0 RW L Oh Uncore IO latency Rank 0 DIMM O IOLAT_RODO 2 13 4 TC_SRFTP_CO Self Refresh Timing Parameters Register This register is for the Self refresh timing parameters B D F Type 0 0 0 MCHBAR MCO Address Offset 42A4 42A7h Reset Value 0100B200h Access RW L Size 32 bits BIOS Optimal Default Oh e Reset RST Se Bit Access Value PWR Description tMOD This field is the time between MRS command and any other 31 28 RW L Oh Uncore command in DCLK cycles Actual value is 8 programmed Value For example when programming 4 in the field tMOD value is actually 12 DCLK cycles 27 26 RO Oh Reserved RSVD tZQOPER E SE GEN ZS Defines the period required for ZQCL after SR exit tXS_offset 15 12 RW L Bh Uncore Delay fr
63. 20 IQT_REG Invalidation Queue Tail Register 285 2 18 21 IQA REG Invalidation Queue Address Register 286 2 18 22 ICS_REG Invalidation Completion Status Register 286 2 18 23 IECTL_REG Invalidation Event Control Register 287 2 18 24 IEDATA_REG Invalidation Event Data Register 288 2 18 25 IEADDR_REG Invalidation Event Address Register 288 2 18 26 IEVADDR_REG Invalidation Event Upper Address Register 289 2 18 27 IRTA_REG Interrupt Remapping Table Address Register 289 2 18 28 IVA_REG Invalidate Address Register 290 2 18 29 IOTLB_REG IOTLB Invalidate Register 291 Datasheet Volume 2 2 18 30 FRCDL_REG Fault Recording Low Register 293 2 18 31 FRCDH_REG Fault Recording High Register c cceeeeeeeeeeeeeeeeeeeenees 294 2 18 32 VTPOLICY DMA Remap Engine Policy Control Register 295 2 19 BERGERE EEGENEN 296 2 19 1 MEM_TRML_ESTIMATION_CONFIG Memory Thermal Estimation Configuration Register 297 2 19 2 MEM_TRML_THRESHOLDS_CONFIG Memory Thermal Thresholds Configuration Register 298 2 19 3 MEM_TRML_STATUS_REPORT Memory Thermal Status Report ReoIsb t sgou i ssgkzerdgsesgp eegag n cede dead SEENEN EEN SEENEN 299 2 19 4 MEM_TRML_TEMPERATURE_REPORT Memory Thermal Temperature Report Register 300 2 19 5 MEM_TRML_INTERRUPT Memory Thermal ege fiel E EE 200 2 19 6 GT_PERF_STATUS GT Performance Status Register 301 2 19 7 RP_STATE_LIMITS RP State Limitations Register
64. 31 16 RO Oh Reserved RSVD Pointer to Next Capability PNC 15 8 RO 80h Uncore This field contains a pointer to the next item in the capabilities list which is the PCI Power Management capability Capability ID CID 7 0 RO ODh Uncore Value of ODh identifies this linked list item capability structure as being for SSID SSVID registers in a PCI to PCI Bridge 2 6 28 SS Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset B D F Type 0 1 0 2 PCI Address Offset 8C 8Fh Reset Value 00008086h Access Rw O Size 32 bits Reset RST SE Bit Access Value PWR Description Subsystem ID SSID 31 16 RW O 0000h Uncore This field identifies the particular subsystem and is assigned by the vendor Subsystem Vendor ID SSVID z This field identifies the manufacturer of the subsystem and is the 15 0 SEH SEN Uncorg same as the vendor ID which is assigned by the PCI Special Interest Group Datasheet Volume 2 107 intel MSI_CAPID Message Signaled Interrupts Capability ID Register 108 Processor Configuration Registers When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item a message to a predefined memory address The reporting of the existence of this capability ca
65. 32 bits BIOS Optimal Default 00h S Reset RST aoe Bit Access Value PWR Description 31 24 RO 00h Uncore Reserved for Port Arbitration Table Offset PATO 23 RO Oh Reserved RSVD 22 16 RO 00h Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions REJSNPT 0 Transactions with or without the No Snoop bit set within the 15 RO Ob Uncore TLP header are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request 14 8 RO Oh Reserved RSVD Port Arbitration Capability PAC 7 0 RO Olh Uncore Having only bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed 220 Datasheet Volume 2 Processor Configuration Registers intel 2 12 6 DMIVCORCTL DMI VCO Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0 B D F Type 0 0 0 DMIBAR Address Offset 14 17h Reset Value 8000007Fh Access RO RW Size 32 bits BIOS Optimal Default 00000h S Reset RST EP Bit Access Value PWR Description Virtual Channel 0 Enable VCOE 31 RO 1b Uncore For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved RSVD Virtual Channel 0 ID VCOID 26 24 RO 000b Uncore This field assigns a VC ID to the VC resource For VCO this is hardwired t
66. 3BOh to 3BBh and 3COh to 3DFh inclusive of ISA address aliases A 15 10 are not decoded The function and interaction of these two bits is described below Datasheet Volume 2 45 DN t l Processor Configuration Registers 2 4 46 MDA Present MDAP This bit works with the VGA Enable bit in the BCTRL register of Device 1 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set when the VGA Enable bit is not set If the VGA enable bit is set accesses to I O address range x3BCh x3BFh are forwarded to DMI Interface If the VGA enable bit is not set accesses to I O address range x3BCh x3BFh are treated just like any other I O accesses that is the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and ISA enable bit is not set otherwise they are forwarded to DMI Interface MDA resources are defined as the following Memory 0B0000h 0B7FFFh I O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh Including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will be forwarded to DMI Interface even if the reference includes I O locations not listed above For I O reads which are split into multiple DWord accesses this decode applies to each DWord independently For example a read to x3B3 and x3B4 quadword read to x3BO with BE E7h will res
67. 6 7 Equalization Control Register 141 2 7 12 EQCTL8_9 Lane 8 9 Equalization Control Register 142 2 7 13 EQCTL1i0_11 Lane 10 11 Equalization Control Register 143 2 7 14 EQCTL12_13 Lane 12 13 Equalization Control Register 144 2 7 15 EQCTL14_15 Lane 14 15 Equalization Control Register 145 2 7 16 EQCFG Equalization Configuration ReGiSter csceeeeeeeeeeeee teen eeeeeees 146 2 8 PCI Device 2 Configuration Space Register 148 2 8 1 VID2 Vendor Identification Register cccee eee eeee senses estate eee ee teenies 149 2 8 2 DID2 Device Identification Register 149 2 8 3 PCICMD2 PCI Command Register 150 2 8 4 PCISTS2 PCLI Status Register sisonu nade i EEN AER 151 2 8 5 RID2 Revision Identification Register 152 2 8 6 CC Class Code Register EE 152 2 8 7 CLS Cache Line Size Register REN SERKNE NENNEN ENER ANNER ENKEN EEN ENER NNN 153 2 8 8 MLT2 Master Latency Timer Register 153 2 8 9 HDR2 Header Type Register 153 2 8 10 GITMMADR Graphics Translation Table Memory Mapped Range Address Register 154 2 8 11 GMADR Graphics Memory Range Address Register 155 2 8 12 IOBAR I O Base Address Register 156 Datasheet Volume 2 5 D 2 8 13 SVID2 Subsystem Vendor Identification Register 156 2 8 14 SID2 Subsystem Identification Register 157 2 8 15 ROMADR Video BIOS ROM Base Address Register 157 2 8 16 CAPPOINT Capabilities Pointer Register 157 2 8
68. Access RW Size 32 bits Reset RST ERE Bit Access Value PWR Description 20 19 RW 00000000h Reserved RSVD ppi_clipped_pl1 18 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by PL1 POWER_LIMIT_1 power limiting algorithm ppi_clipped_thermals 17 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by internal Thermal Throttling algorithm ppi_clipped_ext_prochot 16 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by external PROCHOT indication ppO_clipped 15 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped ppO_clipped_n_core_turbo Set if the PPO IA frequency requested by the operating system 14 RW 00000000h U RSENS was clipped but current frequency is lower than MAX_TURBO n cores ppO_clipped_non_turbo 13 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped but current frequency is lower than MAX_NON_TURBO 12 9 RW 00000000h Reserved RSVD pp0O_clipped_edp 8 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped by EDP limit Vmax Iccmax Reliability and so on ppO_clipped_mct 7 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped by Multi Core Turbo demotion algorithm ppO_clipped_hot_vr 6 RW 00000000h Uncore Set if the PPO IA frequency requested by the ope
69. Access RWI1CS Size 32 bits BIOS Optimal Default 00000000h Reset RST ee Bit Access Value PWR Description 31 1 RO Oh Reserved RSVD Invalidation Wait Descriptor Complete IWC This bit indicates completion of Invalidation Wait Descriptor RW1icS 0 P d o p Klek with Interrupt Flag IF field set Hardware implementations not supporting queued invalidations implement this field as RsvdZ 286 Datasheet Volume 2 Processor Configuration Registers intel 2 18 23 IECTL_REG Invalidation Event Control Register This register specifies the invalidation event interrupt control bits This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 GFXVTBAR A0 A3h 80000000h RW L RO V 32 bits 00000000h Bit Access Reset Value RST PWR Description 31 1b Uncore Interrupt Mask IM 0 No masking of interrupt When an invalidation event condition is detected hardware issues an interrupt message using the Invalidation Event Data amp Invalidation Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set 30 RO V Ob Uncore Interrupt Pendin
70. B_OOOOh B_7FFFh Legacy support requires the ability to have a second graphics controller monochrome in the system Accesses in the standard VGA range are forwarded to IGD PCI Express or the DMI Interface depending on configuration bits Since the monochrome adapter may be mapped to any of these devices the processor must decode cycles in the MDA range 000B_0000h 000B_7FFFh and forward either to IGD PCI Express or the DMI Interface This capability is controlled by the VGA steering bits and the legacy configuration bit MDAP bit In addition to the memory range BOOOOh to B7FFFh the processor decodes I O cycles at 3B4h 3B5h 3B8h 3B9h 3BAh and 3BFh and forwards them to the either IGD PCI Express and or the DMI Interface PEG 16 bit VGA Decode The PCI to PCI Bridge Architecture Specification Revision 1 2 it is required that 16 bit VGA decode be a feature When 16 bit VGA decode is disabled the decode of VGA I O addresses is performed on 10 lower bits only essentially mapping also the aliases of the defined I O addresses PAM C_OOOOh F_FFFFh The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area Each section has Read enable and Write enable attributes The PAM registers are mapped in Device 0 configuration space e ISA Expansion Area C_0000h D_FFFFh e Extended System BIOS Area E_0000h E_FFFFh e System BIOS Area F_0000h F_FFFFh The processor decodes the core request then route
71. Backward compatibility for the architecture is maintained with new revision numbers allowing software to load remapping hardware drivers written for prior architecture versions B D F Type 0 0 0 GFXVTBAR Address Offset 0 3h Reset Value 00000010h Access RO Size 32 bits BIOS Optimal Default 000000h i Reset RST SE Bit Access Value PWR Description 31 8 RO Oh Reserved RSVD 7 4 RO 0001b Se Major Version number MAX Indicates supported architecture version 3 0 RO 0000b nt re Minor Version number MIN Indicates supported architecture minor version Datasheet Volume 2 261 intel 2 18 2 262 Processor Configuration Registers CAP_REG Capability Register This register reports general remapping hardware capabilities B D F Type 0 0 0 GFXVTBAR Address Offset 8 Fh Reset Value 00C0000020E60262h Access RO Size 64 bits BIOS Optimal Default 0000h e Reset RST ear Bit Access Value PWR Description 63 56 RO Oh Reserved RSVD DMA Read Draining DRD 55 RO 1b Uncore 0 Hardware does not support draining of DMA read requests 1 Hardware supports draining of DMA read requests DMA Write Draining DWD 54 RO 1b Uncore 0 Hardware does not support draining of DMA write requests 1 Hardware supports draining of DMA write requests Maximum Address Mask Value MAMV The value in this field indicates the maximum supported value for 3 the Ad
72. Enable Relaxed Ordering ROE Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked Unsupported Request UR An ERR_CORR is signaled RW Ge ZE when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register Fatal Error Reporting Enable FERE When set this bit enables signaling of ERR_FATAL to the Root 2 RW Ob Uncore Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Non Fatal Error Reporting Enable NERE When set this bit enables signaling of ERR_NONFATAL to the 1 RW Ob Uncore Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Correctable Error Reporting Enable CERE When set this bit enables signaling of ERR_CORR to the Root 0 RW Ob Uncore Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Datasheet Volume 2 Processor Configuration Registers intel 2 6 37 DSTS Device Status Register This registe
73. Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 6 0 PCI Address Offset 1Ah Reset Value 00h Access RW Size 8 bits Bit Access sb S gl Description Subordinate Bus Number BUSN This register is programmed by configuration software with the V number of the highest subordinate bus that lies behind the CH RW pon Ungore processor root port bridge When only a single PCI device resides on the PCI Express G segment this register will contain the same value as the SBUSN1 register Datasheet Volume 2 169 DN t Processor Configuration Registers 2 10 12 2 10 13 170 IOBASE I O Base Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined I O address range will be aligned to a 4 KB boundary B D F Type 0 6 0 PCI Address Offset 1Ch Reset Value FOh Access RW Size 8 bits BIOS Optimal Default Oh e Reset RST DS Bit Access Value PWR Description I O Address Base IOBASE 7 4 RW Fh Uncore This field corresponds to A 15 12 of the I O addresses passed by the root port to PCI Express G 3 0 RO Oh Reserved RSVD IOLI
74. Express devices sitting on PCI Express that require such a window The PCICMD register can override the routing of memory accesses to PCI Express In other words the memory access enable bit must be set to enable the memory base limit and pre fetchable base limit windows The upper PMUBASE PMULIMIT registers are implemented for PCI Express Specification compliance The processor locates MMIO space above 4 GB using these registers Datasheet Volume 2 35 DN t Processor Configuration Registers 2 3 7 2 3 7 1 Note 2 3 7 2 36 Graphics Memory Address Ranges The integrated memory controller can be programmed to direct memory accesses to IGD when addresses are within any of two ranges specified using registers in MCH Device 2 configuration space 1 The Graphics Memory Aperture Base Register GMADR is used to access graphics memory allocated using the graphics translation table 2 The Graphics Translation Table Base Register GTTADR is used to access the translation table and graphics control registers This is part of GTTMMADR register These ranges can reside above the Top of Low DRAM and below High BIOS and APIC address ranges They MUST reside above the top of memory TOLUD and below 4 GB so they do not steal any physical DRAM memory space Alternatively these ranges can reside above 4 GB similar to other BARs which are larger than 32 bits in size GMADR is a Prefetchable range in order to apply USWC attri
75. For VCO this is hardwired to 0 and read only 23 20 RO Oh Reserved RSVD Port Arbitration Select PAS Port Arbitration Select This field configures the VC resource to provide a particular Port Arbitration service This field is valid for RCRBs Root Ports that support peer to peer traffic and Switch Ports but not for PCI Express Endpoint devices or Root Ports that 19 17 RW 000b Uncore do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource This field does not affect the root port behavior 16 RO Oh Reserved RSVD TC High VCO Map TCHVCOM 15 8 RW 00h Uncore Allow usage of high order TCs BIOS should keep this field zeroed to allow usage of the reserved TC 3 for other purposes TC VCO Map TCVCOM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this 7 1 RW 7Fh Uncore VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link TCO VCO Map TCOVCOM 0 RO 1b onsale Traffic Class 0 is always routed to VCO
76. Greater than 4 GB of Physical Memor 32 Example DMI Upstream VCO Memory Map 41 PEG Upstream VCO Memory Map nies ccicsisecsccesteecnseetetee denies a a ees 43 Register Attributes and Terminologie 15 Register Attribute Modifiers E SNE KN RER NENNEN ene ease eten nnu nAn aE EE 16 PCI DeViceS ANd FUNCTIONS ebe ege Ee EEN 16 SMM REGIONS s KEREN REESEN DEENEN SEENEN EEN SERA teem ENEE SEN SASSEL K EN 37 IGD Frame lege te geed EEN ge 44 IG VGA O Mapping EE 44 VGA and MDA I O Transaction Mapping ssssssssssrsssrsssrsrrnsrrnnnrnrnnnnrnnnnnnnnnnnnnnnnnnnnn 45 PCI Device 0 Function 0 Configuration Space Register Address Map 47 PCI Device 1 Function 0 2 Configuration Space Register Address Map 86 PCI Device 1 Function 0 2 Extended Configuration Register Address Map 5 132 PCI Device 2 Configuration Space Register Address Map 148 Device 2 IO Register Address Map 160 PCI Device 6 Register Address Map cccccccecceeeeeeersaeseneeeeeeaeeeeeeeeaeeeeeeueaeanseeneaeeena 161 PCI Device 6 Extended Configuration Register Address Map 203 DMIBAR Register Address Map cccccctcsccceseceeeeeeesenereneeeeneaeeseeneedeeeeeeaensanaeeeennenee 217 MCHBAR Registers in Memory Controller Channel 0 Register Address Map 239 MCHBAR Registers in Memory Controller Channel 1 Register Address Map 245 MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub IMPH Register Address Map NEEN REENEN
77. Implemented Hardwired to 0 Memory Write and Invalidate Enable MWIE 4 RO Ob SNE Not Applicable or Implemented Hardwired to 0 Special Cycle Enable SCE RO b 3 H SES Not Applicable or Implemented Hardwired to 0 Bus Master Enable BME This bit controls the ability of the PEG port to forward Memory Read Write Requests in the upstream direction 0 This device is prevented from making memory requests to its primary bus Note that according to PCI Specification as MSI interrupt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them 2 RW Ob Uncore from its secondary bus to its primary bus Upstream memory writes reads peer writes reads and MSIs will all be treated as illegal cycles Writes are aborted Reads are aborted and will return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the data is available This bit does not affect forwarding of Completions from the primary interface to the secondary interface Datasheet Volume 2 89 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset 4 5h Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 00h S Rese
78. Interrupt Enable LBMIE When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Ob Uncore RW Hardware Autonomous Width Disable HAWD When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob Ob Uncore RO Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as follows 0 Clock power management is disabled and device must hold CLKREQ signal low 1 When this bit is set to 1 the device is permitted to use CLKREQ signal to power manage link clock according to protocol defined in appropriate form factor specification Reset Value of this field is Ob Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabilities Register must hardwire this bit to Ob Ob Uncore RW Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and
79. LHSASH amp LHSASL 11 Bits 28 27 of GMADR are RO allowing 512 MB of GMADR 10 Illegal Programming 01 Bit 28 of GMADR is RW but bit 27 of GMADR is RO allowing 256 MB of GMADR 00 Bits 28 27 of GMADR are RW allowing 128 MB of GMADR 1 RW K ib Uncore 0 RO Oh Reserved RSVD Datasheet Volume 2 159 intel Processor Configuration Registers 2 9 Device 2 IO Registers Table 2 12 Device 2 IO Register Address Map grey ek Register Name Reset Value Access 0 3h Index MMIO Address Register 00000000h RW 4 7h Data MMIO Data Register 00000000h RW 2 9 1 Index MMIO Address Register MMIO_INDEX A 32 bit I O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed An I O Read returns the current value of this register This mechanism to access internal graphics MMIO registers must not be used to access VGA I O registers which are mapped through the MMIO space VGA registers must be accessed directly through the dedicated VGA I O ports B D F Type 0 2 0 PCIIO Address Offset 0 3h Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 00000000h z Reset RST Sib Bit Access Value PWR Description 31 21 RO Oh Reserved RSVD Register GTT Offset REGGTTO F FLR This field selects any one of the DWord registers within the MMIO SE RW 0000o Uncore register space of Device 2 if the
80. MB buses 0 127 Bits 38 27 are decoded in the PCI Express Base Address Field 10 64 MB buses 0 63 Bits 38 26 are decoded in the PCI Express Base Address Field 11 Reserved This register is locked by Intel TXT PCIEXBAR Enable PCIEXBAREN 0 The PCIEXBAR register is disabled Memory read and write transactions proceed as if there were no PCIEXBAR register PCIEXBAR bits 38 26 are RW with no functionality behind them 0 RW Ob Uncore 1 The PCIEXBAR register is enabled Memory read and write transactions whose address bits 38 26 match PCIEXBAR will be translated to configuration reads and writes within the Uncore These Translated cycles are routed as shown in the above table This register is locked by Intel TXT Datasheet Volume 2 61 62 Processor Configuration Registers DMIBAR Root Complex Register Range Base Address Register This is the base address for the Root Complex configuration space This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the Host Bridge There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMIBAREN Device 0 offset 68h bit 0 All the bits in this register are locked in Intel TXT mode
81. Number Register This register identifies the subordinate bus if any that resides at the level below PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 1 0 2 PCI Address Offset 1Ah Reset Value 00h Access RW Size 8 bits J Reset RST SE Bit Access Value PWR Description Subordinate Bus Number BUSN This register is programmed by configuration software with the 7 0 RW h number of the highest subordinate bus that lies behind the Gi ZS processor root port bridge When only a single PCI device resides on the PCI Express G segment this register will contain the same value as the SBUSN1 register Datasheet Volume 2 Processor Configuration Registers 2 6 12 intel IOBASE I O Base Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined I O address range will be aligned to a 4 KB boundary B D F Type Address Offset Reset Value 0 1 0 2 PCI 1Ch FOh 2 6 13 Access RW Size 8 bits BIOS Optimal Default Oh Reset RST Bit Access Value PWR Description I O Address Base IOBASE This field corresponds to A 15 12 of the I O addresses passe
82. OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature htm Intel Active Management Technology requires activation and a system with a corporate network connection an Intel AMT enabled chipset network hardware and software For notebooks Intel AMT may be unavailable or limited over a host OS based VPN when connecting wirelessly on battery power sleeping hibernating or powered off Results dependent upon hardware setup amp configuration For more information
83. PCISTS PCI Status Register This status register reports the occurrence of error events on Device 0 s PCI interface Since Device 0 does not physically reside on PCI_A many of the bits are not implemented B D F Type 0 0 0 PCI Address Offset 6 7h Reset Value 0090h Access RW1C RO Size 16 bits BIOS Optimal Default 00h Reset RST Value PWR Detected Parity Error DPE ae o ue This bit is set when this Device receives a Poisoned TLP 50 Datasheet Volume 2 Bit Access Description Processor Configuration Registers Size B D F Type Address Offset Reset Value Access BIOS Optimal Default 0 0 0 PCI 6 7h 0090h RW1C RO 16 bits 00h Bit Access Reset Value RST PWR Description 14 RW1C Ob Uncore Signaled System Error SSE This bit is set to 1 when Device 0 generates an SERR message over DMI for any enabled Device 0 error condition Device 0 error conditions are enabled in the PCICMD ERRCMD and DMIUEMSK registers Device 0 error flags are read reset from the PCISTS ERRSTS or DMIUEST registers Software clears this bit by writing a 1 to it 13 RW1C Ob Uncore Received Master Abort Status RMAS This bit is set when the processor generates a DMI request that receives an Unsupported Request completion packet Software clears this bit by writing a 1 to it 12 RW1C Ob Uncore Received Target Abort Status RTAS This bi
84. PWR Description 31 16 RO Oh Reserved RSVD Reject Snoop Transactions REJSNPT 0 Transactions with or without the No Snoop bit set within the 15 RO ib Uncore TLP header are allowed on the VC 1 Any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request 14 0 RO Oh Reserved RSVD 226 Datasheet Volume 2 Processor Configuration Registers intel 2 12 15 DMIVCMRCTL DMI VCm Resource Control Register Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 DMIBAR 38 3Bh 07000080h RW RO 32 bits 00000h Bit Access Reset Value RST PWR Description 31 RW Ob Uncore Virtual Channel enable VCMEN 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is currently disabled BIOS Requirement 1 To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link 2 To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared i
85. Port Virtual Channel 0 B D F Type 0 0 0 PXPEPBAR Address Offset 14 17h Reset Value 800000FFh Access RO RW Size 32 bits BIOS Optimal Default 00000h a Reset RST Sek Bit Access Value PWR Description 31 20 RO Oh Reserved RSVD Port Arbitration Select PAS This field configures the VC resource to provide a particular Port 19 17 RW 000b Uncore Arbitration service The value of Oh corresponds to the bit position of the only asserted bit in the Port Arbitration Capability field 16 0 RO Oh Reserved RSVD 308 Datasheet Volume 2 Processor Configuration Registers 2 21 Registers Default PEG DMI VTd Remapping Engine intel Table 2 24 Default PEG DMI VTd Remapping Engine Register Address Map Sheet 1 of 2 Datasheet Volume 2 Address 2 Offset Symbol Register Name Reset Value Access 0 3h VER_REG Version Register 00000010h RO 4 7h RSVD Reserved Oh RO 8 Fh CAP_REG Capability Register 902008020960 RO 10 17h ECAP_REG Extended Capability Register Ee oe RO V RO 18 1Bh GCMD_REG Global Command Register 00000000h RO WO 1C 1Fh GSTS_REG Global Status Register 00000000h RO RO V 20 27h RTADDR_REG Root Entry Table Address Register 9000070000990 RW 28 2Fh CCMD_REG Context Command Register 0000090000000 RW V RW RO V 30 33h RSVD Reserved Oh RO 34 37h FSTS_REG Fault Status Register 00000000h
86. Preset for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD 22 20 RW Lane 1 Upstream Component Receiver Preset Hint UCRPH1 Receiver Preset Hint for Upstream Component The upstream 000b Uncore SE g Eege component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 19 16 15 RW RO Lane 1 Upstream Component Transmitter Preset UCTP1 Transmitter Preset for an Upstream Component See the PCIe 1000b SE Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Oh Reserved RSVD 14 12 6 4 3 0 RW RW RO RW RW Lane 0 Downstream Component Receiver Preset Hint DCRPHO 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Downstream Component Transmitter Preset DCTPO 0111b Uncore Transmitter Preset for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are def
87. Role Based Error Reporting RBER This bit indicates that this device implements the functionality 15 RO 1b Unicorg defined in the Error Reporting ECN as required by the PCI Express 1 1 specification 14 6 RO Oh Reserved RSVD Extended Tag Field Supported ETFS 3 RO op ZE Hardwired to indicate support for 5 bit Tags as a Requestor Phantom Functions Supported PFS SS RO 00b Reder Not Applicable or Implemented Hardwired to 0 Max Payload Size MPS 2 0 RW O 000b Uncore Default indicates 128B maximum supported payload for Transaction Layer Packets TLP Datasheet Volume 2 111 112 Processor Configuration Registers DCTL Device Control Register This register provides control for PCI Express device specific capabilities The error reporting enable bits are in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR_CORR ERR_NONFATAL ERR_FATAL received by Root Port is controlled exclusively by Root Port Command Register B D F Type 0 1 0 2 PCI Address Offset A8 A9h Reset Value 0020h Access RO RW Size 16 bits BIOS Optimal Default Oh S Reset RST ine Bit Access Value PWR Description 15 RO Oh Reserved RSVD 14 12 RO 000b Uncore Reserved for Max Read Request Size MRRS 11 RO Ob Uncore Reserved for Enable No Snoop NSE 10 5 RO Oh Reserved RSVD 4 RO Ob Uncore Reserved for
88. S SS op Wide N A Hardwired to 0 Capability List CLIST 4 RO 1b Uncore This bit is set to 1 to indicate that the register at 34h provides an offset into the function s PCI Configuration Space containing a pointer to the location of the first item in the list Interrupt Status INTSTS This bit reflects the state of the interrupt in the device Only 3 RO V Ob Uncore when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1 will the devices INTx signal be asserted 2 0 RO Oh Reserved RSVD Datasheet Volume 2 151 Processor Configuration Registers intel 2 8 5 RID2 Revision Identification Register This register contains the revision number for Device 2 Functions 0 These bits are read only and writes to this register have no effect B D F Type 0 2 0 PCI Address Offset 8h Reset Value 00h Access RO FW Size 8 bits Bit Access SE it Description Revision Identification Number RID 7 0 RO FW Oh Uncore Refer to the Mobile 3rd Generation Intel Core Processor Family Specification Update for the value of the RID register 2 8 6 CC Class Code Register This register contains the device programming interface information related to the Sub Class Code and Base Class Code definition for the IGD This register also contains the Base Class Code and the function sub class in relation to the Base Class Code B D F Type 0 2 0 PCI A
89. Subsystem Vendor ID SUBVID This value is used to identify the vendor of the subsystem This 15 0 RW O 0000h Uncore register should be programmed by BIOS during boot up Once written this register becomes Read only This register can only be cleared by a Reset Datasheet Volume 2 Processor Configuration Registers intel 2 8 14 SID2 Subsystem Identification Register This register is used to uniquely identify the subsystem where the PCI device resides B D F Type 0 2 0 PCI Address Offset 2E 2Fh Reset Value 0000h Access RW 0 Size 16 bits a Reset RST SES Bit Access Value PWR Description Subsystem Identification SUBID This value is used to identify a particular subsystem This field 15 0 RW O 0000h Uncore should be programmed by BIOS during boot up Once written this register becomes Read only This register can only be cleared by a Reset 2 8 15 ROMADR Video BIOS ROM Base Address Register The IGD does not use a separate BIOS ROM therefore this register is hardwired to Os B D F Type 0 2 0 PCI Address Offset 30 33h Reset Value 00000000h Access RO Size 32 bits BIOS Optimal Default 0000h Reset RST See Bit Access Value PWR Description 31 18 RO oooh Uncore ROM Base Address RBA Hardwired to Os 17 11 RO 00h Kee Address Mask ADMSK Hardwired to Os to indicate 256 KB address range 10 1 RO Oh Reserved RSVD ROM BIOS Enab
90. TC VC Mapping Details 1 VCO enabled by default a Snoop port and Non snoop Asynchronous transactions are supported b Internal Graphics GMADR writes can occur These will NOT be snooped regardless of the snoop not required SNR bit c Internal Graphics GMADR reads unsupported d Peer writes are only supported between PEG ports PEG to DMI peer write accesses are NOT supported e MSI can occur These will route to the cores IntLogical IntPhysical regardless of the SNR bit 2 VC1 is not supported 3 VCm is not supported Datasheet Volume 2 Processor Configuration Registers D t Figure 2 8 PEG Upstream VCO Memory Map 2 3 13 3 Upstream Initiated VCO Cycle Memory Map 2 TB 64 GB TOM total physical DRAM REMAPLIMIT TOUUD REMAPBASE 4 GB FEE0_0000h FEEF_FFFFh MSI GMADR TOLUD gt TOLUD Gfx Stolen Gfx GTT stolen TSEG_BASE TSEG TSEG_BASE DPR A0000h BFFFFh VGA mem writes gt peer write if matching PEG range else invalid mem reads gt Invalid transaction mem writes gt Route based on SNR bit mem reads gt Route based on SNR bit mem writes gt CPU IntLogical IntPhysical mem reads gt Invalid transaction mem writes gt non snoop mem write mem reads gt invalid transaction GZ mem writes gt invalid transaction mem reads gt Invalid transaction Legacy VGA and I O Range Decode Rules The legacy 128 KB VGA
91. Type Address Offset Reset Value 0 0 0 VCOPREMAP 100 107h 0000000000000000h RW 64 bits BIOS Optimal Default 00000000h Bit 63 39 Access RO Reset RST Value PWR Oh Description Reserved RSVD 38 12 RW 0000000h Uncore Address ADDR Software provides the DMA address that needs to be page selectively invalidated To make a page selective invalidation request to hardware software must first write the appropriate fields in this register and then issue the appropriate page selective invalidate command through the IOTLB_REG Hardware ignores bits 63 N where N is the maximum guest address width MGAW supported RO Oh Reserved RSVD RW Oh Uncore Invalidation Hint IH The field provides hint to hardware about preserving or flushing the non leaf page directory entries that may be cached in hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware must flush both the cached leaf and non leaf page table entries corresponding to the mappings specified by ADDR and AM fields 1 Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware may preserve the cached non leaf page table entries corresponding to mappings spec
92. Type 0 0 0 GFXVTBAR Address Offset A4 A7h Reset Value 00000000h Access RW L Size 32 bits Bit Access Seas evils Description Extended Interrupt Message Data EIMD This field is valid only for implementations supporting 32 bit 31 16 RW L 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data treat this field as Rsvd Interrupt Message data IMD van AWE ogoun Reie Data value in the interrupt request 2 18 25 IEADDR_REG Invalidation Event Address Register This register specifies the Invalidation Event Interrupt message address This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset A8 ABh Reset Value 00000000h Access RW L Size 32 bits BIOS Optimal Default Oh i Reset RST BH Bit Access Value PWR Description Message address MA S S 00000000 When fault events are enabled the contents of this register oe RWE h CR specify the DWord aligned address bits 31 2 for the interrupt request 1 0 RO Oh Reserved RSVD 288 Datasheet Volume 2 Processor Configuration Registers intel 2 18 26 IEUADDR_REG Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address B D F Type 0 0 0 GFXVTBAR Address Offset AC AFh Res
93. V RW1C Size 16 bits BIOS Optimal Default 0000h gt Reset RST ah Bit Access Value PWR Description 15 6 RO Oh Reserved RSVD Link Equalization Request LNKEQREQ This bit is set by hardware to request the Link equalization 5 RWic Ob Uncore process to be performed on the Link Refer to PCIe Specification Sections 4 2 3 and 4 2 6 4 2 for details The Reset Value of this bit is Ob Equalization Phase 3 Successful EQPH3SUCC When set to 1b this bit indicates that Phase 3 of the Transmitter 3 Equalization procedure has successfully completed Details of the S ROY Ob nears Transmitter Equalization process and when this bit needs to be set to 1b is provided in PCIe Specification Section 4 2 6 4 2 The Reset Value of this bit is Ob Equalization Phase 2 Successful EQPH2SUCC When set to 1b this bit indicates that Phase 2 of the Transmitter 2 Equalization procedure has successfully completed Details of the 3 SZ o9 oncore Transmitter Equalization process and when this bit needs to be set to 1b is provided in PCIe specification Section 4 2 6 4 2 The Reset Value of this bit is Ob Equalization Phase 1 Successful EQPH1SUCC When set to 1b this bit indicates that Phase 1 of the Transmitter a Equalization procedure has successfully completed Details of the S ROY op Uncere Transmitter Equalization process and when this bit needs to be set to 1b is provided in PCIe specification Section 4 2 6 4 2 The Reset Value of this bit is Ob Equalization Comp
94. a Data Link Layer State Changed event software must read the Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device RO Ob Uncore Reserved for Electromechanical Interlock Status EIS If an Electromechanical Interlock is implemented this bit indicates the current status of the Electromechanical Interlock 0 Electromechanical Interlock Disengaged 1 Electromechanical Interlock Engaged Ob Uncore Presence Detect State PDS In band presence detect state 0 Slot Empty 1 Card present in slot This bit indicates the presence of an adapter in the slot reflected by the logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor The in band presence detect mechanism requires that power be applied to an adapter for its presence to be detected Consequently form factors that require a power controller for hot plug must implement a physical pin presence detect mechanism 0 Slot Empty 1 Card Present in slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to slots where the Slot Implemented bit of the PCI Express Capabilities Register is Ob this bit must return 1b Note PCI Express Hot Plug is not supported on the proce
95. a Register Symbol Register Name Reset Value Access 0 3h DMIVCECH DMI Virtual Channel Enhanced Capability 04010002h RO 4 7h DMIPVCCAP1 DMI Port VC Capability Register 1 00000000h RO RW O 8 Bh DMIPVCCAP2 DMI Port VC Capability Register 2 00000000h RO C Dh DMIPVCCTL DMI Port VC Control 0000h RW RO E Fh RSVD Reserved Oh RO 10 13h DMIVCORCAP DMI VCO Resource Capability 0000000ih RO 14 17h DMIVCORCTL DMI VCO Resour ce Control 8000007Fh RO RW 18 19h RSVD Reserved Oh RO 1A 1Bh DMIVCORSTS DMI VCO Resource Status 0002h RO V 1C 1Fh DMIVC1RCAP DMI VC1 Resource Capability 00008001h RO 20 23h DMIVC1RCTL DMI VC1 Resource Control 01000000h RO RW 24 25h RSVD Reserved Oh RO 26 27h DMIVC1RSTS DMI VC1 Resource Status 0002h RO V 28 2Bh DMIVCPRCAP DMI VCp Resource Capability 00000001h RO 2C 2Fh DMIVCPRCTL DMI VCp Resource Control 02000000h RO RW 30 31h RSVD Reserved Oh RO 32 33h DMIVCPRSTS DMI VCp Resource Status 0002h RO V 34 37h DMIVCMRCAP DMI VCm Resource Capability 00008000h RO 38 3Bh DMIVCMRCTL DMI VCm Resource Control 07000080h RW RO 3C 3Dh RSVD Reserved Oh RO 3E 3Fh DMIVCMRSTS DMI VCm Resource Status 0002h RO V 40 43h DMIRCLDECH DMI Root Complex Link Declaration 08010005h RO 44 47h DMIESD DMI Element Self Description 01000202h RO RW O 48 4Fh RSVD Reserved Oh RO 50 53h DMILE1D DMI Link Entry 1 Description 00000000h RW O RO 54 57h RSVD Reserved Oh RO 58 5Bh DMILE1A DMI Link Entry 1 Address 00000000h RW O 5C 5Fh DMILUE1A DMI Link Upper Entry 1 Address 0000
96. also support Queued Invalidation QI Device IOTLB Support DI 0 Hardware does not support device IOTLBs 2 RO Ob Uncore 1 Hardware supports Device IOTLBs Implementations reporting this field as set must also support Queued Invalidation QI Queued Invalidation Support QI 1 RO V 1b Uncore 0 Hardware does not support queued invalidations 1 Hardware supports queued invalidations Datasheet Volume 2 315 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 10 17h Reset Value 0000000000F010DAh Access RO V RO Size 64 bits BIOS Optimal Default 00000000000h S Reset RST ae Bit Access Value PWR Description Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent Ssnooped or not 0 RO Ob Uncore 0 Hardware accesses to remapping structures are non coherent 1 Hardware accesses to remapping structures are coherent Hardware access to advanced fault log and invalidation queue are always coherent 2 21 4 GCMD_REG Global Command Register This register controls remapping hardware If multiple control fields in this register need to be modified software must serialize the modifications through multiple writes to this register B D F Type 0 0 0 VCOPREMAP Address Offset 18 1Bh Reset Value 00000000h Access RO WO Size 32 bits BI
97. are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary This register is locked by Intel TXT BIOS must program MESEG_BASE and MESEG_MASK so that Intel ME stolen Memory is carved out from TOM B D F Type 0 0 0 PCI Address Offset 70 77h Reset Value 0000007FFFF00000h Access RW L Size 64 bits BIOS Optimal Default 000000000000h o Reset RST aia Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD ME UMA Memory Base Address MEBASE 38 20 RW L 7FFFFA Uncore This field corresponds to A 38 20 of the base address memory range that is allocated to the ME 19 0 RO Oh Reserved RSVD Datasheet Volume 2 63 Note 64 Processor Configuration Registers MESEG_MASK Intel Management Engine Limit Address Register This register determines the Mask Address register of the memory range that is pre allocated to the Intel Management Engine Together with the MESEG_BASE register it controls the amount of memory allocated to the ME This register is locked by Intel TXT BIOS must program MESEG_BASE and MESEG_MASK so that Intel ME stolen Memory is carved out from TOM B D F Type 0 0 0 PCI Address Offset 78 7Fh Reset Value 0000000000000000h Access RW L RW KL Size 64 bits BIOS Optimal Default 00000000000h P Reset RST MERTA Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD ME UMA
98. can only be routed across PEG60 if IOAE PCICMD60 0 is set 0 No MDA 1 MDA Present Datasheet Volume 2 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value 0 0 0 PCI 87h 00h RW 8 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description RW Ob Uncore PEG12 MDA Present MDAP12 This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set if Device 1 Function 2 VGA Enable bit is not set If Device 1 Function 2 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 1 Function 2 if the address is within the corresponding IOBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h 0B7FFFh 1 O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the beh
99. chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see htp www intel com info hyperthreading Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost Enhanced Intel SpeedStep Technology See the Processor Spec Finder or contact your Intel repres 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http ark intel com or contact your Intel representative for more information All products platforms dates and
100. command to data out of DDR pins This does not define the sample point in the I O This is defined by training in round trip register and other registers because this is also affected by board delays 11 8 RW L 6h Uncore Delay from CAS command to data out of DDR pins Range is 5 15 Note This does not define the sample point in the IO This is defined by training in round trip register and other registers because this is also affected by board delays Note The range of 12 15 is not yet defined by JEDEC will be tested only when such definition will exist tRP in DCLK cycles tRP a SE eh ER PRE to ACT same bank delay range is 4 15 DCLK cycles tRCD in DCLK cycles tRCD 3 0 RW L 6h Uncore ACT to CAS RD or WR same bank delay tRCD range is between 4 and 15 2 14 2 TC_RAP_Ci Timing of DDR Regular Access Parameters Register This register provides the regular timing parameters in DCLK cycles B D F Type 0 0 0 MCHBAR MCL Address Offset 4404 4407h Reset Value 86104344h Access RW L Size 32 bits e Reset RST Pare Bit Access Value PWR Description 1n 2N or 3N selection CMD_stretch This field defines the operation mode of the command 31 30 RW L 10b Uncore 00 1N operation 10 2N operation 11 3N operation Command 3 state options CMD_3st This bit defines when command amp address bus is driving d 0 Drive when channel is active Tri stated when all ranks are in 23 Gate 9b Un
101. cycle does not go to DRAM The system agent will forward this Memory Write along with the data to the processor as an Interrupt Message Transaction High BIOS Area For security reasons the processor will positively decode this range to DMI This positive decode will ensure any overlapping ranges will be ignored The top 2 MB FFEO_OOOOh FFFF_FFFFh of the PCI Memory Address Range is reserved for System BIOS High BIOS extended BIOS for PCI devices and the A20 alias of the system BIOS The processor begins execution from the High BIOS after reset This region is positively decoded to DMI The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be considered Main Memory Address Space 4 GB to TOUUD The processor supports 39 bit addressing The maximum main memory size supported is 32 GB total DRAM memory A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger As a result TOM and TOUUD registers and REMAPBASE REMAPLIMIT registers become relevant The remap configuration registers exist to remap lost main memory space The greater than 32 bit remap handling will be handled similar to other MCHs Upstream read and write accesses above 39 bit addressing will be treated as invalid cycles by PEG and DMI Top of Memory TOM The Top of Memory TOM register reflects the total amount of populated physical mem
102. dE SEENEN 38 2 3 11 1 PCI Express I O Address Mapping 38 2 3 12 MCTP and KVM FlOWSwieiscisiee vet ccund dene tes das eneed AEN facet ce e ZE 39 2 3 13 Decode Rules and Cross Bridge Address Mapping eeeeeeeeeeeeeeeee eres 39 2 3 13 1 DMI Interface Decode RUIES c eceee sees teeter eee eset eeeee enia caia 39 2 3 13 2 PCI Express Interface Decode Rules ee ee eee eens ee eeeeees 42 2 3 13 3 Legacy VGA and I O Range Decode Rule 43 2 4 0O M pped REGIStErS lt nne dee EE REENEN 46 2 5 PCI Device 0 Function 0 Configuration Space Reglsters sees ee ee eee eeee teenies 47 2 5 1 VID Vendor Identification Register 48 2 5 2 DID Device Identification Register 49 2 5 3 PCICMD PCI Command Register 49 2 5 4 PCISTS PCL Status EE 50 2 5 5 RID Revision Identification Register ccceeee eect eee e rete eee eee eeeeeeneaeas 52 2 5 6 CC Class Code Register orrena en NES Se SEN NEE d See ned 52 2 5 7 HDR Header Type Regleter ek SNEENENNEE NEES EE NEEN e Ke EEN e NENNEN NEEN 53 2 5 8 SVID Subsystem Vendor Identification Register 53 2 5 9 SID Subsystem Identification Register 53 Datasheet Volume 2 3 D Diaintn inf ininDn Dain Dn Dn Din Dn in Dn Dn a in D a Dn Dn Di WWWWWWWWWWNNNNNNNNNNRFPRPRPRPRPRPRPRP Re WOANAUBWNKFPOUWOANADUARWNKFOUWUOANDUAWNHFO eS E DAANDDDADAADADADADAAADAARAAD NNNNNNFRPRPRFPRPRPRFPRPRFPRFPOONODUBRWNEH OMBRWNRFOUWOANDUARWNFO CAPPTR Capabilit
103. defined by the length field in this register above TOLUD and still within 39 bit addressable memory space The PCI Express Base Address cannot be less than the maximum address written to the Top of physical memory register TOLUD Software must ensure that these ranges do not overlap with known ranges located above TOLUD Software must ensure that the sum of the length of the enhanced configuration region TOLUD any other known ranges reserved above TOLUD is not greater than the 39 bit addessable limit of 512 GB In general system implementation and the number of PCI PCI Express PCI X buses supported in the hierarchy will dictate the length of the region All the bits in this register are locked in Intel TXT mode B D F Type 0 0 0 PCI Address Offset 60 67h Reset Value 0000000000000000h Access RW RW V Size 64 bits BIOS Optimal Default 000000000000h e Reset RST SE Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD PCI Express Base Address PCIEXBAR This field corresponds to bits 38 28 of the base address for PCI Express enhanced configuration space BIOS will program this register resulting in a base address for a contiguous memory address space The size of the range is defined by bits 2 1 of this register This Base address shall be assigned on a boundary consistent with the number of buses defined by the Length field in this register above TOLUD and still within the 39 bit addressable 3
104. disabled on slow side 29 18 RO Oh Reserved RSVD Slow ratio for gen 3 SRG3 Se RW 190909 Uncore This field defines the BGF slow ration for gen3 BGF Ratio delta for Gen 3 RDG3 12 8 RW 00100b Uncore This register defines the BGF Ratio delta for Gen 3 Delta between the fast and slow clock multiplier 7 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D intel 2 11 18 EQPRESET1_2 Equalization Preset 1 2 Register This register contains coefficients for Preset 1 and 2 B D F Type 0 6 0 MMR Address Offset DCO DC3h Reset Value 3400FBCOh Access RW Size 32 bits BIOS Optimal Default Oh S Reset RST SC Bit Access Value PWR Description 31 30 RO Oh Reserved RSVD 29 24 RW 34h Ss Preset 2 cursor Coefficient CURSOR2 Cursor coefficient for Preset 2 23 18 RW 00h See Preset 2 Precursor Coefficient PRECUR2 Precursor coefficient for Preset 2 17 6 RO Oh Reserved RSVD Preset 1 Precursor Coefficient PRECUR1 239 RW oon Uncore Precursor coefficient for Preset 1 2 11 19 EQPRESET2_3_4 Equalization Preset 2 3 4 Register This register contains coefficients for Presets 2 3 4 B D F Type 0 6 0 MMR Address Offset DC4 DC7h Reset Value 0037100Ah Access RW Size 32 bits BIOS Optimal Default Oh Reset RST a Bit Access Value PWR Description 31 12 RO Oh Reserved RSVD 11 6 RW 00h U co e Preset 3 Precursor C
105. do not support peer to peer traffic Each bit location within this field corresponds to a Port Arbitration Capability defined below When more than one bit in this field is set it indicates that the VC resource can be configured to provide different arbitration services Software selects among these capabilities by writing to the Port Arbitration Select field see below Defined bit positions are Bit 0 Non configurable hardware fixed arbitration scheme such as Round Robin RR Bit 1 Weighted Round Robin WRR arbitration with 32 phases Bit 2 WRR arbitration with 64 phases Bit 3 WRR arbitration with 128 phases Bit 4 Time based WRR with 128 phases Bit 5 WRR arbitration with 256 phases Bits 6 7 Reserved Processor only supported arbitration indicates Non configurable hardware fixed arbitration scheme Datasheet Volume 2 Processor Configuration Registers intel 2 11 5 VCORCTL VCO Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0 B D F Type 0 6 0 MMR Address Offset 114 117h Reset Value 800000FFh Access RO RW Size 32 bits BIOS Optimal Default 0000h Reset RST SCH Bit Access Value PWR Description VCO Enable VCOE 31 RO 1b Uncore For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved RSVD VCO ID VCOID 26 24 RO 000b Uncore Assigns a VC ID to the VC resource
106. figures specified are preliminary based on current expectations and are subject to change without notice All dates specified are target dates are provided for planning purposes only and are subject to change Intel Intel Core and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2012 Intel Corporation All rights reserved 2 Datasheet Volume 2 Contents 1 dee od Le Lu WEE 13 Processor Configuration Registers ccceceee cece eee eee eee een eee eee eene ea eees 15 ZE Register TerminGQlOGy vate atskasgtessmde enge AE ee GES de eet NEE EE AE 15 2 2 PCI Deviees ANd FUNCIONS serne ninni a Bes vg SERGE dE NE EE E NEE 16 2 3 System Address Map 001ENE bebe EE REENEN dae ENEE EENS EE SEENEN ater nares 17 2 3 1 Legacy Address Range siissciceniece eng de SEENEN ENEE dE EE AER E EA deeg e 19 2 3 1 1 DOS Range QH 9_FRFEN wisciecsisesessseececa si vaeeds ceed ede dE KEK AEN ENEE 20 2 3 1 2 Legacy Video Area A OOO0b PB FEEF 20 SL PAM C Q0QQO0H F_FRFFA wis ira ennie EENS ge KEE EENS NEEN EN 2 3 2 Main Memory Address Range 1 MB TOLUD teen ees 22 2 3 2 1 ISA Hole 15 MB 16 MB EENS NNN KNNNEN ER NENNEN ENEE ENNEN ANEN 22 K Oe e EE 23 2 3 2 3 Protected Memory Range PMR programmable nossscccererrcs 23 2 3 2 4 DRAM Protected Range DR 24 2 3 2 5 Pre allocated Memonm NENNEN ENNER ER NENERENR NE
107. hardware read modify write thus there is a small chance of misreporting B D F Type 0 0 0 MCHBAR PCU Address Offset 5C24 5C27h Default Value 00000000h Access RW Size 32 bits S Reset RST ae Bit Access Value PWR Description ppi_clipped aa RW 00900000 Uncore Set if the PP1 GT frequency requested was clipped 30 RW 00000000h Reserved RSVD ppi_clipped_non_turbo 29 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped but current frequency is lower than RP1 MAX_NON_TURBO 28 25 RW 00000000h Reserved RSVD ppi_clipped_edp 24 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by EDP limit Vmax Iccmax Reliability and so on 23 RW 00000000h Reserved RSVD ppi_clipped_hot_vr 22 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by HOT indication from VR on SVID p1_clipped_pl2 21 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by PL2 POWER_LIMIT_2 power limiting algorithm 20 19 RW 00000000h Reserved RSVD ppi_clipped_pl1i 18 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by PL1 POWER_LIMIT_1 power limiting algorithm ppi_clipped_thermals 17 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by internal Thermal Throttling algorithm ppi_clipped_ext_prochot 16 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by exte
108. if the address is within the corresponding IOBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h 0B7FFFh I O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 0 All References to MDA and VGA space are not claimed by Device 1 Function 1 0 1 Illegal combination 1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 1 1 1 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 1 MDA references are not claimed by Device 1 Function 1 VGA and MDA memory cycles can only be routed across PEG11 when MAE PCICMD11 1 is set VGA and MDA I O cycles can only be routed across PEG11 if IOAE PCICMD11 0 is set Datasheet Volume 2 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value 0 0 0 PCI 87h 00h RW 8 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description RW Ob Uncore PEG10 MDA Present MDAP10 This bit works with the VGA Enable bits in the BCTRL register of Device
109. invalidation enable status 0 queued invalidation is not enabled 1 queued invalidation is enabled 25 RO V Ob Uncore Interrupt Remapping Enable Status IRES This field indicates the status of Interrupt remapping hardware 0 Interrupt remapping hardware is not enabled 1 Interrupt remapping hardware is enabled 24 RO V Ob Uncore Interrupt Remapping Table Pointer Status IRTPS This field indicates the status of the interrupt remapping table pointer in hardware This field is e Cleared by hardware when software sets the SIRTP field in the Global Command register e Set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers intel 2 21 6 RTADDR_REG Root Entry Table Address Register This register provides the base address of root entry table B D F Type 0 0 0 VCOPREMAP Address Offset 20 27h Reset Value 000000000000000 0h Access RW Size 64 bits BIOS Optimal Default 0000000000h S Reset RST SC Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Root Table Address RTA This register points to base of page aligned 4 KB sized root entry table in system memory Hardware ignores and not implements bits 63 HAW where HAW is the host address width 38 12 R
110. memory base register disables the protected low memory region Software must not modify this register when protected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 6C 6Fh Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 00000h Reset RST Bit Access Value PWR Description Protected Low Memory Limit PLML 31 20 RW 000h Uncore This register specifies the last host physical address of the DMA protected low memory region in system memory 19 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D t I H 2 18 17 PHMBASE_REG Protected High Memory Base Register This register sets up the base address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os
111. memory range 000A_0000h 000B_FFFFh can be mapped to IGD Device 2 PCI Express Device 1 Functions or Device 6 and or to the DMI Interface depending on the programming of the VGA steering bits Priority for VGA mapping is constant in that the processor always decodes internally mapped devices first Internal to the processor decode precedence is always given to IGD The processor always positively decodes internally mapped devices namely the IGD Subsequent decoding of regions mapped to either PCI Express port or the DMI Interface depends on the Legacy VGA configurations bits VGA Enable amp MDAP For the remainder of this section PCI Express can refer to either the Device 1 port functions or the Device 6 port VGA range accesses will always be mapped as UC type memory Datasheet Volume 2 43 intel Accesses to the VGA memory range are directed to IGD depend on the configuration The configuration is specified by e Internal Graphics Controller in Device 2 is enabled DEVEN D2EN bit 4 e Internal Graphics VGA in Device 0 Function 0 is enabled through register GGC bit 1 e IGD Memory accesses PCICMD2 04 05h MAE bit 1 in Device 2 configuration space are enabled Table 2 5 Note Table 2 6 Note 44 Processor Configuration Registers e VGA Compatibility Memory accesses VGA Miscellaneous output Register MSR Register bit 1 are enabled e Software sets the proper value for VGA Memory Map Mode Register VGA
112. memory region6 if the platform supports main memory above 4 GB Once the protected low high memory region registers are configured bus master protection to these regions is enabled through the Protected Memory Enable register For platforms with multiple DMA remapping hardware units each of the DMA remapping hardware units must be configured with the same protected memory regions and enabled Datasheet Volume 2 23 DN t Processor Configuration Registers 2 3 2 4 2 3 2 5 2 3 2 6 2 3 2 6 1 24 DRAM Protected Range DPR This protection range only applies to DMA accesses and GMADR translations It serves a purpose of providing a memory range that is only accessible to processor streams The DPR range works independent of any other range including the PMRC checks in VTd It occurs post any VTd translation Therefore incoming cycles are checked against this range after the VTd translation and faulted if they hit this protected range even if they passed the VTd translation The system will set up e 0 to TSEG_BASE DPR size 1 for DMA traffic e TSEG_BASE to TSEG_BASE DPR size as no DMA After some time software could request more space for not allowing DMA It will get some more pages and make sure there are no DMA cycles to the new region DPR size is changed to the new value When it does this there should not be any DMA cycles going to DRAM to the new region If there were cycles from a rogue device
113. of the lower limit of the memory range that will be passed to PCI Express G 3 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D t I H 2 10 16 Note Note MLIMIT Memory Limit Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCI Express memory access performance Configuration software is responsible for programming all a
114. presence detect changed event Ob Uncore Reserved for MRL Sensor Changed Enable MSCE When set to 1b this bit enables software notification on a MRL sensor changed event Reset Value of this field is Ob If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Ob Uncore Reserved for Power Fault Detected Enable PFDE When set to 1b this bit enables software notification on a power fault event Reset Value of this field is Ob If Power Fault detection is not supported this bit is permitted to be read only with a value of Ob Ob Uncore Reserved for Attention Button Pressed Enable ABPE When set to 1b this bit enables software notification on an attention button pressed event Datasheet Volume 2 199 intel Processor Configuration Registers 2 10 43 SLOTSTS Slot Status Register This is a PCI Express Slot related register 200 Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 6 0 PCI BA BBh 0000h RO RO V RW1C 16 bits 00h Bit Access Reset Value RST PWR Description 15 9 RO Oh Reserved RSVD RO Ob Uncore Reserved for Data Link Layer State Changed DLLSC This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed In response to
115. respond to a power up request based on a detected fault condition independent of the Power Controller Control setting The defined encodings are 0 Power On 1 Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob then writes to this field have no effect and the read value of this field is undefined 9 8 RO 00b Uncore Reserved Power Indicator Control PIC If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 6 0 PCI B8 B9h 0000h RO 16 bits Oh Bit Access Reset Value RST PWR Description 7 6 RO 00b Uncore Reserved for Attention Indicator Control AIC If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must ref
116. structure B D F Type 0 6 0 PCI Address Offset AO Aih Reset Value 0010h Access RO Size 16 bits e Reset RST anias Bit Access Value PWR Description Pointer to Next Capability PNC This value terminates the capabilities list The Virtual Channel 15 8 RO 00h Uncore Capability and any other PCI Express specific capabilities that are i reported using this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space Capability ID CID 7 0 RO 10h Uncore This field identifies this linked list item capability structure as being for PCI Express registers Datasheet Volume 2 187 Processor Configuration Registers intel 2 10 34 PEG_CAP PCI Express G Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 6 0 PCI Address Offset A2 A3h Reset Value 0142h Access RO RW O Size 16 bits BIOS Optimal Default Oh 5 Reset RST noae Bit Access Value PWR Description 15 14 RO Oh Reserved RSVD Interrupt Message Number IMN 13 9 RO 00h 3 9 ancore Not Applicable or Implemented Hardwired to 0 Slot Implemented SI 0 The PCI Express Link associated with this port is connected to an integrated component or is disabled 8 RW O 1b Uncore 1 The PCI Express Link associated with this port is connected to a slot BIOS Requirement This field must be initialized appropriately if a sl
117. supporting 32 bit 31 16 RW 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data may treat this field as RsvdZ 15 0 RW 0000h Uiicore Interrupt Message Data IMD Data value in the interrupt request 2 21 11 FEADDR_REG Fault Event Address Register This register specifies the interrupt message address B D F Type 0 0 0 VCOPREMAP Address Offset 40 43h Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default Oh Reset RST Se Bit Access Value PWR Description Message Address MA 00000000 When fault events are enabled the contents of this register oe ee h SR specify the DWord aligned address bits 31 2 for the interrupt request 1 0 RO Oh Reserved RSVD 2 21 12 FEUADDR_REG Fault Event Upper Address Register This register specifies the interrupt message upper address B D F Type 0 0 0 VCOPREMAP Address Offset 44 47h Reset Value 00000000h Access RW Size 32 bits Reset RST BE Bit Access Value PWR Description Message upper address MUA Hardware implementations supporting Extended Interrupt Mode 31 0 RW 00000000h Uncore are required to implement this register Hardware implementations not supporting Extended Interrupt Mode may treat this field as RsvdZ Datasheet Volume 2 327 intel 2 21 13 328 Processor Configuration Registers AFLOG_REG Advanced Fault Log Register T
118. the physical component that is targeted by this link 23 16 RW O 00h Uncore Entry i _ eee BIOS Requirement This field must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 RO Oh Reserved RSVD Link Type LTYP This bit indicates that the link points to memory mapped space 1 RO Ob Uncore for RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 RW O Ob Uncore 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link ll 230 Datasheet Volume 2 Processor Configuration Registers intel 2 12 20 DMILELA DMI Link Entry 1 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 58 5Bh Reset Value 00000000h Access RW O Size 32 bits BIOS Optimal Default 000h Reset RST Bit Access Value PWR Description Link Address LA 31 12 RW O 00000h Uncore Memory mapped base address of the RCRB that is the target element egress port of PCH for this link entry 11 0 RO Oh Reserved RSVD 2 12 21 DMILUE1A DMI Link Upper Entry 1 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element
119. the value 010001b which maps TC1 and TC5 to VC1 Traffic Class 0 Virtual Channel 1 Map TCOVC1M RO ob SE Traffic Class 0 is always routed to VCO Datasheet Volume 2 223 intel Processor Configuration Registers 2 12 10 DMIVC1RSTS DMI VC1 Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMIBAR Address Offset 26 27h Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h e Reset RST ear Bit Access Value PWR Description 15 2 RO Oh Reserved RSVD Virtual Channel 1 Negotiation Pending VC1NP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This bit indicates the status of the process of Flow Control 1 RO V 1b Uncore initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Oh Reserved RSVD 2 12 11 DMIVCPRCAP DMI VCp Resource Capability Register B D F Type 0 0 0 DMIBAR Address Offset 28 2Bh Reset Value
120. to Back Enable FB2B This bit controls whether or not the master can do fast back to 9 RO Ob Uncore back write Since Device 0 is strictly a target this bit is not implemented and is hardwired to 0 Writes to this bit position have no effect SERR Enable SERRE This bit is a global enable bit for Device 0 SERR messaging The processor communicates the SERR condition by sending an SERR message over DMI to the PCH 1 The processor is enabled to generate SERR messages over DMI for specific Device 0 error conditions that are individually enabled in the ERRCMD and DMIUEMSK registers The error status is reported in the ERRSTS PCISTS and DMIUEST registers 0 The SERR message is not generated by the Host for Device 0 This bit only controls SERR messaging for Device 0 Other integrated devices have their own SERRE bits to control error reporting for error conditions occurring in each device The control bits are used in a logical OR manner to enable the SERR DMI message mechanism 0 Device 0 SERR disabled 1 Device 0 SERR enabled 8 RW Ob Uncore Datasheet Volume 2 49 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 4 5h Reset Value 0006h Access RO RW Size 16 bits BIOS Optimal Default 00h Reset RST meS Bit Access Value PWR Description Address Data Stepping Enable ADSTEP Address data stepping is not implemented in the processor and 7 RO Ob
121. to INTC A value of 4 corresponds to INTD Devices or device functions that do not use an interrupt pin must put a 0 in this register The values 05h through FFh are reserved This register is write once BIOS must set this register to select the INTx to be used by this root port 2 10 24 BCTRL Bridge Control Register This register provides extensions to the PCICMD register that are specific to PCI PCI bridges The BCTRL provides additional control for the secondary interface that is PCI Express G as well as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within the processor such as VGA compatible address ranges mapping B D F Type 0 6 0 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh Reset RST SE Bit Access Value PWR Description 15 12 RO Oh Reserved RSVD Discard Timer SERR Enable DTSERRE ge RO ob SES Not Applicable or Implemented Hardwired to 0 Discard Timer Status DTSTS 19 RO Ge Ungorg Not Applicable or Implemented Hardwired to 0 Secondary Discard Timer SDT 9 RO b a Uneore Not Applicable or Implemented Hardwired to 0 Primary Discard Timer PDT S RO Ob SS Not Applicable or Implemented Hardwired to 0 Fast Back to Back Enable FB2BEN RO Ge SES Not Applicable or Implemented Hardwired to 0 Datasheet Volume 2 179 Processor Configuration R
122. to access internal graphics MMIO registers must not be used to access VGA I O registers that are mapped through the MMIO space VGA registers must be accessed directly through the dedicated VGA I O ports Trusted Graphics Ranges No trusted graphics ranges are supported Datasheet Volume 2 Processor Configuration Registers D t I H 2 3 8 Table 2 4 2 3 9 2 3 10 System Management Mode SMM The Core handles all SMM mode transaction routing Also the platform no longer supports HSEG The processor will not allow I O devices access to CSEG TSEG HSEG ranges DMI Interface and PCI Express masters are not allowed to access the SMM space SMM Regions SMM Space Enabled Transaction Address Space DRAM Space DRAM Compatible 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh TSEG TOLUD STOLEN TSEG to TOLUD STOLEN TSEG to TOLUD STOLEN TOLUD STOLEN SMM and VGA Access through GTT TLB Accesses through GTT TLB address translation SMM DRAM space are not allowed Writes will be routed to Memory address 000C_0000h with byte enables de asserted and reads will be routed to Memory address 000C_0000h If a GTT TLB translated address hits SMM DRAM space the graphics device will report a page table error PCI Express and DMI Interface originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation If a GTT TLB translated address hits enabled SMM DRAM sp
123. to indicate that this is a multi function 7 0 RO 8ih Uncore device with bridge header layout Device 6 returns O1h to indicate that this is a single function device with bridge header layout 2 6 9 PBUSN Primary Bus Number Register This register identifies that this virtual Host PCI Express bridge is connected to PCI bus 0 B D F Type 0 1 0 2 PCI Address Offset 18h Reset Value 00h Access RO Size 8 bits 4 Reset RST SS Bit Access Value PWR Description Primary Bus Number BUSN Configuration software typically programs this field with the 7 0 RO 00h Uncore number of the bus on the primary side of the bridge Since the processor root port is an internal device and its primary bus is always 0 these bits are read only and are hardwired to 0 2 6 10 SBUSN Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the virtual bridge that is to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 1 0 2 PCI Address Offset 19h Reset Value 00h Access RW Size 8 bits Reset RST is Bit Access Value PWR Description Secondary Bus Number BUSN 7 0 RW 00h Uncore This field is programmed by configuration software with the bus number assigned to PCI Express G Datasheet Volume 2 93 94 Processor Configuration Registers SUBUSN Subordinate Bus
124. to the new region then those could use the previous decode until the new decode can ensure PV No flushing of cycles is required On a clock by clock basis proper decode with the previous or new decode needs to be ensured All upstream cycles from 0 to TSEG_BASE 1 DPR size and not in the legacy holes VGA are decoded to DRAM Because Bus Master cycles can occur when the DPR size is changed the DPR size needs to be treated dynamically Pre allocated Memory Voids of physical addresses that are not accessible as general system memory and reside within system memory address range lt TOLUD are created for SMM mode legacy VGA graphics compatibility and graphics GTT stolen memory It is the responsibility of BIOS to properly initialize these regions Graphics Stolen Spaces GTT Stolen Space GSM GSM is allocated to store the graphics GFX translation table entries GSM always exists regardless of VT d as long as internal graphics is enabled This space is allocated to store accesses as page table entries are getting updated through virtual GTTMMADR range Hardware is responsible to map PTEs into this physical space Direct accesses to GSM are not allowed only hardware translations and fetches can be directed to GSM Datasheet Volume 2 Processor Configuration Registers D t I H 2 3 2 7 Intel Management Engine Intel ME UMA Intel ME the AMT Intel Management Engine can be allocated UMA memory Intel MEmemory is
125. which is useful for memory access indication and early path indication TOLUD can be 1 MB aligned TSEG_BASE The TSEG_BASE register reflects the total amount of low addressable DRAM below TOLUD BIOS will calculate and program this register so the system agent has knowledge of where TOLUD GFX stolen GFX GTT stolen TSEG is located I O blocks use this minus DPR for upstream DRAM decode Memory Re claim Background The following are examples of Memory Mapped I O devices are typically located below 4 GB e High BIOS es TSEG e GFX stolen e GTT stolen e XAPIC e Local APIC e MSI Interrupts e Mbase Mlimit e PMbase PMlimit e Memory Mapped IO space that supports only 32B addressing The processor provides the capability to re claim the physical memory overlapped by the Memory Mapped IO logical address space The MCH re maps physical memory from the Top of Low Memory TOLUD boundary up to the 4 GB boundary to an equivalent sized logical address range located just below the Intel Management Engine stolen memory Datasheet Volume 2 Processor Configuration Registers 2 3 4 2 2 3 4 3 2 3 4 4 Indirect Accesses to MCHBAR Registers Similar to prior chipsets MCHBAR registers can be indirectly accessed using e Direct MCHBAR access decode Cycle to memory from processor Hits MCHBAR base AND MCHBAR is enabled AND Within MMIO space above and below 4 GB e GTTMMADR 10000h 13FFFh range gt MCH
126. with a Type 1 Configuration header when the Completer Abort was generated by its Primary Side Reset Value of this bit is Ob Not Applicable or Implemented Hardwired to 0 The concept of a target abort does not exist on primary side of this device 11 RO Ob Uncore DEVSELB Timing DEVT This device is not the subtractively decoded device on bus 0 This 10 9 RO 00b Uncore bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode Does not apply to PCI Express and must be hardwired to 00b Master Data Parity Error PMDPE This bit is set by a Requester Primary Side for Type 1 Configuration Space header Function if the Party Error Response bit in the Command register is 1b and either of the following two conditions occurs e Requester receives a Completion marked poisoned 8 RW1C Ob Uncore e Requester poisons a write Request If the Parity Error Response bit is Ob this bit is never set Reset Value of this bit is Ob This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned peer to peer posted forwarded will not set this bit They are reported at the receiving port Fast Back to Back FB2B 7 RO b 0 Ve Not Applicable or Implemented Hardwired to 0 6 RO Oh Reserved RSVD 66 60MHz capability CAP66 gt RO ob SE Not Applicable or Implemented Hardwired to 0 Capabilities List CAPL S RO tb EES Indicates that a c
127. write and correspond to address bits A 38 32 of the 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 1 0 2 PCI Address Offset 2C 2Fh Reset Value 00000000h Access RW Size 32 bits Reset RST SR Bit Access Value PWR Description Prefetchable Memory Address Limit PMLIMITU This field corresponds to A 63 32 of the upper limit of the 31 0 RW 00000900 ZS prefetchable Memory range that will be passed to PCI Express G CAPPTR Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities B D F Type 0 1 0 2 PCI Address Offset 34h Reset Value 88h Access RO Size 8 bits Bit Access ott ga Description First Capability CAPPTR1 7 0 RO 88h Uncore The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability Datasheet Volume 2 101 Processor Configuration Registers 2 6 22 INT
128. 00000001h Access RO Size 32 bits BIOS Optimal Default 00h Reset RST DES Bit Access Value PWR Description 31 24 RO 00h Uncore Reserved for Port Arbitration Table Offset PATO 23 RO Oh Reserved RSVD 22 16 RO 00h Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions REJSNPT 0 Transactions with or without the No Snoop bit set within the 15 RO Ob Uncore TLP header are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request 14 8 RO Oh Reserved RSVD 7 0 RO Oih Uncore Reserved for Port Arbitration Capability PAC 224 Datasheet Volume 2 Processor Configuration Registers intel 2 12 12 DMIVCPRCTL DMI VCp Resource Control Register This register controls the resources associated with the DMI Private Channel VCp B D F Type 0 0 0 DMIBAR Address Offset 2C 2Fh Reset Value 02000000h Access RO RW Size 32 bits BIOS Optimal Default 00000h Bit Access PEE vlt Description Virtual Channel private Enable VCPE 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express
129. 0000h RW O 60 63h DMILE2D DMI Link Entry 2 Description 00000000h RO RW O 64 67h RSVD Reserved Oh RO 68 6Bh DMILE2A DMI Link Entry 2 Address 00000000h RW O 6C 6Fh RSVD Reserved 00000000h RW O 70 7Fh RSVD Reserved Oh RO 80 83h RSVD Reserved 00010006h RO 84 87h LCAP Link Capabilities 0001AC41h e 88 89h LCTL Link Control 0000h RW RW V Datasheet Volume 2 217 intel Processor Configuration Registers Table 2 15 DMIBAR Register Address Map Sheet 2 of 2 grees Register Symbol Register Name Reset Value Access 8A 8Bh LSTS DMI Link Status 0001h RO V 8C 97h RSVD Reserved Oh RO 98 99h LCTL2 Link Control 2 0002h RWS RWS V 9A 9Bh LSTS2 Link Status 2 0000h RO V 9C D33h RSVD Reserved Oh RO D34 D37h RSVD Reserved 0000005Fh RW RW1CS 2 12 1 DMIVCECH DMI Virtual Channel Enhanced Capability Register This register indicates DMI Virtual Channel capabilities B D F Type 0 0 0 DMIBAR Address Offset 0 3h Reset Value 04010002h Access RO Size 32 bits a Reset RST paar Bit Access Value PWR Description Pointer to Next Capability PNC i This field contains the offset to the next PCI Express capability 1 2 RO 40h 31 20 o SES structure in the linked list of capabilities Link Declaration Capability PCI Express Virtual Channel Capability Version PCIEVCCV 19 16 RO th Uncore Hardwired to 1 to indicate compliances with the 1 1 version of the PCI Express specifi
130. 01Ah Access RO RO V Size 64 bits BIOS Optimal Default 00000000000h 3 Reset RST Pare Bit Access Value PWR Description Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent snooped or not 0 RO Ob Uncore 0 Hardware accesses to remapping structures are non coherent 1 Hardware accesses to remapping structures are coherent Hardware access to advanced fault log and invalidation queue are always coherent 2 18 4 GCMD_REG Global Command Register This register controls remapping hardware If multiple control fields in this register need to be modified software must serialize the modifications through multiple writes to this register B D F Type 0 0 0 GFXVTBAR Address Offset 18 1Bh Reset Value 00000000h Access RO WO Size 32 bits BIOS Optimal Default 000000h j Reset RST S Bit Access Value PWR Description Translation Enable TE Software writes to this field to request hardware to enable disable DMA remapping 0 Disable DMA remapping 1 Enable DMA remapping Hardware reports the status of the translation enable operation through the TES field in the Global Status register 31 wo op adore There may be active DMA requests in the platform when software updates this field Hardware must enable or disable remapping logic only at deterministic transaction boundaries so that any in flight transaction is either subj
131. 0b Uncore Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only 23 20 RO Oh Reserved RSVD Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service This field is valid for RCRBs Root Ports that support peer to peer traffic and Switch Ports but not for PCI n Express Endpoint devices or Root Ports that do not support peer 19 17 RW 000b Uncore to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource This field does not affect the root port behavior 16 RO Oh Reserved RSVD TC High VCO Map TCHVCOM 15 8 RW 00h Uncore Allow usage of high order TCs BIOS should keep this field zeroed to allow usage of the reserved TC 3 for other purposes TC VCO Map TCVCOM This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped 7 1 RW 7Fh Uncore to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link 0 RO ib U core TCO VCO Map TCOVCOM Traffic Class 0 is al
132. 0h X16 All other encodings are reserved Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link The encoding is the binary value of the bit location in the Supported Link Speeds Vector in the Link Capabilities 2 register 3 0 RO Oh Uncore that corresponds to the current Link speed For example a value of 0010b in this field indicates that the current Link speed is that corresponding to bit 2 in the Supported Link Speeds Vector which is 5 0 GT s All other encodings are reserved The value in this field is undefined when the Link is not up 2 10 41 SLOTCAP Slot Capabilities Register Note PCI Express Hot Plug is not supported on the processor 196 B D F Type 0 6 0 PCI Address Offset B4 B7h Reset Value 00040000h Access RW O RO Size 32 bits Reset RST Peer Bit Access Value PWR Description Physical Slot Number PSN This field indicates the physical slot number attached to this Port 31 19 RW O 0000h Uncore BIOS Requirement This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis No Command Completed Support NCCS When set to 1b this bit indicates that this slot does not generate software notification when an issued command is completed by 18 RO 1b Uncore the Hot Plug Controller This bit is only permitted to be set to 1b if the hot plug capable port is able to accept
133. 1 DN t l Processor Configuration Registers 2 21 17 332 PHMBASE_REG Protected High Memory Base Register This register sets up the base address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software may set up the protected high memory region either above or below 4 GB Software must not modify this register when protected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 70 77h Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 000000000000h e Reset RST SES Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Protected High Memory Base PHMB This register specifies the base of protected high memory 38 20 RW 00000h Uncore region in system memory Hardware ignores a
134. 1 DMIVCPRCAP DMI VCp Resource Capability Register 224 2 12 12 DMIVCPRCTL DMI VCp Resource Control Register eeeeeeeeeeeeeee ees 225 2 12 13 DMIVCPRSTS DMI VCp Resource Status Register 226 2 12 14 DMIVCMRCAP DMI VCm Resource Capability Register 226 2 12 15 DMIVCMRCTL DMI VCm Resource Control Register 227 2 12 16 DMIVCMRSTS DMI VCm Resource Status Register 228 2 12 17 DMIRCLDECH DMI Root Complex Link Declaration Register 228 2 12 18 DMIESD DMI Element Self Description Register 229 2 12 19 DMILE1D DMI Link Entry 1 Description Register 230 2 12 20 DMILE1A DMI Link Entry 1 Address Register 231 2 12 21 DMILUE1A DMI Link Upper Entry 1 Address Register cseeeeeeeeees 231 2 12 22 DMILE2D DMI Link Entry 2 Description Register 232 2 12 23 DMILE2A DMI Link Entry 2 Address Register 233 2 12 24 LCAP Link Capabilities Register 233 2 12 25 LCTL Link Control Register 234 2 12 26 LSTS DMI Link Status Register 235 2 12 27 LCTL2 Link Control 2 Register 236 2 12 28 LSTS2 Link Status 2 Register sorsia iniaa a adaa 238 2 13 MCHBAR Registers in Memory Controller Channel 0 Register 239 2 13 1 TC_DBP_CO Timing of DDR Bin Parameters Register 240 2 13 2 TC_RAP_CO0 Timing of DDR Regular Access Parameters Register 241 Datasheet Volume 2 7 D 2 18 2 13 3 SC_IO_LATENCY_CO IO Latency configuration Register 242 2 13 4 TC_SRFTP_C0
135. 1 MB aligned gt 1 MB aligned GFX Stolen GFX Stolen BASE 1 MB aligned GFX GTT STOLEN GFX GTT Stolen BASE 1 MB aligned TSEG TSEG TSEG BASE 1 MB aligned LOW OS VISIBLE DRAM lt 4GB 0 0 e Populated Physical Memory 2 GB e Address Space allocated to Memory Mapped IO 1 GB e Remapped Physical Memory 0 GB e TOM 00_7FFO_0000h 2 GB e ME base 00_7FFO_0000h 1 MB e ME Mask 00_7FFO_0000h e TOUUD 00_0000_0000h Disable Avoid access above 4 GB e TOLUD 00_7FEO_0000h 2 GB minus 1 MB e REMAPBASE 7F_FFFF_0000h default e REMAPLIMIT 00_0000_0000h 0 GB boundary default Datasheet Volume 2 31 Processor Configuration Registers intel 2 3 4 5 2 Case 2 Greater than 4 GB of Physical Memory Figure 2 6 Case 2 Greater than 4 GB of Physical Memory Physical Memo Host System View y ry DRAM Controller View 512 GB High PCI Memory Add Range subtractively decoded to RU ToM C i TOUUD BASE L_ 1 MB aligned Reclaim Limit Reclaim Base x Main 1 MB aligned Memory ME UMA Reclaim Reclaim BASE Add Range MESEG BASE t 1 MB aligned 1 MB aligned Main memory OS visible Address gt A GR Range 4 GB Flash APIC Intel TXT OS invisible FECO_0000 8 OME x Reclaim TOLUD BASE Kaz Weg t PCI Or reciaim SaaS lemon GFX Stolen 0 256 MB Add Range GFX Stolen BASE subtractively 1 MB aligned decoded to GFX GTT DMI STOLEN
136. 11 Domain page selective invalidation performed using the address mask and hint specified by software in the Invalidate Address register and domain id specified in DID field This can be in response to a page selective invalidation request 56 50 RO Oh Reserved RSVD 49 RW Ob Uncore Drain Reads DR This field is ignored by hardware if the DRD field is reported as clear in the Capability register When the DRD field is reported as set in the Capability register the following encodings are supported for this field 1 Hardware may complete the IOTLB invalidation without draining any translated DMA read requests 1 Hardware must drain DMA read requests 48 RW Ob Uncore Drain Writes DW This field is ignored by hardware if the DWD field is reported as clear in the Capability register When the DWD field is reported as set in the Capability register the following encodings are supported for this field 0 Hardware may complete the IOTLB invalidation without draining DMA write requests 1 Hardware must drain relevant translated DMA write requests 47 40 RO Oh Reserved RSVD 39 32 RW 00h Uncore Domain ID DID This field indicates the ID of the domain whose IOTLB entries need to be selectively invalidated This field must be programmed by software for domain selective and page selective invalidation requests The Capability register reports the do
137. 17 INTRLINE Interrupt Line Register 158 2 8 18 INTRPIN Interrupt Pin Register 158 2 8 19 MINGNT Minimum Grant Register 158 2 8 20 MAXLAT Maximum Latency Register cecceeeeee reese etter eee eee ee eeaeeeeenaes 159 2 8 21 MSAC Multi Size Aperture Control Register cc ceeeeeeeeeeeeeee eee eeeeeaes 159 2 9 DEVICE 2 10 REGISLEIS aicicivcncescsareecntsvoaadwaced a Cond ey ieeuats A BEA 160 2 9 1 Index MMIO Address Register 160 2 9 2 Data MMIO Data Registe i ciccciscctidcccvecie SEENEN KEEN SEN na a 160 2 10 PCI Device 6 REGISUELS ie cceincencentiie AEN KREE tec kiini aai inatia REES KEE EEN cedencevntee 161 2 10 1 VID Vendor Identification Register 162 2 10 2 DID Device Identification Register 163 2 10 3 PCICMD PCI Command Register 163 2 10 4 PCISTS PCL Status REGI EE 166 2 10 5 RID Revision Identification Register 167 2 10 6 CC Class Code Register serisini naiai NETE Er O EEAS 168 210 7 Ch Cache line Size Registef ies ictecacitcsaieetescsrentee na a aa a ada 168 2 10 8 HDR Header Type Regleter nsnsi nienia i ariora 168 2 10 9 PBUSN Primary Bus Number Register ssssssssssssrssrrrsrrrrnrsrrrnrrnrrnnsrnnrs 169 2 10 10 SBUSN Secondary Bus Number Register 169 2 10 11 SUBUSN Subordinate Bus Number Register 169 2 10 12 IOBASE I O Base Address Register 170 2 10 13 IOLIMIT I O Limit Address Register 170 2 10 14 SSTS Secondary Status Register 171 2 10 15 MBASE
138. 1Ah SUBUSN Subordinate Bus Number 00h RW 1Bh RSVD Reserved Oh RO 1Ch IOBASE I O Base Address FOh RW 1Dh IOLIMIT I O Limit Address 00h RW 1E 1Fh SSTS Secondary Status 0000h RW1C RO 20 21h MBASE Memory Base Address FFFOh RW 22 23h MLIMIT Memory Limit Address 0000h RW 24 25h PMBASE Prefetchable Memory Base Address FFFih RW RO 26 27h PMLIMIT Prefetchable Memory Limit Address 0001h RW RO 28 2Bh PMBASEU ae Memory Base Address 00000000h RW 2C 2Fh PMLIMITU Py Memory Limit Address 00000000h RW 30 33h RSVD Reserved Oh RO 34h CAPPTR Capabilities Pointer 88h RO 35 3Bh RSVD Reserved Oh RO 3Ch INTRLINE Interrupt Line 00h RW 3Dh INTRPIN Interrupt Pin Oih RW O RO 3E 3Fh BCTRL Bridge Control 0000h RO RW 40 7Fh RSVD Reserved Oh RO 80 83h PM_CAPID Power Management Capabilities C8039001h RO RO V 84 87h PM_CS Power Management Control Status 00000008h RO RW Subsystem ID and Vendor ID 88 8Bh SS_CAPID Capabilities 0000800Dh RO 8C 8Fh ss oe ID and Subsystem Vendor 00008086h RW O Datasheet Volume 2 161 intel Table 2 13 PCI Device 6 Register Address Map Sheet 2 of 2 Processor Configuration Registers Address Register Offset Symbol Register Name Reset Value Access 90 91h MSI_CAPID Ch Signaled Interrupts Capability A005h RO 92 93h MC Message Control 0000h RO RW 94 97h MA Message Address 00000000h RW RO 98 99h MD Message Data 0000h RW 9A 9Fh RSVD Reserved O
139. 23 intel 2 21 8 324 Processor Configuration Registers FSTS_REG Fault Status Register This register indicates the various error status B D F Type 0 0 0 VCOPREMAP Address Offset 34 37h Reset Value 00000000h Access RW1CS ROS V RO Size 32 bits BIOS Optimal Default 00000h n Reset RST Ka Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD Fault Record Index FRI This field is valid only when the PPF field is set The FRI field indicates the index from base of the fault 15 8 ROS V 00h Powergood recording register to which the first pending fault was recorded when the PPF field was set by hardware The value read from this field is undefined when the PPF field is clear 7 RO Oh Reserved RSVD Invalidation Time out Error ITE Hardware detected a Device IOTLB invalidation completion time out At this time a fault event may be generated based on 6 RO op Gate the programming of the Fault Event Control register Hardware implementations not supporting device Device IOTLBs implement this bit as RsvdZ Invalidation Completion Error ICE Hardware received an unexpected or invalid Device IOTLB invalidation completion This could be due to either an invalid ITag or invalid source id in an invalidation completion response gt RO op Untore At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations no
140. 33 MHz reference clock This is a reversed 3 bit field 7 Up to DDR 1066 4 x 266 6 4 RO FW 000b Uncore Up to DDR 1333 5 x 266 Up to DDR 1600 6 x 266 Up to DDR 1866 7 x 266 Up to DDR 2133 8 x 266 Up to DDR 2400 9 x 266 Up to DDR 2666 10 x 266 Up to DDR 2933 11 x 266 reserved fuse value not really supported 3 RO FW Ob Reserved RSVD 2 RO FW Ob Reserved RSVD 1 RO FW Ob Reserved RSVD 0 RO FW Ob Reserved RSVD Datasheet Volume 2 85 Table 2 9 86 Processor Configuration Registers PCI Device 1 Function 0 2 Configuration Space Registers PCI Device 1 Function 0 2 Configuration Space Register Address Map Sheet 1 of 2 gooey eae Register Name Reset Value Access 0 1h VID Vendor Identification 8086h RO 2 3h DID Device Identification 0151h RO FW 4 5h PCICMD PCI Command 0000h RO RW 6 7h PCISTS PCI Status 0010h RO RWIC 8h RID Revision Identification 00h RO FW 9 Bh CC Class Code 060400h RO Ch CL Cache Line Size 00h RW Dh RSVD Reserved Oh RO Eh HDR Header Type 8ih RO F 17h RSVD Reserved Oh RO 18h PBUSN Primary Bus Number 00h RO 19h SBUSN Secondary Bus Number 00h RW 1Ah SUBUSN Subordinate Bus Number 00h RW 1Bh RSVD Reserved Oh RO 1Ch IOBASE I O Base Address FOh RW 1Dh IOLIMIT LO Limit Address 00h RW 1E 1Fh SSTS Secondary Status 0000h RW1C RO 20 21h MBASE Me
141. 3BOh 3BBh 3BCh 3BFh PCI Express Bridge or DMI PCI Express Bridge or DMI H IGD Interface IGD Interface PCI Express Bridge or DMI PCI Express Bridge or DMI 1 IGD IGD Interface Interface Additional qualification within IGD comprehends internal MDA support The VGA and MDA enabling bits detailed below control ranges not mapped to IGD Datasheet Volume 2 Processor Configuration Registers D t I H Table 2 7 For regions mapped outside of the IGD or if IGD is disabled the legacy VGA memory range AOOOOh BFFFFh are mapped either to the DMI Interface or PCI Express depending on the programming of the VGA Enable bit in the BCTRL configuration register in the PEG configuration space and the MDAPxx bits in the Legacy Access Control LAC register in Device 0 configuration space The same register controls mapping VGA I O address ranges VGA I O range is defined as addresses where A 9 0 are in the ranges 3BOh to 3BBh and 3COh to 3DFh inclusive of ISA address aliases A 15 10 are not decoded The function and interaction of these two bits is described below VGA Enable Controls the routing of processor initiated transactions targeting VGA compatible I O and memory address ranges When this bit is set the following processor accesses will be forwarded to the PCI Express e memory accesses in the range 0A0000h to OBFFFFh e I O addresses where A 9 0 are in the ranges 3B0h to 3BBh and 3COh to 3DFh including ISA address aliases
142. 46A4 46A7h Reset Value 0100B200h Access RW L Size 32 bits BIOS Optimal Default Oh Reset RST Sc Bit Access Value PWR Description tMOD The time between MRS command and any other command in 31 28 RW L Oh Uncore DELK cycles Actual value is 8 programmed Value For example when programming 4 in the field tMOD value is actually 12 DCLK cycles 27 26 RO Oh Reserved RSVD tZQOPER 25 1 RW L 100h RES This field defines the period required for ZQCL after SR exit tXS_offset 15 12 RW L Bh Uncore Delay from SR exit to the first DDR command tXS tRFC 10ns Setup of tXS_offset is of cycles for 10 ns The range is between 3 and 11 DCLK cycles tXSDLL e x Delay between DDR SR exit and the first command that requires 11 RW L 200h g SES data RD WR from DDR is in the range of 128 to 1024 DCLK cycles though all JEDEC DDRs assume 512 DCLK cycles 250 Datasheet Volume 2 Processor Configuration Registers 2 15 Table 2 18 2 15 1 intel MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub IMPH MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub IMPH Register Address Map EN Register Symbol Register Name Reset Value Access 0 740Bh RSVD Reserved 740C 740Fh CRDTCTL3 Credit Control 3 B124F851h RW L 7410 7413h CRDTCTL4 Credit Control 4 00000017h RW L 7410C 7FFFh RSVD Reserved CRDTCTL3 Credit Control 3 R
143. 6FOEN 0 Bus 0 Device 6 Function 0 is disabled and hidden 13 RW L 1b Uncore 1 Bus 0 Device 6 Function 0 is enabled and visible This bit will be set to Ob and remain Ob if PEG60 capability is disabled 12 8 RO Oh Reserved RSVD 57 58 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 54 57h Reset Value 0000209Fh Access RW L RO RW Size 32 bits BIOS Optimal Default 000000h Reset RST a Bit Access Value PWR Description Device 4 Enable D4EN 0 Bus 0 Device 4 is disabled and not visible 7 RW L 1b Uncore 1 Bus 0 Device 4 is enabled and visible This bit will be set to Ob and remain Ob if Device 4 capability is disabled 6 5 RO Oh Reserved RSVD Internal Graphics Engine D2EN 0 Bus 0 Device 2 is disabled and hidden 4 RW L 1b Uncore 1 Bus 0 Device 2 is enabled and visible This bit will be set to Ob and remain Ob if Device 2 capability is disabled PEG10 Enable D1FOEN 0 Bus 0 Device 1 Function 0 is disabled and hidden 3 RW L 1b Uncore 1 Bus 0 Device 1 Function 0 is enabled and visible This bit will be set to Ob and remain Ob if PEG10 capability is disabled PEG11 Enable D1F1iEN 0 Bus 0 Device 1 Function 1 is disabled and hidden 1 Bus 0 Device 1 Function 1 is enabled and visible S SE H wee This bit will be set to Ob and remain Ob if e PEG11 capability is disabled by fuses OR e PEG11 is disabled by strap PEGOCFGSEL PEG12 Enable
144. 8 28 RW 000h Uncore Memory space The address bits decoded depend on the length of the region defined by this register This register is locked by Intel TXT The address used to access the PCI Express configuration space for a specific device can be determined as follows PCI Express Base Address Bus Number 1MB Device Number 32 KB Function Number 4 KB This address is the beginning of the 4 KB space that contains both the PCI compatible configuration space and the PCI Express extended configuration space Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 60 67h Reset Value 0000000000000000h Access RW RW V Size 64 bits BIOS Optimal Default 000000000000h d Reset RST Pare Bit Access Value PWR Description 128 MB Base Address Mask ADMSK128 a This bit is either part of the PCI Express Base Address RW or 27 RW V Ob U ER part of the Address Mask RO read 0b depending on the value of bits 2 1 in this register 64 MB Base Address Mask ADMSK64 This bit is either part of the PCI Express Base Address RW or ER RWV gh Uncore part of the Address Mask RO read 0b depending on the value of bits 2 1 in this register 25 3 RO Oh Reserved RSVD Length LENGTH This field describes the length of this region 00 256 MB buses 0 255 Bits 38 28 are decoded in the PCI Express Base Address Field 2 1 RW 00b Uncore 01 128
145. 800 8 x 200 4 Up to DDR 2000 10 x 200 5 Up to DDR 2200 11 x 200 6 Up to DDR 2400 12 x 200 7 No limit but still limited by MAX_DDR_FREQ200 to 2600 PCIe Gen 3 Disable PEGG3_DIS PCODE will update this field with the value of FUSE_PEGG3_DIS and then apply SSKU overrides This is a defeature fuse an un programmed device should 20 RO FW Ob Uncore have PCIe Gen 3 capabilities enabled 0 Capable of running any of the Gen 3 compliant PEG controllers in Gen 3 mode Devices 0 1 0 0 1 1 0 1 2 1 Not capable of running any of the PEG controllers in Gen 3 mode 19 RO FW Ob Reserved RSVD Additive Graphics Enabled ADDGFXEN 18 RO FW Ob Uncore 0 Additive Graphics Disabled 1 Additive Graphics Enabled Additive Graphics Capable ADDGFXCAP 17 RO FW Ob Uncore 0 Capable of Additive Graphics 1 Not capable of Additive Graphics 16 RO FW Ob Reserved RSVD 15 12 RO FW Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 0 0 PCI Address Offset E8 EBh Default Value 00100000h Access RO FW RO KFW Size 32 bits BIOS Optimal Default 000000h RST Bit Access Reset Value PWR Description 11 RO FW Ob Reserved RSVD 10 8 RO FW 000b Reserved RSVD 7 RO FW Ob Reserved RSVD DDR3 Maximum Frequency Capability DMFC PCODE will update this field with the value of FUSE_DMFC and then apply SSKU overrides Maximum allowed memory frequency with 1
146. 93h RSVD Reserved 5994 5997h RP_STATE_LIMITS RP State Limitations 000000FFh RW 5998 599Bh RP_STATE_CAP RP State Capability 00000000h RO FW 599C 5C1Fh RSVD Reserved PCU_MMIO_FREQ PCU MMIO Frequency Clipping 5C20 5C23h _CLIPPING_CAUS Cause Status 00000000h RW E_STATUS PCU_MMIO_FREQ PCU MMIO Frequency Clipping 5C24 5C27h _CLIPPING_CAUS Cause Log 00000000h RW E_LOG 5C28 5DOFh RSVD Reserved 5D10 5D17h SSKPD Sticky Scratchpad Data 00000000000 RWS RW 00000h 5D18 5F03h RSVD Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 19 1 MEM_TRML_ESTIMATION_CONFIG Memory Thermal Estimation Configuration Register This register contains configuration regarding VTS temperature estimation calculations that are done by PCODE Access Size B D F Type Address Offset Reset Value 0 0 0 MCHBAR PCU 5880 5883h CA9171E7h RW 32 bits BIOS Optimal Default CA9171E7h Bit Access Reset RST Value PWR Description 31 22 21 12 RW RW VTS multiplier VTS_MULTIPLIER The VTS multiplier serves as a multiplier for the translation of the 10Eh Uncore A h e memory BW to temperature The units are given in 1 power 2 44 VTS time constant VTS_TIME_CONSTANT This factor is relevant only for BW based temperature estimation OC8h Uncore It is equal to 1 minus alpha The value of the time constant 1 alpha is determined by VTS_TIME_C
147. A 1 0 RO 00b Uncore Hardwired to 0 so that addresses assigned by system software are always aligned on a DWord address boundary 2 6 32 MD Message Data Register B D F Type 0 1 0 2 PCI Address Offset 98 99h Reset Value 0000h Access RW Size 16 bits Reset RST Pee Bit Access Value PWR Description Message Data MD Base message data pattern assigned by system software and used to handle an MSI from the device 15 0 RW 0000h Uncore When the device must generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register 2 6 33 PEG CAPL PCI Express G Capability List Register This register enumerates the PCI Express capability structure B D F Type 0 1 0 2 PCI Address Offset AO Aih Reset Value 0010h Access RO Size 16 bits Reset RST nii Bit Access Value PWR Description Pointer to Next Capability PNC This value terminates the capabilities list The Virtual Channel 15 8 RO 00h Uncore Capability and any other PCI Express specific capabilities that are reported using this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space Capability ID CID 7 0 RO 10h Uncore This field identifies this linked list item capability structure as being for PCI Express registers
148. AR 2 Addresses decoded to the memory mapped window to DMI VC1 VT remap engine registers DMIVC1BAR 3 Addresses decoded to the memory mapped window to PEG DMI VCO VT remap engine registers VTIDPVCOBAR 4 TCm accesses to Intel ME stolen memory from PCH do not go through VT remap engines Some of the MMIO Bars may be mapped to this range or to the range above TOUUD There are sub ranges within the PCI Memory address range defined as APIC Configuration Space MSI Interrupt Space and High BIOS Address Range The exceptions listed above for internal graphics and the PCI Express ports Must Not overlap with these ranges Datasheet Volume 2 25 intel Figure 2 4 PCI Memory Address Range 2 3 3 1 26 Processor Configuration Registers FFFF_FFFFh l 4 GB High BIOS FFE0_0000h 4 GB 2 MB DMI Interface subtractive decode FEF0_0000h 4 GB 17 MB MSI Interrupts FEE0_0000h 4 GB 18 MB DMI Interface subtractive decode FED0_0000h teg ee Local CPU APIC FEC8_0000h UO APIC FECO_0000h 4 GB 20 MB DMI Interface subtractive decode F000_0000h gt 4 GB 256 MB Possible PCI Express Configuration address range Space size not ensured E000_0000h 4 GB 512 MB BARS Internal Graphics DMI Interface ranges PCI subtractive decode Express Port CHAPADR could be here TOLUD APIC Configuration Space FECO0_0000h FECF_FFFFh This range is reserved for AP
149. Attribute Map 1 Register This register controls the read write and shadowing attributes of the BIOS range from C_0000h to C_7FFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 81h Reset Value 00h Access RW Size 8 bits BIOS Optimal Default Oh e Reset RST RS Bit Access Value PWR Description 7 6 RO Oh Reserved RSVD 0C4000 0C7FFF Attribute HIENABLE This field controls the steerin
150. B D F Type 0 0 0 GFXVTBAR Address Offset FFO FF3h Reset Value 00000000h Access RW L RO RO KFW RW KL Size 32 bits BIOS Optimal Default 0000h Bit Access PEE vlt Description DMA Remap Engine Policy Lock Down DMAR_LCKDN This register bit protects all the DMA remap engine specific policy 31 RW KL Ob Uncore configuration registers Once this bit is set by software all the DMA remap engine registers within the range FOOh to FFCh will be read only This bit can only be clear through platform reset 30 0 RO Oh Reserved RSVD Datasheet Volume 2 295 intel 2 19 PCU MCHBAR Registers Table 2 22 PCU MCHBAR Register Address Map 296 Processor Configuration Registers Ke Register Symbol Register Name Reset Value Access 0 587Fh RSVD Reserved E MEM_TRML_ESTI Memory Thermal Estimation 5880 5883h MATION CONFIG Configuration CA3171E7h RW 5884 5887h RSVD Reserved 00000000h RW x MEM_TRML_THRE Memory Thermal Thresholds 5888 588Bh SHOLDS_CONFIG Configuration O0E4DADOR RW 588C 589Fh RSVD Reserved MEM_TRML_STAT Memory Thermal Status Report E 58A0 58A3h US_REPORT 00000000h RO V MEM_TRML_TEMP Memory Thermal Temperature j 58A4 58A7h ERATURE_REPORT Report 00000000h RO V 58A8 58ABh HERR Memory Thermal Interrupt 00000000h RW 58AC 5947h RSVD Reserved 5948 594Bh GT_PERF_STATUS GT Performance Status 00000000h RO V 594C 59
151. BAR TMBAR 64 bit BAR PMBASE PMLIMIT 64 bit BAR using Upper PMBASE PMLIMIT CHAPADR 64 bit BAR GFXVTBAR 39 bit BARS VTDPVCOBAR 39 bit BARS Implementation Notes e Remap applies to transactions from all interfaces All upstream PEG DMI transactions that are snooped get remapped e Upstream PEG DMI transactions that are not snooped Snoop not required attribute set get remapped e Upstream reads and writes above TOUUD are treated as invalid cycles e Remapped addresses remap starting at TOLUD They do not remap starting at TSEG_BASE DMI and PEG need to be careful with this for both snoop and non snoop accesses In other words for upstream accesses the range between TOLUD GfxStolensize GFXGTTstolensize TSEGSIZE DPR to TOLUD will never map directly to memory Accesses from PEG DMI should be decoded as to the type of access before they are remapped For instance a DMI write to FEEx_xxxxh is an interrupt transaction but there is a DMI address that will be re mapped to the DRAM address of FEEx_xxxxh In all cases the remapping of the address is done only after all other decodes have taken place Unmapped addresses between TOLUD and 4 GB Accesses that don t hit DRAM or PCI space are subtractive decoded to DMI Because the TOLUD register is used to mark the upper limit of DRAM space below the 4 GB boundary no address between TOLUD and 4 GB ever decodes directly to main memory Thus even if remap is disabled any ad
152. BAR decode Cycle to memory from processor AND Device 2 IGD is enabled AND Memory accesses for Device 2 is enabled AND Targets graphics MMIO Function 0 AND MCHBAR is enabled or cycle is a read If MCHBAR is disabled only read access is allowed e MCHTMBAR gt MCHBAR Thermal Monitor Cycle to memory from processor AND AND Targets MCHTMBAR base e IOBAR gt GTTMMADR gt MCHBAR Follows IOBAR rules See GTTMMADR information above as well Memory Remapping An incoming address referred to as a logical address is checked to see if it falls in the memory re map window The bottom of the re map window is defined by the value in the REMAPBASE register The top of the re map window is defined by the value in the REMAPLIMIT register An address that falls within this window is remapped to the physical memory starting at the address defined by the TOLUD register The TOLUD register must be 1M aligned Hardware Remap Algorithm The following pseudo code defines the algorithm used to calculate the DRAM address to be used for a logical address above the top of physical memory made available using re claiming IF ADDRESS_IN 38 20 gt REMAP_BASE 35 20 AND ADDRESS_IN 38 20 lt REMAP_LIMIT 35 20 THEN ADDRESS_OUT 38 20 ADDRESS_IN 38 20 REMAP_BASE 35 20 0000000b amp TOLUD 31 20 ADDRESS_OUT 19 0 ADDRESS_IN 19 0 Datasheet Volume 2 29 intel Processor Configuration Registers 2 3 4 5 P
153. BIOS Optimal Default 00000h e Reset RST E Bit Access Value PWR Description Protected Low Memory Base PLMB 31 20 RW 000h Uncore This field specifies the base of protected low memory region in system memory 19 0 RO Oh Reserved RSVD Datasheet Volume 2 281 DN t l Processor Configuration Registers 2 18 16 282 PLMLIMIT_REG Protected Low Memory Limit Register This register sets up the limit address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region limit depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position with O in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all is The Protected low memory base and limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits 31 N 1 specifies a protected low memory region of size 2 N 1 bytes e Programming the protected low memory limit register with a value less than the protected low
154. BIOS Optimal Default o000h S Reset RST ae Bit Access Value PWR Description Supported Adjusted Guest Address Widths SAGAW This 5 bit field indicates the supported adjusted guest address widths which in turn represents the levels of page table walks for the 4 KB base page size supported by the hardware implementation A value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported The adjusted guest address widths corresponding to various bit positions within this 12 8 RO 00010b Uncore field are 0 30 bit AGAW 2 level page table 1 39 bit AGAW 3 level page table 2 48 bit AGAW 4 level page table 3 57 bit AGAW 5 level page table 4 64 bit AGAW 6 level page table Software must ensure that the adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field Caching Mode CM 0 Not present and erroneous entries are not cached in any of the remapping caches Invalidations are not required for modifications to individual not present or invalid entries However any modifications that result in decreasing the effective permissions or partial permission increases require 7 RO Ob Uncore invalidations for them to be effective 1 Not present and erroneous mappings may be cached in the remapping caches Any software updates to the remapping structures including updates to not present or e
155. CI compliant master abort and PCI compliant target abort PCISTS also indicates the DEVSEL timing that has been set by the IGD B D F Type 0 2 0 PCI Address Offset 6 7h Reset Value 0090h Access RO RO V Size 16 bits BIOS Optimal Default Oh t Reset RST nns Bit Access Value PWR Description Detected Parity Error DPE 15 RO Ob Uncore Since the IGD does not detect parity this bit is always hardwired to 0 Signaled System Error SSE 14 RO Ob Uncore The IGD never asserts SERR therefore this bit is hardwired to 0 Received Master Abort Status RMAS 13 RO Ob Uncore The IGD never gets a Master Abort therefore this bit is hardwired to 0 Received Target Abort Status RTAS 12 RO Ob Uncore The IGD never gets a Target Abort therefore this bit is hardwired to 0 Signaled Target Abort Status STAS 11 RO b o encore Hardwired to 0 The IGD does not use target abort semantics DEVSEL Timing DEVT 10 3 S SP Ungare N A These bits are hardwired to 00 Master Data Parity Error Detected DPD 8 RO Ob Uncore Since Parity Error Response is hardwired to disabled and the IGD does not do any parity detection this bit is hardwired to 0 Fast Back to Back FB2B 7 RO 1b Uncore Hardwired to 1 The IGD accepts fast back to back when the transactions are not to the same agent User Defined Format UDF RO 0b RES Hardwired to 0 66 MHz PCI Capable C66
156. D 22 RO 1b Uncore ASPM Optionality Compliance AOC This bit must be set to 1b in all Functions Components implemented against certain earlier versions of this specification will have this bit set to Ob Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests 21 RO 1b Uncore Link Bandwidth Notification Capability LBNC A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms This capability is required for all Root Ports and Switch downstream ports supporting Links wider than x1 and or multiple Link speeds This field is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob 20 RO Ob Uncore Data Link Layer Link Active Reporting Capable DLLLARC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine For a hot plug capable Downstream Port as indicated by the Hot Plug Capable field of the Slot Capabilities register this bit must be set to 1b For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob Note PCI Express Hot
157. DMA remapping fault conditions bits 63 12 of this field contain the page address in the faulted DMA request Hardware treats bits 63 N as reserved 0 where N is the maximum guest address 63 12 ROS Vv 09090000 Powergood width MGAW supported When the Fault Reason FR field indicates one of the interrupt remapping fault conditions bits 63 48 of this field indicate the interrupt_index computed for the faulted interrupt request and bits 47 12 are cleared This field is relevant only when the F field is set 11 0 RO Oh Reserved RSVD Datasheet Volume 2 293 intel 2 18 31 294 Processor Configuration Registers FRCDH_REG Fault Recording High Register This register records fault information when primary fault logging is active Hardware reports the number and location of fault recording registers through the Capability register This register is relevant only for primary fault logging This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1 B D F Type 0 0 0 GFXVTBAR Address Offset 208 20Fh Reset Value 0000000000000000h Access RO RW1CS ROS V Size 64 bits BIOS Optimal Default 0000000000000000h S Reset RST SL Bit Access Value PWR Description Fault F Hardware sets this field to indicate a fault is logged in this Fault Recording register The F field is set by hardware after 63 RW1CS
158. DO_INTx messages will not be sent to DMI Fast Back to Back FB2B 3 RO ob STEE Not Implemented Hardwired to 0 SERR Enable SERRE S RO up SE Not Implemented Hardwired to 0 Address Data Stepping Enable ADSTEP 7 RO 0 U p eege Not Implemented Hardwired to 0 Parity Error Enable PERRE Not Implemented Hardwired to 0 Since the IGD belongs to the 6 RO Ob Uncore category of devices that does not corrupt programs or data in system memory or hard drives the IGD ignores any parity error that it detects and continues with normal operation Video Palette Snooping VPS RO 0 U gt b DSRS This bit is hardwired to 0 to disable snooping Memory Write and Invalidate Enable MWIE 4 RO Ob Uncore Hardwired to 0 The IGD does not support memory write and invalidate commands Special Cycle Enable SCE 3 RO Ob U abi This bit is hardwired to 0 The IGD ignores Special cycles Bus Master Enable BME 2 RW Ob Gente 0 Disable IGD bus mastering 1 Enable the IGD to function as a PCI compliant master Memory Access Enable MAE 1 RW Ob FLR This bit controls the IGD s response to memory space accesses Uncore 0 Disable 1 Enable I O Access Enable IOAE 0 RW Ob FLR This bit controls the IGD s response to I O space accesses Uncore 0 Disable 1 Enable Datasheet Volume 2 Processor Configuration Registers intel 2 8 4 PCISTS2 PCI Status Register PCISTS is a 16 bit status register that reports the occurrence of a P
159. Datasheet Volume 2 Processor Configuration Registers Size B D F Type Address Offset Reset Value Access BIOS Optimal Default 0 0 0 VCOPREMAP 28 2Fh 0000000000000000h RW V RW RO V 64 bits 000000000h Bit Access Reset Value RST PWR Description 60 59 RO V Oh Uncore Context Actual Invalidation Granularity CAIG Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion by clearing the ICC field The following are the encodings for this field 00 Reserved 01 Global Invalidation performed This could be in response to a global domain selective or device selective invalidation request 10 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or device selective invalidation request 11 Device selective invalidation performed using the source id and domain id specified by software in the SID and FM fields This can only be in response to a device selective invalidation request 58 34 RO Oh Reserved RSVD 33 32 RW Oh Uncore Function Mask FM Software may use the Function Mask to perform device selective invalidations on behalf of devices supporting PCI Express Phantom Functions This field specifies which bits of the function number portion le
160. Datasheet Volume 2 207 intel Processor Configuration Registers 2 11 6 VCORSTS VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 6 0 MMR Address Offset 11A 11Bh Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h e Reset RST ear Bit Access Value PWR Description 15 2 RO Oh Reserved RSVD VCO Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control 1 RO V ib Uncore initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Oh Reserved RSVD 2 11 7 RCLDECH Root Complex Link Declaration Enhanced This capability declares links from this element PEG to other elements of the root complex component to which it belongs See PCI Express specification for link topology declaration requirements B D F Type 0 6 0 MMR Address Offset 140 143h Reset Value 00010005h Access RO V RO Size 32 bits z Reset RST aa Bit A
161. Default 0000h o Reset RST Ge Bit Access Value PWR Description 31 18 RO Oh Reserved RSVD PME Pending PMEP This bit indicates that another PME is pending when the PME Status bit is set When the PME Status bit is cleared by software 17 RO 0 b SE the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately The PME pending bit is cleared by hardware if no more PMEs are pending PME Status PMES This bit indicates that PME was asserted by the requestor ID indicated in the PME Requestor ID field Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field An interrupt is asserted if PMEIE is asserted and PMES is changing from 0 to 1 An interrupt is deasserted if PMEIE is asserted and PMES is 16 RWI1C Ob Uncore changing from 1 to 0 An Assert_PMEGPE is sent upstream if PMEGPEE in PEG Legacy Control register PEGLC is asserted and PMES is changing from 0 to 1 A Deassert_PMEGPE is sent upstream if PMEGPEE in PEG Legacy Control register PEGLC is asserted and PMES is changing from 1 to 0 An interrupt is deasserted if PMEIE is asserted and PMES is changing from 1 to 0 PME Requestor ID PMERID 15 0 RO V 0000h Uncore This field indicates the PCI requestor ID of the last PME requestor 126 Datasheet Volume 2 Processor Configuration Registers D 2 6 46 DCAP2 Device Capabilities 2 Regist
162. Defined encodings are 0001b 2 5 GT s Link speed supported 0010b 5 0 GT s and 2 5 GT s Link speeds supported 2 12 25 LCTL Link Control Register This register allows control of PCI Express link 234 B D F Type 0 0 0 DMIBAR Address Offset 88 89h Reset Value 0000h Access RW RW V Size 16 bits BIOS Optimal Default 0000h 5 Reset RST Se Bit Access Value PWR Description 15 10 RO Oh Reserved RSVD Hardware Autonomous Width Disable HAWD When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link 3 RW ab Uncore operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob 8 RO Oh Reserved RSVD Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state 7 RW Ob Uncore This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns 6 RO Oh Reserved RSVD Retrain Link RL 0 Normal operation o 1 Full Link retraining is initiated by directing the Physical Layer 5 RW V Ob U de LTSSM
163. Description Device Identification Number MSB DID_MSB 15 0 RO FW 015Dh Uncore Identifier assigned to the processor root port virtual PCI to PCI bridge PCI Express Graphics port 2 10 3 PCICMD PCI Command Register B D F Type 0 6 0 PCI Address Offset 4 5h Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 00h Reset RST Bit Access Value PWR Description 15 11 RO Oh Reserved RSVD INTA Assertion Disable INTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt messages Any INTA emulation interrupts already asserted 10 RW 0b Uncore must be de asserted when this bit is set Only affects interrupts generated by the device PCI INTA from a PME or Hot plug event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and deassert messages Note PCI Express Hot Plug is not supported on the processor Fast Back to Back Enable FB2B 9 R b o 2 Uncore Not Applicable or Implemented Hardwired to 0 Datasheet Volume 2 163 164 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 6 0 PCI 4 5h 0000h RW RO 16 bits BIOS Optimal Default 00h Bit Access Reset RST Value PWR Description RW Ob Uncore SERR Message Enable SERRE This bit cont
164. Device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is 1 Both received if enabled by BCTRLi 1 and internally detected error messages do not affect this field 13 RO Ob Uncore Received Master Abort Status RMAS This bit is set when a Requester receives a Completion with Unsupported Request Completion Status On a Function with a Type 1 Configuration header the bit is set when the Unsupported Request is received by its Primary Side Not applicable UR not on primary interface 90 Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 1 0 2 PCI Address Offset 6 7h Reset Value 0010h Access RO RW1C RO V Size 16 bits BIOS Optimal Default Oh Reset RST Bit Access Value PWR Description Received Target Abort Status RTAS This bit is set when a Requester receives a Completion with Completer Abort Completion Status On a Function with a Type 1 Configuration header the bit is set when the Completer Abort is received by its Primary Side Reset Value of this bit is Ob Not Applicable or Implemented Hardwired to 0 The concept of a Completer abort does not exist on primary side of this device 12 RO Ob Uncore Signaled Target Abort Status STAS This bit is set when a Function completes a Posted or Non Posted Request as a Completer Abort error This applies to a Function
165. E PCICMD10 1 is set VGA and MDA I O cycles can only be routed across PEG10 if IOAE PCICMD10 0 is set Datasheet Volume 2 75 intel 2 5 29 Processor Configuration Registers REMAPBASE Remap Base Address Register B D F Type 0 0 0 PCI Address Offset 90 97h Reset Value OOOOOOOFFFFOOOOOh Access RW L RW KL Size 64 bits BIOS Optimal Default 000000000000h o Reset RST ae Bit Access Value PWR Description 63 36 RO Oh Reserved RSVD Remap Base Address REMAPBASE The value in this register defines the lower boundary of the Remap window The Remap window is inclusive of this address In the decoder A 19 0 of the Remap Base Address are assumed to be Os Thus the bottom of the defined memory range will be 35 20 RW L FFFFh Uncore aligned to a 1 MB boundary When the value in this register is greater than the value programmed into the Remap Limit register the Remap window is disabled These bits are Intel TXT lockable 19 1 RO Oh Reserved RSVD Lock LOCK 0 RW KL Ob Uncore This bit will lock all writeable settings in this register including itself 76 Datasheet Volume 2 Processor Configuration Registers 2 5 30 REMAPLIMIT Remap Limit Address Register B D F Type 0 0 0 PCI Address Offset 98 9Fh Reset Value 0000000000000000h Access RW L RW KL Size 64 bits BIOS Optimal Default 000000000000h s Reset RST Ge Bit Access Valu
166. ENEE ENEN NR ER NENNEN ENNEN E EN NNN 251 MCHBAR Registers in Memory Controller Common Register Address Map 253 Memory Controller MMIO Registers Broadcast Group Register Address Map 257 Integrated Graphics VTd Remapping Engine Register Address Map 260 PCU MCHBAR Register Address Map cccccceceeceeeeeeneeeseeeeeeeaeeseeneeaeeeaeeaeaennaeeenaeenee 296 PXPEPBAR AddreSS Mat 3 gege eRe nia den sblaladin de ace apdes ANE Sage 308 Default PEG DMI VTd Remapping Engine Register Address Map 309 Datasheet Volume 2 Revision History Datasheet Volume 2 Revision Sot Revision Number Description Date 001 Initial release April 2012 e Updated Section 2 6 to reflect support for Functions 0 2 002 e Updated Section 2 7 to relfect support for Functions 0 2 June 2012 11 12 Datasheet Volume 2 Introduction Note Note Note Note intel Introduction This is Volume 2 of the Datasheet for the following products e Mobile 3rd Generation Intel Core processor family The processor contains one or more PCI devices within a single physical component The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket This document describes the configuration space registers or device specific control and status registers CSRs only This document does NOT include Model Specific Registers MSRs Throughout this d
167. FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 6 0 PCI Address Offset 26 27h Reset Value 0001h Access RW RO Size 16 bits Bit Access d re cae Description Prefetchable Memory Address Limit PMLIMIT 15 4 RW 000h Uncore This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 64 bit Address Support AS64B e This field indicates that the upper 32 bits of the prefetchable RO th SH vneare memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch Datasheet Volume 2 175 DN t Processor Configuration Registers 2 10 19 176 PMBASEU Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write a
168. Fh IEUADDR_REG Validation Event Upper Address 00000000h RW L Register BO B7h RSVD Reserved Oh RO B8 BFh IRTA_REG Interrupt Remapping Table Address 0000000000000 RW L Register 000h CO FFh RSVD Reserved Oh RO 100 107h IVA_REG Invalidate Address Register 0000000000000 RW 108 10Fh IOTLB_REG IOTLB Invalidate Register 0000900000000 RW RW V RO V 110 FF3h RSVD Reserved 2 21 1 VER_REG Version Register This register reports the architecture version supported Backward compatibility for the architecture is maintained with new revision numbers allowing software to load remapping hardware drivers written for prior architecture versions B D F Type 0 0 0 VCOPREMAP Address Offset 0 3h Reset Value 00000010h Access RO Size 32 bits BIOS Optimal Default 000000h 5 Reset RST Ge Bit Access Value PWR Description 31 8 RO Oh Reserved RSVD Major Version number MAX ws RO SEH uncore This field indicates supported architecture version Minor Version number MIN ae RO ogee ER This bit indicates supported architecture minor version 310 Datasheet Volume 2 Processor Configuration Registers D 2 21 2 CAP_REG Capability Register This register reports general remapping hardware capabilities B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9008020660262h Access RO Size 64 bits BIOS Optimal Default 000h Reset RST SCH Bit Access Value
169. GFX GTT Stolen BASE 0 2 MB 1 MB aligned TSEG TSEG 0 8 MB TSEC BALE 1 MB aligned Main Memory OS Add Range VISIBLE lt 4GB 1MB Legacy 0 Add Range 0 In this case the amount of memory remapped is the range between TOLUD and 4 GB This physical memory will be mapped to the logical address range defined between the REMAPBASE and the REMAPLIMIT registers 32 Datasheet Volume 2 Processor Configuration Registers Example 5 GB of Physical Memory with 1 GB allocated to Memory Mapped IO e Populated Physical Memory 5 GB e Address Space allocated to memory mapped IO including Flash APIC and Intel TXT 1 GB e Remapped Physical Memory 1 GB e TOM 01_4000_0000h 5 GB e ME stolen size 00000b 0 MB e TOUUD 01_8000_0000h 6 GB 1 MB aligned e TOLUD 00_C000_000h 3 GB e REMAPBASE 01_4000_0000h 5 GB e REMAPLIMIT 01_7FFO_O000h 6 GB 1 The Remap window is inclusive of the Base and Limit addresses In the decoder A 19 0 of the Remap Base Address are assumed to be Os Similarly A 19 0 of the Remap Limit Address are assumed to be Fs Thus the bottom of the defined memory range will be aligned to a MB boundary and the top of the defined range will be one less than a MB boundary Setting the Remap Base register to a value greater than that programmed into the Remap Limit register disables the remap function Software Responsibility and Restrictions e BIOS is responsible for prog
170. GRO6 Register bits 3 2 See Table 2 5 for translations IGD Frame Buffer Accesses Mem Access gt BOOOOh B7FFFh GRO6 3 2 AOOOOh AFFFFh MDA B8000h BFFFFh 00 IGD IGD IGD ou IGD PCI Express Bridge or DMI PCI Express Bridge or DMI Interface Interface 10 PCI Express Bridge or DMI IGD PCI Express Bridge or DMI Interface Interface 11 PCI Express Bridge or DMI PCI Express Bridge or DMI IGD Interface Interface Additional qualification within IGD comprehends internal MDA support The VGA and MDA enabling bits detailed below control segments not mapped to IGD VGA I O range is defined as addresses where A 15 0 are in the ranges 03B0h to 03BBh and 03COh to 03DFh VGA I O accesses directed to IGD depends on the following configuration e Internal Graphics Controller in Device 2 is enabled through register DEVEN D2EN bit 4 e Internal Graphics VGA in Device 0 function 0 is enabled through register GGC bit 1 e IGD I O accesses PCICMD2 04 05h IOAE bit 0 in Device 2 are enabled e VGA I O decodes for IGD uses 16 address bits 15 0 there is no aliasing This is different when compared to a bridge device Device 1 that used only 10 address bits A 9 0 for VGA I O decode e VGA I O input output address select VGA Miscellaneous output Register MSR Register bit 0 used to select mapping of I O access as defined in Table 2 6 IGD VGA I O Mapping I O Access gt MSRbO 3CXh 3DXh
171. I Express Hardwired to 0 VGA 16 bit Decode VGA16D Enables the PCI to PCI bridge to provide 16 bit decoding of VGA I O address precluding the decoding of alias addresses every 4 RW op Uncons 1 KB This bit only has meaning if bit 3 VGA Enable of this register is also set to 1 enabling VGA I O decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA I O accesses 1 Execute 16 bit address decodes on VGA I O accesses VGA Enable VGAEN This bit controls the routing of processor initiated transactions 3 RW Ob viele targeting VGA compatible I O and memory address ranges See the VGAEN MDAP table in Device 0 offset 97h 0 Datasheet Volume 2 103 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh Reset RST itas Bit Access Value PWR Description ISA Enable ISAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the root port to an I O access issued by the processor that target ISA I O addresses This applies only to I O addresses that are enabled by the IOBASE and IOLIMIT registers 2 RW ae Ss 0 All addresses defined by the IOBASE and IOLIMIT for processor I O transactions will be mapped to PCI Express G 1 The root port will not forward to PCI Express G any I O transactions address
172. IC configuration space The I O APIC s usually reside in the PCH portion of the chipset but may also exist as stand alone components like PXH The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system Since it is difficult to relocate an interrupt controller using plug and play software fixed address decode regions have been allocated for them Processor accesses to the default IOAPIC region FECO_O000h to FEC7_FFFFh are always forwarded to DMI The processor optionally supports additional I O APICs behind the PCI Express Graphics port When enabled using the APIC_BASE and APIC_LIMIT registers mapped PCI Express Configuration space offset 240h and 244h the PCI Express port s will positively decode a subset of the APIC configuration space Datasheet Volume 2 Processor Configuration Registers 2 3 3 2 2 3 3 3 2 3 3 4 2 3 4 Memory requests to this range would then be forwarded to the PCI Express port This mode is intended for the entry Workstation Server SKU of the MCH and would be disabled in typical Desktop systems When disabled any access within entire APIC Configuration space FECO_O000h to FECF_FFFFh is forwarded to DMI HSEG FEDA_0000h FEDB_FFFFh This decode range is not supported on the processor platform MSI Interrupt Memory Space FEE0_0000 FEEF_FFFF Any PCI Express or DMI device may issue a Memory Write to OFEEx_xxxxh This Memory Write
173. Interleave mode Enh_Interleave 22 RW L 1b Uncore 0 off 1 on Rank Interleave RI 21 RW L 1b Uncore 0 off 1 on DIMM B DDR width DBW 20 RW L Ob Uncore 0 X8 chips 1 X16 chips DIMM A DDR width DAW 19 RW L Ob Uncore 0 X8 chips 1 X16 chips DIMM B number of ranks DBNOR 18 RW L Ob Uncore 0 single rank 1 dual rank DIMM A number of ranks DANOR 17 RW L Ob Uncore 0 single rank 1 dual rank DIMM A select DAS Selects which of the DIMMs is DIMM A should be the larger 16 RW L Ob Uncore DIMM 0 DIMM O 1 DIMM 1 Size of DIMM B DIMM_B_Size 15 8 SN SEN Uncore Size of DIMM B in 256 MB multiples 7 0 RW L 00h ancora Size of DIMM A DIMM_A_Size Size of DIMM A in 256 MB multiples 254 Datasheet Volume 2 Processor Configuration Registers intel 2 16 3 MAD_DIMM_chi Address Decode Channel 1 Register This register defines channel characteristics number of DIMMs number of ranks size interleave options B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5008 500Bh Reset Value 00600000h Access RW L Size 32 bits BIOS Optimal Default 00h Reset RST adig Bit Access Value PWR Description 31 26 RO Oh Reserved RSVD 25 24 RO 00b Reserved RSVD 23 RO Oh Reserved RSVD Enhanced Interleave mode Enh_Interleave 22 RW L 1b Uncore 0 off 1 on Rank Interleave RI 21 RW L 1b Uncore 0 off 1
174. Interrupt Remap Table Pointer operation software must globally invalidate the interrupt entry cache This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer and not any stale cached entries While interrupt remapping is active software may update the interrupt remapping table pointer through this field However to ensure valid in flight interrupt requests are deterministically remapped software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer Clearing this bit has no effect The value returned on a read of this field is undefined 23 0 RO Oh Reserved RSVD Datasheet Volume 2 319 intel 2 21 5 320 Processor Configuration Registers GSTS_REG Global Status Register This register reports general remapping hardware status Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 VCOPREMAP 1C 1Fh 00000000h RO RO V 32 bits 000000h Bit Access Reset Value RST PWR Description 31 RO V Ob Uncore Translation Enable Status TES This field indicates the status of DMA remapping hardware 0 DMA remapping hardware is not enabled 1 DMA remapping hardware is enabled 30 R
175. L S Invalidation Queue Address Register 0000000000 s 90 97h IQA_REG 000000h RW L 98 9Bh RSVD Reserved Oh RO 9C 9Fh ICS_REG Invalidation Completion Status 00000000h RW1CS Register AO A3h IECTL_REG Invalidation Event Control Register 80000000h RW L RO V A4 A7h IEDATA_REG Invalidation Event Data Register 00000000h RW L A8 ABh IEADDR_REG Invalidation Event Address Register 00000000h RW L 260 Datasheet Volume 2 Processor Configuration Registers Table 2 21 2 18 1 intel Integrated Graphics VTd Remapping Engine Register Address Map Sheet 2 of 2 Address Register Symbol Register Name Reset Value Access Offset g LA g AC AFh IEUADDR_REG VE E Event Upper Address 00000000h RW L Register BO B7h RSVD Reserved Oh RO S Interrupt Remapping Table Address 000000000 z B8 BFh IRTA_REG Register 0000000h RW L CO FFh RSVD Reserved Oh RO Invalidate Address Register 000000000 100 107h IVA_REG 0000000h RW Z IOTLB Invalidate Register 020000000 RO V RW 108 10Fh IOTLB_REG 0000000h RW V 110 1FFh RSVD Reserved Oh RO Fault Recording Low Register 000000000 E 200 207h FRCDL_REG 0000000h ROS V 2 Fault Recording High Register 0000000000 RO RW1CS 208 20Fh FRCDH_REG 000000h ROS V 210 FEFh RSVD Reserved Oh RO DMA Remap Engine Policy Control RW L RO RO FFO FF3h VTPOLICY 00000000h KFW RW KL VER_REG Version Register This register reports the architecture version supported
176. Link 3 Software must ensure that no traffic is using a Virtual Channel at the time it is disabled 4 Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO Oh Reserved RSVD Virtual Channel 1 ID VC1ID e Assigns a VC ID to the VC resource Assigned value must be non 26 24 RW oe SS zero This field cannot be modified when the VC is already enabled 23 20 RO Oh Reserved RSVD Port Arbitration Select PAS Configures the VC resource to provide a particular Port 19 17 RW 000b Uncore Arbitration service Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 8 RO Oh Reserved RSVD 7 RO Ob Uncore Traffic Class m Virtual Channel 1 TCMVC1M Traffic Class Virtual Channel 1 Map TCVC1M This indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 6 is set in this field TC6 is mapped to this VC resource When more than one bit in this field is set it 6 1 RW 00h Uncore indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link BIOS Requirement Program this field with
177. M If a hole is created the processor will route the request to DMI since the request does not target DRAM Graphics translated requests to the range will always route to DRAM 22 Datasheet Volume 2 Processor Configuration Registers D t I H 2 3 2 2 TSEG For processor initiated transactions the processor relies on correct programming of SMM Range Registers SMRR to enforce TSEG protection TSEG is below IGD stolen memory which is at the Top of Low Usable physical memory TOLUD BIOS will calculate and program the TSEG BASE in Device 0 TSEGMB used to protect this region from DMA access Calculation is TSEGMB TOLUD DSM SIZE GSM SIZE TSEG SIZE SMM mode processor accesses to enabled TSEG access the physical DRAM at the same address When the extended SMRAM space is enabled processor accesses to the TSEG range without SMM attribute or without WB attribute are handled by the processor as invalid accesses Non processor originated accesses are not allowed to SMM space PCI Express DMI and Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle type with reads and writes to location C_O000h and byte enables turned off for writes 2 3 2 3 Protected Memory Range PMR programmable For robust and secure launch of the MVMM the MVMM code and private data needs to be loaded to a memory region protected from bus master accesses Support for the protected memory region is required fo
178. MIT I O Limit Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type 0 6 0 PCI Address Offset 1Dh Reset Value 00h Access RW Size 8 bits BIOS Optimal Default Oh Reset RST Bit Access Value PWR Description I O Address Limit IOLIMIT e This field corresponds to A 15 12 of the I O address limit of the 7 4 RW Oh mars root port Devices between this upper limit and IOBASE1 will be passed to the PCI Express hierarchy associated with this device 3 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers intel 2 10 14 SSTS Secondary Status Register SSTS is a 16 bit status register that reports the occurrence of error conditions associated with secondary side that is PCI Express G side of the virtual PCI PCI bridge embedded within the processor Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 6 0 PCI 1E 1Fh 0000h RW1C RO 16 bits 00h Bit 15 14 Access RW1C RW1C Reset RST Value PWR Ob Ob Uncore Uncore Description Detected Parity Error DPE
179. MSI will be generated when we receive PME messages INTA will not be generated and INTA Status PCISTS1 3 will not be set Uncore 2 10 31 MA Message Address Register 186 B D F Type 0 6 0 PCI Address Offset 94 97h Reset Value 00000000h Access RW RO Size 32 bits n Reset RST SE Bit Access Value PWR Description Message Address MA a Used by system software to assign an MSI address to the device ote om 00090000N Uncore The device handles an MSI by writing the padded contents of the MD register to this address Force DWord Align FDWA 1 0 RO 00b Uncore Hardwired to 0 so that addresses assigned by system software are always aligned on a DWord address boundary Datasheet Volume 2 Processor Configuration Registers 2 10 32 MD Message Data Register B D F Type 0 6 0 PCI Address Offset 98 99h Reset Value 0000h Access RW Size 16 bits n Reset RST PE Bit Access Value PWR Description Message Data MD Base message data pattern assigned by system software and used to handle an MSI from the device 15 0 RW 0000h Uncore When the device must generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register 2 10 33 PEG_CAPL PCI Express G Capability List Register This register enumerates the PCI Express capability
180. Memory Mask MEMASK This field indicates the bits that must match MEBASE in order to qualify as an Intel MEMemory Range access For example if the field is set to 7FFFFh then Intel MEMemory is 38 20 RW L 00000h Uncore 1 MB in size Another example is that if the field is set to 7FFFEh then Intel MEMemory is 2 MB in size In other words the size of Intel MEMemory Range is limited to power of 2 times 1 MB 19 12 RO Oh Reserved RSVD ME Stolen Memory Enable ME_STLEN_EN 11 RW L Ob Uncore Indicates whether the Intel ME stolen Memory range is enabled or not ME Range Lock MELCK This field indicates whether all bits in the MESEG_BASE and 10 RW KL 0 b SES MESEG_MASK registers are locked When locked updates to any field for these registers must be dropped 9 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers 2 5 21 intel PAMO Programmable Attribute Map 0 Register This register controls the read write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These at
181. Mobile 3rd Generation Intel Core Processor Family Datasheet Volume 2 of 2 June 2012 Document Number 326769 002 intel INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY
182. NE Interrupt Line Register This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information B D F Type 0 6 0 PCI Address Offset 3Ch Reset Value 00h Access RW Size 8 bits Reset RST BS Bit Access Value PWR Description Interrupt Connection INTCON This field is used to communicate interrupt line routing information 7 0 RW 00h Uncore BIOS Requirement POST software writes the routing information into this register as it initializes and configures the system The value indicates to which input of the system interrupt controller this device s interrupt pin is connected 178 Datasheet Volume 2 Processor Configuration Registers D 2 10 23 INTRPIN Interrupt Pin Register This register specifies which interrupt pin this device uses B D F Type 0 6 0 PCI Address Offset 3Dh Reset Value Oih Access RW O RO Size 8 bits a Reset RST Se Bit Access Value PWR Description 7 3 RO 00h Uncore Reserved RSVD Interrupt Pin INTPIN As a multifunction device the PCI Express device may specify any INTx x A B C D as its interrupt pin The Interrupt Pin register tells which interrupt pin the device or device function uses A value of 1 corresponds to INTA Default A value of 2 corresponds to INTB 2 RW O ih 0 Uncore A value of 3 corresponds
183. NNEN ENNEN ER NENNEN 24 2 3 2 6 Graphics Stolen Spaces E ef eg cath mi EAR Caden dats bear vee uni 24 2 3 2 7 Intel Management Engine Intel ME UMA ees 25 2 3 3 PCI Memory Address Range TOLUD 4 GB 25 2 3 3 1 APIC Configuration Space FECO_O000h FECF_FFFFh 26 2 3 3 2 HSEG FEDA_0000h h FEDR FEEF 27 2 3 3 3 MSI Interrupt Memory Space FEE0_0000 FEEF_FFFF 27 2 3 3 4 High BIOS Area EE 27 2 3 4 Main Memory Address Space 4 GBroTOUUD eset ee ee eee ee teenies 27 2 3 4 1 Memory Re claim Background cccceeeeeee eee ee eee eee ee eee eeeeee enna 28 2 3 4 2 Indirect Accesses to MCHBAR Reglsters 29 2 3 4 3 Memory REMAPPING dg BCEE NEE ESANE E SE ge one deg SES sonnets 29 2 3 4 4 Hardware Remap Algooritbm eect eee eee ee ee ee eee ee ea eee 29 2 3 4 5 Programming Model 2058 ENNEREEER dindi heads en Ee edu d 30 2 3 5 PCI Express Configuration Address Space sssssssssrsssssrsrserrrsssrrrrrrrrnns 35 2 3 6 PCI Express Graphics Attach DEG 35 2 3 7 Graphics Memory Address Ranges eect tees eee ee eee ea sidrana didesnei 36 2 3 7 1 IOBAR Mapped Access to Device 2 MMIO Space cccececeeceeeeaeeneaes 36 2 3 7 2 Trusted Graphics RANGES NENNEN NNN a NENNEN RENE ERR NENER ER ENNEN 26 2 3 8 System Management Mode MM 37 2 3 9 SMM and VGA Access through GTT TU 37 2 3 10 ME Stolen MEMOry ACCESSES ssri apies nenn a ENNER SEENEN 37 2 3 11 I O Address SPaC A ee SEENEN DEN SEENEN d jie
184. Not Applicable or Implemented Hardwired to 0 RO Ob Uncore Memory Write and Invalidate Enable MWIE Not Applicable or Implemented Hardwired to 0 RO Ob Uncore Special Cycle Enable SCE Not Applicable or Implemented Hardwired to 0 Datasheet Volume 2 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value 0 6 0 PCI 4 5h 0000h RW RO 16 bits BIOS Optimal Default 00h Bit Access Reset RST Value PWR Description RW 0b Uncore Bus Master Enable BME THis bit controls the ability of the PEG port to forward Memory Read Write Requests in the upstream direction 0 This device is prevented from making memory requests to its primary bus According to PCI Specification as MSI interrupt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus Upstream memory writes reads peer writes reads and MSIs will all be treated as illegal cycles Writes are aborted Reads are aborted and will return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the data is available This bit does not affect forwarding of Completions from the
185. O 32 bits 000000h Bit Access Reset Value RST PWR Description 24 WO Ob Uncore Set Interrupt Remap Table Pointer SIRTP This field is valid only for implementations supporting interrupt remapping Software sets this field to set update the interrupt remapping table pointer used by hardware The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address IRTA_REG register Hardware reports the status of the Set Interrupt Remap Table Pointer operation through the IRTPS field in the Global Status register The Set Interrupt Remap Table Pointer operation must be performed before enabling or re enabling after disabling interrupt remapping hardware through the IRE field After a Get Interrupt Remap Table Pointer operation software must globally invalidate the interrupt entry cache This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer and not any stale cached entries While interrupt remapping is active software may update the interrupt remapping table pointer through this field However to ensure valid in flight interrupt requests are deterministically remapped software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer
186. O FW h o E BEE for the Integrated Graphics Engine GT Values are in units of 100 MHz 2 19 9 PCU_MMIO_FREQ_CLIPPING_CAUSE_STATUS Register This register provides the status of the frequency clipping cause in MMIO for both Power plane 0 IA and Power plane 1 GT B D F Type 0 0 0 MCHBAR PCU Address Offset 5C20 5C23h Reset Value 00000000h Access RW Size 32 bits P Reset RST boni Bit Access Value PWR Description ppi_clipped bai 00090009R oncore Set if the PP1 GT frequency requested was clipped 30 RW 00000000h Reserved RSVD ppi_clipped_non_turbo 29 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped but current frequency is lower than RP1 MAX_NON_TURBO 28 25 RW 00000000h Reserved RSVD ppi_clipped_edp 24 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by EDP limit Vmax Iccmax Reliability and so on 23 RW 00000000h Reserved RSVD ppi_clipped_hot_vr 22 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by HOT indication from VR on SVID pi_clipped_pI2 21 RW 00000000h Uncore Set if the PP1 GT frequency requested was clipped by PL2 POWER_LIMIT_2 power limiting algorithm 302 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 MCHBAR PCU Address Offset 5C20 5C23h Reset Value 00000000h
187. O Oh Reserved RSVD Link Type LTYP Indicates that the link points to memory mapped space for 1 RO Ge Uncorg RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 Link Entry is not valid and will be ignored 0 RW O Ob Uncore 1 Link Entry specifies a valid link BIOS should write 1 to this bit once it has programmed Link Entry 1 Address LE1A and while it writes the TCID in this register 2 11 10 LE1A Link Entry 1 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element Access Size B D F Type Address Offset Reset Value 0 6 0 MMR 158 15Bh 00000000h RW O 32 bits BIOS Optimal Default 000h Reset RST Bit Access Value PWR Description Link Address LA Memory mapped base address of the RCRB that is the target 31 12 RW O 00000h Uncore element Egress Port for this link entry BIOS Requirement This field is inserted by BIOS such that it matches PXPEPBAR 11 0 RO Oh Reserved RSVD 210 Datasheet Volume 2 Processor Configuration Registers intel 2 11 11 LE1AH Link Entry 1 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 6 0 MMR Address Offset 15C 15Fh Reset Value 00000000h Access RW O Size 32 bits BIOS Optimal Default
188. O V Ob Uncore Root Table Pointer Status RTPS This field indicates the status of the root table pointer in hardware This field is cleared by hardware when software sets the SRTP field in the Global Command register This field is set by hardware when hardware completes the Set Root Table Pointer operation using the value provided in the Root Entry Table Address register 29 RO Ob Uncore Fault Log Status FLS This field is e Cleared by hardware when software Sets the SFL field in the Global Command register e Set by hardware when hardware completes the Set Fault Log Pointer operation using the value provided in the Advanced Fault Log register 28 RO Ob Uncore Advanced Fault Logging Status AFLS This field is valid only for implementations supporting advanced fault logging It indicates the advanced fault logging status 0 Advanced Fault Logging is not enabled 1 Advanced Fault Logging is enabled 27 RO Ob Uncore Write Buffer Flush Status WBFS This field is valid only for implementations requiring write buffer flushing This field indicates the status of the write buffer flush command It is e Set by hardware when software sets the WBF field in the Global Command register e Cleared by hardware when hardware completes the write buffer flushing operation 26 RO V Ob Uncore Queued Invalidation Enable Status QIES This field indicates queued
189. ONSTANT power 2 25 per 1 mSec 11 RO Oh Reserved RSVD 10 4 RW VTS offset adder VTS_OFFSET 32h Uncore The offset is intended to provide a temperature proxy offset so the option of having a fixed adder to VTS output is available RO Oh Reserved RSVD RW Disable EXTTS DISABLE_EXTTS When set the processor will ignore the EXTTS signal status that 1b Uncore it receives from the PCH through PM_SYNC messaging 0 Enable 1 Disable RW Disable virtual Temperature Sensor DISABLE_VTS When set the processor will ignore the VTS 0 Enable 1 Disable Ob Uncore RW Disable PECI Injected Temperature DISABLE_PECI_INJECT_TEMP When set the processor will ignore any DRAM temperature written to it over the PECI bus 0 Enable 1 Disable Ob Uncore Datasheet Volume 2 297 intel 2 19 2 298 Processor Configuration Registers MEM_TRML_THRESHOLDS_CONFIG Memory Thermal Thresholds Configuration Register This register is used to describe the thresholds of the memory thermal management in the memory controller The warm threshold defines when self refresh is at double data rate Throttling can also be applied at this threshold based on the configuration in the memory controller The hot threshold defines the threshold at which severe thermal throttling will occur Self Refresh is also at double rate during a hot condition
190. OS Optimal Default 000000h Reset RST Gagn Bit Access Value PWR Description Translation Enable TE Software writes to this field to request hardware to enable disable DMA remapping 0 Disable DMA remapping 1 Enable DMA remapping Hardware reports the status of the translation enable operation through the TES field in the Global Status register 31 wo op Un ore There may be active DMA requests in the platform when software updates this field Hardware must enable or disable remapping logic only at deterministic transaction boundaries so that any in flight transaction is either subject to remapping or not at all Hardware implementations supporting DMA draining must drain any in flight DMA read write requests queued within the Root Complex before completing the translation enable command and reflecting the status of the command through the TES field in the Global Status register The value returned on a read of this field is undefined 316 Datasheet Volume 2 Processor Configuration Registers Size B D F Type Address Offset Reset Value Access BIOS Optimal Default 0 0 0 VCOPREMAP 18 1Bh 00000000h RO WO 32 bits 000000h Bit Access Reset Value RST PWR Description 30 WO Ob Uncore Set Root Table Pointer SRTP Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified throug
191. Ob Reserved for Attention Indicator Present AIP Uncore When set to 1b this bit indicates that an Attention Indicator is electrically controlled by the chassis RO Ob Reserved for MRL Sensor Present MSP Uncore When set to 1b this bit indicates that an MRL Sensor is implemented on the chassis for this slot RO Ob Reserved for Power Controller Present PCP When set to 1b this bit indicates that a software programmable Power Controller is implemented for this slot adapter depending on form factor Uncore RO Ob Reserved for Attention Button Present ABP Uncore When set to 1b this bit indicates that an Attention Button for this slot is electrically controlled by the chassis Datasheet Volume 2 Processor Configuration Registers D 2 6 42 SLOTCTL Slot Control Register Note PCI Express Hot Plug is not supported on the processor B D F Type 0 1 0 2 PCI Address Offset B8 B9h Reset Value 0000h Access RO Size 16 bits BIOS Optimal Default Oh A Reset RST zis Bit Access Value PWR Description 15 13 RO Oh Reserved RSVD Reserved for Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented 12 RO 0b Uncore when set to 1b this field enables software notification when Data Link Layer Link Active field is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to b
192. Ob Powergood Selectable De emphasis selectabledeemphasis When the Link is operating at 5 GT s speed selects the level of de emphasis Encodings 1b 3 5 dB Ob 6 dB When the Link is operating at 2 5 GT s speed the setting of this bit has no effect Components that support only the 2 5 GT s speed are permitted to hardwire this bit to Ob NOTE For DMI this bit has no effect in functional mode as DMI is half swing and will use 3 5 dB whenever de emphasis is enabled Datasheet Volume 2 237 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value 0 0 0 DMIBAR 98 99h 0002h RWS RWS V 16 bits Bit Access Reset RST Value PWR Description RWS Ob Powergood Hardware Autonomous Speed Disable HASD When set to 1b this bit disables hardware from changing the link speed for reasons other than attempting to correct unreliable link operation by reducing link speed RWS Ob Powergood Enter Compliance EC Software is permitted to force a link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link 3 0 RWS 2h Powergood Target Link Speed TLS For Downstream ports this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its
193. Ob Powergood the details of the fault is recorded in other fields When this field is set hardware may collapse additional faults from the same source id SID Software writes the value read from this field to clear it Type T Type of the faulted request 0 Write request 62 ROS V Ob Powergood 1 Read request or AtomicOp request This field is relevant only when the F field is set and when the fault reason FR indicates one of the DMA remapping fault conditions Address Type AT This field captures the AT field from the faulted DMA request Hardware implementations not supporting Device IOTLBs DI 61 60 RO 00b Uncore e in Extended Capability register treat this field as When supported this field is valid only when the F field is set and when the fault reason FR indicates one of the DMA remapping fault conditions 59 40 RO Oh Reserved RSVD Fault Reason FR 39 32 ROS V 00h Powergood This field provides the reason for the fault This field is relevant only when the F field is set 31 16 RO Oh Reserved RSVD 000000000 Source Identifier SID 15 0 ROS V gQg00000b_ Powergood This field provides the Requester id associated with the fault condition This field is relevant only when the F field is set Datasheet Volume 2 Processor Configuration Registers intel 2 18 32 VTPOLICY DMA Remap Engine Policy Control Register This register contains all the policy bits related to the DMA remap engine
194. Ob Uncore TcO VCp Map TCOVCPM Datasheet Volume 2 225 intel Processor Configuration Registers 2 12 13 DMIVCPRSTS DMI VCp Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMIBAR Address Offset 32 33h Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h e Reset RST Parr Bit Access Value PWR Description 15 2 RO Oh Reserved RSVD Virtual Channel private Negotiation Pending VCPNP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This bit indicates the status of the process of Flow Control 1 RO V 1b Uncore initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Oh Reserved RSVD 2 12 14 DMIVCMRCAP DMI VCm Resource Capability Register Access Size B D F Type Address Offset Reset Value 0 0 0 DMIBAR 34 37h 00008000h RO 32 bits BIOS Optimal Default 00000000h Reset RST Bit Access Value
195. PCI Express Controller 0151h 1 0 PCI Express Controller 0155h 1 1 PCI Express Controller 0159h 1 2 Integrated Graphics Device 0156h 2 0 PCI Express Controller 015Dh 6 0 Note Not all devices are enabled in all configurations 16 Datasheet Volume 2 Processor Configuration Registers D t I H 2 3 System Address Map The processor supports 512 GB 39 bit of addressable memory space and 64 KB 3 of addressable I O space This section focuses on how the memory space is partitioned and the use of the separate memory regions I O address space has simpler mapping and is explained near the end of this section The processor supports PEG port upper prefetchable base limit registers This allows the PEG unit to claim I O accesses above 32 bit Addressing of greater than 4 GB is allowed on either the DMI Interface or PCI Express PClIe interface The processor supports a maximum of 32 GB of DRAM No DRAM memory will be accessible above 32 GB DRAM capacity is limited by the number of address pins available There is no hardware lock to stop someone from inserting more memory than is addressable When running in internal graphics mode processor initiated TilexX Tiley linear reads writes to GMADR range are supported Write accesses to GMADR linear regions are supported from both DMI and PEG GMADR write accesses to tileX and tileY regions defined using fence registers are not supported from DMI or the PEG port GMADR r
196. PWR Description 63 56 RO Oh Reserved RSVD DMA Read Draining DRD 55 RO 1b Uncore 0 Hardware does not support draining of DMA read requests 1 Hardware supports draining of DMA read requests DMA Write Draining DWD 54 RO 1b Uncore 0 Hardware does not support draining of DMA write requests 1 Hardware supports draining of DMA write requests Maximum Address Mask Value MAMV The value in this field indicates the maximum supported value for the Address Mask AM field in the Invalidation Address register IVA_REG and IOTLB Invalidation Descriptor iotlb_inv_dsc This field is valid only when the PSI field in Capability register is reported as set 53 48 RO 001001b Uncore Number of Fault recording Registers NFR The number of fault recording registers is computed as N 1 where N is the value reported in this field Implementations must support at least one fault recording 00000000 47 40 RO U b ee register NFR 0 for each remapping hardware unit in the platform The maximum number of fault recording registers per remapping hardware unit is 256 Page Selective Invalidation PSI 0 Hardware supports only domain and global invalidates for IOTLB 39 RO 1b Uncore 1 Hardware supports page selective domain and global invalidates for IOTLB Hardware implementations reporting this field as set are recommended to support a Maximum Address Mask Value MAMV value of at least 9 38 38 RO Oh Reserve
197. Plug is not supported on the processor 19 RO Ob Uncore Surprise Down Error Reporting Capable SDERC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob 114 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset AC AFh Reset Value 0261CD03h Access RO RO V RW O RW OV Size 32 bits Reset RST Zs Bit Access Value PWR Description Clock Power Management CPM A value of 1b in this bit indicates that the component tolerates the removal of any reference clock s when the link is in the L1 and L2 3 Ready link states A value of Ob indicates the component does not have this capability and that reference 18 RO Ob D se clock s ae nor be removed in these link states This capability is applicable only in form factors that support clock request CLKREQ capability For a multi function device each function indicates its capability independently Power Management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit 17 15 RO Oh Reserved RSVD LOs Exit Latency LOSELAT This field indicates the length of time this Port requir
198. QO_0000h FEEF_FFFFh MSI TOLUD TOLUD Gfx Stolen Gfx GTT stolen TSEG_BASE TSEG TSEG_BASE DPR A0000h BFFFFh VGA mem writes gt peer write if matching PEG range else invalid mem reads gt Invalid transaction mem writes gt Route based on SNR bit mem reads gt Route based on SNR bit mem writes gt CPU IntLogical IntPhysical mem reads gt Invalid transaction mem writes gt non snoop mem write mem reads gt invalid transaction YZ mem writes gt peer write based on Dev1 VGA en else invalid mem reads gt Invalid transaction Datasheet Volume 2 41 DN t Processor Configuration Registers 2 3 13 2 2 3 13 2 1 42 PCI Express Interface Decode Rules All SNOOP semantic PCI Express transactions are kept coherent with processor caches All Snoop not required semantic cycles must reference the direct DRAM address range PCI Express non snoop initiated cycles are not snooped If a Snoop not required semantic cycle is outside of the address range mapped to system memory then it will proceed as follows e Reads Sent to DRAM address 000C_0000h non snooped and will return unsuccessful completion e Writes Sent to DRAM address 000C_0000h non snooped with byte enables all disabled Peer writes from PEG to DMI are not supported If PEG bus master enable is not set all reads and writes are treated as unsupported requests
199. Queue Address Register This register configures the base address and size of the invalidation queue This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 90 97h Reset Value 0000000000000000h Access RW L Size 64 bits BIOS Optimal Default 000000000h z Reset RST a Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Invalidation Queue Base Address IQA This field points to the base of 4 KB aligned invalidation request queue Hardware ignores and does not implement bits 63 HAW aoe Ret 00000001 neers where HAW is the host address width Reads of this field return the value that was last programmed to it 11 3 RO Oh Reserved RSVD Queue Size QS This field specifies the size of the invalidation request queue A 2 0 RW L Oh Uncore value of X in this field indicates an invalidation request queue of 2X 4 KB pages The number of entries in the invalidation queue is 2 X 8 2 18 22 ICS _REG Invalidation Completion Status Register This register reports completion status of invalidation wait descriptor with Interrupt Flag IF set This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 9C 9Fh Reset Value 00000000h
200. R Description Device Identification Number MSB DID_MSB 15 0 RO FW 0151h Uncore Identifier assigned to the processor root port virtual PCI to PCI bridge PCI Express Graphics port 2 6 3 PCICMD PCI Command Register B D F Type 0 1 0 2 PCI Address Offset 4 5h Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 00h a Reset RST iis Bit Access Value PWR Description 15 11 RO Oh Reserved RSVD INTA Assertion Disable INTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt messages Any INTA emulation interrupts already asserted 10 RW Ob Uncore must be de asserted when this bit is set This bit only affects interrupts generated by the device PCI INTA from a PME or Hot plug event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and deassert messages Note PCI Express Hot Plug is not supported on the processor Fast Back to Back Enable FB2B 9 RO 0 b Uncore Not Applicable or Implemented Hardwired to 0 88 Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 1 0 2 PCI Address Offset 4 5h Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 00h Reset RST Bit Access Value PWR Description SERR Message Enable SERRE This bit controls the root port
201. RLINE Interrupt Line Register This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information B D F Type 0 1 0 2 PCI Address Offset 3Ch Reset Value 00h Access RW Size 8 bits J Reset RST ae Bit Access Value PWR Description Interrupt Connection INTCON This field is used to communicate interrupt line routing information 7 0 RW 00h Uncore BIOS Requirement POST software writes the routing information into this register as it initializes and configures the system The value indicates to which input of the system interrupt controller this device s interrupt pin is connected 2 6 23 INTRPIN Interrupt Pin Register This register specifies which interrupt pin this device uses B D F Type 0 1 0 2 PCI Address Offset 3Dh Reset Value Oih Access RW O RO Size 8 bits Reset RST eer Bit Access Value PWR Description 7 3 RO 00h Uncore Reserved RSVD Interrupt Pin INTPIN As a multifunction device the PCI Express device may specify any INTx x A B C D as its interrupt pin The Interrupt Pin register indicates which interrupt pin the device or device function uses A value of 1 corresponds to INTA Default A value of 2 corresponds to INTB 2 0 RWO Sir SE A value of 3 corresponds to INTCH A value of 4 corresponds to INTD Devices
202. RO Oh Reserved RSVD Unsupported Request Detected URD This bit indicates that the Function received an Unsupported 3 RW1C Ob Uncore Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Fatal Error Detected FED This bit indicates status of Fatal errors detected Errors are 2 RW1C Ob Uncore logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Non Fatal Error Detected NFED This bit indicates status of Nonfatal errors detected Errors are 1 RW1C Ob Uncore logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Correctable Error Detected CED This bit indicates status of correctable errors detected Errors are 0 RW1C Ob Uncore logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function 190 Datasheet Volume 2 Processo
203. RSVD Reserved Oh RO D 6C D6Fh BGFCTL3 BGF Control 3 400204E0h RW D70 DBFh RSVD Reserved Oh RO DCO DC3h EQPRESET1_2 Equalization Preset 1 2 Register 3400FBCOh RW DC4 DC7h EQPRESET2_3_4 Equalization Preset 2 3 4 Register 0037100Ah RW DC8 DCBh RSVD Reserved Oh RO DCC DCFh EQPRESET6_7 Equalization Preset 6 7 Register 36200E06h RW DDO DD7h RSVD Reserved Oh RO DD8 DDBh EQCFG Equalization Configuration Register 00000000h RW Datasheet Volume 2 203 intel Processor Configuration Registers 2 11 1 PVCCAP1 Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 6 0 MMR Address Offset 104 107h Reset Value 00000000h Access RO Size 32 bits BIOS Optimal Default 0000000h o Reset RST Ge Bit Access Value PWR Description 31 7 RO Oh Reserved RSVD Low Priority Extended VC Count LPEVCC Indicates the number of extended Virtual Channels in addition 6 4 RO 00 to the default VC belonging to the low priority VC LPVC group E SE that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Oh Reserved RSVD Extended VC Count EVCC 2 0 RO 000b Uncore Indicates the number of extended Virtual Channels in addition to the default VC supported by the device 2 11 2 PVCCAP2 Port VC Capability Register 2 Th
204. Refresh Timing Parameters Register This register provides the Refresh timing parameters B D F Type 0 0 0 MCHBAR MCO Address Offset 4298 429Bh Reset Value 46B41004h Access RW L Size 32 bits Reset RST pores Bit Access Value PWR Description 9 tREFI 31 25 RW L 23h Uncore Period of minimum between 9 tREFI and tRAS maximum normally 70 us in 1024 DCLK cycles default is 35h Refresh execution time tRFC 24 16 RW L OB4h Uncore Time of refresh from beginning of refresh until next ACT or refresh is allowed in DCLK cycles default is 180h tREFI period in DCLK cycles tREFI 15 0 RW L 1004h Uncore This field defines the average period between refreshes and the rate that tREFI counter is incremented in DCLK cycles default is 4100h 244 Datasheet Volume 2 Processor Configuration Registers ntel 2 14 MCHBAR Registers in Memory Controller Channel 1 Table 2 17 MCHBAR Registers in Memory Controller Channel 1 Register Address Map Address Register Register Name Reset Value Access Symbol 0 43FFh RSVD Reserved Oh RO 4400 4403h TC_DBP_C1 Timing of DDR bin parameters 00146666h RW L 8 Timing of DDR regular access g 4404 4407h TC_RAP_C1 parameters 86104344h RW L 4408 4427h RSVD Reserved 4428 442Bh SC_IO_LATENCY_ IO Latency configuration 000E0000h RW L 442C 44AFh RSVD Reserved 44B0 44B3
205. Register This register defines which channel is assigned to be channel A channel B and channel C according to the rule size A size B size C Since the processor implements only two channels channel C is always channel 2 and its size is always 0 B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5000 5003h Reset Value 00000024h Access RW L Size 32 bits BIOS Optimal Default 0000000h Bit Access ierg ss cae Description 31 6 RO Oh Reserved RSVD Channel C assignment CH_C CH_C defines the smallest channel 5 4 RW L 10b Uncore 00 Channel 0 01 Channel 1 10 Channel 2 Channel B assignment CH_B CH_B defines the mid size channel 3 2 RW L 01b Uncore 00 Channel 0 01 Channel 1 10 Channel 2 Channel A assignment CH_A CH A defines the largest channel 1 0 RW L 00b Uncore 00 Channel 0 01 Channel 1 10 Channel 2 Datasheet Volume 2 253 Processor Configuration Registers intel 2 16 2 MAD_DIMM_ch0 Address Decode Channel 0 Register This register defines channel characteristics number of DIMMs number of ranks size interleave options B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5004 5007h Reset Value 00600000h Access RW L Size 32 bits BIOS Optimal Default 00h Reset RST Pare Bit Access Value PWR Description 31 26 RO Oh Reserved RSVD 25 24 RO 00b Reserved RSVD 23 RO Oh Reserved RSVD Enhanced
206. S V 000b Powergood Transmit Margin txmargin This field controls the value of the non deemphasized voltage level at the Transmitter pins This field is reset to 000b on entry to the LTSSM Polling Configuration substate see PCIe Specification Chapter 4 for details of how the transmitter voltage level is determined in various states 000 Normal operating range 001 800 1200 mV for full swing and 400 700 mV for half swing 010 n 1 Values must be monotonic with a non zero slope The value of n must be greater than 3 and less than 7 At least two of these must be below the normal operating range n 200 400 mV for full swing and 100 200 mV for half swing n 111 Reserved Reset Value is 000b Components that support only the 2 5 GT s speed are permitted to hardwire this bit to Ob When operating in 5 GT s mode with full swing the de emphasis ratio must be maintained within 1 dB from the specification defined operational value either 3 5 or 6 dB The processor supports the following values 000 Normal operation Reset Value coefficients cursor precursor postcursor are at defined values 001 Coefficients are divided by 2 010 Coefficients are divided by 4 011 Coefficients are divided by 8 All other codes are reserved The coefficients translate to 4 level values that are sent to the AFE Note that Tx margining has no effect on the levels if bypass levels are enabled 6 RWS
207. STS Device Status Register 190 2 10 38 LCAP Link Capabilities Register 191 2 10 39 LCTL Link Control Register ccccceeeee cece eee eee e eee a eee a eee ee eee iE 193 2 10 40 LSTS Link Status Regester e KENE KAREN iernii EEN SE ENEE NNSE REENEN 195 2 10 41 SLOTCAP Slot Capabilities Register 196 2 10 42 SLOTCTL Slot Control Regester sVeke ENKER NERE NEES EEN ENNEN N EEN 198 2 10 43 SLOTSTS Slot Status Register ee imaan REENEN EES ESSE KK 200 Datasheet Volume 2 2 10 44 RCTL Root Control Register SkSNNK NES EN REENEN NENNEN ERR NNR E RENE SR EN NN 202 2 10 45 LCAP2 Link Capabilities 2 Register cceeeeee eee eeee eens eee eee eeeeeeeeeeaeas 202 2 11 PCI Device 6 Extended Configuration Reglsters teeta eeeeeeeeeeeeeeias 203 2 11 1 PVCCAP1 Port VC Capability Register 1 204 2 11 2 PVCCAP2 Port VC Capability Register 2 204 2 11 3 PVCCTL Port VC Control ReGiSter cc eeeeeeeee eee ee sees tees eee eeeeeeeaeeeies 205 2 11 4 VCORCAP VCO Resource Capability Register 205 2 11 5 VCORCTL VCO Resource Control Register 207 2 11 6 VCORSTS VCO Resource Status Register 10 cece cece eee eee eee eaten tenn eee 208 2 11 7 RCLDECH Root Complex Link Declaration Enhanced esscsescceerrrse 208 2 11 8 ESD Element Self Description Register 209 2 11 9 LE1D Link Entry 1 Description Register 210 2 11 10 LE1A Link Entry 1 Address Register 210 2 11 11 LE1AH Link Entry
208. See 38 3Bh FECTL_REG Fault Event Control Register 80000000h RW RO V 3C 3Fh FEDATA_REG Fault Event Data Register 00000000h RW 40 43h FEADDR_REG Fault Event Address Register 00000000h RW 44 47h FEUADDR_REG Fault Event Upper Address Register 00000000h RW 48 57h RSVD Reserved Oh RO 58 5Fh AFLOG_REG Advanced Fault Log Register 0000970090900 RO 60 63h RSVD Reserved Oh RO 64 67h PMEN_REG Protected Memory Enable Register 00000000h RW RO V 68 6Bh PLMBASE_REG Protected Low Memory Base Register 00000000h RW 6C 6Fh PLMLIMIT_REG Protected Low Memory Limit Register 00000000h RW 70 77h PHMBASE_REG Protected High Memory Base 0000000000000 RW Register 000h 8 Protected High Memory Limit 0000000000000 78 7Fh PHMLIMIT_REG Register 000h RW 80 87h IQH_REG Invalidation Queue Head Register 9000070000000 RO V 88 8Fh IQT_REG Invalidation Queue Tail Register 0999070090900 RW L 90 97h IQA_REG Invalidation Queue Address Register 0090070990900 RW L 98 9Bh RSVD Reserved Oh RO 9C 9Fh ICS_REG Invalidation Completion Status 00000000h RWICS Register A0 A3h IECTL_REG Invalidation Event Control Register 80000000h RW L RO V A4 A7h IEDATA_REG Invalidation Event Data Register 00000000h RW L A8 ABh IEADDR_REG Invalidation Event Address Register 00000000h RW L 309 Processor Configuration Registers intel Table 2 24 Default PEG DMI VTd Remapping Engine Register Address Map Sheet 2 of 2 poor Symbol Register Name Reset Value Access AC A
209. Self Refresh Timing Parameters Register 242 2 13 5 PM_PDWN_config_C0 Power down Configuration Register 243 2 13 6 TC_RFP_CO Refresh Parameters Register 244 2 13 7 TC_RFTP_CO Refresh Timing Parameters Register 244 MCHBAR Registers in Memory Controller Channel 1 245 2 14 1 TC_DBP_Ci Timing of DDR Bin Parameters Register sscccceccerrerern 245 2 14 2 TC_RAP_Ci Timing of DDR Regular Access Parameters Register 246 2 14 3 SC_IO_LATENCY_C1i IO Latency configuration Register 247 2 14 4 PM_PDWN_config_C1 Power down Configuration Register 248 2 14 5 TC_RFP_Ci Refresh Parameters Register 249 2 14 6 TC_RFTP_C1i Refresh Timing Parameters Register 250 2 14 TC_SRFTP_Ci Self refresh Timing Parameters Register 250 MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub IMPH ccceeeeeeeeeeee ee eee e eee ea eases tenet eeeeaeaeas 251 2 15 1 CRDTCTL3 Credit Control 3 Register 251 2 15 2 CRDTCTL4 Credit Control 4 Register 252 MCHBAR Registers in Memory Controller COMMON tees eee eeeeeee eee eeeeeaee 253 2 16 1 MAD_CHNL Address Decoder Channel Configuration Register 253 2 16 2 MAD_DIMM_chO Address Decode Channel 0 Register 254 2 16 3 MAD_DIMM_chi Address Decode Channel 1 Register 255 2 16 4 PM_SREF_config Self Refresh Configuration Register 256 Memory Controller MMIO Registers Broadcast Group Reglsters 257 2 17 1 PM_PDWN_config
210. This bit defines when command amp address bus is driving 29 RW L b 0 Drive when channel is active Tri stated when all ranks are in 9 SIS CKE off or when memory is in SR or deeper 1 Command bus is always driving When no new valid command is driven previous command amp address is driven tWR in DCLK cycles tWR 28 24 RW L 06h S S ancore Write recovery time The range is 5 to 16 DCLK cycles tFAW in DCLK cycles tFAW S Four activate window is the time frame in which maximum of 4 23 16 SE toh ngore ACT commands to the same rank are allowed The minimum value is 4 tRRD whereas the maximum value is 63 DCLK cycles tWTR in DCLK cycles tWTR s Delay from internal WR transaction to internal RD transaction 15 12 RW L 4h SES The minimum delay is 4 DCLK cycles whereas the maximum delay is 8 DCLK cycles tCKE in DCLK cycles tCKE e CKE minimum pulse width in DCLK cycles The minimum value is 11 RW L h S 3 EISE 3 DCLK cycles whereas the maximum value is the actual value of tXP tRTP in DCLK cycles tRTP 7 4 RW L 4h Uncore Minimum delay from CAS RD to PRE The minimum delay is 4 DCLK cycles whereas the maximum delay is 8 DCLK cycles tRRD in DCLK cycles tRRD S tRRD is the minimum delay between two ACT commands S RW L 4h 3 0 SSES targeted to different banks in the same rank The minimum delay is 4 DCLK cycles whereas the maximum delay is 7 cycles Datasheet Volume
211. Top of Low Usable DRAM Register 80 SKPD Scratchpad Data Register 81 CAPIDO_A Capabilities A REQiSter ccccccscsecesseneeeeeceeeeeeeeeeceaaensaeaaeeeees 82 CAPIDO_B Capabilities B Register 84 evice 1 Function 0 2 Configuration Space Reglsters este eeeeeeaeaees 86 VID Vendor Identification Register 87 DID Device Identification Register 88 PCICMD PCI Command Register 88 PCISTS PCI Status Register eERN REENEN EEN EE RENE SEENEN REENEN EEN EES E EEN 90 RID Revision Identification Register 92 CC Class C de Registe aninion inai NENNEN ENNER ENEE ENEE E de vena 92 CL Cache Line Size REGiIStORieciescciiscicaieeeseaceeseag EES NE REENEN ER A 92 HDR Header Type Register 93 PBUSN Primary Bus Number Register e e eeeeeee esse ee eeeeeeeee eset eeeaeaee 93 SBUSN Secondary Bus Number Register ceceeeeeeeeeee este este eeeeeeeenees 93 SUBUSN Subordinate Bus Number Register 94 IOBASE I O Base Address Register 95 IOLIMIT I O Limit Address Register 95 SSTS Secondary Status Register 96 MBASE Memory Base Address Register c eeeeeeeee tees eee eeeeeeeeeeeeeanaee 97 MLIMIT Memory Limit Address Register 98 PMBASE Prefetchable Memory Base Address Register 99 PMLIMIT Prefetchable Memory Limit Address Register 100 PMBASEU Prefetchable Memory Base Address Upper Register 100 PMLIMITU Prefetchable Memory Limit Address Upper Register
212. U ZE this bit is hardwired to 0 Writes to this bit position have no effect Parity Error Enable PERRE This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set 6 RW Ob Uncore 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set VGA Palette Snoop Enable VGASNOOP 5 RO Ob Uncore The processor does not implement this bit and it is hardwired to a 0 Writes to this bit position have no effect Memory Write and Invalidate Enable MWIE 4 RO Ob Uncore The processor will never issue memory write and invalidate commands This bit is therefore hardwired to 0 Writes to this bit position will have no effect 3 RO Oh Reserved RSVD Bus Master Enable BME The processor is always enabled as a master on the backbone a Ro tp Ge This bit is hardwired to a 1 Writes to this bit position have no effect Memory Access Enable MAE The processor always allows access to main memory except 1 RO ib ncore When such access would violate security principles Such S exceptions are outside the scope of PCI control This bit is not implemented and is hardwired to 1 Writes to this bit position have no effect I O Access Enable IOAE 0 RO Ob Uncore This bit is not implemented in the processor and is hardwired to a 0 Writes to this bit position have no effect 2 5 4
213. V Size 16 bits BIOS Optimal Default 00h Reset RST a Bit Access Value PWR Description 15 12 RO Oh Reserved RSVD Link Training LTRN This field indicates that the Physical Layer LTSSM is in the o Configuration or Recovery state or that 1b was written to the 11 RO V b r S g SBS Retrain Link bit but Link training has not yet begun Hardware clears this bit when the LTSSM exits the Configuration Recovery state once Link training is complete 10 0 RO Oh Reserved RSVD Datasheet Volume 2 235 intel Processor Configuration Registers 2 12 27 LCTL2 Link Control 2 Register 236 B D F Type 0 0 0 DMIBAR Address Offset 98 99h Reset Value 0002h Access RWS RWS V Size 16 bits Reset RST SEN Bit Access Value PWR Description Compliance De emphasis ComplianceDeemphasis For 8 GT s Data Rate This field sets the Transmitter Preset level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1b The encodings are defined in PCIe Specification Section 4 2 3 2 For 5 GT s Data Rate This bit filed sets the de emphasis level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1b 0001b 3 5 dB 0000b 6 dB 15 12 RWS 0000b Powergood When the Link is operating at 2 5 GT s the setting of this bit has no effect Components that support only 2 5 GT s speed are permitted to hardwire this bit to Ob For a Multi Function
214. VC Arbitration Table As a VC Arbitration Table is never used by this component this field will never be used 2 11 4 VCORCAP VCO Resource Capability Register B D F Type 0 6 0 MMR Address Offset 110 113h Reset Value 00000001h Access RO Size 32 bits BIOS Optimal Default 00h Reset RST inii Bit Access Value PWR Description 31 24 RO 00h Uncore Reserved for Port Arbitration Table Offset PATO 23 RO Oh Reserved RSVD 22 16 RO 00h Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the 15 RO Ob Uncore TLP header are allowed on this VC 1 When set any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request 14 8 RO Oh Reserved RSVD Datasheet Volume 2 205 206 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 6 0 MMR 110 113h 00000001h RO 32 bits BIOS Optimal Default 00h Bit Access Reset RST Value PWR Description 7 0 RO Oih Uncore Port Arbitration Capability PAC Indicates types of Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that
215. VD Link Type LTYP This field indicates that the link points to memory mapped space 1 RO Ob Uncore for RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 RW O Ob Uncore 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 232 Datasheet Volume 2 Processor Configuration Registers intel 2 12 23 DMILE2A DMI Link Entry 2 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 68 6Bh Reset Value 00000000h Access RW O Size 32 bits BIOS Optimal Default 0000h 8 Reset RST aias Bit Access Value PWR Description Link Address LA 31 12 RW O 00000h Uncore Memory mapped base address of the RCRB that is the target element Egress Port for this link entry 11 0 RO Reserved RSVD 2 12 24 LCAP Link Capabilities Register This register indicates DMI specific capabilities B D F Type 0 0 0 DMIBAR Address Offset 84 87h Reset Value 0001AC4ih Access RW O RO RW OV Size 32 bits BIOS Optimal Default 00002h Bit Access ierg gail Description 31 18 RO Reserved RSVD L1 Exit Latency L1SELAT This field indicates the length of time this Port requires to complete the transition from L1 to LO The value 011b indicates the range of 4 us t
216. VD 6 4 3 0 RW RW Lane 0 Upstream Component Receiver Preset Hint UCRPHO Receiver Preset Hint for Upstream Component The upstream 000b Uncore dan g SE component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO Transmitter Preset for an Upstream Component See the PCIe 1000b U oo E Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 140 Datasheet Volume 2 Processor Configuration Registers intel 2 7 11 EQCTL6_7 Lane 6 7 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane B D F Type 0 1 0 1 MMR Address Offset DAC DAFh Reset Value 07080708h Access RW Size 32 bits BIOS Optimal Default Oh e Reset RST uis Bit Access Value PWR Description 31 RO Oh Reserved RSVD Lane 1 Downstream Component Receiver Preset Hint DCRPH1 S Receiver Preset Hint for Downstream Component The Upstream 30 2 RW 000b U EES Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Downstream Component Transmitter Preset DCTP1 z Transmitter Preset for Downstrea
217. VREF DDR3L 1 35V DDR operation allowed DDR3L_EN 0 RO FW Ob Uncore This bit allows DDR3L 1 35V DDR operation PCODE will update this field with the value of FUSE_DDR3L_EN Datasheet Volume 2 83 intel Processor Configuration Registers 2 5 39 CAPIDO_B Capabilities B Register Control of bits in this register are only required for customer visible SKU differentiation 84 B D F Type 0 0 0 PCI Address Offset E8 EBh Default Value 00100000h Access RO FW RO KFW Size 32 bits BIOS Optimal Default 000000h P RST SEN Bit Access Reset Value PWR Description 31 RO FW Oh Reserved RSVD 30 RO FW Ob Reserved RSVD 29 RO FW Ob Reserved RSVD SMT Capability SMT 28 RO FW Ob Uncore This setting indicates whether or not the processor is SMT capable Cache Size Capability CACHESZ 27 25 SE Ger SES This setting indicates the supporting cache sizes 24 RO FW Ob Reserved RSVD DDR3 Maximum Frequency Capability with 100 Memory PLL_REF100_CFG DDR3 Maximum Frequency Capability with 100 MHz memory PCODE will update this field with the value of FUSE_PLL_REF100_CFG and then apply SSKU overrides Maximum allowed memory frequency with 100 MHz reference clock Also serves as defeature Unlike 133 MHz reference fuses these are normal 3 bit fields 23 21 RO FW 000b Unicare 200 Mia tef disabled 1 Up to DDR 1400 7 x 200 2 Up to DDR 1600 8 x 200 3 Up to DDR 1
218. VT field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field Software must not submit another invalidation request through this register while the IVT field is set nor update the associated Invalidate Address register Software must not submit IOTLB invalidation requests when there is a context cache invalidation request pending at this remapping hardware unit Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flushing before invalidating the IOTLB 63 RW V Oh Uncore 62 62 RO Oh Reserved RSVD IOTLB Invalidation Request Granularity IIRG When requesting hardware to invalidate the IOTLB by setting the IVT field software writes the requested invalidation granularity through this field The following are the encodings for the field 00 Reserved 01 Global invalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field 11 Page selective invalidation request The target address mask and invalidation hint must be specified in the Invalidate Address register and the domain id must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates comp
219. W 0000000h Uncore Software specifies the base address of the root entry table through this register and programs it in hardware through the SRTP field in the Global Command register Reads of this register returns value that was last programmed to it 11 0 RO Oh Reserved RSVD Datasheet Volume 2 321 intel Processor Configuration Registers 2 21 7 CCMD_REG Context Command Register This register manages context cache The act of writing the uppermost byte of the CCMD_REG with the ICC field set causes the hardware to perform the context cache invalidation Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 VCOPREMAP 28 2Fh 0000000000000000h RW V RW RO V 64 bits 000000000h Bit 63 Access RW V Reset Value Oh RST PWR Uncore Description Invalidate Context Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field is Clear to confirm the invalidation is complete Software must not update this register when this field is set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field Software must submit a context cache inval
220. W Ob Uncore 0 Enable VTd 1 Disable VTd 22 RO FW Ob Reserved RSVD 21 RO FW Ob Reserved RSVD 20 19 RO FW 00b Reserved RSVD 18 RO FW Ob Reserved RSVD 17 RO FW Ob Reserved RSVD 16 RO FW Ob Reserved RSVD 15 RO KFW Ob Reserved RSVD 2 DIMMS per Channel Disable DDPCD This bit allows Dual Channel operation but only supports 1 DIMM per channel 14 RO FW Ob Uncore 0 2 DIMMs per channel enabled 1 2 DIMMs per channel disabled This setting hardwires bits 2 and 3 of the rank population field for each channel to zero MCHBAR offset 260h bits 22 23 for channel 0 and MCHBAR offset 660h bits 22 23 for channel 1 13 RO FW Ob Reserved RSVD 12 RO FW Ob Reserved RSVD 11 RO KFW Ob Reserved RSVD 10 RO FW Ob Reserved RSVD 9 8 RO FW 00b Reserved RSVD 7 4 RO FW Oh Reserved RSVD 82 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset E4 E7h Reset Value 00000000h Access RO FW RO KFW Size 32 bits BIOS Optimal Default 000000h e Reset RST SE Bit Access Value PWR Description IA Overclocking Enabled by DSKU OC_ENABLED_DSKU 2 RO FW Ob Uncore The default constant non fuse value is zero When the VDM sets this bit OC will be applied if OC_CTL_SSKU points to DSKU On die DDR write Vref generation allowed DDR_WRTVREF 1 RO FW Ob Uncore This bit allow on die DDR write Vref generation PCODE will update this field with the value of FUSE_DDR_WRT
221. _REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant zero bit position with O in the value read back from the register Bits N 0 of this register is decoded by hardware as all Os Software must set up the protected low memory region below 4 GB Software must not modify this register when protected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 68 6Bh Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 00000h Reset RST ee Bit Access Value PWR Description Protected Low Memory Base PLMB 31 20 RW 000h Uncore This register specifies the base of protected low memory region in system memory 19 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D t I H 2 21 16 PLMLIMIT_REG Protected Low Memory Limit Register This register sets up the limit address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected mem
222. ace 35 MB lost memory 3 GB 35 MB minimum granularity O_ECBO_0000h Since 0_ECBO_0000h PCI and other system requirements is less than 1_0000_0000h TOLUD should be programmed to ECBh These bits are Intel TXT lockable Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 0 0 PCI Address Offset BC BFh Reset Value 00100000h Access RW KL RW L Size 32 bits BIOS Optimal Default 00000h Reset RST Bit Access Value PWR Description Top of Low Usable DRAM TOLUD This register contains bits 31 20 of an address one byte above the maximum DRAM memory below 4 GB that is usable by the operating system Address bits 31 20 programmed to O1h implies a minimum memory size of 1 MB Configuration software must set this value to the smaller of the following 2 choices maximum amount memory in the system minus Intel ME stolen memory plus one byte or the minimum address allocated for PCI memory Address bits 19 0 are assumed to be 0_0000h for the 31 20 RW L O01h Uncore purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and TSEG BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by TSEG size to determine base of TSEG All t
223. ace the graphics device will report a page table error PCI Express and DMI Interface write accesses through GMADR range will not be snooped Only PCI Express and DMI assesses to GMADR linear range defined using fence registers are supported PCI Express and DMI Interface tileY and tileX writes to GMADR are not supported If when translated the resulting physical address is to enable SMM DRAM space the request will be remapped to address 000C_0000h with de asserted byte enables PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns PCI Express and DMI Interface reads to GMADR will be remapped to address 000C_0000h The read will complete with UR unsupported request completion status GTT fetches are always decoded at fetch time to ensure not in SMM actually anything above base of TSEG or 640 KB 1 MB Thus they will be invalid and go to address 000C_0000h but that is not specific to PCI Express or DMI it applies to processor or internal graphics engines ME Stolen Memory Accesses There are only 2 ways to legally access Intel ME stolen memory e PCH accesses mapped to VCm will be decoded to ensure only Intel ME stolen memory is targeted These VCm accesses will route non snooped directly to DRAM This is the means by which the Intel MEengine located within the PCH is able to access the Intel ME stolen range e The Display engine is allowed to a
224. age selective invalidation requests 01 Global Invalidation performed This could be in response to a global domain selective or page selective invalidation request 10 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or a page selective invalidation request 11 Domain page selective invalidation performed using the address mask and hint specified by software in the Invalidate Address register and domain id specified in DID field This can be in response to a page selective invalidation request 56 50 RO Oh Reserved RSVD 49 RW Ob Uncore Drain Reads DR This field is ignored by hardware if the DRD field is reported as clear in the Capability register When the DRD field is reported as set in the Capability register the following encodings are supported for this field 0 Hardware may complete the IOTLB invalidation without draining any translated DMA read requests 1 Hardware must drain DMA read requests 48 RW Ob Uncore Drain Writes DW This field is ignored by hardware if the DWD field is reported as Clear in the Capability register When the DWD field is reported as set in the Capability register the following encodings are supported for this field 0 Hardware may complete the IOTLB invalidation without draining DMA write requests 1 Hardware must drain releva
225. aim BASE Add Range MESEG BASE 1 MB aligned Main memory OS visible Address gt 4GB Range 4 GB Flash APIC Intel TXT OS invisible FEC0_0000 H CEV Reclaim TOLUD BASE 1 MB aligned PCI Memory SEH Add Range GFX Stolen BASE subtractively decoded to GFX GTT DMI STOLEN GFX GTT Stolen BASE 0 2 MB TSEG TSEG 0 8 MB TSEG BASE be Main Memory OS Add Range VISIBLE lt 4GB 1 MB Legacy Add Range 0 1 MB aligned 1 MB aligned 1 MB aligned for reclaim 1 MB aligned 1 MB aligned 1 MB aligned 2 3 1 Legacy Address Range This area is divided into the following address regions e 0 640 KB DOS Area 640 768 KB Legacy Video Buffer Area 768 896 KB in 16 KB sections total of 8 sections Expansion Area 896 960 KB in 16 KB sections total of 4 sections Extended System BIOS Area e 960 KB 1 MB Memory System BIOS Area Datasheet Volume 2 19 DN t Processor Configuration Registers Figure 2 2 DOS Legacy Address Range 2 3 1 1 2 3 1 2 20 1 MB 000F_FFFFh System BIOS Upper 000F_0000h 64 KB 960 KB 000E_FFFFh Extended System BIOS Lower 64 KB 16KBx4 000E_0000h A 000D_FFFFh Expansion Area 128 KB 16KBx8 000C_0000h 768 KB 000B_FFFFh Legacy Video Area SMM Memory 128 KB 000A_0000h F 640 KB 0009_FFFFh DOS Area 0000_0000h DOS Range 0h 9_FFFFh The DOS area is 640 KB 0000_0000h 0009_FFFFh in size and is alwa
226. ammed in this field Datasheet Volume 2 289 intel Processor Configuration Registers 2 18 28 IVA_REG Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register This register is a write only register Access Size B D F Type Address Offset Reset Value 0 0 0 GFXVTBAR 100 107h 0000000000000000h RW 64 bits BIOS Optimal Default 00000000h Bit 63 39 Access RO Reset RST Value PWR Oh Description Reserved RSVD 38 12 RW 0000000h Uncore Address ADDR Software provides the DMA address that needs to be page selectively invalidated To make a page selective invalidation request to hardware software must first write the appropriate fields in this register and then issue the appropriate page selective invalidate command through the IOTLB_REG Hardware ignores bits 63 N where N is the maximum guest address width MGAW supported RO Oh Reserved RSVD RW Oh Uncore Invalidation Hint IH The field provides hint to hardware about preserving or flushing the non leaf page directory entries that may be cached in hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware must flu
227. and Completed notification is not supported this bit must be hardwired to Ob Datasheet Volume 2 123 124 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset BA BBh Reset Value 0000h Access RO RW1C RO V Size 16 bits BIOS Optimal Default 00h z Reset RST Ets Bit Access Value PWR Description Presence Detect Changed PDC A pulse indication that the inband presence detect state has 3 RW1ic Ob Uncore changed This bit is set when the value reported in Presence Detect State is changed Reserved for MRL Sensor Changed MSC If an MRL sensor is implemented this bit is set when a MRL 2 RO 0 p Z Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Reserved for Power Fault Detected PFD If a Power Controller that supports power fault detection is implemented this bit is set when the Power Controller detects a 1 RO Ob Uncore Power fault at this slot Depending on hardware capability it is possible that a power fault can be detected at any time independent of the Power Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Reserved for Attention Button Pressed ABP If an Attention Button is implemented this bit is set when the 0 R 0 r S b pacers attention button is pressed If an Attention Button is not supported this bit must not be set
228. anularity of 4 KB The processor positively decodes I O accesses to PCI Express I O address space as defined by the following equation I O_Base_Address lt processor I O Cycle Address lt I O_Limit_Address The effective size of the range is programmed by the plug and play configuration software and it depends on the size of I O space claimed by the PCI Express device Datasheet Volume 2 Processor Configuration Registers D t I H Note 2 3 12 2 3 13 2 3 13 1 The processor also forwards accesses to the Legacy VGA I O ranges according to the settings in the PEG configuration registers BCTRL VGA Enable and PCICMD IOAE unless a second adapter monochrome is present on the DMI Interface PCI or ISA The presence of a second graphics adapter is determined by the MDAP configuration bit When MDAP is set the processor will decode legacy monochrome I O ranges and forward them to the DMI Interface The I O ranges decoded for the monochrome adapter are 3B4h 3B5h 3B8h 3B9h 3BAh and 3BFh The PEG I O address range registers defined above are used for all I O space allocation for any devices requiring such a window on PCI Express The PCICMD register can disable the routing of I O cycles to PCI Express MCTP and KVM Flows Refer to THE DMI2 specification for details MCTP cycles are not processed within the processor MCTP cycles are merely passed from input port to destination port based on routing ID Decode Rules an
229. apabilities list is present Hardwired to 1 INTx Status INTAS This bit indicates that an interrupt message is pending internally to the device Only PME and Hot plug sources feed into this status bit not PCI INTA INTD assert and deassert messages 3 RO V Ob Uncore The INTA Assertion Disable bit PCICMD1 10 has no effect on this bit Note INTA emulation interrupts received across the link are not reflected in this bit Note PCI Express Hot Plug is not supported on the processor 2 0 RO Oh Reserved RSVD Datasheet Volume 2 91 Processor Configuration Registers intel 2 6 5 RID Revision Identification Register This register contains the revision number of the processor root port These bits are read only and writes to this register have no effect B D F Type 0 1 0 2 PCI Address Offset 8h Reset Value 00h Access RO FW Size 8 bits Bit Access ere ct Description Revision Identification Number RID This is an 8 bit value that indicates the revision identification 7 0 RO FW Oh Uncore number for the root port Refer to the Mobile 3rd Generation Intel Core Processor Family Specification Update for the value of the RID register 2 6 6 CC Class Code Register This register identifies the basic function of the device a more specific sub class and a register specific programming interface B D F Type 0 1 0 2 PCI Address Offset 9 Bh Reset Value 060400
230. arded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 68 Datasheet Volume 2 Processor Configuration Registers intel 2 5 25 PAM4 Programmable Attribute Map 4 Register This register controls the read write and shadowing attributes of the BIOS range from D8000h to DFFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the s
231. ast significant three bits of the SID field to mask when performing device selective invalidations The following encodings are defined for this field 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of function number in the SID field 11 Mask all three bits of function number in the SID field The context entries corresponding to all the source ids specified through the FM and SID fields must have to the domain id specified in the DID field 31 16 RW 0000h Uncore Source ID SID This field indicates the source id of the device whose corresponding context entry needs to be selectively invalidated This field along with the FM field must be programmed by software for device selective invalidation requests 15 8 RO Oh Reserved RSVD 7 0 RW 00h Uncore Domain ID DID This field indicates the id of the domain whose context entries need to be selectively invalidated This field must be programmed by software for both domain selective and device selective invalidation requests The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware may ignore and not implement bits15 N where N is the supported domain id width reported in the Capability register Datasheet Volume 2 3
232. at are enabled by the IOBASE and IOLIMIT registers 0 All addresses defined by the IOBASE and IOLIMIT for processor I O transactions will be mapped to PCI Express G 1 The root port will not forward to PCI Express G any I O transactions addressing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers RW Ob Uncore SERR Enable SERREN 0 No forwarding of error messages from secondary side to primary side that could result in an SERR 1 ERR_COR ERR_NONFATAL and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register RW Ob Uncore Parity Error Response Enable PEREN Controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the root port receives across the link upstream a Read Data Completion Poisoned TLP 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set 180 Datasheet Volume 2 Processor Configuration Registers intel 2 10 25 PM_CAPID Power Management Capabilities Register Size B D F Type Address Offset Reset Value Access 0 6 0 PCI 80 83h C8039001h RO RO V 32 bits Bit Access Reset Value RST PWR Description 31 27 RO 19h Uncore PME Support PMES This field indi
233. ated as a new interrupt condition The IP field is kept set by hardware while the interrupt message 30 RO V Ob Uncore is held pending The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field e Software servicing the IWC field in the Invalidation Completion Status register 29 0 RO Oh Reserved RSVD 2 21 24 IEDATA_REG Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A4 A7h Reset Value 00000000h Access RW L Size 32 bits Bit Access erg R Gar Description Extended Interrupt Message Data EIMD This field is valid only for implementations supporting 32 bit 31 16 RW L 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data treat this field as Rsvd Interrupt Message data IMD 15 RW L 000h 39 ZER SES Data value in the in
234. ates status of errors as perceived by the respective Function Non Fatal Error Detected NFED This bit indicates status of Nonfatal errors detected Errors are 1 RW1iC Ob Uncore logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Correctable Error Detected CED This bit indicates status of correctable errors detected Errors are 0 RW1iC Ob Uncore logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Datasheet Volume 2 113 intel 2 6 38 Processor Configuration Registers LCAP Link Capabilities Register B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI AC AFh 0261CD03h RO RO V RW O RW OV 32 bits Bit Access Reset Value RST PWR Description 31 24 RO 02h Uncore Port Number PN This field indicates the PCI Express port number for the given PCI Express link Matches the value in Element Self Description 31 24 The value if this field differs between root ports 2h Device 1 function 0 3h Device 1 function 1 4h Device 1 function 2 5h Device 6 function 0 23 RO Oh Reserved RSV
235. avior for all combinations of MDA and VGA VGAEN MDAP Description 0 0 All References to MDA and VGA space are not claimed by Device 1 Function 2 1 Illegal combination 1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 2 1 1 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 2 MDA references are not claimed by Device 1 Function 2 VGA and MDA memory cycles can only be routed across PEG12 when MAE PCICMD12 1 is set VGA and MDA I O cycles can only be routed across PEG12 if IOAE PCICMD12 0 is set Datasheet Volume 2 73 74 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 0 0 PCI 87h 00h RW 8 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description RW Ob Uncore PEG11 MDA Present MDAP11 This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set if Device 1 Function 1 VGA Enable bit is not set If Device 1 Function 1 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 1 Function 1
236. b Uncore Interrupt Mask IM 0 No masking of interrupt When an interrupt condition is detected hardware issues an interrupt message using the Fault Event Data and Fault Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set 30 RO V Oh Uncore Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition which is defined as When primary fault logging is active an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in Fault Status register When advanced fault logging is active an interrupt condition occurs when hardware records a fault in the first fault record at index 0 of the current fault log and sets the APF field in the Fault Status register Hardware detected error associated with the Invalidation Queue setting the IQE field in the Fault Status register Hardware detected invalid Device IOTLB invalidation completion setting the ICE field in the Fault Status register Hardware detected Device IOTLB invalidation completion time out setting the ITE field in the Fault Status register If any of the status fields in the Fault Status register was already set at the time of setting any of these fields it is not treated as a new interrup
237. b 0 Vers Not Applicable or Implemented Hardwired to 0 Capabilities List CAPL 4 RO 1b Uncorg Indicates that a capabilities list is present Hardwired to 1 INTx Status INTAS This bit indicates that an interrupt message is pending internally to the device Only PME and Hot plug sources feed into this status bit not PCI INTA INTD assert and deassert messages 3 RO V Ob Uncore The INTA Assertion Disable bit PCICMD1 10 has no effect on this bit INTA emulation interrupts received across the link are not reflected in this bit Note PCI Express Hot Plug is not supported on the processor 2 0 RO Oh Reserved RSVD 2 10 5 RID Revision Identification Register This register contains the revision number of the processor root port These bits are read only and writes to this register have no effect B D F Type 0 6 0 PCI Address Offset 8h Reset Value 00h Access RO FW Size 8 bits Bit Access PRE A Description Revision Identification Number RID This is an 8 bit value that indicates the revision identification 7 0 RO FW Oh Uncore number for the root port Refer to the Mobile 3rd Generation Intel Core Processor Family Specification Update for the value of the RID register Datasheet Volume 2 167 Processor Configuration Registers intel 2 10 6 CC Class Code Register This register identifies the basic function of the device a more specific s
238. bal Status register 3 0 RO Reserved RSVD 2 21 20 IQT_REG Invalidation Queue Tail Register This register indicates the invalidation tail head This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 88 8Fh Reset Value 0000000000000000h Access RW L Size 64 bits BIOS Optimal Default 0000000000000h a Reset RST bale Bit Access Value PWR Description 63 19 RO Reserved RSVD Queue Tail QT 18 4 RW L 0000h Uncore This field specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software 3 0 RO Reserved RSVD 334 Datasheet Volume 2 Processor Configuration Registers intel 2 21 21 IQA_REG Invalidation Queue Address Register This register configures the base address and size of the invalidation queue This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 90 97h Reset Value 0000000000000000h Access RW L Size 64 bits BIOS Optimal Default 000000000h Reset RST a Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Invalidation Queue Base Address IQA This field points to the base of 4 KB aligned invalidation request p d queue Hardwa
239. bal Status register The fault log pointer must be set before enabling advanced fault logging through EAFL field Once advanced fault logging is enabled the fault log pointer may be updated through this field while DMA remapping is active Clearing this bit has no effect The value returned on read of this field is undefined 28 RO Ob Uncore Enable Advanced Fault Logging EAFL This field is valid only for implementations supporting advanced fault logging Software writes to this field to request hardware to enable or disable advanced fault logging 0 Disable advanced fault logging In this case translation faults are reported through the Fault Recording registers 1 Enable use of memory resident fault log When enabled translation faults are recorded in the memory resident log The fault log pointer must be set in hardware through the SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Global Status register The value returned on read of this field is undefined Datasheet Volume 2 317 318 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 0 0 VCOPREMAP 18 1Bh 00000000h RO WO 32 bits 000000h Bit Access Reset Value RST PWR Description 27 RO Ob Uncore Write Buf
240. be removed from the system without any prior notification This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation RO Ob Uncore Reserved for Power Indicator Present PIP When set to 1b this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot RO Ob Uncore Reserved for Attention Indicator Present AIP When set to 1b this bit indicates that an Attention Indicator is electrically controlled by the chassis RO Ob Uncore Reserved for MRL Sensor Present MSP When set to 1b this bit indicates that an MRL Sensor is implemented on the chassis for this slot RO Ob Uncore Reserved for Power Controller Present PCP When set to 1b this bit indicates that a software programmable Power Controller is implemented for this slot adapter depending on form factor RO Ob Uncore Reserved for Attention Button Present ABP When set to 1b this bit indicates that an Attention Button for this slot is electrically controlled by the chassis Datasheet Volume 2 197 intel Processor Configuration Registers 2 10 42 SLOTCTL Slot Control Register Note 198 PCI Express Hot Plug is not supported on the processor B D F Type Address Offset Reset Value Access Size BIOS Optimal Default
241. bilities 00008000h RO RW O A8 A9h DCTL Device Control 0020h RO RW AA ABh DSTS Device Status 0000h RW1C RO AC AFh LCAP Link Capabilities 0261CD03h RUO EE BO Bih LCTL Link Control 0000h RW RO RW V B2 B3h LSTS Link Status 1001h Ee B4 B7h SLOTCAP Slot Capabilities 00040000h RW O RO B8 B9h SLOTCTL Slot Control 0000h RO BA BBh SLOTSTS Slot Status 0000h ey BC BDh RCTL Root Control 0000h RO RW BE BFh RSVD Reserved Oh RO CO C3h RSTS Root Status 00000000h GC C4 C7h DCAP2 Device Capabilities 2 00000800h RO RW O C8 C9h DCTL2 Device Control 2 0000h RW V RW CA CBh RSVD Reserved Oh RO CC CFh LCAP2 Link Capabilities 2 0000000Eh RO V DO Dih LCTL2 Link Control 2 0003h RWS RWS V D2 D3h LSTS2 Link Status 2 0000h RO V RW1C vID Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device B D F Type 0 1 0 2 PCI Address Offset O ih Reset Value 8086h Access RO Size 16 bits Bit Access deich ed Description Vendor Identification VID 13 9 o SEN PCI standard identification for Intel Datasheet Volume 2 87 Processor Configuration Registers intel 2 6 2 DID Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 1 0 2 PCI Address Offset 2 3h Reset Value 0151h Access RO FW Size 16 bits Reset RST ZE Bit Access Value PW
242. bilities list If z MSICH CAPL 0 7Fh is 0 then the next item in the SE SES zon Uncore capabilities list is the Message Signaled Interrupts MSI capability at 90h If MSICH CAPL 0 7Fh is 1 then the next item in the capabilities list is the PCI Express capability at AOh Capability ID CID 7 0 RO Oih Uncore Value of O1h identifies this linked list item capability structure as being for PCI Power Management registers 2 6 26 PM_CS Power Management Control Status Register B D F Type 0 1 0 2 PCI Address Offset 84 87h Reset Value 00000008h Access RO RW Size 32 bits BIOS Optimal Default 000000h 5 Reset RST SA Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD PME Status PMESTS 15 RO Ob Uncore This bit indicates that this device does not support PME generation from D3cold Data Scale DSCALE 14 13 RO 00b Uncore This field indicates that this device does not support the power management data register Data Select DSEL 12 9 RO Oh Uncore This field indicates that this device does not support the power management data register Datasheet Volume 2 105 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value 0 1 0 2 PCI 84 87h 00000008h RO RW 32 bits BIOS Optimal Default 000000h Bit Access Reset RST Value PWR Description RW PME Enable PMEE Th
243. bit register defines the Top of Upper Usable DRAM Configuration software must set this value to TOM minus all Intel ME stolen memory if reclaim is disabled If reclaim is enabled this value must be set to reclaim limit 1 byte 1 MB aligned since reclaim limit is 1 MB aligned Address bits 19 0 are assumed to be 000_0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4 GB BIOS Restriction Minimum value for TOUUD is 4 GB These bits are Intel TXT lockable B D F Type 0 0 0 PCI Address Offset A8 AFh Reset Value 0000000000000000h Access RW KL RW L Size 64 bits BIOS Optimal Default 00000000000h e Reset RST Peer Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD TOUUD TOUUD This register contains bits 38 20 of an address one byte above the maximum DRAM memory above 4 GB that is usable by the operating system Configuration software must set this value to TOM minus all Intel ME stolen memory if reclaim is disabled If reclaim is enabled this value must be set to reclaim limit 1 MB 38 20 Ret 00000h Uncore aligned since reclaim limit 1byte is 1 MB aligned Address bits 19 0 are assumed to be 000_0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than t
244. bute from the processor point of view to that range The USWC attribute is used by the processor for write combining IOBAR Mapped Access to Device 2 MMIO Space Device 2 integrated graphics device contains an IOBAR register If Device 2 is enabled then IGD registers or the GTT table can be accessed using this IOBAR The IOBAR is composed of an index register and a data register MMIO_Index MMIO_INDExX is a 32 bit register A 32 bit all bytes enabled I O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed An I O Read returns the current value of this register I O read write accesses less than 32 bits in size all bytes enabled will not target this register MMIO_Data MMIO_DATA is a 32 bit register A 32 bit all bytes enabled I O write to this port is re directed to the MMIO register pointed to by the MMIO index register An I O read to this port is re directed to the MMIO register pointed to by the MMIO index register I O read write accesses less than 32 bits in size all bytes enabled will not target this register The result of accesses through IOBAR can be e Accesses directed to the GTT table that is route to DRAM e Accesses to internal graphics registers with the device e Accesses to internal graphics display registers now located within the PCH that is route to DMI GTT table space writes GTTADR are supported through this mapping mechanism This mechanism
245. care Power down idle timer PDWN_idle_counter 7 0 RW L 00h Uncore This field defines the rank idle period in DCLK cycles that causes power down entrance Datasheet Volume 2 243 Processor Configuration Registers intel 2 13 6 TC_RFP_CO Refresh Parameters Register This register provides the refresh parameters B D F Type 0 0 0 MCHBAR MCO Address Offset 4294 4297h Reset Value 0000980Fh Access RW L Size 32 bits BIOS Optimal Default 0000h e Reset RST oe Bit Access Value PWR Description 31 18 RO Oh Reserved RSVD Double Refresh Control DOUBLE_REFRESH_CONTROL This field will allow the double self refresh enable disable 17 16 RW L 00b Wncore 00 Double refresh rate when DRAM is WARM HOT 01 Force double self refresh regardless of temperature 10 Disable double self refresh regardless of temperature 11 Reserved Refresh panic WM Refresh_panic_wm tREFI count level in which the refresh priority is panic default is 15 12 RW L 9h Uncore 9 It is recommended to set the panic WM at least to 9 in order to use the maximum no refresh period possible Refresh high priority WM Refresh_HP_WM 11 8 RW L 8h Uncore tREFI count level that turns the refresh priority to high default is Rank idle timer for opportunistic refresh OREF_RI 7 0 RW L OFh Uncore Rank idle period that defines an opportunity for refresh in DCLK cycles 2 13 7 TC_RFTP_CO
246. cated anywhere in 16bit I O Address Space Bits 2 1 are fixed and return zero bit 0 is hardwired to a one indicating that 8 bytes of I O space are decoded Access to the 8Bs of I O space is allowed in PM state DO when I O Enable PCICMD bit 0 set Access is disallowed in PM states D1 D3 or if I O Enable is clear or if Device 2 is turned off or if internal graphics is disabled thru the fuse or fuse override mechanisms Access to this I O BAR is independent of VGA functionality within Device 2 If accesses to this I O bar are allowed then all 8 16 or 32 bit I O cycles from IA cores that falls within the 8B are claimed B D F Type 0 2 0 PCI Address Offset 20 23h Reset Value 00000001h Access RW RO Size 32 bits BIOS Optimal Default 00000h n Reset RST BS Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD FLR IO Base Address IOBASE 15 6 ii gooh Uncore Set by the OS these bits correspond to address signals 15 6 5 3 RO Oh Reserved RSVD Memory Type MEMTYPE 2 1 RO 00b Unicorg Hardwired to Os to indicate 32 bit address 0 RO ib wacere Memory IO Space MIOS Hardwired to 1 to indicate I O space SVID2 Subsystem Vendor Identification Register This register is used to uniquely identify the subsystem where the PCI device resides B D F Type 0 2 0 PCI Address Offset 2C 2Dh Reset Value 0000h Access RW O Size 16 bits Bit Access eng if Description
247. cates the power states in which this device may indicate PME wake using PCI Express messaging DO D3hot amp D3cold This device is not required to do anything to support D3hot amp D3cold it simply must report that those states are supported Refer to the PCI Power Management 1 1 specification for encoding explanation and other power management details 26 RO Ob Uncore D2 Power State Support D2PSS Hardwired to 0 to indicate that the D2 power management state is NOT supported 25 RO Ob Uncore D1 Power State Support D1PSS Hardwired to 0 to indicate that the D1 power management state is NOT supported 24 22 RO 000b Uncore Auxiliary Current AUXC Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements 21 RO Ob Uncore Device Specific Initialization DSI Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it 20 RO Ob Uncore Auxiliary Power Source APS Hardwired to 0 19 RO Ob Uncore PME Clock PMECLK Hardwired to 0 to indicate this device does NOT support PME generation 18 16 RO 011b Uncore PCI PM CAP Version PCIPMCV A value of 011b indicates that this function complies with revision 1 2 of the PCI Power Management Interface Specification Was Previously Hardwired to 02h to indicate there are 4 bytes o
248. cation Note This version does not change for 2 0 compliance Extended Capability ID ECID 15 0 RO 0002h Uncore Value of 0002h identifies this linked list item capability structure as being for PCI Express Virtual Channel registers 218 Datasheet Volume 2 Processor Configuration Registers intel 2 12 2 DMIPVCCAP1 DMI Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 0 0 DMIBAR Address Offset 4 7h Reset Value 00000000h Access RO RW O Size 32 bits BIOS Optimal Default 0000000h 5 Reset RST iias Bit Access Value PWR Description 31 7 RO Oh Reserved RSVD Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in n addition to the default VC belonging to the low priority VC LPVC oa RO ooo Ven group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Oh Reserved RSVD Extended VC Count EVCC 2 0 RW O 000b Uncore This field indicates the number of extended Virtual Channels in addition to the default VC supported by the device 2 12 3 DMIPVCCAP2 DMI Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port
249. ccess Intel ME stolen memory as part of KVM flows Specifically Display initiated HHP reads for displaying a KVM frame and display initiated LP non snoop writes for display writing a KVM captured frame to Intel ME stolen memory are allowed Datasheet Volume 2 37 DN t l Processor Configuration Registers 2 3 11 1 38 I O Address Space The system agent generates either DMI Interface or PCI Express bus cycles for all processor I O accesses that it does not claim Configuration Address Register CONFIG_ADDRESS and the Configuration Data Register CONFIG_DATA are used to generate PCI configuration space access The processor allows 64K 3 bytes to be addressed within the I O space The upper 3 locations can be accessed only during I O address wrap around when address bit 16 is asserted Address bit 16 is asserted on the processor bus whenever an I O access is made to 4 bytes from address OFFFDh OFFFEh or OFFFFh Address bit 16 is also asserted when an I O access is made to 2 bytes from address OFFFFh A set of I O accesses are consumed by the internal graphics device if it is enabled The mechanisms for internal graphics I O decode and the associated control is explained later The I O accesses are forwarded normally to the DMI Interface bus unless they fall within the PCI Express I O address range as defined by the mechanisms explained below I O writes are NOT posted Memory writes to PCH or PCI Express are posted The PCI Ex
250. ccess Value PWR Description 31 20 RO Oh Reserved RSVD Link Declaration Capability Version LDCV Hardwired to 1 to indicate compliances with the 1 1 version of 19 16 RO Lhi score the PCI Express specification Note This version does not change for 2 0 compliance Extended Capability ID ECID Value of 0005 h identifies this linked list item capability 15 0 RO 0005h Uncore structure as being for PCI Express Link Declaration Capability See corresponding Egress Port Link Declaration Capability registers for diagram of Link Declaration Topology 208 Datasheet Volume 2 Processor Configuration Registers intel 2 11 8 ESD Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability B D F Type 0 6 0 MMR Address Offset 144 147h Reset Value 05000100h Access RO RW O Size 32 bits BIOS Optimal Default Oh 8 Reset RST iias Bit Access Value PWR Description Port Number PN Specifies the port number associated with this element with respect to the component that contains this element Note the value is instantiation dependent 31 24 RO O5h Uncore BDF 0 1 0 gt 02 BDF 0 1 1 gt 03 BDF 0 1 2 gt 04 BDF 0 6 0 gt 05 Component ID CID Identifies the physical component that contains this Root 23 16 RW O 00h Uncore Complex Element BIOS Requirement This field must be initialized a
251. ccording to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS Number of Link Entries NLE 15 8 RO Oih Uncore Indicates the number of link entries following the Element Self Description This field reports 1 to Egress port only 7 4 RO Oh Reserved RSVD Element Type ET 0 RO h 3 9 Ungore Indicates Configuration Space Element Datasheet Volume 2 209 intel Processor Configuration Registers 2 11 9 LE1D Link Entry 1 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 6 0 MMR Address Offset 150 153h Reset Value 00000000h Access RO RW O Size 32 bits BIOS Optimal Default 0000h e Reset RST Se Bit Access Value PWR Description Target Port Number TPN Specifies the port number associated with the element targeted e by this link entry Egress Port The target port number is with aaa RO SEN Uncere respect to the component that contains this element as specified by the target component ID OOh is the egress port memory Target Component ID TCID Identifies the physical or logical component that is targeted by 23 16 RW O 00h Uncore this link entry BIOS Requirement This field must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 R
252. ceived across the link upstream a Read Data Completion Poisoned TLP EP 1 This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set RO Ob Uncore Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 RO Oh Reserved RSVD RO Ob Uncore 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 0 RO Oh Reserved RSVD Datasheet Volume 2 171 intel 2 10 15 172 Processor Configuration Registers MBASE Memory Base Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 20 21h Reset Value FFFOh Access RW Size 16 bits BIOS Optimal Default Oh o Reset RST Ge Bit Access Value PWR Description Memory Address Base MBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20
253. cess performance Configuration software is responsible for programming all address range registers prefetchable non prefetchable with the values that provide exclusive address ranges that is prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the processor hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured B D F Type 0 1 0 2 PCI Address Offset 22 23h Reset Value 0000h Access RW Size 16 bits BIOS Optimal Default Oh o Reset RST Se Bit Access Value PWR Description Memory Address Limit MLIMIT 15 4 RW 000h Uncore This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 3 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D t I H 2 6 17 PMBASE Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initia
254. ching Mode CM 0 Not present and erroneous entries are not cached in any of the remapping caches Invalidations are not required for modifications to individual not present or invalid entries However any modifications that result in decreasing the effective permissions or partial permission increases require 7 RO Ob Uncore invalidations for them to be effective 1 Not present and erroneous mappings may be cached in the remapping caches Any software updates to the remapping structures including updates to not present or erroneous entries require explicit invalidation Hardware implementations of this architecture must support a value of 0 in this field Protected High Memory Region PHMR 6 RO 1b Uncore 0 Indicates protected high memory region is not supported 1 Indicates protected high memory region is supported Protected Low Memory Region PLMR 5 RO 1b Uncore 0 Protected low memory region is not supported 1 Protected low memory region is supported Datasheet Volume 2 313 314 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9008020660262h Access RO Size 64 bits BIOS Optimal Default o00h Bit Access Weg af Description Required Write Buffer Flushing RWBF 0 Indicates no write buffer flushing is needed to ensure changes to memory resident structures are visible to 4 RO Ob Uncore hardware 1 Indicates software mus
255. corg CKE off or when memory is in SR or deeper 1 Command bus is always driving When no new valid command is driven previous command amp address is driven tWR in DCLK cycles tWR 28 24 RWE geh SS Write recovery time The range is 5 to 16 DCLK cycles tFAW in DCLK cycles tFAW s d Four activate window is the time frame in which maximum of 4 23 16 RWL 10h SES ACT commands to the same rank are allowed The minimum value is 4 tRRD whereas the maximum value is 63 DCLK cycles 246 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 MCHBAR MC1 Address Offset 4404 4407h Reset Value 86104344h Access RW L Size 32 bits Reset RST SE Bit Access Value PWR Description tWTR in DCLK cycles tWTR Delay from internal WR transaction to internal RD transaction 15 12 RW L 4h gt Ungore The minimum delay is 4 DCLK cycles whereas the maximum delay is 8 DCLK cycles tCKE in DCLK cycles tCKE e E CKE minimum pulse width in DCLK cycles The minimum value is e RMEL an Uncorg 3 DCLK cycles whereas the maximum value is the actual value of tXP tRTP in DCLK cycles tRTP 7 4 RW L 4h Uncore Minimum delay from CAS RD to PRE The minimum delay is 4 DCLK cycles whereas the maximum delay is 8 DCLK cycles tRRD in DCLK cycles tRRD 0 RW L 4h tRRD is the minimum delay between two ACT commands 3 SES targeted to different banks in the same rank The minimum delay is 4 DCLK cycl
256. d Hardware must enable or disable interrupt remapping logic only at deterministic transaction boundaries so that any in flight interrupts are either subject to remapping or not at all Hardware implementations must drain any in flight interrupts requests queued in the Root Complex before completing the interrupt remapping enable command and reflecting the status of the command through the IRES field in the Global Status register The value returned on a read of this field is undefined Datasheet Volume 2 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 VCOPREMAP 18 1Bh 00000000h RO WO 32 bits 000000h Bit Access Reset Value RST PWR Description 24 WO Ob Uncore Set Interrupt Remap Table Pointer SIRTP This field is valid only for implementations supporting interrupt remapping Software sets this field to set update the interrupt remapping table pointer used by hardware The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address IRTA_REG register Hardware reports the status of the Set Interrupt Remap Table Pointer operation through the IRTPS field in the Global Status register The Set Interrupt Remap Table Pointer operation must be performed before enabling or re enabling after disabling interrupt remapping hardware through the IRE field After a Set
257. d RSVD Super Page Support SPS This field indicates the super page sizes supported by hardware A value of 1 in any of these bits indicates the corresponding super page size is supported The super page sizes corresponding to various bit positions within this field are 0 21 bit offset to page frame 2 MB 1 30 bit offset to page frame 1 GB 2 39 bit offset to page frame 512 GB 3 48 bit offset to page frame 1 TB Hardware implementations supporting a specific super page size must support all smaller super page sizes that is only valid values for this field are 0001b 0011b 0111b 1111b 37 34 RO 0000b Uncore H Datasheet Volume 2 311 312 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 0 0 VCOPREMAP 8 Fh 00C9008020660262h RO 64 bits BIOS Optimal Default o00h Bit Access Reset RST Value PWR Description 33 24 RO 020h Uncore Fault recording Register offset FRO This field specifies the location to the first fault recording register relative to the register base address of this remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first fault recording register is calculated as X 16 Y 23 RO Ob Uncore Isochrony ISOCH 0 Remapping hardware unit has no critical isochronous requesters in its scope 1 Re
258. d by the root port to PCI Express G 7 4 RW Fh Uncore 3 0 RO Oh Reserved RSVD IOLIMIT I O Limit Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type 0 1 0 2 PCI Address Offset 1Dh Reset Value 00h Access RW Size 8 bits BIOS Optimal Default Oh e Reset RST Se Bit Access Value PWR Description I O Address Limit IOLIMIT 7 This field corresponds to A 15 12 of the I O address limit of the Ga RW ZE root port Devices between this upper limit and IOBASE1 will be passed to the PCI Express hierarchy associated with this device 3 0 RO Reserved RSVD Datasheet Volume 2 95 Processor Configuration Registers 2 6 14 SSTS Secondary Status Register SSTS is a 16 bit status register that reports the occurrence of error conditions associated with secondary side that is PCI Express G side of the virtual PCI PCI bridge embedded within the processor Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 1 0 2 PCI 1E 1Fh 0000h RW1C RO 16 bits 00h Bit 15 14 Access RW1C RW1C
259. d Cross Bridge Address Mapping DMI Interface Decode Rules All SNOOP semantic PCI Express transactions are kept coherent with processor caches All Snoop not required semantic cycles must reference the main DRAM address range PCI Express non snoop initiated cycles are not snooped The processor accepts accesses from DMI Interface to the following address ranges e All snoop memory read and write accesses to Main DRAM including PAM region except stolen memory ranges TSEG AOOOOh BFFFFh space e Write accesses to enabled VGA range MBASE MLIMIT and PMBASE PMLIMIT will be routed as peer cycles to the PCI Express interface e Write accesses above the top of usable DRAM and below 4 GB not decoding to PCI Express or GMADR space will be treated as master aborts e Read accesses above the top of usable DRAM and below 4 GB not decoding to PCI Express will be treated as unsupported requests e Reads and accesses above the TOUUD will be treated as unsupported requests on VCO VCp DMI Interface memory read accesses that fall between TOLUD and 4 GB are considered invalid and will master abort These invalid read accesses will be reassigned to address 000C_0000h and dispatch to DRAM Reads will return unsupported request completion Writes targeting PCI Express space will be treated as peer to peer cycles There is a known usage model for peer writes from DMI to PEG A video capture card can be plugged into the PCH PCI bus The vid
260. d correspond to address bits A 38 32 of the 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 6 0 PCI Address Offset 2C 2Fh Reset Value 00000000h Access RW Size 32 bits Bit Access ate Ge Description Prefetchable Memory Address Limit PMLIMITU 31 0 RW 00000000h Uncore This field corresponds to A 63 32 of the upper limit of the prefetchable Memory range that will be passed to PCI Express G Datasheet Volume 2 177 Processor Configuration Registers intel 2 10 21 CAPPTR Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities B D F Type 0 6 0 PCI Address Offset 34h Reset Value 88h Access RO Size 8 bits Bit Access ere it Description First Capability CAPPTR1 7 0 RO 88h Uncore The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability 2 10 22 INTRLI
261. ddress Offset 9 Bh Reset Value 030000h Access RO V RO Size 24 bits Bit Access Hsia ald Description Base Class Code BCC 23 16 RO V 03h Uncore This is an 8 bit value that indicates the base class code 03h Display Controller Sub Class Code SUBCC 15 8 RO V 00h Uncore 00h VGA compatible Programming Interface PI ger RO goh ZE 00h Display Controller 152 Datasheet Volume 2 Processor Configuration Registers D 2 8 7 CLS Cache Line Size Register The IGD does not support this register as a PCI slave B D F Type 0 2 0 PCI Address Offset Ch Reset Value 00h Access RO Size 8 bits a Reset RST el Bit Access Value PWR Description Cache Line Size CLS 7 0 RO 00h Uncore This field is hardwired to Os The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and in general does not perform operations based on cache line size 2 8 8 MLT2 Master Latency Timer Register The IGD does not support the programmability of the master latency timer because it does not perform bursts B D F Type 0 2 0 PCI Address Offset Dh Reset Value 00h Access RO Size 8 bits Reset RST Par Bit Access Value PWR Description 7 0 RO 00h ancora Master Latency Timer Count Value MLTCV Hardwired to Os 2 8 9 HDR2 Header Type Register This register contains the Header Type of the IGD
262. ddress range registers prefetchable non prefetchable with the values that provide exclusive address ranges that is prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the processor hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured B D F Type 0 6 0 PCI Address Offset 22 23h Reset Value 0000h Access RW Size 16 bits BIOS Optimal Default Oh 2 Reset RST eee Bit Access Value PWR Description Memory Address Limit MLIMIT 15 4 RW 000h Uncore This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 3 0 RO Oh Reserved RSVD Datasheet Volume 2 173 DN t Processor Configuration Registers 2 10 17 174 PMBASE Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address
263. decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 24 25h Reset Value FFFih Access RW RO Size 16 bits Bit Access eg if Description Prefetchable Memory Base Address PMBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 64 bit Address Support AS64 3 This field indicates that the upper 32 bits of the prefetchable 0 R th S a aS memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h Datasheet Volume 2 Processor Configuration Registers D t I H 2 10 18 PMLIMIT Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be
264. determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size PCI Device 0 offset 52h bits 9 8 from the Graphics Base of Data Stolen Memory PCI Device 0 offset BOh bits 31 20 B D F Type 0 0 0 PCI Address Offset B4 B7h Reset Value 00100000h Access RW L RW KL Size 32 bits BIOS Optimal Default 00000h i Reset RST ca Bit Access Value PWR Description Graphics Base of GTT Stolen Memory BGSM This register contains the base address of stolen DRAM memory i 8 for the GTT BIOS determines the base of GTT stolen memory by 1 2 RW L 1h See SR SE subtracting the GTT graphics stolen memory size PCI Device 0 offset 52h bits 11 8 from the Graphics Base of Data Stolen Memory PCI Device 0 offset BOh bits 31 20 19 1 RO Reserved RSVD Lock LOCK 0 RW KL Uncore This bit will lock all writeable settings in this register including itself Datasheet Volume 2 79 DN t Processor Configuration Registers Note 2 5 36 80 TSEGMB TSEG Memory Base Register This register contains the base address of TSEG DRAM memory BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory PCI Device 0 Offset B4h bits 31 20 BIOS must program TSEGMB to an 8 MB naturally aligned boundary B D F Type 0 0 0 PCI Address Offset B8 BBh Reset Value 00000000h Access RW L RW KL Size 32 bits BIOS Optimal Default 00000h
265. device associated with an Upstream Port the bit in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is of type RsvdP The Reset Value of this bit is Ob This bit is intended for debug compliance testing purposes System firmware and software is allowed to modify this bit only during debug or compliance testing Compliance SOS compsos When set to 1b the LTSSM is required to send SKP Ordered Sets periodically in between the modified compliance patterns For a Multi Function device associated with an 11 RWS Ob Powergood Upstream Port the bit in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is of type RsvdP The Reset Value of this bit is 0b Components that support only the 2 5 GT s speed are permitted to hardwire this field to Ob Enter Modified Compliance entermodcompliance When this bit is set to 1b the device transmits modified compliance pattern if the LTSSM enters Polling Compliance 10 RWS Ob Powergood State Components that support only the 2 5 GT s speed are permitted to hardwire this bit to Ob Reset Value of this field is Ob Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 DMIBAR Address Offset 98 99h Reset Value 0002h Access RWS RWS V Size 16 bits Bit Access sei RS Description 9 7 RW
266. dress Mask AM field in the Invalidation Address register Pa RO 000000 neers IVA_REG and IOTLB Invalidation Descriptor iotlb_inv_dsc This field is valid only when the PSI field in Capability register is reported as set Number of Fault recording Registers NFR Number of fault recording registers is computed as N 1 where N is the value reported in this field e 00000000 Implementations must support at least one fault recording 47 40 RO U b mene register NFR 0 for each remapping hardware unit in the platform The maximum number of fault recording registers per remapping hardware unit is 256 Page Selective Invalidation PSI 0 Hardware supports only domain and global invalidates for IOTLB 1 Hardware supports page selective domain and global 39 RO 0b RER invalidates for IOTLB Hardware implementations reporting this field as set are recommended to support a Maximum Address Mask Value MAMV value of at least 9 38 38 RO Oh Reserved RSVD Super Page Support SPS This field indicates the super page sizes supported by hardware A value of 1 in any of these bits indicates the corresponding super page size is supported The super page sizes corresponding to various bit positions within this field are 0 21 bit offset to page frame 2 MB 37 34 RO 0000b ao EES 1 30 bit offset to page frame 1 GB 2 39 bit offset to page frame 512 GB 3 48 bit offset to page frame 1 TB Hardware implementations supporting a specific super pa
267. dress in this range has a non memory destination The top of DRAM address space is either e TOLUD if there is less than 4 GB of DRAM or 32 bit addressing or e TOUUD if there is more than 4 GB of DRAM and 36 bit addressing The system address space includes the remapped range For instance if there is 8 GB of DRAM and 1 GB of PCI space the system has a 9 GB address space where DRAM lies from 0 3 GB and 4 9 GB BIOS will report an address space of 9 GB to the operating system Datasheet Volume 2 Processor Configuration Registers D t I H 2 3 5 2 3 6 Note PCI Express Configuration Address Space PCIEXBAR is located in Device 0 configuration space The processor detects memory accesses targeting PCIEXBAR BIOS must assign this address range such that it will not conflict with any other address ranges See the configuration portion of this document for more details PCI Express Graphics Attach PEG The processor can be programmed to direct memory accesses to a PCI Express interface When addresses are within either of two ranges specified using registers in each PEG s configuration space e The first range is controlled using the Memory Base MBASE register and Memory Limit MLIMIT register e The second range is controlled using the Pre fetchable Memory Base PMBASE register and Pre fetchable Memory Limit PMLIMIT register Conceptually address decoding for each range follows the same basic concept The top
268. e NERE When set this bit enables signaling of ERR_NONFATAL to the 1 RW Ob Uncore Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Correctable Error Reporting Enable CERE When set this bit enables signaling of ERR_CORR to the Root 0 RW Ob Uncore Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Datasheet Volume 2 189 Processor Configuration Registers intel 2 10 37 DSTS Device Status Register This register reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link B D F Type 0 6 0 PCI Address Offset AA ABh Reset Value 0000h Access RO RW1C Size 16 bits BIOS Optimal Default 0000h z Reset RST a Bit Access Value PWR Description 15 6 RO Oh Reserved RSVD Transactions Pending TP 0 All pending transactions including completions for any outstanding non posted requests on any used virtual 5 RO Ob ES e channel have been completed 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes Not Applicable or Implemented Hardwired to 0 4
269. e PWR Description 63 36 RO Oh Reserved RSVD f Remap Lim Remap Base register the Remap window is disabled 35 20 RUEL 9900h Ungore These Bits are Intel TXT lockable 19 1 RO Oh Reserved RSVD Lock LOCK 0 RW KL Ob Uncore This bit will lock all writeable settings in this register including itself 2 5 31 TOM Top of Memory Register This Register contains the size of physical memory BIOS determines the memory size reported to the OS using this Register B D F Type 0 0 0 PCI Address Offset AO A7h Reset Value 0000007FFFF00000h Access RW L RW KL Size 64 bits BIOS Optimal Default 00000000000h 2 Reset RST ee Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Top of Memory TOM This register reflects the total amount of populated physical memory This is NOT necessarily the highest main memory 2 RW L 7FFFFh address holes may exist in main memory address map due to 39 20 ancore addresses allocated for memory mapped IO These bits correspond to address bits 38 20 1 MB granularity Bits 19 0 are assumed to be 0 All the bits in this register are locked in Intel TXT mode 19 1 RO Oh Reserved RSVD Lock LOCK 0 RW KL Ob Uncore This bit will lock all writeable settings in this register including itself Datasheet Volume 2 77 intel 2 5 32 78 Processor Configuration Registers TOUUD Top of Upper Usable DRAM Register This 64
270. e in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR_CORR ERR_NONFATAL ERR_FATAL received by Root Port is controlled exclusively by Root Port Command Register B D F Type 0 6 0 PCI Address Offset A8 A9h Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh d Reset RST pa Bit Access Value PWR Description 15 RO Oh Reserved RSVD 14 12 RO 000b Uncore Reserved for Max Read Request Size MRRS 11 RO 0b Uncore Reserved for Enable No Snoop NSE 10 5 RO Oh Reserved RSVD 4 RO Ob Uncore Reserved for Enable Relaxed Ordering ROE Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked Unsupported Request UR An ERR_CORR is signaled 3 RW op Unicare when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register Fatal Error Reporting Enable FERE When set this bit enables signaling of ERR_FATAL to the Root 2 RW Ob Uncore Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Non Fatal Error Reporting Enabl
271. e overflow of fault recording 0 Rwics Ob Powergood registers Software writing 1 clears this field When this field is set hardware does not record any new faults until software clears this field Datasheet Volume 2 Processor Configuration Registers D 2 18 9 FECTL_REG Fault Event Control Register This register specifies the fault event interrupt message control bits B D F Type 0 0 0 GFXVTBAR Address Offset 38 3Bh Reset Value 80000000h Access RW RO V Size 32 bits BIOS Optimal Default 00000000h Reset RST SCH Bit Access Value PWR Description Interrupt Mask IM 0 No masking of interrupt When an interrupt condition is detected hardware issues an interrupt message using the 31 RW 1b Uncore Fault Event Data and Fault Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition which is defined as When primary fault logging is active an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in Fault Status register When advanced fault logging is active an interrupt condition occurs when hardware records a fault in the first fault record at index 0 of the curren
272. e read only with a value of Ob Reserved for Electromechanical Interlock Control EIC If an Electromechanical Interlock is implemented a write of 1b to 11 RO Ob Uncore this field causes the state of the interlock to toggle A write of Ob to this field has no effect A read to this register always returns a 0 Reserved for Power Controller Control PCC If a Power Controller is implemented this field when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to the slot or within the adapter In some cases the power 10 RO Ob Uncore controller may autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the Power Controller Control setting The defined encodings are 0 Power On 1 Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob then writes to this field have no effect and the read value of this field is undefined Reserved Power Indicator Control PIC If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflec
273. e receiving port 14 RW1C Signaled System Error SSE This bit is set when this Device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is 1 Both received if enabled by BCTRLi 1 and internally detected error messages do not affect this field Ob Uncore 13 RO Received Master Abort Status RMAS This bit is set when a Requester receives a Completion with Unsupported Request Completion Status On a Function with a Type 1 Configuration header the bit is set when the Unsupported Request is received by its Primary Side Not applicable There is No UR on primary interface Ob Uncore 12 RO Received Target Abort Status RTAS This bit is set when a Requester receives a Completion with Completer Abort Completion Status On a Function with a Type 1 Configuration header the bit is set when the Completer Abort is received by its Primary Side Reset Value of this bit is Ob Not Applicable or Implemented Hardwired to 0 The concept of a Completer abort does not exist on primary side of this device Ob Uncore 11 RO Signaled Target Abort Status STAS This bit is set when a Function completes a Posted or Non Posted Request as a Completer Abort error This applies to a Function with a Type 1 Configuration header when the Completer Abort was generated by its Primary Side Reset Value of this bit is Ob Not Applicable or Implem
274. e state of the Data Link Control and Management State Machine For a hot plug capable Downstream Port as indicated by the Hot Plug Capable field of the Slot Capabilities register this bit must be set to 1b For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob Note PCI Express Hot Plug is not supported on the processor Ob Uncore 19 RO Surprise Down Error Reporting Capable SDERC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob Ob Uncore 18 RO Clock Power Management CPM A value of 1b in this bit indicates that the component tolerates the removal of any reference clock s when the link is in the L1 and L2 3 Ready link states A value of Ob indicates the component does not have this capability and that reference clock s must not be removed in these link states This capability is applicable only in form factors that support clock request CLKREQ capability For a multi function device each function indicates its capability independently Power Management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit Ob Uncore 17 15 Datas
275. ead accesses are not supported from either DMI or PEG In the following sections it is assumed that all of the compatibility memory ranges reside on the DMI Interface The exception to this rule is VGA ranges which may be mapped to PCI Express DMI or to the internal graphics device IGD In the absence of more specific references cycle descriptions referencing PCI should be interpreted as the DMI Interface PCI while cycle descriptions referencing PCI Express or IGD are related to the PCI Express bus or the internal graphics device respectively The processor does not remap APIC or any other memory spaces above TOLUD Top of Low Usable DRAM The TOLUD register is set to the appropriate value by BIOS The remapbase remaplimit registers remap logical accesses bound for addresses above 4 GB onto physical addresses that fall within DRAM The Address Map includes a number of programmable ranges e Device 0 PXPEPBAR PxP egress port registers 4 KB window MCHBAR Memory mapped range for internal MCH registers 32 KB window DMIBAR This window is used to access registers associated with the processor PCH Serial Interconnect DMI register memory range 4 KB window GGC GMS Graphics Mode Select Used to select the amount of main memory that is pre allocated to support the internal graphics device in VGA non linear and Native linear modes 0 1 GB options GGC GGMS GTT Graphics Memory Size Used to select
276. ear it while writing a 1 to a bit has no effect Hardware sets these bits RWIS Read Write 1 to Set These bits can be read and set by software Writing a 1 to a bit will set it while writing a 0 to a bit has no effect Hardware clears these bits RsvdP Reserved and Preserved These bits are reserved for future RW implementations and their value must not be modified by software When writing to these bits software must preserve the value read When software updates a register that has RsvdP fields it must read the register value first so that the appropriate merge between the RsvdP and updated fields will occur RsvdZ Reserved and Zero These bits are reserved for future RW1C implementations Software must use 0 for writes WO Write Only These bits can only be written by software reads return zero Note Use of this attribute type is deprecated and can only be used to describe bits without persistent state RC Read Clear These bits can only be read by software but a read causes the bits to be cleared Hardware sets these bits Note Use of this attribute type is only allowed on legacy functions as side effects on reads are not desirable RSW1C Read Set Write 1 to Clear These bits can be read and cleared by software Reading a bit will set the bit to 1 Writing a 1 to a bit will clear it while writing a 0 to a bit has no effect RCW Read Clear
277. ect to remapping or not at all Hardware implementations supporting DMA draining must drain any in flight DMA read write requests queued within the Root Complex before completing the translation enable command and reflecting the status of the command through the TES field in the Global Status register The value returned on a read of this field is undefined Datasheet Volume 2 267 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 GFXVTBAR 18 1Bh 00000000h RO WO 32 bits 000000h Bit Access Reset Value RST PWR Description 30 WO Ob Uncore Set Root Table Pointer SRTP Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified through the Root entry Table Address RTA_REG register Hardware reports the status of the Set Root Table Pointer operation through the RTPS field in the Global Status register The Set Root Table Pointer operation must be performed before enabling or re enabling after disabling DMA remapping through the TE field After a Set Root Table Pointer operation software must globally invalidate the context cache and then globally invalidate of IOTLB This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer and not stale cached entries While DMA remapping
278. ed RSVD Link Autonomous Bandwidth Interrupt Enable LABIE When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to 0b 11 RW 0b Uncore Link Bandwidth Management Interrupt Enable LBMIE Link Bandwidth Management Interrupt Enable When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches 10 RW 0b Uncore Hardware Autonomous Width Disable HAWD When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob 9 RW Ob Uncore Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as follows 0 Clock power management is disabled and device must hold CLKREQ signal low 1 When this bit is set to 1 the device is permitted t
279. efficients during Equalization Default is 20d A Note All equalization presets coefficients have been calculated SS RW aah Uncorg using the default LF value of 20d If LF is changed the preset tables located in EQPRESET registers may need to be re programmed to fulfill LF Cmi CO Cpi gt LF 19 16 RO Oh Reserved RSVD Bypass Phase 2 Equalization EQPH2BYP 15 RW Ob Uncore If set after Phase 1 is complete the LTSSM will bypass Phase 2 and 3 of equalization Bypass Phase 3 Equalization EQPH3BYP 14 RW 1b Uncore If set after Phase 2 is complete the LTSSM will bypass Phase 3 of equalization and go back to Recovery RcvrLock Disable Margining MARGINDIS 13 RW Ob Uncore When set it will disable Tx margining during Polling Compliance and Recovery 12 8 RO Oh Reserved RSVD Gen3 Bypass Levels G3BYPLVL If this bit is set the Tx Eq Levels will be bypassed only during Gen3 The values of the bypass levels are found in the port e RW Ob Uncore EQBYPLVLBND registers When this bit is set Phase 2 and Phase 3 equalization is expected to be bypassed Global Bypass Levels GLBBYPLVL If this bit is set the Tx Eq Levels will be bypassed for all speeds The values of the bypass levels are found in the port 6 RN Ob Uncore EQBYPLVLBND registers When this bit is set Phase 2 and Phase 3 equalization is expected to be bypassed 146 Datasheet Volume 2 Processor Configuration Registers
280. egister This register will have the minimum Read Return Tracker credits for each of the PEG DMI GSA streams B D F Type 0 0 0 MCHBAR IMPH Address Offset 740C 740Fh Reset Value B1i24F85ih Access RW L Size 32 bits F Reset RST Se Bit Access Value PWR Description i GSA VC1 Minimum Completion Credits GSAVC1 SH RUGE ER Ungore Minimum number of credits for GSA VC1 completions GSA VCO Minimum Completion Credits GSAVCO CES RWAL th uncorg Minimum number of credits for GSA VCO completions PEG60 VCO Minimum Completion Credits PEG60VCO SE Kee th Wii Minimum number of credits for PEG60 VCO completions i PEG12 VCO Minimum Completion Credits PEG12VC0 one Auk th Uncore Minimum number of credits for PEG12 VCO completions PEG11 VCO Minimum Completion Credits PEG11VC0 wets AMIE th Ungore Minimum number of credits for PEG11 VCO completions PEG10 VCO Minimum Completion Credits PEG10VCO peeks SE 7h uncorg Minimum number of credits for PEG10 VCO completions S DMI VC1 Minimum Completion Credits DMIVC1 SE RWE ah Uncore Minimum number of credits for DMI VC1 completions i DMI VCm Minimum Completion Credits DMIVCM SS SE th SES Minimum number of credits for DMI VCm completions i DMI VCp Minimum Completion Credits DMIVCP ae SE 2h Unicore Minimum number of credits for DMI VCp completions DMI VCO Minimum Completion Credits DMIVCO om SR th Ungore Minimum number of credits for DMI VCO completio
281. egisters Access Size B D F Type Address Offset Reset Value 0 6 0 PCI 3E 3Fh 0000h RO RW 16 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description RW Ob Uncore Secondary Bus Reset SRESET Setting this bit triggers a hot reset on the corresponding PCI Express Port This will force the LTSSM to transition to the Hot Reset state using Recovery from LO LOs or L1 states RO Ob Uncore Master Abort Mode MAMODE Does not apply to PCI Express Hardwired to 0 RW Ob Uncore VGA 16 bit Decode VGA16D Enables the PCI to PCI bridge to provide 16 bit decoding of VGA I O address precluding the decoding of alias addresses every 1 KB This bit only has meaning if bit 3 VGA Enable of this register is also set to 1 enabling VGA I O decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA I O accesses 1 Execute 16 bit address decodes on VGA I O accesses RW Ob Uncore VGA Enable VGAEN Controls the routing of processor initiated transactions targeting VGA compatible I O and memory address ranges See the VGAEN MDAP table in device 0 offset 97h 0 RW Ob Uncore ISA Enable ISAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the root port to an I O access issued by the processor that target ISA I O addresses This applies only to I O addresses th
282. egment is Read Only Access Size B D F Type Address Offset Reset Value 0 0 0 PCI 84h 00h RW 8 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 7 6 RO Oh Reserved RSVD 5 4 RW 00b Uncore ODCOOO ODFFFF Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from ODCOOOh to ODFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO Oh Reserved RSVD 1 0 RW 00b Uncore OD8000 ODBFFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OD8000h to ODBFFFh 00 DRAM Disabled All reads are sent to DRAM All writes are forwarded to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 69 Processor Configuration Registers 2 5 26 PAM5 Programmable Attribute Map 5 Register Thi
283. ented Hardwired to 0 The concept of a target abort does not exist on primary side of this device Ob Uncore RO DEVSELB Timing DEVT This device is not the subtractively decoded device on bus 0 This 00b Uncore bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode Does not apply to PCI Express and must be hardwired to 00b 166 Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 6 0 PCI Address Offset 6 7h Reset Value 0010h Access RW1C RO RO V Size 16 bits BIOS Optimal Default Oh Reset RST Value PWR Description Bit Access Master Data Parity Error PMDPE This bit is set by a Requester Primary Side for Type 1 Configuration Space header Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs e Requester receives a Completion marked poisoned 8 RW1C Ob Uncore e Requester poisons a write Request If the Parity Error Response bit is Ob this bit is never set Reset Value of this bit is Ob This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned peer 2 peer posted forwarded will not set this bit They are reported at the receiving port Fast Back to Back FB2B g SS 0b negre Not Applicable or Implemented Hardwired to 0 6 RO Oh Reserved RSVD 66 60MHz capability CAP66 5 RO
284. eo capture card can send video capture data writes directly into the frame buffer on an external graphics card writes to the PEG port As a result peer writes from DMI to PEG must be supported I O cycles and configuration cycles are not supported in the upstream direction The result will be an unsupported request completion status Datasheet Volume 2 39 DN t Processor Configuration Registers 2 3 13 1 1 40 DMI Interface Accesses to the processor that Cross Device Boundaries The processor does not support transactions that cross device boundaries This should never occur because PCI Express transactions are not allowed to cross a 4 KB boundary For reads the processor will provide separate completion status for each naturally aligned 64 byte block or if chaining is enabled each 128 byte block If the starting address of a transaction hits a valid address the portion of a request that hits that target device PCI Express or DRAM will complete normally If the starting transaction address hits an invalid address the entire transaction will be remapped to address 000C_0000h and dispatched to DRAM A single unsupported request completion will result TC VC Mapping Details 1 VCO enabled by default a Snoop port and Non snoop Asynchronous transactions are supported b Internal Graphics GMADR writes can occur These will NOT be snooped regardless of the snoop not required SNR bit c Internal Graphics GMADR reads
285. er B D F Type 0 1 0 2 PCI Address Offset C4 C7h Reset Value 00000800h Access RO RW O Size 32 bits BIOS Optimal Default 0000000h z Reset RST Ge Bit Access Value PWR Description 31 12 RO Oh Reserved RSVD Latency Tolerance and BW reporting Mechanism Supported LTRS A value of 1b indicates support for the optional Latency Tolerance amp Bandwidth Requirement Reporting LTBWR mechanism capability 11 RO ib Uncore Root Ports Switches and Endpoints are permitted to implement this capability For Switches that implement LTBWR this bit must be set only at the upstream port For a multi Function device each Function must report the same value for this bit For Bridges Downstream Ports and components that do not implement this capability this bit must be hardwired to Ob 10 6 RO Oh Reserved RSVD ARI Forwarding Supported ARIFS Applicable only to Switch Downstream Ports and Root Ports must 5 RW O Ob Uncore be Ob for other Function types This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability Completion Time out Disabled Supported CTODS A value of 1b indicates support for the Completion Timeout Disable mechanism The Completion Timeout Disable mechanism is required for 4 RO Ob Uncore Endpoints that issue Requests on their own behalf and PCI Express to PCI PCI X Bridges that take ownership of Requests issued on PCI Express This mechanism is op
286. er Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ Primary Pending Fault PPF This field indicates if there are one or more pending faults logged in the fault recording registers Hardware computes this field as the logical OR of Fault F fields across all the fault recording registers of this remapping hardware unit 1 ROS V Ob Powergood 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The FRI field is updated by hardware whenever the PPF field is set by hardware Also depending on the programming of Fault Event Control register a fault event is generated when hardware sets this field Primary Fault Overflow PFO Hardware sets this field to indicate overflow of fault recording 0 RW1CS Ob Powergood registers Software writing 1 clears this field When this field is set hardware does not record any new faults until software clears this field Datasheet Volume 2 325 intel Processor Configuration Registers 2 21 9 FECTL_REG Fault Event Control Register This register specifies the fault event interrupt message control bits Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 VCOPREMAP 38 3Bh 80000000h RW RO V 32 bits 00000000h Bit Access Reset Value RST PWR Description 31 RW 1
287. ermine whether a memory thermal interrupt is to be generated or not B D F Type 0 0 0 MCHBAR PCU Address Offset 58A8 58ABh Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 00000000h o Reset RST ae Bit Access Value PWR Description 31 5 RO Oh Reserved RSVD 4 RW Ob Reserved RSVD 3 RO Oh Reserved RSVD Hot Threshold Interrupt Enable HOT_THRESHOLD_INT_ENABLE 2 RW ob Drs This bit controls the generation of a thermal interrupt whenever the Hot Threshold temperature is crossed 1 RO Oh Reserved RSVD Warm Threshold Interrupt Enable WARM_THRESHOLD_INT_ENABLE o RW Ob Uricore This bit controls the generation of a thermal interrupt whenever the Warm Threshold temperature is crossed 300 Datasheet Volume 2 Processor Configuration Registers intel 2 19 6 GT_PERF_STATUS GT Performance Status Register This register provides the P state encoding for the Secondary Power Plane s current PLL frequency and the current VID B D F Type 0 0 0 MCHBAR PCU Address Offset 5948 594Bh Reset Value 00000000h Access RO V Size 32 bits BIOS Optimal Default 0000h 5 Reset RST iias Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD RP State Ratio RP_STATE_RATIO 13 8 SE gon Ungore This field provides the ratio of the current RP state 7 0 RO V 00h Reserved RSVD 2 19 7 RP_STATE_LIMITS RP State Limitations Register
288. es whereas the maximum delay is 7 cycles 2 14 3 SC_IO_LATENCY_Ci I0 Latency configuration Register This register identifies the I O latency per rank and I O compensation global B D F Type 0 0 0 MCHBAR MC1 Address Offset 4428 442Bh Reset Value DOOEOOOOh Access RW L Size 32 bits BIOS Optimal Default 00h Reset RST GL Bit Access Value PWR Description 31 22 RO Oh Reserved RSVD 21 16 RW L OEh Uncore Round trip I O compensation RT_IOCOMP 15 12 RW L Oh Uncore IO latency Rank 1 DIMM 1 IOLAT_R1D1 11 8 RW L Oh Uncore IO latency Rank O DIMM 1 IOLAT_ROD1 7 4 RW L Oh Uncore IO latency Rank 1 DIMM O IOLAT_R1D0 3 0 RW L Oh Uncore IO latency Rank Oo DIMM O IOLAT_RODO Datasheet Volume 2 247 intel 2 14 4 248 Processor Configuration Registers PM_PDWN_ config_C1 Power down Configuration Register This register defines the power down CKE off operation power down mode idle timer and global per rank decision B D F Type 0 0 0 MCHBAR MC1 Address Offset 44B0 44B3h Reset Value 00000000h Access RW L Size 32 bits BIOS Optimal Default 00000h Bit Access enee A Description 31 13 RO Oh Reserved RSVD Global power down GLPDN 12 RW L Ob Uncore 1 Power down decision is global for channel 0 Separate decision is taken for each rank Power down mode PDWN_mode Selects the mode of power down Oh No Po
289. es to complete the transition from LOs to LO 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 14 12 RO V 100b Uncore 011 256 ns to less than 512 ns 100 512 ns to less than 1 us 101 1 us to less than 2 us 110 2 us 4 us 111 More than 4 us The actual value of this field depends on the common Clock Configuration bit LCTL 6 and the Common and Non Common clock LOs Exit Latency values in LOSLAT Offset 22Ch Active State Link PM Support ASLPMS 11 10 RW O 11 5 uncore Root port supports ASPM LOs and L1 9 0 RO Oh Reserved RSVD Datasheet Volume 2 116 Processor Configuration Registers LCTL Link Control Register This register allows control of PCI Express link Access Size B D F Type Address Offset Reset Value 0 1 0 2 PCI BO Bih 0000h RW RO RW V 16 bits BIOS Optimal Default 00h Bit Access Reset RST Value PWR Description 15 12 RO Oh Reserved RSVD 11 RW Link Autonomous Bandwidth Interrupt Enable LABIE When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob Ob Uncore 10 RW Link Bandwidth Management
290. ess Offset 1A 1Bh Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h e Reset RST ear Bit Access Value PWR Description 15 2 RO Oh Reserved RSVD Virtual Channel 0 Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control 1 RO V 1 initialization It is set by default on Reset as well as whenever neers the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state BIOS Requirement Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Oh Reserved RSVD 2 12 8 DMIVCi1RCAP DMI VC1 Resource Capability Register B D F Type 0 0 0 DMIBAR Address Offset 1C 1Fh Reset Value 00008001h Access RO Size 32 bits BIOS Optimal Default 00h z Reset RST an Bit Access Value PWR Description 31 24 RO 00h Uncore Reserved for Port Arbitration Table Offset PATO 23 RO Oh Reserved RSVD 22 16 RO 00h Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions REJSNPT 0 Transactions with or without the No Snoop bit set within the 15 RO 1b Uncore TLP header are allowed on this VC 1 When set any transaction for which the No S
291. et Value 00000000h Access RW L Size 32 bits Reset RST Bit Access Description Value PWR Message Upper Address MUA Hardware implementations supporting Queued Invalidations and 31 0 RW L 00000000h Uncore Extended Interrupt Mode are required to implement this register Hardware implementations not supporting Queued Invalidations or Extended Interrupt Mode may treat this field as RsvdZ 2 18 27 IRTA_REG Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table This register is treated as RsvdZ by implementations reporting Interrupt Remapping IR as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset B8 BFh Reset Value 0000000000000000h Access RW L Size 64 bits BIOS Optimal Default 00000000h e Reset RST GC Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Interrupt Remapping Table Address IRTA This field points to the base of 4 KB aligned interrupt remapping table Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Reads of this field returns value that was last programmed to it 38 12 RW L 0000000h Uncore 11 4 RO Oh Reserved RSVD Size S 3 0 RW L Oh Uncore This field specifies the size of the interrupt remapping table The number of entries in the interrupt remapping table is 2 X 1 where X is the value progr
292. et if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change 14 RW1C Ob Uncore Link Bandwidth Management Status LBWMS This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status e A link retraining initiated by a write of 1b to the Retrain Link bit has completed Note This bit is set following any write of 1b to the Retrain Link bit including when the Link is in the process of retraining for some other reason e Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an LTSSM time out or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change 13 Ob Uncore Data Link Layer Link Active Optional DLLLA This bit indicates the status of the Data Link Control and Management State Machine It returns a 1b to indicate the DL_Active state Ob otherwise This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob 12 RO 1b Uncore Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the presence of a reference on the connec
293. f power management registers implemented and that this device complies with revision 1 1 of the PCI Power Management Interface Specification 15 8 RO V 90h Uncore Pointer to Next Capability PNC This contains a pointer to the next item in the capabilities list If MSICH CAPL 0 7Fh is 0 then the next item in the capabilities list is the Message Signaled Interrupts MSI capability at 90h If MSICH CAPL 0 7Fh is 1 then the next item in the capabilities list is the PCI Express capability at AOh 7 0 RO Oih Uncore Capability ID CID Value of O1h identifies this linked list item capability structure as being for PCI Power Management registers Datasheet Volume 2 181 intel Processor Configuration Registers 2 10 26 PM_CS Power Management Control Status Register 182 B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 6 0 PCI 84 87h 00000008h RO RW 32 bits 000000h Bit Access Reset Value RST PWR Description 31 16 RO Oh Reserved RSVD 15 RO Ob Uncore PME Status PMESTS This bit indicates that this device does not support PME generation from D3cold 14 13 RO 00b Uncore Data Scale DSCALE This field indicates that this device does not support the power management data register RO Oh Uncore Data Select DSEL This field indicates tha
294. fer Flush WBF This bit is valid only for implementations requiring write buffer flushing Software sets this field to request that hardware flush the Root Complex internal write buffers This is done to ensure any updates to the memory resident remapping structures are not held in any internal write posting buffers Hardware reports the status of the write buffer flushing operation through the WBFS field in the Global Status register Clearing this bit has no effect The value returned on a read of this field is undefined 26 WO Ob Uncore Queued Invalidation Enable QIE This field is valid only for implementations supporting queued invalidations Software writes to this field to enable or disable queued invalidations 0 Disable queued invalidations 1 Enable use of queued invalidations Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register The value returned on a read of this field is undefined 25 WO Ob Uncore Interrupt Remapping Enable IRE This field is valid only for implementations supporting interrupt remapping 0 Disable interrupt remapping hardware 1 Enable interrupt remapping hardware Hardware reports the status of the interrupt remapping enable operation through the IRES field in the Global Status register There may be active interrupt requests in the platform when software updates this fiel
295. fied in the DID field 11 Page selective invalidation request The target address mask and invalidation hint must be specified in the Invalidate Address register and the domain id must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the IVT field At this time the granularity at which actual invalidation was performed is reported through the IAIG field 61 60 RW Oh Uncore 59 59 RO Oh Reserved RSVD Datasheet Volume 2 291 292 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 0 0 GFXVTBAR 108 10Fh 0200000000000000h RO V RW RW V 64 bits 0000000000000h Bit Access Reset Value RST PWR Description 58 57 RO V ih Uncore IOTLB Actual Invalidation Granularity IAIG Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion by clearing the IVT field The following are the encodings for this field 00 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for p
296. from LO LOs or Li states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no need to write a 0 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 DMIBAR Address Offset 88 89h Reset Value 0000h Access RW RW V Size 16 bits BIOS Optimal Default 0000h 3 Reset RST Pare Bit Access Value PWR Description Link Disable LD 0 Normal operation 1 link is disabled Forces the LTSSM to transition to the Disabled state using Recovery from LO LOs or L1 states Link retraining happens automatically on 0 to 1 transition 4 RW Ob Uncore just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state After clearing this bit software must honor timing requirements defined in Section 6 6 1 with respect to the first Configuration Read following a Conventional Reset Read Completion Boundary RCB S RO op SR Hardwired to 0 to indicate 64 byte 2 RO Oh Reserved RSVD Active State PM ASPM This field controls the level of active state power management supported on the given link 1 0 RW 00b Uncore 00 Disabled 01 LOs Entry Supported 10 Reserved 11 LOs and Li Entry Supported 2 12 26 LSTS DMI Link Status Register This register indicates DMI status B D F Type 0 0 0 DMIBAR Address Offset 8A 8Bh Reset Value oooih Access RO
297. g IP Hardware sets the IP field whenever it detects an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF field set completed setting the IWC field in the Invalidation Completion Status register e If the IWC field in the Invalidation Completion Status register was already set at the time of setting this field it is not treated as a new interrupt condition The IP field is kept set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field e Software servicing the IWC field in the Invalidation Completion Status register 29 0 RO Oh Reserved RSVD Datasheet Volume 2 287 Processor Configuration Registers intel 2 18 24 IEDATA_REG Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F
298. g of read and write cycles that address the BIOS area from O0C_4000h to OC_7FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW 00b Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO Oh Reserved RSVD 0CO000 OC3FFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OC0000h to OC3FFFh 00 DRAM Disabled All reads are sent to DRAM All writes are forwarded to DMI j 01 Read Only All reads are sent to DRAM All writes are 10 RW SE Seefe forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 66 Datasheet Volume 2 Processor Configuration Registers intel 2 5 23 PAM2 Programmable Attribute Map 2 Register This register controls the read write and shadowing attributes of the BIOS range from C_8000h to C_FFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR regi
299. ge size must support all smaller super page sizes that is only valid values for this field are 0001b 0011b 0111b 1111b Datasheet Volume 2 Processor Configuration Registers Size B D F Type Address Offset Reset Value Access 0 0 0 GFXVTBAR 8 Fh 00C0000020E60262h RO 64 bits BIOS Optimal Default 000h Bit Access Reset Value RST PWR Description 33 24 RO 020h Uncore Fault recording Register offset FRO This field specifies the location to the first fault recording register relative to the register base address of this remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first fault recording register is calculated as X 16 Y 23 RO 1b Uncore Isochrony ISOCH 0 Remapping hardware unit has no critical isochronous requesters in its scope 1 Remapping hardware unit has one or more critical isochronous requesters in its scope To ensure isochronous performance software must ensure invalidation operations do not impact active DMA streams from such requesters This implies when DMA is active software performs page selective invalidations and not coarser invalidations 22 RO 1b Uncore Zero Length Read ZLR 0 Remapping hardware unit blocks and treats as fault zero length DMA read requests to write only pages 1 Remapping hardware unit supports zer
300. gions are blocked e DMA requests that are subject to address remapping and accessing the protected memory regions may or may not be blocked by hardware For such requests software must not depend on hardware protection of the protected memory regions and instead program the DMA remapping page tables to not allow DMA to protected memory regions Remapping hardware access to the remapping structures are not subject to protected memory region checks DMA requests blocked due to protected memory region violation are not recorded or reported as remapping faults Hardware reports the status of the protected memory enable disable operation through the PRS field in this register Hardware implementations supporting DMA draining must drain any in flight translated DMA requests queued within the Root Complex before indicating the protected memory region as enabled through the PRS field 30 1 RO Oh Reserved RSVD RO V Oh Uncore Protected Region Status PRS This field indicates the status of protected memory regions 0 Protected memory region s disabled 1 Protected memory region s enabled Datasheet Volume 2 329 DN t Processor Configuration Registers 2 21 15 330 PLMBASE_REG Protected Low Memory Base Register This register sets up the base address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN
301. gister ccceceeeceee eee e ee eee eens eens eeeeeeeaeaees 121 2 6 43 SLOTSTS Slot Status Register SKS KNR SNE NEN a REESEN EEN NEN ENEE NN 123 2 6 44 RCTL ROOt Control Registe ee EEN inna REENEN EES ENESENN NEE ENEE 125 2 6 45 RSTS ROOt Status REGISEM eege BEE bit teat ege 126 2 6 46 DCAP2 Device Capabilities 2 Register 127 2 6 47 DCTL2 Device Control 2 ReGiSter cceeeeeeeee teeta tees eee eee diuisa eeeeae 128 2 6 48 LCAP2 Link Capabilities 2 Register ccceeeeeece cece eee teens eee eeeeeeeanaeaes 129 2 6 49 LCTL2 Link Control 2 Register cceceeee cece e reece teeta ee ee eaten niedi 129 2 6 50 LSTS2 Link Status 2 Register SEENEN cna RE EE REENEN EEN NENNEN 131 2 7 PCI Device 1 Function 0 2 Extended Configuration Reglsters ees 132 2 7 1 PVCCAP1 Port VC Capability Register 1 133 2 7 2 PVCCAP2 Port VC Capability Register 2 133 2 7 3 PVCCTL Port VC Control Register ee keNNSET KEE NE ENER tee saedadenen aise 134 2 7 4 VCORCAP VCO Resource Capability Register 135 2 7 5 VCORCTL VCO Resource Control Register 136 2 7 6 VCORSTS VCO Resource Status Register cccceeee cess eee ee eee eee eee eee nae 137 2 7 7 PEG_TC PCI Express Completion Timeout Register 137 2 7 8 EQCTLO_1 Lane 0 1 Equalization Control Register 138 2 7 9 EQCTL2_3 Lane 2 3 Equalization Control Register 139 2 7 10 EQCTL4_5 Lane 4 5 Equalization Control Register 140 2 7 11 EQCTL6_7 Lane
302. h Access RO Size 24 bits Bit Access ere ct Description Base Class Code BCC 23 16 RO 06h Uncore This field indicates the base class code for this device This code has the value 06h indicating a Bridge device Sub Class Code SUBCC 15 8 RO 04h Uncore This field indicates the sub class code for this device The code is 04h indicating a PCI to PCI Bridge Programming Interface PI 7 0 RO 00h Uncore This field indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device 2 6 7 CL Cache Line Size Register B D F Type 0 1 0 2 PCI Address Offset Ch Reset Value 00h Access RW Size 8 bits Bit Access PE Gi Description Cache Line Size CLS 7 0 RW 00h Uncore Implemented by PCI Express devices as a read write field for legacy compatibility purposes but has no impact on any PCI Express device functionality 92 Datasheet Volume 2 Processor Configuration Registers intel 2 6 8 HDR Header Type Register This register identifies the header layout of the configuration space No physical register exists at this location B D F Type 0 1 0 2 PCI Address Offset Eh Reset Value 81h Access RO Size 8 bits e Reset RST Sage Bit Access Value PWR Description Header Type Register HDR Device 1 returns 81h
303. h PM_PDWN_config Power down configuration register 00000000h RW L 44BC 44C7h RSVD Reserved Oh RO 44D0 4693h RSVD Reserved 4694 4697h TC_RFP_C1 Refresh parameters 0000980Fh RW L 4698 469Bh TC_RFTP_C1 Refresh timing parameters 46B41004h RW L 469C 469Fh RSVD Reserved 00000000h RW L 46A0 46A3h RSVD Reserved 00000000h RW L 46A4 46A7h TC_SRFTP_C1 Self Refresh Timing Parameters 0100B200h RW L 46A8 478Fh RSVD Reserved 2 14 1 TC_DBP_C1 Timing of DDR Bin Parameters Register This register defines the BIN timing parameters for safe logic tRCD tRP tCL tWCL and tRAS B D F Type 0 0 0 MCHBAR MCL Address Offset 4400 4403h Reset Value 00146666h Access RW L Size 32 bits BIOS Optimal Default 00h Reset RST Pare Bit Access Value PWR Description 31 24 RO Oh Reserved RSVD i 8 tRAS in DCLK cycles tRAS 23 16 SEH tai ungorg Minimum ACT to PRE timing Range is 10 to 40 DCLK cycles Write CAS latency in DCLK cycles tWCL e d Delay from CAS WR command to data valid on DDR pins Range 15 12 RWL Gh Ungore is 5 15 The value 5 should not be programmed if the DEC_WRD bit in TC_RWP register is set Datasheet Volume 2 245 Processor Configuration Registers B D F Type 0 0 0 MCHBAR MC1 Address Offset 4400 4403h Reset Value 00146666h Access RW L Size 32 bits BIOS Optimal Default 00h 2 Reset RST ae Bit Access Value PWR Description CAS latency in DCLK cycles tCL Delay from CAS
304. h RO AO Aih PEG_CAPL PCI Express G Capability List 0010h RO A2 A3h PEG_CAP PCI Express G Capabilities 0142h RO RW O A4 A7h DCAP Device Capabilities 00008000h RO RW O A8 A9h DCTL Device Control 0000h RO RW AA ABh DSTS Device Status 0000h RO RWiC Link Capabilities RO RW O RO AC AFh LCAP 0521CC42h V RW OV BO Bih LCTL Link Control 0000h RO RW RW V B2 B3h LSTS Link Status 1001h RW LC RO3M B4 B7h SLOTCAP Slot Capabilities 00040000h RW O RO B8 B9h SLOTCTL Slot Control 0000h RO Slot Status RO RO V BA BBh SLOTSTS 0000h RW1C BC BDh RCTL Root Control 0000h RW RO BE CBh RSVD Reserved CC CFh LCAP2 Link Capabilities 2 00000006h RO V DO Dih RSVD Reserved 0002h RWS RWS V 2 10 1 vID Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device B D F Type 0 6 0 PCI Address Offset 0 1h Reset Value 8086h Access RO Size 16 bits i Reset RST WH Bit Access Value PWR Description i Vendor Identification VID SS RO sogeh uncore PCI standard identification for Intel 162 Datasheet Volume 2 Processor Configuration Registers intel 2 10 2 DID Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 6 0 PCI Address Offset 2 3h Reset Value 015Dh Access RO FW Size 16 bits Reset RST a Bit Access Value PWR
305. h the Root entry Table Address RTA_REG register Hardware reports the status of the Set Root Table Pointer operation through the RTPS field in the Global Status register The Set Root Table Pointer operation must be performed before enabling or re enabling after disabling DMA remapping through the TE field After a Set Root Table Pointer operation software must globally invalidate the context cache and then globally invalidate of IOTLB This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer and not stale cached entries While DMA remapping hardware is active software may update the root table pointer through this field However to ensure valid in flight DMA requests are deterministically remapped software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer Clearing this bit has no effect The value returned on read of this field is undefined 29 RO Ob Uncore Set Fault Log SFL This field is valid only for implementations supporting advanced fault logging Software sets this field to request hardware to set update the fault log pointer used by hardware The fault log pointer is specified through Advanced Fault Log register Hardware reports the status of the Set Fault Log operation through the FLS field in the Glo
306. hardware is active software may update the root table pointer through this field However to ensure valid in flight DMA requests are deterministically remapped software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer Clearing this bit has no effect The value returned on read of this field is undefined 29 RO Ob Uncore Set Fault Log SFL This field is valid only for implementations supporting advanced fault logging Software sets this field to request hardware to set update the fault log pointer used by hardware The fault log pointer is specified through Advanced Fault Log register Hardware reports the status of the Set Fault Log operation through the FLS field in the Global Status register The fault log pointer must be set before enabling advanced fault logging through EAFL field Once advanced fault logging is enabled the fault log pointer may be updated through this field while DMA remapping is active Clearing this bit has no effect The value returned on read of this field is undefined 28 RO Ob Uncore Enable Advanced Fault Logging EAFL This field is valid only for implementations supporting advanced fault logging Software writes to this field to request hardware to enable or disable advanced fault logging 0 Disable adva
307. he Bits in this register are locked in Intel TXT mode This register must be 1 MB aligned when reclaim is enabled 19 1 RO Oh Reserved RSVD Lock LOCK 0 RW KL Ob Uncore This bit will lock all writeable settings in this register including itself 2 5 37 SKPD Scratchpad Data Register This register holds 32 writable bits with no functionality behind them It is for the convenience of BIOS and graphics drivers B D F Type 0 0 0 PCI Address Offset DC DFh Reset Value 00000000h Access RW Size 32 bits r Reset RST SA Bit Access Value PWR Description Scratchpad Data SKPD 31 0 RW 00000000h Uncore 1 DWord of data storage Datasheet Volume 2 81 intel Processor Configuration Registers 2 5 38 CAPIDO_A Capabilities A Register This register control of bits in this register are only required for customer visible SKU differentiation B D F Type 0 0 0 PCI Address Offset E4 E7h Reset Value 00000000h Access RO FW RO KFW Size 32 bits BIOS Optimal Default 000000h 5 Reset RST St Bit Access Value PWR Description 31 RO KFW Ob Reserved RSVD 30 RO KFW Ob Reserved RSVD 29 RO KFW Ob Reserved RSVD 28 RO KFW Ob Reserved RSVD 27 RO FW Ob Reserved RSVD 26 RO FW Ob Reserved RSVD 25 RO FW Ob Uncore Reserved 24 RO FW Ob Reserved RSVD VTd Disable VTDD 23 RO KF
308. he logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power 6 RO V Ob Uncore be applied to an adapter for its presence to be detected Consequently form factors that require a power controller for hot plug must implement a physical pin presence detect mechanism 0 Slot Empty 1 Card Present in slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to slots where the Slot Implemented bit of the PCI Express Capabilities Register is 0b this bit must return 1b Reserved for MRL Sensor State MSS This register reports the status of the MRL sensor if it is 5 RO 0b Uncore implemented 0 MRL Closed 1 MRL Open Reserved for Command Completed CC If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register this bit is set when a hot plug command has completed and the Hot Plug Controller is ready to accept a subsequent command The Command Completed status bit is set as an S RO Ob Ungore indication to host software that the Hot Plug Controller has processed the previous command and is ready to receive the next command it provides no assurance that the action corresponding to the command is complete If Comm
309. he value programmed in this register and greater than 4 GB All the bits in this register are locked in Intel TXT mode 19 1 RO Oh Reserved RSVD Lock LOCK 0 RW KL Ob Uncore This bit will lock all writeable settings in this register including itself Datasheet Volume 2 Processor Configuration Registers intel 2 5 33 BDSM Base Data of Stolen Memory Register This register contains the base address of graphics data stolen DRAM memory BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size PCI Device 0 offset 52 bits 7 4 from TOLUD PCI Device 0 offset BCh bits 31 20 B D F Type 0 0 0 PCI Address Offset BO B3h Reset Value 00000000h Access RW KL RW L Size 32 bits BIOS Optimal Default 00000h s R t RST Geo Bit Access rte G Description Graphics Base of Stolen Memory BDSM This register contains bits 31 20 of the base address of stolen 31 20 RW L 000h Uncore DRAM memory BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size PCI Device 0 offset 52 bits 6 4 from TOLUD PCI Device 0 offset BCh bits 31 20 19 1 RO Reserved RSVD Lock LOCK 0 RW KL Uncore This bit will lock all writeable settings in this register including itself 2 5 34 BGSM Base of GTT Stolen Memory Register This register contains the base address of stolen DRAM memory for the GTT BIOS
310. heet Volume 2 RO Oh Reserved RSVD 191 192 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset AC AFh Reset Value 0521CC42h Access RO RW O RO V RW OV Size 32 bits BIOS Optimal Default Oh Bit Access ee i Description LOs Exit Latency LOSELAT This field indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 14 12 RO V 100b Uncore 011 256 ns to less than 512 ns 100 512 ns to less than 1 us 101 1 us to less than 2 us 110 2 us 4 us 111 More than 4 us The actual value of this field depends on the common Clock Configuration bit LCTL 6 and the Common and Non Common clock LOs Exit Latency values in LOSLAT Offset 22Ch r Active State Link PM Support ASLPMS Kee RWO SS uneore Root port supports ASPM LOs and L1 Max Link Width MLW 9 4 RW OV 04h Uncore This field indicates the maximum number of lanes supported for this link 3 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D 2 10 39 LCTL Link Control Register This register allows control of PCI Express link B D F Type 0 6 0 PCI Address Offset BO Bih Reset Value 0000h Access RO RW RW V Size 16 bits BIOS Optimal Default 00h Reset RST Bit Access Value PWR Description 15 12 RO Oh Reserv
311. her status fields in the Fault Status register by writing back the value read from the respective fields 29 0 RO Oh Reserved RSVD Datasheet Volume 2 277 intel Processor Configuration Registers 2 18 10 FEDATA_REG Fault Event Data Register This register specifies the interrupt message data B D F Type 0 0 0 GFXVTBAR Address Offset 3C 3Fh Reset Value 00000000h Access RW Size 32 bits s Reset RST Sat Bit Access Value PWR Description Extended Interrupt Message Data EIMD This field is valid only for implementations supporting 32 bit 31 16 RW 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data may treat this field as RsvdZ 15 0 RW 0000h Ee Interrupt Message Data IMD Data value in the interrupt request 2 18 11 FEADDR_REG Fault Event Address Register This register specifies the interrupt message address Access Size B D F Type Address Offset Reset Value 0 0 0 GFXVTBAR 40 43h 00000000h RW 32 bits BIOS Optimal Default Oh e Reset RST ar Bit Access Value PWR Description Message Address MA d When fault events are enabled the contents of this register 1 2 RW h 3 00090900 Uncore specify the DWord aligned address bits 31 2 for the interrupt request 1 0 RO Oh Reserved RSVD 2 18 12 FEUADDR_REG Fault Event Upper Address Register This register s
312. his register specifies the base address of the memory resident fault log region This register is treated as RsvdZ for implementations not supporting advanced translation fault logging AFL field reported as 0 in the Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 58 5Fh Reset Value 0000000000000000h Access RO Size 64 bits BIOS Optimal Default 000h S Reset RST a Bit Access Value PWR Description Fault Log Address FLA This field specifies the base of 4 KB aligned fault log region in system memory Hardware ignores and does not implement bits 00000000 63 HAW where HAW is the host address width 63 12 RO 00000h Uncore Software specifies the base address and size of the fault log region through this register and programs it in hardware through the SFL field in the Global Command register When implemented reads of this field return the value that was last programmed to it Fault Log Size FLS This field specifies the size of the fault log region pointed by the S FLA field The size of the fault log region is 2 X 4KB where X is 11 3 RO Oh Ungorg the value programmed in this register When implemented reads of this field return the value that was last programmed to it 8 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers intel 2 21 14 PMEN_REG Protected Memory Enable Register This register enables the DMA protected memory regions setup t
313. hrough the PLMBASE PLMLIMT PHMBASE PHMLIMIT registers The register is always treated as RO for implementations not supporting protected memory regions PLMR and PHMR fields reported as Clear in the Capability register Protected memory regions may be used by software to securely initialize remapping structures in memory To avoid impact to legacy BIOS usage of memory software is recommended to not overlap protected memory regions with any reserved memory regions of the platform reported through the Reserved Memory Region Reporting RMRR structures Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 VCOPREMAP 64 67h 00000000h RW RO V 32 bits 00000000h Bit Access Reset Value RST PWR Description 31 RW Oh Uncore Enable Protected Memory EPM This field controls DMA accesses to the protected low memory and protected high memory regions 0 Protected memory regions are disabled 1 Protected memory regions are enabled DMA requests accessing protected memory regions are handled as follows When DMA remapping is not enabled all DMA requests accessing protected memory regions are blocked When DMA remapping is enabled e DMA requests processed as pass through Translation Type value of 10b in Context Entry and accessing the protected memory regions are blocked e DMA requests with translated address AT 10b and accessing the protected memory re
314. idation request through this field only when there are no invalidation requests pending at this remapping hardware unit Since information from the context cache may be used by hardware to tag IOTLB entries software must perform domain selective or global invalidation of IOTLB after the context cache invalidation has completed Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flush before invalidating the context cache 62 61 RW Oh Uncore Context Invalidation Request Granularity CIRG Software provides the requested invalidation granularity through this field when setting the ICC field 00 Reserved 01 Global Invalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field 11 Device selective invalidation request The target source id s must be specified through the SID and FM fields and the domain id that was programmed in the context entry for these device s must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field 322
315. idations Software writes to this field to enable or disable queued invalidations 26 wo Ob Ungore 0 Disable queued invalidations 1 Enable use of queued invalidations Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register The value returned on a read of this field is undefined Interrupt Remapping Enable IRE This field is valid only for implementations supporting interrupt remapping 0 Disable interrupt remapping hardware 1 Enable interrupt remapping hardware Hardware reports the status of the interrupt remapping enable operation through the IRES field in the Global Status register There may be active interrupt requests in the platform when 25 wo Ob Uncore software updates this field Hardware must enable or disable interrupt remapping logic only at deterministic transaction boundaries so that any in flight interrupts are either subject to remapping or not at all Hardware implementations must drain any in flight interrupts requests queued in the Root Complex before completing the interrupt remapping enable command and reflecting the status of the command through the IRES field in the Global Status register The value returned on a read of this field is undefined Datasheet Volume 2 269 270 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 0 0 GFXVTBAR 18 1Bh 00000000h RO W
316. ies NLE This field indicates the number of link entries following the 15 8 RO 02h Uncore Element Self Description This field reports 2 one for MCH egress port to main memory and one to egress port belonging to ICH on other side of internal link 7 4 RO Oh Reserved RSVD Element Type ETYP 3 0 RO 2h Uncore This field indicates the type of the Root Complex Element a value of 2h represents an Internal Root Complex Link DMI Datasheet Volume 2 229 Processor Configuration Registers intel 2 12 19 DMILE1D DMI Link Entry 1 Description Register This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 50 53h Reset Value 00000000h Access RW O RO Size 32 bits BIOS Optimal Default 0000h Reset RST Bit Access Value PWR Description Target Port Number TPN This field specifies the port number associated with the element targeted by this link entry egress port of PCH The target port number is with respect to the component that contains this 31 24 RW O 00h Uncore element as specified by the target component ID This can be programmed by BIOS but the Reset Value will likely be correct because the DMI RCRB in the PCH will likely be associated with the default egress port for the PCH meaning it will be assigned port number 0 Target Component ID TCID Identifies
317. ies Pointer Register 54 PXPEPBAR PCI Express Egress Port Base Address Register 54 MCHBAR Host Memory Mapped Register Range Base Register 05 55 GGC GMCH Graphics Control Register 55 DEVEN Device Enable ReGISte c cccccccscecencncatacceeeceneecaedaceecaneeceseneseerenes 57 PAVPC Protected Audio Video Path Control Register 59 DPR DMA Protected Range Register 59 PCIEXBAR PCI Express Register Range Base Address Register 60 DMIBAR Root Complex Register Range Base Address Register 62 MESEG_BASE Intel Management Engine Base Address Register 63 MESEG_MASK Intel Management Engine Limit Address Register 64 PAMO Programmable Attribute Map O Register 65 PAM1 Programmable Attribute Map 1 Register 66 PAM2 Programmable Attribute Map 2 Register 67 PAM3 Programmable Attribute Map 3 Register 68 PAM4 Programmable Attribute Map 4 Register 69 PAM5 Programmable Attribute Map 5 Register 70 PAM6 Programmable Attribute Map 6 Register 71 LAC Legacy Access Control Register 72 REMAPBASE Remap Base Address Register 76 REMAPLIMIT Remap Limit Address Register 77 TOM Top of Memory Register 77 TOUUD Top of Upper Usable DRAM Register eceeeeeeeeeeeee este eeeeeeaee 78 BDSM Base Data of Stolen Memory Register 79 BGSM Base of GTT Stolen Memory Register 79 TSEGMB TSEG Memory Base Reoteter ee eee eens tenet eee eeeaeeaenenaes 80 TOLUD
318. ified by ADDR and AM fields 5 0 RW 00h Uncore Address Mask AM The value in this field specifies the number of low order bits of the ADDR field that must be masked for the invalidation operation This field enables software to request invalidation of contiguous mappings for size aligned regions For example Mask ADDR bits Pages Value masked invalidated 0 None 1 1 12 2 2 13 12 4 3 14 12 8 4 15 12 16 When invalidating mappings for super pages software must specify the appropriate mask value For example when invalidating mapping for a 2 MB page software must specify an address mask value of at least 9 Hardware implementations report the maximum supported mask value through the Capability register 340 Datasheet Volume 2 Processor Configuration Registers intel 2 21 29 IOTLB_REG IOTLB Invalidate Register This register invalidates IOTLB The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation B D F Type 0 0 0 VCOPREMAP Address Offset 108 10Fh Reset Value 0000000000000000h Access RW RW V RO V Size 64 bits BIOS Optimal Default 0000000000000h Reset RST Bit Access Value PWR Description Invalidate IOTLB IVT Software requests IOTLB invalidation by setting this field Software must also set the requested invalidation granularity by programming the IIRG field A Hardware clears the I
319. ignificant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all is The protected high memory base amp limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits HAW N 1 specifies a protected low memory region of size 2 N 1 bytes e Programming the protected high memory limit register with a value less than the protected high memory base register disables the protected high memory region Software must not modify this register when protected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 78 7Fh Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 000000000000h J Reset RST SE Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Protected High Memory Limit PHML This register specifies the last host physical address of the DMA 38 20 RW 00000h Uncore protected high memory region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width 19 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers intel 2 18 19 IQH_REG Invalidation Queue Head Register This register indicates the invalidation queue head This register is trea
320. ined in Section 4 2 3 2 Oh Reserved RSVD Lane 0 Upstream Component Receiver Preset Hint UCRPHO Receiver Preset Hint for Upstream Component The upstream 000b Uncore GE f PANA component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO Transmitter Preset for an Upstream Component See the PCIe 1000b U more Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 138 Datasheet Volume 2 Processor Configuration Registers intel 2 7 9 EQCTL2_3 Lane 2 3 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane B D F Type 0 1 0 2 MMR Address Offset DA4 DA7h Reset Value 07080708h Access RW Size 32 bits BIOS Optimal Default Oh d Reset RST GC Bit Access Value PWR Description 31 RO Oh Reserved RSVD Lane 1 Downstream Component Receiver Preset Hint DCRPH1 S Receiver Preset Hint for Downstream Component The Upstream 30 2 RW 000b U EES Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Downstream Component Transmitter Preset DCTP1 S Transmitter Preset for Downst
321. ing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers SERR Enable SERREN 0 No forwarding of error messages from secondary side to 1 RW Ob Uncore primary side that could result in an SERR 1 ERR_COR ERR_NONFATAL and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register Parity Error Response Enable PEREN This bit controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the root port receives across the link upstream a Read Data Completion Poisoned TLP RW 0 a b uneore 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set 2 6 25 PM_CAPID Power Management Capabilities Register B D F Type 0 1 0 2 PCI Address Offset 80 83h Reset Value C8039001ih Access RO RO V Size 32 bits o Reset RST re Bit Access Value PWR Description PME Support PMES This field indicates the power states in which this device may indicate PME wake using PCI Express messaging DO D3hot and 31 27 RO 19h Uncore D3cold This device is not required to do anything to support D3hot and D3cold it simply must report that those states are supported Refer to the PCI Power Management 1 1 specification for encoding explanation and other power management details D2 Powe
322. ion Value PWR g Invalidate Context Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field is Clear to confirm the invalidation is complete Software must not update this register when this field is set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field Oh Uncore Software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this remapping hardware unit Since information from the context cache may be used by hardware to tag IOTLB entries software must perform domain selective or global invalidation of IOTLB after the context cache invalidation has completed Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flush before invalidating the context cache 62 61 RW Context Invalidation Request Granularity CIRG Software provides the requested invalidation granularity through this field when setting the ICC field 00 Reserved 01 Global Invalidation request 10 Domain selective invalidation request The target domain id must be specified i
323. ion device with bridge header layout 168 Datasheet Volume 2 Processor Configuration Registers intel 2 10 9 PBUSN Primary Bus Number Register This register identifies that this virtual Host PCI Express bridge is connected to PCI bus 0 B D F Type 0 6 0 PCI Address Offset 18h Reset Value 00h Access RO Size 8 bits e Reset RST a Bit Access Value PWR Description Primary Bus Number BUSN Configuration software typically programs this field with the 7 0 RO 00h Uncore number of the bus on the primary side of the bridge Since the processor root port is an internal device and its primary bus is always 0 these bits are read only and are hardwired to 0 2 10 10 SBUSN Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the virtual bridge that is to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 6 0 PCI Address Offset 19h Reset Value 00h Access RW Size 8 bits Bit Access ere e Description Secondary Bus Number BUSN 7 0 RW 00h Uncore This field is programmed by configuration software with the bus number assigned to PCI Express G 2 10 11 SUBUSN Subordinate Bus Number Register This register identifies the subordinate bus if any that resides at the level below PCI
324. ion 0 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set if Device 6 VGA Enable bit is not set If Device 6 Function 0 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 6 Function 0 if the address is within the corresponding IOBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h 0B7FFFh T O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 0 All References to MDA and VGA space are not claimed by Device 6 Function 0 1 Illegal combination 1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 6 function 0 1 1 All VGA references are routed to PCI Express Graphics Attach Device 6 Function 0 MDA references are not claimed by Device 6 Function 0 VGA and MDA memory cycles can only be routed across PEG60 when MAE PCICMD60 1 is set VGA and MDA I O cycles
325. is bit indicates that this device does not generate PME assertion from any D state Ob Uncore 0 PME generation not possible from any D State 1 PME generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 4 RO Oh Reserved RSVD RO No Soft Reset NSR 1 When set to 1 this bit indicates that the device is transitioning from D3hot to DO because the power state commands do not perform an internal reset Configuration context is preserved Upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits 0 When clear the devices do not perform an internal reset upon transitioning from D3hot to DO using software control of the power state bits Regardless of this bit the devices that transition from a D3hot to DO by a system or bus segment reset will return to the device state DO uninitialized with only PME context preserved if PME is supported and enabled 1b Uncore RO Oh Reserved RSVD 1 0 RW Power State PS This field indicates the current power state of this device and can be used to set the device into a new power state If software attempts to write an unsupported state to this field write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 01 Di Not supported in this device 10 D2 N
326. is register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 6 0 MMR Address Offset 108 10Bh Reset Value 00000000h Access RO Size 32 bits BIOS Optimal Default 0000h J Reset RST GE Bit Access Value PWR Description VC Arbitration Table Offset VCATO Indicates the location of the VC Arbitration Table This field contains the zero based offset of the table in DQWORDS 16 oi RO ooh Reie bytes from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO Oh Reserved RSVD 7 0 RO 00h Uncore Reserved for VC Arbitration Capability VCAC 204 Datasheet Volume 2 Processor Configuration Registers D 2 11 3 PVCCTL Port VC Control Register B D F Type 0 6 0 MMR Address Offset 10C 10Dh Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 0000h z Reset RST Perr Bit Access Value PWR Description 15 4 RO Oh Reserved RSVD VC Arbitration Select VCAS This field will be programmed by software to the only possible 3 1 RW 000b Uncore value as indicated in the VC Arbitration Capability field Since there is no other VC supported than the default this field is reserved Reserved for Load VC Arbitration Table VCARB Used for software to update the VC Arbitration Table when VC 0 RO Ob Uncore arbitration uses the
327. isters 2 17 Group Registers intel Memory Controller MMIO Registers Broadcast Table 2 20 Memory Controller MMIO Registers Broadcast Group Register Address Map pa p di Register Name Reset Value Access 0 4CAFh RSVD Reserved 4CBO 4CB3h Ge Gi Power down Configuration 00000000h RW L 4CB4 4CC7h RSVD Reserved 4CD0 4F83h RSVD Reserved 4F84 4F87h PM_CMD_PWR Power Management Command Power 00000000h RW LV 4F88 4F8Bh te BW Limit Configuration FFFFO3FFh RW L 4F8C 4F8Fh RSVD Reserved FF1D1519h RW L Datasheet Volume 2 257 Processor Configuration Registers intel 2 17 1 PM_PDWN_config Power down Configuration Register This register defines the power down CKE off operation power down mode idle timer and global per rank decision B D F Type 0 0 0 MCHBAR_MCBCAST Address Offset 4CBO 4CB3h Reset Value 00000000h Access RW L Size 32 bits BIOS Optimal Default 00000h Reset RST Se Bit Access Value PWR Description 31 13 RO Oh Reserved RSVD Global power down GLPDN 12 RW L Ob Uncore Global Power Down When this bit is set the power down decision is global for channel When this register is clear a separate decision is taken for each rank Power down mode PDWN_mode Selects the mode of power down All encodings not in table are reserved Note When selecting DLL off or APD DLL off DIMM MRO register bit 12 PPD must equal 0 No
328. isters PCI Device 0 Function 0 Configuration Space Register Address Map Sheet 1 of 2 Address Register Offset Symbol Register Name Reset Value Access 0 1h VID Vendor Identification 8086h RO 2 3h DID Device Identification 0150h RO FW RO V 4 5h PCICMD PCI Command 0006h RO RW 6 7h PCISTS PCI Status 0090h RW1C RO 8h RID Revision Identification 00h RO FW 9 Bh cc Class Code 060000h RO C Dh RSVD Reserved Oh RO Eh HDR Header Type 00h RO F 2Bh RSVD Reserved Oh RO 2C 2Dh SVID Subsystem Vendor Identification 0000h RW O 2E 2Fh SID Subsystem Identification 0000h RW O 30 33h RSVD Reserved Oh RO 34h CAPPTR Capabilities Pointer EOh RO 35 3Fh RSVD Reserved Oh RO 40 47h PXPEPBAR PCI Express Egress Port Base Address 00000000000 RW 00000h 48 4Fh MCHBAR Host Memory Mapped Register Range Base 09900000009 RW 50 51h GGC GMCH Graphics Control Register 0028h RW L RW KL 52 53h RSVD Reserved Oh RO 54 57h DEVEN Device Enable 0000209Fh RW L RO RW 58 5Bh PAVPC Protected Audio Video Path Control 00000000h RW L RW KL 5C 5Fh DPR DMA Protected Range 00000000h RA BON 60 67h PCIEXBAR PCI Express Register Range Base Address GE de RW RW V 68 6Fh DMIBAR Root Complex Register Range Base Address Seana RW 7 Intel Management Engine Base Address 0000007FFFFO z 70 77h MESEG_BASE Register 0000h RW L Intel Management Engine Limit Address 00000000000 8 78 7Fh MESEG_MASK Register 00000h RW L RW KL 80h PAMO Programmable Attribute Map 0 00h RW 8ih PAM1 Programmab
329. itration Capability field Since there is no other VC supported than the default this field is reserved Reserved for Load VC Arbitration Table VCARB Used for software to update the VC Arbitration Table when VC 0 RO Ob Uncore arbitration uses the VC Arbitration Table As a VC Arbitration Table is never used by this component this field will never be used Datasheet Volume 2 Processor Configuration Registers 2 7 4 VCORCAP VCO Resource Capability Register B D F Type 0 1 0 2 MMR Address Offset 110 113h Reset Value 00000001h Access RO Size 32 bits BIOS Optimal Default 00h z Reset RST DS Bit Access Value PWR Description 31 24 RO 00h Uncore Reserved for Port Arbitration Table Offset PATO 23 RO Oh Reserved RSVD 22 16 RO 00h Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the 15 RO Ob Uncore TLP header are allowed on this VC 1 When set any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request 14 8 RO Oh Reserved RSVD Port Arbitration Capability PAC This field indicates types of Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that d
330. le RBE 9 RO SS Encore 0 ROM not accessible 2 8 16 CAPPOINT Capabilities Pointer Register This register points to a linked list of capabilities implemented by this device B D F Type 0 2 0 PCI Address Offset 34h Reset Value 90h Access RO V Size 8 bits Bit Access EE Ran Description Capabilities Pointer Value CPV This field contains an offset into the function s PCI Configuration g E Space for the first item in the New Capabilities Linked List the H ROSY SEN Uncore MSI Capabilities ID registers at address 90h or the Power Management capability at DOh This value is determined by the configuration in CAPL 0 Datasheet Volume 2 157 2 8 18 2 8 19 158 Processor Configuration Registers INTRLINE Interrupt Line Register This 8 bit register is used to communicate interrupt line routing information It is read write and must be implemented by the device POST software will write the routing information into this register as it initializes and configures the system The value in this register tells which input of the system interrupt controller s the device s interrupt pin is connected to The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information B D F Type 0 2 0 PCI Address Offset 3Ch Reset Value 00h Access RW Size 8 bits Bit Access PE ct Description
331. le Attribute Map 1 00h RW 82h PAM2 Programmable Attribute Map 2 00h RW 83h PAM3 Programmable Attribute Map 3 00h RW 84h PAM4 Programmable Attribute Map 4 00h RW 85h PAM5 Programmable Attribute Map 5 00h RW 86h PAM6 Programmable Attribute Map 6 00h RW 87h LAC Legacy Access Control 00h RW Reserved RW LV RW L 88h RSVD 02h RW KL RO Datasheet Volume 2 47 intel Processor Configuration Registers Table 2 8 PCI Device 0 Function 0 Configuration Space Register Address Map Sheet 2 of 2 EE ot Register Name Reset Value Access 89 8Fh RSVD Reserved Oh RO 90 97h REMAPBASE Remap Base Address Register se rh RW L RW KL 98 9Fh REMAPLIMIT Remap Limit Address Register KN RW L RW KL AO A7h TOM Top of Memory 0000007FFFFO RW L RW KL 0000h A8 AFh TOUUD Top of Upper Usable DRAM 00000000000 RW KL RW L 00000h BO B3h BDSM Base Data of Stolen Memory 00000000h RW KL RW L B4 B7h BGSM Base of GTT stolen Memory 00100000h RW L RW KL B8 BBh TSEGMB TSEG Memory Base 00000000h RW L RW KL BC BFh TOLUD Top of Low Usable DRAM 00100000h RW KL RW L CO DBh RSVD Reserved Oh RO DC DFh SKPD Scratchpad Data 00000000h RW EO E3h RSVD Reserved Oh RO E4 E7h CAPIDO_A Capabilities A 00000000h RO FW RO KFW E8 EBh CAPIDO_B Capabilities B 00000000h RO FW RO KFW 2 5 1 vID Vendor Identification Register This register combined with the Device Identification register uniquely ide
332. lect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled directly by the downstream port through implementation specific mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Ob Uncore Reserved for Hot plug Interrupt Enable HPIE When set to 1b this bit enables generation of an interrupt on enabled hot plug events Reset Value of this field is Ob If the Hot plug Capable field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Ob Uncore Reserved for Command Completed Interrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 1b this bit enables software notification when a hot plug command is completed by the Hot Plug Controller Reset Value of this field is Ob If Command Completed notification is not supported this bit must be hardwired to Ob Ob Uncore Presence Detect Changed Enable PDCE When set to 1b this bit enables software notification on a
333. lete EQCOMPLETE When set to 1b this bit indicates that the Transmitter ci Equalization procedure has completed Details of the Transmitter Ge o Uncore Equalization process and when this bit needs to be set to 1b is provided in PCIe specification Section 4 2 6 4 2 The Reset Value of this bit is Ob Current De emphasis Level CURDELVL When the Link is operating at 5 GT s speed this reflects the level of de emphasis 0 RO V Ob Uncore 4_ _35qp 0 6dB When the Link is operating at 2 5 GT s speed this bit is 0b Datasheet Volume 2 131 Processor Configuration Registers intel 2 7 PCI Device 1 Function 0 2 Extended Configuration Registers Table 2 10 PCI Device 1 Function 0 2 Extended Configuration Register Address Map 132 SE peel Register Name Reset Value Access 0 103h RSVD Reserved Oh RO 104 107h PVCCAP1 Port VC Capability Register 1 00000000h RO 108 10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO 10C 10Dh PVCCTL Port VC Control 0000h RW RO 10E 10Fh RSVD Reserved Oh RO 110 113h VCORCAP VCO Resource Capability 00000001h RO 114 117h VCORCTL VCO Resource Control 800000FFh RO RW 118 119h RSVD Reserved Oh RO 11A 11Bh VCORSTS VCO Resource Status 0002h RO V 11C 207h RSVD Reserved Oh RO 208 20Bh PEG_TC PCI Express Completion Time out 00010005h RW 20C D9Fh RSVD Reserved 02000100h RO RW O DAO DA3h EQCTLO_1 Lane 0 1 Equalization Contr
334. letion of the invalidation request by clearing the IVT field At this time the granularity at which actual invalidation was performed is reported through the IAIG field 61 60 RW Oh Uncore 59 59 RO Oh Reserved RSVD Datasheet Volume 2 341 342 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 0 0 VCOPREMAP 108 10Fh 0000000000000000h RW RW V RO V 64 bits 0000000000000h Bit Access Reset Value RST PWR Description 58 57 RO V Oh Uncore IOTLB Actual Invalidation Granularity IAIG Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion by clearing the IVT field The following are the encodings for this field 00 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page selective invalidation requests 01 Global Invalidation performed This could be in response to a global domain selective or page selective invalidation request 10 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or a page selective invalidation request
335. lized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 2 PCI Address Offset 24 25h Reset Value FFFih Access RO RW Size 16 bits Bit Access edel CAD Description Prefetchable Memory Base Address PMBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 64 bit Address Support AS64 z This field indicates that the upper 32 bits of the prefetchable 3 0 RO th Wee memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h Datasheet Volume 2 99 DN t Processor Configuration Registers Note 2 6 19 100 PMLIMIT Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuratio
336. lue 0000h Access RW RO Size 16 bits BIOS Optimal Default 0000h 8 Reset RST GE Bit Access Value PWR Description 15 3 RO Oh Reserved RSVD System Error on Fatal Error Enable SEFEE This bit controls the Root Complex s response to fatal errors 2 RW Ob Uncore 0 No SERR generated on receipt of fatal error 1 SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself 1 0 RO Oh Reserved RSVD 2 10 45 LCAP2 Link Capabilities 2 Register B D F Type 0 6 0 PCI Address Offset CC CFh Reset Value 00000006h Access RO V Size 32 bits BIOS Optimal Default 000000h o Reset RST ae Bit Access Value PWR Description 31 8 RO Oh Reserved RSVD Supported Link Speeds Vector SLSV This field indicates the supported Link speed s of the associated Port For each bit a value of 1b indicates that the corresponding Link speed is supported otherwise the Link speed is not supported Bit definitions are Bit 1 2 5 GT s 7 1 RO V 03h Uncore Bit 2 5 0 GT s Bit 3 8 0 GT s Bits 7 4 Reserved Multi Function devices associated with an Upstream Port must report the same value in this field for all Functions DMI does not support this control register since it is Gen3 register 0 RO Oh Reserved RSVD 202 Datasheet Volume 2 Processor Configuration Registers intel
337. lue PWR Description 15 2 RO Oh Reserved RSVD Virtual Channel Negotiation Pending VCNEGPND 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This bit indicates the status of the process of Flow Control 1 RO V 1b Uncore initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Oh Reserved RSVD 2 12 17 DMIRCLDECH DMI Root Complex Link Declaration Register This capability declares links from the respective element to other elements of the root complex component to which it belongs and to an element in another root complex component See PCI Express specification for link topology declaration requirements B D F Type 0 0 0 DMIBAR Address Offset 40 43h Reset Value 08010005h Access RO Size 32 bits 3 Reset RST ar Bit Access Value PWR Description Pointer to Next Capability PNC e This field contains the offset to the next PCI Express capability 1 2 R Oh one 9 og RES structure in the linked list of capabilities Internal Link Control Capability
338. m Component The Upstream 27 24 RW 0111b U e Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD Lane 1 Upstream Component Receiver Preset Hint UCRPH1 22 20 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Upstream Component Transmitter Preset UCTP1 i Transmitter Preset for an Upstream Component See the PCIe 19 16 RW 1000b U 9 Ge Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 15 RO Oh Reserved RSVD Lane 0 Downstream Component Receiver Preset Hint DCRPHO 14 12 RW 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Downstream Component Transmitter Preset DCTPO Transmitter Preset for Downstream Component The Upstream It RW 0111b U S WEN Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 7 RO Oh Reserved RSVD Lane 0 Upstream Co
339. main id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware ignores and not implements bits 47 32 N where N is the supported domain id width reported in the Capability register RO Oh Reserved RSVD SS Datasheet Volume 2
340. mands assuming that each RAS command for a given page is followed by a PRE command to the same page in the near future 2 17 3 PM_BW_LIMIT_CONFIG BW Limit Configuration Register This register defines the BW throttling at temperature Note The field BW_limit_tf may not be changed in run time Other fields may be changed in run time B D F Type 0 0 0 MCHBAR_MCBCAST Address Offset 4F88 4F8Bh Reset Value FFFFO3FFh Access RW L Size 32 bits BIOS Optimal Default 5F7003FFh d Reset RST Pare Bit Access Value PWR Description BW limit when rank is hot BW_limit_hot 31 24 RW L FFh Uncore Number of transactions allowed per rank when status of rank is hot Range 0 255h BW limit when rank is warm BW_limit_warm 23 16 RW L FFh Uncore Number of transactions allowed per rank when status of rank is warm Range 0 255h 15 10 RO Oh Reserved RSVD BW limit time frame BW_limit_tf 9 0 RW L 3FFh Time frame in which the BW limit is enforced in DCLK cycles Datasheet Volume 2 SEERS Range 1 1023h Note The field BW_limit_tf may not be changed in run time 259 intel Processor Configuration Registers 2 18 Integrated Graphics VTd Remapping Engine Registers Table 2 21 Integrated Graphics VTd Remapping Engine Register Address Map Sheet 1 of 2 Addtess Register Symbol Register Name Reset Value Acce
341. mapping hardware unit has one or more critical isochronous requesters in its scope To ensure isochronous performance software must ensure invalidation operations do not impact active DMA streams from such requesters This implies when DMA is active software performs page selective invalidations and not coarser invalidations 22 RO 1b Uncore Zero Length Read ZLR 0 Indicates the remapping hardware unit blocks and treats as fault zero length DMA read requests to write only pages Indicates the remapping hardware unit supports zero length DMA read requests to write only pages DMA remapping hardware implementations are recommended to report ZLR field as set 1 21 16 RO 100110b Uncore Maximum Guest Address Width MGAW This field indicates the maximum DMA virtual addressability supported by remapping hardware The Maximum Guest Address Width MGAW is computed as N 1 where N is the value reported in this field For example a hardware implementation supporting 48 bit MGAW reports a value of 47 101111b in this field If the value in this field is X untranslated and translated DMA requests to addresses above 2 x 1 1 are always blocked by hardware Translations requests to address above 2 x 1 1 from allowed devices return a null Translation Completion Data Entry with R W 0 Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adj
342. me 2 Processor Configuration Registers intel 2 21 27 IRTA_REG Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table This register is treated as RsvdZ by implementations reporting Interrupt Remapping IR as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset B8 BFh Reset Value 0000000000000000h Access RW L Size 64 bits BIOS Optimal Default 00000000h Reset RST SC Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Interrupt Remapping Table Address IRTA This field points to the base of 4 KB aligned interrupt remapping table 112 RW L 0 00h 38 0900009 Ungore Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Reads of this field returns value that was last programmed to it 11 4 RO Oh Reserved RSVD Size S S 8 This field specifies the size of the interrupt remapping table The RW L h ae k SZ Er number of entries in the interrupt remapping table is 2 X 1 where X is the value programmed in this field Datasheet Volume 2 339 intel Processor Configuration Registers 2 21 28 IVA_REG Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register This register is a write only register Access Size B D F
343. mory Base Address FFFOh RW 22 23h MLIMIT Memory Limit Address 0000h RW 24 25h PMBASE Prefetchable Memory Base Address FFFih RO RW 26 27h PMLIMIT Prefetchable Memory Limit Address 0001h RW RO 28 2Bh PMBASEU Prefetchable Memory Base Address Upper 00000000h RW 2C 2Fh PMLIMITU Prefetchable Memory Limit Address Upper 00000000h RW 30 33h RSVD Reserved Oh RO 34h CAPPTR Capabilities Pointer 88h RO 35 3Bh RSVD Reserved Oh RO 3Ch INTRLINE Interrupt Line 00h RW 3Dh INTRPIN Interrupt Pin Oih RW O RO 3E 3Fh BCTRL Bridge Control 0000h RO RW 40 7Fh RSVD Reserved Oh RO 80 83h PM_CAPID Power Management Capabilities C803900ih RO RO V 84 87h PM_CS Power Management Control Status 00000008h RO RW 88 8Bh SS_CAPID Subsystem ID and Vendor ID Capabilities 0000800Dh RO 8C 8Fh SS Subsystem ID and Subsystem Vendor ID 00008086h RW O 90 91h MSI_CAPID Message Signaled Interrupts Capability ID A005h RO Datasheet Volume 2 Processor Configuration Registers Table 2 9 2 6 1 intel PCI Device 1 Function 0 2 Configuration Space Register Address Map Sheet 2 of 2 penta pare Register Name Reset Value Access 92 93h MC Message Control 0000h RW RO 94 97h MA Message Address 00000000h RW RO 98 99h MD Message Data 0000h RW 9A 9Fh RSVD Reserved Oh RO AO Aih PEG_CAPL PCI Express G Capability List 0010h RO A2 A3h PEG_CAP PCI Express G Capabilities 0142h RO RW O A4 A7h DCAP Device Capa
344. mplemented on chip The allocation is for 4 MB and the base address is defined by bits 38 22 B D F Type 0 2 0 PCI Address Offset 10 17h Reset Value 0000000000000004h Access RO RW Size 64 bits e Reset RST SE Bit Access Value PWR Description FLR Reserved for Memory Base Address RSVDRW 63 33 RW 0000000 Uncore Must be set to 0 since addressing above 512 GB is not supported Memory Base Address MBA FLR set by the operating system these bits correspond to address 38 22 RW EEN Uncore signals 38 22 4 MB combined for MMIO and Global GTT table aperture 2 MB for MMIO and 2 MB for GTT Address Mask ADM 21 4 RO SES Unicore Hardwired to Os to indicate at least 4 MB address range Prefetchable Memory PREFMEM 3 RO SS Ze Hardwired to 0 to prevent prefetching Memory Type MEMTYP 00 To indicate 32 bit base address 2 1 RO 10b Uncore 01 Reserved 10 To indicate 64 bit base address 11 Reserved Memory IO Space MIOS S RO ob ngore Hardwired to 0 to indicate memory space Datasheet Volume 2 Processor Configuration Registers intel 2 8 11 GMADR Graphics Memory Range Address Register GMADR is the PCI aperture used by S W to access tiled graphics surfaces in a linear fashion B D F Type 0 2 0 PCI Address Offset 18 1Fh Reset Value 000000000000000Ch Access RW RO RW L Size 64 bits e Reset RST So a Bit Access Value PWR Description
345. mponent Receiver Preset Hint UCRPHO 6 4 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO x Transmitter Preset for an Upstream Component See the PCIe 0 RW 1000b 2 S Unicore Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Datasheet Volume 2 141 intel Processor Configuration Registers 2 7 12 EQCTL8_9 Lane 8 9 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane Access Size B D F Type Address Offset Reset Value 0 1 0 MMR DBO DB3h 07080708h RW 32 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 31 30 28 RO RW Oh Reserved RSVD Lane 1 Downstream Component Receiver Preset Hint DCRPH1 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 27 24 RW Lane 1 Downstream Component Transmitter Preset DCTP1 0111b Uncore Transmitter Preset for Do
346. n be disabled by setting MSICH CAPL 0 7Fh In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability B D F Type 0 1 0 2 PCI Address Offset 90 91ih Reset Value A005h Access RO Size 16 bits o Reset RST ae Bit Access Value PWR Description Pointer to Next Capability PNC 15 8 RO AOh Uncore This field contains a pointer to the next item in the capabilities list which is the PCI Express capability Capability ID CID 7 0 RO 05h Uncore Value of 05h identifies this linked list item capability structure as being for MSI registers Datasheet Volume 2 Processor Configuration Registers intel 2 6 30 MC Message Control Register System software can modify bits in this register but the device is prohibited from doing so If the device writes the same message multiple times only one of those messages is ensured to be serviced If all of them must be serviced the device must not generate the same message again until the driver services the earlier one B D F Type 0 1 0 2 PCI Address Offset 92 93h Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 00h d Reset RST Paes Bit Access Value PWR Description 15 8 RO Oh Reserved RSVD 64 bit Address Capable B64AC Hardwired to 0 to indicate that the function does not implement a SS Ge Ungore the upper 32 bi
347. n both Components on a Link 3 Software must ensure that no traffic is using a Virtual Channel at the time it is disabled 4 Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO Oh Reserved RSVD 26 24 RW 111b Uncore Virtual Channel ID VCID This field assigns a VC ID to the VC resource Assigned value must be non zero This field cannot be modified when the VC is already enabled 23 8 RO Oh Reserved RSVD 7 0 RO 80h Uncore Traffic Class Virtual Channel Map TCVCMMAP This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link Datasheet Volume 2 227 intel Processor Configuration Registers 2 12 16 DMIVCMRSTS DMI VCm Resource Status Register B D F Type 0 0 0 DMIBAR Address Offset 3E 3Fh Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h o Reset RST ae Bit Access Va
348. n software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 1 0 2 PCI Address Offset 26 27h Reset Value 0001h Access RW RO Size 16 bits Bit Access Les lt Description Prefetchable Memory Address Limit PMLIMIT 15 4 RW 000h Uncore This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express graphics 64 bit Address Support AS64B 3 This field indicates that the upper 32 bits of the prefetchable 0 RO th 3 uncore memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch PMBASEU Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspo
349. n software that this device function implements a list of new capabilities A list of new capabilities is accessed using register CAPPTR at configuration address offset 34h Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capability Identification register resides 3 0 RO Oh Reserved RSVD Datasheet Volume 2 51 intel Processor Configuration Registers 2 5 5 RID Revision Identification Register This register contains the revision number of Device 0 These bits are read only and writes to this register have no effect B D F Type 0 0 0 PCI Address Offset 8h Reset Value 00h Access RO FW Size 8 bits Reset RST te Bit Access Value PWR Description Revision Identification Number RID 7 0 RO FW Oh Uncore Refer to the Mobile 3rd Generation Intel Core Processor Family Specification Update for the value of the RID register 2 5 6 CC Class Code Register This register identifies the basic function of the device a more specific sub class and a register specific programming interface B D F Type 0 0 0 PCI Address Offset 9 Bh Reset Value 060000h Access RO Size 24 bits o Reset RST REP Bit Access Value PWR Description Base Class Code BCC e This is an 8 bit value that indicates the base class code for the ER RO geh SS Host Bridge device This code has
350. n the DID field 11 Device selective invalidation request The target source id s must be specified through the SID and FM fields and the domain id that was programmed in the context entry for these device s must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field Oh Uncore Datasheet Volume 2 273 274 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 0 0 GFXVTBAR 28 2Fh 0800000000000000h RW RW V RO V 64 bits BIOS Optimal Default 000000000h Bit Access Reset RST Value PWR Description 60 59 RO V Context Actual Invalidation Granularity CAIG Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion by clearing the ICC field The following are the encodings for this field 00 Reserved 01 Global Invalidation performed This could be in response to a global domain selective or device selective invalidation 1h Uncore request 10 Domain selective invalidation performed using the domain id specified by software i
351. n the DID field This could be in response to a domain selective or device selective invalidation request 11 Device selective invalidation performed using the source id and domain id specified by software in the SID and FM fields This can only be in response to a device selective invalidation request 58 34 RO Oh Reserved RSVD 33 32 RW Function Mask FM Software may use the Function Mask to perform device selective invalidations on behalf of devices supporting PCI Express Phantom Functions This field specifies which bits of the function number portion least significant three bits of the SID field to mask when performing device selective invalidations The following encodings are defined for this field Oh Uncore 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of function number in the SID field 11 Mask all three bits of function number in the SID field The context entries corresponding to all the source ids specified through the FM and SID fields must have to the domain id specified in the DID field 31 16 RW Source ID SID Indicates the source id of the device whose corresponding 0000h Uncore context entry needs to be selectively invalidated This field along with the FM field must be programmed by software for device selective invalidation requests RO Oh Reserved RSVD 7
352. nced fault logging In this case translation faults are reported through the Fault Recording registers 1 Enable use of memory resident fault log When enabled translation faults are recorded in the memory resident log The fault log pointer must be set in hardware through the SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Global Status register The value returned on read of this field is undefined 268 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 18 1Bh Reset Value 00000000h Access RO WO Size 32 bits BIOS Optimal Default 000000h d Reset RST Pare Bit Access Value PWR Description Write Buffer Flush WBF This bit is valid only for implementations requiring write buffer flushing Software sets this field to request that hardware flush the Root Complex internal write buffers This is done to ensure any 27 RO Ob Uncore updates to the memory resident remapping structures are not held in any internal write posting buffers Hardware reports the status of the write buffer flushing operation through the WBFS field in the Global Status register Clearing this bit has no effect The value returned on a read of this field is undefined Queued Invalidation Enable QIE This field is valid only for implementations supporting queued inval
353. nd correspond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Base Address register are read write and correspond to address bits A 38 32 of the 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 28 2Bh Reset Value 00000000h Access RW Size 32 bits Bit Access was pared Description Prefetchable Memory Base Address PMBASEU 31 0 RW 00000000h Uncore This field corresponds to A 63 32 of the lower limit of the prefetchable memory range that will be passed to PCI Express G Datasheet Volume 2 Processor Configuration Registers D t I H 2 10 20 Note PMLIMITU Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Limit Address register are read write an
354. nd does not implement bits 63 HAW where HAW is the host address width 19 0 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers D t I H 2 21 18 PHMLIMIT_REG Protected High Memory Limit Register This register sets up the limit address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region limit depends on the number of reserved bits N 0 of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The protected high memory base and limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits HAW N 1 specifies a protected low memory region of size 2 N 1 bytes e Programming the protected high memory limit register with a value less than the protected high memory base register disables the protected high memory region Software must not modify this register when p
355. nd to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Base Address register are read write and correspond to address bits A 38 32 of the 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 2 PCI Address Offset 28 2Bh Reset Value 00000000h Access RW Size 32 bits Bit Access Lon ten Gi Description Prefetchable Memory Base Address PMBASEU Uncore This field corresponds to A 63 32 of the lower limit of the prefetchable memory range that will be passed to PCI Express G 0000000 31 0 RW Oh Datasheet Volume 2 Processor Configuration Registers D t I H 2 6 20 Note 2 6 21 PMLIMITU Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Limit Address register are read
356. nent Receiver Preset Hint UCRPHO 6 4 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO x Transmitter Preset for an Upstream Component See the PCIe 0 RW 1000b 2 S Unicore Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Datasheet Volume 2 143 intel Processor Configuration Registers 2 7 14 EQCTL12_13 Lane 12 13 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane Access Size B D F Type Address Offset Reset Value 0 1 0 MMR DBS DBBh 07080708h RW 32 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 31 30 28 RO RW Oh Reserved RSVD Lane 1 Downstream Component Receiver Preset Hint DCRPH1 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 27 24 RW Lane 1 Downstream Component Transmitter Preset DCTP1 0111b Uncore Transmitter Preset for D
357. nent Receiver Preset Hint UCRPHO 6 4 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO x Transmitter Preset for an Upstream Component See the PCIe 0 RW 1000b 2 S Unicore Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Datasheet Volume 2 145 intel Processor Configuration Registers 2 7 16 EQCFG Equalization Configuration Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane B D F Type 0 1 0 MMR Address Offset DD8 DDBh Reset Value F9404400h Access RW Size 32 bits BIOS Optimal Default Oh Reset RST Se Bit Access Value PWR Description Full Swing Value FS FS is used to calculate the transmitter coefficients during Equalization Default is 62d Note all equalization presets coefficients have been calculated 31 26 RW 3Eh Uncore using the default FS value of 62d If FS is changed the preset tables located in EQPRESET registers may need to be re programmed to fulfill FS FS Cmi CO Cp1 CO gt 0 Low Frequency Value LF LF is used to calculate the transmitter co
358. noop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request 14 8 RO Oh Reserved RSVD Port Arbitration Capability PAC 7 0 RO Oth Uncore Having only bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed 222 Datasheet Volume 2 Processor Configuration Registers intel 2 12 9 DMIVCiRCTL DMI VC1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1 B D F Type 0 0 0 DMIBAR Address Offset 20 23h Reset Value 01000000h Access RO RW Size 32 bits BIOS Optimal Default 00000h Bit Access PEE vlt Description Virtual Channel 1 Enable VC1E 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is currently disabled 31 RW Ob Uncore BIOS Requirement 1 To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link 2 To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a
359. ns Datasheet Volume 2 251 Processor Configuration Registers intel 2 15 2 CRDTCTL4 Credit Control 4 Register This register will have the minimum Read Return Tracker credits for each of the PEG DMI GSA streams B D F Type 0 0 0 MCHBAR IMPH Address Offset 7410 7413h Reset Value 00000017h Access RW L Size 32 bits Reset RST ZE Bit Access Value PWR Description 31 6 RO Oh Uncore Reserved RSVD Read Return Tracker Shared Credits RDRT_SHRD This field indicates the number of credits that are in the RDRTRN 5 0 RW L 17h Uncore shared pool BIOS should configure this field to a value that is equal to 64 minus the sum of all minimum dedicated RDRTN credits 252 Datasheet Volume 2 Processor Configuration Registers D intel 2 16 MCHBAR Registers in Memory Controller Common Table 2 19 MCHBAR Registers in Memory Controller Common Register Address Map a Gier Register Name Reset Value Access O 4FFFh RSVD Reserved Oh RO 5000 5003h MAD_CHNL Address decoder Channel Configuration 00000024h RW L 5004 5007h MAD_DIMM_chO Address Decode Channel 0 00600000h RW L 5008 500Bh MAD_DIMM_chi Address Decode Channel 1 00600000h RW L 500C 505Fh RSVD Reserved 5060 5063h PM_SREF_config Self Refresh Configuration 000100FFh RW L 5064 50FBh RSVD Reserved 2 16 1 MAD_CHNL Address Decoder Channel Configuration
360. nt translated DMA write requests 47 40 RO Oh Reserved RSVD 39 32 RW 00h Uncore Domain ID DID This field indicates the ID of the domain whose IOTLB entries need to be selectively invalidated This field must be programmed by software for domain selective and page selective invalidation requests The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware ignores and not implements bits 47 32 N where N is the supported domain id width reported in the Capability register RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers intel 2 18 30 FRCDL_REG Fault Recording Low Register This register records fault information when primary fault logging is active Hardware reports the number and location of fault recording registers through the Capability register This register is relevant only for primary fault logging This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1 B D F Type 0 0 0 GFXVTBAR Address Offset 200 207h Reset Value 0000000000000000h Access ROS V Size 64 bits BIOS Optimal Default 0000000000000000h e Reset RST ae Bit Access Value PWR Description Fault Info FI When the Fault Reason FR field indicates one of the
361. ntifies any PCI device B D F Type 0 0 0 PCI Address Offset 0 ih Reset Value 8086h Access RO Size 16 bits Reset RST ere Bit Access Value PWR Description Vendor Identification Number VID Gen RO sogh Uneore PCI standard identification for Intel 48 Datasheet Volume 2 Processor Configuration Registers intel 2 5 2 DID Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 0 0 PCI Address Offset 2 3h Reset Value 0150h Access RO FW RO V Size 16 bits z Reset RST ZE Bit Access Value PWR Description Device Identification Number MSB DID_MSB 15 4 RO FW 015h Uncore This is the upper part of device identification assigned to the processor Device Identification Number SKU DID_SKU 3 2 RO V 00b Uncore This is the middle part of device identification assigned to the processor Device Identification Number LSB DID_LSB 1 0 RO FW 00b Uncore This is the lower part of device identification assigned to the processor 2 5 5 PCICMD PCI Command Register Since Device 0 does not physically reside on PCI_A many of the bits are not implemented B D F Type 0 0 0 PCI Address Offset 4 5h Reset Value 0006h Access RO RW Size 16 bits BIOS Optimal Default 00h o Reset RST a Bit Access Value PWR Description 15 10 RO Oh Reserved RSVD Fast Back
362. ntrols DMA accesses to the DMA Protected Range DPR region 2 RW L Ob Uncore 0 DPR is disabled 1 DPR is enabled All DMA requests accessing DPR region are blocked Hardware reports the status of DPR enable disable through the PRS field in this register Protected Region Status PRS This field indicates the status of DPR z SES ag ee 0 DPR protection disabled 1 DPR protection enabled 0 RO Oh Reserved RSVD Datasheet Volume 2 59 60 Processor Configuration Registers PCIEXBAR PCI Express Register Range Base Address Register This is the base address for the PCI Express configuration space This window of addresses contains the 4 KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the Uncore There is no actual physical memory within this window of up to 256 MB that can be addressed The actual size of this range is determined by a field in this register Each PCI Express Hierarchy requires a PCI Express BASE register The Uncore supports one PCI Express Hierarchy The region reserved by this register does not alias to any PCI2 3 compliant memory mapped space For example the range reserved for MCHBAR is outside of PCIEXBAR space On reset this register is disabled and must be enabled by writing a 1 to the enable field in this register This base address shall be assigned on a boundary consistent with the number of buses
363. o 0 and read only 23 20 RO Oh Reserved RSVD Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service A valid value for this field is a number 19 17 RW 000b Uncore corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource Because only bit 0 of that field is asserted This field will always be programmed to 1 16 8 RO Oh Reserved RSVD 7 RO Ob Uncore Traffic Class m Virtual Channel 0 Map TCMVCOM Traffic Class Virtual Channel 0 Map TCVCOM This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values 6 1 RW 3Fh Uncore For example when bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link Traffic Class 0 Virtual Channel 0 Map TCOVCOM 9 RO tb SE Traffic Class 0 is always routed to VCO Datasheet Volume 2 221 intel Processor Configuration Registers 2 12 7 DMIVCORSTS DMI VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMIBAR Addr
364. o be FECH Bits 0 11 are don t care for 11 4 RW 00h Uncore address decode Address decoding to the APIC range is done as APIC_BASE 31 12 lt A 31 12 lt APIC_LIMIT 31 12 3 0 RO Reserved RSVD 2 11 14 CMNRXERR Common Rx Error Register B D F Type 0 6 0 MMR Address Offset C34 C37h Reset Value 00000000h Access RWI1CS Size 32 bits BIOS Optimal Default 0000000h Reset RST Pare Bit Access Value PWR Description 31 3 RO Reserved RSVD Gen1 2 UFD Framing Error Status UFDFRAMEERR Only applicable for Geni Gen2 When set this field indicates S SES Powergood that a framing error occurred in the Link that is dropped STP dropped SDP dropped END 1 0 RO Reserved RSVD 212 Datasheet Volume 2 Processor Configuration Registers 2 11 15 PEGTST PCI Express Test Modes Register B D F Type 0 6 0 MMR Address Offset DOC DOFh Reset Value 00000000h Access RO FW RW Size 32 bits BIOS Optimal Default 0000000h z Reset RST eet Bit Access Value PWR Description 31 21 RO Oh Reserved RSVD PEG Lane Reversal Strap Status LANEREVSTS This register bit reflects the status of the PEG lane reversal strap The PEGLaneReversal strap is mirrored in this register bit 0 PEG lane is not reversed 20 RO FW Ob Uncore 1 PEG lane is reversed This bit is applicable only for Function 0 in Devices 1 and 6 Note Lane reversal is done end to end regardless of
365. o length DMA read requests to write only pages DMA remapping hardware implementations are recommended to report ZLR field as set 21 16 RO 100110b Uncore Maximum Guest Address Width MGAW This field indicates the maximum DMA virtual addressability supported by remapping hardware The Maximum Guest Address Width MGAW is computed as N 1 where N is the value reported in this field For example a hardware implementation supporting 48 bit MGAW reports a value of 47h 101111b in this field If the value in this field is X untranslated and translated DMA requests to addresses above 2 x 1 1 are always blocked by hardware Translations requests to address above 2 x 1 1 from allowed devices return a null Translation Completion Data Entry with R W 0 Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page table structure Adjusted guest address widths supported by hardware are reported through the SAGAW field Implementations are recommended to support MGAW at least equal to the physical addressability host address width of the platform 15 13 RO Oh Reserved RSVD Datasheet Volume 2 263 264 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 0 0 GFXVTBAR 8 Fh 00C0000020E60262h RO 64 bits
366. o less than 8 us 000 Less than ius 001 1 us to less than 2 us 010 2 us to less than 4 us 17 15 RW O 011ib Uncore 011 4 us to less than 8 us 100 8 us to less than 16 us 101 16 us to less than 32 us 110 32 us 64 us 111 More than 64 us Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate and undesired value from ever existing LOs Exit Latency LOSELAT This field indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64 ns to less than 128 ns 14 12 RW O 010b Uncore 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to less than 1 us 101 1 us to less than 2 us 110 2 us 4 us 111 More than 4 us Datasheet Volume 2 233 Processor Configuration Registers B D F Type Address Offset Reset Value 0 0 0 DMIBAR 84 87h 0001AC4ih Access RW O RO RW OV Size 32 bits BIOS Optimal Default 00002h Reset RST a Bit Access Value PWR Description Active State Link PM Support ASLPMS 11 10 RO 11b ZE LOs amp L1 entry supported Max Link Width MLW 9 4 RO 04h Uncore This field indicates the maximum number of lanes supported for this link Max Link Speed MLS This Reset Value reflects gen1 Later the field may be changed by BIOS to allow gen2 subject to 3 0 RW OV 0001b Uncore Fuse enabled
367. o not support peer to peer traffic Each bit location within this field corresponds to a Port Arbitration Capability defined below When more than one bit in this field is set it indicates that the VC resource can be configured to provide different arbitration services Software selects among these capabilities by writing to the Port Arbitration Select field see below 7 0 RO Oih Uncore Defined bit positions are Bit 0 Non configurable hardware fixed arbitration scheme such as Round Robin RR Bit 1 Weighted Round Robin WRR arbitration with 32 phases Bit 2 WRR arbitration with 64 phases Bit 3 WRR arbitration with 128 phases Bit 4 Time based WRR with 128 phases Bit 5 WRR arbitration with 256 phases Bits 6 7 Reserved Processor only supported arbitration indicates Non configurable hardware fixed arbitration scheme Datasheet Volume 2 135 intel 2 7 5 136 Processor Configuration Registers VCORCTL VCO Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0 B D F Type 0 1 0 2 MMR Address Offset 114 117h Reset Value 800000FFh Access RO RW Size 32 bits BIOS Optimal Default 0000h e Reset RST DS Bit Access Value PWR Description VCO Enable VCOE 31 RO 1b Uncore For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved RSVD VCO ID VCOID 26 24 RO 00
368. o the Display Engine when Memory PLL Shutdown is enabled The Display LP3 latency and watermark values GTTMMADR offset 45110h should be programmed to match the latency in this register 23 RWS Ob Powergood Reserved for Future Use RWSVD2 Reserved for Future Use MPLL Fast Lock Disable MPLL_FAST_DIS 22 RW 0 U Pe we S neore Copy of CR PCU SBPLL_FAST_DIS MPLL Shutdown Latency Time WM2 Number of microseconds to access memory if the MPLL is shutdown requires memory in Self Refresh The value is programmed in 0 5 us granularity 00h 0 us Oih 0 5 us 02h 1 us 21 16 RWS 000000b Powergood 3Fh 31 5 us Note The value in this field corresponds to the memory latency requested to the Display Engine when MPLL shutdown is enabled The Display LP2 latency and watermark values GTTMMADR offset 4510Ch should be programmed to match the latency in this register 15 14 RWS 00b Powergood Reserved for Future Use RWSVD1 Reserved for Future Use 306 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 MCHBAR PCU Address Offset 5D10 5D17h Reset Value 0000000000000000h Access RWS RW Size 64 bits X Reset RST NE Bit Access Value PWR Description Self Refresh and MDLL Latency Time WM1 This field provides the number of microseconds to access memory if memory is in Self Refresh and MDLL is turned off 0 5 us granularity 00h Ous Oih 0 5 us 02h 1 us 13 8 RWS 000000b Powe
369. o use RO b U 8 o E CLKREQ signal to power manage link clock according to protocol defined in appropriate form factor specification Reset Value of this field is Ob Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabilities Register must hardwire this bit to Ob Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state 7 RW Ob Uncore This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns Datasheet Volume 2 193 194 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 6 0 PCI BO Bih 0000h RO RW RW V 16 bits BIOS Optimal Default 00h Bit Access Reset RST Value PWR Description RW Common Clock Configuration CCC 0 This component and the component at the opposite end of this Link are operating with asynchronous reference clock 1 This component and the component at the opposite end of Ob Uncore this Link are operating with a distributed common reference clock The state of this bit affects the LOs Exi
370. ocument Mobile 3rd Generation Intel Core processor family may be referred to simply as processor Throughout this document the Intel 6 7 Series Chipset Platform Controller Hub may also be referred to as PCH The term MBL refers to mobile platforms PCI Express Hot Plug is not supported on the processor SS Datasheet Volume 2 13 14 Introduction Datasheet Volume 2 Processor Configuration Registers D 2 Processor Configuration Registers This chapter contains the following e Register terminology e PCI Devices and Functions on processor System address map e Processor register introduction Detailed register bit descriptions 2 1 Register Terminology Table 2 1 lists the register related terminology and access attributes that are used in this document Table 2 2 provides the attribute modifiers Table 2 1 Register Attributes and Terminology Item Description RO Read Only These bits can only be read by software writes have no effect The value of the bits is determined by the hardware only RW Read Write These bits can be read and written by software RW1C Read Write 1 to Clear These bits can be read and cleared by software Writing a 1 to a bit will clear it while writing a 0 to a bit has no effect Hardware sets these bits RWOC Read Write 0 to Clear These bits can be read and cleared by software Writing a 0 to a bit will cl
371. oefficient PRECUR3 Precursor coefficient for Preset 3 5 0 RW OAh aeons Preset 2 Fostcursor Coefficient POSTCUR2 Postcursor coefficient for Preset 2 Datasheet Volume 2 215 Processor Configuration Registers intel 2 11 20 EQPRESET6_7 Equalization Preset 6 7 Register This register contains coefficients for Preset 6 and 7 B D F Type 0 6 0 MMR Address Offset DCC DCFh Reset Value 36200E06h Access RW Size 32 bits BIOS Optimal Default Oh 5 Reset RST nons Bit Access Value PWR Description 31 6 RO Oh Reserved RSVD 5 0 RW 06h Uncore Preset 6 Precursor Coefficient PRECUR6 Precursor coefficient for Preset 6 2 11 21 EQCFG Equalization Configuration Register B D F Type 0 6 0 MMR Address Offset DD8 DDBh Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 00000000h e Reset RST pai Bit Access Value PWR Description 31 2 RO Oh Reserved RSVD Disable Margining MARGINDIS 1 RW 0 Uncore When set it will disable Tx margining during Polling Compliance and Recovery 0 RO 0 Reserved RSVD 216 Datasheet Volume 2 Processor Configuration Registers intel 2 12 Direct Media Interface Base Address Registers DMIBAR Table 2 15 DMIBAR Register Address Map Sheet 1 of 2
372. ol Register 07080708h RW DA4 DA7h EQCTL2_3 Lane 2 3 Equalization Control Register 07080708h RW DA8 DABh EQCTL4_5 Lane 4 5 Equalization Control Register 07080708h RW DAC DAFh EQCTL6_7 Lane 6 7 Equalization Control Register 07080708h RW DBO DB3h EQCTL8_9 Lane 8 9 Equalization Control Register 07080708h RW DB4 DB7h EQCTLIO_11 GE 1i Equalization Control 07080708h RW DB8 DBBh EQCTL12_13 ae 13 Equalization Control 07080708h RW DBC DBFh EQCTL14_15 A 15 Equalizatioricontrol 07080708h RW DCO DD7h RSVD Reserved Oh RO DD8 DDBh EQCFG Equalization Configuration Register F9404400h RW Datasheet Volume 2 Processor Configuration Registers intel 2 7 1 PVCCAP1 Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 1 0 2 MMR Address Offset 104 107h Reset Value 00000000h Access RO Size 32 bits BIOS Optimal Default 0000000h 5 Reset RST iias Bit Access Value PWR Description 31 7 RO Oh Reserved RSVD Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in 6 4 R Ob addition to the default VC belonging to the low priority VC LPVC 9 as Uncore group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Oh Reserved RSVD Extended VC Count EVCC
373. om SR exit to the first DDR command tXS tRFC 10ns Setup of tXS_offset is of cycles for 10 ns Range is between 3 and 11 DCLK cycles tXSDLL S Delay between DDR SR exit and the first command that requires elo eee mn Uncore Gata RD WR from DDR is in the range of 128 to 1024 DCLK cycles though all JEDEC DDRs assume 512 DCLK cycles 242 Datasheet Volume 2 Processor Configuration Registers intel 2 13 5 PM_PDWN_ config_CO Power down Configuration Register This register defines the power down CKE off operation power down mode idle timer and global per rank decision B D F Type 0 0 0 MCHBAR MCO Address Offset 40B0 40B3h Reset Value 00000000h Access RW L Size 32 bits BIOS Optimal Default 00000h Reset RST zis Bit Access Value PWR Description 31 13 RO Oh Reserved RSVD Global power down GLPDN 1 When this bit is set the power down decision is global for 12 RW L Ob Uncore channel 0 When this bit is clear a separate decision is taken for each rank Power down mode PDWN_mode Selects the mode of power down Oh No Power Down ih APD 2h PPD 3h APD PPD 4h Reserved i 5h Reserved 11 8 RW L Oh Uncore 6h PPD_DLLoff 7h APD PPD_DLLoff 8h Fh Reserved Note When selecting DLL off or APD DLL off DIMM MRO register bit 12 PPD must equal 0 Note When selecting APD PPD or APD PPD DIMM MRO register bit 12 PPD must equal 1 The value 0x0 no power down is a don t
374. omponent The Upstream 27 24 RW 0111b U e Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD Lane 1 Upstream Component Receiver Preset Hint UCRPH1 22 20 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Upstream Component Transmitter Preset UCTP1 i Transmitter Preset for an Upstream Component See the PCIe 19 16 RW 1000b U 9 Ge Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 15 RO Oh Reserved RSVD Lane 0 Downstream Component Receiver Preset Hint DCRPHO 14 12 RW 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Downstream Component Transmitter Preset DCTPO Transmitter Preset for Downstream Component The Upstream It RW 0111b U S WEN Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 7 RO Oh Reserved RSVD Lane 0 Upstream Compo
375. omponent The Upstream 27 24 RW 0111b U e Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD Lane 1 Upstream Component Receiver Preset Hint UCRPH1 22 20 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Upstream Component Transmitter Preset UCTP1 i Transmitter Preset for an Upstream Component See the PCIe 19 16 RW 1000b U 9 Ge Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 15 RO Oh Reserved RSVD Lane 0 Downstream Component Receiver Preset Hint DCRPHO 14 12 RW 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Downstream Component Transmitter Preset DCTPO Transmitter Preset for Downstream Component The Upstream It RW 0111b U S WEN Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 7 RO Oh Reserved RSVD Lane 0 Upstream Compo
376. onfiguration space is disabled and must be enabled by writing a 1 to PXPEPBAREN Device 0 offset 40h bit 0 All the bits in this register are locked in Intel TXT mode B D F Type 0 0 0 PCI Address Offset 40 47h Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 000000000h i Reset RST ar Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD PCI Express Egress Port MMIO Base Address PXPEPBAR This field corresponds to bits 38 12 of the base address PCI Express Egress Port MMIO configuration space BIOS will program this register resulting in a base address for a 4 KB block 38 12 RW 0000000h Uncore of contiguous memory address space This register ensures that a naturally aligned 4 KB space is allocated within the first 512 GB of addressable memory space System software uses this base address to program the PCI Express Egress Port MMIO register set All the bits in this register are locked in Intel TXT mode 11 1 RO Oh Reserved RSVD PXPEPBAR Enable PXPEPBAREN 0 Disable PXPEPBAR is disabled and does not claim any memory RW 0 b uncorg 1 Enable PXPEPBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers intel 2 5 12 MCHBAR Host Memory Mapped Register Range Base Register This is the base address for the H
377. ore 1 Enable MCHBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT 2 5 13 GGC GMCH Graphics Control Register All the bits in this register are Intel TXT lockable B D F Type 0 0 0 PCI Address Offset 50 51h Reset Value 0028h Access RW L RW KL Size 16 bits BIOS Optimal Default 00h 2 Reset RST or Bit Access Value PWR Description 15 RO Oh Reserved RSVD 14 RW L 0b Uncore Reserved RSVD 13 10 RO Oh Reserved RSVD Datasheet Volume 2 55 56 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 50 5ih Reset Value 0028h Access RW L RW KL Size 16 bits BIOS Optimal Default 00h Reset RST SEN Bit Access Value PWR Description GTT Graphics Memory Size GGMS This field is used to select the amount of Main Memory that is pre allocated to support the Internal Graphics Translation Table The BIOS ensures that memory is pre allocated only when Internal graphics is enabled GSM is assumed to be a contiguous physical DRAM space with DSM and BIOS needs to allocate a contiguous memory chunk 9 8 RW L Oh Uncore Hardware will derive the base of GSM from DSM only using the GSM size programmed in the register Hardware functionality in case of programming this value to Reserved is not ensured Oh No Preallocated Memory 1h 1 MB of Preallocated Memory 2h 2 MB of Preallocated Memory 3h Reserved
378. ory This is NOT necessarily the highest main memory address holes may exist in main memory address map due to addresses allocated for memory mapped I O above TOM The Intel Management Engine ME stolen size register reflects the total amount of physical memory stolen by the Intel Management Engine The Intel ME stolen memory is located at the top of physical memory The Intel ME stolen memory base is calculated by subtracting the amount of memory stolen by the Intel Management Engine from TOM Datasheet Volume 2 27 Note 2 3 4 1 28 intel Processor Configuration Registers Top of Upper Usable DRAM TOUUD The Top of Upper Usable Dram TOUUD register reflects the total amount of addressable DRAM If remap is disabled TOUUD will reflect TOM minus Intel Management Engine stolen size If remap is enabled then it will reflect the remap limit When there is more than 4 GB of DRAM and reclaim is enabled the reclaim base will be the same as TOM minus Intel ME stolen memory size to the nearest 1 MB alignment shown in the following case 2 Top of Low Usable DRAM TOLUD TOLUD register is restricted to 4 GB memory A 31 20 but the processor can support up to 32 GB limited by DRAM pins For physical memory greater than 4 GB the TOUUD register helps identify the address range in between the 4 GB boundary and the top of physical memory This identifies memory that can be directly accessed including remap address calculation
379. ory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region limit depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position with O in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all is The Protected low memory base and limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits 31 N 1 specifies a protected low memory region of size 2 N 1 bytes e Programming the protected low memory limit register with a value less than the Protected low memory base register disables the protected low memory region Software must not modify this register when protected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 6C 6Fh Reset Value 00000000h Access RW Size 32 bits BIOS Optimal Default 00000h o Reset RST Pa Bit Access Value PWR Description Protected Low Memory Limit PLML 31 20 RW 000h Uncore This register specifies the last host physical address of the DMA protected low memory region in system memory 19 0 RO Oh Reserved RSVD Datasheet Volume 2 33
380. ost Memory Mapped Configuration space There is no physical memory within this 32 KB window that can be addressed The 32 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the Host MMIO Memory Mapped Configuration space is disabled and must be enabled by writing a 1 to MCHBAREN Device 0 offset 48h bit 0 All the bits in this register are locked in Intel TXT mode The register space contains memory control initialization timing and buffer strength registers clocking registers and power and thermal management registers B D F Type 0 0 0 PCI Address Offset 48 4Fh Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 0000000000h Reset RST ioii Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Host Memory Mapped Base Address MCHBAR This field corresponds to bits 38 15 of the base address Host Memory Mapped configuration space BIOS will program this register resulting in a base address for a 32 KB block of 38 15 RW 000000h Uncore contiguous memory address space This register ensures that a naturally aligned 32 KB space is allocated within the first 512 GB of addressable memory space System software uses this base address to program the Host Memory Mapped register set All the bits in this register are locked in Intel TXT mode 14 1 RO Oh Reserved RSVD MCHBAR Enable MCHBAREN 0 Disable MCHBAR is disabled and does not claim any memory 0 i Ob Unc
381. ost read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 83h Reset Value 00h Access RW Size 8 bits BIOS Optimal Default Oh e Reset RST RS Bit Access Value PWR Description 7 6 RO Oh Reserved RSVD 0D4000 0D7FFF Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to OD7FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW 00b Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO Oh Reserved RSVD 0D0000 0D3FFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to OD3FFFh 00 DRAM Disabled All reads are sent to DRAM All writes are forwarded to DMI j 01 Read Only All reads are sent to DRAM All writes are 10 RW SE Seefe forw
382. ot connection is not implemented Device Port Type DPT 7 4 RO 4h Uncore Hardwired to 4h to indicate root port of PCI Express Root Complex PCI Express Capability Version PCIECV 3 0 RO 2h Uncore Hardwired to 2h to indicate compliance to the PCI Express Capabilities Register Expansion ECN 2 10 35 DCAP Device Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 6 0 PCI Address Offset A4 A7h Reset Value 00008000h Access RO RW O Size 32 bits BIOS Optimal Default 0000000h Reset RST Bae Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD Role Based Error Reporting RBER This bit indicates that this device implements the functionality 1 RO 1 b SS defined in the Error Reporting ECN as required by the PCI Express 1 1 specification 14 6 RO Oh Reserved RSVD Extended Tag Field Supported ETFS gt SS Ob SE Hardwired to indicate support for 5 bit Tags as a Requestor Phantom Functions Supported PFS Ke PS oub Set Not Applicable or Implemented Hardwired to 0 Max Payload Size MPS 2 0 RW O 000b Uncore Default indicates 128B max supported payload for Transaction Layer Packets TLP 188 Datasheet Volume 2 Processor Configuration Registers intel 2 10 36 DCTL Device Control Register This register provides control for PCI Express device specific capabilities The error reporting enable bits ar
383. ot supported in this device 11 D3 Support of D3cold does not require any special action 00b Uncore While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort that is not claim any downstream cycles with exception of type 0 configuration cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the processor logs as Master Aborts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States ll 106 Datasheet Volume 2 Processor Configuration Registers intel 2 6 27 SS_CAPID Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides Because this device is an integrated part of the system and not an add in device it is anticipated that this capability will never be used However it is necessary because Microsoft will test for its presence B D F Type 0 1 0 2 PCI Address Offset 88 8Bh Reset Value 0000800Dh Access RO Size 32 bits BIOS Optimal Default 0000h 5 Reset RST SA Bit Access Value PWR Description
384. ownstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD 22 20 RW Lane 1 Upstream Component Receiver Preset Hint UCRPH1 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 19 16 RW Lane 1 Upstream Component Transmitter Preset UCTP1 Transmitter Preset for an Upstream Component See the PCIe 1000b Snore Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 15 RO Oh Reserved RSVD 14 12 RW Lane 0 Downstream Component Receiver Preset Hint DCRPHO 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 RW Lane 0 Downstream Component Transmitter Preset DCTPO 0111b Uncore Transmitter Preset for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 RO Oh Reserved RSVD
385. pecifies the interrupt message upper address B D F Type 0 0 0 GFXVTBAR Address Offset 44 47h Reset Value 00000000h Access RW Size 32 bits o Reset RST EE Bit Access Value PWR Description Message upper address MUA Hardware implementations supporting Extended Interrupt Mode 31 0 RW 00000000h Uncore are required to implement this register Hardware implementations not supporting Extended Interrupt Mode may treat this field as RsvdZ 278 Datasheet Volume 2 Processor Configuration Registers intel 2 18 13 AFLOG_REG Advanced Fault Log Register This register specifies the base address of the memory resident fault log region This register is treated as RsvdZ for implementations not supporting advanced translation fault logging AFL field reported as 0 in the Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 58 5Fh Reset Value 0000000000000000h Access RO Size 64 bits BIOS Optimal Default 000h e Reset RST So a Bit Access Value PWR Description Fault Log Address FLA This field specifies the base of 4 KB aligned fault log region in system memory Hardware ignores and does not implement bits 00000000 63 HAW where HAW is the host address width 63 12 RO 00000h Uncore Software specifies the base address and size of the fault log region through this register and programs it in hardware through the SFL field in the Global Command regi
386. plements LTBWR the bit in Function 0 is of type RW and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is of type RsvdP Components that do not implement LTBWR are permitted to hardwire this bit to Ob Reset Value of this bit is Ob This bit is cleared when the port goes to DL_down state Hardware ignores the value of this bit RO Oh Reserved RSVD RW Ob Uncore ARI Forward Enable ARIFEN When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to Extended Functions in an ARI Device immediately below the Port Reset Value of this bit is Ob It must be hardwired to Ob if the ARI Forwarding Supported bit is Ob 4 0 RO Oh Reserved RSVD 128 Datasheet Volume 2 Processor Configuration Registers 2 6 48 LCAP2 Link Capabilities 2 Register B D F Type 0 1 0 2 MMR Address Offset CC CFh Reset Value 0000000Eh Access RO V Size 32 bits BIOS Optimal Default 0000000h z Reset RST Ge Bit Access Value PWR Description 31 8 RO Oh Reserved RSVD Supported Link Speeds Vector SLSV This field indicates the supported Link speed s of the associated Port For each bit a value of 1b indicates that the corresponding Link speed is supported otherwise the Link speed is not
387. ponding to bit 2 in the Supported Link Speeds Vector which is 5 0 GT s All other encodings are reserved The value in this field is undefined when the Link is not up 2 6 41 SLOTCAP Slot Capabilities Register Note PCI Express Hot Plug is not supported on the processor B D F Type 0 1 0 2 PCI Address Offset B4 B7h Reset Value 00040000h Access RW O RO Size 32 bits f Reset RST SE Bit Access Value PWR Description Physical Slot Number PSN This field indicates the physical slot number attached to this Port 31 19 RW O 0000h Uncore BIOS Requirement This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis No Command Completed Support NCCS When set to 1b this bit indicates that this slot does not generate software notification when an issued command is completed by 18 RO 1b Uncore the Hot Plug Controller This bit is only permitted to be set to 1b if the hot plug capable port is able to accept writes to all fields of the Slot Control register without delay between successive writes Reserved for Electromechanical Interlock Present EIP 17 RO Ob Uncore When set to 1b this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot Datasheet Volume 2 119 120 Processor Configuration Registers B D F Type Address Offset Reset Value Access Si
388. port A 0 read from this bit indicates that the Virtual Channel is currently disabled 31 RW Ob Uncore BIOS Requirement 1 To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link 2 To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link 3 Software must ensure that no traffic is using a Virtual Channel at the time it is disabled 4 Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO Oh Reserved RSVD Virtual Channel private ID VCPID 26 24 RW 010b Uncore This field assigns a VC ID to the VC resource This field cannot be modified when the VC is already enabled 23 8 RO Oh Reserved RSVD 7 RO Ob Uncore Traffic Class m Virtual Channel private Map TCMVCPM Traffic Class Virtual Channel private Map TCVCPM It is recommended that private TC6 01000000b is the only value that should be programmed into this field for VCp traffic which will be translated by a virtualization engine and TC2 00000010b is the only value that should be programmed into this field for VCp traffic which will not be translated by a virtualization engine This strategy can simplify debug and limit validation permutations BIOS Requirement Program this field with the value 100010b which maps TC2 and TC6 to VCp 6 1 RW 00h Uncore 0 RO
389. pped_pl1 Set if the PPO IA frequency requested by OS was 2 RW 000900001 Uncore clipped by PL1 POWER_LIMIT_1 power limiting algorithm ppO_clipped_thermals 1 RW 00000000h Uncore Set if the PPO IA frequency requested by OS was clipped by internal Thermal Throttling algorithm ppO_clipped_ext_prochot 0 RW 00000000h Uncore Set if the PPO IA frequency requested by OS was clipped by external PROCHOT indication Datasheet Volume 2 305 intel Processor Configuration Registers 2 19 11 SSKPD Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them It is for the convenience of BIOS and graphics drivers B D F Type 0 0 0 MCHBAR PCU Address Offset 5D10 5D17h Reset Value 0000000000000000h Access RWS RW Size 64 bits Reset RST Gene Bit Access Value PWR Description d Scratchpad Data SKPD 63 32 RWS 00000000h Powergood 2 WORDs of data storage Reserved for Future Use RWSVD3 31 30 RWS 00b Powergood Bit 30 controls the way BIOS calculate WM3 value Bit 31 is reserved for future use DDRIO Power down Shutdown Latency Time WM3 Number of microseconds to access memory if memory is in Self Refresh SR with DDRIO in Power down EPG mode 0 5 us granularity 00h 0 us Oih 0 5 us 29 24 RWS 00h Powergood Camm Ug 3Fh 31 5 us Note The value in this field corresponds to the memory latency requested t
390. press devices have a register that can disable the routing of I O cycles to the PCI Express device The processor responds to I O cycles initiated on PCI Express or DMI with an UR status Upstream I O cycles and configuration cycles should never occur If one does occur the transaction will complete with an UR completion status I O reads that lie within 8 byte boundaries but cross 4 byte boundaries are issued from the processor as 1 transaction It will be divided into 2 separate transactions I O writes that lie within 8 byte boundaries but cross 4 byte boundaries will be split into 2 transactions by the processor PCI Express I O Address Mapping The processor can be programmed to direct non memory I O accesses to the PCI Express bus interface when processor initiated I O cycle addresses are within the PCI Express I O address range This range is controlled using the I O Base Address IOBASE and I O Limit Address IOLIMIT registers in Device 1 Functions 0 1 2 or Device 6 configuration space Address decoding for this range is based on the following concept The top 4 bits of the respective I O Base and I O Limit registers correspond to address bits A 15 12 of an I O address For the purpose of address decoding the device assumes that lower 12 address bits A 11 0 of the I O base are zero and that address bits A 11 0 of the I O limit address are FFFh This forces the I O address range alignment to 4 KB boundary and produces a size gr
391. processor Graphics device B D F Type 0 2 0 PCI Address Offset 2 3h Reset Value 0152h Access RO V RO FW Size 16 bits e Reset RST a Bit Access Value PWR Description Device Identification Number MSB DID_MSB This is the upper part of a 16 bit value assigned to the Graphics device 15 4 RO FW 015h Uncore Valid Values 15h 16h Device Identification Number SKU DID_SKU Those are bits 3 2 of the 16 bit value assigned to the processor Graphics device 3 2 RO V 00b Uncore SKU Bits 3 2 Mobile DI Device Identification Number LSB DID_LSB 1 0 RO V 10b Uncore This is the lower part of a 16 bit value assigned to the processor Graphics device Datasheet Volume 2 149 150 Processor Configuration Registers PCICMD2 PCI Command Register This 16 bit register provides basic control over the IGD s ability to respond to PCI cycles The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory Access Size B D F Type Address Offset Reset Value 0 2 0 PCI 4 5h 0000h RW RO 16 bits BIOS Optimal Default 00h z Reset RST a Bit Access Value PWR Description 15 11 RO Oh Reserved RSVD Interrupt Disable INTDIS FcR This bit disables the device from asserting INTx 10 RW Ob Uncore 9 Enable the assertion of this device s INTx signal 1 Disable the assertion of this device s INTx signal
392. pt control bits This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A0O A3h Reset Value 80000000h Access RW L RO V Size 32 bits BIOS Optimal Default 00000000h Reset RST ER Bit Access Value PWR Description Interrupt Mask IM 0 No masking of interrupt When an invalidation event condition is detected hardware issues an interrupt message using the Invalidation Event Data and Invalidation Event 31 RW L 1b Uncore Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set 336 Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 0 0 VCOPREMAP Address Offset AO A3h Reset Value 80000000h Access RW L RO V Size 32 bits BIOS Optimal Default 00000000h Bit Access E sit Description Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF field set completed setting the IWC field in the Invalidation Completion Status register e If the IWC field in the Invalidation Completion Status register was already set at the time of setting this field it is not tre
393. r Configuration Registers 2 10 38 LCAP Link Capabilities Register This register indicates PCI Express device specific capabilities Access Size B D F Type Address Offset Reset Value 0 6 0 PCI AC AFh 0521CC42h RO RW O RO V RW OV 32 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 31 24 23 22 RO RO Port Number PN Indicates the PCI Express port number for the given PCI Express link Matches the value in Element Self Description 31 24 The value if this field differs between root ports 2h device 1 Function 0 3h device 1 Function 1 4h device 1 Function 2 5h device 6 Function 0 Oh Reserved RSVD 05h Uncore 21 RO Link Bandwidth Notification Capability LBNC A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms This capability is required for all Root Ports and Switch downstream ports supporting Links wider than x1 and or multiple Link speeds This field is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to 0b 1b Uncore 20 RO Data Link Layer Link Active Reporting Capable DLLLARC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of reporting the DL_Activ
394. r DMA remapping hardware implementations on platforms supporting Intel TXT and is optional for non Intel TXT platforms Since the protected memory region needs to be enabled before the MVMM is launched hardware must support enabling of the protected memory region independently from enabling the DMA remapping hardware As part of the secure launch process the SINIT AC module verifies the protected memory regions are properly configured and enabled Once launched the MVMM can setup the initial DMA remapping structures in protected memory to ensure they are protected while being setup before enabling the DMA remapping hardware units To optimally support platform configurations supporting varying amounts of main memory the protected memory region is defined as two non overlapping regions e Protected Low memory Region This is defined as the protected memory region below 4 GB to hold the MVMM code private data and the initial DMA remapping structures that control DMA to host physical addresses below 4 GB DMA remapping hardware implementations on platforms supporting Intel TXT are required to support protected low memory region5 e Protected High memory Region This is defined as a variable sized protected memory region above 4 GB enough to hold the initial DMA remapping structures for managing DMA accesses to addresses above 4 GB DMA remapping hardware implementations on platforms supporting Intel TXT are required to support protected high
395. r State Support D2PSS 26 RO Ob Uncore Hardwired to 0 to indicate that the D2 power management state is NOT supported D1 Power State Support D1PSS 25 RO Ob Uncore Hardwired to 0 to indicate that the D1 power management state is NOT supported 104 Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 1 0 2 PCI Address Offset 80 83h Reset Value C8039001h Access RO RO V Size 32 bits Bit Access sts pod Description Auxiliary Current AUXC 24 22 RO 000b Uncore Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements Device Specific Initialization DSI 21 RO Ob Uncore Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it Auxiliary Power Source APS 20 RO 0b SE Hardwired to 0 PME Clock PMECLK 19 RO Ob Uncore Hardwired to 0 to indicate this device does NOT support PME generation PCI PM CAP Version PCIPMCV A value of 011b indicates that this function complies with Revision 1 2 of the PCI Power Management Interface Specification Was previously hardwired to 02h to indicate there are 4 bytes of power management registers implemented and that this device complies with revision 1 1 of the PCI Power Management Interface Specification 18 16 RO 011b Uncore Pointer to Next Capability PNC This contains a pointer to the next item in the capa
396. r isochronous traffic The PCI Express Egress port PXPEPBAR must also be programmed appropriately b The snoop not required SNR bit must be set Any transaction with the SNR bit not set will be treated as an unsupported request c MSI and peer transactions will be treated as unsupported requests d No pacer arbitration or TWRR arbitration will occur Never remaps to a different port PCH takes care of Egress port remapping The PCH will meter TCm Intel ME accesses and Intel High Definition Audio TC1 access bandwidth os Datasheet Volume 2 Processor Configuration Registers intel e Internal Graphics GMADR writes and GMADR reads are not supported 4 VCm accesses a See DMI2 specification for TC mapping to VCm VCm access only map to Intel ME stolen DRAM These transactions carry the direct physical DRAM address no redirection or remapping of any kind will occur This is how the PCH Intel Management Engine accesses its dedicated DRAM stolen space b DMI block will decode these transactions to ensure only Intel ME stolen memory is targeted and abort otherwise c VCm transactions will only route non snoop d VCm transactions will not go through VTd remap tables e The remapbase remaplimit registers to not apply to VCm transactions Figure 2 7 Example DMI Upstream VCO Memory Map Upstream Initiated VCO Cycle Memory Map 27B TOM total physical DRAM REMAPLIMIT TOUUD REMAPBASE 4GB FEE
397. r reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link B D F Type 0 1 0 2 PCI Address Offset AA ABh Reset Value 0000h Access RW1C RO Size 16 bits BIOS Optimal Default 000h e Reset RST So as Bit Access Value PWR Description 15 6 RO Oh Reserved RSVD Transactions Pending TP 0 All pending transactions including completions for any outstanding non posted requests on any used virtual channel have been completed 5 R b o 9 Uncore 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes Not Applicable or Implemented Hardwired to 0 4 RO Oh Reserved RSVD Unsupported Request Detected URD This bit indicates that the Function received an Unsupported 3 RW1iC Ob Uncore Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Fatal Error Detected FED This bit indicates status of Fatal errors detected Errors are 2 RW1C 0b Uncore logged in this register regardless of whether error reporting is enabled or not in the Device Control register For a multi Function device each Function indic
398. ramming the REMAPBASE and REMAPLIMIT registers based on the values in the TOLUD TOM and Intel ME stolen size registers e The amount of remapped memory defined by the REMAPBASE and REMAPLIMIT registers must be equal to the amount of physical memory between the TOLUD and the lower of either 4 GB or TOM minus the Intel ME stolen size e Addresses of MMIO region must not overlap with any part of the Logical Address Memory Remap range e When TOM is equal to TOLUD remap is not needed and must be disabled by programming REMAPBASE to a value greater than the value in the REMAPLIMIT register Interaction with other Overlapping Address Space The following Memory Mapped IO address spaces are all logically addressed below 4 GB where they do not overlap the logical address of the re mapped memory region GFXGTTstolen At TOLUD GFXstolensize to TOLUD GFXstolen At TOLUD GFXstolensize GFXGTTstolensize to TOLUD GFXstolensize TSEG At TOLUD GFXstolensize GFXGTTstolensize TSEGSIZE to TOLUD GFXGTTstolensize GFXstolensize High BIOS Reset vector just under 4 GB boundary Positive decode to DMI occurs XAPIC At fixed address below 4 GB Local APIC At fixed address below 4 GB Datasheet Volume 2 33 DN t Processor Configuration Registers Note Note 34 MSI Interrupts At fixed address below 4 GB GMADR 64 bit BARs GTTMMADR 64 bit BARS MBASE MLIMIT PXPEPBAR 39 bit BAR DMIBAR 39 bit BAR MCHBAR 39 bit
399. ransition to the Disabled state using Recovery from LO LOs or L1 states Link retraining happens automatically on the 0 toi transtion 4 RO Oh just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state After clearing this bit software must honor timing requirements defined in the PCIe Specification Section 6 6 1 with respect to the first Configuration Read following a Conventional Reset Read Completion Boundary RCB 3 R Ob ee Hardwired to 0 to indicate 64 byte 2 RO Oh Reserved RSVD Active State PM ASPM 1 0 RW 00b Uncore This field controls the level of ASPM Active State Power Management supported on the given PCI Express Link Datasheet Volume 2 intel 2 6 40 118 Processor Configuration Registers LSTS Link Status Register The register indicates PCI Express link status Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 1 0 2 PCI B2 B3h 1001h RWI1C RO V RO 16 bits Oh Bit Access Reset Value RST PWR Description 15 RW1C Ob Uncore Link Autonomous Bandwidth Status LABWS This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width without the port transitioning through DL_Down status for reasons other than to attempt to correct unreliable link operation This bit must be s
400. rating system was clipped by HOT indication from VR on SVID ppO_clipped_pI2 5 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped by PL2 POWER_LIMIT_2 power limiting algorithm ppO_clipped_gt_driver 4 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped by GT driver 3 RW 00000000h Reserved RSVD ppO_clipped_pl1i 2 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped by PL1 POWER_LIMIT_1 power limiting algorithm ppO_clipped_thermals 1 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped by internal Thermal Throttling algorithm ppO_clipped_ext_prochot 0 RW 00000000h Uncore Set if the PPO IA frequency requested by the operating system was clipped by external PROCHOT indication Datasheet Volume 2 303 intel 2 19 10 Note 304 Processor Configuration Registers PCU_MMIO_FREQ_CLIPPING_CAUSE_LOG Register This register is the log of the frequency clipping cause in MMIO for both Power plane 0 IA and Power plane 1 GT The bit definitions are the same as in PCU_MMIO_FREQ_CLIPPING_CAUSE_STATUS register the processor will constantly or in the status to give a log of any clipping since the last clear Software can clear the log by writing zeros to this register There is no assurance of atomicity of software read clear and
401. re ignores and does not implement bits 63 HAM 38 12 RUAL GE oncore where HAW is the host address width Reads of this field return the value that was last programmed to it 11 3 RO Oh Reserved RSVD Queue Size QS This field specifies the size of the invalidation request queue A 2 0 RW L Oh Uncore value of X in this field indicates an invalidation request queue of 2 X 4 KB pages The number of entries in the invalidation queue is 2 X 8 Datasheet Volume 2 335 intel Processor Configuration Registers 2 21 22 ICS _REG Invalidation Completion Status Register This register reports completion status of invalidation wait descriptor with Interrupt Flag IF set This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 9C 9Fh Reset Value 00000000h Access RWI1CS Size 32 bits BIOS Optimal Default 00000000h e Reset RST SE Bit Access Value PWR Description 31 1 RO Oh Reserved RSVD Invalidation Wait Descriptor Complete IWC This bit indicates completion of Invalidation Wait Descriptor 0 RW1icS Ob Powergood with Interrupt Flag IF field set Hardware implementations not supporting queued invalidations implement this field as Rsvdz 2 21 23 IECTL_REG Invalidation Event Control Register This register specifies the invalidation event interru
402. ream Component The Upstream 27 24 RW 0111b U e Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD Lane 1 Upstream Component Receiver Preset Hint UCRPH1 22 20 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 1 Upstream Component Transmitter Preset UCTP1 i Transmitter Preset for an Upstream Component See the PCIe 19 16 RW 1000b U 9 neare Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 15 RO Oh Reserved RSVD Lane 0 Downstream Component Receiver Preset Hint DCRPHO 14 12 RW 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Downstream Component Transmitter Preset DCTPO Transmitter Preset for Downstream Component The Upstream It RW 0111b U S WEN Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 7 RO Oh Reserved RSVD Lane 0 Upst
403. ream Component Receiver Preset Hint UCRPHO 6 4 RW 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Lane 0 Upstream Component Transmitter Preset UCTPO x Transmitter Preset for an Upstream Component See the PCIe 0 RW 1000b 2 S Unicore Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 Datasheet Volume 2 139 intel Processor Configuration Registers 2 7 10 EQCTL4_5 Lane 4 5 Equalization Control Register Lane Equalization Control Register 2 lanes are combined lane 0 is the lower numbered lane lane 1 is the higher numbered lane Access Size B D F Type Address Offset Reset Value 0 1 0 1 MMR DAS DABh 07080708h RW 32 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 31 30 28 RO RW Oh Reserved RSVD Lane 1 Downstream Component Receiver Preset Hint DCRPH1 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 27 24 RW Lane 1 Downstream Component Transmitter Preset DCTP1 0111b Uncore Transmitter Prese
404. rgood 3Fh 31 5 us Note The value in this field corresponds to the memory latency requested to the Display Engine when Memory is in Self Refresh The Display LP1 latency and watermark values GTTMMADR offset 45108h should be programmed to match the latency in this register 7 6 RWS 00b Powergood Reserved for Future Use RWSVDO Reserved for Future Use Normal Latency Time WMO This field provides the number of microseconds to access memory for normal memory operations 0 1 us granularity 00h 0 us Oih 0 1 us 02h 0 2 us 3Fh 6 3 us Note For the processor the worst case latency is 0 6 us 5 0 RWS 000000b Powergood WMO latency is the sum of e Partial Intel High Definition Audio request in front of the Display Request 100 ns e Refresh just in front of the Intel High Definition Audio request 300 ns e Maintenance ZQCAL some clocks 130 ns DDR 1067 to 80 ns DDR 1600 e Activate 15 ns e CAS 15 ns e SA Roundtrip 15 ns Total 525 ns DDR 1600 575 ns DDR 1067 Datasheet Volume 2 307 Processor Configuration Registers intel 2 20 PXPEPBAR Registers Table 2 23 PXPEPBAR Address Map on Register Symbol Register Name Reset Value Access 0 13h RSVD Reserved Oh RO 14 17h EPVCORCTL EP VC 0 Resource Control 800000FFh RO RW 18 9Fh RSVD Reserved 2 20 1 EPVCORCTL EP VC 0 Resource Control Register This register controls the resources associated with Egress
405. rnal PROCHOT indication 15 RW 00000000h Uncore PPO_clipped Set if the PPO IA frequency requested by OS was clipped ppO_clipped_n_core_turbo 14 RW 00000000h Uncore Set if the PPO IA frequency requested by OS was clipped but current frequency is lower than MAX_TURBO n cores Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 0 0 MCHBAR PCU Address Offset 5C24 5C27h Default Value 00000000h Access RW Size 32 bits Reset RST Bit Access Description Value PWR ppO_clipped_non_turbo 13 RW 00000000h Uncore Set if the PPO IA frequency requested by OS was clipped but current frequency is lower than MAX_NON_TURBO 12 9 RW 00000000h Reserved RSVD ppO_clipped_edp Set if the PPO IA frequency requested by OS was 8 on SEBES pagers clipped by EDP limit Vmax Iccmax Reliability and so on pp0O_clipped_mct 7 RW 00000000h Uncore Set if the PPO IA frequency requested by OS was clipped by Multi Core Turbo demotion algorithm ppO_clipped_hot_vr 6 RW 00000000h Uncore Set if the PPO IA frequency requested by OS was clipped by HOT indication from VR on SVID ppO_clipped_pI2 Set if the PPO IA frequency requested by OS was a PRH Uncore clipped by PL2 POWER_LIMIT_2 power limiting algorithm ppO_clipped_gt_driver 4 RW 00000000h Uncore Set if the PPO IA frequency requested by OS was clipped by GT driver 3 RW 00000000h Reserved RSVD ppO_cli
406. rocessor Configuration Registers 2 10 29 2 10 30 intel MSI_CAPID Message Signaled Interrupts Capability ID Register When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item a message to a predefined memory address The reporting of the existence of this capability can be disabled by setting MSICH CAPL 0 7Fh In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability B D F Type 0 6 0 PCI Address Offset 90 91h Reset Value AOO5h Access RO Size 16 bits Bit Access la iR HA Description Pointer to Next Capability PNC 15 8 RO AOh Uncore This field contains a pointer to the next item in the capabilities list which is the PCI Express capability Capability ID CID 7 0 RO O5h Uncore Value of 05h identifies this linked list item capability structure as being for MSI registers MC Message Control Register System software can modify bits in this register but the device is prohibited from doing So If the device writes the same message multiple times only one of those messages is ensured to be serviced If all of them must be serviced the device must not generate the same message again until the driver services the earlier one B D F Type 0 6 0 PCI Address Offset 92 93h Reset Value 0000h Access RO RW Size 16 bits
407. rogramming Model The memory boundaries of interest are Bottom of Logical Address Remap Window defined by the REMAPBASE register which is calculated and loaded by BIOS Top of Logical Address Remap Window defined by the REMAPLIMIT register which is calculated and loaded by BIOS Bottom of Physical Remap Memory defined by the existing TOLUD register Top of Physical Remap Memory which is implicitly defined by either 4 GB or TOM minus Intel Management Engine stolen size Mapping steps 1 2 3 rae Oy ON a 9 Determine TOM Determine TOM minus Intel ME stolen size Determine MMIO allocation Determine TOLUD Determine graphics stolen base Determine graphics GTT stolen base Determine TSEG base Determine remap base limit Determine TOUUD The following diagrams show the three possible general cases of remapping 30 Case 1 Less than 4 GB of Physical Memory no remap Case 2 Greater than 4 GB of Physical Memory Case 3 4 GB or Less of Physical Memory Datasheet Volume 2 Processor Configuration Registers D t I H 2 3 4 5 1 Case 1 Less than 4 GB of Physical Memory no remap Figure 2 5 Case 1 Less than 4 GB of Physical Memory no remap Host System View Physical Memory DRAM Controller View 4GB TOM L 1 MB aligned ME UMA TOUUD BASE ME BASE 1 MB aligned 1 MB aligned Wasted Only if 4 GB minus PCI PCI MMIO MMIO space is greater than 4 GB minus ME stolen base TOLUD BASE
408. rols the root port s SERR messaging The processor communicates the SERR condition by sending an SERR message to the PCH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Register In addition for Type 1 configuration space header devices this bit when set enables transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface This bit does not affect the transmission of forwarded ERR_COR messages 0 The SERR message is generated by the root port only under conditions enabled individually through the Device Control Register 1 The root port is enabled to generate SERR messages which will be sent to the PCH for specific root port error conditions generated detected or received on the secondary side of the virtual PCI to PCI bridge The status of SERRs generated is reported in the PCISTS register RO Oh Reserved RSVD RW Ob Uncore Parity Error Response Enable PERRE This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set RO Ob Uncore VGA Palette Snoop VGAPS
409. rotected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 78 7Fh Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 000000000000h Reset RST SE Bit Access Value PWR Description 63 39 RO Oh Reserved RSVD Protected High Memory Limit PHML This register specifies the last host physical address of the DMA 38 20 RW 00000h Uncore protected high memory region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width 19 0 RO Oh Reserved RSVD Datasheet Volume 2 333 intel Processor Configuration Registers 2 21 19 IQH_REG Invalidation Queue Head Register This register indicates the invalidation queue head This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 80 87h Reset Value 0000000000000000h Access RO V Size 64 bits BIOS Optimal Default 0000000000000h 2 R t RST S Bit Access Noe ER Description 63 19 RO Reserved RSVD Queue Head QH This field specifies the offset 128 bit aligned to the invalidation 18 4 RO V 0000h Uncore queue for the command that will be fetched next by hardware Hardware resets this field to 0 whenever the queued invalidation is disabled QIES field Clear in the Glo
410. rroneous entries require explicit invalidation Hardware implementations of this architecture must support a value of 0 in this field Protected High Memory Region PHMR 6 RO 1b Uncore 0 Protected high memory region is not supported 1 Protected high memory region is supported Protected Low Memory Region PLMR 5 RO 1b Uncore 0 Protected low memory region is not supported 1 Protected low memory region is supported Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 8 Fh Reset Value 00C0000020E60262h Access RO Size 64 bits BIOS Optimal Default 000h d Reset RST Pay Bit Access Value PWR Description Required Write Buffer Flushing RWBF 0 No write buffer flushing is needed to ensure changes to 4 RO Ob Uncore memory resident structures are visible to hardware 1 Software must explicitly flush the write buffers to ensure updates made to memory resident remapping structures are visible to hardware Advanced Fault Logging AFL 0 Advanced fault logging is not supported Only primary fault 3 RO Ob Uncore logging is supported 1 Advanced fault logging is supported Number of domains supported ND 000 Hardware supports 4 bit domain ids with support for up to 16 domains 001 Hardware supports 6 bit domain ids with support for up to 64 domains 010 Hardware supports 8 bit domain ids with support for up to
411. s Bit Access SE BaT Description Maximum Latency Value MLV 7 0 RO 00h Uncore The IGD has no specific requirements for how often it needs to access the PCI bus 2 8 21 MSAC Multi Size Aperture Control Register This register determines the size of the graphics memory aperture in Function 0 and in the trusted space Only the system BIOS will write this register based on pre boot address allocation efforts but the graphics may read this register to determine the correct aperture size System BIOS needs to save this value on boot so that it can reset it correctly during S3 resume B D F Type 0 2 0 PCI Address Offset 62h Reset Value 02h Access RW RW K Size 8 bits BIOS Optimal Default Oh i Reset RST Ge Bit Access Value PWR Description 7 4 RW Oh Wncore Reserved RW RSVDRW Scratch Bits Only Have no physical effect on hardware 3 RO Oh Reserved RSVD Untrusted Aperture Size High LHSASH This field is used in conjunction with LHSASL The description below is for both fields LHSASH amp LHSASL 11 Bits 28 27 of GMADR are RO allowing 512 MB of GMADR 10 Illegal Programming 01 Bit 28 of GMADR is RW but bit 27 of GMADR is RO allowing 256 MB of GMADR 00 Bits 28 27 of GMADR are RW allowing 128 MB of GMADR 2 RW K Ob Uncore Untrusted Aperture Size Low LHSASL This field is used in conjunction with LHSASH The description below is for both fields
412. s SERR messaging The processor communicates the SERR condition by sending an SERR message to the PCH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Register In addition for Type 1 configuration space header devices this bit when set enables transmission by the primary interface of 8 RW Ob Uncore ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface This bit does not affect the transmission of forwarded ERR_COR messages 0 The SERR message is generated by the root port only under conditions enabled individually through the Device Control Register 1 The root port is enabled to generate SERR messages which will be sent to the PCH for specific root port error conditions generated detected or received on the secondary side of the virtual PCI to PCI bridge The status of SERRs generated is reported in the PCISTS register 7 RO Oh Reserved RSVD Parity Error Response Enable PERRE This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set 6 RW Ob Uncore 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set 5 RO op Wncore VGA Palette Snoop VGAPS Not Applicable or
413. s been written once it becomes read only 2 5 9 SID Subsystem Identification Register This value is used to identify a particular subsystem B D F Type 0 0 0 PCI Address Offset 2E 2Fh Reset Value 0000h Access RW O Size 16 bits Bit Access dere gt Description Subsystem ID SUBID 15 0 RW O 0000h Uncore This field should be programmed during BIOS initialization After it has been written once it becomes read only Datasheet Volume 2 53 intel 2 5 10 2 5 11 54 Processor Configuration Registers CAPPTR Capabilities Pointer Register The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list B D F Type 0 0 0 PCI Address Offset 34h Reset Value EOh Access RO Size 8 bits Reset RST ZE Bit Access Value PWR Description Capabilities Pointer CAPPTR 7 0 RO EOh Uncore Pointer to the offset of the first capability ID register block In this case the first capability is the product specific Capability Identifier CAPIDO PXPEPBAR PCI Express Egress Port Base Address Register This is the base address for the PCI Express Egress Port MMIO Configuration space There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the EGRESS port MMIO c
414. s field controls DMA accesses to the protected low memory and protected high memory regions 0 Protected memory regions are disabled 1 Protected memory regions are enabled DMA requests accessing protected memory regions are handled as follows When DMA remapping is not enabled all DMA requests accessing protected memory regions are blocked When DMA remapping is enabled e DMA requests processed as pass through Translation Type value of 10b in Context Entry and accessing the protected memory regions are blocked DMA requests with translated address AT 10b and accessing the protected memory regions are blocked DMA requests that are subject to address remapping and accessing the protected memory regions may or may not be blocked by hardware For such requests software must not depend on hardware protection of the protected memory regions and instead program the DMA remapping page tables to not allow DMA to protected memory regions Remapping hardware access to the remapping structures are not subject to protected memory region checks DMA requests blocked due to protected memory region violation are not recorded or reported as remapping faults Hardware reports the status of the protected memory enable disable operation through the PRS field in this register Hardware implementations supporting DMA draining must drain any in flight translated DMA requests queued within the Root Complex before indicating the protected memor
415. s register controls the read write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 85h Reset Value 00h Access RW Size 8 bits BIOS Optimal Default Oh e Reset RST ZS Bit Access Value PWR Description 7 6 RO Oh Reserved RSVD OE4000 0E7FFF Attribute HIENABLE This field controls the steering of read and write cycles that
416. s register is locked by Intel TXT 3 2 RO Oh Reserved RSVD 1 0 RW 00b Uncore OC8000 OCBFFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from O0C8000h to OCBFFFh 00 DRAM Disabled All reads are sent to DRAM All writes are forwarded to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 67 Processor Configuration Registers 2 5 24 PAM3 Programmable Attribute Map 3 Register This register controls the read write and shadowing attributes of the BIOS range from DOOOOh to D7FFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the h
417. s set CAS latency in DCLK cycles tCL This field is the Delay from CAS command to data out of DDR pins This does not define the sample point in the IO This is defined by training in round trip register and other registers because this is also affected by board delays 11 8 RW L 6h Uncore Delay from CAS command to data out of DDR pins Range is 5 15 Notes 1 This does not define the sample point in the IO This is defined by training in round trip register and other registers because this is also affected by board delays 2 The range of 12 15 is not yet defined by JEDEC will be tested only when such definition will exist tRP in DCLK cycles tRP 7 4 RW L 6h SN PRE to ACT same bank delay range is 4 15 DCLK cycles tRCD in DCLK cycles tRCD 3 0 RW L 6h Uncore ACT to CAS RD or WR same bank delay tRCD range is between 4 and 15 240 Datasheet Volume 2 Processor Configuration Registers intel 2 13 2 TC_RAP_CO Timing of DDR Regular Access Parameters Register Thie register is for the regular timing parameters in DCLK cycles B D F Type 0 0 0 MCHBAR MCO Address Offset 4004 4007h Reset Value 86104344h Access RW L Size 32 bits Bit Access ce Ban Description 1n 2N or 3N selection CMD_stretch This field defines the operation mode of the command 31 30 RW L 10b Uncore 00 N operation 10 2N operation 11 3N operation Command 3 state options CMD_3st
418. s to the appropriate destination DRAM or DMI Snooped accesses from PCI Express or DMI to this region are snooped on processor caches Non snooped accesses from PCI Express or DMI to this region are always sent to DRAM Graphics translated requests to this region are not allowed If such a mapping error occurs the request will be routed to C_0000 Writes will have the byte enables de asserted Datasheet Volume 2 21 intel 2 3 2 Processor Configuration Registers Main Memory Address Range 1 MB TOLUD This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the processor as programmed in the TOLUD register The processor will route all addresses within this range to the DRAM unless it falls into the optional TSEG optional ISA Hole or optional IGD stolen VGA memory Figure 2 3 Main Memory Address Range FFFF_FFFFh Contains Dev 0 1 2 6 7 BARS amp PCH PCI ranges 0100_0000h 00F0_0000h 0010_0000h Oh 4 GB Max FLASH APIC Intel TXT PCI Memory Range TOLUD IGD IGGTT TSEG TSEG_BASE DPR Main Memory 16MB ISA Hole optional 15MB Main Memory 1MB DOS Compatibility Memory OMB 2 3 2 1 ISA Hole 15 MB 16 MB The ISA Hole is enabled in the Legacy Access Control Register in Device 0 configuration space If no hole is created the processor will route the request to DRA
419. served RSVD Channel 1 Status CHANNEL1_STATUS The format is for each channel and is defined as follows 00 Cold 01 Warm 15 8 RO V 00h Uncore 11 Hot Bits 8 9 Rank O Channel 1 Bits 10 11 Rank 1 Channel 1 Bits 12 13 Rank 2 Channel 1 Bits 14 15 Rank 3 Channel 1 Channel 0 Status CHANNELO_STATUS The format is for each channel and is defined as follows 00 Cold 01 Warm 7 0 RO V 00h Uncore 11 Hot Bits 0 1 Rank O Channel 0 Bits 2 3 Rank 1 Channel 0 Bits 4 5 Rank 2 Channel 0 Bits 6 7 Rank 3 Channel 0 Datasheet Volume 2 299 intel Processor Configuration Registers 2 19 4 MEM_TRML_TEMPERATURE_REPORT Memory Thermal Temperature Report Register This register is used to report the thermal status of the memory The channel max temperature field is used to report the maximal temperature of all ranks Access Size B D F Type Address Offset Reset Value 0 0 0 MCHBAR PCU 58A4 58A7h 00000000h RO V 32 bits BIOS Optimal Default 00h Reset RST p Bit Access Value PWR Description 31 24 RO Oh Reserved RSVD 23 16 RO V 00h Uncore Reserved RSVD Channel 1 Maximum Temperature 15 8 RO V 00h Uncore CHANNEL1_MAX_TEMPERATURE Temperature in Degrees C Channel 0 Maximum Temperature 7 0 RO V 00h Uncore CHANNELO_MAX_TEMPERATURE Temperature in Degrees C 2 19 5 MEM_TRML_INTERRUPT Memory Thermal Interrupt Register Hardware uses this information to det
420. sh both the cached leaf and non leaf page table entries corresponding to the mappings specified by ADDR and AM fields 1 Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware may preserve the cached non leaf page table entries corresponding to mappings specified by ADDR and AM fields 5 0 RW 00h Uncore Address Mask AM The value in this field specifies the number of low order bits of the ADDR field that must be masked for the invalidation operation This field enables software to request invalidation of contiguous mappings for size aligned regions For example Mask ADDR bits Pages Value masked invalidated 0 None 1 1 12 2 2 13 12 4 3 14 12 8 4 15 12 16 When invalidating mappings for super pages software must specify the appropriate mask value For example when invalidating mapping for a 2 MB page software must specify an address mask value of at least 9 Hardware implementations report the maximum supported mask value through the Capability register 290 Datasheet Volume 2 Processor Configuration Registers intel 2 18 29 IOTLB_REG IOTLB Invalidate Register This register invalidates IOTLB The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation B D F Type 0 0 0 GFXVTBAR Address Offset 108
421. sor is implemented this bit is set when a MRL Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Ob Uncore Reserved for Power Fault Detected PFD If a Power Controller that supports power fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note that depending on hardware capability it is possible that a power fault can be detected at any time independent of the Power Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Ob Uncore Reserved for Attention Button Pressed ABP If an Attention Button is implemented this bit is set when the attention button is pressed If an Attention Button is not supported this bit must not be set Datasheet Volume 2 201 intel Processor Configuration Registers 2 10 44 RCTL Root Control Register This register allows control of PCI Express Root Complex specific parameters The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register B D F Type 0 6 0 PCI Address Offset BC BDh Reset Va
422. ss Offset g ee g S 0 3h VER_REG Version Register 00000010h RO 4 7h RSVD Reserved Oh RO S Capability Register 00C0000020 8 Fh CAP_REG E60262h RO Extended Capability Register 0000000000 7 10 17h ECAP_REG FO101Ah RO RO V 18 1Bh GCMD_REG Global Command Register 00000000h RO WO 1C 1Fh GSTS_REG Global Status Register 00000000h RO V RO ep Root Entry Table Address Register 0000000000 20 27h RTADDR_REG 000000h RW Context Command Register 0800000000 RW RW V RO 28 2Fh CCMD_REG 000000h V 30 33h RSVD Reserved Oh RO Fault Status Register RO ROS V 34 37h FSTS_REG 00000000h RW1ICS 38 3Bh FECTL_REG Fault Event Control Register 80000000h RW RO V 3C 3Fh FEDATA_REG Fault Event Data Register 00000000h RW 40 43h FEADDR_REG Fault Event Address Register 00000000h RW 44 47h FEUADDR_REG Fault Event Upper Address Register 00000000h RW 48 57h RSVD Reserved Oh RO Advanced Fault Log Register 0000000000 58 5Fh AFLOG_REG 000000h RO 60 63h RSVD Reserved Oh RO 64 67h PMEN_REG Protected Memory Enable Register 00000000h RW RO V 68 6Bh PLMBASE_REG Protected Low Memory Base Register 00000000h RW 6C 6Fh PLMLIMIT_REG Protected Low Memory Limit Register 00000000h RW 70 77h PHMBASE_REG Protected High Memory Base Register 0000000000 RW 000000h 78 7Fh PHMLIMIT_REG Protected High Memory Limit Register 0000000000 RW 000000h Invalidation Queue Head Register 0000000000 80 87h IQH_REG 000000h RO V Invalidation Queue Tail Register 0000000000 F 88 8Fh IQT_REG 000000h RW
423. ssor RO Ob Uncore Reserved for MRL Sensor State MSS This register reports the status of the MRL sensor if it is implemented 0 MRL Closed 1 MRL Open Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 6 0 PCI BA BBh 0000h RO RO V RW1C 16 bits BIOS Optimal Default 00h Bit Access Reset Value RST PWR Description Ob Uncore Reserved for Command Completed CC If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register this bit is set when a hot plug command has completed and the Hot Plug Controller is ready to accept a subsequent command The Command Completed status bit is set as an indication to host software that the Hot Plug Controller has processed the previous command and is ready to receive the next command it provides no assurance that the action corresponding to the command is complete If Command Completed notification is not supported this bit must be hardwired to Ob Note PCI Express Hot Plug is not supported on the processor 3 RW1C Ob Uncore Presence Detect Changed PDC A pulse indication that the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is changed Ob Uncore Reserved for MRL Sensor Changed MSC If an MRL sen
424. st IOTLB invalidation register is calculated as X 16 Y Snoop Control SC 0 Hardware does not support 1 setting of the SNP field in the 7 RO Ob Uncore page table entries 1 Hardware supports the 1 setting of the SNP field in the page table entries Pass Through PT 0 Hardware does not support pass through translation type in 6 RO Ob Uncore context entries 1 Hardware supports pass through translation type in context entries Caching Hints CH 0 Hardware does not support IOTLB caching hints ALH and 5 RO Ob Uncore EH fields in context entries are treated as reserved 1 Hardware supports IOLTB caching hints through the ALH and EH fields in context entries 4 RO Oh Reserved RSVD Interrupt Remapping Support IR 0 Hardware does not support interrupt remapping 3 RO V 1b Uncore 1 Hardware supports interrupt remapping Implementations reporting this field as set must also support Queued Invalidation QI Device IOTLB Support DI 0 Hardware does not support device IOTLBs 2 RO Ob Uncore 1 Hardware supports Device IOTLBs Implementations reporting this field as set must also support Queued Invalidation QI Queued Invalidation Support QI 1 RO V 1b Uncore 0 Hardware does not support queued invalidations 1 Hardware supports queued invalidations Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 10 17h Reset Value 0000000000F01
425. ster When implemented reads of this field return the value that was last programmed to it Fault Log Size FLS This field specifies the size of the fault log region pointed by the i FLA field The size of the fault log region is 2 X 4KB where X is e RO Oh Uncore the value programmed in this register When implemented reads of this field return the value that was last programmed to it 8 0 RO Oh Reserved RSVD Datasheet Volume 2 279 intel Processor Configuration Registers 2 18 14 PMEN_REG Protected Memory Enable Register This register enables the DMA protected memory regions setup through the PLMBASE PLMLIMT PHMBASE PHMLIMIT registers This register is always treated as RO for implementations not supporting protected memory regions PLMR and PHMR fields reported as Clear in the Capability register Protected memory regions may be used by software to securely initialize remapping structures in memory To avoid impact to legacy BIOS usage of memory software is recommended to not overlap protected memory regions with any reserved memory regions of the platform reported through the Reserved Memory Region Reporting RMRR structures Access Size B D F Type Address Offset Reset Value BIOS Optimal Default 0 0 0 GFXVTBAR 64 67h 00000000h RW RO V 32 bits 00000000h Bit Access Reset Value RST PWR Description 31 RW Oh Uncore Enable Protected Memory EPM Thi
426. ster in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only Access Size B D F Type Address Offset Reset Value 0 0 0 PCI 82h 00h RW 8 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 7 6 RO Oh Reserved RSVD 5 4 RW 00b Uncore OCCOOO OCFFFF Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from OCCOOOh to OCFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM Thi
427. system and not an add in device it is anticipated that this capability will never be used However it is necessary because Microsoft will test for its presence B D F Type 0 6 0 PCI Address Offset 88 8Bh Reset Value 0000800Dh Access RO Size 32 bits BIOS Optimal Default 0000h a Reset RST Baie Bit Access Value PWR Description 31 16 RO Oh Reserved RSVD Pointer to Next Capability PNC 15 8 RO 80h Uncore This field contains a pointer to the next item in the capabilities list which is the PCI Power Management capability Capability ID CID 7 0 RO ODh Uncore Value of ODh identifies this linked list item capability structure as being for SSID SSVID registers in a PCI to PCI Bridge 2 10 28 SS Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset B D F Type 0 6 0 PCI Address Offset 8C 8Fh Reset Value 00008086h Access RW O Size 32 bits J Reset RST GE Bit Access Value PWR Description Subsystem ID SSID nee S SR SE Identifies the particular subsystem and is assigned by the vendor Subsystem Vendor ID SSVID S S Identifies the manufacturer of the subsystem and is the same as 13 0 SCH gogh wagers the vendor ID which is assigned by the PCI Special Interest Group 184 Datasheet Volume 2 P
428. t Latency reported in LCAP 14 12 and the N_FTS value advertised during link training See LOSLAT at offset 22Ch RW V Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer Ob Uncore LTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no need to write a 0 RW Link Disable LD 0 Normal operation 1 Link is disabled Forces the LTSSM to transition to the Disabled state using Recovery from LO LOs or L1 states Link retraining happens automatically on 0 to 1 transition Ob Uncore just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state After clearing this bit software must honor timing requirements defined in the PCIe Specification Section 6 6 1 with respect to the first Configuration Read following a Conventional Reset RO Read Completion Boundary RCB ob oncore Hardwired to 0 to indicate 64 byte RO Oh Reserved RSVD 1 0 RW Active State PM ASPM 00b Uncore This field controls the level of ASPM Active State Power Management supported on the given PCI Express Link Datasheet Volume 2 Processor Configuration Registers D 2 10 40 LSTS Link Status Register This register indicates PCI Express link status B D F Type
429. t RST ae Bit Access Value PWR Description Memory Access Enable MAE 0 All of device s memory space is disabled 1 RW Ob Uncore 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE MLIMIT PMBASE and PMLIMIT registers IO Access Enable IOAE 0 RW Ob ncore 0 All of device s I O space is disabled 1 Enable the I O address range defined in the IOBASE and IOLIMIT registers 2 6 4 PCISTS PCI Status Register This register reports the occurrence of error conditions associated with primary side of the virtual Host PCI Express bridge embedded within the Root port Access Size B D F Type Address Offset Reset Value 0 1 0 2 PCI 6 7h 0010h RO RW1C RO V 16 bits BIOS Optimal Default Oh Bit Access Reset Value RST PWR Description 15 RW1C Ob Uncore Detected Parity Error DPE This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register On a Function with a Type 1 Configuration header the bit is set when the Poisoned TLP is received by its Primary Side Reset Value of this bit is Ob This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned peer to peer posted forwarded will not set this bit They are reported at the receiving port 14 RW1C Ob Uncore Signaled System Error SSE This bit is set when this
430. t condition The IP field is kept set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being set or other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field Software servicing all the pending interrupt status fields in the Fault Status register as follows e When primary fault logging is active software clearing the Fault F field in all the Fault Recording registers with faults causing the PPF field in Fault Status register to be evaluated as clear e Software clearing other status fields in the Fault Status register by writing back the value read from the respective fields 29 0 RO Oh Reserved RSVD 326 Datasheet Volume 2 Processor Configuration Registers 2 21 10 FEDATA_REG Fault Event Data Register This register specifies the interrupt message data B D F Type 0 0 0 VCOPREMAP Address Offset 3C 3Fh Reset Value 00000000h Access RW Size 32 bits a Reset RST Sen Bit Access Value PWR Description Extended Interrupt Message Data EIMD This field is valid only for implementations
431. t explicitly flush the write buffers to ensure updates made to memory resident remapping structures are visible to hardware Advanced Fault Logging AFL 3 RO Ob Uncore E Advanced fault logging is not supported Only primary fault logging is supported 1 Advanced fault logging is supported Number of domains supported ND 000 Hardware supports 4 bit domain ids with support for up to 16 domains 001 Hardware supports 6 bit domain ids with support for up to 64 domains 010 Hardware supports 8 bit domain ids with support for up to 256 domains 011 Hardware supports 10 bit domain ids with support for 2 0 RO 010b Uncore o den Gees pikdomain id NERT UP 100 Hardware supports 12 bit domain ids with support for up to 4K domains 100 Hardware supports 14 bit domain ids with support for up to 16K domains 110 Hardware supports 16 bit domain ids with support for up to 64K domains 111 Reserved Datasheet Volume 2 Processor Configuration Registers D 2 21 3 ECAP_REG Extended Capability Register This register reports remapping hardware extended capabilities B D F Type 0 0 0 VCOPREMAP Address Offset 10 17h Reset Value 0000000000F010DAh Access RO V RO Size 64 bits BIOS Optimal Default 00000000000h i Reset RST SA Bit Access Value PWR Description 63 24 RO Oh Reserved RSVD Maximum Handle Mask Value MHMV The value in this field indicates the maximum supported value for
432. t fault log and sets the APF field in the Fault Status register Hardware detected error associated with the Invalidation Queue setting the IQE field in the Fault Status register Hardware detected invalid Device IOTLB invalidation completion setting the ICE field in the Fault Status register Hardware detected Device IOTLB invalidation completion time out setting the ITE field in the Fault Status register If any of the status fields in the Fault Status register was already set at the time of setting any of these fields it is not treated as a 30 RO V Oh Uncore new interrupt condition The IP field is kept set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being set or other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field e Software servicing all the pending interrupt status fields in the Fault Status register as follows When primary fault logging is active software clearing the Fault F field in all the Fault Recording registers with faults causing the PPF field in Fault Status register to be evaluated as clear Software clearing ot
433. t for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD 22 20 RW Lane 1 Upstream Component Receiver Preset Hint UCRPH1 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 19 16 RW Lane 1 Upstream Component Transmitter Preset UCTP1 Transmitter Preset for an Upstream Component See the PCIe 1000b Snore Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 15 RO Oh Reserved RSVD 14 12 RW Lane 0 Downstream Component Receiver Preset Hint DCRPHO 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 RW Lane 0 Downstream Component Transmitter Preset DCTPO 0111b Uncore Transmitter Preset for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 RO Oh Reserved RS
434. t is set when the processor generates a DMI request that receives a Completer Abort completion packet Software clears this bit by writing a 1 to it 11 RO Ob Uncore Signaled Target Abort Status STAS The processor will not generate a Target Abort DMI completion packet or Special Cycle This bit is not implemented and is hardwired to a 0 Writes to this bit position have no effect 10 9 RO 00b Uncore DEVSEL Timing DEVT These bits are hardwired to 00 Writes to these bit positions have no effect Device 0 does not physically connect to PCI_A These bits are set to 00 fast decode so that optimum DEVSEL timing for PCI_A is not limited by the Host RW1C Ob Uncore Master Data Parity Error Detected DPD This bit is set when DMI received a Poisoned completion from PCH This bit can only be set when the Parity Error Enable bit in the PCI Command register is set RO 1b Uncore Fast Back to Back FB2B This bit is hardwired to 1 Writes to these bit positions have no effect Device 0 does not physically connect to PCI_A This bit is set to 1 indicating fast back to back capability so that the optimum setting for PCI_A is not limited by the Host RO Oh Reserved RSVD RO Ob Uncore 66 MHz Capable MC66 Does not apply to PCI Express Must be hardwired to 0 RO 1b Uncore Capability List CLIST This bit is hardwired to 1 to indicate to the configuratio
435. t supporting Device IOTLBs implement this bit as RsvdZ Invalidation Queue Error IQE Hardware detected an error associated with the invalidation queue This could be due to either a hardware error while fetching a descriptor from the invalidation queue or hardware 4 RW1CS Ob Powergood detecting an erroneous or invalid descriptor in the invalidation queue At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting queued invalidations implement this bit as RsvdZ Advanced Pending Fault APF When this field is clear hardware sets this field when the first fault record at index 0 is written to a fault log At this time a 3 RO Ob Uncore fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 34 37h Reset Value 00000000h Access RW1CS ROS V RO Size 32 bits BIOS Optimal Default 00000h d Reset RST SE Bit Access Value PWR Description Advanced Fault Overflow AFO Hardware sets this field to indicate advanced fault log overflow condition At this time a fault event is generated based on the 2 RO Ob Uncore programming of the Fault Event Control regist
436. t the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in 9 8 RO 00b Wncore which case the read value is undefined 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Datasheet Volume 2 121 Processor Configuration Registers Access Size B D F Type Address Offset Reset Value 0 1 0 2 PCI B8 B9h 0000h RO 16 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 7 6 RO Reserved for Attention Indicator Control AIC If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled directly by the downstream port through implementation specific mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a val
437. t this device does not support the power management data register RW Ob Uncore PME Enable PMEE This bit indicates that this device does not generate PME assertion from any D state 0 PME generation not possible from any D State 1 PME generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 4 RO Oh Reserved RSVD RO 1b Uncore No Soft Reset NSR When set to 1 this bit indicates that the device is transitioning from D3hot to DO because the power state commands do not perform an internal reset Configuration context is preserved Upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits When clear the devices do not perform an internal reset upon transitioning from D3hot to DO using software control of the power state bits Regardless of this bit the devices that transition from a D3hot to DO by a system or bus segment reset will return to the device state DO uninitialized with only PME context preserved if PME is supported and enabled RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset 84 87h Reset Value 00000008h Access RO RW Size 32 bits BIOS Optimal Default 000000h Reset RST Saut Bit Access Value PWR Description
438. target is MMIO Registers This field selects a GTT offset if the target is the GTT Target TARG FLR 00 MMIO Registers 1 0 RW 00b Uncore 01 GTT 1X Reserved 2 9 2 Data MMIO Data Register MMIO_DATA A 32 bit I O write to this port is re directed to the MMIO register GTT location pointed to by the MMIO index register A 32 bit I O read to this port is re directed to the MMIO register GTT location pointed to by the MMIO index register B D F Type 0 2 0 PCIIO Address Offset 4 7h Reset Value 00000000h Access RW Size 32 bits e Reset RST BS Bit Access Value PWR Description FLR MMIO Data Window DATA 31 0 RW 00000900 Uncore This field is the data field associated with the IO2MMIO access 160 Datasheet Volume 2 Processor Configuration Registers 2 10 PCI Device 6 Registers Table 2 13 PCI Device 6 Register Address Map Sheet 1 of 2 ge paca Register Name Reset Value Access 0 ih VID Vendor Identification 8086h RO 2 3h DID Device Identification 015Dh RO FW 4 5h PCICMD PCI Command 0000h RW RO 6 7h PCISTS PCI Status 0010h RW1C RO RO 8h RID Revision Identification 00h RO FW 9 Bh CC Class Code 060400h RO Ch CL Cache Line Size 00h RW Dh RSVD Reserved Oh RO Eh HDR Header Type 8ih RO Fh RSVD Reserved Oh RO 18h PBUSN Primary Bus Number 00h RO 19h SBUSN Secondary Bus Number 00h RW
439. te When selecting APD PPD or APD PPD DIMM MRO register bit 12 PPD must equal 1 The value Oh no power down is a don t care 11 8 RW L Oh Hee Oh No Power Down 1h APD 2h PPD 3h APD PPD 4h Reserved 5h Reserved 6h PPD_DLLoff 7h APD PPD_DLLoff 8h Fh Reserved Power down idle timer PDWN_idle_counter 7 0 RW L 00h Uncore This field defines the rank idle period in DCLK cycles that causes power down entrance 258 Datasheet Volume 2 Processor Configuration Registers intel 2 17 2 PM_CMD_PWR Power Management Command Power Register This register defines the power contribution of each command ACT PRE CAS read and CAS write Assumption is that the ACT is always followed by a PRE although not immediately and REF commands are issued in a fixed rate and there is no need to count them The register has 3 8 bit fields B D F Type 0 0 0 MCHBAR_MCBCAST Address Offset 4F84 4F87h Reset Value 00000000h Access RW LV Size 32 bits BIOS Optimal Default 00h Reset RST SE Bit Access Value PWR Description 31 24 RO Oh Reserved RSVD 23 16 RW LV 00h Uncore Power contribution of CAS Write command PWR_CAS_W 15 8 RW LV 00h Uncore Power contribution of CAS Read command PWR_CAS_R Power contribution of RAS command and PRE command PWR_RAS_PRE 7 0 RW LV 00h Uncore Power contribution of RAS command and PRE command The value should be the sum of the two com
440. ted as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 80 87h Reset Value 0000000000000000h Access RO V Size 64 bits BIOS Optimal Default 0000000000000h x R t RST SR Bit Access Valse GA Description 63 19 RO Reserved RSVD Queue Head QH Specifies the offset 128 bit aligned to the invalidation queue for 18 4 RO V 0000h Uncore the command that will be fetched next by hardware Hardware resets this field to 0 whenever the queued invalidation is disabled QIES field Clear in the Global Status register 3 0 RO Reserved RSVD 2 18 20 IQT_REG Invalidation Queue Tail Register This register indicates the invalidation tail head This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 88 8Fh Reset Value 0000000000000000h Access RW L Size 64 bits BIOS Optimal Default 0000000000000h 3 Reset RST Foii Bit Access Value PWR Description 63 19 RO Reserved RSVD Queue Tail QT 18 4 RW L 0000h Uncore This field specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software 3 0 RO Reserved RSVD Datasheet Volume 2 285 intel 2 18 21 Processor Configuration Registers IQA_REG Invalidation
441. terrupt request Datasheet Volume 2 337 Processor Configuration Registers intel 2 21 25 IEADDR_REG Invalidation Event Address Register This register specifies the Invalidation Event Interrupt message address This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A8 ABh Reset Value 00000000h Access RW L Size 32 bits BIOS Optimal Default Oh Reset RST Bit Access Value PWR Description Message address MA S When fault events are enabled the contents of this register 1 2 RW L h 3 09009000 Mavote specify the DWord aligned address bits 31 2 for the interrupt request 1 0 RO Oh Reserved RSVD 2 21 26 IEUADDR_REG Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address B D F Type 0 0 0 VCOPREMAP Address Offset AC AFh Reset Value 00000000h Access RW L Size 32 bits Bit Access Aarme E Description Message Upper Address MUA Hardware implementations supporting Queued Invalidations and 31 0 RW L 00000000h Uncore Extended Interrupt Mode are required to implement this register Hardware implementations not supporting Queued Invalidations or Extended Interrupt Mode may treat this field as RsvdZ 338 Datasheet Volu
442. the amount of main memory that is pre allocated to support the Internal Graphics Translation Table 0 2 MB options For each of the following five device functions e Device 1 Function 0 PCIe x16 Controller e Device 1 Function 1 PCIe x8 Controller e Device 1 Function 2 PCIe x4 Controller Datasheet Volume 2 17 intel Processor Configuration Registers e Device 6 Function 0 PCIe x4 Controller MBASE MLIMIT PCI Express port non prefetchable memory access window PMBASE PMLIMIT PCI Express port prefetchable memory access window PMUBASE PMULIMIT PCI Express port upper prefetchable memory access window IOBASE IOLIMIT PCI Express port I O access window e Device 2 Function 0 Integrated Graphics Device IGD IOBAR I O access window for internal graphics Through this window address data register pair using I O semantics the IGD and internal graphics instruction port registers can be accessed Note this allows accessing the same registers as GTTMMADR The IOBAR can be used to issue writes to the GTTMMADR or the GTT table GMADR Internal graphics translation window 128 MB 256 MB 512 MB window GTTMMADR This register requests a 4 MB allocation for combined Graphics Translation Table Modification Range and Memory Mapped Range GTTADR will be at GTTMMADR 2 MB while the MMIO base address will be the same as GTTMMADR The rules for the above programmable ranges are
443. the status of the Data Link Control and Management State Machine It returns a 1b to indicate the 13 RO V 0b Uncore DL_Active state 0b otherwise This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the 12 RO 1b Uncore presence of a reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connector Link Training LTRN This bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the 11 RO V Ob U r Gear Retrain Link bit but Link training has not yet begun Hardware clears this bit when the LTSSM exits the Configuration Recovery state once Link training is complete Datasheet Volume 2 195 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size 0 6 0 PCI B2 B3h 1001h RW1C RO V RO 16 bits BIOS Optimal Default Oh Bit Access ee Af Description 10 RO Oh Reserved RSVD Negotiated Link Width NLW This field indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 00h Reserved 9 4 RO V 00h Uncore 01h X1 02h X2 04h X4 08h X8 1
444. the value 06h indicating a Bridge device Sub Class Code SUBCC e This is an 8 bit value that indicates the category of Bridge into 15 R h SZ O SR EES which the Host Bridge device falls The code is 00h indicating a Host Bridge Programming Interface PI 7 0 RO 00h Uncore This is an 8 bit value that indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device 52 Datasheet Volume 2 Processor Configuration Registers intel 2 5 7 HDR Header Type Register This register identifies the header layout of the configuration space No physical register exists at this location B D F Type 0 0 0 PCI Address Offset Eh Reset Value 00h Access RO Size 8 bits Bit Access PaE id Description PCI Header HDR This field always returns 0 to indicate that the Host Bridge is a 7 R h S 9 SR SS single function device with standard header layout Reads and writes to this location have no effect 2 5 8 SVID Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem B D F Type 0 0 0 PCI Address Offset 2C 2Dh Reset Value 0000h Access RW O Size 16 bits Bit Access a Ea Description Subsystem Vendor ID SUBVID 2 This field should be programmed during boot up to indicate the 13 0 Rg SEN uncore vendor of the system board After it ha
445. ting advanced 28 RO Ob Uncore fault logging It indicates the advanced fault logging status 0 Advanced Fault Logging is not enabled 1 Advanced Fault Logging is enabled Write Buffer Flush Status WBFS This field is valid only for implementations requiring write buffer flushing This field indicates the status of the write buffer flush command It is e set by hardware when software sets the WBF field in the Global Command register e cleared by hardware when hardware completes the write buffer flushing operation 27 RO Ob Uncore Queued Invalidation Enable Status QIES This field indicates queued invalidation enable status 0 Queued invalidation is not enabled 1 Queued invalidation is enabled 26 RO V Ob Uncore ll Interrupt Remapping Enable Status IRES This field indicates the status of Interrupt remapping hardware 0 Interrupt remapping hardware is not enabled 1 Interrupt remapping hardware is enabled 25 RO V Ob Uncore Interrupt Remapping Table Pointer Status IRTPS This field indicates the status of the interrupt remapping table pointer in hardware This field is 24 RO V 0b Uncore e cleared by hardware when software sets the SIRTP field in the Global Command register e set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register 23 0 RO Oh Reserved RSVD
446. tion time out At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting device Device IOTLBs implement this bit as RsvdZ RO Ob Uncore Invalidation Completion Error ICE Hardware received an unexpected or invalid Device IOTLB invalidation completion This could be due to either an invalid ITag or invalid source id in an invalidation completion response At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device IOTLBs implement this bit as RsvdZ RW1cS Ob Powergood Invalidation Queue Error IQE Hardware detected an error associated with the invalidation queue This could be due to either a hardware error while fetching a descriptor from the invalidation queue or hardware detecting an erroneous or invalid descriptor in the invalidation queue At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting queued invalidations implement this bit as RsvdZ RO Ob Uncore Advanced Pending Fault APF When this field is clear hardware sets this field when the first fault record at index 0 is written to a fault log At this time a fault event is generated based on the programming of the Fault Event Control register Sof
447. tional for Root Ports The Root port does not support completion timeout disable Completion Timer Ranges Supported CTOR Device Function support for the optional Completion Timeout programmability mechanism This mechanism allows system software to modify the Completion Timeout value This field is applicable only to Root Ports Endpoints that issue Requests on their own behalf and PCI Express to PCI PCI X 3 0 R 0000b o 9 Unicore Bridges that take ownership of Requests issued on PCI Express For all other Functions this field is reserved and must be hardwired to 0000b 0000b Completion Timeout programming not supported the Function must implement a time out value in the range 50 us to 50 ms Datasheet Volume 2 127 intel 2 6 47 Processor Configuration Registers DCTL2 Device Control 2 Register B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 1 0 2 PCI C8 C9h 0000h RW V RW 16 bits 0000h Bit Access Reset Value RST PWR Description 15 12 RO Oh Reserved RSVD 11 Ob Uncore Latency Tolerance and BW Reporting Mechanism Enable LTREN When set to 1b this bit enables the Latency Tolerance amp Bandwidth Requirement Reporting LTBWR mechanism This bit is required for all Functions that support the LTBWR Capability For a Multi Function device associated with an upstream port of a device that im
448. tor 1 The device uses the same physical reference clock that the platform provides on the connector 11 RO V Ob Uncore Link Training LTRN When set this bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the LTSSM exits the Configuration Recovery state once Link training is complete Datasheet Volume 2 Processor Configuration Registers D B D F Type 0 1 0 2 PCI Address Offset B2 B3h Reset Value 1001h Access RW1C RO V RO Size 16 bits BIOS Optimal Default Oh d Reset RST Pay Bit Access Value PWR Description 10 RO Oh Reserved RSVD Negotiated Link Width NLW This field indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 00h Reserved 9 4 RO V 00h Uncore Oih X1 02h X2 04h X4 08h X8 10h X16 All other encodings are reserved Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link The encoding is the binary value of the bit location in the Supported Link Speeds Vector in the Link Capabilities 2 register 3 0 RO Oh that corresponds to the current Link speed For example a value of 0010b in this field indicates that the current Link speed is that corres
449. training sequences 0001b 2 5 Gb s Target Link Speed 0010b 5 Gb s Target Link Speed All other encodings are reserved If a value is written to this field that does not correspond to a speed included in the Supported Link Speeds field the result is undefined The Reset Value of this field is the highest link speed supported by the component as reported in the Supported Link Speeds field of the Link Capabilities Register unless the corresponding platform form factor requires a different Reset Value For both Upstream and Downstream ports this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode 2 12 28 LSTS2 Link Status 2 Register B D F Type 0 0 0 DMIBAR Address Offset 9A 9Bh Reset Value 0000h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST e Bit Access Value PWR Description 15 1 RO Oh Reserved RSVD Current De emphasis Level CURDELVL When the Link is operating at 5 GT s speed this reflects the level of de emphasis 0 RO V Ob Uncore 4 3 5 dB Ob 6 dB When the Link is operating at 2 5 GT s speed this bit is Ob 238 Datasheet Volume 2 Processor Configuration Registers 2 13 O Registers intel MCHBAR Registers in Memory Controller Channel Table 2 16 MCHBAR Registers in Memory Controller Channel 0 Register Address Map
450. tributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 80h Reset Value 00h Access RW Size 8 bits BIOS Optimal Default 00h e Reset RST zis Bit Access Value PWR Description 7 6 RO Oh Reserved RSVD OFOOOO OFFFFF Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from OF_0000h to OF_FFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW 00b Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 0 RO Oh Reserved RSVD Datasheet Volume 2 65 Processor Configuration Registers 2 5 22 PAM1i Programmable
451. ts of the Message Address register and is incapable of generating a 64 bit memory address Multiple Message Enable MME System software programs this field to indicate the actual 6 4 RW 000b Uncore number of messages allocated to this device This number will be equal to or less than the number actually requested The encoding is the same as for the MMC field below Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device 000 1 Message Requested All of the following are reserved in this implementation 3 o 000 GE S R 00b Uncore 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved MSI Enable MSIEN This bit controls the ability of this device to generate MSIs 0 RW Ob Uncore 9 MSI will not be generated 1 MSI will be generated when we receive PME messages INTA will not be generated and INTA Status PCISTS1 3 will not be set Datasheet Volume 2 109 intel Processor Configuration Registers 2 6 31 MA Message Address Register B D F Type 0 1 0 2 PCI Address Offset 94 97h Reset Value 00000000h Access RW RO Size 32 bits d Reset RST Geen Bit Access Value PWR Description Message Address MA S Used by system software to assign an MSI address to the ane RW 99090009 uncore device The device handles an MSI by writing the padded contents of the MD register to this address Force DWord Align FDW
452. tware writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ Datasheet Volume 2 275 276 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 34 37h Reset Value 00000000h Access RO ROS V RW1CS Size 32 bits BIOS Optimal Default 00000h Reset RST Ae Bit Access Value PWR Description Advanced Fault Overflow AFO Hardware sets this field to indicate advanced fault log overflow condition At this time a fault event is generated based on the 2 RO Ob Uncore programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ Primary Pending Fault PPF This field indicates if there are one or more pending faults logged in the fault recording registers Hardware computes this field as the logical OR of Fault F fields across all the fault recording registers of this remapping hardware unit 1 ROS V Ob Powergood 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The FRI field is updated by hardware whenever the PPF field is set by hardware Also depending on the programming of Fault Event Control register a fault event is generated when hardware sets this field Primary Fault Overflow PFO Hardware sets this field to indicat
453. ub class and a register specific programming interface B D F Type 0 6 0 PCI Address Offset 9 Bh Reset Value 060400h Access RO Size 24 bits Bit Access ere it Description Base Class Code BCC 23 16 RO 06h Uncore Indicates the base class code for this device This code has the value 06h indicating a Bridge device Sub Class Code SUBCC 15 8 RO 04h Uncore Indicates the sub class code for this device The code is 04h indicating a PCI to PCI Bridge Programming Interface PI 7 0 RO 00h Uncore Indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device 2 10 7 CL Cache Line Size Register B D F Type 0 6 0 PCI Address Offset Ch Reset Value 00h Access RW Size 8 bits Bit Access neser if Description Cache Line Size CLS 7 0 RW 00h Uncore Implemented by PCI Express devices as a read write field for legacy compatibility purposes but has no impact on any PCI Express device functionality 2 10 8 HDR Header Type Register B D F Type 0 6 0 PCI Address Offset Eh Reset Value 81ih Access RO Size 8 bits Bit Access PEE E Description Header Type Register HDR Device 1 returns 81h to indicate that this is a multi function 7 0 RO 8ih Uncore device with bridge header layout Device 6 returns Oth to indicate that this is a single funct
454. ue of 00b 00b Uncore RO Reserved for Hot plug Interrupt Enable HPIE When set to 1b this bit enables generation of an interrupt on enabled hot plug events Reset Value of this field is Ob If the Hot plug Capable field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Ob Uncore RO Reserved for Command Completed Interrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 1b this bit enables software notification when a hot plug command is completed by the Hot Plug Controller If Command Completed notification is not supported this bit must be hardwired to Ob Ob Uncore RO Presence Detect Changed Enable PDCE Ob Uncore When set to 1b this bit enables software notification on a presence detect changed event RO Reserved for MRL Sensor Changed Enable MSCE When set to ib this bit enables software notification on a MRL Ob Uncore sensor changed event If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob RO Reserved for Power Fault Detected Enable PFDE When set to 1b this bit enables software notification on a power Ob Uncore fault event If Power Fault detection is not supported this bit is permitted to be read only with a value of Ob
455. ult in a DWord read from PEG at 3B0 BE Eh and a DWord read from DMI at 3B4 BE 7h Since the processor will not issue I O writes crossing the DWord boundary this special case does not exist for writes Summary of decode priority 1 Internal Graphics VGA if enabled gets 03COh O3CFh always O3BOh O3BBh if MSR 0 0 MSR is I O register 03C2 03D0h 03DFh if MSR O 1 Note 03BCh O3BFh never decodes to IGD 3BCh 3BEh are parallel port I Os and 3BF is only used by true MDA devices apparently 2 Else If MDA Present if VGA on PEG is enabled DMI gets x3B4 5 8 9 A F any access with any of these bytes enabled regardless of the other BEs 3 Else If VGA on PEG is enabled PEG gets x3BOh x3BBh x3COh x3CFh x3D0h x3DFh 4 Else if ISA Enable 1 DMI gets upper 768 bytes of each 1K block 5 Else IOBASE IOLIMIT apply I O Mapped Registers The processor contains two registers that reside in the processor I O address space the Configuration Address CONFIG_ADDRESS Register and the Configuration Data CONFIG_DATA Register The Configuration Address Register enables disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window Datasheet Volume 2 Processor Configuration Registers 2 5 Table 2 8 intel PCI Device 0 Function O Configuration Space Reg
456. used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only Access Size B D F Type Address Offset Reset Value 0 0 0 PCI 86h 00h RW 8 bits BIOS Optimal Default Oh Bit Access Reset RST Value PWR Description 7 6 RO Oh Reserved RSVD 5 4 RW 00b Uncore OECOOO OEFFFF Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from OECOOOh to OEFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT
457. usted guest address width of the corresponding page table structure Adjusted guest address widths supported by hardware are reported through the SAGAW field Implementations are recommended to support MGAW at least equal to the physical addressability host address width of the platform 15 13 RO Oh Reserved RSVD Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9008020660262h Access RO Size 64 bits BIOS Optimal Default 000h d Reset RST Pare Bit Access Value PWR Description Supported Adjusted Guest Address Widths SAGAW This 5 bit field indicates the supported adjusted guest address widths which in turn represents the levels of page table walks for the 4 KB base page size supported by the hardware implementation A value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported The adjusted guest address widths corresponding to various bit positions within this 12 8 RO 00010b Uncore field are 0 30 bit AGAW 2 level page table 1 39 bit AGAW 3 level page table 2 48 bit AGAW 4 level page table 3 57 bit AGAW 5 level page table 4 64 bit AGAW 6 level page table Software must ensure that the adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field Ca
458. visit http www intel com technology platform technology intel amt No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE Intel TXT also requires the system to contain a TPM vi s For more information visit http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM Functionality performance or other benefits will vary depending on hardware and software configurations Software applications may not be compatible with all operating systems Consult your PC manufacturer For more information visit http www intel com go virtualization Warning Altering clock frequency and or voltage may i reduce system stability and useful life of the system and processor ii cause the processor and other system components to fail iii cause reductions in system performance iv cause additional heat or other damage and v affect system data integrity Intel has not tested and does not warranty the operation of the processor beyond its specifications Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled
459. ways routed to VCO Datasheet Volume 2 Processor Configuration Registers D 2 7 6 VCORSTS VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 1 0 2 MMR Address Offset 11A 11Bh Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST SCH Bit Access Value PWR Description 15 2 RO Oh Reserved RSVD VCO Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control 1 RO V 1b Uncore initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Oh Reserved RSVD 2 7 7 PEG_TC PCI Express Completion Timeout Register This register reports PCI Express configuration control of PCI Express Completion Timeout related parameters that are not required by the PCI Express specification B D F Type 0 1 0 2 MMR Address Offset 208h Access RW e Reset RST ae Bit Access eeh GC Description 000000000 Reserved RSVD 31 15
460. wer Down 1h APD 2h PPD 3h APD PPD 4h Reserved 5h Reserved 11 8 RW L Oh Uncore 6h PPD_DLLoff 7h APD PPD_DLLoff 8h Fh Reserved Note When selecting DLL off or APD DLL off DIMM MRO register bit 12 PPD must equal 0 Note When selecting APD PPD or APD PPD DIMM MRO register bit 12 PPD must equal 1 The value Oh no power down is a don t care Power down idle timer PDWN_idle_counter 7 0 RW L 00h Uncore This field defines the rank idle period in DCLK cycles that causes power down entrance Datasheet Volume 2 Processor Configuration Registers D 2 14 5 TC_RFP_Ci Refresh Parameters Register This register provides refresh parameters B D F Type 0 0 0 MCHBAR MCL Address Offset 4694 4697h Reset Value 0000980Fh Access RW L Size 32 bits BIOS Optimal Default 0000h Reset RST a Bit Access Value PWR Description 31 18 RO Oh Reserved RSVD Double Refresh Control DOUBLE_REFRESH_CONTROL This field will allow the double self refresh enable disable 17 16 RW L 00b adore 00 Double refresh rate when DRAM is WARM HOT 01 Force double self refresh regardless of temperature 10 Disable double self refresh regardless of temperature 11 Reserved Refresh panic WM Refresh_panic_wm tREFI count level in which the refresh priority is panic default is 15 12 RW L 9h Uncore 9 It is recommended to set the panic WM at least to 9 in order to use the maximum no refresh period possible
461. when in the Recovery state Ob Uncore This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns Datasheet Volume 2 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset BO Bih Reset Value 0000h Access RW RO RW V Size 16 bits BIOS Optimal Default 00h g Reset RST sce Bit Access Value PWR Description Common Clock Configuration CCC 0 Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock 6 RW Ob Uncore 1 Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the LOs Exit Latency reported in LCAP 14 12 and the N_FTS value advertised during link training See LOSLAT at offset 22Ch Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer 3 RWE ob Uncore LTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no need to write a 0 Link Disable LD 0 Normal operation 1 Link is disabled Forces the LTSSM to t
462. within Device 2 Function 0 Class Code register is 80 1 RW L Ob Uncore BIOS Requirement BIOS must not set this bit to 0 if the GMS field bits 7 3 of this register pre allocates no memory This bit MUST be set to 1 if Device 2 is disabled either using a fuse or fuse override CAPIDO_A IGD 1 or using a register DEVEN 3 0 This register is locked by Intel TXT lock 0 Enable 1 Disable GGC Lock GGCLCK aiden bb Uncore When set to 1b this bit will lock all bits in this register 2 5 14 DEVEN Device Enable Register This register allows for enabling disabling of PCI devices and functions that are within the processor package The following table bit definitions describe the behavior of all combinations of transactions to devices controlled by this register All the bits in this register are Intel TXT Lockable Datasheet Volume 2 B D F Type 0 0 0 PCI Address Offset 54 57h Reset Value 0000209Fh Access RW L RO RW Size 32 bits BIOS Optimal Default 000000h 3 Reset RST Saas Bit Access Value PWR Description 31 15 RO Oh Reserved RSVD Chap Enable D7EN 0 Bus 0 Device 7 is disabled and not visible 1 Bus 0 Device 7 is enabled and visible 14 RW 0b Uncore Non production BIOS code should provide a setup option to enable Bus 0 Device 7 When enabled Bus 0 Device 7 must be initialized in accordance to standard PCI device initialization procedures PEG60 Enable D
463. wnstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 23 RO Oh Reserved RSVD 22 20 RW Lane 1 Upstream Component Receiver Preset Hint UCRPH1 000b Uncore Receiver Preset Hint for Upstream Component The upstream component may use this hint for receiver equalization See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 19 16 RW Lane 1 Upstream Component Transmitter Preset UCTP1 Transmitter Preset for an Upstream Component See the PCIe 1000b Snore Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 15 RO Oh Reserved RSVD 14 12 RW Lane 0 Downstream Component Receiver Preset Hint DCRPHO 000b Uncore Receiver Preset Hint for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 RW Lane 0 Downstream Component Transmitter Preset DCTPO 0111b Uncore Transmitter Preset for Downstream Component The Upstream Component must pass on this value in the EQ TS2 s See the PCIe Base Specification 3 0 Section 4 2 3 for details The encodings are defined in Section 4 2 3 2 RO Oh Reserved RSVD
464. writes to all fields of the Slot Control register without delay between successive writes Reserved for Electromechanical Interlock Present EIP 17 RO Ob Uncore When set to 1b this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot Datasheet Volume 2 Processor Configuration Registers Size B D F Type Address Offset Reset Value Access 0 6 0 PCI B4 B7h 00040000h RW O RO 32 bits Bit Access Reset Value RST PWR Description 16 15 00b Uncore Slot Power Limit Scale SPLS This field specifies the scale used for the Slot Power Limit Value 00 1 0x 01i 0 1x 10 0 01x 11 0 001x If this field is written the link sends a Set_Slot_Power_Limit message 14 7 RW O 00h Uncore Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by slot Power limit in Watts is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set_Slot_Power_Limit message RO Ob Uncore Reserved for Hot plug Capable HPC When set to 1b this bit indicates that this slot is capable of supporting hot plug operations RO Ob Uncore Reserved for Hot plug Surprise HPS When set to 1b this bit indicates that an adapter present in this slot might
465. y Address Base MBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 3 0 RO Oh Reserved RSVD Datasheet Volume 2 97 DN t Processor Configuration Registers Note Note 98 MLIMIT Memory Limit Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCI Express memory ac
466. y region as enabled through the PRS field 30 1 RO Oh Reserved RSVD RO V Oh Uncore Protected Region Status PRS This field indicates the status of protected memory regions 0 Protected memory region s disabled 1 Protected memory region s enabled 280 Datasheet Volume 2 Processor Configuration Registers D t I H 2 18 15 PLMBASE_REG Protected Low Memory Base Register This register sets up the base address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant zero bit position with O in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software must setup the protected low memory region below 4 GB Software must not modify this register when protected memory regions are enabled PRS field set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 68 6Bh Reset Value 00000000h Access RW Size 32 bits
467. ys mapped to the main memory controlled by the memory controller Legacy Video Area A_0000h B_FFFFh The legacy 128 KB VGA memory range frame buffer 000A_0000h 000B_FFFFh can be mapped to IGD Device 2 to PCI Express Device 1 or Device 6 and or to the DMI Interface The appropriate mapping depends on which devices are enabled and the programming of the VGA steering bits Based on the VGA steering bits priority for VGA mapping is constant The processor always decodes internally mapped devices first Non SMM mode processor accesses to this range are considered to be to the Video Buffer Area as described above The processor always positively decodes internally mapped devices namely the IGD and PCI Express Subsequent decoding of regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA configuration bits VGA Enable amp MDAP This region is also the default for SMM space Datasheet Volume 2 Processor Configuration Registers 2 3 1 3 Compatible SMRAM Address Range A_0000h B_FFFFh When compatible SMM space is enabled SMM mode processor accesses to this range route to physical system DRAM at 000A_0000h 000B_FFFFh PCI Express and DMI originated cycles to enable SMM space are not allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the VGA device DMI initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port Monochrome Adapter MDA Range
468. ze Bit Access Reset RST Value 0 1 0 2 PCI B4 B7h 00040000h RW O RO 32 bits PWR Description 16 15 RW O 00b Slot Power Limit Scale SPLS This field specifies the scale used for the Slot Power Limit Value 00 1 0x 01 0 1x 10 0 01x 11 0 001x If this field is written the link sends a Set_Slot_Power_Limit message Uncore 14 7 RW O 00h Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by slot Power limit in Watts Uncore is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set_Slot_Power_Limit message RO Ob Reserved for Hot plug Capable HPC Uncore When set to 1b this bit indicates that this slot is capable of supporting hot plug operations RO Ob Reserved for Hot plug Surprise HPS When set to 1b this bit indicates that an adapter present in this Uncore Slot might be removed from the system without any prior notification This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation RO Ob Reserved for Power Indicator Present PIP Uncore When set to 1b this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot RO

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