Dataram DTM64370A memory module
Contents
1. PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tease 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Mon 0 50 Mon 0 51 Von V 1 UO Reference Voltage VREFCA 0 49 Vop 0 50 Von 0 51 Voo V 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 VIH DC VREF 0 1 Vpop V Logical Low Logic 0 ViL oC Vss Veer 0 1 V AC Input Logic Levels Single Ended Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac VREF 0 175 vV Logical Low Logic 0 ViL ac Vrer 0 175 V Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 4 DRPATAR2. 0 V PARAMETER Symbol Test Condition Max Unit Value Operating One Bank Active 1550 Operating current One bank ACTIVATE to PRECHARGE 1305 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 1395 mA Precharge Current Precharge Power Ipp2P Precharge power down current Slow exit 846 T Down Current Precharge Power Ipp2P Precharge power down current Fast exit 900 MA Down Current Precharge Quiet xx Precharge quiet standby current Standby Current oecH EE Precharge Standby lpp2N Precharge standby current 1050 mA Current Active Povver Dovvn Ibo3P Active power down current 990 mA Current Active Standby xx Active standby current Curvent Ipp3N 1310 mA Operating Burst x Burst write operating current Write Current Geh ae L Operating Burst x Burst read operating current Read Current oi 110 mA Burst Refresh Ipp5 Refresh current 1940 mA Current Self Refresh Ipp6 Self refresh temperature current MAX Tc 85 C 246 mA Current Operating Bank A interleave Read lbo7 All bank interleaved read current 2160 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Deet EERSTEN Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 6 IYPDATARAM DTM64370A NE 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM AC
3. Tale d Keel i mees za ue oi oi e t sa di Features 240 pin JEDEC compliant DIMM 133 35 mm vvide by 30 mm high Ty DTM64370A 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Operating Voltage 1 5V 0 075 I O Type SSTL_15 On board DC temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 12 8 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 9 10 and 11 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully RoHS Compliant Pin Configuration Identification DTM64370A 512MX72 4GB 2Rx8 PC3 12800R 11 11 B1 Performance range Clock Module Speed CL trep Ze 800 MHz PC3 12800 11 11 11 667 MHz PC3 10600 10 10 10 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 1 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64370A is a registered 512Mx72 memory module which conforms to JEDEC s DDR3 PC3 12800 standard The assembly is Dual Rank Each Rank is comprised of nine 256Mx8 DDR3 Samsung SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmabl
4. 1 0 R ODT 1 0 R omg VTT IRS 1 0 All 22 OHMS IS0 18 BAJ2 0 A 15 0 IRAS ICAS MWE CKEO CKE1 ODTO Ko PAR IN CKO 120 OHMS CKO RESET 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM TDQSR13 DQRI39 32 OH DQSR5 DQSR5 DMRS TDQSR14 o g a Votz0 RANK 1 DQRI47 40 O 1 0 7 0 DQSRE IDQSRE DMR6 TDQSR15 Da OO oO o an Oo oO o 26 268 88 26 26846 a a aa Ei a aa E ES E S DQRI55 48 OH 1 0 7 0 VO 7 0 DQSR7 O DQSR7 O DMR7O TDQSR16O DQR 63 56 TO SDRAMS IRSO IRSI BAJ2 0 R A 14 0 R IRASR ICASR WER CKEOR CKEIR ODTOR ODTIR IERR OUT LR CLK 1 0 LCLK 1 0 REG PLL IL R CLK 1 0 SDRAMS CK1 120 OHMS ICK1 All 240 OHMS ZQ eee ae Vss Vop All 39 OHMS 100 nF VDD Al390Hms 100 LCLK 1 0 al RCLK 1 0 RCLK 1 0 DECOUPLING VDDSPD Serial PD VDD e All Devices VREF DQ All SDRAMs Vss I All Devices VREF CA All SDRAMs VIT gt _ AISDRAMS EVENT TEMPERATURE MONITOR SERIAL PD A 2 Document 06214 Revision A 05 Jul 11 Dataram Corporation O 2011 Page 3 DODATARAM DTM64370A 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Opera vue E E TE Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability
5. 2 Bit 0 Primary bus width in bits Ox0B Bit 4 Bit 3 Bus vvidth extension in bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend 1 Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor Ox11 Bit 7 Bit 4 Fine Timebase FTB Dividend 10 Medium Timebase MTB Dividend 1 MTB 0x01 0 125ns 11 Medium Timebase MTB Divisor 8 MTB 0x08 0 125ns 12 SDRAM Minimum Cycle Time tCKmin UNUSED CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 Bit 3 CL 7 OxFC Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 15 CAS Latencies Supported Most Significant Byte 0x00 Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 8 IYPDATARAM DTM64370A 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Oper Wue aed Pestova Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble 1 Bit 7 Bit 4 tRC Most Significant Nibble 1 Minimum Active to Precharge Delay Time tRASmin Least Significant Byte Minimum Active to Active Refresh Delay Time tRCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Mo
6. 4Vss 134DM1 164 CB6 194 Mon 224 DQ54 ODT 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Voo 105 DQ50 M35NC 165 CB7 195 ODTO 225 DQ55 SA 2 0 SPD Address 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 1166 Vss 196 A13 226 Vss SCL SPD Clock Input 17Vss 47 Vss 77 ODT1 107Vss 137 DQ14 167 NC TEST 197 Mon 227 DQ60 SDA SPD Data Input Output 18 DQ10 W Ven 78 Voo 108 DQ56 138 DQ151168 IRESET 1198183 NC 228 DQ61 JEVENT Temperature Sensing 19DQ11 49 Vyr 79 S2 NC 109DQ57 f139Vss 169 CKE1 199 Vss 229 Vss IRESET Reset for register and DRAMs 20Vss 50 CKEO 80 Vss 110Vss 140 DQ201170 Voo 200 DQ36 230 DM7 PAR_IN Parity bit for Addr Ctrl 21 DQ16 151 Von 81 DQ32 111 DQS7f141 DQ21 171 A15 201 DQ37 231 NC ERR_OUT Error bit for Parity Error 22 DQ17 52 BA2 82 DQ33 112 DQS7 42 Vss 172 A14 202 Vss 232 Vss A12 BC Combination input Addr12 Burst Chop 23Vss 53 Err_Our 83 Vss 113Vss 143 DM2 1173 Voo 203 DMA 233 DQE2 A10 AP Combination input Addr10 Auto precharge 24 IDQS2154 Von 84 DQS4 114 DQ58 HAAN 174 A1218c 204 Nc 234 DQ63 Vss Ground 25 DQS2 55 A11 85 DQS4 115 DQ59 f145 Vss 175 A9 205 Vss 235 Vss Ven Power 26Vss 56 A7 86 Vss 116Vss 146 DQ221176 Voo 206 DQ38 236 Vbosro VppsPo SPD EEPROM Power 27 DQ18 157 Voo 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 Vrerna Reference Voltage for DQ S 28 DQ19 58 A5 88 DQ35 118SCL f148Vss 178 A6 208 Vss 238 SDA Vrerca Reference Voltage for CA 29Vss 59A4 89 Vss 119SA2 ag DQ28 179 Voo 209 DQ44 239 Vss Vor Termination V
7. AM Opera uue E E TE DTM64370A 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu pr DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix F090 ZPS y Capacitance Ta 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO ICKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 1 5 2 5 DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 3 5 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 HA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current loL 10 10 HA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 5 Gester DIME4370A NE 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss
8. CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 vvvvvv dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 12
9. Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 75 13 125 20 ns CAS to CAS Command Delay tceco 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tok 1 5 1 875 ns Clock Low Level VVidth teL avg 0 47 0 53 tek Data Input Hold Time after DQS Strobe toH 45 ps DQ Input Pulse Width toipw 360 ps DQS Output Access Time from Clock tpascK 225 225 ps Write DQS High Level Width tbasH 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 100 ps Data Input Setup Time Before DQS Strobe tos 10 ps DQS Falling Edge from Clock Hold Time tosH 0 18 tck avg DQS Falling Edge to Clock Setup Time toss 0 18 tck avg Clock Half Period thp minimum of tenor ter ns Address and Command Hold Time after Clock Dn 120 ps Address and Command Setup Time before Clock tis ac150 45 ps Load Mode Command Cycle Time turo 4 tek DQ to DQS Hold Lou 0 38 tektavg Active to Precharge Time tras 35 O tREFI ns Active to Active Auto Refresh Time tre 48 75 48 125 ns RAS to CAS Delay trep 13 75 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C treri 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C treri 3 9 us Auto Refresh Row Cycle Time trec 160 ns Row Precharge Time tr
10. e 13 75 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time terest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay for Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twpRE 0 9 tck avg Write DQS Postamble Time twpst 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 7 IYPDATARAM DTM64370A Pe 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Key Byte DRAM Device Type DDR3 SDRAM Key Byte Module Type Bit 3 Bit 0 Module Type RDIMM 0x01 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits 2Gb 0x03 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved SDRAM Addressing Bit 2 Bit 0 Column Address Bits 0x19 Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved UNUSED Module Organization Bit 2 BitO SDRAM Device Width 0x09 Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Module Memory Bus Width Bit
11. e thickness 1 mm Reference Raw Card Used Bit 4 Bit 0 Reference Raw Card Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved Address Mapping from Edge Connector to DRAM Bit 0 Rank 1 Mapping Registered DIMM Reserved 0x05 Bit 7 Bit 1 Reserved EE Ss 58 6 w Module Specie Secten LE S 63 K 0x00 14 176 0x00 117 Module Manufacturer ID Code Least Significant Bye o 118 Module Manufacturer ID Code Most Significant Die LL me mg 0x00 120 121 Module Manufacturing Date TJ 122 125 Module Serial Number TJ 126 127 128 Module PartNumber JIM Tow 129 0x33 130 Module Part Number LL Dm OBT DT Ox20 Ox20 0x20 C C OxFE M 131 0x33 132 0x42 133 0x35 134 0x32 135 0x37 136 0x33 137 0x44 138 0x48 EX 64 66 per 68 69 70 71 112 ERR 114 116 117 118 ads 120 121 122 126 126 27 128 129 130 121 132 133 134 135 136 137 138 Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 10 erster DIME4370A NE 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM mm Moue Par Number JT 1 Mode Part Number ll fein a Module Part Number O O o T oao 146 147 Module Revision ek lm Document 06214 Revision A 05 Jul 11 Dataram Corporation O 2011 Page 11 DRDATARAM DTM64370A en 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Wen DATARAM
12. e to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Pin Description Front Side Back Side Name Function 1 Vrernaj81 DQ25 61 A2 91 DQ41 f121 Vss 1151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Voo 92 Vss f122D04 152 DM3 182 Voo 212DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 Das5f123 DQ5 153 NC 183 Voo 213 NC DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DOS3 64 CK1 94 DQAS5f124Vss 1154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Voo 95 Vss 125 DMO 1155 DQ30 185 CKO 215 DQ48 TDQS 17 9 Termination strobes 6 DQS0 36 DQ26 66 Voo 96 DQ42126NC 156 DQ31 186 Voo 216 DQA7 CK 1 0 CK 1 0 Differential Clock Inputs 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 f127 Vss 1157 Vss 187 Event 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 Par Ju 98 Vss 128DQ6 158 CB4 188 AO 218 DQ52 CAS Column Address Strobe 9 DQ2 39cBo 69 VDD 99 DQ48 129 DQ7 1159 CB5 189 Voo 219 DQ53 RAS Row Address Strobe 10DQ3 40CB1 70A10 AP 100 DQ49 30 Vss 1160 Vss 190 BA1 220 Vss S 3 0 Chip Selects 11Vss MI Vss 71 BAO 101Vss 131 DQ12 161 DM8 191 Mon 221DM6 NVE Write Enable 12DQ8 42 DQS8 72 Voo 102 DQS6 132 DQ13 162 NC 192 RAS 222 NC A 15 0 Address Inputs 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 1163 Vss 193 SO 223 Vss BA 2 0 Bank Addresses 14Vss MA Van 74 CAS 10
13. oltage 30 DQ24 60 Von 90 DQ40 120V 150 DQ29 180 A3 210 DQ45 240 Vor NC No Connection Not used Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 1 D Zpatagan DTM64370A 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Front view le 133 35 15 250 9 50 0 374 30 00 ii 1 184 m LC 17 30 0 681 O AT AA O Y 5 00 0 197 2 50 5 175 47 00 SR 0 098 ra ra 0 204 1 850 2 795 123 00 14 843 w Back view Side view 4 00Max 7 Rate WI 4 00 Min 0 157 Min O NANA AN O 1 27 t 10 JL 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 2 rri DTM64370A e Value and Performance RS10 IRSO O DQSRO O DQSR4 DQSRO O DQSR4 CH DMR4 TDQSR9O DORI7 0 VO 7 0 DQSR1 DQSR1 DMR1 TDQSR100 DORI15 8 IMDQSR110 RANK 1 DQR 23 16 DQS DOS TDQSR120 DQR 31 24 TDQSR17O CBRI7 0 All 15 OHMS DQ 63 0 O VVV O DQR 63 0 CBI7 0 O VVV O CarI7 0 DQSI8 0 O VWA O__DASRIB 0 IDASI8 0 O VVV O DQSRI 8 0 DMI8 0 O VVV O DMRIS 0 IMDASH17 9 O VVM O TDQSRI17 9 GLOBAL SDRAM CONNECTS All39 OHMS BA 2 0 R A 15 0 R IRASR ICASR IWER VTT All 39 OHMS CKE
14. st Significant Byte tWTRmin tRTPmin Upper Nibble for tFAW Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved Minimum Four Activate Window Delay Time tFAWmin Least 30 0ns Significant Byte SDRAM Optional Features CO 1 16 17 9 20 N N N N N o wo N 26 7 2 N CA N CH Ke Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved Module Thermal Sensor With TS SDRAM Device Type Monolithic 31 32 33 0x69 0x78 0x69 0x30 0x69 0x11 0x18 0x81 0x00 0x05 0x3C Ox3C Ox00 OxFO 0x83 0x01 0x80 0x00 Document 06214 Revision A 05 Jul 11 Dataram Corporation 2011 Page 9 DODATARAM DTM64370A NE 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM 38 Fine Offset for Minimum Active to Active Refresh Delay 48 125ns 0x00 Time tRCmin 50 50 UNUSED G Module Nominal Height Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 OxOF Bit 7 Bits Reserved 0 Module Maximum Thickness Bit 3 Bit 0 Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baselin
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