Dataram DTM67209A memory module
Contents
1. PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 500 500 ps CAS to CAS Command Delay 2 Clock High Level Width 0 45 0 55 Clock Cycle Time tck 3750 8000 ps Clock Low Level Width tc 0 45 0 55 tck Data Input Hold Time after DQS Strobe 225 ps DQ Input Pulse Width toipw 0 35 DQS Output Access Time from Clock toasck 450 450 ps Write DQS High Level Width tpasH 0 35 tck Write DQS Low Level Width tros 0 35 tck DQS Out Edge to Data Out Edge Skew toasa 300 ps Data Input Setup Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time tpsH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tup minimum of or tci ns Address and Command Hold Time after Clock tin 375 ps Address and Command Setup Time before Clock tis 250 ps Load Mode Command Cycle Time 2 DQ to DQS Hold ton tup tous Data Hold Skew Factor tans 400 ps Active to Precharge Time tras 127 5 ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval tREFI 7 8 Hs Auto Refresh Row Cycle Time 75 70 ns Row Precharge Time tre 15 ns Read DQS Preamble Time RPRE 0 9 1 1 tck Read DQS Postamble Time tRPsT 0 4 0 6 tox Row Active to Row Active Delay tRRD 7 5 ns Internal Read to Precharge Command Delay 7 5 ns Write DQS Preamble Time twPRE 0 25 ps W2. PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address Bank Active 100 bus inputs switching Data bus inputs are switchin 920 ma Precharge Current p 9 9 Operating One lout 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is Bank Active Read Ipp1 HIGH between valid commands Address bus inputs are switch 600 mA Precharge Current ing Precharge Power 5 2 All banks idle is LOW Other control and address bus inputs 80 mA Down Current nd are stable Data bus inputs are floating Precharge Quiet lpp2Q All banks idle CKE is HIGH CS is HIGH Other control and ad 216 mA Standby Current BD dress bus inputs are stable Data bus inputs are floating Precharge Standby In e2N All banks idle CKE is HIGH CS is HIGH Other control and ad 280 mA Current pp dress bus inputs are switching Data bus inputs are switching All banks open CKE is LOW Other control and address bus in Active Power Down Ipp3P puts are stable Data bus inputs are floating Fast Power down 160 mA Current exit Mode Register bit 12 0 All banks open tras 70 ms is HIGH CS is HIGH between Ipp3N valid commands Other control and address bus inputs are 360 mA switching Data bus inputs are switching All banks open Continuous burst writes BL 4 CL 3 tcx Operating Burst AL 0 tras 70 ms CKE is HIGH CS is HIGH between valid Write Current Ipo4
3. from Clock at CL X 1 ns Minimum Clock Cycle Time at CL X 2 ns Maximum Data Access Time tAC from Clock at CL X 2 ns Minimum Row Precharge Time tRP ns Minimum Row Active to Row Active Delay tRRD ns Minimum RAS to CAS Delay tRCD ns Minimum Active to Precharge Time tRAS ns e gi EM ME P M eai eee Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 9 DTM67209A tid 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM 31 Module Rank Density 1GB 0x01 32 Address and Command Setup Time Before Clock tIS ns 0 25 0x25 33 Address and Command Hold Time After Clock ns 0 37 0x37 34 Data Input Setup Time Before Strobe tDS ns 0 1 0x10 35 Data Input Hold Time After Strobe tDH ns 0 22 0x22 36 Write Recovery Time tWR ns 15 0x3C 37 Internal write to read command delay tWTR ns 7 5 Ox1E Internal read to precharge command delay tRTP ns 7 5 Memory Analysis Probe Characteristics UNUSED Extension of Byte 41 tRC and Byte 42 tRFC ns Add this value to byte 41 Add this value to byte 42 SDRAM Device Minimum Active to Active Auto Refresh Time tRC ns SDRAM Device Minimum Auto Refresh to Active Auto Refresh Command Period tRFC ns SDRAM Device Maximum Cycle Time tCK max ns SDRAM Dev DQS DQ Skew for DQS amp DQ signals tDQSQ ns DDR SDRAM Device Read Data Hold
4. Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C ost 55 Bit 0 0 if DT4W is greater than DT4R Bits 1 7 0 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh UNUSED 0x00 DT5B Degree C 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto Precharge DT7 Degree C HAUSEN Thermal Resistance of PLL Package from Top to Ambient Psi 98 PLL C Watt UNUSED 0x00 59 Thermal Resistance of Register Package from Top to Ambient Psi T A Register C Watt UNUSED 0x00 PLL Case Temperature Rise from Ambient due to PLL Active DT PLL Active Degree C UNUSED Register Case Temperature Rise from Ambient due to Register Ac tive Mode Bit DT Register Active Mode Bit Bit 0 If O Unit for Bits 2 7 is 0 75C Bit 1 RFU Default 0 0 Register Active Bits 2 7 0 SPD Revision Revision 1 2 Checksum for Bytes 0 62 Module Manufacturer s JEDEC ID Code Dataram ID Module Manufacturer s JEDEC ID Code Dataram ID Module Manufacturer s JEDEC ID Code UNUSED Module Manufacturing Location UNUSED Module Part Number D Module Part Number T Module Part Number M Module Part Number 6 Module Part Number 7 Module Part Number 2 79 Module Part Number 0 0x30 80 Module Part Number 9 0x39 81 90 Module Part Number 0x20 91 92 Module Revision Code UNUSED 0x00 uoi
5. Capacitance T4 25 C f 100 MHz PARAMETER Pin Symbol Min Max Unit Input Capacitance Clock CKO CKO CK1 CK1 CIN1 4 8 pF Hips a Address b 2 0 A 13 0 RAS CAS ODTO CKEO So CIN2 8 16 pF Input Output Capacitance DQ 63 0 DQS 7 0 DQS 7 0 DM 7 0 CIO 2 5 4 pF DC Characteristics 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 pA 1 Input Leakage Current S0 CKEO ODTO lu 40 40 1 Input Leakage Current 1 0 CK 1 0 lu 30 30 pA 1 Input Leakage Current DM lu 10 10 pA 1 Output Leakage Current DQS DQ loz 10 10 pA 2 Output Minimum Source DC Current lon 13 4 mA 3 Output Minimum Sink DC Current lo 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vout S 3 Vpp 1 7 V Vout 1420 mV Vpp lou must be less than 21 Ohms for values of Vout between Von and Vpp 280 mV 4 Vpp 1 7 V Vout 280 mV Vour lo must be less than 21 Ohms for values of Voyr between 0 V and 280 mV Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 5 DM 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM lbo Specifications and Conditions 0 to 70 C Voltage referenced to Vss 0 V Max
6. Skew Factor tQHS ns PLL Relock Time us UNUSED DRAM maximun Case Temperature Delta Degree C DT4R4W Delta Bits 0 3 Tcasemax delta Bits 7 4 Thermal Resistance of DRAM Package from Top Case to Ambient Psi T A DRAM C Watt DRAM Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree C Bit 0 If DRAM does not support high temperature self refresh entry UNUSED Bit 1 If 0 Do not need double refresh rate for the proper operation DTO Bits 2 7 DRAM Case Temperature Rise from Ambient due to Precharge Quiet UNUSED Standby DT2N DT2Q Degree C DRAM Case Temperature Rise from Ambient due to Precharge UNUSED Power Down DT2P Degree C DRAM Case Temperature Rise from Ambient due to Active Standby DT3N Degree C UNUSED 53 DRAM Case temperature Rise from Ambient due to Active Power Down with Fast PDN Exit DT3Pfast Degree C UNUSED 9x09 aaa a A MM CMM M pc A Y Pen EE 60 Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 10 DTM67209A tid 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM 54 DRAM Case temperature Rise from Ambient due to Active Power Down with Slow PDN Exit DT3Pslow Degree C UNUSED ORDO DRAM Case Temperature Rise from Ambient due to Page Open Burst
7. Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vrer 0 125 Vpp 0 300 V Logical Low Logic 0 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vrer 0 250 Logical Low Logic 0 ViL AC Vrer 0 250 V eee PR Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 4 n DATARAM 2 Optimizing Value and Performance DTM6720 9A 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vpp 0 300 V 1 DC Differential Input Voltage 0 250 Voo 0 600 V 2 AC Differential Input Voltage 0 500 Voo 0 600 V 3 AC Differential Cross Point Voltage Vix AC 0 50 Vpp 0 175 0 50 0 175 V 4 Notes 1 Specifies the allowable DC excursion of each input of a differential pair 2 specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Specifies the input differential voltage required for switching 4 The typical value of Vic is expected to be 0 5 Voo and is expected to track variations in Vpp
8. e a a I Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 11 D Pye DTM67209A 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Optimizing Value and Performance 93 94 Module Manufacturing Date UNUSED 0x00 95 Module Serial Number S 0x53 96 Module Serial Number E 0x45 97 Module Serial Number R 0x52 98 Module Serial Number 0x23 57 Manufacturer s Specific Data UNUSED 0x00 Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 12 DTM67209A MM 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM 2 Med Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Da taram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trade marks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 13
9. 2 O DM DQS CS I O 7 0 DM DM DQS CS V O 7 0 DM DMR6 parso S DM DQS cS DM 0 7 0 DM DQS CS DM I O 7 0 2 X 200 OHMS CKO ie SDRAM X 4 2 X 200 OHMS CK1 nus SDRAM X4 DECOUPLING VDDSPD 4 Serial PD VDD T All Devices VREF SDRAMs Vss All Devices Page 3 DTM67209A 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 85 C Voltage on Vpp relative to Vss Vpp 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vpp 1 7 1 8 1 9 V 1 0 Reference Voltage VREF 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 Bus Termination Voltage Vit Vrer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to
10. DTM67209A 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM A TA rd B Optimizing Value and Performance Identification DTM67209A 128Mx64 Performance range Clock Module Speed CL tncp trp 266 MHz DDR2 533 5 4 4 266 MHz DDR2 533 4 4 4 200 MHz DDR2 400 3 3 3 zr ttit P izle Sor i EPI pr tere tere Features Description 200 pin JEDEC SO DIMM Dual sided assembly 67 600mm The Dataram DTM67209A assembly is 2 661 wide by 30 0mm 1 1817 high Operating Voltage 1 8 V 0 1 Type SSTL_18 Data Transfer Rate 4 2 Gigabytes sec Bursts Length 4 and 8 Programmable I O driver strength OCD 128Mx64bit Unbuffered Non ECC memory module which conforms to JEDEC s DDR2 PC2 4200 stan dard The DTM67209A assembly consists of one rank comprised of eight 128Mx8 Hynix DDR2 SDRAMs in a 60 Ball FBGA package A 2Kbit EEPROM for serial presence detect pro vides critical timing and configuration information used by the system to identify and configure the Programmable On Die Termination ODT memory The assembly is a Small Outline Dual In line Mem ory Module intended for mounting into 200 pin edge connector sockets Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 One Physical Rank Fully RoHS Compliant Pin Names Pin Configurations Front side Back side Pin name Function 1 VREF A1 IRAS Row add
11. Page 1 DTM67209A ME GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Front view 67 600 2 661 30 000 1 181 4900 157 eG 449 4 200 PM 165 a 63 000 1 2 480 Back view Side view 3 500 Max 138 Max 4 000 Min 157 Min 1 000 T MN 040 004 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches ren I cc ER EIC MCI LC M NM C ee Hz J Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 2 DTM67209A 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Optimizing Value and Performance 3 OHMS S0O DMRO O DQRS0O DQSROO DQS DQS CS DM I O 7 0 DQS DAS CS I O 7 0 DQS DQS cs DQR 23 16 O 7 0 DMR3 DQSR3 DQSR3 DQS DAS CS DQR 31 24 110 7 0 22 OHMS DQ 63 0 O O DQR 63 0 DQS 7 0 O O DOQSR 7 0 IDQS 7 0 O O DQSR 7 0 DM 7 0 O O DMRI7 0 GLOBAL SDRAM CONNECTS 10 OHMS 2 0 O W O BA Z 0 R 13 0 O AA O A 13 0 R IRAS Q AA O RASR ICAS Q AA O CASR O A AN O 3 OHMS CKEO O AA CKEOR O A N SCL SERIAL PD SDA SAO SA1 SA2 Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 DQR 39 3
12. W commands Address bus inputs are switching Data bus inputs 1900 mA are switching All banks open Continuous burst reads lour 0 mA BL 4 Operating Burst 5548 CL 3 AL 0 tras 70 ms is HIGH CS is HIGH be 4000 mA Read Current tween valid commands Address bus inputs are switching Data bus inputs are switching Refresh command at every 75 ns CKE is HIGH CS is HIGH be Ipp5 tween valid commands Other control and address bus inputs are 1320 mA Burst Refresh Cur rent Saas switching Data bus inputs are switching Self Refresh Cur loo6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 80 mA rent Dp inputs are floating Data bus inputs are floating All bank interleaving reads lout 0 mA BL 4 CL 3 tcx Operating Bank In B x we terleave Read Cur 567 AL 70 ns trrp 7 5 ns is HIGH CS is HIGH between 1400 mA valid commands Address bus inputs are stable during deselects Data bus inputs are switching rent Note For all Ip5X measurements tek 3 75 ns trc 60 ns trcp 15 ns tras 45 ns and tgp 15 ns unless otherwise specified All currents are based on DRAM absolute maximum values Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 6 DM 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM AC Operating Conditions
13. dth 8 0x08 14 Error Checking SDRAM Width None 0x00 15 Reserved UNUSED 0x00 SDRAM Device Attributes Burst Lengths Supported 0x0C TBD TBD Burst Length 4 X 16 Burst Length 8 X TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM Device 8 0x08 Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 8 DTM67209A eid 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM SDRAM Device Attributes CAS Latency TBD TBD Latency 2 Latency 3 Latency 4 Latency 5 Latency 6 TBD DIMM Mechanical Characteristics Max module thickness mm x lt 3 80 DIMM type information Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm X Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD SDRAM Module Attributes Refer to Byte20 for DIMM type information Number of active registers on the DIMM N A for UDIMM Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD SDRAM Device Attributes General Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD Minimum Clock Cycle Time at Reduced CAS Latency CL X 1 ns Maximum Data Access Time tAC
14. ress strobe 3 V s 53 Vss Voo 104 Vpp 154 DQ47 ICAS Column address strobe 5 DQO 55 DQ18 A10 AP 106 BA1 156 Vss Write enable 57 19 108 RAS 158 0052 IS 1 0 Chip select input 9 Vss 59 Vss 110 SO 160 DQ53 CK 1 0 CK 1 0 Differential Clock inputs 11 0 61 po24 Voo 112 162 Vss 1 0 Clock enable input 13 paso 63 po25 114 ODT 164 CK1 BA 2 0 Bank select input 15 Vss 65 Vss 116 A13 166 CK1 A 13 0 Address input Multiplexed 17 pQ2 67 DM3 118 Vpp 168 Vss ODT 1 0 On Die Termination 19 69 NC 120 NC 170 DM6 DQS 7 0 DQS 7 0 Data strobes 21 Vss 71 Vss 122 Vss 172 Vss DMI7 0 Data masks 23 DQ8 73 DQ26 124 DQ36 174 DQ54 DQ 63 0 Data I Os Data bus 25 Dag 75 DQ27 126 DQ37 176 DQ55 SCL Serial clock 27 Vss 77 VSS 128 Vss 178 Vss SDA Serial data 29 DQS1 79 CKEO 130 DM4 180 DQ60 SA 1 0 Address EEPROM 31 DQS1 81 132 Vss 182 DQ61 Event Temperature sensing 33 Vss 83 NC 134 DQ38 184 Vss VREF Reference voltage 35 DQ10 85 NC 136 DQ39 186 DQS7 VDD Power supply 1 8V 0 1V 37 DQ11 87 Voo 138 Vss 188 DQS7 VSS Ground 39 Vss 89 A12 140 DQ44 190 Vss VDDSPD Serial EEPROM power supply 41 Vss 91 A9 142 0045 192 DQ62 NC No connects 43 DQ16 93 A8 144 Vss 194 DQ63 45 0017 95 146 DQS5 196 Vss 47 Vss 97 A5 148 DQS5 198 SA0 49 DQS2 99 A3 VppSPD 50 Event 150 Vss 200 SA1 not used on the DTM67209A Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009
15. rite DQS Postamble Time twPsT 0 4 0 6 tck Write Recovery Time twn 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrp 200 tck Document 06547 Revision A 1 JUN 09 Dataram Corporation 2009 Page 7 D 67209 Optimizing Value and 1GB 200 1Rx8 Unbuffered Non ECC DDR2 SO DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex 0 Number of Bytes Utilized by Module Manufacturer 128 bytes 0x80 1 Total number of Bytes in Serial PD device 256 bytes 0x08 2 Memory Type DDR2 SDRAM 0x08 3 Number of Row Addresses 14 OxOE Number of Column Addresses 10 Module Attributes Number of Ranks Package and Height 0x60 of Ranks 1 5 Card on Card No DRAM Package Planar Module Height 30mm 6 Module Data Width 64 0x40 7 Reserved UNUSED 0x00 9 Voltage Interface Level of this assembly SSTL 1 8V 0x05 9 SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 3 75 Ox3D 10 SDRAM Access from Clock Highest CAS latency tAC ns 0 5 0x50 DIMM configuration type Non parity Parity or ECC 0x00 Data Parity Data ECC Address Command Parity 11 TBD TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR 0x82 13 Primary SDRAM Wi
Download Pdf Manuals
Related Search