Dataram 2GB DDR2
Contents
1. PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 400 400 ps CAS io CAS Command Delay tceco 2 tck Clock High Level Width tcH 0 45 0 55 tek Clock Cycle Time tck 2 5 8000 ps Clock Low Level Width teL 0 45 0 55 tck Data Input Hold Time after DQS Strobe toH 125 ps DQ Input Pulse Width toipw 0 35 tox DOS Output Access Time from Clock tbasck 400 400 ps Write DQS High Level Width toasH 0 35 tox Write DQS Low Level Width toast 0 35 tck DQS Out Edge to Data Out Edge Skew toasa 200 ps Data Input Setup Time Before DQS Strobe tos 50 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tue minimum of tcy or teL ns Address and Command Hold Time after Clock Du 250 ps Address and Command Setup Time before Clock tis 175 ps Load Mode Command Cycle Time tmRD 2 tck DQ to DQS Hold Lou tup tans Data Hold Skew Factor Lous 300 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 57 5 ns RAS to CAS Delay trep 12 5 ns Average Periodic Refresh Interval REFI 7 8 US Auto Refresh Row Cycle Time treo 127 5 ns Row Precharge Time tre 12 5 ns Read DQS Preamble Time tRPRE 0 9 1 1 tox Read DQS Postamble Time trest 0 4 0 6 tck Row Active to Row Active Delay RRD 7 5 ns Internal Read to Precharge Command Dela2. terre D TM63367B i 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM Identification DTM63367B 256Mx64 2GB 2Rx8 PC2 6400U 555 12 E1 Performance range Clock Module Speed CL trep Ze 400 MHz PC2 6400 5 5 5 333 MHz PC2 5300 5 5 5 266 MHz PC2 4200 4 4 4 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm DTM63367B is an Unbuffered 256Mx64 high non ECC memory module which conforms Operating Voltage 1 8 V 0 1 to JEDEC s DDR2 PC2 6400 standard The assembly is comprised of two Ranks VO Type STs Each Rank is comprised of eight 128Mx8 Data Transfer Rate 6 4 Gigabytes sec DDR2 Samsung SDRAMs One 2K bit Data Bursts 4 or 8 bits Sequential or Interleaved ordering EEPROM is used for Serial Presence Detect Programmable I O driver strength OCD Both output driver strength and input Programmable On Die Termination ODT termination impedance are programmable Programmable CAS Latency 4 or 5 to maintain signal integrity on the I O signals Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully RoHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDD 211 DM5 CB 7 0 Data Check Bits 2 VSS 32 VSS 62 VDD 92 DQS5 f122 DQ4 152 DQ28 182 A3 212 NC DQ 63 0 Data Bits 3 DQO 33 DQ24 63 A2 93 DQS5 f123 DQ5 153 DQ29 183 A1 213 VSS DQS 8 0
3. Symbol Test Condition Value Unit Operating One _ CKE is HIGH CS is HIGH between valid commands Address Bank Active oc bus inputs are switching Data bus inputs are switchin 680 mA Precharge Current H 9 H 9 Operating One lout 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is Bank Active Read Ipp1 HIGH between valid commands Address bus inputs are 760 mA Precharge Current switching Precharge Power Ipp2P All banks idle CKE is LOW Other control and address bus 160 mA Down Current pO inputs are stable Data bus inputs are floating Precharge Quiet lpp2Q All banks idle CKE is HIGH CS is HIGH Other control and 512 mA Standby Current Ge address bus inputs are stable Data bus inputs are floating Precharge Standby lon 2QN All banks idle CKE is HIGH CS is HIGH Other control and 720 mA Current DD address bus inputs are switching Data bus inputs are switching Active Power All banks open CKE is LOW Other control and address bus Down Current Ipp3P inputs are stable Data bus inputs are floating Fast Power down 400 mA exit Mode Register bit 12 0 S All banks open tras 70 ms CKE is HIGH CS is HIGH Ce Ibp3N between valid commands Other control and address bus inputs 880 mA are switching Data bus inputs are switching Operating Burst All banks open Continuous burst writes BL 4 CL 5 AL 0 tras 70 ms CKE is HIGH CS is HIGH between valid Write Current loo4W commands Address bus inputs
4. are switching Data bus inputs 1449 mA are switching All banks open Continuous burst reads lour 0 mA BL 4 Operating Burst ip CL 5 AL 0 tras 70 ms CKE is HIGH CS is HIGH aah ma Read Current between valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH Ipp5 between valid commands Other control and address bus inputs 2800 mA Current tere A GER are switching Data bus inputs are switching Self Refresh L ns CK and CK at 0 V CKE lt 0 2 V Other control and address bus 160 mA Current PB inputs are floating Data bus inputs are floating i All bank interleaving reads lour 0 mA BL 4 CL 5 AL 70 Operating Bank i a Geff ee Interleave Read E ns tarp 7 5 ns CKE is HIGH CS is HIGH between valid 2960 mA Current commands Address bus inputs are stable during deselects Data bus inputs are switching One module rank in this operation rest in IDD2P All module ranks in this operation Note For all Ipp gt X measurements tek 2 5 ns tre 57 5 ns trop 12 5 ns tras 45 ns and tpp 15 ns unless otherwise specified All currents are based on DRAM absolute maximum values D EECHER EE Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 6 rr D M63367B eeh 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM AC Operating Conditions
5. 0 0 0040 PI Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a a a a a Se a a a a a Se E Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 2 pr DT M63367B 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM Optimizing Value and Performance EM SO DMRO DQSRO DQSRO DQS DQS DAS DAS CS D DAQRI 7 0 O 1 0 7 0 VO 7 0 DMR1 O DQSR1 DQSR1 DMR2 O DQSR2 O DQSR2 O DQS DOS CS DM VO 7 0 DMR3 DQSR3 DQSR3 CS DM DQS DOS DQS DOS CS DM DQR 31 24 O 1 0 7 0 VO 7 0 All 22 OHMS DQ 63 0 O VW O DQRI63 0 DQS 7 0 O VWA O DarRsi7 0 DQS 7 0 O VW O DARSI7 0 DMI7 0 O VW O DMRI7 0 GLOBAL SDRAM CONNECTS All 5 1 OHMS BAD OI O A O A 13 0 Ce IRAS O VWA O ICAS O AA O WE O AA O BA 2 0 R A 13 0 R IRASR ICASR AWER ODTO ODT1 22 PF DMR4 DQSR4 DQSR4 DQRI 39 32 DMRS DQSR5 DQSR5 DQR 47 40 O DMR6 O DQR 55 48 0 DMR7 DQSR7 DQR 63 56 DQS DOS DOS DOS VO 7 0 VO 7 0 DOS DOS CS DM V O 7 0 DQS DOS CS DM DOS DOS CS DM VO 7 0 VO 7 0 DOS DOS CS DM DOS DOS CS DM VO 7 0 V O 7 0 3 X 200 OHMS Ge SDRAM X 4 ICKO 1 5 pF 3 X 200 OHMS SE SDRAM X 6 I
6. 00 Vrer 0 125 V AC Input Logic Levels Single Ended CT 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical Low Logic 0 Vuuac Vrer 0 250 V Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 4 DRPATARA Optimizing Value and Performance rj DTM63367B Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vop 0 300 V 1 DC Differential Input Voltage Ve 0 250 Voo 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Voo 0 600 V 3 AC Differential Cross Point Voltage Vixac 0 50 Vpb 0 175 0 50 VpD 0 175 V 4 Notes 1 Vnpco specifies the allowable DC excursion of each input of a differential pair 2 Vipo specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Vipiac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vor Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CIN
7. 1 4 8 pF Input Capacitance Clock CK1 CK1 CK2 CK2 CIN1 6 12 pF Input Capacitance Conirol S0 S1 CKEO CKE1 ODTO ODT1 CIN2 8 14 pF eek cea Address 5A 2 0 A 13 0 RAS CAS WE CIN2 16 28 pF Input Output Capacitance Geer er Meer CIO 5 7 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Address and Control lL 160 160 UA 1 Input Leakage Current S 1 0 CKE 1 0 lL 80 80 yA 1 ODT 1 0 Input Leakage Current CK 0 CK 0 lL 4 4 yA 1 Input Leakage Current CK 2 1 CK 2 1 I 6 6 HA 1 Input Leakage Current DM lL 20 20 yA 1 Output Leakage Current DQS DQ loz 20 20 HA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current Jo 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vour S Voo 3 Vpp 1 7 V Vour 1420 mV Dour Voo lon must be less than 21 Ohms for values of Vout between Vpp and Vpp 280 mV A Vo 1 7 V Vout 280 mV Moullo must be less than 21 Ohms for values of Vout between 0 V and 280 mV Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 5 DRPATARA Optimizing Value and Performance oa DTM63367B 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V Max PARAMETER
8. 10 DQ56 140 DQ14 170 VDD 200 DQ37 230 DQ61 VREF Reference Voltage 21 DQ10 51 VDD 81 DQ33 111 DQ57 RA DQ15 171 CKE1 201 VSS 231 VSS NC No Connection 22 DQ11 52 CKEO 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 DQ20 173 A15 203 NC 233 NC 24 DQ16 54 BA2 84 DQS4 114 DQS7 f144 DQ21 174 A14 204 VSS 234 VSS 25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDD 205 DQ38 235 DQ62 26 VSS 56 VDD 86 DQ34 116 DQ58 f146 DM2 176 A12 206 DQ39 236 DQ63 27 DQS2 57 A11 87 DQ35 117 DQ59 f147 NC 177 A9 207 VSS 237 VSS 28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD 29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SAO 30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1 Connected but not used Not used Non ECC DIMM Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 1 rr DIM63367B a iieialoies 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM Front view 133 35 F 5 250 10 00 4 00 1 181 nu d t 17 80 Il 0 700 UI vmmmmummmmmmmmmmummg N 5 00 A 0 197 2 54 Min 518 LA 63 00 55 00 0 100 Min 0 204 2 480 2 165 P 123 00 D 4 843 g Back view Side view 4 00Max 7 EES Max 4 00 Min 0 157 Min 1 27 10 S 0 050
9. CK1 3 X 200 OHMS oy SDRAM X 6 ICK2 DECOUPLING VppsP gt _ Serial PD VDD All Devices VREF All SDRAMs Vss All Devices SCL SERIAL PD SDA SA0 SA1 SA2 Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 3 pr D M63367B 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TstToRAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tease 0 85 C Voltage on Vpp relative to Vss Von 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER SE E a SC Note Power Supply Voltage UO Reference Voltage Bus Termination Voltage Notes Vrer 0 04 VREF Vrer 0 04 1 The value of Vor is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin 0c Vrer 0 125 Von 0 300 V Logical Low Logic 0 Vit oc 0 3
10. DQS 8 0 Differential Data Strobes 4 Dai 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS op DQ42 125 DMO 155 DM3 185 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 DQS3 66 VSS 96 DQ43 126 NC 156 NC 186 CKO 216 VSS CKE 1 0 Clock Enables 7 DQSO 87 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52 ICAS Column Address Strobe 8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 AO 218 DQ53 RAS Row Address Strobe 9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS S 1 0 Chip Selects 10 DQ3 d DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2 IWE Write Enable 11 VSS 41 VSS 71 BAO 101 SA2 131 DQ12 161 CB4 191 VDD 221 CK2 A 15 0 Address Inputs 12 DQ8 42 CBO 72 VDD 102 NC 132 DQ13 162 CB5 192 RAS 222 VSS BA 2 0 Bank Addresses 13 DO 43 CB1 73 WE 103 VSS 133 VSS 163 VSS 193 SO 223 DM6 ODT 1 0 On Die Termination Inputs 14 VSS 44 VSS 74 CAS 104 DQS6 134 DM1 164 DM8 194 VDD 224 NC SA 2 0 SPD Address 15 DQS1 45 DQS8 75 VDD 105 DQS6 135 NC 165 NC 195 ODTO 225 VSS SCL SPD Clock Input 16 DQS1 46 DQS8 76 S1 106 VSS 136 VSS 166 VSS 196 A13 226 DQ54 SDA SPD Data Input Output 17 VSS 47 VSS 77 ODT1 107 DQ50 4137 CK1 167 CB6 197 VDD 227 DQ55 VSS Ground 18 NC 48 CB2 78 VDD 108 DQ51 138 CK1 168 CB7 198 VSS 228 VSS VDD Power 19 NC 49 CB3 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60 VDDSPD SPD EEPROM Power 20 VSS 50 VSS 80 DQ32 1
11. ase Temperature Rise from Ambient due to 1 095 0x49 Precharge Power Down DT2P Degree C 52 DRAM Case Temperature Rise from Ambient due to Active 0x28 Standby DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active Sc 0x37 Power Down with Fast PDN Exit DT3Pfast Degree C 54 DRAM Case temperature Rise from Ambient due to Active 1 325 0x35 Power Down with Slow PDN Exit DT3Pslow Degree C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Ox5E Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 0 if DT4W is greater than DT4R DTAR Bits 1 7 56 DRAM Case Temperature Rise from Ambient due to Burst 19 5 0x27 Refresh DT5B Degree C Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 10 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM 57 DRAM Case Temperature Rise from Ambient due to Bank 20 5 0x29 Interleave Reads with Auto Precharge DT7 Degree C Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi T A PLL C Watt Thermal Resistance of Register Package from Top to Ambient UNUSED 0x00 Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active UNUSED 0x00 DT PLL Active Degree CH Register Case Temperature Rise from Ambient due to Register Active Mode Bit 0x00 DT Register Active Mode Bit Bit 0 If O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default 0 0 Reg
12. charge Time tRAS ns 36 Write Recovery Time tWR ns Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 9 AAS 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM Internal write to read command delay tWTR ns Internal read to precharge command delay tRTP ns Memory Analysis Probe Characteristics UNUSED 40 Extension of Byte 41 tRC and Byte 42 tRFC ns 0x36 Add this value to byte 41 Add this value to byte 42 0 5 eee SE Minimum Active to Active Auto Refresh Time GE 42 SDRAM SE Minimum Auto Refresh to Active Auto 127 5 Ox7F Refresh Command Period tRFC ns 43 SDRAM Device Maximum Cycle Time tCK max ns o 8 amp 8 0o80 44 SE Dev DQS DQ Skew for DOS amp DQ signals t DQSQ ed Ge SDRAM Device Read Data Hold Skew Factor tQHS Ox1E 6 PLL Relock Time us UNUSED 0x00 47 DRAM maximun Case Temperature Delta Degree C 0x50 DT4R4W Delta Bits 0 3 a Tcasemax delta Bits 7 4 48 Thermal Resistance of DRAM Package from Top Case to 0x74 Ambient Psi T A DRAM C Watt 9 DRAM Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree C Bit 0 If 0 DRAM does not support high temperature self 1 refresh entry Bit 1 If 0 Do not need double refresh rate for the proper 1 operation DTO Bits 2 7 50 DRAM Case Temperature Rise from Ambient due to 0x32 Precharge Quiet Standby DT2N DT2Q Degree C DRAM C
13. ister Active Bits 2 7 0 S es Dedeunb met LS 65 em EE S 192 o7 Module SerialNumber o o o R T Manufacturer s Specific Data UNUSED Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 11 yee DTM63367B ae 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM PyYPDATARAM eed BB Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 12
14. r of Banks on SDRAM 0x08 Device 18 SDRAM Device Attributes CAS Latency 0x30 TBD TBD Latency 2 Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 8 EELER 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM Latency 3 Latency 4 X Latency 5 X Latency 6 TBD DIMM Mechanical Characteristics Max module thickness x lt 4 10 0x01 mm 20 DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD 22 24 25 TBD SDRAM Device Attributes General 0x02 Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD 25 Minimum Clock Cycle Time at CL X 2 ns SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed D Data Access Time tAC from Clock at CL X 1 Minimum Clock Cycle Time at Reduced CAS Latency CL X 0x3D 1 ns pe tare Minimum Clock Cycle Time at CL X 2 ns 1 UNUSED Klee Data Access Time tAC 1 from Clock at CL X 2 UNUSED LG Kar RAS to CAS Delay tRCD ns 30 Minimum Active to Pre
15. y tRTP 7 5 ns Write DQS Preamble Setup Time twPRE 0 35 ps Write DQS Postamble Time twpsT 0 4 0 6 tck Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trrc min 10 ns Exit Self Refresh to Read Command txsRD 200 tck Document 06609 Revision A 21 Oct 10 Dataram Corporation 2010 Page 7 pr DT M63367B EELER 2 GB 240 Pin Unbuffered non ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX 0 Number of Bytes Utilized by Module Manufacturer 128 bytes pp Ox0E OA 5 Module Attributes Number of Ranks Package and Height 0x61 of Ranks 2 Card on Card No DRAM Package Planar Module Height 30mm 00E OA DS Data Width si UNUSED 8 Voltage Interface Level of this assembly SSTL 1 8V Ae Cycle time Max Supported CAS Latency CL X 2 5 0x25 tCK ns 10 SDRAM Access from Clock Highest CAS latency AC ns 11 DIMM configuration type Non parity Parity or ECC 0x00 Data Parity Data ECC Address Command Parity TBD TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR 13 Primary SDRAM Width SCH foo 14 Emor Checking SDRAM Width 15 Reserved UNUSED 16 SDRAM Device Attributes Burst Lengths Supported 0x0C TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD 17 SDRAM Device Attributes Numbe
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