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Intel S1200BTS

1. 96 Table 30 RJ 45 10 100 1000 NIC Connector Pin out 1 97 Table 31 6Gb s SATA Connector Pin Out Pee te c 97 Table 32 3Gb s SATA Connector 97 x Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS List of Tables Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Revision 1 0 SAS Connector Pinsout IATA tno be nt tu Geo pad rt FR 98 External Serial A Port Pin out 8 1 444 98 Internal 9 pin Serial B Header Pin out J1B2 98 Internal USB Connector Pin out J1D1 99 Pin out of Internal USB Connector for low profile Smart module J3F2 99 Pin out of adaptive riser slot PCl Express slot 6 100 Three PCI Express x8 connectors J2B2 J3B1 and J4B2 102 One PCI X32 connector J1B1 Re IRR RE ee ORE 102 SSI 4 pin Fan Header
2. 26 Figure 14 Server Management Bus SMBUS Block 32 s eet 56 Figure 16 Advanced Ru EORR Dh b I 59 Figure 17 Processor Configuration Screen rssssssssssssss 62 Figure 18 Memory Configuration 5 68 Figure 19 Mass Storage Controller Configuration Screen 71 Figure 20 Serial Port Configuration 4 42442444 10 72 Figure 21 USB Configuration Screen 73 Figure 22 PCI Configuration Screen ten EUR ieee ERA 74 Figure 23 System Acoustic and Performance Configuration 75 Figure 24 Securily gu ete One act pares 75 Figure 25 Server Management Screen S1200BTL 76 Figure 26 Server Management Screen 51200 5 77 Figure 27 Console Redirection Sor een soe ce Lx E ec eb ete Lue en URP EO Meu iS 77 Figure 28 System Information Screen S1200BTL
3. 88 rcc 89 Jumper Blocks J4A2 J1F1 J1F3 J1F2 and J1E2 on S1200BTL 104 Jumper Blocks J2G1 J1G1 J1H3 and J2J1 on S1200BTS 105 POST Code Diagnostic LED Location le eter nita 110 Output Voltage Timing 115 On Off Timing Power Supply 116 Intel order number G13326 003 List of Tables Intel amp Server Board 51200 TPS List of Tables Table 1 Intel Server Board S1200BT Feature 2 Table 2 Major Board Components recen e Ee eX ERE HIR ER END ERR ARR 6 Table 3 Major Board Components tret 7 Table 4 Memory Configuration Table 20 Table 5 UDIMM memory configuration rule een 20 Table 6 UDIMM Maximum configuration mener 20 Table 7 Optional RMM4 Advanced Management Board Fealures 27 Table 8 Serial B Header J1B2 on S1200BTL or J8A1 on 51200 5 Pin out 27 Table 9 Video MOUS c 28 Table 10 Dual rie ter 29 Table 11 Basic and Advanced Management
4. 120 Appendix C POST Code Diagnostic LED Decoder 129 Appendix D POST Code Errors U 133 Appendix E Supported Intel Server Chassis uu 136 137 Reference Documents m 141 Intel order number G13326 003 List of Figures Intel Server Board 51200 TPS List of Figures Figure 1 Intel Server Board S1200BTL Picture 4 Figure 2 Intel Server Board S1200BTS 5 Figure 3 Intel Server Board S1200BTL Layout 6 Figure 4 Intel Server Board S1200BTS Layout 7 Figure 5 Intel Server Board S1200BTL Hole and Component Positions 9 Figure 6 Intel Server Board S1200BTL Major Connector Pin Location 1 0 2 10 Figure 7 Intel Server Board S1200BTL Major Connector Pin Location 2 of 2 11 Figure 8 Intel Server Board S1200BTL Primary Side Keepout Zone 12 Figure 9 Intel Server Board S1200BTL Secondary Side Keepout 2 13 Figure 10 Intel Server Board S1200BT Rear I O Layout 14 Figure 11 Intel Server Board S1200BTL Functional Block Diagram 15 Figure 12 Intel Server Board S1200BTS Functional Block Diagram 16 Figure 13 Integrated BMC Hardware
5. Figure 10 Intel Server Board S1200BT Rear I O Layout 14 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Functional Architecture 3 Functional Architecture The architecture and design of the Intel Server Board S1200BT is based on the Intel C202 Chipset The chipset is designed for systems based on the Intel Xeon processor in the FC LGA 1155 socket package The Intel Server Board S1200BTL uses Intel C204 Chipset and the Intel Server Board S1200BTS uses Intel C202 Chipset The Intel Xeon Processor E3 1200 Series are made up of multi core processors based on the 32nm processor technology The Intel CoreTM Processor i3 2100 is made up of dual core processors based on the 32nm processor technology This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server board Intel amp Server Board S1200BTL Block Diagram ATX 12 x 9 6 x16 connector Slot 6 Slot 5 Slot 4 x8 connector 4 Unbuffered DIMMs x8 connector Mezzanine Module Lewisville x8 connector PCle Gen1 x1 in physical Slot 3 Slot 1 A 1 on board SATA II 2 3 4 RGMII VIDEO UL USB USB 4 4 Dedicated Internal USB Type A Rear I O USB NIC Module Header x2 Header Ports x2
6. 35 Table 12 NM Features ter Er qr en pe v p deer qo gant aa go tee ku ie 43 Table 13 POST HotKeys 49 Table 14 BIOS Setup Page Layoul een e ER E VE o HERR RR nn 51 Table 15 BIOS Setup Keyboard Command Bar 52 Table 16 Screen n eM uu aap AER DM 54 Table 17 Board Connector Matrix on S1200BTL seen 90 Table 18 Board Connector Matrix on 51200 5 91 Table 19 Baseboard Power Connector Pin out 901 91 Table 20 SSI Processor 8 PIN Power Connector Pin out 9 1 92 Table 21 Intel 4 lite Connector Pin out 481 92 Table 22 Dedicated NIC connector for eene 92 Table 23 Header Pin out J1H5 4 93 Table 24 HSBP Header Pin out J1J2 93 Table 25 SGPIO Header Pin out 9143 on S1200BTL and J2J2 on 51200 5 93 Table 26 Front Panel SSI Standard 24 pin Connector Pin out 1 1 on S1200BTL J1C2 on S010 e AKS E EE T ash A 93 Table 27 System Status LED Indicator States 95 Table 28 VGA Connector 96 Table 29 RJ 45 10 100 1000 NIC Connector Pin out
7. 8 103 Server Board Jumpers J1F1 J1F2 J1F3 J1E2 and J4A2 on S1200BTL 104 Server Board Jumpers J2G1 J1G1 J1H3 and J2J1 on S1200BTS 105 Front Panel LED Behavior 109 Server Board Design Specifications 111 Intel Xeon Processor 2 112 350 W Load e a bep Sasu D uas 112 Voltage Regulation Limits tee b tete M te tede a M reb bud 113 Transient Load Requirements tren tn rec nini ER rte RUE E Rn Rn Eu 113 Capacitve Loading Conditions tta e conn tie En Rn Fuse quan 114 Ripple and Io pP 114 Output Voltage Timing qu m rta E 115 TUM OMO TIMING ccm 116 Over Gurrent Protection OCP tees aw ees rede 117 Over voltage Protection OVP Limits arn 117 Gore Sensors DM RH NER ded eae nt eee vb 122 POST Progress Code LED 2 129 POST Progress 2096 eee erbe er e ERR HER 129 POST Error Codes and Messages a irc cei 133 POST Error Beep Codes oro EO E 135 Intel order number G13326 003 List of Tables xii This is intentionally left blank gt Intel order number
8. r 78 Figure 29 System Information Screen 51200 5 79 Figure 30 BMC LAN Configuration Screen 51200 80 Figure 31 Hardware Monitor Screen Auto Fan Control S1200BTS 81 Figure 32 Hardware Monitor Screen Manual Fan Control 54200 5 81 viii Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS List of Figures Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Revision 1 0 Realtime Teperature and Voltage Status Screen 51200 5 82 Boot Options Screen Fel etur tete Fa emer 83 Hard Disk Order Screen 84 CDROM Order e 84 Floppy Order Screen esas ir bae tm Ede 85 Network Device Order Screen a 85 BEV Device Order Screen bota eei 86 Add EFI Boot Option 86 Delete EFI Boot Option 5 87 Boot Manager Screen 87 Error Manager SeIBOlT ect 88 System Event Log Screen S1200BTS
9. 5 holdup I I T V out I i T TAC on delay gt I Tsb on delay E Tpwok_holdup gt i Tpwok low T t i 1 2 H Tpwok on gt lt Tpwok_off pe Tsb on delay I i 1 I 1 i T 108 i 5 VSB Fe gt I i i i I I I 1 I 1 I gt Tpson on delay I lt _ re Tpwok off Tpson pwok I I i PSON i lt AC turn on off cycle lt PSON turn on off cycle gt AF002710 Figure 50 Turn On Off Timing Power Supply Signals Intel order number G13326 003 Revision 1 0 Intel amp Server Board S1200BT TPS Design and Environmental Specifications 10 3 11 Residual Voltage Immunity in Standby Mode The power supply is immune to any residual voltage placed on its outputs typically a leakage voltage through the system from standby output up to 500 mV There is no additional heat generated nor stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously It also does not trip the power supply protection circuits during turn on The residual voltage at the power supply outputs for no load condition does not exceed 100 mV when AC voltage is applied and the signal is de asserted 10 3 12 Protection Circuits
10. AF003618 Figure 47 Jumper Blocks J2G1 J1G1 J1H3 and J2J1 on S1200BTS Table 43 Server Board Jumpers J2G1 J1G1 J1H3 and J2J1 on S1200BTS Jumper Name Pins System Results J1H3 CMOS 1 2 These pins should have a jumper in place for normal system operation Default Clear 2 3 If these pins are jumpered with AC power plugged the CMOS settings are cleared within five seconds These pins should not be jumpered for normal operation J1J2 ME Force 1 2 ME Firmware Force Update Mode Disabled Default Update 2 8 ME Firmware Force Update Mode Enabled J1G1 1 2 These pins should have a jumper in place for normal system operation Default Password Clear 2 3 If these pins are jumpered administrator and user passwords are cleared within 5 10 seconds after the system is powered on These pins should not be jumpered for normal operation J2G1 BIOS 1 2 These pins should have a jumper in place for normal system operation Default Recovery 2 3 Given that the main system BIOS will not boot with these pins jumpered system can only boot from EFlI bootable recovery media with the recovery BIOS image 81 CMOS Clear and Password Reset Usage Procedure The CMOS Clear and Password Reset recovery features are designed such that the desired operation can be achieved with minimal system downtime The usage procedure for these two Revision 1 0 105 Intel order number G13326 003 Jump
11. 39 4 2 5 Embedded Platform Debug ree e cse ee 40 4 2 6 Data Center Management Interface 41 4 2 7 Local Directory Authentication Protocol LDAP 41 4 3 Thermal METTE 41 4 3 1 Memory Thermal Throttling ia p 41 4 3 2 Fan Speed dot e Pete tr pct ao bm re pale 42 4 4 Intel Intelligent Power Node Manager 42 4 4 1 CVG PUI scs cata eot ME M LI KE Ct c e 42 4 4 2 alyaSess 43 4 4 3 Role of Integrated BMC in 44 Revision 1 0 Intel order number G13326 003 Table of Contents Intel Server Board 51200 TPS 5 Server Management Capability for Intel Server Board S1200BTS 46 5 1 n C ere ene 46 5 1 1 Key Features of supper l O eue rer epe 46 6 BIOS User Interfaces 47 6 1 BIOS POST pe Ease eter me 47 6 1 1 BIOS Revision Identification 47 6 2 HotKeys Supported During POST 48 6 3 POST Log
12. A Status LED F Diagnostic LED 4 B ID LED G Diagnostic LED 3 Diagnostic LED 7 MSB LED H Diagnostic LED 2 D Diagnostic LED 6 Diagnostic LED 1 E Diagnostic LED 45 Diagnostic LED 0 LSB LED 110 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 5 Design and Environmental Specifications 10 Design and Environmental Specifications 10 1 Intel Server Board S1200BT Design Specifications The operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 45 Server Board Design Specifications 0 C to 55 C 32 F to 131 F 40 C to 70 C 40 F to 158 F 5 of all nominal voltages Shock Packaged 20 pounds 36 inches 20 to 40 pounds 30 inches 40 to 80 pounds 24 inches 80 to 100 pounds 18 inches 100 to 120 pounds 12 inches 120 pounds 9 inches Vibration Unpackaged 1 Chassis design must provide proper airflow to avoid exceeding the Intel Xeon processor maximum case temperature Disclaimer Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet
13. 1149 1 JTAG note that BSDL testing is NOT supported 3 8 2 Gigabit Ethernet PHY 82579 The 82579 is a single port Gigabit Ethernet Physical Layer Transceiver PHY It connects to the Intel C200 series Chipset s integrated Media Access Controller MAC through a dedicated interconnect The 82579 supports operation at 1000 100 10 Mb s data rates The PHY circuitry Revision 1 0 29 Intel order number G13326 003 Functional Architecture Intel Server Board 51200 TPS provides a standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASE TX and 10BASE T applications 802 3 802 3u and 802 3ab Lewisville also supports the Energy Efficient Ethernet EEE 802 az specification The 82579 operates with the Platform Controller Hub PCH chipset that incorporates the MAC and interfaces with its integrated LAN controller through two interfaces PClebased and SMBus The PCle main interface is used for all link speeds when the system is in an active state SO while the SMBus is used only when the system is in a low power state Sx In SMBus mode the link speed is reduced to 10 Mb s dependent on low power options The PCle interface incorporates two aspects a PCle SerDes electrically and a custom logic protocol 3 8 3 MAC Address Definition Each Intel Server Board S1200BTL has the following four MAC addresses assigned to it at the Intel factory NIC 1 MAC address NIC 2 MAC address Assigned the NIC 1 MAC address 1 I
14. Intel Remote Management Module 4 Intel 4 lite connector is not compatible with the Intel Remote Management Module Product Order Code Intel Remote Management Module 2 Product Order Code 2 or Intel Remote Management Module 3 Product Order Code Clear the CMOS with the AC power cord plugged in Removing the AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down after the CMOS clear procedure is followed and AC power is re applied If this happens remove the AC power cord wait 30 seconds and then re connect the AC power cord Power up the system and proceed to the F2 BIOS Setup utility to reset the needed settings Normal Integrated BMC functionality is disabled with the force Integrated BMC update jumper set to the enabled position pins 2 3 The server should never be run with the Integrated BMC force update jumper set in this position and should only be used when the standard firmware update process fails This jumper should remain in the default disabled position pins 1 2 when the server is running normally When performing a normal BIOS update procedure the BIOS recovery jumper must be set to its default position pins 1 2 Revision 1 0 119 Intel order number G13326 003 Appendix B Integrated BMC Sensor Tables Intel amp Server Board S1200BT TPS Appendix B Integrated BMC Sensor Ta
15. To access this screen from the Main screen or other top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Boot Options screen is selected 82 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 BIOS User Interface e REST Boot Options Manager System Boot Timeout Boot Option 1 Boot Option 2 Boot Option n Hard Disk Order gt CDROM Order gt Floppy Order gt Network Device Order BEV Device Order Add EFI Boot Option gt Delete EFI Boot Option EFI Optimized Boot Enabled Disabled Use Legacy Video for EFI OS Enabled Disabled Boot Option Retry Enabled Disabled USB Boot Priority Enabled Disabled Figure 34 Boot Options Screen 6 5 2 19 Hard Disk Order The Hard Disk Order screen allows the user to control the order in which BIOS attempts to boot from the hard disk drives installed in the system This screen is only available when there is at least one hard disk device available in the system configuration Note A USB Hard Disk drive or a USB Key device formatted as a hard disk will appear in this section To access this screen from the Main screen select Boot Options gt Hard Disk Order To move to another screen press the Esc key to return to the Boot Options screen then select the desired screen Revision 1 0 83 Intel order number G13
16. specific Processor Thermal Control 96 8h P1 Therm Ctrl 96 Oh h 2h Oh h h D 1 Catastrophic Error 8 CATERR MSID Mismatch 8 MSID Mismatch Processor Population Fault CPU Missing Processor VRD Temperature P1 VRD Hot Power Supply 1 Fan Tachometer 1 PS1 Fan Tach 1 Power Supply 1 Fan Tachometer 2 PS1 Fan Tach 2 Revision 1 0 Processor Sensor Specific 07h 6Fh Processor Digital Discrete As and 1 Non fatal Processor Digital Discrete As and 1 A Non fatal Al Processor Digital Discrete 07h 03h Chassis A1 Fan Threshold 04h 01h Chassis Fan specific 04h Sensor Type Event Reading Type Event Offset Triggers Contrib To System Assert De Readable Event Rearm assert Data Status Threshold Lube mal nc Degraded 01 Non fatal De Threshold u Degraded 01h Non fatal Threshold Degraded As and 01h Non fatal 01 Thermal trip Fatal e As and Value Offsets Current 03h Temperature 01h Temperature Temperature 01h Temperature 01h Non fatal Threshold 01h Threshold Degrageg Oth u c nc De 01 State Asserted D As and As and i Temperature 01h Digital Discrete 05h 01 Limit exceeded Threshold 01h Intel order number G13326 003 125 Stand by Appendix B Integrated BMC Sensor Tables Intel amp Server Board S1200BT TPS
17. BMC Boot Flash RMM4 LITE Module SERIAL 2 Internal Header el SERIAL 1 Notes Rear I O Rear I O 1 Video integrated into BMC VGA Port COM Port Module Figure 11 Intel Server Board S1200BTL Functional Block Diagram Revision 1 0 15 Intel order number G13326 003 Functional Architecture Intel amp Server Board 51200 TPS Intel Server Board S1200BTS Block Diagram x16 connector Ag Slot 7 APA x8 connector DDR3 Channel A Slot 6 gt gt 4 Unbuffered 22 DIMMs DDR3 Channel B 21 19 x8 connector Slot 5 Slot 4 9 VIDEO Rear I O VGA Port SATA II Nag Header 9 SERIAL 1 SERIAL 2 Rear I O Internal COM Port Header USB USB Internal USB Type A Rear I O USB Header x2 Header Ports x2 Figure 12 Intel Server Board S1200BTS Functional Block Diagram 3 1 Processor Sub System The Intel Server Board S1200BT supports the following processor Intel Xeon Processor E3 1200 Series Intel Core Processor i3 2100 Series The Intel Xeon Processor E3 1200 Series are made up of multi core processors based on the 32 nm processor technology Intel Core Processor i3 2100 Series are made up of dual core processors based on the 32nm processor technology 3 1 1 Intel Xeon Processor E3 1200 Series The Intel Xeon Processor E3 120
18. Processor initialization 0x36 XX OO X O O X CPU PEI Module for CPU SMM initialization 0x4F X O X X O OOO Dxe IPL started DXE Phase 0x60 X O O X X X X X DXE Core started 0x61 X O O X X X X O DXE NVRAM initialization 0x62 X O O X X X O X SB RUN initialization 0x63 X O O X X X O O Dxe CPU initialization 0x68 X O O X O X X X DXE PCI Host Bridge initialization 0x69 X O O X O X X O DXE NB initialization 0x6A X O O X O X O X DXE NB SMM initialization 0x70 X OOO X X X X DXE SB initialization Intel amp Server Board 51200 TPS Appendix C POST Code Diagnostic LED Decoder Diagnostic LED Decoder O On X Off Progress Code Upper Nibble Lower Nibble Description MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB 7 6 5 4 3 2 1 0 0 71 XO OO X X X O DXE SB SMM initialization 0x72 XO OO X X O X DXE SB devices initialization 0x78 XO OO O X X X DXE initialization 0x79 XO OO O X X O DXE CSM initialization 0x90 O XX O X X X X DXE BDS Started 0x91 O X X O X X X O DXE BDS connect drivers 0x92 O X X O X X O X DXE PCI Bus begin 0x93 O X X O X X O O DXE PCI Bus HPC initialization 0x94 O X X O X O X X DXE PCI Bus enumeration 0x95 O X X O X O X O DXE PCI Bus resource requested 0x96 O X X O X O O X DXE PCI Bus assign resource 0x97 O X X O XO OO DXE CON_OUT connect 0x98 O X X O O X X X DXE CON_IN connect 0x99 O X X O O X X O DXE SIO initialization 0
19. DIMM A1 Installed Not Installed Failed Disabled DIMM A2 Installed Not Installed Failed Disabled DIMM B1 Installed Not Installed Failed Disabled DIMM B2 Installed Not Installed Failed Disabled Figure 18 Memory Configuration Screen 68 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS BIOS User Interface Screen Field Descriptions 1 Total Memory Option Values Total Physical Memory Installed in System Help Text None Comments Information only Displays the amount of memory available in the system in the form of installed DDR3 DIMMs in units of GB Effective Memory Option Values Total Effective Memory Help Text None Comments Information only Displays the amount of memory available to the OS in MB or GB The Effective Memory is the difference between Total Physical Memory and the sum of all memory reserved for internal usage RAS redundancy and SMRAM This difference includes the sum of all DDR3 DIMMs that failed Memory BIST during POST or were disabled by the BIOS during the memory discovery phase in order to optimize memory configuration Note some server operating systems do not display the total physical memory installed Revision 1 0 69 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS 70 Current Configuration Option Values Single Channel Dual Channel Symmetric Intel Flex Help Text None Comment
20. Word 16 bit quantity WS MAN Web Services for Management Revision 1 0 139 Intel order number G13326 003 i Server Management Interrupt SMI is the highest priority non maskable interrupt V V ROM RTC SDR EL IO 5 5 5 BD DP IM UDP URS UTC ID RD T Glossary Intel amp Server Board 51200 TPS ZIF Zero Insertion Force 140 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Reference Documents Reference Documents Refer to the following documents for additional information Intel Server Board S1200BT BIOS External Product Specification Intel Server Board 1200BT Common Core Integrated BMC External Product Specification Revision 1 0 141 Intel order number G13326 003
21. 2 150 54 61 2 645 167 18 3700 93 98 4 600 116841 5 780 14681 6 480 164 59 7 180 182 37 7 880 200 15 0 085 216 a 54 28 77 1 m 4 531 11510 1 418 36 01 11 210 284 73 0 296 7 51 0 280 7101 0 255 648 1 AF003632 Figure 7 Intel Server Board S1200BTL Major Connector Pin Location 2 of 2 Revision 1 0 Intel order number G13326 003 Overview 6 680 169 67 Overview Intel amp Server Board 51200 TPS MAX COMPONENT HEIGHT 0 068 AREA MAX HEIGHT FOR VR FET IS 0 043 RMM4 LITE MAX COMPONENT MAX HEIGHT FOR OTHER COMPONENTS 15 0 035 COMPONENT HEIGHT 0 050 6 PLACES HEIGHT 0 2 osso 16 511 NO PIN THRU HOLE COMPONENT ZONE 9 PLACES TRUSTED PLATFORM MODULE MAX COMPONENT HEIGHT 0 2 0400 10 16 GROUND PADS 9 PLACES COMPONENT HEIGHT RESTRICTION 0 10 MAX IEATSINK FEET AREA NO COMPONENTS TRACES OR VIAS ALLOWED HERE TOTAL TWO AREAS SSeS d 0240 6101 COMPONENT HEIGHT RESTRICTION CPU ILM MOUNTING HOLE 0 059 MAX BOARD ROUNTING KEEP OUT ZONE BARE DIE HEATSINK WIRE CLIP AREA MAX COMPONENT HEIGHT 0 125 3 175MM 2 PLACES COPPER PAD ON SURFACE 7 PLACES PU HEATSINK 0 370 MAX COMPONENT HEIGHT RESTRICTION JOMPONENT HEIGHT RESTRICTION 0 047 MAX PU HEATSINK AREA NO COMPONENT
22. Protection circuits inside the power supply should cause only the power supply s main outputs to shut down If the power supply latches off due to a protection circuit tripping an AC cycle OFF for 15 seconds and a PSON cycle HIGH for 1 second should reset the power supply 10 3 12 1 Over current Protection OCP The power supply has current limits to prevent the 3 3 V 5 V and 12 V outputs from exceeding the values shown in the following table If the current limits are exceeded the power supply shuts down and latches off The latch is cleared by toggling the PSON signal or using an AC power interruption The power supply is not damaged from repeated power cycling in this condition 12 V and 5 VSB are protected under over current or shorted conditions so no damage can occur to the power supply Auto recovery feature is a requirement on 5 VSB rail Table 54 Over Current Protection OCP VOLTAGE OVER CURRENT LIMIT 3 3V 15A 21A 5V 20A 27A 30A 40 0 625A 2A 5VSB N A 4A 10 3 12 2 Over Voltage Protection OVP The power supply over voltage protection is locally sensed The power supply shuts down and latches off after an over voltage condition occurs You can clear this latch by toggling the PSON signal or using an AC power interruption The following table contains the over voltage limits The values are measured at the output of the power supply s connectors The voltage never exceeds the maximum levels when measured at the p
23. TPS Item Description Minimum Maximum Units Ts on delay Delay from AC being applied to 5 VSB being within regulation N A 1500 Msec on delay Delay from AC being applied to all output voltages being within regulation N A 2500 Msec Tvout_holdup Duration for which all output voltages stay within regulation after loss of AC Measured at 80 of maximum load 21 N A Msec Tpwok_holdup Delay from loss of AC to de assertion of PWOK Measured at 80 of maximum load 20 N A Msec Tpson_O n_del ay Delay from PSON active to output voltages within regulation limits 5 400 Msec Tpson_Pwok Delay from PSON deactive to PWOK being de asserted N A 50 Msec Tpwok_On Delay from output voltages within regulation limits to PWOK asserted at turn on 100 500 Msec Tpwo O ff Delay from PWOK de asserted to output voltages 3 3 V 5 V 12 V 12 V dropping out of regulation limits N A Msec Tpwok_low Duration of PWOK being in the de asserted state during an off on cycle using AC or the PSON signal 100 N A Msec Tsb_vout Delay from 5 VSB being in regulation to O Ps being in regulation at AC turn on 50 1000 Msec Tsvsp_holdup Duration for which the 5 VSB output voltage stays within regulation after loss of AC 70 N A Msec 116 AC Input
24. lt None gt Comments Information only Displays the Processor Signature value from the CPUID instruction identifying the type of processor and the stepping Processor Frequency Option Values Current Processor Operating Frequency Help Text None Comments Information only Displays current operating frequency of the processor 2 Microcode Revision Option Values lt Microcode Revision Number Help Text None Comments Information only Displays Revision Level of the currently loaded processor microcode 3 11 Cache RAM Option Values L1 cache size Help Text None Comments Information only Displays size in KB of the processor L1 Cache Since L1 cache is not shared between cores this is shown as the amount of L1 cache per core There are two types of L1 cache for the SandyBridge processor family this amount is the total of L1 Instruction Cache plus L1Data Cache for each core 4 12 Cache RAM Option Values L2 cache size Help Text None Comments Information only Displays size in KB of the processor L2 Cache Since L2 cache is not shared between cores this is shown as the amount of L2 cache per core 5 1 Cache RAM Option Values L3 cache size Help Text None Comments Information only Displays size in MB of the processor L3 Cache Since L3 cache is shared between all cores in a processor package this is shown as the total amount of L3 cache per processor package S1200BT boards have
25. r 109 9 2 Post Code Diagnostic LEDS cic an cee Ie a ee a ees ed 109 10 Design and Environmental Specifications 111 10 1 Intel Server Board S1200BT Design 111 10 2 Board level Calculated 111 10 2 1 Processor Power Support soe cR Ee EDS 111 10 3 Power Supply Output Requirements 112 uqa 113 10 3 2 Standby OuIpillss 113 10 3 5 Rem te Sense ususin DD 113 10 3 4 Voltage 113 1053 5 Dynamic nna aa ee fut 113 10 3 6 Capacitive eno ert 114 10 377 Slosed Ioop Stability e e Ree dete seem a ee 114 10 3 8 Common Mode Noise eet eerte 114 10 53 97 NOISE y 114 10 3 10 Timing 860 22225555 EE Stute ivan Te 114 10 3 11 Residual Voltage Immunity in Standby Mode 117 10 3 12 Protection 117 Appendix A Integration and Usage Tips U 119 Appendix B Integrated BMC Sensor Tables U u
26. then select the desired screen 84 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface Boot Options Floppy Order Floppy Disk 1 Available Floppy Disk devices Floppy Disk 2 Available Floppy Disk devices Figure 37 Floppy Order Screen 6 5 2 22 Network Device Order The Network Device Order screen allows the user to control the order in which BIOS attempts to boot from the network bootable devices installed in the system This screen is only available when there is at least one network bootable device available in the system configuration To access this screen from the Main screen select Boot Options gt Network Device Order To move to another screen press the Esc key to return to the Boot Options screen then select the desired screen Boot Options Network Device Order Network Device 1 Available bootable Network devices Network Device 2 Available bootable Network devices Figure 38 Network Device Order Screen 6 5 2 23 BEV Device Order The BEV Device Order screen allows the user to control the order in which BIOS attempts to boot from the BEV Devices installed in the system This screen is only available when there is at least one BEV device available in the system configuration To access this screen from the Main screen select Boot Options BEV Device Order move to another screen press the Esc key to return to the Boot Opt
27. 4 Degree Celsius Default Fan PWM 40 60 80 100 Figure 32 Hardware Monitor Screen Manual Fan Control 81200BTS 6 5 2 17 Realtime Temperature and Voltage Status The Realtime Temperature and Voltage Status screen allows the user to view displays of current processor and system fan speeds current system temperature and the status of various voltages which are monitored on the board Revision 1 0 81 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS To access this screen from the Main screen select Server Management gt Hardware Monitor Realtime Temperature and Voltage Status To move to another screen press the Esc key to return to the Hardware Monitor screen if necessary press the Esc key again to return to the Server Management screen then select the desired screen Server Management Real time Temperature CPU Fan PWM System Fan PWM System temperature Voltage status Vccp 12V 3 3V 5 0V 41 5V 41 05 3 3V standby Figure 33 Realtime Teperature and Voltage Status Screen S1200BTS 6 5 2 18 Boot Options Screen Tab The Boot Options screen displays any bootable media encountered during POST and allows the user to configure the desired order in which boot devices are to be tried The first boot device in the specified Boot Order which is present and bootable during POST will be used to boot the system any time the system is rebooted after that
28. 6 5 2 3 Advanced Screen Tab The Advanced screen provides an access point to configure several groups of options On this screen the user can select the option group to be configured Configuration actions are performed on the selected screen and not directly on the Advanced screen To access this screen from the Main screen or other top level screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Advanced screen is selected 58 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface Security Server Management Boot Options Boot Manager Figure 16 Advanced Screen Revision 1 0 59 Intel order number G13326 003 BIOS User Interface Intel Server Board 51200 TPS Screen Field Descriptions 60 1 Processor Configuration Option Values None Help Text View Configure processor information and settings Comments Selection only Position to this line and press the Enter key to go to the Processor Configuration group of configuration settings Memory Configuration Option Values None Help Text View Configure memory information and settings Comments Selection only Position to this line and press the Enter key to go to the Memory Configuration group of configuration settings Mass Storage Controller Configuration Option Values None Help Text View Configure mass storage controller information and
29. 97 37 4 270 108 45 5 957 151 32 6 100 154 94 6 672 169 46 6 787 172 38 7 389 187 68 7 930 201 42 8 950 227 33 9 043 229 69 5 qa AF003629 Figure 5 Intel Server Board S1200BTL Hole and Component Positions Revision 1 0 9 Intel order number G13326 003 Overview 0 000 0 00 0 420 10 67 1 225 31 12 1 389 3528 4 575 116 19 6 045 153 55 7 959 202 16 8 333 211 66 8 569 217 65 8 770 22276 0 000 0 00 7 92 1 1 005 25 53 1811 46 00 2611 66 32 0312 Gad pu 0 400 10161 1507 1 0322 8471 1524 Intel amp Server Board S1200BT TPS Se ro EN 3 8 4 ns 9 83 2 Roa Ra 26 Sa 2 5 AS Kt lt SA rT n nm o C 1 Figure 6 Intel Server Board S1200BTL Major Connector Pin Location 1 of 2 Revision 1 0 Intel order number G13326 003 T VEI S EUN gr k vas de 0 64 5 624 1 0 652 16 56 ml I 1 1 500 38 10 1 5 500 13970 6 115 155 32 7 687 195 24 8 770 222751 28 eS of 8 ot Bh S6 8 Sa 8 54099 Intel amp Server Board S1200BT TPS 0 000 0 00 1300 33 02
30. BARE DIE HEATSINK ANCHOR SOLDERING AREA NO COMPONENT ALLOWED 2 PLACES HEIGHT RESTRICTION 0 1 MAX MAX COMPONENT HEIGHT 0 1 FOR SAS MODULE KEY POWER CONNECTOR IT 20 0057 COMPONENT HEIGHT MAX COMPONENT HEIGHT 0 20 2PLACES RESTRICTION MAX COMPONENT HEIGHT 0 07 00236 NOCOMPONENT ZONE 16 00 FOR ADD ON CARD RETENTION COMPONENT HEIGHT 0 080 5 PLACES COMPONENT HEIGHT 0 100 MAX COMPONENT HEIGHT 0 137 COMPONENT HEIGHT 0 236 AF003633 Figure 8 Intel Server Board S1200BTL Primary Side Keepout Zone 12 Revision 1 0 Intel order number G13326 003 Overview Intel amp Server Board S1200BT TPS ROATX ATX COMPONENT HEIGHT RESTRICTION NO COMPONENT ZO 25 BASEBOARD MOUNTING RESTRICTED AREA IMITED COMPONENT HEIGHT 0 058 MAX 9PLACES UA BASEBOARD MOUNTING KEEPOUT AREA NO COMPONENT ZONE 9 PLACES ROATX COMPONENT HEIGHT RESTRICTION MAX 007 AF003637 Figure 9 Intel Server Board S1200BTL Secondary Side Keepout Zone Revision 1 0 Intel order number G13326 003 Overview Intel amp Server Board 51200 TPS 2 2 3 Server Board Rear I O Layout The following figure shows the layout of the rear components for the server board im AF003511 A Serial Port A C NIC Port 1 1 Gb and Dual USB Port Connector B Video D NIC port 2 1 Gb and Dual USB Port Connector
31. BE 1 A44 AD 15 B14 RSVD A14 3 3Vaux B45 AD 14 A45 3 3V B15 Ground A15 RST B46 Ground A46 AD 13 B16 CLK A16 V IO B47 AD 12 A47 AD 11 B17 Ground A17 GNT B48 AD 10 A48 Ground Intel order number G13326 003 Intel amp Server Board 51200 TPS Connector Header Locations and Pin outs Pin Signal Pin 4 Signal Pin Signal Pin Signal B18 REQ 18 Ground B49 M66EN A49 AD 09 B19 V IO A19 PME B50 KEY 50 20 AD 31 A20 AD 30 B51 KEY 51 21 AD 29 21 43 3V B52 AD 08 A52 C BE 0 B22 Ground A22 AD 28 53 AD 07 A53 3 3V B23 27 A23 AD 26 B54 3 3V 54 AD 06 B24 AD 25 A24 Ground B55 AD 05 A55 AD 04 B25 3 3V A25 AD 24 B56 AD 03 56 Ground B26 C BE 3 A26 IDSEL B57 Ground 57 AD 02 B27 AD 23 A27 3 3V B58 AD 01 58 AD 00 B28 Ground A28 AD 22 B59 V IO A59 V IO B29 AD 21 A29 AD 20 B60 ACK64 A60 REQ64 B30 AD 19 A30 Ground B61 5V A61 5V B31 3 3V A31 AD 18 B62 5V A62 5V 7 7 Fan Headers The server board provides five SSI compliant 4 pin fan headers to be used as the CPU and chassis The pin configuration for each of the 4 pin fan headers is identical and defined in the following table 4 pin fan headers are designated as processor cooling fans CPU fan J5J1 on S1200BTL and J4J1 on S1200BTS SYS1 fan J1J4 on S1200BTL and J7J1 on S1200BTS SYS2 fan 542 on S1200BTL and 7 1 on S1200BTS SYS3 fa
32. BIOS Boot Pop up Menu The BIOS Boot Specification BBS provides a Boot Pop up menu that can be invoked by pressing the F6 key during POST The BBS Pop up menu displays all available boot devices The boot order in the pop up menu is not the same as the boot order in the BIOS setup The pop up menu simply lists all of the available devices from which the system can be booted and allows a manual selection of the desired boot device When an Administrator password is installed in Setup the Administrator password will be required in order to access the Boot Pop up menu using the F6 key If a User password is entered the Boot Pop up menu will not even appear the user will be taken directly to the Boot Manager in the Setup where a User password allows only booting in the order previously defined by the Administrator 6 5 BIOS Setup Utility The BIOS Setup utility is a text based utility that allows the user to configure the system and view current settings and environment information for the platform devices The Setup utility controls the platform s built in devices the boot manager and error manager The BIOS Setup interface consists of a number of pages or screens Each page contains information or links to other pages The advanced tab in Setup displays a list of general categories as links These links lead to pages containing a specific category s configuration The following sections describe the look and behavior for the platfo
33. CPU C 56 4 27 GND GND B28 2 CPU C 56 4 28 GND GND B29 GND GND A29 P2E CPU 56 lt 4 gt B30 RSVD NC A30 P2E CPU 56 lt 4 gt B31 PRSNT2 N NC A31 GND GND B32 GND GND A32 RSVD NC End of x4 End of x4 B33 PETP4 P2E_CPU_C_S6_TXP lt 3 gt A33 RSVD NC B34 PETN4 P2E_CPU_C_S6_TXN lt 3 gt A34 GND GND B35 GND GND A35 PERP4 P2E_CPU_S6_RXN lt 3 gt B36 GND GND A36 PERN4 P2E_CPU_S6_RXP lt 3 gt B37 PETP5 P2E_CPU_C_S6_TXP lt 2 gt A37 GND GND B38 PETN5 P2E_CPU_C_S6_TXN lt 2 gt A38 GND GND 100 Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT TPS Connector Header Locations and Pin outs Pin Signal Description Pin Signal Description B39 GND GND A39 PERP5 2 CPU S6 RXN 2 B40 GND GND A40 PERN5 P2E CPU S6 lt 2 gt B41 6 2 CPU C S6 1 A41 GND GND 42 PETN6 P2E CPU C S6 TXN 1 A42 GND GND B43 GND GND 43 PERP6 P2E CPU S6 RXN 1 B44 GND GND A44 PERN6 P2E CPU S6 RXP 1 B45 PETP7 P2E CPU C 56 lt 0 gt A45 GND GND B46 7 2 56 0 46 GND GND B47 GND GND A47 PERP7 2 CPU S6 0 B48 PRSNT2 N NC A48 PERN7 P2E CPU S6 RXP 0 B49 GND GND A49 GND GND End of x8 End of x8 B50 PETP8 A50 RSVD NC B51 8 51 GND GND B52 GND G
34. ECC UDIMMs anywhere the platform is not supported Static Closed Loop Thermal Throttling supported via BMC requires ECC DIMMs with thermal sensor 3 2 2 Post Error Codes The range 0 OxEF of POST codes is used for memory errors in early POST In late POST this same range of POST code values is used for reporting other system errors OxE8 No Usable Memory Error If no usable memory is available the BIOS emits beep code and displays POST Diagnostic LED code OxE8 and halts the system 18 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Functional Architecture This can also occur if all memory in the system fails and or has become disabled during memory initialization For example if a DDR3 DIMM has no SPD information the BIOS treats the DIMM slot as if no DDR3 DIMM is present on it Therefore if this is the only DDR3 DIMM installed in the system there is no usable memory the BIOS goes to a memory error code OxE8 as described above Channel Training Error If the memory initialization process is unable to properly perform the Data Data Strobe timing training on a memory channel the BIOS emits a beep code and displays POST Diagnostic LED code OXEA momentarily during the beeping If there is usable memory in the system on other channels POST memory initialization continues Otherwise the system beeps and halts with POST Diagnostic LED code OxEA staying
35. G13326 003 Intel Server Board 51200 TPS Revision 1 0 Intel Server Board S1200BT TPS Introduction 1 Introduction This Technical Product Specification TPS provides board specific information detailing the features functionality and high level architecture of the Intel Server Board S1200BT In addition you can obtain design level information for specific subsystems by ordering the External Product Specifications EPS or External Design Specifications EDS for a given subsystem EPS and EDS documents are not publicly available and must be ordered through your local Intel representative 1 1 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Server Board Overview Chapter 3 Functional Architecture Chapter 4 Platform Management Chapter 5 Server Management Capability Chapter 6 BIOS User Interface Chapter 7 Connector Header Locations and Pin outs Chapter 8 Jumpers Blocks Chapter 9 Intel Light Guided Diagnostics Chapter 10 Design and Environmental Specifications Appendix A Integration and Usage Tips Appendix B Integrated BMC Sensor Tables Appendix C POST Code Diagnostic LED Decoder Appendix D POST Code Errors Appendix E Supported Intel Server Chassis Glossary Reference Documents 1 2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high
36. If Quiet Boot is enabled in the BIOS setup a splash screen is displayed with a logo image which is the standard Intel Logo Screen or a customized OEM Logo Screen By default Quiet Boot is enabled in the BIOS setup so the Logo Screen will be the default POST display However if the logo is displayed during POST the user can press Esc to hide the logo and display the Diagnostic Screen instead If a logo is not present in the BIOS Flash Memory space or if Quiet Boot is disabled in the system configuration the POST Diagnostic Screen is displayed with a summary of system configuration information The diagnostic screen displays the following information Copyright year Intel Corporation AMI Copyright statement BIOS version ID BMC firmware version SDR version ME firmware version Platform ID identifies the board on which the BIOS is running System memory detected total size of all installed DDR3 DIMMs Current memory speed currently configured memory operating frequency Processor information Intel Brand String identifying type of processor and nominal operating frequency and number of physical processors identified Keyboards detected if any attached Mouse devices detected if any attached Instructions showing hotkeys for going to Setup going to popup Boot Menu starting Network Boot Revision 1 0 49 Intel order number G13326 003 BIOS User Interface Intel Server Board 51200 TPS 6 4
37. If these pins are jumpered with AC power plugged the CMOS settings are cleared within five seconds These pins should not be jumpered for normal operation J1F2 ME 1 2 ME Firmware Force Update Mode Disabled Default Force Update 2 3 ME Firmware Force Update Mode Enabled J1F1 1 2 These pins should have a jumper in place for normal system operation Default Password Clear 2 3 If these pins are jumpered administrator and user passwords are cleared within 5 10 seconds after the system is powered on These pins should not be jumpered for normal operation J1F3 BIOS 1 2 These pins should have a jumper in place for normal system operation Default Recovery 2 3 Given that the main system BIOS will not boot with these pins jumpered system can only boot from EFI bootable recovery media with the recovery BIOS image J4A2 BMC 1 2 Integrated BMC Firmware Force Update Mode Disabled Default Force Update 2 3 Integrated BMC Firmware Force Update Mode Enabled 104 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS Recovery 2 3 J2G1 Protected RTC 2 3 ME Force Update J2J1 a Default r Enabled Default F Cleared Default F Clear Default Enabled Jumper Blocks es E B
38. Nuvoton LOT6 CK420BQ DB1900Z XDP 0 Ox6C 0 2 0 08 SMLink0 400kHz 3 3V 5 Lewsville 0xC8 Bromollow HSBP 3 3 8 0 88 0x88 is default for SSB HSBP1 HSBP2 HSBP3 PSOC 0 00 PSOC 0xD6 PSOC 0xD4 Temp 0x90 Temp 0x96 Temp 0x94 FRU 0xA0 FRU 0xA6 FRU 0xA4 mmo OxTBD Riser1 Riser2 SAS Module FRU 0xA0 FRU 0xA2 FRU 0xA4 FRU 0xA6 Temp 0x90 Temp 0x92 Temp 0x94 Temp 0x96 PMBus 3 3V 5 SMLink1 100kHz 3 3V STBY 1 OxTBD PATSBURG A D 0 0 STUFFED PMBus PS 1 PMBus PS 0 FRU 0xA0 Device FRU 0xA2 Device 0 2 0 0 S SMBusSlave Main _ SMBus Master Main MM SMBus Multi Master Main SMBus Multi Master Standby SMBus Slave Standby Figure 14 Server Management Bus SMBUS Block Diagram 32 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Platform Management 4 1 Feature Support 4 1 1 IPMI 2 0 Features Baseboard management controller BMC IPMI Watchdog timer Messaging support including command bridging and user session support Chassis device functionality including power reset control and BIOS boot flags support Event receiver device The BMC receives and processes events from other platform subsystems Field replaceable unit FRU inventory device functionality The BMC supports access to system FRU
39. OOO XX OO Recovery PEIM Capsule found OxF4 0000 X O Recovery PEIM Capsule loaded 132 Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT TPS Appendix D POST Code Errors Appendix D POST Code Errors The BIOS outputs the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information The class and subclass fields point to the type of hardware that is being initialized The operation field represents the specific initialization activity Based on the data bit availability to display progress codes a progress code can be customized to fit the data width The higher the data bit the higher the granularity of information that can be sent on the progress port The progress codes may be reported by the system BIOS or option ROMs The Response section in the following table is divided into three types Pause The message displays on the screen during POST or in the Error Manager The system continues booting with a degraded state The user may want to replace the erroneous unit The setup POST error Pause setting does not have any effect with this error Pause The message displays on the Error Manager screen and an error is logged to the SEL The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error where the user can take immediate c
40. are ECC UDIMMs only with a maximum size of 8 GB Slot must be populated first before Slot2 on either channel Channel A and Channel B are independent and are not required to have the same number of DIMMs installed Either channel may be used for a single DIMM configuration o When only one memory channel is populated the memory runs in Single Channel mode with no interleaving 3 2 5 Memory RAS Support For Intel Server Board S1200BT the form of Memory RAS provided is Error Correction Code ECC ECC uses extra bits 64 bit data in a 72 bit DRAM array to add an 8 bit calculated Hamming Code to each 64 bits of data This additional encoding enables the memory controller to detect and report single or double bit errors and to correct single bit errors There is a specific step in memory initialization in which all of memory is cleared to zeroes before the ECC function is enabled in order to bring the ECC codes into agreement with memory contents During operation in the process of every fetch from memory the data and ECC bits are examined for each 64 bit data 8 bit ECC group If the ECC computation indicates that a single bit Correctable Error has occurred it is corrected and the corrected data is passed on to the processor If a double bit Uncorrectable Error is detected it cannot be corrected In each case a Correctable or Uncorrectable ECC Error event is generated For Correctable Errors there is a certain t
41. contains the following integrated subsystems and features The following is a summary of the BMC management hardware features used by the BMC 400 2 32 bit ARM9 processor with memory management unit MMU Two independent10 100 1000 Ethernet Controllers with Reduced Media Independent Interface RGMII Reduced Gigabit Media Independent Interface support DDR2 3 16 bit interface with up to 800 MHz operation 12 10 bit Analog to Digital Converters Sixteen fan tachometers Eight Pulse Width Modulators PWM Chassis intrusion logic 24 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Functional Architecture Revision 1 0 JTAG Master Eight interfaces with master slave and SMBus timeout support All interfaces are SMBus 2 0 compliant Parallel general purpose 1 Ports 16 direct 32 shared Serial general purpose 1 Ports 80 in and 80 out Three UARTs Platform Environmental Control Interface PECI Six general purpose timers Interrupt controller Multiple SPI flash interfaces NAND Memory interface Sixteen mailbox registers for communication between the Integrated BMC and host LPC ROM interface Integrated BMC watchdog timer capability SD MNC card controller with DMA support LED support with programmable blink rate controls on GPIOs Port 80h snooping capability Secondary Service Processor SSP which provides the HW capability of offloading time critical pro
42. density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system meets the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Revision 1 0 1 Intel order number G13326 003 Overview 2 Overview Intel Server Board 51200 TPS The Intel Server Board S1200BT is a monolithic printed circuit board PCB with features designed to support entry level severs It has two board SKUs namely S1200BTL and S1200BTS 2 1 Intel Server Board S1200BT Feature Set Table 1 Intel Server Board S1200BT Feature Set Description of S1200BTL Description of S1200BTS Processor Chipset Support for one Intel Xeon Processor E3 1200 Series or Intel Core Processor i3 2100 Series in FC LGA 1155 socket package 2 5 GT s point to point DMI interface to PCH 1155 pin socket Two memory channels with support for
43. desired screen 86 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface Boot Options Delete EFI Boot Option Delete Boot Option Select one to Delete Internal EF Shell Figure 41 Delete EFI Boot Option Screen 6 5 2 26 Boot Manager Screen Tab The Boot Manager screen allows the user to view a list of devices available for booting and to select a boot device for immediately booting the system Note This list is not in order according to the system Boot Option order The Internal EFI Shell will always be available regardless of whether any other bootable devices are available To access this screen from the Main screen or other top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Boot Manager screen is selected Main Advanced Security Server Management 127919140 EES Boot Manager Internal EFI Shell lt Boot device 1 gt lt Boot Option 2 gt lt Boot Option n gt Figure 42 Boot Manager Screen 6 5 2 27 Error Manager Screen Tab The Error Manager screen displays any POST Error Codes encountered during BIOS POST along with an explanation of the meaning of the code To access this screen from the Main screen or other top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Error Manager screen is selected Revision 1 0 87 Intel or
44. devices using IPMI FRU commands System event log SEL device functionality The BMC supports and provides access to a SEL Sensor data record SDR repository device functionality The BMC supports storage and access of system SDRs Sensor device and sensor scanning monitoring The BMC provides IPMI management of sensors It polls sensors to monitor and report system health IPMI interfaces o Hostinterfaces include system management software SMS with receive message queue support and server management mode SMM o IPMB interface LAN interface that supports the IPMI over LAN protocol RMCP RMCP Serial over LAN SOL ACPI state synchronization The BMC tracks ACPI state changes that are provided by the BIOS BMC self test The BMC performs initialization and run time self tests and makes results available to external entities Please see the Intelligent Platform Management Interface Specification Second Generation v2 0 for detail information 4 1 2 Non IPMI Features The BMC supports the following non IPMI features This list does not preclude support for future enhancements or additions In circuit BMC firmware update Fault resilient booting FRB FRB2 is supported by the watchdog timer functionality Chassis intrusion detection Basic fan control using TControl version 2 SDRs Power supply redundancy monitoring and support Hot swap fan support Acoustic management Support for multiple fan profiles Revisi
45. devices will appear as floppy disks over media redirection This allows for the installation of device drivers during OS installation If either a virtual IDE or virtual floppy device is remotely attached during system boot both the virtual IDE and virtual floppy are presented as bootable devices It is not possible to present only a single mounted device type to the system BIOS 38 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Platform Management 4 2 3 1 Availability The default inactivity timeout is 30 minutes and is not user configurable Media redirection sessions persist across system reset but not across an AC power loss or BMC reset 4 2 3 2 Network Port Usage The KVM and media redirection features use the following ports 5120 CD Redirection 5123 FD Redirection 5124 CD Redirection Secure 5127 FD Redirection Secure 7578 Video Redirection 7582 Video Redirection Secure 4 2 4 Embedded Web server Integrated BMC Base manageability provides an embedded web server and an OEM customizable web GUI which exposes the manageability features of the Integrated BMC base feature set It is supported over all on board NICs that have management connectivity to the Integrated BMC as well as an optional dedicated add in management NIC At least two concurrent web sessions from up to two different users is supported The embedded web user interface shall support the f
46. displayed Memory Test Error If DDR3 DIMM or set of DDR3 DIMMs on the same memory channel fails memory testing but usable memory remains available the BIOS emits a beep code and displays POST Diagnostic LED code momentarily during the beeping then continues POST If all of the memory fails memory testing then system memory error code OxE8 No Usable Memory as described above OxED Population Error If the installed memory contains an invalid DIMM configuration on any channel in the system the system beeps and halts with POST Diagnostic LED code OxED Note Mixed DIMM configurations are not supported and not validated by Intel 3 2 3 Memory Map and Population Rules The overall configuration is a single processor with two channels and two DIMM slots on each channel on the Intel Server Board S1200BT All memory DIMMs are ECC UDIMMs only with a maximum size of 8 GB Slot must be populated first before Slot2 on either channel Channel A and Channel B are independent and are not required to have the same number of DIMMs installed Either channel may be used for a single DIMM configuration o When only one memory channel is populated the memory runs in Single Channel mode with no interleaving o When both channels are populated identically the memory runs in Dual Channel Symmetric mode The memory is interleaved by full 64 byte cache lines alternating between channels i e the first entire
47. level core frequency cache sizes Intel QuickPath Interconnect information for all processors currently installed It also allows the user to enable or disable a number of processor options To access this screen from the Main screen select Advanced gt Processor Configuration To move to another screen press the Esc key to return to the Advanced screen then select the desired screen Revision 1 0 61 Intel order number G13326 003 BIOS User Interface Intel amp Server Board S1200BT TPS Advanced Processor Configuration Processor ID tepping Processor Frequency Microcode Revision Processor Version Intel Boost Technology Enabled Disabled Enhanced Intel SpeedStep 792 Enabled Disabled urbo Boost Performance Watt Mode Power Optimized T raditional Processor C3 Enabled Disabled Processor C6 Enabled Disabled Intel Hyper Threading Tech Enabled Disabled Core Multi Processing All 1 2 3 Execute Disable Bit Enabled Disabled Intel Virtualization Technology Enabled Disabled Intel VT for Directed VO Enabled Disabled Interrupt Remapping Enabled Disabled Pass through DMA Support Enabled Disabled Hardware Prefetcher Enabled Disabled Adjacent Cache Line Prefetch Enabled Disabled Figure 17 Processor Configuration Screen 62 Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT 5 BIOS User Interface Screen Field Descriptions 1 Processor ID Option Values lt CPUID gt Help Text
48. may include the meaning and usage of the item allowable values effects of the options etc Keyboard Command Bar The Keyboard Command Bar is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys 6 5 1 2 Entering BIOS Setup To enter the BIOS Setup using a keyboard or emulated keyboard press the F2 function key during boot time when the OEM or Intel logo is displayed The following message is displayed on the diagnostics screen and under the Quiet Boot logo screen Press F2 to enter setup When the Setup Utility is entered the Main screen is displayed However serious errors cause the system to display the Error Manager screen instead of the Main screen 6 5 1 3 Setup Navigation Keyboard Commands The bottom right portion of the Setup screen provides a list of commands that are used to navigate through the Setup utility These commands are displayed at all times Revision 1 0 51 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS Each Setup menu page contains a number of features Each feature is associated with a value field except those used for informative purposes Each value field contains configurable parameters Depending on the security option chosen and in effect by the password a menu feature s value may or may not be changed If a value cannot be changed its field is made inaccessible and app
49. mounted as a remote device to the server 15 possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE IMG and CD ROM or DVD ROM ISO files See the Tested supported Operating System List for more information Media redirection shall support redirection for a minimum of two virtual devices concurrently with any combination of devices As an example a user could redirect two CD or two USB devices The media redirection feature supports multiple encryption algorithms including RC4 and AES The actual algorithm that is used is negotiated with the client based on the client s capabilities remote media session is maintained even when the server is powered off in standby mode No restart of the remote media session is required during a server reset or power on off An Integrated BMC reset e g due to an Integrated BMC reset after Integrated BMC firmware update will require the session to be re established mounted device is visible to and useable by managed system s OS and BIOS both pre boot and post boot states mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to boot from this remote device ltis possible to install an operating system on a bare metal server no OS present using the remotely mounted device This may also require the use of KVM r to configure the OS during install USB storage
50. oDh 01 Drive Fault Degraded De HDD 1 Status 02 Predictive Failure Degraded HDD 0 Status progress Degraded Trig Offset Trig Offset Revision 1 0 127 Intel order number G13326 003 Appendix B Integrated BMC Sensor Tables Intel amp Server Board S1200BT TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Type Event Offset Triggers Contrib To System Assert De Readable Event Rearm Stand by Sensor name in SDR Applicability Status assert Data Value Offsets progress 00 Drive Presence 225 Drive 2 Drive Slot Sensor Specific 01 PNE Degraded poem Trig 1 HDD 2 Stat specific 6Fh 02 Predictive Failure Degraded De Offset X 07 Rebuild Remap in Degraded progress 00 Drive Presence Drive 3 Chassis Drive Slot Sensor Specific 01 Drive Fault Degraded As and Trig HDD 3 Stat specific ODh 6Fh 02 Predictive Failure Degraded De Offset atus 07 Rebuild Remap in Degraded progress 9 128 Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT TPS Appendix C POST Code Diagnostic LED Decoder Appendix C POST Code Diagnostic LED Decoder During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server boa
51. the event the standard ME firmware update process fails Revision 1 0 107 Intel order number G13326 003 Jumper Blocks Intel amp Server Board S1200BT TPS 1 Power down and remove the AC power cord Open the server chassis For instructions see your server chassis documentation Move jumper from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 Close the server chassis Reconnect the AC cord and power up the server Perform the ME firmware update procedure as documented in the README TXT file that is included in the given ME firmware update package same package as BIOS Power down and remove the AC power cord Open the server chassis Move jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server 8 4 BIOS Recovery Jumper The following procedure boots the recovery BIOS and flashes the normal BIOS 1 Turn off the system power 2 Move the BIOS recovery jumper to the recovery state 3 Insert a bootable BIOS recovery media containing the new BIOS image files 4 Turn on the system power The BIOS POST screen will appear displaying the progress and the system will boot to the EFI shell The EFI shell then executes the Startup nsh batch file to start the flash update process The user should then switch off the power and return the recovery
52. to the manageability features that are supported on the previous generation of servers The following is a list of the more significant changes that are common to this generation servers 34 Sensor and SEL logging additions enhancements e g additional thermal monitoring capability better isolation of faults to the FRU level Embedded platform debug feature which allows capture of detailed data for later analysis by Intel engineering Provisioning and inventory enhancements o Signed Firmware improved security o Inventory data system information export partial SMBIOS table Enhancements to fan speed control DOMI 1 0 compliance Support for embedded web server UI in Basic Manageability feature set Enhancements to embedded web server Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Platform Management Human readable SEL Additional system configurability Additional system monitoring capability o Enhanced on line help Enhancements to redirection o Support for higher resolution Management support for PMBus rev1 2 compliant power supplies Integrated BMC firmware reliability enhancements o Redundant Integrated BMC boot blocks to avoid possibility of a corrupted boot block resulting in a scenario that prevents a user from updating the Integrated BMC 4 2 Basic and Optional Advanced Management Features This section explains the advanced management features suppor
53. x1 Optional Intel Remote Management Module 4 4 Lite only or Intel Remote Management Module 4 RMM4 TPM module connector TPM module connector Intel order number G13326 003 Slot4 One 5V PCI 32 bit 33 MHz connector Slot5 One PCI Express Gen2 x8 x4 throughput connector Slot6 One PCI Express Gen2 x8 x8 throughput connector Slot7 One PCI Express Gen2 x16 x8 throughput connector Silicon Motion SM712GX04LF02 BA Support for six Serial ATA hard drives through six onboard SATA connectors with SW RAID 0 1 5 and 10 Six 3Gb s SATA ports Embedded Server RAID Technology through onboard SATA connectors provides SATA RAID 0 1 and 10 and optional RAID 5 support provided by the Intel RAID Activation Key AXXRAKSW5 Intel Rapid Storage RAID through onboard SATA connectors provides SATA RAID 0 1 5 and 10 One Gigabit Ethernet device 82574L connect to PCI E x1 interfaces on the PCH One Gigabit Ethernet PHY 82579 connected to PCH through PCI E x1 interface Overview Intel amp Server Board 51200 TPS 2 2 Server Board Layout Figure 1 Intel Server Board S1200BTL Picture 4 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Overview ih 11 71 POPC PVT E PPP PP AS Figure 2 Intel Server Board S1200BTS Picture 2 2 1 Server Board Connector and Component Layout The following figure shows the board l
54. 0 Series highly integrated solution variant is composed of quad processor cores FC LGA 1155 socket package with 2 5 GT s Up to 95 W Thermal Design Power TDP processors with higher TDP are not supported 16 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Functional Architecture The server board does not support previous generations of the Intel Xeon processors The list of supported processors may be found at http serverconfigurator intel com Note The workstation processor is not supported in this platform 3 1 2 Intel Core Processor i3 2100 Series The Intel Core Processor i3 2100 Series highly integrated solution variant is composed of Duo cores FC LGA 1155 socket package with 2 5 GT s Up to 65 W Thermal Design Power TDP processors with higher TDP are not supported The server board does not support previous generations of the Intel Core Processor i3 Series The list of supported processors may be found at http serverconfigurator intel com 3 1 3 Intel Turbo Boost Technology Intel Turbo Boost Technology is featured on certain processors in the Intel Xeon Processor E3 1200 Series Intel Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency if the processor is operating below power temperature and current limits This results in increased performance for both multi threaded and sing
55. 0BTL 28 3 7 2 Video for Intel Server Board S1200BTS 29 3 8 Network Interface Controller NIC 29 3 8 1 Gigabit Ethernet Controller 82574L r 29 3 8 2 Gigabit Ethernet PHY 8259 itp e poet engines 29 3 8 3 MAC Address Definition ret recon tet resin ere iet EA 30 3 9 Intel Acceleration Technolgy 2 Intel 1 2 30 3 9 1 Direct Cache Access DCA Ep AE 30 3 10 Intel Virtualization Technology for Directed Intel 30 3 11 TPM Trusted Platform etin ed ke nri n 31 4 Platform Managetrient nie eee rrt 32 4 1 Feat re Support E DNE 33 4 1 1 IPMI 2 0 FealurBS ret RERO OP REX o 33 4 1 2 Non IPMI fL 33 4 1 3 New Manageability Features a a 34 4 2 Basic and Optional Advanced Management Features 35 4 2 1 Enabling Advanced Management 36 4 2 2 Keyboard Video and Mouse Redirection 36 4 2 3 Media Hedlreclion ne eer e e dete d 38 4 2 4 Embedded Web server sedi et alae db br e eh
56. 100 1000 NIC Connector Pin out Pin Signal Name Pin Signal Name 1 P5V USB PWR75 2 USB PCH 11 FB DN 3 USB PCH 11 FB DP 4 GND 5 P5V USB PWR75 6 USB PCH 10 FB DN 7 USB PCH 10 FB DP 8 GND 9 P1V9 LAN2 R 10 NIC2 MDIP 0 11 NIC2_MDIN lt 0 gt 12 NIC2_MDIP lt 1 gt 13 NIC2_MDIN lt 1 gt 14 NIC2_MDIP lt 2 gt 15 NIC2_MDIN lt 2 gt 16 NIC2_MDIP lt 3 gt 17 NIC2_MDIN lt 3 gt 18 GND 19 LED NIC2 1 20 P3V3 AUX 21 LED NIC2 LINK100 R O 22 LED NIC2 LINK1000 2 Intel order number G13326 003 Revision 1 0 Intel amp Server Board 51200 TPS Connector Header Locations and Pin outs Table 30 RJ 45 10 100 1000 NIC Connector Pin out J6A1 Pin Signal Name Pin Signal Name 1 P5V USB PWR75 2 USB PCH 11 FB DN 3 USB PCH 11 FB DP 4 GND 5 P5V USB PWR75 6 USB PCH 10 FB DN 7 USB PCH 10 FB DP 8 GND 9 P1V8 PHY VCT R 10 MDIP 0 11 NIC1 MDIN 0 12 NIC1_MDIP lt 1 gt 13 NIC1_MDIN lt 1 gt 14 NIC2_MDIP lt 2 gt 15 NIC1_MDIN lt 2 gt 16 NIC2_MDIP lt 3 gt 17 NIC1_MDIN lt 3 gt 18 GND 19 LED NIC1 LINK ACT 0 R 20 P3V3 AUX 21 LED NIC1 2 22 LED NIC1 LINK1000 1 7 5 3 The sever board provides up to two 6Gb s SATA connectors and four 3Gb s SATA connectors The pin configuration for each connector i
57. 1066 1333 MHz ECC Unbuffered UDIMM DDR3 Upto 2 UDIMMs per channel 32 GB max with x8 ECC UDIMM 2 Gb DRAM Support for Intel C204 Platform Controller Hub PCH chipset ServerEngines LLC Pilot BMC controller Integrated BMC External connections DB 15 video connectors DB 9 serial Port A connector Four ports on two USB LAN combo connectors at rear of board Internal connections Two USB 2x5 pin headers each supporting two USB 2 0 ports One 2x5 Serial Port B headers Two 6Gb s SATA ports and four 3Gb s SATA ports One SAS mezzanine slot for optional SAS module Intel order number G13326 003 Support for one Intel Xeon Processor E3 1200 Series or Intel Core Processor i3 2100 Series in FC LGA 1155 socket package 2 5 GT s point to point DMI interface to PCH LGA 1155 pin socket Two memory channels with support for 1066 1333 MHz ECC Unbuffered UDIMM DDR3 Upto 2 UDIMMs per channel 32 GB max with x8 ECC UDIMM 2 Gb DRAM Support for Intel C202 Platform Controller Hub PCH chipset External connections DB 15 video connectors DB 9 serial Port A connector Four ports on two USB LAN combo connectors at rear of board Internal connections Two USB 2x5 pin headers each supporting two USB 2 0 ports 2x5 Serial Port B headers Six 3Gb s SATA ports Revision 1 0 Intel amp Server Board 51200 5 Overview Description of S1200BTL Description of S1200B
58. 1200BT TPS BIOS User Interface Categories Top Tabs 2nd Level Screens 3rd Level Screens Security Screen Tab Server Management Screen Tab Console Redirection System Information With BMC Only BMC LAN Configuration v Non BNC Only Hardware Monitor v Non BNC Only Realtime Temperature and Voltage Status Boot Options Screen Tab Hard Disk Order CDROM Order Floppy Order Network Device Order BEV Device Order Add EFI Boot Option 8 Delete Boot Option Boot Manager Screen Tab Error Manager Screen Tab System Event Log Screen Tab Non BMC Only Exit Screen Tab Revision 1 0 Intel order number G13326 003 55 BIOS User Interface Intel amp Server Board 51200 TPS 6 5 2 2 Main Screen Tab The Main Screen is the first screen that appears when the BIOS Setup configuration utility is entered unless an error has occurred If an error has occurred the Error Manager Screen appears instead Advanced Security Server Management Boot Options Boot Manager Figure 15 Screen 56 Revision 1 0 Intel order number G13326 003 Intel Server Board 51200 TPS BIOS User Interface Screen Field Descriptions 1 Logged in as Option Values Administrator User Help Text None Comments Information only Displays password level tha
59. 326 003 BIOS User Interface Intel amp Server Board 51200 TPS Boot Options Hard Disk Order Hard Disk 1 Available Hard Disk devices Hard Disk Available Hard Disk devices Figure 35 Hard Disk Order Screen 6 5 2 20 CDROM Order The CDROM Order screen allows the user to control the order in which BIOS attempts to boot from the CDROM drives installed in the system This screen is only available when there is at least one CDROM device available in the system configuration Note A USB CDROM device will appear in this section To access this screen from the Main screen select Boot Options CDROM Order To move to another screen press the Esc key to return to the Boot Options screen then select the desired screen Boot Options CDROM Order CDROM 1 Available CDROM devices CDROM 2 Available CDROM devices Figure 36 CDROM Order Screen 6 5 2 21 Floppy Order The Floppy Order screen allows the user to control the order in which BIOS attempts to boot from the Floppy Disk drives installed in the system This screen is only available when there is at least one Floppy Disk diskette device available in the system configuration Note A USB Floppy drive or a USB Key device formatted as a diskette drive will appear in this section To access this screen from the Main screen select Boot Options gt Floppy Order To move to another screen press the Esc key to return to the Boot Options screen
60. 34 Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT TPS Appendix D POST Code Errors POST Error Beep Codes The following table lists POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users on error conditions The beep code is followed by a user visible code on POST Progress LEDs Table 60 POST Error Beep Codes 3 Memory error Multiple System halted because a fatal error related to the memory was detected The following Beep Codes are from the BMC and are controlled by the Firmware team They are listed here for socket is empty convenience 1 5 2 1 CPU socket population error DC power unexpectedly lost power good dropout Power unit sensors report power unit failure offset 1 5 4 2 Power fault 1 5 4 4 Power control fault Power good assertion timeout Power unit sensors report soft power control failure offset A 1 5 2 4 MSID Mismatch N A MSID mismatch occurs if a processor is installed into a system board that has incompatible power capabilities d Revision 1 0 135 Intel order number G13326 003 Appendix E Supported Intel amp Server Chassis Intel amp Server Board S1200BT TPS Appendix E Supported Intel Server Chassis The Intel Server Board S1200BT is supported in the following Intel server chassis 1 Intel Server Chassis PA304XXSFCN 2 Intel Server Chassis P4304XXSHCN 136 Revision 1 0 Inte
61. 6 IP Address Static Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Functional Architecture All users disabled 3 6 2 Optional 4 Advanced Management Board On the Intel Server Board S1200BTL provides RMM4 module Give the customer the option to add a dedicated management 100 Mbit LAN interface to the product Provide additional flash space enabling the Advanced Management functions to support WS MAN and CIMON Table 7 Optional RMM4 Advanced Management Board Features Feature Description KVM Redirection Remote console access via keyboard video and mouse redirection over LAN USB Media Redirection Remote USB media access over LAN WS MAN Full SMASH profiles for WS MAN based consoles 3 6 3 Serial Ports The server board provides two serial ports an external DB9 serial port connector and an internal DH 10 serial header The rear 9 Serial A port is a fully functional serial port that can support any standard serial device The Serial B port is an optional port accessed through a 9 pin internal DH 10 header J1B1 on S1200BTL J8A1 on S1200BTS You can use a standard DH 10 to DB9 cable to direct serial A port to the rear of a chassis The serial B interface follows the standard RS 232 pin out as defined in the following table Table 8 Serial B Header J1B2 on S1200BTL or J8A1 on S1200BTS Pin out Pin Signal
62. 8h 4h 2h 1h LSB 7 6 5 4 3 2 1 0 SEC Phase 0x01 X X X X X X X O First POST code after CPU reset 0x02 X X X X X X O X CPU Microcode load begin 0x03 X X X X X XO O Cache As RAM initialization begin 0x05 X X X X X O X O SEC Core at Power On Begin Revision 1 0 129 Intel order number G13326 003 Appendix C POST Code Diagnostic LED Decoder 130 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Diagnostic LED Decoder O On X Off Progress Code Upper Nibble Lower Nibble Description MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB 7 6 5 4 3 2 1 0 XXXX XOOX Early CPU initialization during Sec 0x06 Phase 0x07 X X X X X OOO Early South Bridge initialization 0x08 QUAS Early North Bridge initialization 0x09 X X X X O X X O End Of Sec Phase 0x0E X X X CPU Not Found CPU Microcode Not Loaded PEI Phase 0x10 X X X O X X X X PEI Core Starts 0 11 X X X O X X X O CPU PEI Module Starts 0x15 X X X O North Bridge Module Starts 0x19 X X X O O X X O South Bridge PEI Module Starts 0x31 X X O O X X X O Memory Installed 0x32 X XO O X X O X CPU PEI Module for CPU initialization 0x33 X XO O X XO O CPU PEI Module for Cache initialization X X O O X O X X CPU PEI Module for Boot Strap 0x34 Processor Select X X O O X O X O CPU PEI Module for Application 0x35
63. AG4 TDO B7 GND 2 RESERVED B32 GND A8 JTAG5 TMS B8 3 3V A33 RESERVED B33 HSOP 4 9 3 3V B9 JTAGI TRST A34 GND B34 HSON 4 A10 3 3 B10 3 3VAUX A35 HSIP 4 B35 GND 11 PERST B11 WAKE A36 HSIN 4 B36 GND 12 GND B12 RESERVED A37 GND B37 HSOP 5 A13 REFCLK B13 GND A38 GND B38 HSON 5 A14 REFCLK B14 HSOP 0 A39 HSIP 5 B39 GND A15 GND B15 HSON 0 40 HSIN 5 B40 16 HSIP 0 B16 GND A41 GND B41 6 17 HSIN 0 B17 2 42 GND B42 HSON 6 A18 GND B18 GND 43 HSIP 6 B43 GND 19 RESERVED B19 HSOP 1 44 HSIN 6 B44 GND A20 IGND B20 HSON 1 45 GND 45 HSOP 7 21 HSIP 1 B21 GND 46 GND B46 HSONI7 22 HSIN 1 B22 GND 47 HSIP 7 B47 GND A23 GND B23 HSOP 2 48 HSIN 7 B48 PRSNT2 24 24 HSON 2 49 GND B49 GND 25 HSIP 2 B25 GND Table 40 One PCI X32 connector J1B1 Pin Signal Pin Signal Pin Signal Pin Signal 1 12V A1 TRST B32 AD 17 A32 AD 16 B2 TCK A2 12V B33 C BE 2 A33 3 3V B3 Ground TMS B34 Ground A34 FRAME B4 TDO A4 TDI B35 IRDY A35 Ground B5 45V A5 5 B36 3 3V A36 TRDY B6 5V A6 INTA B37 DEVSEL A37 Ground B7 INTB A7 INTC B38 Ground A38 STOP B8 INTD A8 5V B39 LOCK A39 3 3V 9 PRSNT1 AQ RSVD B40 PERR A40 RSVD B10 RSVD 10 V IO B41 3 3V 41 RSVD B11 PRSNT2 11 RSVD B42 SERR A42 Ground B12 GND A12 GND B43 3 3V A43 PAR B13 GND A13 GND B44 C
64. B RI RI Ring indicate SPB EN N Enable Pin 5 7 10 5_ 6 7 SPB DTR Data terminal ready 8 9 10 98 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Connector Header Locations and Pin outs 7 5 6 USB Connector There are four external USB ports on two NIC USB combinations Section 5 5 2 details the pin out of the connector Two 2x5 connector on the server board J1D1 J1E1 provides an option to support an additional USB port each connector supporting two USB ports The following table defines the pin out of the connector One 2x5 connectors on the server board provides an option to support Smart module The Table 36 Internal USB Connector Pin out J1E1 J1D1 USB port 5 negative signal U USB ICH P4P CONN _ USB port 4 positive signal 6 USB ICH 5 CONN _ USB port 5 positive signal O 9 TP USB ICH NC Test point following table defines the pin out of the connector Table 37 Pin out of Internal USB Connector for low profile Smart module J3F2 Revision 1 0 sme USB Data USB port positive signal 6 NC AqNA 9 LED Activity LED Intel order number G13326 003 99 Connector Header Locations and Pin outs Intel amp Server Board 51200 TPS 7 6 PCI Express Slot PCI Slot Riser Card Slot A PCI E Riser card will enable a PCI E add on card to be accomm
65. Configuration screen allows the user to configure the thermal control behavior of the system in order to balance performance and acoustics with power consumption and heat generation 74 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 BIOS User Interface To access this screen from the Main screen select Advanced System Acoustic and Performance Configuration To move to another screen press the Esc key to return to the Advanced screen then select the desired screen Advanced System Acoustic and Performance Configuration Set Throttling Mode Auto CLTT OLTT Altitude 300m or less 301m 900m 901m 1500m Higher than 1500m Set Fan Profile Performance Acoustic Figure 23 System Acoustic and Performance Configuration 6 5 2 11 Security Screen Tab The Security screen allows the user to enable and set the user and administrative password and to lock out the front panel buttons so they cannot be used This screen also allows the user to enable and activate the Trusted Platform Module TPM security settings on those boards that support TPM To access this screen from the Main screen or other top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Security screen is selected Advanced Security Cl Ce II S Tee EO e Boot Manager Administrator Password Status User Password Status Set Administrator Passwo
66. Full Sensor Name Sensor Platform Sensor Type Event Reading Type Event Offset Triggers Contrib To System Assert De Readable Event Rearm Stand by Sensor name in SDR Applicability Status assert Data Value Offsets 2 Chassis Analog PS2 Fan Tach 1 specific 01 52 Fan Tach 2 specific 01h 9 Processor DIMM nc Degraded Aggregate Thermal Non fatal T Threshol c Margin Boh All Eo ibl i og u I and Analog R T P1 Thrm Mrgn Processor DIMM Temperature Digital Discrete Mem P1 Thrm Trip Baseboard 12V Voltage Threshold nc Degraded As and 12 0V i oth ul ene Non fatal Analog Baseboard 5 Voltage Threshold nc Degraded As and Baseboard 3 3V Voltage Threshold nc Degraded 3 3V Oth Non fatal Analog V D Threshold e ne egraded a and 02h Oth c Non fatal nc Degraded Voltage Threshold 02h c nc c Non fatal Stand by BB 5 0 STBY Baseboard 3 3V Auxiliary BB 3 3V AUX Baseboard 1 5V VDDQ BB 1 5V P1 MEM Baseboard CMOS Battery BB 3 3V Vbat Voltage Threshold nc Degraded Threshold u l Degraded 02h 01h c Non fatal 126 Revision 1 0 Intel order number G13326 003 Baseboard 1 2 Processor Vccp All edd 2 1 AS
67. ION u ui e Scu DRE CER Ced i 96 7 5 2 Rear NIC and USB connector 96 eed aite ead 97 TG ORAS CONMCCIONS aub gt 97 7 5 5 Serial Port c voa p noie v raat hub 98 7 5 6 WISE COMM 5 edo ot ipae tbv Pt ae ad b de RR 99 7 6 PCI Express Slot PCI Slot Riser Card 5 0 100 7 7 Eam Headers qr m n aso dated cente descen asd 103 8 Jumper 0 2 6 06 5223 54225285 55 eder mie bite 104 vi Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Table of Contents 8 1 CMOS Clear and Password Reset Usage Procedure 105 8 1 1 Clearing the CMOS ns tances 106 8 1 2 Clearing the Password 106 8 2 Integrated BMC Force Update Procedure Only for The Intel Server Board 2 200 1 525 107 8 3 ME Force Update Jumper pads 107 8 4 BIOS Recovery 108 9 Intel Light Guided Diagnostics eerte tnt ntn tnnt tnt 109 9 1 System Status LED Only for S1200BTL a
68. Intel Server Board S1200BTS 51 Supper I O 5 1 1 Key Features of supper I O W83627DHG P is from the Nuvoton s Super I O product line This family features the LPC Low Pin Count interface This interface is more economical than its ISA counterpart It has approximately forty pins less yet it provides as great performance In addition the improvement allows even more efficient operation of software BIOS and device drivers The W83627DHG P provides the following key features Meet LPC Spec 1 01 Integrated hardware monitor functions Support ACPI Advanced Configuration and Power Interface Support up to 2 16550 compatible UARTs ports 8042 based keyboard controller Smart Fan control system Five fan speed monitoring inputs Four fan speed controls GPIO Support 1 0 and 1 1a Specifications 46 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface 6 BIOS User Interface 6 1 BIOS POST Initialization 6 1 1 BIOS Revision Identification 6 1 1 1 BIOS ID String The BIOS Identification string is used to uniquely identify the revision of the BIOS being used on the server The BIOS ID string is displayed on the Power On Self Test POST diagnostic screen and in Setup and System Management BIOS SMBIOS structures The BIOS ID string is formatted as follows 6 1 1 2 BoardFamilyID OEMID MajorVer RelRev RelNum BuildDateTime Where BoardFami
69. ND A52 PERP8 NC B53 GND GND A53 PERN8 NC B54 PETP9 NC A54 GND GND B55 PETN9 NC A55 GND GND B56 GND GND A56 PERP9 NC B57 GND GND A57 PERN9 NC B58 PETP10 NC A58 GND GND 59 PETN10 A59 GND GND B60 GND GND A60 PERP10 NC B61 GND GND A61 PERN10 NC B62 PExP11 NC A62 GND GND B63 PETN11 NC A63 GND GND B64 GND GND A64 PERP11 NC B65 GND GND A65 PERN11 NC B66 PETP12 NC A66 GND GND B67 PETN12 NC A67 GND GND B68 GND GND A68 PERP12 NC B69 GND GND A69 PERN12 NC B70 PETP13 NC A70 GND GND B71 PETN13 NC A71 GND GND B72 GND GND A72 PERP13 NC B73 GND GND A73 PERN13 NC B74 PETP14 NC A74 GND GND B75 PETN14 NC A75 GND GND B76 GND GND A76 PERP14 NC B77 GND GND A77 PERN14 NC B78 PETP15 NC A78 GND GND B79 PETN15 NC A79 GND GND B80 GND GND A80 PERP15 NC B81 PRSNT2N NC A81 PERN15 NC B82 RSVD NC A82 GND GND Revision 1 0 101 Intel order number G13326 003 Connector Header Locations and Pin outs Intel amp Server Board 51200 TPS Table 39 Three PCI Express x8 connectors J2B2 J3B1 and J4B2 Pin Signal Pin Signal Pin Signal Pin Signal 1 PRSNT1 B1 12 26 2 26 GND 2 12 B2 12 27 GND B27 HSOP 3 12 B3 RESERVED A28 GND B28 HSON 3 A4 GND B4 GND A29 HSIP 3 B29 GND 5 JTAG2 TCk B5 SMCLK A30 HSIN 3 B30 RESERVED JTAGS TDI B6 SMDAT A31 GND B31 2 7 JT
70. Name Serial Port B Header Pin out 1 DCD 2 DSR 1 3 RX OO 4 RTS 5 TX s 0 6 6 CTS 7 2 7 DTR 9 5 O 8 RI 9 GND 3 6 4 Floppy Disk Controller The server board does not support a floppy disk controller interface However the system BIOS recognizes USB floppy devices Revision 1 0 27 Intel order number G13326 003 Functional Architecture Intel amp Server Board 51200 TPS 3 6 5 Keyboard and Mouse Support The server board does not support PS 2 interface keyboards and mouse However the system BIOS recognizes USB specification compliant keyboard and mouse 3 6 6 Wake up Control The super I O contains functionality that allows various events to power on and power off the system 3 7 Video Support 3 7 1 Intel Server Board S1200BTL The server board includes on board Server Engine LLC Pilot Controller with 128 MB DDR3 memory in which 8MB is usable accessible memory for iBMC video graphic display functions The graphic controller internally has access to larger memory for the internal operations The 32MB memory reported by display driver is the attached memory Attached memory can be 32MB or greater but only 8 is accessible for display functions 3 7 1 1 Video Modes The integrated video controller supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD Table 9 Video Modes 2D Mode Refresh rate 8bpp 16bpp 32bpp 640 x 480 60 70 72 75 support
71. Server Board 51200 TPS 6 5 2 14 System Information The System Information screen allows the user to view part numbers serial numbers and firmware revisions To access this screen from the Main screen select Server Management gt System Information To move to another screen press the Esc key to return to the Server Management screen then select the desired screen Figure 28 System Information Screen S1200BTL 78 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface Figure 29 System Information Screen S1200BTS 6 5 2 15 BMC LAN Configuration The BMC configuration screen allows the Setup user to configure the BMC Baseboard LAN channel and the RMM4 LAN channel and to manage BMC User settings for up to five BMC Users To access this screen from the Main screen select Server Management gt System Information To move to another screen press the lt Esc gt key to return to the Server Management screen then select the desired screen Revision 1 0 79 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS Server Management BMC LAN Configuration Baseboard LAN configuration IP Source Static Dynamic IP Address Subnet Mask Gateway IP Intel RMM4 LAN configuration Intel 4 Not Pre IP Source Static Dynamic IP Address Gateway IP BMC DHCP Host Name User Configuration User ID an
72. TS Add in PCI Card PCI Express Card Onboard Hard Drive RAID Support Server Management Revision 1 0 51011 One PCI 32 bit 33 MHz connector Slot3 One PCI Express Gen2 x8 x4 throughput connector Slot4 One PCI Express Gen2 x8 x4 throughput connector Slot5 One PCI Express Gen2 x8 x4 throughput connector Slot6 One PCI Express Gen2 x16 x8 throughput connector Onboard ServerEngines LLC Pilot III BMC Controller External 32MB or above DDR3 800MHz memory Support for six Serial ATA II hard drives through six onboard SATA connectors with SW RAID 0 1 5 and 10 Up to four SAS hard drives through optional Intel SAS Entry RAID Module card Two 6Gb s SATA ports and four 3Gb s SATA ports Intel Embedded Server RAID Technology II through onboard SATA connectors provides SATA RAID 0 1 and 10 and optional RAID 5 support provided by the Intel RAID Activation Key AXXRAKSW5 Intel Rapid Storage RAID through onboard SATA connectors provides SATA RAID 0 1 5 and 10 One optional internal SAS module connector which supports AXXRMS2AF040 AXXRMS2LL040 and AXX4SASMOD One Gigabit Ethernet device 82574L connect to PCI E x1 interfaces on the PCH One Gigabit Ethernet PHY 82579 connected to PCH through PCI E x1 interface Onboard LLC Pilot Controller Integrated Baseboard Management Controller Integrated BMC IPMI 2 0 compliant Integrated 2D video controller on PCI E
73. a single processor display Romley boards have for the second processor if not installed 6 Processor Version Revision 1 0 63 Intel order number G13326 003 BIOS User Interface Intel Server Board 51200 TPS 64 10 Option Values ID string from processor Help Text None Comments Information only Displays Brand ID string read from processor with CPUID instruction Intel Turbo Boost Technology Option Values Enabled Disabled Help Text Intel Turbo Boost Technology allows the processor to automatically increase its frequency if it is running below power temperature and current specifications Comments This option is only visible if all processors installed in the system support Intel Turbo Boost Technology In order for this option to be available Enhanced Intel SpeedStep Technology must be Enabled Enhanced Intel SpeedStep Tech Option Values Enabled Disabled Help Text Enhanced Intel SpeedStep Technology allows the system to dynamically adjust processor voltage and core frequency which can result in decreased average power consumption and decreased average heat production Contact your OS vendor regarding OS support of this feature Comments When Disabled the processor setting reverts to running at Max TDP Core Frequency rated frequency This option is only visible if all processors installed in the system support Enhanced Intel SpeedStep Technology In order for the I
74. able 27 System Status LED Indicator States Solid on System booted and ready Green 1 Hz blink Degraded System degraded Non critical temperature threshold asserted Non critical voltage threshold asserted Non critical fan threshold asserted Fan redundancy lost sufficient system cooling maintained This does not apply to non redundant systems Power supply predictive failure Power supply redundancy lost This does not apply to non redundant systems Correctable errors over a threshold of 10 and migrating to a spare DIMM memory sparing This indicates the user no longer has spared DIMMs indicating a redundancy lost condition Corresponding DIMM LED should light up 4 Amber 1 Hzblink Non critical Non fatal alarm system is likely to fail CATERR asserted Critical temperature threshold asserted Critical voltage threshold asserted Critical fan threshold asserted VRD hot asserted SMI Timeout asserted Amber Solid on Critical non Fatal alarm system has failed or shutdown recoverable Thermtrip asserted Non recoverable temperature threshold asserted Non recoverable voltage threshold asserted Power fault Power Control Failure Fan redundancy lost insufficient system cooling This does not apply to non redundant systems Off N A Not ready AC power off if no degraded non critical critical or non recoverable conditions exist Notes 1 The BIOS detects these conditions and sends a Set Fault Indication com
75. ace 6 5 2 29 Exit Screen Tab The Exit screen allows the user to choose whether to save or discard the configuration changes made on other Setup screens It also allows the user to restore the BIOS settings to the factory defaults or to save or restore them to a set of user defined default values If Load Default Values is selected the factory default settings noted in bold in the tables in this chapter are applied If Load User Default Values is selected the system is restored to previously saved user defined default values To access this screen from the Main screen or other top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Exit screen is selected Error Manager Save Changes and Exit Discard Changes and Exit Save Changes Discard Changes Load Default Values Save as User Default Values Load User Default Values Figure 45 Exit Screen Revision 1 0 89 Intel order number G13326 003 Connector Header Locations and Pin outs Intel amp Server Board 51200 TPS T Connector Header Locations and Pin outs 7 1 Board Connector Information The following section provides detailed information regarding all connectors headers and jumpers on the server board It lists all connector types available on the board and the corresponding reference designators printed on the silkscreen Table 17 Board Connector Matrix on S1200BTL Quantity Reference Desig
76. and P1 Vccp POR ala ass Intel amp Server Board S1200BT TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Type Event Offset Triggers Contrib To System Assert De Readable Event Rearm Stand by Sensor name in SDR Applicability Status assert Data Value Offsets Baseboard Vol Threshold nc Degraded Processor Vcc s u l cnc De BB P1 Vcc I Baseboard Vol Threshold nc Degraded Processor VccUSA Don u l c nc De BB P1 VccUSA Baseboard 1 05V Voltage Threshold nc Degraded PCH 02h 01h c nc Non fatal De 1 05 1 1 05V Voltage Threshold nc Degraded Auxiliary 02h Oth u l e nc Non fatal De BB 1 05V AUX Eee Baseboard 1 35V nc Degraded VDDQ Voltage Threshold c Non fatal u l c nc 2 1 35 P1 02h Oth u1 De MEM Analog Analog Analog Analog Baseboard 12 0V Voltage Threshold nc Degraded 02h Oth e ne c Non fatal De 12 0V V1 M Baseboard 1 5V Valisge Threshold nc Degraded Auxiliar y 02h 01h 14 1 c nc Non fatal pe BB 1 5V AUX 00 Drive Presence OK 01 Drive Fault Degraded Drive 0 Chassis Drive Slot Sensor Specific 02 Predictive Degraded specific ODh 6Fh 07 Rebuild Remap in De Hard Disk Drive 1 00 Drive Presence OK S Chassis Drive Slot Sensor Specific tatus Specific
77. annel Dual Channel Symmetric Asymmetric Symmetric 3 DIMMs A1 B1 B2 Intel Flex Memory Dual Channel Dual Channel Dual Channel Symmetric Symmetric Asymmetric 4 DIMMs A1 A2 B1 B2 Dual Channel Symmetric Dual Channel Dual Channel Dual Channel Dual Channel Symmetric Symmetric Symmetric Symmetric 3 2 3 2 DIMM Configuration rules Table 5 UDIMM memory configuration rule DIMM slots per channel DIMMs populated per channel Speed Ranks per channel 2 1 1066 1333 Single Rank Dual Rank 2 2 1066 1333 Single Rank Dual Rank To get the maximum memory size on UDIMM you get the detailed information from following table Table 6 UDIMM Maximum configuration Max Memory Possible 1Gb DRAM Technology 2Gb DRAM Technology 4Gb DRAM Technology Single Rank UDIMM 4GB 8GB 16GB 4x 1GB DIMMs 4x 2GB DIMMs 4x 4GB DIMMs Dual Rank UDIMMs 8GB 16GB 32GB 20 Intel order number G13326 003 Revision 1 0 Intel amp Server Board 51200 TPS Functional Architecture Max Memory Possible 1Gb DRAM Technology 2Gb DRAM Technology 4Gb DRAM Technology 4x 2GB DIMMs 4x 4GB DIMMs 4 DIMMs 3 2 4 Publishing System Memory For 51200 Server Boards with an SNB DT processor the memory configurations and population rules are relatively simple The overall configuration is a single processor IMC with two channels and two DIMM slots on each channel All memory DIMMs
78. ayout of the server board Each connector and major component is identified by a number or letter and Table 2 provides the description Revision 1 0 5 Intel order number G13326 003 Overview Intel amp Server Board 51200 TPS K L M AA N BB as Z YXW V U T S R AF003509 Figure 3 Intel Server Board S1200BTL Layout Table 2 Major Board Components Description Description A Slot 1 32 Mbit 33 MHz PCI R System FAN2 and System FAN3 Connector B TPM S CPU connector C Slot 3 4 PCI Express Gen2 x4 x8 connector T CPU Fan connector D Slot 5 PCI Express Gen2 4 x8 connector U USB connector for smart module E Slot 6 PCI Express Gen2 x8 x16 connector V SAS Module connector F Chassis Intrusion IPMB G SATA KEY X SYS FAN 1 H Two Ethernet and Dual USB COMBO Y HSBP Video port 7 SATA SGPIO J External Serial port AA Internal Serial Connector K RMM4 Lite Connector BB Front Panel Connector Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Overview Description Description L CPU Power Connector CC HDDLED 5 5 FAN 4 DD Internal USB Connector N 4 Dedicated NIC connector EE CMOS battery O Four DIMM Slots FF Four 3Gb s SATA ports P P S AUX GG Tw
79. bles Intel Server Board S1200BTL implements the below sensors Sensor Type Codes Sensor table given below lists the sensor identification numbers and information regarding the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose Refer to the ntelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information 120 Sensor Type The sensor type references the values in the Sensor Type Codes table in the Intelligent Platform Management Interface Specification Second Generation v2 0 It provides a context to interpret the sensor Event Reading Type The event reading type references values from the Event Reading Type Code Ranges and the Generic Event Reading Type Code tables in the Intelligent Platform Management Interface Specification Second Generation v2 0 Digital sensors are specific type of discrete sensors that only have two states Event Thresholds Triggers The following event thresholds are supported for threshold type sensors u nr c nc upper non recoverable upper critical upper non critical lower non recoverable lower critical lower non critical uc Ic upper critical lower critical Event triggers are supported event generating offsets for discrete type sensors The offsets can be found in the Generic Event Reading Type Code or Sensor Type Code tables in the ntelligent Plattorm Managem
80. c Sensor Type Temperature 01h Temperature 01h Other Units OBh Other Units OBh Current 03h Event Reading Type Threshold 01h Threshold 01h Threshold 01h Sensor Specific 6Fh Sensor Specific 6Fh Threshold 01h Threshold 01h Threshold 01h Event Offset Triggers 0 1 c nc 0 1 c nc I c nc 06 Configuration error 06 Configuration error u c nc u c nc u c nc Intel order number G13326 003 Contrib To System Status nc Degraded Non fatal Degraded Non fatal Degraded Non fatal2 OK Degraded Degraded Degraded OK OK Degraded Degraded Degraded OK nc Degraded Non fatal Degraded Non fatal Degraded Non fatal Assert De assert De De Readable Value Offsets Event Data Offset Offset OPCE TS LL ISI 20 4 Rearm Stand by Revision 1 0 Intel amp Server Board 51200 5 Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor name in SDR Applicability Chassis specific 5 Chassis specific 5 Power Supply 2 12V 95 of Maximum Current Output PS2 Curr Out 95 Power Supply 1 Temperature PS1 Temperature Power Supply 2 Temperature PS2 Temperature Processor Status P1 Status Processor Thermal Margin P1 Therm Margin 9h h o Chassis h
81. cache line resides in DIMM 1 the second in DIMM B1 and so on This allows Adjacent Cache Line Prefetch to fetch cache lines from both channels simultaneously approximately doubling the potential memory bandwidth o When both channels are populated but with different numbers of DIMMs Intel Flex Memory Technology divides the installed memory into two zones using interleaved Dual Channel Symmetric mode as far as the highest address on the less populated channel then using uninterleaved Dual Channel Asymmetric mode for the remaining memory on the more populated channel maximum total installed memory size supported is 32 GB using four 8 GB DIMMs Revision 1 0 19 Intel order number G13326 003 Functional Architecture Intel amp Server Board 51200 TPS The maximum memory bandwidth is 10 6 GB s in Single Channel mode or 21 GB s in Dual Channel Symmetric mode assuming DDR3 running at 1333 MT s 3 2 3 1 Memory Configuration Table Table 4 Memory Configuration Table Single Channel Configuration DIMM A1 DIMM A2 DIMM B1 DIMM B2 1 DIMM A1 only Single Channel Single Channel 1 DIMM B1 only Single Channel 2 DIMMs Single Channel A1 A2 Single Channel Single Channel 2 DIMMs Single Channel B1 Single Channel B2 Single Channel 2 DIMMs A1 B1 Dual Channel Symmetric Dual Channel Dual Channel Symmetric Symmetric 3 DIMMs A1 A2 B1 Intel Flex Memory Dual Channel Dual Ch
82. cessing tasks from the main ARM core 25 Intel order number G13326 003 Functional Architecture Intel amp Server Board 51200 TPS 3 6 1 USB External SPI Interface Interface to amp NAND for Host Interface ARM code EXtBUS amp M JTAG NAND amp Interface M SPI Flash Vectored Interrupt Controller Fan Tech 16 PWM 8 ADC 16 ARM926EJ S 16K D amp 16K I Cache 400MHz SD MMC GPIO KCS BT System amp amp Wakeup SGPIO Mailboxes Control Watchdog Timer SPI Memory ia PCI press Interface to Host LPC to SPI Flash Bridge System BIOS Super 1 0 Subsystem Graphics Subsystem Figure 13 Integrated BMC Hardware Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 1000M network interfaces Interface 1 This interface is available from either of the available NIC ports in system that can be shared with the host Only one NIC may be enabled for management traffic at any time To change the NIC enabled for management traffic please use the Write LAN Channel Port OEM IPMI command The default active interface is port 1 NIC1 Interface 2 This interface is available from the optional RMM4 which is a dedicated management NIC that is not shared with the host For these channels support can be enabled for IPMI over LAN and For security reasons embedded LAN channels have the following default settings 2
83. cient state 05 Non redundant Fatal insufficient resources 06 Redundant Degraded degraded from fully redundant state 07 Redundant Degraded Transition from non 00 Timer expired status only 01 Hard reset redundant state Intel order number G13326 003 Assert De Readable Value Offsets Event Data Trig Offset Trig Offset A A Rearm Stand by Revision 1 0 Intel amp Server Board 51200 5 Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Type Sensor name in SDR Applicability Chassis Intrusion is chassis specific Physical Security 05h Sensor Specific 6Fh Physical Security Physical Scrty Critical Interrupt 13h FP Interrupt E Specific FP NMI Diag Int Chassis specific Event Offset Triggers Contrib To System Assert De Readable Event Rearm Stand by Status assert Data Value Offsets 02 Powerdown Power down 03 08 Timer 08 Timer interrupt 00 intrusion As and Trig LAN leash lost De Offset 00 Front panel tig Offset diagnostic interrupt SMI Timeout Timeout Digital Discrete 01 State asserted Fatal As and Trig SMI Timeout 03h De Offset Logging Disabled System Event Log Sensor Specific System Event Log u System Event Sensor Specific System Event Button Sensor s Switc Speci
84. d except Date and Time the systems requires a save and reboot to take place in order for the changes to take effect Alternatively pressing lt ESC gt discards the changes and resumes POST to continue to boot the system according to the boot order set from the last boot 6 5 2 1 Map of Screens and Functionality There are a number of screens in the entire Setup collection They are organized into major categories Each category has a hierarchy beginning with a top level screen from which lower level screens may be selected Each top level screen appears as a tab arranged across the top of the Setup screen image of all top level screens There are more categories than will fit across the top of the screen so at any given time there will be some categories which will not appear until the user has scrolled across the tabs which are present The categories and the screens included in each category are listed below with links to each of the screens named Table 16 Screen Map Categories Top Tabs 2nd Level Screens 3rd Level Screens Main Screen Tab Advanced Screen Tab E 5 Processor Configuration Memory Configuration Mass Storage Controller Configuration Serial Port Configuration 5 USB Configuration PCI Configuration System Acoustic and Performance Configuration 54 Revision 1 0 Intel order number G13326 003 Intel Server Board S
85. d view current power state Virtual front panel display and overall system health Provides embedded firmware version information Configuration of various IPMI parameters LAN parameters users passwords etc Configuration of alerting SNMP and SMTP Display system asset information for the product board and chassis Display of BMC owned sensors name status current reading enabled thresholds including color code status of sensors Automatic refresh of sensor data with a configurable refresh rate On line help Display clear SEL display is in easily understandable human readable format Supports major industry standard browsers Internet Explorer and Mozilla Firefox Automatically logs out after user configurable inactivity period GUI session automatically times out after a user configurable inactivity period By default this inactivity period is 30 minutes Embedded Platform Debug feature Allow the user to initiate a diagnostic dump to a file that can be sent to Intel for debug purposes Display of power statistics current average minimum and maximum consumed by the server 4 2 5 Embedded Platform Debug The Embedded Platform Debug feature supports capturing low level diagnostic data applicable MSRs PCI config space registers etc This feature allows a user to export this data into a file that is retrievable via the embedded web GUI as well as through host and remo
86. der number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS Error Manager ERROR CODE SEVERITY INSTANCE Figure 43 Error Manager Screen 6 5 2 28 System Event Log Screen Tab The System Event Log screen appears only for server boards other than Compute Module boards which do not have an onboard Baseboard Management Controller These boards maintain the System Event Log internally by using the SMBIOS Type 15 mechanism The System Event Log viewer can display as many log records as are stored in a single page Each Event Record is displayed on one line The most recent Event Record is displayed on the top When there are more Event Records that can be displayed at once the lt PageUp gt and lt PageDown gt keys be used There is also a scroll bar to allow users to view the logs from beginning to the end Note When the System Event Log is full or when the user wishes to remove the current Event Records the user can choose Clear System Event Log in Setup System Event Log Event Info Time M BIT MEM ECC Error CPUO Ch 0 10 15 09 15 12 23 S BIT MEM ECC Error CPUO Ch 0 DimmO 10 15 09 15 11 25 UNCOR ERR 0 Dev 1C 0 10 15 09 15 08 36 MEM Parity Error CPUO Ch 0 10 15 09 15 07 11 Thermal Trip Occurred 10 15 09 15 05 05 Figure 44 System Event Log Screen S1200BTS 88 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interf
87. dog timer failed on last boot Major 8198 OS boot watchdog timer failure Major 8300 Baseboard management controller failed self test Major 8305 Hot Swap Controller failure Major 83A0 Management Engine ME failed Selftest Major 83A1 Management Engine ME Failed to respond Major 84F2 Baseboard management controller failed to respond Major 84F3 Baseboard management controller in update mode Major 84F4 Sensor data record empty Major 84FF System event log full Minor 8500 Memory component could not be configured in the selected RAS mode Major 8501 DIMM Population Error Major 8520 DIMM failed test initialization Major 8521 DIMM 2 failed test initialization Major 8523 DIMM B1 failed test initialization Major 8524 DIMM B2 failed test initialization Major 8540 DIMM 1 disabled Major 8541 DIMM A2 disabled Major 8543 DIMM B1 disabled Major 8544 DIMM B2 disabled Major 9667 PEI module component encountered an illegal software state error Fatal 9687 PEI module component encountered an illegal software state error Fatal 96A7 PEI module component encountered an illegal software state error Fatal A000 TPM device not detected Minor A001 TPM device missing or not responding Minor A002 TPM device failure Minor A003 TPM device failed self test Minor A100 BIOS Error Major A421 PCI component encountered a SERR error Fatal A5A0 PCI Express component encountered a PERR error Minor 1 PCI Express component encountered SERR error Fatal 1
88. e These lists follow the following guidelines The text heading for each Field Description is the actual text as displayed on the BIOS Setup screen This screen text is a hyperlink to it s corresponding Field Description text shown in the Option Values and Help Text entries in each Field Description are the actual text and values are displayed on the BIOS Setup screens Inthe Option Values entries the text for default values is shown with an underline These values do not appear underline on the BIOS Setup screen The underlined text in this document is to serve as a reference to which value is the default value The Help Text entry is the actual text which appears on the screen to accompany the item when the item is the one in focus active on the screen The Comments entry provides additional information where it may be helpful This information does not appear on the BIOS Setup screens Information enclosed in angular brackets lt gt in the screen shots identifies text that can vary depending on the option s installed For example Amount of memory installed is replaced by the actual value for Total Memory Revision 1 0 53 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS Information enclosed in square brackets in the tables identifies areas where the user must type in text instead of selecting from a provided option Whenever information is change
89. e DCMI DOMI is an IPMI based standard that builds upon a set of required IPMI standard commands by adding a set of DCMI specific IPMI OEM commands BTP1200 LC platform will support DCMI 1 0 specification 4 2 7 Local Directory Authentication Protocol LDAP The Lightweight Directory Access Protocol LDAP is an application protocol supported by the Integrated BMC for the purpose of authentication and authorization The Integrated BMC user connects with an LDAP server for login authentication This is only supported for non IPMI logins including the embedded web UI and SM CLP IPMI users passwords and sessions are not supported over LDAP LDAP can be configured IP address of LDAP server port etc via the Integrated BMC s Embedded Web UI LDAP authentication and authorization is supported over the any NIC configured for system management The BMC uses a standard Open LDAP implementation for Linux 4 3 Thermal Control 4 3 1 Memory Thermal Throttling The system shall support thermal management through open loop throttling OLTT or static closed loop throttling CLTT of system memory based on availability of valid temperature Revision 1 0 41 Intel order number G13326 003 Platform Management Intel Server Board 51200 TPS sensors on the installed memory DIMMs The Integrated Memory Controller IMC dynamically changes throttling levels to cap throttling based on memory and system thermal conditions as determined by the system a
90. e if all processors installed in the system support Intel VT The software configuration installed on the system must support this feature in order for it to be enabled 16 Intel VT for Directed Option Values Enabled Disabled Help Text Enable Disable Intel Virtualization Technology for Directed I O Intel VT d Report the I O device assignment to VMM through DMAR ACPI Tables Comments This option is only visible if all processors installed in the system support Intel VT d The software configuration installed on the system must support this feature in order for it to be enabled 17 Interrupt Remapping Option Values Enabled Disabled Help Text Enable Disable Intel VT d Interrupt Remapping support Comments This option only appears when Intel Virtualization Technology for Directed 1 is Enabled 18 ATS Support Option Values Enabled Disabled Help Text Enable Disable Intel VT d Address Translation Services ATS support Comments This option only appears when Intel Virtualization Technology for Directed 1 is Enabled Appears only on Romley boards 19 Pass through DMA Support Option Values Enabled Disabled Help Text Enable Disable Intel VT d Pass through DMA support Comments This option only appears when Intel Virtualization Technology for Directed I O is Enabled 20 Hardware Prefetcher Option Values Enabled Disabled Help Text Hardware Prefetcher is a speculative prefetch uni
91. e interface function D31 F0 contains other functional units including DMA interrupt controllers timers power management system management GPIO and RTC 3 4 5 USB 2 0 Support On the Intel C200 series PCH Chipset the USB controller functionality is provided by the dual EHCI controllers with an interface for up to ten USB 2 0 ports All ports are high speed full speed and low speed capable Four external connectors are located on the back edge of the server board wo internal 2x5 headers J1E1 and 4101 are provided each supporting two optional USB 2 0 ports port on internal smart module connector J1J2 on Intel Server Board S1200BTL 3 4 5 1 Native USB Support During the power on self test POST the BIOS initializes and configures the USB subsystem The BIOS is capable of initializing and using the following types of USB devices Revision 1 0 23 Intel order number G13326 003 Functional Architecture Intel Server Board 51200 TPS USB Specification compliant keyboards USB Specification compliant mouse USB Specification compliant storage devices that utilize bulk only transport mechanism USB devices are scanned to determine if they are required for booting The BIOS supports USB 2 0 mode of operation and as such supports USB 1 1 and USB 2 0 compliant devices and host controllers During the pre boot phase the BIOS automatically supports the hot addition and hot removal of USB devices a
92. ears grayed out Table 15 BIOS Setup Keyboard Command Bar Enter Execute The lt Enter gt key is used to activate submenus when the selected feature is a Command submenu or to display a pick list if a selected option has a value field or to select a subfield for multi valued features like time and date If a pick list is displayed the lt Enter gt key selects the currently highlighted item undoes the pick list and returns the focus to the parent menu lt Esc gt Exit The lt Esc gt key provides a mechanism for backing out of any field When the lt Esc gt key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the lt Esc gt key is pressed in any submenu the parent menu is re entered When the lt Esc gt key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded If is selected and the lt Enter gt key is pressed or if the lt Esc gt key is pressed the user is returned to where they were before lt Esc gt was pressed without affecting any existing settings If Yes is selected and the lt Enter gt key is pressed the setup is exited and the BIOS returns to the main System Options Menu screen T Select Item The up arrow is used to select the previous value in a pick list or the previous option in a menu item s option list The selected item must then be activated by pressing the Ente
93. ecomes the primary video device 3 7 2 Video for Intel Server Board S1200BTS 5 712 is a video chip from Silicon Motion Inc SMI It is one in SMI s LynxEM family It is PCI 2 1 compliant with the standard PCI 33MHz amp 66 MHz PCI Master Slave interface 33 MHz amp 66 MHz PCI Master Slave interface PCI 2 1 compliant Memory control is provided for the 4MB internal memory Support 640x480 800x600 1024x768 resolution and up to 85Hz Dual Video mode is supported 3 8 Network Interface Controller NIC The Intel Server Board S1200BT supports two network interfaces One is provided from the onboard Intel 82574L GbE PCI Express network controller the other is the onboard Intel 82579 Gigabit Network controller 3 8 1 Gigabit Ethernet Controller 82574L The 82574 family 82574L and 825741 are single compact low power components that offer a fully integrated Gigabit Ethernet Media Access Control MAC and Physical Layer PHY port The 82574 uses the PCI Express architecture and provides a single port implementation in a relatively small area so it can be used for server and client configurations as a LAN on Motherboard LOM design External interfaces provided on the 82574 PCle Rev 2 0 2 5 GHz x1 Copper standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASETX and 10BASE T applications 802 3 802 3u and 802 3ab NC SI or SMBus connection to a Manageability Controller MC
94. ed Ea terim 18 3 2 3 Memory Map and Population 19 3 2 4 Publishing System Moemlory ire eg re e gc b ee ea tpe exa 21 3 225 Memory RAS Suppor e teet Hd 21 3 3 21 3 4 VO tona 22 3 4 1 Digital Media Interface 22 3 4 2 POL Express Interlace 22 3 4 9 Serial ATA 22 3 4 4 Low Pin Count LPC Interface Eit 23 3 4 5 USB 2 0 23 3 5 Optional Intel SAS RAID Module 2 24 3 6 Integrated Baseboard Management 24 3 6 1 Integrated BMC Embedded LAN Channel sme 26 3 6 2 Optional RMM4 Advanced Management 27 6 SeriakPoriS 27 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Table of Contents 3 6 4 Floppy Disk Controller oco eo oU toto 27 3 6 5 Keyboard and Mouse Suppolt teen res e e ERE ELA Rena En 28 36 6 vWakesup ee ec pere 28 3 7 VIGGO SUpPPOT rr M 28 3 7 1 Intel Server Board S120
95. ed Supported Supported 85 90 100 200 800 x 600 60 70 72 75 Supported Supported Supported 85 90 100 120 160 1024 x 768 60 70 72 75 Supported Supported Supported 85 90 100 1152x852 43 47 60 70 Supported Supported Supported 75 80 85 1280 x 60 70 74 75 Supported Supported Supported 1024 1600 x Supported Supported Supported 1200 3 7 1 2 Dual Video The BIOS supports both single video and dual video modes The dual video mode is disabled by default In the single mode dual monitor video disabled the on board video controller is disabled when an add in video card is detected In single mode the onboard video controller is disabled when an add in video card is detected 28 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 5 Functional Architecture n dual mode the onboard video controller is enabled and is the primary video device The external video card is allocated resources and is considered the secondary video device When KVM is enabled in iBMC FW dual video is enabled Table 10 Dual Video Modes Enabled Onboard video controller Onboard Video Disabled Warning System video is completely disabled if this option is disabled and an add in video adapter is not installed Enabled If enabled both the onboard video controller Dual Monitor Video Disabled and an add in video adapter are enabled for system video The onboard video controller b
96. ent Interface Specification Second Generation v2 0 depending on whether the sensor event reading type is generic or a sensor specific response Assertion Deassertion Assertion and de assertion indicators reveal the type of events this sensor generates As Assertion De De assertion Readable Value Offsets Readable value indicates the type of value returned for threshold and other non discrete type sensors Readable offsets indicate the offsets for discrete sensors that are readable by means of the Get Sensor Heading command Unless otherwise indicated event triggers are readable Readable offsets consist of the reading type offsets that do not generate events Event Data Event data is the data that is included in an event message generated by the associated sensor For threshold based sensors these abbreviations are used R Reading value Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT TPS Appendix B Integrated BMC Sensor Tables T Threshold value Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states Rearming the sensors can be done manually or automatically This column indicates the type supported by the sensor The following abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm I Rearm by init agent Default Hysteresis The hysteresis setting applies t
97. er Blocks Intel amp Server Board S1200BT TPS features has changed from previous generation Intel server boards The following procedure outlines the new usage model 8 1 1 Clearing the CMOS To clear the CMOS perform the following steps 1 Power down the server Do not unplug the power cord 2 Open the server chassis For instructions see your server chassis documentation Move jumper from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 Wait five seconds Remove AC power Move the jumper back to the default position covering pins 1 and 2 Close the server chassis Power up the server The CMOS is now cleared and can be reset by going into the BIOS setup Note Removing AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down after the procedure is followed and AC power is re applied If this happens remove the AC power cord again wait 30 seconds and re install the AC power cord Power up the system and proceed to the F2 BIOS Setup utility to reset the preferred settings 8 1 2 Clearing the Password To clear the password perform the following steps 1 Power down the server Do not unplug the power cord 2 Open the chassis For instructions see your server chassis documentation Move jumper from the default operating position covering pins 1 and 2 to the password clea
98. ffecting any existing field values 52 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 5 BIOS User Interface lt 10 gt Save and Exit Pressing the lt F10 gt key causes the following message to display Save configuration and reset Yes No If Yes is highlighted and Enter is pressed all changes are saved and the Setup is exited If No is highlighted and Enter is pressed or the Esc key is pressed the user is returned to where they were before 10 was pressed without affecting any existing values 6 5 1 4 Setup Screen Menu Selection Bar The Setup Screen Menu selection bar is located at the top of the BIOS Setup Utility screen It displays tabs showing the major screen selections available to the user By using the left and right arrow keys the user can select the listed screens Some screen selections are out of the visible menu space and become available by scrolling to the left or right of the current selections displayed 6 5 2 BIOS Setup Utility Screens The following sections describe the screens available in the BIOS Setup utility for the configuration of the server platform For each of these screens there is an image of the screen with a list of Field Descriptions which describe the contents of each item on the screen Each item on the screen is hyperlinked to the relevant Field Description Each Field Description is hyperlinked back to the screen imag
99. fic 00 Power Button Button 4h 02 Reset Button Offset T D I Di ae perature s 5089 01 01 State Asserted mmm Threshold ul c nc nc Degraded 01h oes Non fatal Threshold u I cnc nc Degraded 01h 01h GEN c Non fatal Temperature Threshold ul c nc nc Degraded As and 01h Oth c Non fatal De 9 Thermal Trip PCH Therm Trip Baseboard Temperature 1 Baseboard Temp Front Panel Temperature 21h All Front Panel Temp PCH TemperatureNote1 PCH Temp Temperature Temperature Revision 1 0 02 Log area reset cleared Trig Offset 04 PEF action Trig Offset EE 6 As and 5433 En 123 Intel order number G13326 003 Appendix B Integrated BMC Sensor Tables Intel Server Board S1200BT TPS Full Sensor Name Sensor name in SDR Baseboard Temperature 3 Inlet Temp Hot swap Backplane Temperature HSBP Temp Fan Tachometer Sensors Chassis specific sensor names Power Supply 1 Status PS1 Status Power Supply 2 Status PS2 Status Power Supply 1 AC Power Input PS1 Power In Power Supply 2 AC Power Input PS2 Power In Power Supply 1 12V 95 of Maximum Current Output PS1 Curr Out 95 124 Sensor Platform Applicability Chassis specific Chassis specific Chassis specific Chassis specific Chassis specific Chassis specifi
100. he Intel Xeon SandyBridge Series processor Table 46 Intel Xeon Processor TDP Guidelines TPC 150A 10 3 Power Supply Output Requirements This section is for reference purposes only The intent is to provide guidance to system designers to determine a power supply for use with this server board This section specifies the power supply requirements Intel used to develop a power supply for the Intel Server System R1304BTLSHBN The following tables define two power and current ratings for this 350 W power supply The combined output power of all outputs should not exceed the rated output power The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions Table 47 350 W Load Ratings o2 Dev oa u av a o3 o Notes 1 Maximum continuous total DC output power should not exceed 350 W 2 Peaktotal DC output power should not exceed 400 W 3 Peak power and peak current loading should be supported for a minimum of 12 seconds 4 Combined 3 3 V 5 V power should not exceed 100 W 112 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Design and Environmental Specifications 10 3 1 Grounding The grounds of the power supply output connector pins provide the power return path The output connector ground pins are connected to the safety ground power supply enclosure This grounding is designed to e
101. he absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Information provided in this document may be incomplete as denoted by TBD Revised information will be published in a later release of this document and when the related product is made available The Intel Server Board S1200BT may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Intel Pentium Itanium and Xeon are trademark
102. he logo screen during POST Disabled Display the diagnostic screen during POST 7 POST Error Pause Option Values Enabled Disabled Help Text Enabled Go to the Error Manager for critical POST errors Disabled Attempt to boot and do not go to the Error Manager for critical POST errors Comments If enabled the POST Error Pause option takes the system to the error manager to review the errors when major errors occur Minor and fatal error displays are not affected by this setting 8 System Date Option Values System Date initially displays the current system calendar date including the day of the week Help Text System Date has configurable fields for the current Month Day and Year The year must be between 2005 and 2099 Use Enter or Tab key to select the next field Use or key to modify the selected field Comments This field will initially display the current system day of week and date It may be edited to change the system date 9 System Time Option Values System Time initially displays the current system time of day in 24 hour format Help Text System Time has configurable fields for Hours Minutes and Seconds Hours are in 24 hour format Use the Enter or Tab key to select the next field Use the or key to modify the selected field Comments This field will initially display the current system time 24 hour time It may be edited to change the system time
103. ightly delayed depending on the bandwidth and latency of the network Enabling KVM and or media encryption will degrade performance Enabling video compression provides the fastest response while disabling compression provides better video quality For the best possible KVM performance a 2Mb sec link or higher is recommended The redirection of KVM over IP is performed in parallel with the local KVM without affecting the local KVM operation 4 2 2 3 Security The KVM redirection feature supports multiple encryption algorithms including RC4 and AES The actual algorithm that is used is negotiated with the client based on the client s capabilities 4 2 2 4 Availability The remote KVM session is available even when the server is powered off in stand by mode No re start of the remote KVM session shall be required during a server reset or power on off An Integrated BMC reset e g due to an Integrated BMC Watchdog initiated reset or Integrated BMC reset after Integrated BMC firmware update will require the session to be re established KVM sessions persist across system reset but not across an AC power loss 4 2 2 5 Timeout The remote KVM session will automatically timeout after a configurable amount of time 30 minutes is the default The default inactivity timeout is 30 minutes but may be changed through the embedded web server Remote KVM activation does not disable the local system keyboard video or mouse Remote KVM is no
104. ing any point of the voltage rise The 5 V output must never be greater than the 3 3 V output by more than 2 25 V Each output voltage should reach regulation within 50 ms Tyout on of each other when the power supply is turned on Each output voltage should fall out of regulation within 400 msec of each other when the power supply is turned off Figure 49 and Figure 50 shows the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied Table 52 Output Voltage Timing Item Description Minimum Maximum Units rise Output voltage rise time from each main output 5 01 701 Msec on All main outputs must be within regulation of each 50 Msec other within this time Tvout oft All main outputs must leave regulation within this 700 Msec time Note 1 The 5 VSB output voltage rise time should be from 1 0 ms to 25 0 ms t i i EN i i I t i i i V2 i I i i i i 10 i I i v3 1 i i i i i v4 iN i i i i n iT i Tvout rise cer mtd lt gt i Tvout_on AF002709 Figure 49 Output Voltage Timing Revision 1 0 115 Intel order number G13326 003 Design and Environmental Specifications Table 53 Turn On Off Timing Intel Server Board 51200
105. intel Intel Server Board S1200BT Technical Product Specification Intel order number G13326 003 Revision 1 0 HJ intel 2 March 2011 SERVER BOARD inside Enterprise Platforms and Services Division Revision History Intel Server Board 51200 TPS Revision History SSCs 02 July 2010 Initial release November 2010 Updated the hardware info and SE SKU January 2011 Updated S1200BTS info and BIOS setup page January 2011 0 9 Updated S1200BT video mode March 2011 Corrected typos ii Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on t
106. ions screen then select the desired screen Revision 1 0 Intel order number G13326 003 85 BIOS User Interface Intel amp Server Board 51200 TPS Boot Options BEV Device Order BEV Device 1 Available BEV devices BEV Device 2 Available BEV devices Figure 39 BEV Device Order Screen 6 5 2 24 Add EFI Boot Option The Add EFI Boot Option screen allows the user to add an EFI boot option to the boot order This screen is only available when there is at least one EFI bootable device present in the system configuration The Internal EFI Shell Boot Option is permanent and cannot be added or deleted To access this screen from the Main screen select Boot Options Add EFI Boot Option To move to another screen press the Esc key to return to the Boot Options screen then select the desired screen Boot Options Add EFI Boot Option Add boot option label Select File system Available File systems Path for boot option Save Figure 40 Add EFI Boot Option Screen 6 5 2 25 Delete EFI Boot Option The Delete EFI Boot Option screen allows the user to remove an EFI boot option from the boot order The Internal EFI Shell Boot Option will not be listed since it is permanent and cannot be added or deleted To access this screen from the Main screen select Boot Options gt Delete Boot Option To move to another screen press the Esc key to return to the Boot Options screen then select the
107. jumper to its normal position The user should not interrupt the BIOS POST on the first boot after recovery When the flash update completes Remove the recovery media Turn off the system power Restore the jumper to its original position Turn on the system power Re flash any custom blocks such as user binary or language blocks gr de xm The system should now boot using the updated system BIOS 108 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 5 Intel amp Light Guided Diagnostics 9 Intel Light Guided Diagnostics The server board has several on board diagnostic LEDs to assist in troubleshooting board level issues This section shows where each LED is located on the server board and describes the function of each LED 9 1 System Status LED Only for S1200BTL The server board provides a system status indicator LED on the front panel This indicator LED has specific states and corresponding interpretation as shown in the following table Table 44 Front Panel LED Behavior Summary LED Color Condition Description BoweliSiaen Green On Power or 50 sleep Green Blink 1 sleep or S3 standby only for workstation baseboards Off Off also sleep 54 55 modes Green On System ready No alarm System ready but degraded redundancy lost such as PS or Green Blink fan failure non critical temp voltage threshold battery failure or predictive PS failure Critical alar
108. l interface specifies the protocols that must be supported in this version of NM The table below summarizes the feature support for NM 2 0 Table 12 NM Features Platform power monitoring Monitor Power amp Thermal monitoring and thermal policy support Thermal TAE Processor package power monitoring v Memory power monitoring K MN Platform Power limiting policy support iY Revision 1 0 43 Intel order number G13326 003 Platform Management Intel Server Board 51200 TPS nd Thermal Poli Thermal Policy Limit power upon power excursion OS operational 2 Reduce power upon temperature excursion Limit power even when OS is not operational OS failure Reduce power consumption to prevent tripping DC circuit breaker Avoid Triggering IPMI based commands over SMBus monitoring control amp alert PECI Proxy and Pass Through this feature is also available on the ME Si Enabling firmware Interfaces Power telemetry from Integrated BMC or from PMBus compliant power supplies Note EPSD systems have ME get power data directly from power supplies HW Protection Power supply optimization technologies SmaRT amp CLST used to limit power consumption to reduce demand on power supplies in specific scenarios 4 4 3 Role of Integrated BMC in NM This section summarizes the Integrated BMC role in the NM feature implementation 4 4 3 1 External C
109. l order number G13326 003 Intel amp Server Board 51200 TPS Glossary Glossary This appendix contains important terms used in this document For ease of use numeric entries are listed first for example 82460GX followed by alpha entries for example AGP 4 Acronyms are followed by non acronyms 8 bit quantity Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis Common Enabling Kit Challenge Handshake Authentication Protocol Complementary Metal oxide semiconductor In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board Gunning Transceiver Logic Host Physical Address Hot swap Controller Revision 1 0 137 Intel order number G13326 003 Glossary Intel amp Server Board 51200 TPS Hertz 1 cycle second 138 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Glossary Platform Environment Control Interface PWM RASUM Reliability Availability Serviceability Usability and Manageability RISC Read Only Memory Real Time Clock Component of ICH peripheral chip on the server board Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read Only Memory System Event Log Server Input Output S S S 5 5
110. le threaded workloads Intel Turbo Boost Technology operation Turbo Boost operates under Operating System control It is only entered when the operating system requests the highest PO performance state Turbo Boost operation can be enabled or disabled in BIOS Setup Turbo Boost converts any available power and thermal headroom into a higher frequency on active cores At nominal marked processor frequency many applications consume less than the rated processor power draw Turbo Boost availability is independent of the number of active cores Maximum Turbo Boost frequency depends on the number of active cores and varies by processor configuration The amount of time the system spends in Turbo Boost operation depends on workload operating environment and platform design If the processor supports the Intel Turbo Boost Technology feature the BIOS Setup provides an option to enable or disable this feature The default state is enabled 3 2 Memory Subsystem The Intel Xeon Processor E3 1200 series or Intel CoreTM Processor i3 2100 has an Integrated Memory Controller IMC in its package Each processor produces up to two DDR3 channels of memory Each DDR3 channel in the IMC supports up to two UDIMM slots The DDR3 UDIMM frequency can be 1066 1333 MHz Only ECC memory is supported on this platform Revision 1 0 17 Intel order number G13326 003 Functional Architecture Intel Server Board 51200 TPS me
111. lers Platforms supporting AHCI may take advantage of performance features such as no master slave designation for SATA devices each device is treated as a master and hardware assisted native command queuing AHCI also provides usability enhancements such as Hot Plug AHCI requires appropriate software support e g an AHCI driver and for some features hardware support in the SATA device or additional platform hardware 3 4 3 1 Intel Matrix Storage Technology The Intel C200 Series chipset provides support for Intel Rapid Storage Technology providing both AHCI see above for details on AHCI and integrated RAID functionality The RAID capability provides high performance RAID 0 1 5 and 10 functionality on up to 6 SATA ports of the PCH Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives such as RAID 0 and RAID 1 on two disks Other RAID features include hot spare support SMART alerting and RAID 0 auto replace Software components include an Option ROM for pre boot configuration and boot functionality a Microsoft Windows compatible driver and a user interface for configuration and management of the RAID capability of PCH 3 4 4 Low Pin Count LPC Interface The Intel C200 Series chipset implements an LPC Interface as described in the LPC 1 1 Specification The Low Pin Count LPC bridge function of the C202 resides in PCI Device 31 Function 0 In addition to the LPC bridg
112. lled There is a DDR3 DIMM installed in this slot e Not Installed There is no DDR3 DIMM installed in this slot Failed The DDR3 DIMM installed in this slot has been disabled by the BIOS in order to optimize the memory configuration e Disabled The DDR3 DIMM installed in this slot is faulty or malfunctioning 6 5 2 6 Mass Storage Controller Configuration The Mass Storage Configuration screen allows the user to configure the SATA or SAS controller when it is present on the server board midplane or backplane of an Intel system To access this screen from the Main screen select Advanced Mass Storage Controller Configuration To move to another screen press the Esc key to return to the Advanced screen then select the desired screen Advanced Mass Storage Controller Configuration Intel SAS Entry RAID Module Enabled Disabled Configure Intel SAS Entry RAID Module IT IR RAID Intel ESRTII Onboard SATA Controller Enabled Disabled Configure SATA Mode ENHANCED COMPATIBILITY AHCI SW RAID gt SATA Port 0 Not Installed Drive Info gt SATA Port 1 Not Installed Drive Info gt SATA Port 2 Not Installed Drive Info gt SATA Port 3 Not Installed Drive Info gt SATA Port 4 Not Installed Drive Info gt SATA Port 5 Not Installed Drive Info Figure 19 Mass Storage Controller Configuration Screen 6 5 2 7 Serial Port Configuration The Serial Port Configuration screen allows the user to configure
113. load transient repetition rate is tested between 50 Hz and 5 kHz at duty cycles ranging from 1096 9096 The load transient repetition rate is only a test specification The step load may occur anywhere within the Min load to the Max load conditions Table 49 Transient Load Requirements Output Step Load Size Load Slew Rate Test capacitive Load See note 2 025 Aseo 250 uF 0 25 Alusec 400 uF 11 0 0 25 A usec 500 Revision 1 0 143 Intel order number G13326 003 Design and Environmental Specifications Intel Server Board 51200 TPS Output Step Load Size Load Slew Rate Test capacitive Load See note 2 5 VSB 0 25 Aluses 20 uF Note Step loads on each 12 V output may happen simultaneously and should be tested that way 10 3 6 Capacitive Loading The power supply is stable and meets all requirements with the following capacitive loading ranges Table 50 Capacitve Loading Conditions Output Minimum Maximum Units 3 3 V 100 2200 5 400 2200 12 V 500 2200 12 V 1 350 uF 5 VSB 20 350 10 3 7 Closed loop Stability The power supply is unconditionally stable under all line load transient load conditions including capacitive load ranges A minimum of 45 phase margin and 10 dB gain margin is required The power supply manufacturer provides proof of the unit s closed loop stability with local sensing through the submission of Bode plots Closed loop s
114. lyID String name for to identify board family 51200 is used to identify BIOS builds for S1200BT server boards OEMID Three character OEM BIOS Identifier to identify the board BIOS owner Changed only if and when BIOS Development management authorizes a BIOS program for a specific OEM customer 86B is used for BIOS Releases Major Version two decimal digits 01 99 which are changed only to identify major hardware or functionality changes that affect BIOS compatibility between boards 01 is the starting BIOS Major Version for all plattorms This designation can change only at the discretion of BIOS Development management RelRev Release Revision two decimal digits 00 99 which are changed to identify specific point releases or branches based on a given BIOS Release but with targeted minor fixes or special purpose differences in functionality from the primary BIOS Release The Release Revision first digit is incremented for each initial revision of a BIOS Release The second digit will increment only if a revision itself needs to be revised with a change or fix The Release Number will not change when a BIOS is built as a Release Revision and will reset to 00 with each new Release Number 00 is the starting Release Revision for all platform BIOS Releases Release Revisions are not Standard Operating Procedure but may be produced if authorized BIOS management The se
115. m Voltage thermal or power fault CPU Status Amber On missing insufficient power unit redundancy resource offset asserted Non Critical failure Critical temp voltage threshold VDR hot Amoer PK asserted min number fans not present or failed AC power off System unplugged Off AC power on System powered off and in standby no prior degradedWon criticalcritical state Global HDD Green Blink HDD access Activi No access and no fault LAN 1 2 Green On LAN link no access Green Blink LAN access Off Idle Chassis Blue On Front panel chassis ID button pressed Identification Blue Blink Unit selected for identification via software Off No identification 9 2 Post Code Diagnostic LEDs During the system boot process the BIOS executes several platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board To assist in troubleshooting a system hang during the POST process the diagnostic LEDs can be used to identify the last POST process executed Revision 1 0 109 Intel order number G13326 003 Intel amp Light Guided Diagnostics Intel amp Server Board 51200 TPS Upper Nibble LEDs Lower Nibble LEDs t p AB CDEFGHIJ Figure 48 POST Code Diagnostic LED Location
116. mand to the Integrated BMC to provide the contribution to the system status LED 2 Support for upper non critical limit is not provided in the default SDR configuration However if a user does enable this threshold in the SDR then the system status LED should behave as described There is no precedence or lock out mechanism for the control sources When a new request arrives all previous requests are terminated For example if the chassis ID LED is blinking and the chassis ID button is pressed then the chassis ID LED changes to solid on If the button is pressed again with no intervening commands the chassis ID LED turns off Revision 1 0 95 Intel order number G13326 003 Connector Header Locations and Pin outs 7 5 7 5 1 Connectors Connector Intel Server Board 51200 TPS The following table details the pin out definition of the VGA connector J7A1 on S1200BTL and J6A1 on S1200BTS 7 5 2 Table 28 VGA Connector Pin out Pin Signal Name 4 TP VID CONN B9 G VID CONN 11 V 12 V IO DDCDAT DDCDAT 13 V IO HSYNC CONN HSYNC horizontal sync V IO VSYNC CONN VSYNC vertical sync DDCCLK 4 5 7 10 11 12 13 ND DDCCLK Rear NIC and USB connector The server board provides two stacked RJ 45 2xUSB connectors side by side on the back edge of the board The pin out for NIC connectors is identical and defined in the following table 96 Table 29 RJ 45 10
117. mory channels are named as Channel and Channel B The memory slots are named as Slot1 and 51012 on each channel Slot1will be the farthest from the processor socket DIMMs are named to reflect the channel and slot in which they are installed Channel A Slot1 is DIMM 1 Channel Slot2 is DIMM A2 o Channel B Slot1 is DIMM B1 o Channel B Slot2 is B2 3 2 1 Memory Supported The Intel Server Board S1200BT family supports various DDR3 DIMM modules of different types and sizes and speeds In this section the statements of support are subject to qualification in two ways For 51200 Server Boards with an SNB DT processor the Server Board and the BIOS may support DIMMs composed of Dynamic Random Access Memory DRAM chips using 1 Gb 2 Gb or 4 Gb technology DIMMs using x8 DRAM technology only DIMMs organized as Single Rank SR or Dual Rank DR DIMM sizes of 1 GB 2 4 or 8 GB DIMM speeds of 1066 or 1333 MT s megatransfers second Only Unregistered Unbuffered DIMMs UDIMMs are supported Only Error Correction Code ECC enabled DIMMs are supported UDIMMs may or may not have thermal sensors Note UDIMMs must be ECC and may or may not have thermal sensors S1200BT BIOS has the following limitations support for LV DIMMs support for RDIMMs All channels in a system will run at the fastest common frequency Mixing ECC and non
118. n J7J1 on S1200BTL and J2J1 on S1200BTS SYS4 fan J7B1 for S1200BTL Table 41 SSI 4 pin Fan Header Pin out T Ground isthe power supply ground 2 i2V Power supply 12 V pup FAN TACH signal is connected to the Integrated BMC to monitor the fan speed Fan PWM FAN PWM signal to control fan speed Revision 1 0 103 Intel order number G13326 003 Jumper Blocks 8 Intel amp Server Board 51200 TPS Jumper Blocks The server board has several 3 pin jumper blocks that can be used to configure protect or recover specific features of the server board gt Protected RTC 2 2 3 Password Clear 2 J1F1 ME gt Force Update 2 3 BIOS Recovery 2 J1F3 310 Default Enabled Default Clear Default Password Clear F Default Enabled Default Recover AF003510 Figure 46 Jumper Blocks J4A2 J1F1 J1F3 J1F2 and J1E2 on S1200BTL Table 42 Server Board Jumpers J1F1 J1F2 J1F3 J1E2 and J4A2 on S1200BTL Jumper Name Pins System Results J1E2 CMOS 1 2 These pins should have a jumper in place for normal system operation Default Clear 2 3
119. n out J9G1 3 3 12 Revision 1 0 91 Intel order number G13326 003 Connector Header Locations and Pin outs Intel amp Server Board 51200 TPS Table 20 SSI Processor 8 PIN Power Connector Pin out J9A1 2 P12V1 4 7 3 System Management Headers 7 3 4 Intel Remote Management Module 4 Intel RMM4 Lite connetor and Dedicated NIC connector An Intel RMM 4 lite connector J4B1 is included on the server board to support the optional Intel Remote Management Module 4 lite This server board does not support third party management cards Note This connector is not compatible with the Intel Remote Management Module Intel the Intel Remote Management Module 2 Intel 2 or the Intel Remote Management Module 3 Intel RMM3 Table 21 Intel 4 lite Connector Pin out J4B1 Pin Name Pin Name 1 2 DI 3 KEY 4 CLK 5 DO 6 GND 7 CS 8 GND There is an Intel Remote Management Module 4 Intel RMM4 Dedicated NIC connector J5C1 Table 22 Dedicated NIC connector for 4 Pin Name Pin Name 1 3V3 AUX 2 MDIO 3 3V3 AUX 4 MDC 5 GND 6 TXD 0 7 GND 8 TXD 1 9 GND 10 TxD 2 11 GND 12 TXD 3 13 14 TX 15 16 RX Intel order number G13326 003 Revision 1 0 Intel amp Se
120. n process and by System BIOS during run time 4 3 2 1 System Configuration Using the FRUSDR Utility The Field Replaceable Unit and Sensor Data Record Update Utility FRUSDR utility is a program used to write platform specific configuration data to NVRAM on the server board It allows the user to select which supported chassis Intel or Non Intel and platform chassis configuration is used Based on the input provided the FRUSDR writes sensor data specific to the configuration to NVRAM for the BMC controller to read each time the system is powered on 4 4 Intel Intelligent Power Node Manager 4 4 1 Overview Power management deals with requirements to manage processor power consumption and manage power at the platform level to meet critical business needs Node Manager NM is a platform resident technology that enforces power capping and thermal triggered power capping policies for the platform These policies are applied by exploiting subsystem knobs such as processor P states that can be used to control power consumption NM enables data center power management by exposing an external interface to management software through which platform policies can be specified It also implements specific data center power management usage models such as power limiting and thermal monitoring 42 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Platform Management The NM feature is implemented by a compleme
121. n twice as much bandwidth per lane as compared to 2 5 GT s operation When operating with two PCI Express controllers each controller can operate at either 2 5 GT s or 5 0 GT s The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries 3 4 3 Serial ATA Support The Intel C200 Series chipset has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6 0 Gb s on up to two ports Port 0 and 1 Only on S1200BTL while all ports support rates up to 3 0 Gb s The SATA controller contains two modes of operation a legacy mode using space 22 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Functional Architecture and an AHCI mode using memory space Software that uses legacy mode will not have AHCI capabilities Software that uses legacy mode does not have Advanced Host Configuration Interface AHCI capabilities The Intel C202 PCH Chipset supports the Serial ATA Specification Revision 1 0a The also supports several optional sections of the Serial ATA Il Extensions to Serial ATA 1 0 Specification Revision 1 0 AHCI support is required for some elements The Intel C200 Series chipset PCH provides hardware support for AHCI a standardized programming interface for SATA host control
122. nators Connector Type 24 Power supply 3 J9G1 J9A1 J9F1 Main power CPU power 8 P S aux 5 i jr Dedicated NIC NIC Stack2xUSB 2 J5A1 J031 1 DudUSB js Serial potA 1 00019000 SerialpotB 9 Dual USB Internal 2 J1D1 J1E1 Header Header 2 Smart Module 382 SATA RAID key JAAS SATA SGPIO 90 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Connector Header Locations and Pin outs Table 18 Board Connector Matrix on S1200BTS Quantity Reference Designators Connector Type Power supply 2 J9G1 J9A1 Main power 24 1298 1011 CPU 55 memoy fa es sockets 4 System Fans 3 J2J8 J7J1 J7B1 NIC Stack 2x USB 2 8 SerialpotA i J8A1 Connector 9 Header Poes e 3Gb s Serial ATA 6 J191 J192 J1H1 J1H2 Header 7 7 2 Power Connectors The main power supply connection uses an 551 2x12 pin connector J9G1 In addition there is one additional power related connector One SSl compliant 2x4 pin power connector J9G1 which provides 12 V power the CPU VRD The following tables define the connector pin outs Table 19 Baseboard Power Connector Pi
123. nd DIMM power and thermal parameters Support for CLTT on mixed mode DIMM populations i e some installed DIMMs have valid temp sensors and some do not is not supported The Integrated BMC fan speed control functionality is related to the memory throttling mechanism used The following terminology is used for the various memory throttling options Static Open Loop Thermal Throttling Static OLTT OLTT control registers configured by BIOS MRC remain fixed after post The system does not change any of the throttling control registers in the embedded memory controller during runtime Static Closed Loop Thermal Throttling Static CLTT CLTT control registers are configured by BIOS MRC during POST The memory throttling is run as a closed loop system with the DIMM temperature sensors as the control input Otherwise the system does not change any of the throttling control registers in the embedded memory controller during runtime 4 3 2 Fan Speed Control BIOS and BMC software work cooperatively to implement system thermal management support During normal system operation the BMC will retrieve information from the BIOS and monitor several platform thermal sensors to determine the required fan speeds In order to provide the proper fan speed control for a given system configuration the BMC must have the appropriate platform data programmed Platform configuration data is programmed using the FRUSDR utility during the system integratio
124. nd a short beep is emitted to indicate such an action For example if a USB device is hot plugged the BIOS detects the device insertion initializes the device and makes it available to the user During POST when the USB controller is initialized it emits a short beep for each USB device in the system as if they were all just hot added Only on board USB controllers are initialized by BIOS This does not prevent the operating system from supporting any available USB controllers including add in cards 3 4 5 2 Legacy USB Support The BIOS supports PS 2 emulation of USB keyboards and mouse During POST the BIOS initializes and configures the root hub ports and searches for a keyboard and or a mouse on the USB hub and then enables the devices that are recognized 3 5 Optional Intel SAS RAID Module The Intel Server Board S1200BTL provides a SAS Mezzanine slot J2H1 for the installation of an optional Intel SAS RAID Module Once the optional Intel SAS Entry RAID Module is detected the x4 PCI Express links from the chipset to the SAS Mezzanine slot Four modules are supported in this platform AXXRMS2AF040 AXXRMS2LL040 and AXX4SASMOD 3 6 Integrated Baseboard Management Controller The Intel Server Board S1200BTL has the highly integrated single chip baseboard management controller based on ServerEngines Pilot IIl but Intel Server Board S1200BTS does not have the integrated baseboard management control This Intel Integrated BMC
125. nsure passing the maximum allowed common mode noise levels The power supply is provided with a reliable protective earth ground All secondary circuits are connected to protective earth ground Resistance of the ground returns to chassis does not exceed 1 0 m This path may be used to carry DC current 10 3 2 Standby Outputs The 5 VSB output is present when an AC input greater than the power supply turn on voltage is applied 10 3 3 Remote Sense The power supply has remote sense return ReturnS to regulate out ground drops for all output voltages 43 3 V 5 V 12 V 12 V and 5 VSB The power supply uses remote sense to regulate out drops in the system for the 3 3 V 5 V and 12 V outputs The power supply must operate within specification over the full range of voltage drops from the power supply s output connector to the remote sense points 10 3 4 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise All outputs are measured with reference to the return remote sense signal ReturnS Table 48 Voltage Regulation Limits 5 5 5 5 11 40 12 00 12 60 10 10 13 20 12 00 10 80 5 VSB 5 4596 10 3 5 Dynamic Loading The output voltages remain within limits for the step loading and capacitive loading specified in the following table The
126. ntary architecture utilizing the ME Integrated BMC BIOS an ACPI compliant OS The ME provides the NM policy engine and power control limiting functions referred to as Node Manager or NM while the Integrated BMC provides the external LAN link by which external management software can interact with the feature The BIOS provides system power information utilized by the NM algorithms and also exports ASL code used by OSPM for negotiating processor P and T state changes for power limiting PMBus compliant power supplies provide the capability to monitoring input power consumption which is necessary to support NM The NM architecture applicable to this generation of servers is defined by the NPTM Architecture Specification v2 0 NPTM is an evolving technology that is expected to continue to add new capabilities that will be defined in subsequent versions of the specification The ME NM implements the NPTM policy engine and control monitoring algorithms defined in the NPTM specification 4 4 2 Features NM provides feature support for policy management monitoring and querying alerts and notifications and an external interface protocol The policy management features implement specific IT goals that can be specified as policy directives for NM Monitoring and querying features enable tracking of power consumption Alerts and notifications provide the foundation for automation of power management in the data center management stack The externa
127. ntegrated BMC LAN Channel MAC address Assigned the NIC 1 MAC address 2 Intel Remote Management Module 4 dedicated NIC MAC address Assigned the NIC 1 MAC address 3 Each Intel Server Board S1200BTS has the following two MAC addresses assigned to it at the Intel factory NIC 1 MAC address 2 MAC address Assigned the NIC 1 MAC address 1 3 9 Intel Acceleration Technolgy 2 Intel 1 2 Intel AT2 is not supported 3 9 1 Direct Cache Access DCA Direct Cache Access DCA is not supported on Intel Xeon Processor E3 1200 Series 3 10 Intel Virtualization Technology for Directed 1 Intel VT d The Intel C202 chipset provides hardware support for implementation of Intel Virtualization Technology with Directed Intel VT d Intel VT d Technology consists of technology components that support the virtualization of platforms based on Intel Architecture Processors Intel VT d technology enables multiple operating systems and applications to run in independent partitions A partition behaves like a virtual machine VM and provides isolation and protection across partitions Each partition is allocated its own subset of host physical memory Note If the setup options are changed to enable or disable the Virtualization Technology setting in the processor the user must perform an AC power cycle for the changes to take effect 30 Revision 1 0 Intel order number G13326 003 Intel Server B
128. ntel Turbo Boost option to be available Enhanced Intel SpeedStep Technology must be Enabled Turbo Boost Performance Watt Mode Option Values Power Optimized Traditional Help Text When Power Optimized is selected Intel Turbo Boost Technology engages after performance state PO is sustained for more than 2 seconds When Traditional is selected Intel Turbo Boost Technology is engaged even for PO requests less than 2 seconds Comments Turbo Boost Power Optimization is not available on all processors and is available only when Intel Turbo Boost Technology and Enhanced Intel SpeedStep Technology are Enabled Processor C3 Option Values Enabled Disabled Revision 1 0 Intel order number G13326 003 Intel Server Board 51200 TPS BIOS User Interface 11 12 13 14 Help Text Enable Disable Processor C3 ACPI C2 C3 report to OS Comments This is normally Disabled but can be Enabled for improved performance on certain benchmarks and in certain situations Processor C6 Option Values Enabled Disabled Help Text Enable Disable Processor C6 ACPI C3 report to OS Comments This is normally Enabled but can be Disabled for improved performance on certain benchmarks and in certain situations Intel Hyper Threading Tech Option Values Enabled Disabled Help Text Intel Hyper Threading Technology allows multithreaded software applications to execute threads in parallel within each processor C
129. o 6Gb s SATA ports Q MAIN POWER HH Smart module A B CD E F G Y X W K d 1 u qi i 2 TCH 003624 Figure 4 Intel Server Board S1200BTS Layout Table 3 Major Board Components Description Description A Slot 4 32 Mbit 33 MHz PCI N SYS FAN 1 B Slot 5 PCI Express Gen2 x8 x8 connector O CPU connector Slot 6 PCI Express Gen2x4 x8 connector Revision 1 0 f Intel order number G13326 003 Overview Intel Server Board 51200 TPS Description Description C SATA KEY P CPU Fan connector D Slot 7 PCI Express Gen2 x8 x16 connector Q Chassis Intrusion E Ethernet and Dual USB COMBO R SATA SGPIO F Ethernet and Dual USB COMBO S SYS FAN 3 G Video port T Six 3Gb s SATA ports H External Serial port U Low profile USB connector CPU Power connector V Internal USB J SYS FAN 2 W CMOS battery K DIMM slots X Front Panel L MAIN power connector Y HDD LED M TPM connector 2 2 2 Intel Server Board S1200BTL Mechanical Drawings Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Overview de S 5 4 aH alag 85 d H d d 88 855280 89 a3 85 88 Sc 8394 Be zm 2 d AS AS AM e 20 s u CS CS om mW 4 0 000 0 00 0 900 22 861 2 090 53 09 2 270 57 66 2 500 163 501 3 834
130. o Screen Diagnostic Screen 2 1 49 6 4 BIOS Boot Popup MOL te EE 50 6 5 BIOS Sep Of uc e st TM d ord 50 6 5 1 BIOS Setup Operation mr 50 6 5 2 BIOS Setup Utility Screens 53 7 Connector Header Locations and Pin outs J 90 7 1 Board Connector Information 90 7 2 Power Gonf8cIolS u urus 91 7 3 System Management Headers rr 92 7 3 1 Intel Remote Management Module 4 Intel RMM4 Lite connetor and Dedicated Ls S ecce etie toe re pedet 92 7 3 2 a 93 7 3 3 n Eye lo rin Mh 93 72302 2SUOPIO Dead oe 93 7 4 Front Control Panel Connector 93 7 4 1 Power EE 94 7 4 2 ResebBUIOn tants E RP Meats 95 7 4 3 System Status Indicator LED vati Se Peas dte tures 95 7 5 COMMBCIONS ws asi aee Ss beber S deese bebe dst ei mans enter 96 7 5 1 VGA CONNECC
131. o all thresholds of the sensor This column provides the count of hysteresis for the sensor which can be 1 or 2 positive or negative hysteresis Criticality Criticality is a classification of the severity and nature of the condition It also controls the behavior of the front panel status LED Standby Some sensors operate on standby power These sensors may be accessed and or generate events when the main system power is off but AC power is present Revision 1 0 121 Intel order number G13326 003 Appendix B Integrated BMC Sensor Tables Table 56 BMC Core Sensors Intel amp Server Board 51200 TPS Full Sensor Name Sensor Platform Sensor name in SDR Applicability Power Unit Status Pwr Unit Status Power Unit Redundancy1 Pwr Unit Redund Chassis specific IPMI Watchdog IPMI Watchdog 122 Sensor Type Power Unit Power Unit 09h Watchdog 2 Event Reading Type Sensor Specific 6Fh Generic OBh Sensor Specific 6Fh Event Offset Triggers Contrib To System Status assert 00 Powerdown Power down 04 D lost 05 ERI MEM power control As and failure De Fatal 06 Power unit failure 00 Fully Redundant 22 01 Redundancy lost Degraded 02 Redundancy Degraded degraded Degraded 03 Non redundant sufficient resources Transition from full redundant state 04 Non redundant sufficient resources Transition from Degraded insuffi
132. oard 51200 TPS Functional Architecture 3 11 TPM Trusted Platform Module There is one TPM module connector The detail information is listed below Embedded TPM 1 2 firmware 33 2 Low Pin Count LPC interface V1 1 Compliant with TCG PC client specific TPM Implementation Specification TIS V1 2 For the detail Intel TPM module please refer to TPM module user guide Revision 1 0 31 Intel order number G13326 003 Platform Management Intel amp Server Board S1200BT TPS 4 Platform Management This chapter is only for The Intel Server Board S1200BTL The platform management subsystem is based on the Integrated BMC features of the ServerEngines Pilot III The onboard platform management subsystem consists of communication buses sensors system BIOS and server management firmware The following diagram provides an overview of the Server Management Bus SMBUS architecture used on this server board STBY BB Sensor4 BB Optional BB sensor2 BB Sensori BB Sensor3 sensor 5 Temp 0x96 Temp 0x94 Front Panel Front Panel Temp 0x98 FRU Temp 0x9E Temp 0x9A Temp 0x9C Note The SMBus to PCIE slot connection is Note This sensor5 address is optional reserved for certain cased which will use it for only reserved for possible Thermal GPU management management on certain board such as lronPass Host 3 3V Main e
133. odated in the 1U chassis The following table shows the pin out for this riser slot Table 38 Pin out of adaptive riser slot PCI Express slot 6 Pin Signal Description Pin Signal Description B1 12 P12V A1 PRSNT1_N GND B2 12 P12V A2 12 P12V RSVD P12V A3 12 P12V B4 GND GND A4 GND GND B5 SMCLK PU S6 SMBCLK A5 JTAG2 P3V3 RISER A5 B6 SMDATA PU S6 SMBDAT A6 JTAG S6 TDI B7 GND GND A7 JTAG4 NC B8 3 3V P3V3 A8 JTAG5 P3V3 RISER A8 B9 JTAG1 JTAG S6 TRST N A9 3 10 3 3VAUX P3V3_AUX A10 43 3V P3V3 B11 WAKE N FM PE WAKE N A11 PERST N RST PE S236 N R1 KEY KEY KEY KEY B12 RSVD NC A12 GND GND B13 GND GND A13 REFCLKP CLK 100M SLOT6A DP B14 PETPO 2 CPU C S6 7 A14 REFCLKN CLK 100M SLOT6A DPN B15 PETNO 2 CPU C S6 7 A15 GND GND B16 GND GND A16 PERPO P2E CPU S6 RXP 7 B17 PRSNT2 N NC A17 PERNO P2E CPU 56 lt 7 gt B18 GND GND A18 GND GND B19 PETP1 P2E CPU C S6 6 A19 RSVD NC B20 PETN1 P2E CPU C S6 lt 6 gt A20 GND GND B21 GND GND A21 PERP1 P2E CPU S6 lt 6 gt B22 GND GND A22 1 P2E CPU 56 lt 6 gt B23 PETP2 2 CPU C 56 5 A23 GND GND B24 PETN2 P2E CPU C S6 5 A24 GND GND B25 GND GND A25 PERP2 P2E CPU S6 lt 5 gt B26 GND GND A26 PERN2 P2E CPU S6 5 B27 2
134. olerance observed since a Correctable Error can be generated by something as random as a stray Cosmic Ray impacting the DIMM Correctable Errors are counted on a per DIMM basis but are just silently recorded until the tolerance threshold is crossed The Correctable Error Threshold for Intel Server Board S1200BT board is set at 10 events When the 10 CE occurs a single Correctable Error event is logged 3 3 Intel Chipset PCH The Intel C200Series Chipset is designed for use with Intel Xeon Processor E3 1200 series or Intel Core Processor i3 2100 in a UP server platform The role of the in the Intel Server Board S1200BT is to manage the flow of information between its eleven interfaces described below DMlinterface to Processor Express Interface PCI Interface Serial ATA Interface LPC Interface to IBMC and TPM Revision 1 0 21 Intel order number G13326 003 Functional Architecture Intel Server Board 51200 TPS USB host interface SMBus Host interface Serial Peripheral interface LAN interface ACPI interface 3 4 Sub system Intel C200 Series PCH provides extensive I O support 3 4 1 Digital Media Interface DMI Direct Media Interface DMI is the chip to chip connection between the processor and C202 chipset This high speed interface integrates advanced priority based servicing allowing for concurrent traffic and true isochronous transfer capabilities Base functionalit
135. ollowing client web browsers Microsoft Internet Explorer 7 0 Microsoft Internet Explorer 8 0 Microsoft Internet Explorer 9 0 Mozilla Firefox 3 0 Mozilla Firefox 3 5 Mozilla Firefox 3 6 The embedded web user interface supports strong security authentication encryption and firewall support since it enables remote server configuration and control The user interface presented by the embedded web user interface shall authenticate the user before allowing a web session to be initiated Encryption using 128 bit SSL is supported User authentication is based on user id and password The GUI presented by the embedded web server authenticates the user before allowing a web session to be initiated It presents all functions to all users but grays out those functions that the Revision 1 0 39 Intel order number G13326 003 Platform Management Intel Server Board 51200 TPS user does not have privilege to execute e g if a user does not have privilege to power control then the item shall be displayed in grey out font in that user s UI display The web GUI also provides a launch point for some of the advanced features such as KVM and media redirection These features are grayed out in the GUI unless the system has been updated to support these advanced features A partial list of additional features supported by the web GUI includes Presents all the Basic features to the users Power on off reset the server an
136. ommunications Link The Integrated BMC provides the access point for remote commands from external management software and generates alerts to that software The ME plays the role of an IPMI satellite controller that communicates to the Integrated BMC over a secondary IPMB There are mechanisms to forward commands to ME and send response back to originator Similarly events generated by ME to the Integrated BMC via IPMB have to be sent by the Integrated BMC to the external software over the LAN link It is the responsibility of Integrated BMC to implement these mechanisms for communication with Node Manager NM 4 4 3 1 1 Command Passing Via Integrated BMC External software wishing to communicate with the NM will send bridged IPMI commands to Integrated BMC This will be in the form an IPMI packet encapsulated in another packet following standard IPMI bridging as described in the PMI 2 0 Specification Integrated BMC forwards the encapsulated command it to NM engine on the ME and returns the response to the sender Due to the fact that some of the NM commands have potential for performance limiting and system shut down the Integrated BMC firmware enforce an administrator privilege for any commands bridged to the ME 4 4 3 1 2 Alerting Alerts may be sent from the NM in the ME to the external software by one of two different methods depending on the nature of the alert 44 Revision 1 0 Intel order number G13326 003 Intel amp Serve
137. on 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS BIOS User Interface Advanced Security Server Management 5 Assert SERR Enabled Disabled Assert NMI on PERR Enabled Disabled Resume on AC Power Loss Stay Off Last state Power On Clear System Event Log Enabled Disabled FRB 2 Enable Enabled Disabled O S Boot Watchdog Timer Enabled Disabled O S Boot Watchdog Timer Policy Power off Reset O S Boot Watchdog Timer Timeout 5 minutes 10 minutes 15 minutes 20 minutes gt Console Redirection gt System Information Hardware Monitor Figure 26 Server Management Screen S1200BTS 6 5 2 13 Console Redirection The Console Redirection screen allows the user to enable or disable console redirection and to configure the connection options for this feature To access this screen from the Main screen select Server Management gt Console Redirection To move to another screen press the Esc key to return to the Server Management screen then select the desired screen Server Management Console Redirection Console Redirection Disabled Serial Port A Serial Port B Flow Control None RTS CTS Baud Rate 9 6k 19 2k 38 4k 57 6k 115 2k Terminal Type PC ANSI VT100 VT100 VT UTF8 Legacy OS Redirection Disabled Enabled Figure 27 Console Redirection Screen Revision 1 0 77 Intel order number G13326 003 BIOS User Interface Intel amp
138. on 1 0 33 Intel order number G13326 003 Platform Management Intel amp Server Board 51200 TPS 4 1 3 Signal testing support The BMC provides test commands for setting and getting platform signal states The BMC generates diagnostic beep codes for fault conditions System GUID storage and retrieval Front panel management The BMC controls the system status LED and chassis ID LED It supports secure lockout of certain front panel functionality and monitors button presses The chassis ID LED is turned on using a front panel button or a command Power state retention Power fault analysis Intel Light Guided Diagnostics Power unit management Support for power unit sensor The BMC handles power good dropout conditions DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings Address Resolution Protocol ARP The BMC sends and responds to ARPs supported on embedded NICs Dynamic Host Configuration Protocol DHCP The BMC performs DHCP supported on embedded NICs Platform environment control interface PECI thermal management support E mail alerting Embedded web server Integrated KVM Integrated Remote Media Redirection Local Directory Access Protocol LDAP support Intel Intelligent Power Node Manager support New Manageability Features This generation server products offer a number of changes and additions
139. ons It also displays the NIC MAC Addresses in use To access this screen from the Main screen select Advanced PCI Configuration To move to another screen press the Esc key to return to the Advanced screen then select the desired screen Revision 1 0 73 Intel order number G13326 003 BIOS User Interface Intel Server Board S1200BT TPS Advanced PCI Configuration Maximize Memory below 4GB Enabled Disabled Memory Mapped above 4GB Enabled Disabled Onboard Video Enabled Disabled Dual Monitor Video Enabled Disabled Wake on LAN PME Enabled Disabled Onboard NIC1 ROM Enabled Disabled Onboard NIC2 ROM Enabled Disabled Onboard NIC3 ROM Enabled Disabled Onboard NIC4 ROM Enabled Disabled Onboard 5 ROM Enabled Disabled Onboard NIC iSCSI ROM Enabled Disabled NIC 1 MAC Address NIC 2 MAC Address NIC 3 MAC Address NIC 4 MAC Address NIC 5 MAC Address Figure 22 PCI Configuration Screen 10 Wake on LAN PME Option Values Enabled Disabled Help Text Enables or disables PCI PME function for Wake on LAN capability from LAN adapters Comments Enables disables PCI PCle PME signal to generate Power Management Events PME and ACPI Table entries required for Wake on LAN WOL However note that this will enable WOL only with an ACPI capable Operating System which has the WOL function enabled 6 5 2 10 System Acoustic and Performance Configuration The System Acoustic and Performance
140. ontact your OS vendor regarding OS support of this feature Comments This option is only visible if all processors installed in the system support Intel Hyper Threading Technology Core Multi Processing Option Values All 2 4 Help Text Enable 1 2 3 4 5 6 7 or all cores of installed processor packages Comments The number of cores that appear as selections and in the Help text depends on the number of cores in the processors installed Execute Disable Bit Option Values Enabled Disabled Help Text Execute Disable Bit can help prevent certain classes of malicious buffer overflow attacks Contact your OS vendor regarding OS support of this feature Comments This option is only visible if all processors installed in the system support the Execute Disable Bit The OS and applications installed must support this feature in order for it to be enabled Revision 1 0 65 Intel order number G13326 003 BIOS User Interface Intel Server Board 51200 TPS 15 Intel Virtualization Technology Option Values Enabled Disabled Help Text Intel Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions Note A change to this option requires the system to be powered off and then back on before the setting takes effect 66 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface Comments This option is only visibl
141. onymous root User3 User4 User5 Privilege Callback User Operator Administrator User status Disable Enable User Name 5 User Password Figure 30 BMC LAN Configuration Screen S1200BTL 6 5 2 16 Hardware Monitor The Hardware Monitor screen allows the user to configure Fan Speed Control and to view displays of temperature and voltage status To access this screen from the Main screen select Server Management gt Hardware Monitor To move to another screen press the lt Esc gt key to return to the Server Management screen then select the desired screen 80 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 BIOS User Interface Server Management Hardware Monitor gt Real time Temperature and Voltage Status Fan Controller Auto Manual CPU Fan Altitude 300m 900m 1500m 3000m System Fan Altitude 300m 900m 1500m 3000m Figure 31 Hardware Monitor Screen Auto Fan Control S1200BTS Server Management Hardware Monitor gt Real time Temperature and Voltage Status Fan Controller Manual CPU Fan Hysteresis 2 Degree Celsius 3 Degree Celsius 4 Degree Celsius Default Fan PWM 40 60 80 100 System Fan Hysteresis 2 Degree Celsius 3 Degree Celsius 4 Degree Celsius Default Fan PWM 40 60 80 100 Auxiliary Fan 1 Hysteresis 2 Degree Celsius 3 Degree Celsius 4 Degree Celsius Default Fan PWM 40 60 80 100 Auxiliary Fan 2 Hysteresis 2 Degree Celsius 3 Degree Celsius
142. orrective action or choose to continue booting Halt The message displays on the Error Manager screen an error is logged to the SEL and the system cannot boot unless the error is resolved The user must replace the faulty part and restart the system The setup POST error Pause setting does not have any effect with this error For example Error Code 8540 DIMM A1 disabled o Error Class 85 DIMM error o Error Subclass 4 DIMM disabled o Error Descriptor 0 DIMM A1 is the DIMM that has been disabled Be aware that these POST Error Codes must be coordinated with the Server Management Utilities team which maintains a master list of these codes Table 59 POST Error Codes and Messages Error Code Error Message Response 0012 CMOS date time not set Major 0048 Password check failed Major 0140 PCI component encountered a PERR error Major 0141 PCI resource conflict Major 0146 PCI out of resources error Major 5220 CMOS NVRAM configuration cleared Major 5221 Passwords cleared by jumper Major 5224 Password clear jumper is Set Major 8160 Processor 01 unable to apply microcode update Major Intel order number G13326 003 Appendix D POST Code Errors Intel amp Server Board 51200 TPS Error Code Error Message Response 8180 Processor 01 microcode update not found Minor 8190 Watch
143. ower pins of the power supply connector during any single point of fail The voltage never trips any lower than the minimum levels when measured at the power pins of the power supply connector Exception 5 VSB rail should be able to recover after an over voltage condition occurs Table 55 Over voltage Protection OVP Limits ima Revision 1 0 117 Intel order number G13326 003 Design and Environmental Specifications Intel amp Server Board 51200 TPS 5VSB 118 Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT TPS Appendix A Integration and Usage Tips Appendix A Integration and Usage Tips When adding or removing components or peripherals from the server board AC power must be removed With AC power plugged into the server board 5 Volt standby is still present even though the server board is powered off When updating BIOS and BMC AC power must be on Supports only Intel Xeon Processor E3 1200 Series with 95 W or Intel Core Processor i3 2100 and less Thermal Design Power TDP Does not support previous generations of the Intel Xeon processor On the back edge of the server board are diagnostic LEDs that display a sequence of amber POST codes during the boot process If the server board hangs during POST the LEDs display the last POST event run before the hang Supports only unbuffered DDR3 DIMMs UDIMMs Does not support the mixing of RDIMMs and UDIMMs
144. quence will be as in the following examples for Release Revision and Release Number Release 2 i e 2 0 RelRev RelNum 00 0002 Release 2 Revision 1 i e 2 1 RelRev RelNum 10 0002 Release 2 Revision 1 fix 1 i e 2 11 RelRev RelNum 11 0002 Release 3 i e 3 0 reverts to RelRev RelNum 00 0003 Revision 1 0 47 Intel order number G13326 003 BIOS User Interface Intel Server Board 51200 TPS RelNum Release Number four decimal digits which are changed to identify distinct BIOS Releases BIOS Releases are major collections of fixes and changes in functionality 0001 is the starting Release Number for all platform BIOS releases for each distinct BoardFamilyID and OEMID This number increases by 1 for each BIOS release It does not increment for a Release Revision It resets to 0001 when the Major Version changes or for a different BoardFamilyID or OEMID BuildDateTime Build timestamp date and time in MMDDYYYYHHMM format MM Two digit month DD Two digit day of month Four digit year HH Two digit hour using 24 hour clock MM Two digit minute For example the following BIOS ID string is displayed on the POST diagnostic screen for BIOS Release 3 that is generated on August 13 2010 at 11 56 AM S1200BT 86B 01 00 0003 081320101156 The BIOS version in the Setup Utility is displayed without the time date timestamp which is displayed separa
145. r key Select Item The down arrow is used to select the next value in a menu item s option list or a value field s pick list The selected item must then be activated by pressing the Enter key Select Menu The left and right arrow keys are used to move between the major menu pages The keys have no effect if a sub menu or pick list is displayed Tab Select Field The lt Tab gt key is used to move between fields For example Tab can be used to move from hours to minutes in the time item in the main menu Change Value The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full list Change Value The plus key on the keypad is used to change the value of the current menu item to the next value This key scrolls through the values in the associated pick list without displaying the full list On 106 key Japanese keyboards the plus key has a different scan code than the plus key on the other keyboards but will have the same effect Setup Defaults Pressing the F9 key causes the following to display Load Optimized Defaults Yes No If Yes is highlighted and Enter is pressed all Setup fields are set to their default values If No is highlighted and Enter is pressed or if the Esc key is pressed the user is returned to where they were before F9 was pressed without a
146. r Board 51200 TPS Platform Management Alerts that signify fault conditions that should be recorded in the system SEL will be sent to the Integrated BMC by the ME using the IPMI Platform Event Message command The Integrated BMC deposits such events into the SEL The external software must configure the Integrated BMC s PEF and alerting features to then send that event out as an IPMI LAN alert directed to the software application over the LAN link Alerts that provide useful notification to the external software for NM management but do not represent significant fault conditions that need to be put into the SEL will be sent to the Integrated BMC using the IPMI Alert Immediate command This requires that the external software application provide the NM on the ME with the alert destination and alert string information needed to properly form and send the alert The external software must first properly configure the alert destination and string in the Integrated BMC LAN configuration using standard IPMI commands then provide the associated selectors to the Integrated BMC using the Set Node Manager Alert Destination OEM command 4 4 3 2 BIOS Integreated BMC ME Communication In this generation of platforms the BIOS communicates directly with the ME via HECI Revision 1 0 45 Intel order number G13326 003 Server Management Capability for Intel Server Board 51200 5 Intel Server Board S1200BT TPS 5 Server Management Capability for
147. r position covering pins 2 and 3 Close the server chassis Power up the server and wait 10 seconds or until POST completes Power down the server e Open the chassis move the jumper back to the default position covering pins 1 and 2 Close the server chassis 9 Power up the server The password is now cleared and can be reset by going into the BIOS setup 106 Revision 1 0 Intel order number G13326 003 Intel amp Server Board S1200BT TPS Jumper Blocks 8 2 Integrated BMC Force Update Procedure Only for The Intel Server Board S1200BTL When performing the standard Integrated BMC firmware update procedure the update utility places the Integrated BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event the Integrated BMC firmware update process fails due to the Integrated BMC not being in the proper update state the server board provides an Integrated BMC Force Update jumper J4A2 which forces the Integrated BMC into the proper update state The following procedure should be completed in the event the standard Integrated BMC firmware update process fails 1 Power down and remove the AC power cord Open the server chassis For instructions see your server chassis documentation Move jumper from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 Close the server chassis Reconnect the AC cord and power
148. rd Set User Password Front Panel Lockout Enabled Disabled TPM State cL a State TPM Administrative Control No Operation Turn On Turn Off Clear Ownership Figure 24 Security Screen Revision 1 0 75 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS 6 5 2 12 Server Management Screen Tab The Server Management screen allows the user to configure several server management features This screen also provides an access point to the screens for configuring console redirection displaying system information and controlling the BMC LAN configuration To access this screen from the Main screen or other top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Server Management screen is selected Advanced Security Server Management 211401 Assert on SERR Enabled Disabled Assert NMI on PERR Enabled Disabled Resume on AC Power Loss Stay Off Last state Power On Clear System Event Log Enabled Disabled FRB 2 Enable Enabled Disabled O S Boot Watchdog Timer Enabled Disabled O S Boot Watchdog Timer Policy Power off Reset O S Boot Watchdog Timer Timeout 5 minutes 10 minutes 15 minutes 20 minutes Plug amp Play BMC Detection Enabled Disabled gt Console Redirection gt System Information gt BMC LAN Configuration Figure 25 Server Management Screen S1200BTL 76 Revisi
149. rd To assist in troubleshooting a system hang during the POST process you can use the diagnostic LEDs to identify the last POST process executed Later in POST the BIOS displays POST Error Codes on the video monitor in the Error Manager display Any POST Error Codes are automatically logged in the event log The Diagnostic LEDs are a set of LEDs found on the back edge of the server board The exact implementation may differ for some boards but in general there are 8 Diagnostic LEDs which form a 2 hex digit 8 bit code read left to right as facing the rear of the server An LED which is ON represents a 1 bit value and an LED which is OFF represents a 0 bit value The LED bit values are read as Most Significant Bit to the left Least Significant Bit to the right In the following example the BIOS sends a value of ACh to the diagnostic LED decoder The LEDs are decoded as follows Table 57 POST Progress Code LED Example Upper Nibble LEDs Lower Nibble LEDs MSB LSB LED 7 LED 6 LED 5 LED 4 LED 3 LED 2 LED 1 LED 0 8h 4h 2h th 8h 4h 2h th ON sidus OFF ON OFF ON OFF ON OFF 1 0 1 0 1 1 0 0 Results Ah Ch Upper nibble bits 1010b Ah Lower nibble bits 1100b Ch the two are concatenated as ACh Table 58 POST Progress Codes Diagnostic LED Decoder O On X Off Progress Code Upper Nibble Lower Nibble Description MSB 8h 4h 2h 1h
150. re and provides high performance mouse tracking and synchronization It allows remote viewing and configuration in pre boot POST and BIOS setup once BIOS has initialized video Other attributes of this feature include Encryption of the redirected screen keyboard and mouse Compression of the redirected screen 4 2 2 1 Remote Console The Remote Console is the redirected screen keyboard and mouse of the remote host system To use the Remote Console window of your managed host system the browser must include a Java Runtime Environment plug in If the browser has no Java support such as with a small handheld device the user can maintain the remote host system using the administration forms displayed by the browser 36 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Platform Management The Remote Console window is a Java Applet that establishes TCP connections to the Integrated BMC The protocol that is run over these connections is a unique KVM protocol and not HTTP or HTTPS This protocol uses ports 7578 for 5120 for CDROM media redirection and 5123 for Floppy USB media redirection both supporting encryption 4 2 2 2 Performance The remote display accurately represents the local display The feature adapts to changes to the video resolution of the local display and continues to work smoothly when the system transitions from graphics to text or vice versa The responsiveness may be sl
151. rm setup 6 5 1 BIOS Setup Operation The BIOS Setup Utility has the following features Localization The Intel Server Board BIOS is only available in English However BIOS Setup uses the Unicode standard and is capable of displaying data and input in Setup fields in all languages currently included in the Unicode standard Console Redirection BIOS Setup is functional via Console Redirection over various terminal emulation standards Setup screens are designed to be displayable an 80 character x 24 line format in order to work with Console Redirection although that screen layout should display correctly on any format with longer lines or more lines on the screen Password protection BIOS Setup may be protected from unauthorized changes by setting an Administrative Password in the Security screen When an Administrative Password has been set all selection and data entry fields in Setup except System Time and Date are grayed out and cannot be changed unless the Administrative Password has been entered 50 Revision 1 0 Intel order number G13326 003 Intel Server Board 51200 TPS BIOS User Interface Note If an Administrative Password has not been set anyone who boots the system to Setup has access to all selection and data entry fields in Setup and can change any of them 6 5 1 1 Setup Page Layout The Setup page layout is sectioned into functional areas Each occupies a specific area of the screen and ha
152. rver Board S1200BT 5 Connector Header Locations and Pin outs Pin Name Pin Name 17 GND 18 RXDO 19 GND 20 1 21 GND 22 RXD 2 23 GND 24 RXD 25 GND 26 TX 27 GND 28 CLK 29 GND 30 7 3 2 LPC IPMB Header Table 23 LPC IPMB Header Pin out J1H5 scription scription Bi SMB IPMB 5VSB DAT Integrated BMC IMB 5V standby data line GND 10 LOND Integrated Ground BUC WE Yser IMB 5V standby clock line 7 3 3 HSBP Header Table 24 HSBP Header Pin out J1J2 Pin Signal Name 1 SMB_HSBP_5V_DAT 2 GND 3 SMB_HSBP_5V_CLK 4 FM HSBP ADD C2 7 3 4 SGPIO Header Table 25 SGPIO Header Pin out J1J3 on S1200BTL and J2J2 on S1200BTS Pin Signal Name Description 1 SGPIO CLOCK SGPIO Clock Signal 2 SGPIO LOAD SGPIO Load Signal 3 GND 4 SGPIO DATAOUTO SGPIO Data Out 5 SGPIO_DATAOUT1 SGPIO Data In 7 4 Front Control Panel Connector The server board provides a 24 pin SSI front panel connector J1C1 for use with Intel and third party chassis The following table provides the pin out for this connector Table 26 Front Panel SSI Standard 24 pin Connector Pin out J1C1 on S1200BTL or J1C2 on S1200BTS Revision 1 0 93 Intel order number G13326 003 Connector Header Locations and Pin ou
153. s Displays one of the following e Single Channel DIMMs are operating in Single Channel mode This is the configuration when only one channel is populated with DIMMs e Dual Channel Symmetric DIMMs are operating in Dual Channel Symmetric mode This is the configuration when both channels are identically populated with DIMMs Intel Flex DIMMs are configured according to Intel Flex Memory Technology where part of the memory is in Dual Channel Symmetric mode and part in Dual Channel Asymmetric mode This is the configuration when both channels are populated but with unequal amounts of memory Current Memory Speed Option Values 1066 1333 Help Text None Comments Displays the speed in MT s at which the memory is currently running Memory Operating Speed Selection Option Values Auto 1066 1333 Help Text Force specific Memory Operating Speed or use Auto setting Comments Displays the state of each DIMM socket present on the board Each DIMM socket field reflects one of the following possible states DIMM_A1 DIMM_A2 DIMM_B1 DIMM_B2 Option Values Installed Not Installed Failed Disabled Help Text lt None gt Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface Comments Information only for 51200 boards Displays the state of each DIMM socket present on the board Each DIMM socket field reflects one of the following possible states e Insta
154. s dedicated functionality The following table lists and describes each functional area The Setup page is designed to a format of 80 x 24 24 lines of 80 characters each The typical display screen in a Legacy mode or in a terminal emulator mode is actually 80 characters by 25 lines but with line wrap enabled which it usually is the 25th line cannot be used with the Setup page Table 14 BIOS Setup Page Layout Functional Area Description Title Bar The title bar is located at the top of the screen and displays the title of the form page the user is currently viewing It may also display navigational information Setup Item List The Setup Item List is a set of control entries and informational items The list is displayed in two columns For each item in the list a prompt string or label string occupies the left column of the list and the right column contains either a data display a data input field or a multiple choice field The operator navigates up and down the right hand column through the available input or choice fields A Setup Item may also represent a selection to open a new screen with a further group of options for specific functionality In this case the operator navigates to the desired selection and presses Enter to go to the new screen Item Specific Help Area The Item specific Help area is located on the right side of the screen and contains help text for the highlighted Setup Item Help information
155. s identical and defined in the following table Table 31 6Gb s SATA Connector Pin Out Pin Signal Name Table 32 3Gb s SATA Connector Pin out m p e e Ground O SATA SAS_TX_P_C Positive side of transmit differential pair SATA SAS TX N C Negative side of transmit differential pair Ground O Ground 6 RX P C Positive side of receive differential pair 7 5 4 SAS Connectors The Intel Server Board S1200BTL provides one SAS connector The pin configuration is identical and defined in the following table Revision 1 0 97 Intel order number G13326 003 Connector Header Locations and Pin outs Intel amp Server Board 51200 TPS Table 33 SAS Connector Pin out J2H1 Groun eo 4 Ground SATA SAS N C Negative side of receive differential pair 6 _ SATA SAS RX P C Positive side of receive differential pair 7 5 5 Serial Port Connectors The server board provides one external DB9 Serial A port J8A1 and one internal 9 pin serial B header J1B2 The following tables define the pin outs Table 34 External Serial A Port Pin out J8A1 6 SPA DSR DSR dala set ready 8 SPA CTS 9 SPARI RI Ring Indicate 22 75 2 1 Table 35 Internal 9 Serial Header Pin out J1B2 5 SOUT N TXD Transmit data SPB CTS CTS clear to send SP
156. s or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright Intel Corporation 2011 Revision 1 0 Intel order number G13326 003 Table of Contents Intel amp Server Board 51200 TPS Table of Contents T euadere c cde rers 1 1 1 1 1 2 Server Board Use Disclaimer 1 2 m 2 2 1 Intel Server Board S1200BT Feature Set 2 2 2 Server Board Laygut eR Eun etu e P Rei ue a RU 4 2 2 1 Server Board Connector and Component 5 2 2 2 Intel Server Board S1200BTL Mechanical Drawings 8 22 33 Server Board Rear LO Layoutl 14 3 Functional Architecture sisisi edie 15 3 1 Processor SubD SyslolTi eir eb hc 16 3 1 1 Intel Xeon Processor E3 1200 16 3 1 2 Intel Core Processor i3 2100 Series 17 3 1 3 Intel Turbo Boost 4 c bn 17 3 2 Memory SUDSYSIOM se oe ecc ua Ra hk 17 3 2 1 Memory SUDDOLTOG rt Pr eet p 18 3 2 2 Post Erro God6s p et re tec e t
157. settings Comments Selection only Position to this line and press the Enter key to go to the Mass Storage Controller Configuration group of configuration settings Serial Port Configuration Option Values None Help Text View Configure serial port information and settings Comments Selection only Position to this line and press the Enter key to go to the Serial Port Configuration group of configuration settings USB Configuration Option Values None Help Text View Configure USB information and settings Comments Selection only Position to this line and press the Enter key to go to the USB Configuration group of configuration settings PCI Configuration Option Values None Help Text View Configure PCI information and settings Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 5 BIOS User Interface Comments Selection only Position to this line and press the Enter key to go to the PCI Configuration group of configuration settings 7 System Acoustic and Performance Configuration Option Values None Help Text View Configure system acoustic and performance information and settings Comments Selection only Position to this line and press the Enter key to go to the System Acoustic and Performance Configuration group of configuration settings 6 5 2 4 Processor Configuration The Processor Configuration screen displays the processor identification and microcode
158. t deactivated by local system input unless the feature is disabled locally 4 2 2 6 Usage As the server is powered up the remote KVM session displays the complete BIOS boot process The user is able interact with BIOS setup change and save settings as well as enter and interact with option ROM configuration screens At least two concurrent remote KVM sessions are supported It is possible for at least two different users to connect to same server and start remote KVM sessions Revision 1 0 37 Intel order number G13326 003 Platform Management Intel Server Board 51200 TPS 4 2 3 Media Redirection The embedded web server provides a Java applet to enable remote media redirection This may be used in conjunction with the remote KVM feature or as a standalone applet The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD ROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears just like a local device to the server allowing system administrators or users to install software including operating systems copy files update BIOS and so on or boot the server from this device The following capabilities are supported operation of remotely mounted devices is independent of the local devices on the server Both remote and local devices are useable in parallel Either IDE CD ROM floppy or USB devices can be
159. t setup is running in Administrator or User With no passwords set Administrator is the default mode Platform ID Option Values Platform ID Help Text None Comments Information only Displays the Platform ID for the board on which the BIOS is executing POST BIOS Version Option Values Current BIOS version Help Text None Comments Information only The version information displayed is taken from the BIOS ID String with the timestamp segment dropped off The segments displayed are Platform Identifies whether this is a plattorm BIOS 86B Identifies this BIOS as being an EPSD Server BIOS Xx Major Revision level of the BIOS yy Release Revision level for this BIOS 2222 Release Number for this BIOS Build Date Option Values Date and time when the currently installed BIOS was created built Help Text None Comments Information only The time and date displayed are taken from the timestamp segment of the BIOS ID String Total Memory Option Values Amount of memory installed in the system Help Text None Comments Information only Displays the total physical memory installed in the system in MB or GB The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs Quiet Boot Option Values Enabled Disabled Help Text Revision 1 0 57 Intel order number G13326 003 BIOS User Interface Intel Server Board 51200 TPS Enabled Display t
160. t within the processor s Revision 1 0 67 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS Note Modifying this setting may affect system performance Comments System performance is usually best with Hardware Prefetcher Enabled In certain unusual cases disabling this may give improved results 21 Adjacent Cache Line Prefetch Option Values Enabled Disabled Help Text Enabled Cache lines are fetched in pairs even line odd line Disabled Only the current cache line required is fetched Note Modifying this setting may affect system performance Comments System performance is usually best with Adjacent Cache Line Prefetch Enabled In certain unusual cases disabling this may give improved results 6 5 2 5 Memory Configuration The Memory Configuration screen allows the user to view details about the DDR3 DIMMs that are installed as system memory To access this screen from the Main screen select Advanced Memory Configuration To move to another screen press the Esc key to return to the Advanced screen then select the desired screen Advanced Memory Configuration Screen Field Descriptions Total Memory Total Physical Memory Installed in System Effective Memory Total Effective Memory Current Configuration Single Channel Dual Channel Symmetric Intel Flex Current Memory Speed 1066 1333 Memory Operating Speed Selection Auto 1066 1333 DIMM Information
161. tability is ensured at the maximum and minimum loads as applicable 10 3 8 Common Mode Noise The Common Mode noise on any output does not exceed 350 mV pk pk over the frequency band of 10 Hz to 20 MHz measurement is made across a 1000 resistor between each of the DC outputs including ground at the DC power connector and chassis ground power subsystem enclosure The test setup uses a FET probe such as Tektronix model P6046 or equivalent 10 3 9 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in the following table This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors 10 F tantalum capacitor is placed in parallel with a 0 1 F ceramic capacitor at the point of measurement Table 51 Ripple and Noise 50 mVp p 50 mVp p 120 mVp p 120 mVp p 50 mVp p 10 3 10 Timing Requirements The timing requirements for the power supply operation are as follows 114 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS Design and Environmental Specifications The output voltages must rise from 10 to within regulation limits Tyout rise within 5 ms to 70 ms except for 5 VSB in which case it is allowed to rise from 1 0 ms to 25 ms The 3 3 V 5 V and 12 V output voltages should start to rise approximately at the same time All outputs must rise monotonically The 5 V output must be greater than the 3 3 V output dur
162. te IPMI methods for the purpose of sending to an Intel engineer for an enhanced debugging capability The files are compressed encrypted and password protected The file is not meant to be viewable by the end user but rather to provide additional debugging capability to an Intel support engineer 40 Revision 1 0 Intel order number G13326 003 Intel Server Board 51200 TPS Platform Management A list of data that may be captured using this feature includes but is not limited to 1 Platform sensor readings This includes all readable sensors that can be accessed by the Integrated BMC firmware and have associated SDRs populated in the SDR repository This does not include any event only sensors All BIOS sensors and some Integrated BMC and ME sensors are event only meaning that they are not readable using an IPMI Get Sensor Reading command but rather are used just for event logging purposes 2 SEL The current SEL contents are saved in both hexadecimal and text format 3 CPU memory register data useful for diagnosing the cause of the following system errors CATERR ERR 2 SMI timeout PERR and SERR The debug data is saved and timestamped for the last 3 occurrences of the error conditions a error registers b MSR registers c MCH registers 4 Integrated BMC configuration data 5 Integrated BMC firmware debug log a k a SysLog Captures firmware debug messages 4 2 6 Data Center Management Interfac
163. ted by the Integrated Baseboard Management Controller Integrated BMC firmware This section explains the advanced management features supported by the BMC firmware Error Reference source not found lists basic and advanced feature support Individual features may vary by platform For more information refer to Appendix D Table 11 Basic and Advanced Management Features IPMI 2 0 Feature Support In circuit BMC Firmware Update FRB2 j FRB 2 Chassis Intrusion Detection Hot Swap Fan Support E mail Alerting Intel Intelligent Power Node Manager Support Basic management features provided by Integrated BMC Advanced management features available with optional Intel Remote Management Module 4 Intel Intelligent Power Node Manager Support requires PMBus compliant power supply Revision 1 0 35 Intel order number G13326 003 Platform Management Intel Server Board 51200 TPS 4 2 1 Enabling Advanced Management Features The Advanced management features are to be delivered as part of the Integrated BMC firmware image The Integrated BMC s baseboard SPI flash contains code data for both the Basic and Advanced features An optional add in card Intel RMM4 lite is used as the activation mechanism When the Integrated BMC firmware initializes it attempts to access the Intel RMM4 lite If the attempt to access Intel RMM4 lite is successful then the Integrated BMC activates the advanced features Advanced manageabilit
164. tely as Build Date 51200 86 01 00 0003 For the SMBIOS Type 0 BIOS Version field the full BIOS ID string is used including the complete timestamp 6 1 1 3 OEM BIOS Differentiation Support There is an optional OEM Extension segment which can be added by an OEM customer to distinguish an OEM specific edited version of the BIOS from a standard Intel version This OEM Extension will never be present in a standard BIOS supplied directly by Intel This can only be done using a restricted distribution BIOS utility available though Technical Marketing OEM support channels 6 2 HotKeys Supported During POST Certain HotKeys are recognized during POST A HotKey a key or key combination that is recognized as an unprompted command input that is the operator is not prompted to press the HotKey and typically the HotKey will be recognized even while other processing is in progress The Server Board BIOS recognizes a number of HotKeys during POST After the OS is booted HotKeys are the responsibility of the OS and the OS defines its own set of recognized HotKeys Following are the POST HotKeys with the functions they cause to be performed 48 Revision 1 0 Intel order number G13326 003 Intel amp Server Board 51200 TPS BIOS User Interface 6 3 Table 13 POST HotKeys Recognized Pop up BIOS Boot Menu Network boot POST Logo Screen Diagnostic Screen The Logo Screen Diagnostic Screen appears in one of two forms
165. the Serial A COM 1 and Serial B COM2 ports To access this screen from the Main screen select Advanced Serial Port Configuration To move to another screen press the Esc key to return to the Advanced screen then select the desired screen Revision 1 0 71 Intel order number G13326 003 BIOS User Interface Intel amp Server Board 51200 TPS Figure 20 Serial Port Configuration Screen 6 5 2 8 USB Configuration The USB Configuration screen allows the user to configure the USB controller options To access this screen from the Main screen select Advanced USB Configuration To move to another screen press the Esc key to return to the Advanced screen then select the desired screen 72 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS BIOS User Interface Advanced USB Configuration Detected USB Devices USB Controller Enabled Disabled Legacy USB Support Enabled Disabled Auto Port 60 64 Emulation Enabled Disabled Make USB Devices Non Bootable Enabled Disabled USB Mass Storage Device Configuration Device Reset timeout 10 seconds 20 seconds 30 seconds 40 seconds Mass Storage Devices a orage Auto Floppy Forced FDD Hard Disk CD ROM Figure 21 USB Configuration Screen 6 5 2 9 PCI Configuration The PCI Configuration screen allows the user to configure the PCI memory space used for onboard and add in adapters configure video options and configure onboard adapter opti
166. the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits 10 2 Board level Calculated MTBF This section provides results of MTBF Mean Time Between Failures testing done by a third party testing facility MTBF is a standard measure for the reliability and performance of the board under extreme working conditions The MTBF was measured at 20000 hours at 35 degrees Celsius Please go to http www intel com support motherboards server to get the updated MTBF report for Intel Server Board S1200BT family 10 2 1 Processor Power Support The server board supports the Thermal Design Power TDP guideline for Intel Xeon processor The Flexible Motherboard Guidelines FMB was also followed to help determine the Revision 1 0 111 Intel order number G13326 003 Design and Environmental Specifications Intel Server Board 51200 TPS suggested thermal and current design values for anticipating future processor needs The following table provides maximum values for Icc TDP power and for t
167. ts Intel amp Server Board 51200 TPS P3V3 AUX NC PWR LED P3V3 9 HDD ACT N PWR BIN N GND FP RET BTN GND FP ID BTN N PU FM SIO TEMP SENSOR FP BTN N Combined system BIOS and the Integrated BMC support provide the functionality of the various supported control panel buttons and LEDs The following sections describe the supported functionality of each control panel feature Note Control panel features are also routed through the bridge board connector at location J1C1 as is implemented in Intel Server Systems configured using a bridge board and a hot swap backplane 7 4 1 Power Button The BIOS supports a front control panel power button Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset It is monitored by the Integrated BMC and does not directly control power on the power supply Power Button Off to On The Integrated BMC monitors the power button and the wake up event signals from the chipset A transition from either source results in the Integrated BMC starting the power up sequence Since the processor are not executing the BIOS does not participate in this sequence The hardware receives the power good and reset signals from the Integrated BMC and then transitions to an ON state Power Button On to Off Operating system absent The System Control Interrupt 5 1 is masked The BIOS sets up the power b
168. up the server Perform the Integrated BMC firmware update procedure as documented in the README TXT file that is included in the given Integrated BMC firmware update package After successful completion of the firmware update process the firmware update utility may generate an error stating that the Integrated BMC is still in update mode Power down and remove the AC power cord Open the server chassis Move jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server Note Normal Integrated BMC functionality is disabled with the Force Integrated BMC Update jumper set to the enabled position The server should never be run with the Integrated BMC Force Update jumper set in this position This jumper setting should only be used when the standard firmware update process fails This jumper should remain in the default disabled position when the server is running normally 8 3 MEForce Update Jumper When performing the standard ME force update procedure the update utility places the ME into an update mode allowing the ME to load safely onto the flash device In the unlikely event ME firmware update process fails due to ME not being in the proper update state the server board provides an Integrated BMC Force Update jumper which forces the ME into the proper update state The following procedure should be completed in
169. utton event to generate an SMI and checks the power button status bit in the ACPI hardware registers when an SMI occurs If the status bit is set the BIOS sets the ACPI power state of the machine in the chipset to the OFF state The Integrated BMC monitors power state signals from the chipset and de asserts PS PWR ON to the power supply As a safety mechanism if the BIOS fails to service the request the Integrated BMC automatically powers off the system in 4 to 5 seconds Power Button On to Off Operating system present If an ACPI operating system is running pressing the power button switch generates a request using SCI to the operating system to shut down the system The operating system retains control of the system and the operating system policy determines the sleep state into which the system transitions if any Otherwise the BIOS turns off the system 94 Revision 1 0 Intel order number G13326 003 Intel Server Board S1200BT TPS Connector Header Locations and Pin outs 7 4 2 Reset Button The platform supports a front control panel reset button Pressing the reset button initiates a request forwarded by the Integrated BMC to the chipset The BIOS does not affect the behavior of the reset button 7 4 3 System Status Indicator LED The Intel Server Board S1200BTL has a system status indicator LED on the front panel This indicator LED has specific states and corresponding interpretation as shown in the following table T
170. x9A OXXO OXOX DXE USB start Ox9B O X X O USB reset 0x9C O XX O O O X X DXE USB detect 0x9D O X X O O O XO DXE USB enable OxA1 O X O X X X X O DXE IDE begin 0xA2 O X O X X X O X DXE IDE reset 0 O X O X X XO O DXE IDE detect 0 4 O X O X X O X X DXE IDE enable 9 OXOX O X X O DXE verifying SETUP password OxAB OXOX DXE SETUP start OxAC O X O X O O X X DXE SETUP input wait OxAD OXOX OO XO DXE Ready to Boot OXOX DXE Legacy Boot OxAF O X O X OO OO DXE Exit Boot Services 0xB0 O XO O X X X X RT Set Virtual Address Map Begin Revision 1 0 131 Intel order number G13326 003 Appendix C POST Code Diagnostic LED Decoder Intel amp Server Board S1200BT TPS Diagnostic LED Decoder O On X Off Progress Code Upper Nibble Lower Nibble Description MSB 8h 4h 2h dh 8h 4h 2h 1h LSB 7 6 5 4 3 2 1 0 0 1 X X X O RT Set Virtual Address Map End 0xB2 O XO O X X O X DXE Legacy Option ROM init 0xB3 O XO O X XO O DXE Reset system 0xB4 O XO O X O X X DXE USB Hot plug 0xB5 PCI BUS Hot plug OxB6 X O O X DXE NVRAM cleanup 0xB7 DXE Configuration Reset 0x00 X X X X X X X X INT19 BIOS Recovery O OOO X X X X PEIM which detected forced Recovery OxFO vt condition OxF1 O OOO X X X O PEIM which detected User Recovery condition 0xF2 OO OO X X O X Recovery PEIM Recovery started OxF3 O
171. y features are supported over all NIC ports enabled for server manageability This includes baseboard NICs as well as the LAN channel provided by the optional Dedicated NIC add in card There are two RMM4 SKUs Intel RMM4 lite Advance features enabled but no dedicated management NIC Intel RMM4 Advance features enabled with a dedicated management NIC It is a package that contains two modules Intel amp Dedicated Server Management NIC and Intel RMM4 lite 4 2 2 Keyboard Video and Mouse KVM Redirection The BMC firmware supports keyboard video and mouse redirection KVM over LAN This feature is available remotely from the embedded web server as a Java applet This feature is enabled when the Intel RMMA is present The client system must have a Java Runtime Environment JRE version 5 0 or later to run the KVM or media redirection applets The Integrated BMC supports an embedded KVM application Remote Console that can be launched from the embedded web server from a remote console USB1 1 or USB 2 0 based mouse and keyboard redirection are supported It is also possible to use the KVM redirection KVM r session concurrently with media redirection media r This feature allows a user to interactively use the keyboard video and mouse KVM functions of the remote server as if the user were physically at the managed server The KVM redirection feature automatically senses video resolution for best possible screen captu
172. y is completely software transparent permitting current and legacy software to operate normally 3 4 2 PCI Express Interface The PCI E configurations for each SKU are defined below Intel Server Board S1200BTL One PCI E x16 connector to be used as a x8 link two PCI E x8 connectors to be used as a x4 link and one SAS module connector to be used as a x4 link connected to the PCI E ports of the processor One PCI E x8 connector to be used as x4 link connected to the PC E ports of PCH Server Board S1200BTS One PCI E x16 connector to be used as x8 link one PCI E x8 connectors to be used as a x8 link connected to the PCI E ports of the processor One PCI E x8 connector to be used as x4 link connected to the PCI E ports of PCH There is one 32 bit 33 MHz 5 V PCI slot common on both SKUs Compatibility with the PCI addressing model is maintained to ensure all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial recovered clock speed of 1 25 GHz results in 2 5 Gb s each direction which provides a 250 MB s communications channel in each direction 500 MB s total This is close to twice the data rate of classic PCI It is a fact that 8b 10b encoding is used accounts for the 250 MB s where quick calculations would imply 300 MB s The external graphics ports support 5 0 GT s speed as well Operating at 5 0 GT s results i

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