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Elixir M2F2G64CB88B7N-CG memory module

1. 51 50 5950 2954 paso M pas4 M DMO A 1 DM4 M DM CS 095 Das DM CS Das Das DM CS DOS Das DM CS DOS Das N voo DQ32 N oo VO 0 pai N 1 VO 1 pass 1 VO 1 Daz 2 yo 2 DQ34 N 02 Vo 2 DO yo 3 08 DQ35 N os 04 012 04 N 104 VO 4 pass N 04 VO 4 pas N 05 yo 5 DQ37 N 05 Vo 5 N 106 yo 6 pass 06 VO 6 N 107 za Vo 7 za 5939 vo7 zo Ex O7 za 5951 DAS M DOS 0955 DM1 1 DM5 DM CS 005 Dos DM CS DOS 005 DM CS DOGS Das DM CS DOS DOS N yo o DQ40 N oo VO 0 Dae N 1 VO 1 DQ41 1 VO 1 DQ10 N 02 2 0042 02 2 911 D1 09 DQ43 os D5 vO3 D13 0912 04 VO 4 0944 N VO4 VO 4 DQ13 N 5 yo 5 DQ45 N 05 Vo 5 0914 M 6 00946 6 0915 07 zo Ex Vo 7 za 2947 N o7 zo Ex VO7 za 5952 E Dase n 2 pase M t DM2 1 DM6 1 DM CS DOS Das DM CS 005 Das DM CS Das DAS DM CS Das pais N oo yo o DQ48 N oo VO 0 DQ17 N 1 VO 1 DQ49 N
2. SDRAMs 00 07 CKEO A 13 0 p WE SDRAMs 00 07 eu Barm O 00 ODT SDRAMs 00 07 3 CK SDRAMs 00 07 ADRS SDRAMs 00 07 SDRAM RESET _____________ RESET SDRAMs 00 07 EWW Vop Notes 1 DQ to I O wiring is shown as recommended but may be changed DQ DQS DQS ODT DM CKE S relationships must be maintained as shown For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 1 4 One SPD exists per module wry REV 1 1 5 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 4GB 2 Ranks 256Mx8 DDR3 SDRAMs Celixir
3. 4 30 4 25 00 0 2 30 00 0 5 0 15 5 175 47 00 in ue Detail A 71 00 ais 1 27 04 5 00 Detail Detail 2 50 eo e 0 80 0 05 me SO 0010000 DEC 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 1 24 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Package Dimensions M2F4G64CB8HB5N 4GB 2 Ranks 256 8 DDR3 SDRAMs FRONT 133 35 0 15 gt SIDE wo i 4 00 Max s e e E Detail A oe Detail B 5 175 47 00 71 00 a BACK Detail A Detail B 250 o 0 80 0 05 EE 0000 010000 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 1 25 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and sp
4. ODTH4 nCK with write command and BC4 ODTHA4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay 2 tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON es RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Pos o or Wills Leveling Tinin Ss X B a First DQS DQS rising after tWLMRD write leveling mode is programmed DAS DAS delay after write leveling mode is programmed IWLDOSEN Sp ry T Write leveling setup time from rising CK CK tWLS 245 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS 245 crossing to rising crossing Write leveling output delay __ 05 7 8 Write leveling output error REV 1 1 16 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1333MHz DDR3 1333 Parameter Symbol Units ee Glock Timing Minimum Glock Cycle Time DLL of
5. 0 15 2 0 15 V 1 2 5 Reference Voltage for DQ DM 0 49 x VDD 0 51 xVDD 0 49xVDD 0 51xVDD 0 49xVDD O51xVDD V 3 4 Inputs Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS is 350 mV peak to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 1 10 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON m m 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 elixi r Unbuffered DDR3 SDRAM DIMM Operating Standby and Refresh Currents 0 85 Von 1 5V 0 075V 2GB 1 Rank 256 8 DDR3 SDRAMs m PC3 8500 PC3 10600 PC3 12800 Symbol Parameter Condition BE CG CDI Unit IDDO Operating One Bank Active Precharge Current 577 579 609 mA IDD1 Operating One Bank Active Read Precharge Current 725 750 790 mA IDD2PO Precharge Power Down Current Slow Exit 33 48 51 mA IDD
6. 1 VO 1 pais 02 2 950 02 Vo 2 919 N 03 02 010 951 o3 06 014 2920 04 VO 4 DQ52 N 04 VO 4 DQ21 N 5 yo 5 953 N 05 Vo 5 0922 N 6 0954 6 0923 107 za Vo 7 za 2055 7 zo X VO7 za 5953 0057 2 Dass DQs7 t DM3 1 DM7 DM CS Das Das DM CS bas pas DM CS DOS 005 DM CS 005 DOS DQ24 N oo voo pass N oo VO 0 DQ25 1 VO 1 DQ57 1 VO 1 DQ26 N 02 yo 2 pass N 02 Vo 2 DQ27 N 03 D3 Di Dass N 03 D7 015 2928 04 VO 4 paso N 04 VO 4 DQ29 N 05 yo 5 DQ61 05 Vo 5 paso N 6 yo 6 DQ62 N 6 VO 6 DQ31 N 107 za Vo 7 za 2963 w 7 zo Ex O7 za DDR3 Vooso SPD SDRAM Voo Vooa 00 015 CKE 1 0 A 13 0 Vaeroa gt 00 015 RAS CAS WE Va Vss 5 00 015 ODT 1 0 BA 2 0 S 1 0 VagEcA 00 015 2 gt BA0 BA2 SDRAMs 00 015 1 SDRAMs 00 015 DDR3 RAS p RAS SDRAMs 00 015 SDRAM TAS TAS SDRAMs 00 015 ____ _ WE SDRAMs 00 015 oR FW Voo SDRAMs 00 07 CKE1 gt CKE SDRAMs 08 015
7. NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Unbuffered DDR3 SDRAM DIMM Part Number M2F2G64CB88B7N BE M2F2G64CB88B7N CG M2F2G64CB88B7N DI M2F4G64CB8HB5N BE M2F4G64CB8HB5N CG M2F4G64CB8HB5N DI M2F2G64CB88BHN BE M2F2G64CB88BHN CG M2F2G64CB88BHN DI M2F4G64CB8HB9N BE M2F4G64CB8HB9N CG M2F4G64CB8HB9N DI Pin Description DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1066 DDR3 1333 0083 1600 0083 1066 0043 1333 0043 1600 0083 1066 0083 1333 0043 1600 Speed PC3 8500 533MHz 1 875ns 9 CL 7 PC3 10600 667MHz 1 5ns 9 CL 9 PC3 12800 800MHz 1 25ns CL 11 PC3 8500 533MHz 1 875ns 9 CL 7 PC3 10600 667MHz 1 5ns 9 CL 9 PC3 12800 800MHz 1 25ns 9 CL 11 PC3 8500 533MHz 1 875ns 9 CL 7 PC3 10600 667MHz 1 5ns 9 CL 9 PC3 12800 800MHz 1 25ns CL 11 PC3 8500 533MHz 1 875ns 9 CL 7 PC3 10600 667MHz 1 5ns 9 CL 9 PC3 12800 800MHz 1 25ns 9 CL 11 Pin Name Description Pin Name CKO CK1 Clock Inputs positive line 000 0063 CK1 Clock Inputs negative line DQS0 DQS8 CKEO CKE1 Clock Enable DQS0 DQS8 RAS Row Address Strobe DMO DM8 CAS Column Address Strobe EVENT WE Write Enable RESET S0 S1 Chip Selects Vrerva VnEFCA 9 A11 A13 A15 Address Inputs VppsPp A10 AP Address Input Auto Precharge
8. SA1 A12 BC Address Input Burst Chop Vtt BA0 BA2 SDRAM Bank Address Inputs Vss ODTO ODT1 Active termination control lines Vop SCL Serial Presence Detect Clock Input NC SDA Serial Presence Detect Data input output REV 1 1 10 2010 Celixir Organization Power Leads Note 256Mx64 512Mx64 1 5V Gold 256Mx64 512Mx64 Description Data input output Data strobes Data strobes complement Data Masks Temperature event pin Reset pin Input Output Reference SPD and Temp sensor power Serial Presence Detect Address Inputs Termination voltage Ground Core and I O power No Connect NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON _ 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 elixi r Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 121 Vss 31 0025 151 Vss 61 2 181 910 0041 211 Vg DM5 2 122 004 32 Vs 152 a 62 182 Vo 92 212 00514 TDQS14 ER NC DaS12 e NC 3 000 123 005 0053 153 63 1 183 V 93 DOS 213 DOST 150512 159514 4 001 124 Vss 34 0053 154 Vss 64 CKiNC 184 CKO 94 0055 214 Vss 5 125 erc un 35
9. 155 0030 65 185 CKO 95 Vg 215 0046 6 0950 126 prd 36 00926 156 0031 66 Vo 186 96 0042 216 0047 7 0080 127 Vss 37 0027 157 Vss 67 187 ud 97 DQ43 217 Vss 8 Va 128 DQ6 38 158 CBANC 68 P n 188 AO 98 Va 218 0052 Daz 129 DQ7 39 CBO NC 159 CB5 NC 69 Vo 189 V 99 0048 219 0053 10 003 130 Vss 40 CB1 NC 160 Vss 70 A10 AP 190 100 0049 220 Vss DM6 11 Ves 131 0012 41 161 DM amp DQS17 74 4910 101 Vas 221 00815 TDQS17 NC TDOSIS NC DOS17 a y NG 12 008 132 42 0058 162 72 Vo 192 RAS 102 0056 222 00515 TDOST TDQS15 13 DQ9 133 Vss 43 0098 163 Vss 73 WE 193 50 103 0056 223 Vss 14 134 44 164 CB6NC 74 194 104 Vs 224 0054 15 DOSI 135 45 2 165 7 75 V 195 105 0050 225 0055 16 0051 136 Vss 46 CB3 NC 166 Vss 76 196 A13 106 DQ51 226 Vss 417 Vs 137 0014 47 167 NC TEST 77 197 Vpp 107 Vss 227 0060 18 0010 188 0015 48 168 RESET 78 Vp 198 S3 NC 108 0056 228 0061 19 0011 139 Vss 49 169 CKEiI NC 79 S2NC 199 Vs 109 0057 229 Vss DM7 20 Vss 140 0020 50 CKEO 170 Voo 80 Va 200 DQ36 110 Vss 230 DQS16 TDQS16 NC 21 0016 141 51 171 A15NC 81 0032 201 00937 111 0057 231 DOSTS 150516 22 0017 142 Um 52 2 172 14 82 DQ33 202 Vs 112 0087 232 Vss DM4 23 143 53 ERR 173 Voo 83 Va 203 00513 113 Vss 233 0062 NG TDQS13 Ee NC DOS71 2 NO 24 DOSZ 144 NODQSI 174 A250
10. SA2 Input Address pins used to select the Serial Presence Detect and Temp sensor base address EVENT Output The EVENT pin is reserved for use to flag critical module temperature RESET Input This signal resets the DDR3 SDRAM REV 1 1 4 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 2GB 1 Rank 256Mx8 DDR3 SDRAMs 50 0050 M 54 M paso 004 DQS4 N T DMO DM4 M 34 DM CS Das 005 DM CS Das Das Dao N 0 2932 100 N 101 DQ33 N VO 1 Daz N vo2 N 4 1 02 JN 103 DO DQ35 M 103 D4 DQ4 N 104 pass 1 04 pas N 5 2937 N 105 pas N 06 N 1 06 DQ7 N j 107 za DQ39 1 07 za DASI 0055 M pest pass 400 1 DM DM5 DM CS Das 005 DM CS Das Das N 00 DQ40 N oo Dag JN 4 101 2041 N 4 01 DQ10 N j 102 DQ42 N j 102 2911 N 103 D1 DQ43 N 103 D5 DQ12 N 0
11. Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines A9 the column address when sampled at the cross point of the rising edge of CK and falling edge of A10 AP CK In addition to the column address AP is used to invoke autoprecharge operation at the end of A11 Input the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the A12 BC bank to be precharged If AP is low autoprecharge is disabled During a Precharge command A13 A15 cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge 000 0063 Input Data Input Output pins Vbo Vss Supply Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module VREFCA Supply Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor SDA y o A resistor must be connected from the SDA bus line to Vpbsep on the system planar to act as a pull up SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor
12. DQS DQS referenced to Vih ac Vil ac levels 150 7 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQ and DM Input pulse width for each input tDIPW 00 DQS rising edge output access time from rising CK a Strobe Timing Di Di low i QS and DQS low impe iLZ DOS Referenced from RL 1 DQS and DQS high impedance time gramp tHZ DQS Referenced from RL BL 2 lance time Command and Address Timing REV 1 1 10 2010 a Note 19 Note 11 255 a a 0 tCK avg tCK avg 0 o gt to iR o 17 TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2FAG64CB8HB9N 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM DLL locking time tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wee Pts rs Mode Register Set command cycle time o ck tMODmin max 12nCK 15ns Mode Register Set command update delay iMODma to internal read or w
13. LOW pulsewidth baes os o Clock Period siter o 7 7 je S Clock Period Jitter during DLL locking period Cycle to Cycle Period siter tos S Cycle to Cycle Period Jiter during DLL locking period DuyOydedter Ps Cumulative erroracross2cycles as tps S Cumulative error aoross 3oyoles ae tees S Cumulative erroracross4cycles umulative error across 5 cycles tERR 5per ua w Cumulative erroracross6cycles Cumulative error across 7 oyoles tsps S o oe je 175 ps 180 184 o 175 Cumulative error across 12 cycles tERR 12per 188 tERR in 1 0 68 tJIT per min Cumulative error across n 13 14 49 50 cycles tERR nper max 1 0 68In n tJIT per max DataTiming tDS base AC175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQ and DM Input pulse width for each input tDIPW Data setup time to DQS DQS referenced to Vih ac Vil ac levels 00 DQS rising edge output access time from rising CK a Strobe Timing Di Di low i QS and DQS low impe iLZ DOS Referenced from RL 1 DQS and DQS high impedance time gamp tHZ DQS Referenced from RL BL 2
14. row and column count 19 19 19 6 Module minimum nominal voltage 00 00 00 T Module ranks and device DQ count 01 01 01 8 ECC tag and module memory Bus width 03 03 03 9 Fine timebase dividend divisor in ps 52 52 52 10 Medium timebase dividend 01 01 01 11 Medium timebase divisor 08 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 0 13 Reserved 00 00 00 14 CAS latencies supported 1C 3C TE 15 CAS latencies supported 00 00 00 16 Minimum CAS latency time tAAmin 69 69 64 17 Minimum write recovery time tWRmin 78 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 64 19 Minimum Row Active to Row Active delay tRRDmin 3C 30 30 20 Minimum row Precharge delay tRPmin 69 69 64 21 Upper nibble for tRAS and tRC 11 11 11 22 Minimum Active to Precharge delay tRASmin 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin 95 89 7C 24 Minimum refresh recovery delay tRFCmin LSB 00 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 05 26 Minimum internal Write to Read command delay tWTRmin 3C 3C 3C 27 Minimum internal Read to Precharge command delay tRTPmin 3C 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 00 00 29 Minimum four active window delay tFAWmin MSB 2C F0 F0 30 SDRAM device output drivers supported 83 83 83 31 SDRAM device thermal and refresh options 05 05 05 32 Module Thermal Sensor 00 00 00 33 SDRAM Device Type 00 00 00 60 Module height nominal OF OF OF 61 Module thickness Max 01 01 01 62 Raw Card ID referen
15. tCKSREmax t in Valid Clock Requirement before Self Refresh Exit SRX CKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings Exit Power Down with DLL on to any valid command tCKSRX tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax el e nk tCPDEDmin 1 Command pass disable delay tCPDED ICPDEDmin 1 m tCKEmin max 3nCK 5ns CKE minimum pulse width tCKEmax tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmin 1 REV 1 1 21 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2FAG64CB8HB9N _ 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN IWRPDENmin WL 4 tWR tCK avg BL8MRS
16. 2P1 Precharge Power Down Current Fast Exit 104 132 143 mA IDD2Q Precharge Quiet Standby Current 167 204 185 mA IDD2N Precharge Standby Current 182 220 243 mA IDD3P Active Power Down Current 114 144 158 mA IDD3N Active Standby Current 236 231 255 mA IDD4R Operating Burst Read Current 1011 1302 1510 mA IDDAW Operating Burst Write Current 1028 1239 1438 mA IDD5B Burst Refresh Current 1531 1507 1531 mA IDD6 Self Refresh Current Normal Temperature Range 83 56 56 mA 1007 Operating Bank Interleave Read Current 2590 2997 3062 mA Operating Standby and Refresh Currents Tcase 0 85 Vppa Voo 1 5V 0 075V 4GB 2 Ranks 256Mx8 DDR3 SDRAMs m PC3 8500 PC3 10600 PC3 12800 Symbol Parameter Condition BE CG CDI Unit IDDO Operating One Bank Active Precharge Current 813 810 864 mA IDD1 Operating One Bank Active Read Precharge Current 961 980 1045 mA IDD2P0 Precharge Power Down Current Slow Exit 66 95 102 mA IDD2P1 Precharge Power Down Current Fast Exit 209 264 285 mA IDD2Q Precharge Quiet Standby Current 333 408 370 mA IDD2N Precharge Standby Current 364 440 486 mA IDD3P Active Power Down Current 228 289 317 mA IDD3N Active Standby Current 472 461 510 mA IDD4R Operating Burst Read Current 1247 1533 1765 mA IDD4W Burst Write Current 1264 1470 1693 mA IDD5B Burst Refresh Current 1767 1737 1786 mA IDD6 Self Refresh Current Normal Temperature Range 167 113 113 mA 1007 Operating Bank Interle
17. 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BCAMRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BCAMRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings MEINES CEN ODT high time without write command ODTH4min 4 ODTH4 with write command and 4 ODTHA4max e ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON Ooo omms zs e RTT Nom and RTT turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Pos Write Leveling Timings a a ee First DQS DQS rising edge after tWLMRD write leveling mode is programmed DQS DAS delay after write leveling mode is programmed wiDOSEN ck Write leveling setup time from rising CK tWLS 165 crossing to rising DQS DQS crossing Write leveling hold time from rising D
18. 4 DQ44 N j 1 04 DQ13 5 DQ45 N 5 DQi4 N 106 DQ46 N 106 pais 1 07 za gt 2047 N 07 za T ES DQS2 M DQS6 M DQS2 pase DM2 DM6 J M DM CS Das 095 DM CS Das Das pais N 4 100 DQ48 N oo DQ17 N VO 1 DQ49 JN 4 101 pais 102 2950 02 2919 N 103 02 2951 JN 4j 1 03 06 2920 1 04 2952 N j 1 04 2921 N 5 2953 N 5 DQ22 N 1 06 DQ54 N 106 DQ23 1 07 za pass N 7 za r3 DQS3 M DQS7 M bess A T DQS7 _ Tq DM3 DM7 DM CS Das 005 DM CS Das Das DQ24 N 100 pase N O00 DQ25 1 01 2957 N 4 101 2926 2 pass 1 02 2927 1 03 D3 DQ59 N j 1 03 D7 DQ28 N lO 4 104 DQ29 N j 5 DQ61 N 105 DQ30 1 06 2962 N 06 107 za DQ63 N 107 za E ia SCL gt SCL SPD sao gt Ao SPD Voo Vona E 00 07 1 P A1 SDA gt 00 07 A2 Vss 00 07 me 9 J 00 07 2 gt BA0 BA2 SDRAMs 00 07 A0 A13 5 A0 A13 SDRAMs 00 07 RAS RAS SDRAMs 00 07 DDR3 CAS CAS SDRAMs 00 07 SDRAM
19. 4CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM DDR3 1600MHz Speed Bin DDR3 1600 CL nRCD nRP 11 11 11 DI Parameter Symbol ACT to internal read or write delay time 1325 ns PRE command period RP 13 125 s O ACT to orREFcommandperod RC o 48125 ACT to PRE command period 35 3 ns WL 5 L 5 WL 6 eserved Q r I Sj i 5 2 2 o eserved o served Q T e ns ns Vs Di ns served ns eserved ns 875 ns served ns eserved ns 875 25 ns ns ns ns ns ns ns Q iL o Q I 50 Q ojojo Olan Q m a Q T N served eserved served eserved 500 Supported CL Settings 6 7 8 9 10 11 Supported CWL Settings 6 7 8 nCK Optional Q a 2 ojo I 50 WL 5 CL 10 WL 6 m Din e REV 1 1 13 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Unbuffered DDR3 SDRAM DIMM Celixir ecificat
20. 84 00954 204 00513 114 0058 234 0063 TDOSfi 00513 150513 25 0052 145 Vss 55 AM 175 A9 85 DQS4 205 Vs 115 0059 235 26 Vss 146 DQ22 56 A7 176 Voo 86 206 0038 116 Vss 236 Vooseo 27 0018 147 57 Vp 177 A8 87 207 0039 117 SAO 237 SA1 28 0019 148 Vss 58 178 A6 88 0035 208 Vs 118 SCL 238 SDA 29 Vss 149 0028 55 4 179 m 89 Vs 209 0044 119 SA2 239 Vss 30 DQ24 150 DQ29 60 180 A3 90 0040 210 0045 120 Vm 240 Vr Note CK1 CK1 CKE1 S1 and ODT1 are for 4GB modules only REV 1 1 3 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Input Output Functional Description Symbol Type Polarity Function CKO CK1 Cross The system clock inputs All address and command lines are sampled on the cross point of the ain A Input rising edge of CK and falling edge of A Delay Locked Loop DLL circuit is driven from the CK1 point PE h clock inputs and output timing for read operations is synchronized to the input clock CKEO CKE1 Input Active Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By High deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode E
21. CK 24ns tXPDLLmax tCKEmin max 3nCK 5 625ns tCKE tCKEmax tCPDEDmin 1 tCPDED tCPDEDmin Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width Command pass disable delay tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 tACTPDENmax Timing of ACT command to Power Down entry Timing of PRE or PREA command to Power Down entry tPRPDENmin 1 tPRPDENmax tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry 5 T gt MEN E U gt 2 5 8 2 tRDPDENmax REV 1 1 15 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM tWRPDEN BL8MRS 4 IWRPDENmax EI CC MEM C NN MCN tWRAPDEN BL8OTF BL8MRS 4 tWRAPDENmax IWRPDENmin WL 2 WR tCk avg WRPDENmax e m tWRAPDEN BCAMRS tWRAPDENmax Em Em Timing of REF command to Power Down entry tREFPDEN tREFPDENmax Timing of MRS command to Power Down entry tMRSPDEN dept dam ODT Timings mr L ODT high time without write command or ODTH4min 4
22. DQ tied together Single Ended AC and DC Input Levels for Command and Address quM VIH CA DC DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD V VIL CA DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V 1 VIH CA AC Input Logic High Vref 0 175 Note2 Vref 0 175 Note2 Vref 0 175 Note2 V 1 VIL CA AC Input Logic Low Note2 Vref 0 175 Note2 Vref 0 175 Note2 Vref 0 175 V 1 VIH CA AC150 AC Input Logic High Vref 0 15 Note2 Vref 0 15 Note 2 Vref 0 15 Note 2 V 1 VIL CA AC150 AC Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 45 V 1 2 Reference Voltage for ADD 0 49x VDD 0 51 xVDD 0 49xVDD 0 51 xVDD 049xVDD 0O 51xVDD V 3 4 VnetCA DO CMD Inputs Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for _ _ VIH DQ DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD VIL DQ DC DC Input Logic Low vss Vref 0 100 vss Vref 0 100 vss Vref 0 100 V 1 VIH DQ AC Input Logic High Vref 0 175 Note2 Vref 0 15 2 Vref 0 15 Note2 V 1 2 5 VIL DQ AC AC Input Logic Low Note2 0 175 Note2
23. Halogen free product 2GB 4GB SDRAMs are in 78 ball BGA Package RoHS compliance and Halogen free Description M2F2G64CB88B7N M2FA4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBS9N 240 Pin Double Data Rate DDR3 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank of 256Mx64 2GB and two ranks of 512Mx64 4GB high speed memory array Modules use eight 256Mx8 2GB 78 ball BGA packaged devices and sixteen 256Mx8 4GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating of 533MHz 667MHz 800MHz clock speeds and achieves high speed data transfer rates of 1066Mbps 1333Mbps 1600Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs 0 14 2GB 4GB and inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer Ordering Information REV 1 1 1 10 2010
24. M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Celixi r Unbuffered DDR3 SDRAM DIMM Based on DDR3 1066 1333 1600 256Mx8 2GB 4GB SDRAM B Die Features Performance PC3 8500 10600 12800 CG DI Unit DIMM CAS Latency 7 9 11 fck Clock Frequency 533 667 800 MHz tck Clock Cycle 1 875 1 5 1 25 ns fDQ DQ Burst Frequency 1066 1333 1600 Mbps 240 Pin Dual In Line Memory Module UDIMM 256Mx64 2GB 512Mx64 4GB DDR3 Unbuffered DIMM Programmable Operation based on 256Mx8 DDR3 SDRAM B Die devices DIMM CAS Latency 6 7 8 9 10 11 Intended for 533MHz 667MHz 800MHz applications Burst Type Sequential or Interleave Inputs and outputs are SSTL 15 compatible Burst Length BC4 BL8 1 5V 0 075V Operation Burst Read and Write SDRAMs have 8 internal banks for concurrent operation Two different termination values Rtt Nom amp Rtt WR Differential clock inputs 15 10 1 row column rank Addressing for 2GB Data is read or written on both clock edges 15 10 2 row column rank Addressing for 4GB DRAM DLL aligns DQ and DQS transitions with clock transitions Extended operating temperature rage Address and control signals are fully synchronous to positive Auto Self Refresh option clock edge Serial Presence Detect Nominal and Dynamtic On Die Termination support Gold contacts
25. ODT SDRAMs 00 07 ODTi __________ ODT SDRAMs 08 015 SCL SCL CK SDRAMs 00 07 sao M 0 ro le gt SDA CKO SDRAMs 00 07 Sai __ UE cki gt CK SDRAMs 08 015 pz AS CK SDRAMs 08 015 REV 1 10 2010 1 RESET gt Notes 1 DQ to I O wiring is shown as recommended but may be ch 2 DQ DQS DQS ODT DM CKBE S relationships must be mai RESET SDRAMs D8 D15 ned as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 19 4 One SPD exists per module NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Serial Presence Detect M2F2G64CB88B7N M2F2G64CB88BHN 2GB 1 Rank 256 8 DDR3 SDRAMs m Serial PD Data Entry Hex Byte Description CG 06 0 CRC range EEPROM bytes bytes used 92 92 93 1 SPD revision 10 10 10 2 DRAM device type 0B 0B 0B 3 Module type form factor 02 02 02 4 SDRAM Device density and banks 03 03 03 5 SDRAM device
26. ORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Pts Register Set command cycle time web o 00 ck tMODmin max 12nCK 15ns Mode Register Set command update delay to internal read or write delaytime 0 0 0 0 0 0 _ command period ACT or REF command period RO to CASH command delay eeo ok Auto precharge write recovery precharge time ADAL min _ WRerowdupiRP Kavg eek Multi Purpose Register Recovery Time merr ok to PRECHARGE commandperiod RAS Standard Speeding ACTIVE to ACTIVE command period for 1KB page size Rro tRRDmin max 4nCK 10ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size tFAW C m _ e 1d Four activate window for 2KB page size tFAW poss Command and Address setup time to CK CK tlS base 125 referenced to Vih ac Vil ac levels Command and Address hold time from CK tIH ba
27. QS DQS tWLH 165 crossing to rising CK CK crossing Write leveling output delay WLO o o0 ss Write leveling output error Po je REV 1 1 22 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Package Dimensions M2F X 2G64CB88B7N 2GB 1 Rank 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 i gt SIDE wo x S o 2 7 e 2 o e H S Detail A s Detail B 5 175 47 00 71 00 1 27 0 10 5 00 gt Detail A Detail B 2 50 o EX 0 80 0 05 ful 0000 010000 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 1 23 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM M2F2G64CB88BHN 2GB 1 Rank 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 126 0 2 SIDE
28. RFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax t in Valid Clock Requirement before Self Refresh Exit SRX CKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings Exit Power Down with DLL on to any valid command tCKSRX tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax el e nk tCPDEDmin 1 Command pass disable delay tCPDED ICPDEDmin I tCKEmin max 3nCK 5 625ns CKE minimum pulse width tCKEmax tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmin 1 REV 1 1 18 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications wi
29. S DQS referenced to Vih dc Vil dc levels tLZ DQ tHZ DQ DS base C175 tDS base 150 tDH base DC100 DIPW N t t t oo oam J e b o om s je f S os S pet p ee a bw p 231 je ee 237 237 242 242 tERR nper min 1 0 68In n tJIT per min tERR nper max 1 0 68In n tJIT per max a tCK avg wo e e EN e A lt e Note 19 Note 11 o A lt e DQS DQS differential output high time tQSH tQSL tWPRE 51515 w 2 2 lt lt lt je 00 DQS differential WRITE Preamble DQS DQS differential WRITE Postamble tWPST DQS DQS rising edge output access time from rising CK CK tDQSCK DQS and DQS low impedance time tLZ DQS Referenced from RL 1 DQS DQS differential output low time DQS DQS differential input low pulse width DQS DQS differential input high pulse width DQS DQS rising edge to CK CK rising edge tDQSL tDQSH tDQSS tDSS tDSH REV 1 1 10 2010 DQS DQS high impedance time tHZ DQS Referenced from RL BL 2 tDLLK A lt tCK avg tCK avg wo e wo e e wo e EN 51515 2 5 5 w wm lt lt lt e je e A ojo m a lt a 512 pc 14 NANYA TECHNOLOGY CORP
30. ave Read Current 2826 3228 3318 mA REV 1 1 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Standard Speed Bins DDR3 1066MHz Speed Bin CL nRCD nRP Parameter Symbol Min Ma Internal read command tofirstdata ACT to internal read or write delay time ke E ERE ACT to ACT or REF command period boe f ACT to PRE command period IRAS 37 5 e REF fns ICK AVG ICWL 6 ICK AVG RS CWL 5 ICK AVG E 2 U o Djojo ns CWL 6 ICK AVG Reserved ns CWL 5 ICK AV Reserved ns 2 CWL 6 tCK AVG 1 875 1 2 5 Supported CL Settings nCK 5 o CL nRCD nRP 9 9 9 CG Symbol Min 0 000 2 ns to REF command period _ tRC ns ns L 5 ns ns d lt 1 875 R WL n Supported CL Settings 5 6 7 8 9 10 Supported CWL Settings n n n n n n n n n n n n n n S S S S S S S S S S S S S S S REV 1 1 12 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G6
31. ce 01 01 01 63 DRAM address mapping edge connector 01 01 01 117 Module manufacture ID 83 83 83 118 Module manufacture ID 0B 0B 0B 119 121 Module manufacturer Information 126 CRC 47 05 127 CRC 29 80 32 128 145 Module part number 146 Module die revision 147 Module PCB revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 1 7 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Serial Presence Detect M2F4G64CB8HB5N M2F4G64CB8HB9N 4GB 2 Ranks 256Mx8 DDR3 SDRAMs Serial PD Data Entry Byte Description DG 0 CRC range EEPROM bytes bytes used 92 92 93 1 SPD revision 10 10 10 2 DRAM device type 0B 0B 0B 3 Module type form factor 02 02 02 4 SDRAM Device density and banks 03 03 03 5 SDRAM device row and column count 19 19 19 6 Module minimum nominal voltage 00 00 00 T Module ranks and device DQ count 09 09 09 8 ECC tag and module memory Bus width 03 03 03 9 Fine timebase dividend divisor in ps 52 52 52 10 Medium ti
32. e part number 146 Module die revision 147 Module revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 1 8 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Celixi r Unbuffered DDR3 SDRAM DIMM Environmental Requirements Symbol Parameter Rating Units Note Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 1 TsrG Storage Temperature Plastic 55 to 100 C 1 Storage Humidity without condensation 5 to 95 1 Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Absolute Maximum DC Ratings Symbol Parameter Rating Units Note Vpp Voltage on VDD pins relative to Vss 0 4 V 1 975 V V 1 3 VDDQ Voltage on VDDQ pins relative to Vss 0 4 V 1 975 V V 1 3 V
33. ecifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM M2F4G64CB8HB9N 4GB 2 Ranks 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 126 00 0 2 SIDE 5 60 Max 25 00 0 2 30 00 0 5 0 15 1 27 0 1 Detail A Detail B o 250 o bes id 0 80 0 05 fal 00110000 070000 Bl 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 1 26 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 IXI r Unbuffered DDR3 SDRAM DIMM Revision Log Rev 0 1 0 5 1 0 1 1 REV 1 1 10 2010 Date 01 2010 05 2010 06 2010 10 2010 Modification Preliminary Release Preliminary Release 2 Official Release Revision Update Re move Over Clocking Products 27 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
34. f mode Average Clock Period Reter to Standard Speed Bin es Average highpulsewith hoea tka Average low pulsewidth 0 Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth 0 Absolute clock LOW pulsewidth baes 043 Ciok Period siter wo ws Clock Period Jitter during DLL locking period Cycle to Period siter too tgs S Cycle to Cycle Period Jiter during DLL locking period Duty Cycteviter je Cumulative erroracross2cycles Cumulative error aoross 3oyoles Cumulative error across 4 oyoles umulative error across 5 cycles 1 5 o6 468 ee Cumulative erroracross6cycles Cumualveemoracss7cydes ERR 193 193 200 200 205 210 215 tERR nper min 1 0 68In n tJIT per min s nper min 1 0 68In n tERR nper max 1 0 68In n tJIT per max DaaTmimg 00000000 DQo Id time from DQS DQS i ih ative error across n 13 14 49 50 cycles ps 125 250 250 DQS tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC175 tDS base Data setup time to
35. in Vout Voltage on I O pins relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions 7 Symbol Parameter Rating Units Note Normal Operating Temperature Range 0 to 85 C 1 2 TOPER Extended Temperature Range 85 to 95 C 1 3 Note 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 case te
36. iod for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size IFAW o o S Ww Four activate window for 2KB page size IFAW pt ts Command and Address setup time to CK CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK i tlH base 120 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 170 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input ___ Calibration Timing OU Power up and RESET calibration time Normal operation Full calibration time Zope ck ST Normal operation Short calibration time 2005 Reset Timing 2 user sr cio ce c enit E a Se tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR max Self Refresh Timings prre eer T tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLL tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE
37. ions for DDR3 SDRAM Devices Used on Module 1066MHz AC Timing S DDR3 1066 Parameter Symbol Units Min Gama erm eoe see Minimum Clock Cycle Time DLL JckpuLor Average Clock Period Referto StndadSpeedBin Average highpulsewidth tHe oam Wweagelopusewidh 04 05 Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clockHIGH pulsewidth ____ 049 y JjcKeg Absolute clock LOW pulse width O43 Clock Period ster o i i mp ps Clock Period Jitter during DLL locking period __ ps S to Cycle Period der o te ts S Cycle to Cycle Period Jitter during DLL locking period 160 _ ow ps S Duty Cycleviter tury Ps Cumulative error across 4 cycles tERR 4per tERR 7per ERR 8per tERR 9per tERR 10per tERR 1 tper Cumulative error across 12 cycles tERR 12per Cumu Data Timing ative error across n 13 14 49 50 cycles tERR nper DQS DQS to DQ skew per group per access DQ output hold time from DQS DQS tDQSQ tQH t DQ low impedance time from CK CK DQ high impedance time from CK CK Data setup time to DQS DQS referenced to Vih ac Vil ac levels Data setup time to DQS DQS referenced to Vih ac Vil ac levels Data hold time from DQ
38. lance time Command and Address Timing REV 1 1 10 2010 ps 100 225 225 Note 19 Note 11 255 5 tCK avg tCK avg 5 w RR 20 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2FAG64CB8HB9N 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM DLL locking time tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wee Pts rs Mode Register Set command cycle time o ck tMODmin max 12nCK 15ns Mode Register Set command update delay iMODma ACT toimemalreadorwitedelaytime RDP command period ACTtoACTor REF command period ee oo to CAS command delay eeo ok Auto precharge write recovery precharge me _ WReromdupiRP Kavg eek Multi Purpose Register Recovery Time o o ck ACTIVEtoPRECHARGEcommandperod RAS Standard Speed Bins tRRDmin max 4nCK ens ACTIVE to ACTIVE command per
39. m ODTLoff reference RTT dynamic change skew Pos Write Leveling Timings a a ee First DQS DQS rising edge after tWLMRD nCK write leveling mode is programmed DQS DAS delay after write leveling mode is programmed wiDOSEN ck Write leveling setup time from rising CK tWLS 195 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 195 crossing to rising CK crossing Write leveling output delay WLO o ts i Write leveling output error IWLOE Po rs REV 1 1 19 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2F4G64CB8HBON 2GB 256M x 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1600MHz DDR3 1600 Parameter Symbol Units ee Clock Timing o Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed Bins es Average high pulsewidth hoea oa Average low pulsewidth 0 oao Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth os Absolute clock
40. mebase dividend 01 01 01 13 Medium timebase divisor 08 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 0 13 Reserved 00 00 00 14 CAS latencies supported 1C 3C TE 15 CAS latencies supported 00 00 00 16 Minimum CAS latency time tAAmin 69 69 64 17 Minimum write recovery time tWRmin 78 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 64 19 Minimum Row Active to Row Active delay tRRDmin 3C 30 30 20 Minimum row Precharge delay tRPmin 69 69 64 21 Upper nibble for tRAS and tRC 11 11 11 22 Minimum Active to Precharge delay RASmin 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin 95 89 7C 24 Minimum refresh recovery delay tRFCmin LSB 00 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 05 26 Minimum internal Write to Read command delay WTRmin 3C 3C 3C 27 Minimum internal Read to Precharge command delay tRTPmin 3C 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 00 00 29 Minimum four active window delay tFAWmin MSB 2C F0 F0 30 SDRAM device output drivers supported 83 83 83 31 SDRAM device thermal and refresh options 05 05 05 32 Module Thermal Sensor 00 00 00 33 SDRAM Device Type 00 00 00 60 Module height nominal OF OF OF 61 Module thickness Max 11 11 11 62 Raw Card ID reference 01 01 01 63 DRAM address mapping edge connector 01 01 01 117 Module manufacture ID 83 83 83 118 Module manufacture ID 0B 0B 0B 119 121 Module manufacturer Information xs 126 CRC 68 2A D4 127 CRC 59 F0 42 128 145 Modul
41. mperature Full specifications are supported in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to supplier data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 06 and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 1b and MR2 A7 Ob Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range REV 1 1 9 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2FAG64CB8HB9N 2GB 256M 64 AGB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V 2 Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VD
42. nables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by S0 Rank 1 is selected by S1 ana Active 0 Input Low RAS CAS WE Input Active When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE Low define the operation to be executed by the SDRAM Active Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM DID SIM Input High mode register mative The data write masks associated with one data byte In Write mode DM operates as a byte mask DMO DM8 Input High by allowing input data to be written if it is low but blocks the write operation if it is high In Read 9 mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the 00950 DQS8 Cross data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window 0950 0058 point DQS signals are complements and timing is relative to the cross point of respective DQS and DQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to Vss and DDR3 SDRAM mode registers programmed appropriately BA1 BA2 Input
43. rite delaytime RDP command period RP ACT or REF command period RP to CASH command delay tc ok Auto precharge write recovery precharge time WR roundup tRP tCK avg eee Multi Purpose Register Recovery Time o ck ACTIVE to PRECHARGE commandperiod RAS Standard Speed Bins tRRDmin max 4nCK 6ns ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size IFAW pot rs Four activate window for 2KB page size IFAW pts Command and Address setup time to CK CK P tlS base 65 referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 140 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 65 125 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input v p o Calibration Timing OU Power up and RESET calibration time Normal operation Full calibration time Ope se Jk ST Normal operation Short calibration time 2005 Reset Timing 2 user sr cio ce c enit E a Se tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR max Self Refresh Timings 2 tXSmin max 5nCK t
44. se 200 referenced to Vih dc Vil dc levels Command and Address setup time to CK CK ue tlS base AC150 1254150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input Calibration Timing E oe Power up and RESET calibration time tZQinit ae ee Normal operation Full calibration time zaor 29 j Normal operation Short calibration time 1296 Reset Timing opo o y tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR max Self Refresh Timings ee ree ees ee T tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax tXPmin max 3nCK 7 5ns tXPmax A n 20 Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL tXPDLLmin max 10n
45. thout notice M2F2G64CB88B7N M2F4G64CB8HB5N M2F2G64CB88BHN M2FAG64CB8HB9N _ 2GB 256M x 64 4GB 512M x 64PC3 8500 PC3 10600 PC 12800 Q IXI r Unbuffered DDR3 SDRAM DIMM tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN IWRPDENmin WL 4 tWR tCK avg BL8OTF BL8MRS 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDEN IWRAPDENmin WL 4 WR 1 BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BCAMRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BCAMRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings MEN NENNEN ODT high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTHA4max e ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on o aw e RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg fro

Elixir M2F2G64CB88B7N-CG memory module

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