Transcend TS4GSSD25-S solid state drive
Contents
1.2. TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M 2 5 Solid State Disk Description Due to smaller size fit the standard dimensions of 2 5 IDE Hard Disk Drives huge capacity high speed and low power consumption Solid State Disk is perfect replacement storage device for PCs Laptops gaming systems and handheld devices Placement Transcend Master fis ee 33 Slave Features e RoHS compliant e Fully compatible with devices and OS that support the IDE standard 44 Pin pitch 2 00 mm e Non volatile Flash Memory for outstanding data retention e Built in ECC Error Correction Code functionality and wear leveling algorithm ensures highly reliable of data transfer e Supports up to Ultra DMA Mode 4 e Lower Power Consumption e Shock resistance Dimensions Side Millimeters Inches A 100 00 0 40 3 937 0 016 B 69 85 0 20 2 750 0 008 C 7 40 0 15 0 291 0 004 Transcend Information Inc TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M Specifications 2 5 Solid State Disk Physical Specification Form Factor 2 5 inch HDD Storage Capacities 8 GB to 32 GB Length 100 0 0 0 40 Dimensions mm Width 69 85 0 20 Height 7 40 0 15 Input Voltage 5V 5 Weight 80 g Connector 44 Pin standard IDE ATA connector Pitch 2 0 mm Environmental Specifications Operating Temperature 0 c to 70 c Storage Temper
3. ature 40 c to 85 c Reliability Data Reliability Built in 4 symbol page correction ECC Data Retention Connector Durability 10 years 10 000 times Interface Specification Jumper Settings Master Slave Cable select Settings Drivers No Device Driver Required ATA Compatibility ATA ATAPI 5 UDMA Modes 0 4 Compliance and Warranty Compliance CE FCC and BSMI Warranty 2 years Transcend Information Inc TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M 2 5 Solid State Disk Package Dimensions Below figure illustrates the Transcend 2 5 Solid State Disk All dimensions are in mm Transcend Information Inc 3 TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M 2 5 Solid State Disk Pin Assignments Pin No Pin Name Pin No Pin Name RESET GND DD7 DD8 DD6 DD9 DD5 DD10 DD4 DD11 DD3 DD12 DD2 DD13 DD1 DD14 DDO DD15 GND KEY PIN OPEN DMARQ GND DIOW STOP GND DIOR HDMARDY HSTROBE GND IORDY DDMARDY DSTROBE CSEL DMACK GND INTRQ lIOCS16B DA PDIAG CBLID DAO DA2 CS0 CS1 DASP GND VCC VCC GND NC No Connect Pin Layout Slave Mode Cable Select Transcend Information Inc 4 TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M 2 5 Solid State Disk Pin Description 17 15 13 11 09 07 05 03 04 06 08 10 12 14 16 18 DDO DD15 D
4. e 1 to indicate that the device is present 41 42 VCC Power supply 2 19 22 24 26 30 40 43 Note TP An input from the host system to the device GND Ground O An output from the device to the host system 1 0 An input output bi direction common P Power supply Transcend Information Inc TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M 2 5 Solid State Disk Block Diagram DOO D07 A K I zZ o m O O 5 5 9 gt Q O 5 DC Characteristics Data bus CEO CE2 D0 D7 Control CE0 Signal Others CE1 IDE Flash Disk Controller D10 D17 CE1 CE3 Flash Memory WE RE Flash Memory DO D7 CE0 CE1 WE RE Symbol Description Min Max Units lot Driver sink current 4 mA loLDASP Driver sink current for DASP 12 mA loH Driver source current 400 uA oHDMARQ Driver source current for DMARQ 500 uA Iz Device pull up current on DD 15 0 and 10 200 HA STROBE when released Vin Voltage input high 2 0 5 5 V Vit Voltage input low 0 8 V Vou Voltage output high at lon min 2 4 V VoL Voltage output low at lo min 0 5 V AC Characteristics Symbol Description Min Max Units SRISE Rising edge slew rate for any signal 1 25 Vins SFALL Falling edge slew rate for any signal 1 25 Vins Chost Host interface signal capacitance at the 25 pf host connector Casvice Device interface s
5. evice Data Description Hardware reset signal from the host 16 bit bi direction Data Bus DD 7 0 are used for 8 bit register transfers DMARQ DMA Request For DMA data transfers Device will assert DMARQ when the device is ready to transfer data to or from the host DIOW I O Write This is the strobe signal used by the host to write to the device register or Data port STOP Stop UDMA Burst The host asserts this signal during an UDMA burst to stop the DMA burst DIOR I O Read This is the strobe signal used by the host to read from the device register or the Data port HDMARDY UDMA ready When UDMA mode DMA Read is ready HDMARDY should be asserted by the host to indicate that the host is ready to receive DMA data in burst HSTROBE UDMA Strobe HSTROBE receives the data out strobe signal from the host for an UDMA burst IORDY I O channel ready DDMARDY UDMA ready This signal is used to temporarily stop the host register access read or write when the device is not ready to respond to a data transfer request The device will assert this signal to indicate that the device is ready to receive UDMA data out burst DSTROBE UDMA data strobe When UDMA mode DMA Read is active this signal is the data in strobe generated by the device 28 CSEL Cable select This pin is used to configure this device as Device 0 or Device 1 When this pin is grounded t
6. his device is configured as Device 0 When this pin is High this device is configured as Device 1 29 DMACK DMA This signal is used by the host in response to DMARQ to acknowledge initiate DMA transfer 31 INTRQ Interrupt When this device is selected this signal is the active high Interrupt Request to the host Transcend Information Inc TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M 2 5 Solid State Disk 32 35 33 36 1IOCS16B DAO DA2 Device Address During PIO transfer mode 0 1 or 2 this pin indicates to the host the 16 bit data port has been addressed and the device is prepared to send or receive a 16 bit data word When transferring in PIO mode 3 4 or above this signal should not be used by the host and all transfers will be 16 bit When transferring in DMA mode the host must use a 16 bit DMA channel and this signal will not be asserted This is the 3 bit binary coded Address Bus 34 PDIAG Passed diagnostics CBLID Cable assembly type identifier This signal will be asserted by Device 1 to indicate to Device 0 that Device 1 has completed diagnostics CSO CS1 Chip select These signals are used to select the Command Block and Control Block registers When DMACK is asserted CS0 and CS1 shall be negated and transfers shall be 16 bit wide 39 DASP Device active Device 1 present During the reset protocol DASP shall be asserted by Devic
7. ignal capacitance at 20 pf the device connector Transcend Information Inc 7 TS8GSSD25 S TS16GSSD25 S TS32GSSD25 M 2 5 Solid State Disk Ordering Information TS XG SSD 25 X S SLC M MLC Form Factor Transcend Product 25 25 18 1 8 10 1 0 Capacity Solid State Disk 8GB up to 32GB The above technical information is based on industry standard data and has been tested to be reliable However Transcend makes no warranty either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes to the specifications at any time without prior notice USA Los Angeles E mail sales transcendusa com Maryland E mail sales_md transcendusa com www transcendusa com CHINA E mail sales transcendchina com www transcendchina com Transcend Exceeding Your Expectations TAIWAN No 70 XingZhong Rd NeiHu Dist Taipei Taiwan R O C TEL 886 2 2792 8000 Fax 886 2 2793 2222 E mail sales transcend com tw www transcend com tw Transcend Information Inc 8 GERMANY E mail vertrieb transcend de www transcend de HONG KONG E mail sales transcend com hk www transcendchina com JAPAN E mail sales transcend co jp www transcend jp THE NETHERLANDS E mail sales transcend nl www transcend nl United Kingdom E mail sales transcend uk com www transcend uk com
Download Pdf Manuals
Related Search