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Intel Core 2 Duo T7200

1. M 0 SV SKUs to 965 based platform list e Added 1 6 0 stepping MCU e Added 1 and G 0 stepping errata e Added new errata AH108 AH110 AH11S June 2007 594274 013 1 0 e Added Specification Change 1 e Added G 0 17500 17700 processors e Added G 0 X7900 Extreme Edition processor e Added new errata AH111 AH6P July 2007 594274 014 1 0 e Added E 1 X7800 Extreme Edition Processor e Added E 1 X7900 Extreme Edition Processor Added Production stepping G O SV parts August 2007 594274 015 1 0 e Added AH112 AH116 September 2007 355615 016 1 0 e Added AH117 e Added SLV3V for Micro FCBGA U7700 October 2007 Specification Update Document Revision Version Description Date Number 355615 017 1 0 e Added 118 November 2007 e Updated AH8 e Updated Summary Table of Changes 355615 018 1 0 e Added AH119 December 2007 355615 019 1 0 e Added AH120 January 2008 e Updated AH48 and AH51 355615 020 1 0 e Added AH121 July 2008 355615 021 1 0 e Added SLGFJ SLGFV for Micro FCPGA T7400 September 2008 Added SLGFX for Micro FCPGA 17400 355615 022 1 0 e Added Celeron Series processor information September 2008 to the documentation 355615 023 1 0 e Added Errata for Intel Celeron Processor January 2010 500 series for Platforms based on the Intel 965 Express Chipset Family to include a new e
2. Implication Workaround Status AH5P Problem Implication Workaround Status 92 Errata Multi Core Processors Configured for Single Core Operation May Not Be Able to Enter Intel Enhanced Deeper Sleep BIOS may contain the option to disable CMP Core Multiple Processing Disabling CMP configures a processor for single core operation Due to this erratum a multi core processor operating with CMP disabled may not be able to enter Intel Enhanced Deeper Sleep if a SIPI Start up Inter Processor Interrupt is sent to the disabled processor When this erratum occurs the processor may not be able to enter the Intel Enhanced Deeper Sleep and therefore may consume more power than expected Intel has not observed this erratum with any commercially available system or software None Identified For the affected steppings see the Summary Tables of Changes VTPR Access May Lead to System Hang The logical processor may hang if an instruction performs a VTPR access and the next instruction to be executed is located on a different code page Software running VMX non root operation may cause a logical processor to hang if the virtual machine monitor VMM sets both the use TPR shadow and virtualize APIC accesses VM execution controls It is possible for the BIOS to contain a workaround for this erratum For the affected steppings see the Summary Tables of Changes Specification Update Errata AH6P
3. Problem Implication Workaround Status 15 Problem Implication Workaround Status 46 Errata LER MSRs May Be Incorrectly Updated The LER Last Exception Record MSRs MSR LER FROM LIP 1DDH and MSR LER TO LIP 1DEH may contain incorrect values after any of the following e Either STPCLK NMI Non Maskable Interrupt or external interrupts e CMP or TEST instructions with an uncacheable memory operand followed by a conditional jump e STI POP SS MOV SS instructions followed by CMP or TEST instructions and then by a conditional jump When the conditions for this erratum occur the value of the LER MSRs may be incorrectly updated None Identified For the steppings affected see the Summary Tables of Changes Performance Monitoring Events for Retired Instructions COH May Not Be Accurate The INST_RETIRED performance monitor may miscount retired instructions as follows e Repeat string and repeat I O operations are not counted when a hardware interrupt is received during or after the last iteration of the repeat flow e VMLAUNCH and VMRESUME instructions are not counted e HLT and MWAIT instructions are not counted The following instructions if executed during HLT or MWAIT events are also not counted 5 RSM from C state SMI during an MWAIT instruction 6 RSM from an SMI during a HLT instruction There may be a smaller than expected value in the INST_RETIRED performance
4. The upper 32 bits of the From address debug information reported through BTMs or BTSs may be incorrect during this transition None identified For the steppings affected see the Summary Tables of Changes Specification Update Errata AH33 Problem Implication Workaround Status AH34 Problem Implication Workaround Status intel Unsynchronized Cross Modifying Code Operations Can Cause Unexpected Instruction Execution Results The act of one processor or system bus master writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross modifying code XMC XMC that does not force the second processor to execute a synchronizing instruction prior to execution of the new code is called unsynchronized XMC Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code In this case the phrase unexpected or unpredictable execution behavior encompasses the generation of most of the exceptions listed in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3 System Programming Guide including a General Protection Fault GPF or other unexpected behaviors In the event that unpredictable execution causes a GPF the application executing the unsync
5. Fixed CPL Qualified BTS May Report Incorrect Branch From Instruction Address PEBS Does Not Always Differentiate Between CPL Qualified Events x No Fix PMI May Be Delayed to Next PEBS Event Fixed PEBS Buffer Overflow Status Will Not Be Indicated Unless IA32_DEBUGCTL 12 Is Set No Fix The BS Flag in DR6 May Be Set for Non Single Step DB Exception No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP No Fix BO B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint No Fix BTM BTS Branch From Instruction Address May Be Incorrect for Software Interrupts Fixed REP Store Instructions a Specific Situation May Cause the Processor to Hang No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values No Fix Performance Monitoring Events for L1 and L2 Miss May Not Be Accurate AH81 MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63 16 of the Destination Register Unmodified AH82 Fixed Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction followed by SYSRET AH83 No Fix Single Step Interrupts with Floating Point Exception Pending May X X X Be Mishandled AH85 X x X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame AH87 X x X No Fix Unaligned Accesses to Paging Structures May Cause the Processor to Hang AH89 No Fix INVLPG Operation for Large 2M 4M Pages May Be Incomplete
6. 0X100000000 REP CMPS Compare String and SCAS Scan String instructions in 64 bit mode may terminate before the count in RCX reaches zero if the initial value of RCX is greater than or equal to 0X100000000 Early termination of REP CMPS SCAS operation may be observed and RFLAGS may be incorrectly updated It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update Errata AH38 Problem Implication Workaround Status AH39 Problem Implication Workaround Status 40 Problem Implication Workaround Status FXSAVE FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address Alignment lt Ox10h May Cause Instruction or Operand Pointer Corruption If a FXSAVE FXRSTOR instruction stores to the end of the segment causing a wrap to a misaligned base address alignment lt Ox10h and one of the following conditions is satisfied 1 32 bit addressing obtained by using address size override when in 64 bit mode 2 16 bit addressing in legacy or compatibility mode Then depending on the wrap around point one of the below saved values may be corrupted e FPU Instruction Pointer Offset e FPU Instruction Pointer Selector e FPU Operand Pointer Selector e FPU Operand Pointer Offset This erratum could cause FPU Instruction or Operand poin
7. AH104 X X X No Fix A REP STOS MOVS to a MONITOR MWAIT Address Range May Prevent Triggering of the Monitoring Hardware AH105 X X X Plan Fix False Level One Data Cache Parity Machine Check Exceptions May be Signaled AH106 X X X No Fix A Memory Access May Get a Wrong Memory Type Following a GP due to WRMSR to an MTRR Mask AH107 X X X No Fix PMI While LBR Freeze Enabled May Result in Old Out of date LBR Information AH108 X X Plan Fix Overlap of an Intel VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior AH109 No Fix VTPR Write Access During Event Delivery May Cause an APIC Access VM Exit AH110 aa C No Fix BIST BIST Failure After Reset BIST Failure After Reset Reset AH111 No Fix Performance Monitoring Event FP MMX TRANS May Not Count Some Transitions AH112 No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AH113 X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception AH114 X X X No Fix A WB Store Following a REP STOS MOVS or FXSAVE May Lead to Memory Ordering Violations AH115 No Fix VM Exit with Exit Reason TPR Below Threshold Can Cause the Blocking by MOV POP SS and Blocking by STI Bits to Be Cleared in the Guest Interruptibility State Field AH116 No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violat
8. AH56 Fixed Update of Read Write R W or User Supervisor U S or Present P Bits without TLB Shootdown May Cause Unexpected Processor Behavior AH57 t BTS cam Lost When the STPCLK Signal Is Active 58 Set No Fix MOV To From MOV To From Debug Registers Causes Debug Exception Registers Causes Debug Exception AH59 No Fix EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown Specification Update 31 i Summary Tables of Changes Stepping Stepping Stepping ERRATA Fix LBR BTS May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode AH60 AH61 N No Fix A Thermal Interrupt Is Not Generated when the Current Temperature Is Invalid No Fix CMPSB LODSB or SCASB in 64 bit Mode with Count Greater or Equal to 248 May Terminate Early Removed Erratum No Fix Returning to Real Mode from SMM with EFLAGS VM Set May Result in Unpredictable System Behavior 62 AH63 AH64 AH65 AH66 Fixed VMLAUNCH VMRESUME May Not Fail When VMCS Is Programmed to Cause VM Exit to Return to a Different Mode No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Performance Monitoring Event FP ASSIST May Not Be Accurate AH67 AH68 AH69 Fixed 5 Does Not Always Differentiate Between CPL Qualified Events PMI May Be Delayed to Next PEBS Event Fixed PEBS Buffer Overflow St
9. IDA is supported While one core is inactive this feature allows one of the processor cores to temporarily operate at a higher frequency point than HFM when the operating system requests increased performance This higher frequency is called the opportunistic frequency and the HFM frequency is called the guaranteed frequency The opportunistic frequency has a bus ratio of N 1 1 where N is the guaranteed frequency bus ratio 3 Intel Dynamic Front Side Bus Frequency Switching is supported The P state enabled by this feature known as SuperLFM has a frequency of 800 MHz and takes the place of legacy LFM as the lowest voltage and frequency point This feature requires BIOS enabling in both the CPU and a Mobile Intel 965 Express Chipset Family part Please contact an Intel representative for more details 4 Vcc cone 1 3125 1 0750 V for IDA mode 1 250 1 075 1 0000 0 9375 V for Highest Lowest Frequency Mode HFM LFM 0 9 0 8 V for Super LFM Deeper Sleep VID 0 75 0 65 V Intel Enhanced Deeper Sleep VID 0 65 0 60 V 5 Vcc cone 1 2500 1 0750 V for IDA mode 1 250 1 075 1 0000 0 9375 V for Highest Lowest Frequency Mode HFM LFM 0 9 0 8 V for Super LFM Deeper Sleep VID 0 75 0 65 V Intel Enhanced Deeper Sleep VID 0 65 0 60 V 6 Vcc 1 2500 1 0750 V for IDA mode 1 175 1 075 1 0000 0 9375 V for Highest Lowest Frequency Mode HFM LFM 0 9 0 8 V for Super LFM Deeper Sleep VID 0 75 0
10. Normally when the processor encounters a Segment Limit or Canonical Fault due to code execution a GP General Protection Exception fault is generated after all higher priority Interrupts and exceptions are serviced Due to this erratum if RSM Resume from System Management Mode returns to execution flow that results in a Code Segment Limit or Canonical Fault the GP fault may be serviced before a higher priority Interrupt or Exception e g NMI Non Maskable Interrupt Debug break DB Machine Check MC etc If the RSM attempts to return to a non canonical address the address pushed onto the stack for this GP fault may not match the non canonical address that caused the fault Operating systems may observe a GP fault being serviced before higher priority Interrupts and Exceptions Intel has not observed this erratum on any commercially available software None Identified For the steppings affected see the Summary Tables of Changes VM Bit Is Cleared on Second Fault Handled by Task Switch from Virtual 8086 VM86 Following a task switch to any fault handler that was initiated while the processor was in VM86 mode if there is an additional fault while servicing the original task switch then the VM bit will be incorrectly cleared in EFLAGS data segments will not be pushed and the processor will not return to the correct mode upon completion of the second fault handler via IRET When the OS recovers from the second fault ha
11. Problem Implication Workaround Status Activation of Intel Adaptive Thermal Monitor While Intel Dynamic Front Side Bus Frequency Switching Is Active May Lead to an Incorrect Operating Point Frequency Intel Adaptive Thermal Monitor has the ability to use multiple frequency voltage operating points to cool the processor while maintaining a high level of performance If Intel Dynamic Front Side Bus Frequency Switching is active activation of the Intel Adaptive Thermal Monitor may transition the processor to the correct operating point voltage but not frequency This may occur if 1 The software OS requests to go to a higher performance Enhanced Intel SpeedStep Technology operating point during the thermal monitor activation period 2 An entry into C4 state or Intel Enhanced Deeper Sleep interrupts the transition between the Intel Dynamic Front Side Bus Frequency Switching frequency and the targeted thermal monitor operating point frequency If this erratum occurs the Intel Dynamic Front Side Bus Frequency Switching operating point frequency will be observed along with the Intel Adaptive Thermal Monitor operating point voltage The performance state status register IA32 PERF STS will reflect this intermediate performance state There is no functional impact the eventual voltage frequency selection is a valid operating point De activation of the Intel Adaptive Thermal Monitor will result in the processor transitioning to
12. Summary Tables of Changes 19 No Fix Code Segment Limit Violation Occur 4 Gigabyte Limit Stepping Stepping Stepping ERRATA Check AH20 FP Inexact Result Exception Flag May Not Be Set AH21 Global Pages the Data Translation Look Aside Buffer DTLB May Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM 22 Fixed Sequential Code Fetch to Non canonical Address Nondeterministic Results F AH23 Ignores Reserved Bit settings in VM exit Control Field No Fix REP MOVS STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an VMCALL to Activate Dual monitor Treatment of SMIs and SMM 24 Incorrect Data Size or Lead to Memory Ordering Violations AH25 Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions AH26 Premature Execution of a Load Operation Prior to Exception N Handler Invocation N General Protection GP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit AH29 GP Fault is Not Generated on Writing IA32_MISC_ENABLE 34 When Execute Disable is Not supported AH30 Removed Erratum Performance Monitoring Events for Retired Loads CBH and Instructions Retired COH May Not Be Accurate 1 2 Fix Upper 32 bits of From Address Reported through BTMs or BTSs May Be In
13. Values The SIMD_INST_RETIRED Event C7H is used to track retired SSE instructions Due to this erratum the processor may also count other types of instructions resulting in values higher than the number of actual retired SSE instructions The event monitor instruction SIMD_INST_RETIRED may report count higher than expected None identified For the steppings affected see the Summary Tables of Changes Performance Monitoring Events for L1 and L2 Miss May Not Be Accurate Performance monitoring events OCBh with an event mask value of 02h or 08 MEM LOAD RETIRED L1 LINE MISS MEM LOAD RETIRED L2 LINE MISS may under count the cache miss events These performance monitoring events may show a count which is lower than expected the amount by which the count is lower is dependent on other conditions occurring on the same load that missed the cache None Identified For the steppings affected see the Summary Tables of Changes Store to WT Memory Data May Be Seen in Wrong Order by Two Subsequent Loads When data of Store to WT memory is used by two subsequent loads of one thread and another thread performs cacheable write to the same address the first load may get the data from external memory or L2 written by another core while the second load will get the data straight from the WT Store Software that uses WB to WT memory aliasing may violate proper store ordering Do not use WB to WT aliasing For the steppings affect
14. X X X X X X X X X X X X X X X Specification Update 23 i Summary Tables of Changes ERRATA X X Plan Fix FXSAVE FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address Alignment lt Ox10h May Cause FPU Instruction or Operand Pointer Corruption X Fixed Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior X X Plan Fix PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock X X Plan Fix PREFETCHh Instructions May Not Be Executed when Alignment Check AC Is Enabled X X Plan Fix Upper 32 Bits of the FPU Data Operand Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1 s after FXSAVE Fixed Concurrent Multi processor Writes to Non dirty Page May Result in Unpredictable Behavior X Plan Fix Performance Monitor IDLE DURING DIV 18h Count May Not Be Accurate No Fix Values for LBR BTS BTM Will Be Incorrect after an Exit from SMM Fixed Shutdown Condition May Disable Non Bootstrap Processors Fixed SYSCALL Immediately after Changing EFLAGS TF May Not Behave According to the New EFLAGS TF No Fix Code Segment Limit Canonical Faults on RSM May be Serviced before Higher Priority Interrupts Exceptions and May Push the Wrong Address Onto the Stack No Fix VM Bit Is Cleared on Second Fault
15. AC flag set and the interrupt handler s stack is misaligned In IA 32e mode RSP is aligned to a 16 byte boundary before pushing the stack frame In IA 32e mode under the conditions given above an IRET can get a even if alignment checks are disabled at the start of the IRET This erratum can only be observed with a software generated stack frame Software should not generate misaligned stack frames for use with IRET For the steppings affected see the Summary Tables of Changes Specification Update 67 AH67 Problem Problem Implication Workaround Status AH68 Problem Implication Workaround Status AH69 Problem Implication Workaround Status 68 Errata Performance Monitoring Event FP ASSIST May Not Be Accurate Performance monitoring event ASSIST 11H may be inaccurate as assist events will be counted twice per actual assist in the following specific cases e FADD and FMUL instructions with a NaN Not a Number operand and a memory operand e FDIV instruction with zero operand value in memory In addition an assist event may be counted when DAZ Denormals Are Zeros and FTZ Flush To Zero flags are turned on even though no actual assist occurs The counter value for the performance monitoring event ASSIST 11H may be larger than expected The size of the error is dependent on the number of occurrences of the above conditions while the event is active None identifie
16. Controller Access the EFLAGS RFLAGS saved in the VMCS Virtual Machine Control Structure may contain an RF value of O When this erratum occurs following a VM Exit due to a Virtual APIC access the processor may unintentionally break on the subsequent instruction after VM entry None identified For the steppings affected see the Summary Tables of Changes VMCALL Failure Due to Corrupt MSEG Location May Cause VM Exit to Load the Machine State Incorrectly In systems supporting Intel Virtualization Technology if a VMCALL failure occurs due to a corrupt Monitor Segment MSEG subsequent VM Exits may load machine state incorrectly Occurrence of this erratum may result in a VMX abort It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Fixed Function Performance Counters MSR PERF FIXED CTR1 30AH and MSR PERF FIXED CTR2 30BH are Note Cleared When the Processor Is Reset The Fixed Function Performance Counters that count the number of core cycles and reference cycles when the core is not in a halt state are not cleared when the processor is reset The MSR PERF FIXED CTR1 and MSR PERF FIXED CTR2 counters may contain unexpected values after reset BIOS can workaround this erratum by clearing the counters at processor initialization time For the steppings affected see the Summary Tables of Changes Specification Update 91 Problem
17. ESES EREN EX ox ESES EREN X X X X X X X X X X X X X X X X X X X 36 Specification Update Summary Tables of Changes tel e 440000 21 Fixed Global Pages the Data Translation Look Aside Buffer DTLB May X Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM 22 Fixed Sequential Code Fetch to Non canonical Address May X Nondeterministic Results AH24 No Fix MOVS STOS Executing with Fast Strings Enabled and Crossing X X Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory Ordering Violations AH25 X X X No Fix Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions AH26 x x X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation No Fix General Protection GP Fault May Not Be Signaled on Data X Segment Limit Violation above 4 G Limit EIP May Be Incorrect after Shutdown in IA 32e Mode No Fix GP Fault Is Not Generated on Writing IA32 MISC ENABLE 34 When Execute Disable Is Not supported X String REP STOS with Large Data Structures Monitoring Events for Retired Loads Instructions Retired COH May Not Be Accurate X No Fix Upper 32 bits of From Address Reported through BTMs or BTSs May Be Incorrect Fixed Unsynchronized Cross Modifying Code Operations Can C
18. Handled by Task Switch from Virtual 8086 VM86 IA32_FMASK Is Reset during an INIT an Instruction That Signals Floating Point Exception o Fix Last Branch Records LBR Updates May Be Incorrect after a Task Switch No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly INIT Does Not Clear Global Entries in the TLB Plan Fix Using Memory Type Aliasing with Memory Types WB WT May Lead to Unpredictable Behavior X Plan Fix Update of Read Write R W or User Supervisor U S or Present P Bits without TLB Shootdown May Cause Unexpected Processor Behavior No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS POP SS Instruction if it is Followed by N X X X X X X X X X X gt lt 24 Specification Update Summary Tables of Changes Stepping Stepping Stepping ERRATA CAES X AH57 BTS Message Lost When the STPCLK Signal Is Active AH58 MOV To From Debug Registers Causes Debug Exception AH59 X X X No Fix EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown AH60 X X X No Fix LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode AH61 X X X No Fix A Thermal Interrupt Is Not Generated when the Current Temperature Is Invalid AH62 X X X No Fix CMPSB LODSB or SCASB in 64 bit Mode with Count Greater or Equal to 24 May Terminate Ear
19. Not Count Some Transitions AH112 X X X No Fix Instruction Fetch May Cause a Livelock during Snoops of the L1 Data Cache AH110 AH111 AH113 No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception No Fix A WB Store Following a REP STOS MOVS or FXSAVE May Lead to Memory Ordering Violations No Fix VM Exit with Exit Reason TPR Below Threshold Can Cause the Blocking by MOV POP SS and Blocking by STI Bits to Be Cleared in the Guest Interruptibility State Field AH114 AH115 AH116 No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations AH117 No Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results AH118 No Fix NMIs may not be blocked by a VM Entry failure AH119 No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Problem No Fix IA32 1 STATUS MSR Bit 60 Does Not Reflect Machine Check Error Reporting Enable Correctly No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode No Fix FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4 Gbyte Boundary in Code That Uses 32 Bit Address Size in 64 bit Mode AH120 AH121 AH122 34 Specification Update Summary Tables of Changes i Stepping Steppin
20. Performance Monitoring Interrupt should be issued Due to this erratum the PMI may be delayed by one PEBS event Implication Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event Workaround None identified Status For the steppings affected see the Summary Tables of Changes 71 PEBS Buffer Overflow Status Will Not Indicated Unless IA32_DEBUGCTL 12 Is Set Problem IA32_PERF_GLOBAL_STATUS MSR 38EH bit 62 when set indicates that a PEBS Precise Event Based Sampling overflow has occurred and a PMI Performance Monitor Interrupt has been sent Due to this erratum this bit is not set unless IA32 DEBUGCTL MSR 1D9H bit 12 which stops all performance monitor counters upon a PMI is also set Implication Due to this erratum IA32 PERF GLOBAL STATUS 62 will not signal that a PMI was generated due to a PEBS Overflow unless IA32 DEBUGCTL 12 is set Workaround It is possible for the software to set IA32_DEBUGCTL 12 to avoid this erratum Status For the steppings affected see the Summary Tables of Changes AH72 The BS Flag DR6 Set for Non Single Step DB Exception Problem DR6 BS Single Step bit 14 flag may be incorrectly set when the TF Trap Flag bit 8 of the EFLAGS Register is set and a DB Debug Exception occurs due to one of the following e DR7 GD General Detect bit 13 being bit set e INT1 instruction e Code breakpoint Implicati
21. X X X ne under Certain Conditions No Fix Page Access Bit May Be Set Prior to Signaling a Code Segment X X X p Limit Fault x X Plan Fix Update of Attribute Bits on Page Directories without Immediate X TLB Shootdown May Cause Unexpected Processor Behavior Pox pF Invalid Instructions May Lead to Unexpected Behavior EFLAGS CRO CR4 and the EXF4 Signal May Be Incorrect after No Fix Shutdown Specification Update 39 i Summary Tables of Changes Fixed Performance Monitoring Counter MACRO INSTS DECODED May Not Count Some Decoded Instructions Stepping Stepping Stepping AH94 AH95 Plan Fix The Stack May Be Incorrect as a Result of VIP VIF Check on SYSEXIT and SYSRET No Fix Performance Monitoring Event SIMD UOP TYPE EXEC MUL is Counted Incorrectly for PMULUDQ Instruction AH96 AH97 Storage of PEBS Record Delayed Following Execution of MOV SS or No Fix STI No Fix Updating Code Page Directory Attributes without TLB Invalidation May Result Improper Handling of Code PF Performance Monitoring Event CPU CLK UNHALTED REF May Not Count Clock Cycles According to the Processors Operating Frequency x jo X X X Plan Fix Store Ordering May Be Incorrect between WC and WP Memory Types X Fixed Performance Monitoring Event BR INST RETIRED May Count CPUID Instructions as Branches X X X No Fix Performance Monitoring Event MISALIGN MEM REF May Over Count AH104 No Fix A REP STOS MOVS to a MON
22. bit address size For the steppings affected see the Summary Tables of Changes Specification Update 53 AH31 Problem Implication Workaround Status AH32 Problem Implication Workaround Status 54 Errata Performance Monitoring Events for Retired Loads CBH and Instructions Retired COH May Not Be Accurate The following events may be counted as instructions that contain a load by the MEM_LOAD_RETIRED performance monitor events and may be counted as loads by the INST_RETIRED mask 01H performance monitor event e Prefetch instructions x87 exceptions FST and FBSTP instructions e Breakpoint matches on loads stores and I O instructions e Stores which update the A and D bits e Stores that split across a cache line e VMX transitions e Any instruction fetch that misses in the ITLB The MEM_LOAD_RETIRED and INST_RETIRED mask 01H performance monitor events may count a value higher than expected The extent to which the values are higher than expected is determined by the frequency of the above events None identified For the steppings affected see the Summary Tables of Changes Upper 32 Bits of From Address Reported through BTMs or BTSs May Be Incorrect When a far transfer switches the processor from 32 bit mode to IA 32e mode the upper 32 bits of the From source addresses reported through the BTMs Branch Trace Messages or BTSs Branch Trace Stores may be incorrect
23. designing TLB invalidation algorithms For the processors affected Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue 8 Specification Update Documentation Changes i n tel Documentation Changes Note Documentation changes for Intel 64 and IA 32 Architectures Software Developer s Manual volumes 1 2A 2B 3A and 3B will be posted in a separate document Intel 64 IA 32 Architectures Software Developer s Manual Documentation Changes Follow the link below to become familiar with this file http www intel com design processor specupdt 252046 htm Specification Update 97
24. each processor family not across different processor families See http www intel com products processor number for details Specification Update 21 b tel Summary Tables of Changes Errata for Intel Core 2 Duo Processors for Platforms Based on Mobile Intel 945 Express Chipset Family Stepping Stepping Stepping Lud No Fix Writing the Local Vector Table LVT When an Interrupt Is Pending May Cause an Unexpected Interrupt No Fix LOCK Asserted During a Special Cycle Shutdown Transaction May Unexpectedly Deassert No Fix Address Reported by Machine Check Architecture MCA on Single bit L2 ECC Errors May Be Incorrect x No Fix VERW VERR LSL LAR Instructions May Unexpectedly Update the Last Exception Record LER MSR No Fix DR3 Address Match on MOVD MOVQ MOVNTQ Memory X Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired Fixed SYSRET May Incorrectly Clear RF Resume Flag in the RFLAGS Register No Fix General Protection Fault GP for Instructions Greater than 15 Bytes May Be Preempted No Fix Pending x87 FPU exceptions MF following STI may be serviced before higher priority interrupts x No Fix The Processor May Report a TS Instead of a GP Fault a Removed Erratum No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred No Fix Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected T
25. executed matches the address in DR3 the CFH counter may be incorrectly incremented Implication The value observed for performance monitoring count for saturating SIMD instructions retired may be too high The size of the error is dependent on the number of occurrences of the conditions described above while the counter is active None Identified Status For the steppings affected see the Summary Tables of Changes 6 SYSRET May Incorrectly Clear RF Resume Flag the RFLAGS Register Problem In normal operation SYSRET will restore the value of RFLAGS from R11 the value previously saved upon execution of the SYSCALL instruction Due to this erratum the RFLAGS RF bit will be unconditionally cleared after execution of the SYSRET instruction Implication The SYSRET instruction can not be used if the RF flag needs to be set after returning from a system call Intel has not observed this erratum with any commercially available software Workaround Use the IRET instruction to return from a system call if RF flag has to be set after the return Status For the steppings affected see the Summary Tables of Changes Specification Update 43 intel AH7 Problem Implication Workaround Status AHS Problem Implication Workaround Status 9 Problem Implication Workaround Status AH10 44 Errata General Protection Fault GP for Instructions Greater Than 15 Bytes May Be
26. future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Processors will not operate including 32 bit operation without an Intel 64 architecture enabled BIOS Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information System performance battery life high definition quality and functionality and wireless performance and functionality will vary depending on your specific operating system hardware and software configurations References to enhanced performance as measured by SySMark 2004 PCMark 2005 and 3DMark 2005 refer to comparisons with previous generation Intel Centrino mobile technology platforms References to improved battery life as measured by MobileMark 2005 if applicable refer to previous generation Intel Centrino mobile technology platforms Wireless connectivity and some features may require you to purchase additional software services or external hardware Availability of public wire
27. i Summary Tables of Changes Stepping Stepping Stepping ERRATA No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values No Fix Performance Monitoring Events for L1 and L2 Miss May Not Be Accurate No Fix Store to WT Memory Data May Be Seen in Wrong Order by Two Subsequent Loads No Fix A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63 16 of the Destination Register Unmodified Plan Fix Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction followed by SYSRET No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled No Fix Non Temporal Data Store May Be Observed in Wrong Program Order No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Plan Fix CPUID Reports Architectural Performance Monitoring Version 2 is Supported When Only Version 1 AH78 AH79 80 AH81 82 AH83 AH84 AH85 AH86 38280 Capabilities are Available No Fix Unaligned Accesses to Paging Structures May Cause the Processor to Hang AH88 No Fix Microcode Updates Performed During VMX Non root Operation Could Result in Unexpected Behavior No Fix INVLPG Operation for Large 2M 4M Pages May be Incomplete under Certain Conditions No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Update of Attribute Bits on Page Directories without Plan Fix Immediate T
28. in TLB after INIT Write to CR4 setting bits PSE or PAE or CRO setting bits PG or PE registers before writing to memory early in BIOS code to clear all the global entries from TLB For the steppings affected see the Summary Tables of Changes Specification Update Errata AH55 Problem Implication Workaround Status AH56 Problem Implication Workaround Status AH57 Problem Implication Workaround Status Using Memory Type Aliasing with Memory Types WB WT May Lead to Unpredictable Behavior Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses each with different memory type Memory type aliasing with the memory types WB and WT may cause the processor to perform incorrect operations leading to unpredictable behavior Software that uses aliasing of WB and WT memory types may observe unpredictable behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Update of Read Write R W or User Supervisor U S or Present P Bits without TLB Shootdown May Cause Unexpected Processor Behavior Updating a page table entry by changing R W U S or P bits without TLB shootdown as defined by the 4 step procedure in Propagation of Page Table and Page Directory Entry Changes to Multiple Processors In volume 3A of the Intel 64 and IA 32 Ar
29. may occur dependent on the new page memory type 1 UCthe data size of each write will now always be 8 bytes as opposed to the original data size 2 WP the data size of each write will now always be 8 bytes as opposed the original data size and there may be a memory ordering violation 3 WT there may be a memory ordering violation Software should avoid crossing page boundaries from WB or WC memory type to UC WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled For the steppings affected see the Summary Tables of Changes Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions Many Performance Monitoring Events require core specificity which specifies which core s events are to be counted local core other core or both cores Due to this erratum some Bus Performance Monitoring events may not count when the core specificity is set to the local core The following Bus Transaction Performance Monitor events are supposed to count all local transactions e BUS TRANS IO Event 6CH Will not count I O level reads resulting from package resolved C state e BUS TRANS ANY Event 70H Will not count Stop Grants The count values for the affected events may be lower than expected The degree of under count depends on the occurrence of erratum conditions while the affected events are active None identified For the ste
30. monitoring counter The extent to which this value is smaller than expected is determined by the frequency of the above cases None Identified For the steppings affected see the Summary Tables of Changes Specification Update Errata AH16 Problem Implication Workaround Status AH17 Problem Implication Workaround Status Performance Monitoring Event for Number of Reference Cycles When the Processor Is Not Halted 3CH Does Not Count According to the Specification The CPU_CLK_UNHALTED performance monitor with mask 1 counts bus clock cycles instead of counting the core clock cycles at the maximum possible ratio The maximum possible ratio is computed by dividing the maximum possible core frequency by the bus frequency The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower than expected The value is lower by exactly one multiple of the maximum possible ratio Multiply the performance monitor value by the maximum possible ratio For the steppings affected see the Summary Tables of Changes Using 2M 4M Pages When A20M Is Asserted May Result in Incorrect Address Translations An external A20M pin if enabled forces address bit 20 to be masked forced to zero to emulates real address mode address wraparound at 1 megabyte However if all of the following conditions are met address bit 20 may not be masked e Paging is enabled e A linear address has bit 20 set e The address
31. the expected Enhanced Intel SpeedStep Technology operating point None Identified For the affected steppings see the Summary Tables of Changes Specification Update 93 Specification Changes Specification Changes 94 AP 1 The following specification change is incorporated in the Intel Core 2 Duo Processor and Intel Core 2 Extreme Processor for Platforms based on Intel 965 Express Chipset Family Electrical Mechanical and Thermal Specification EMTS Rev 2 7 Table 27 Doc 355617 Specification Update Specification Changes n te 23 CMOS7Open Drain Signal and PoWer Up AC 07 Parameter T35 CMOS asynchronous input 30 pulse width except PWRGOOD T36 PWRGOOD to RESET de 1 assertion time 10 T37 BCLK stable to PWRGOOD assertion T38 PROCHOT pulse width T39 THERMTRIP assertion to Voc turn off T40 FERR Valid Delay from STPCLK deassertion T41 Vec stable to PWRGOOD assertion T42 PWRGOOD rise time T43 Mec BOOT stable to VID BSEL valid T44 VID BSEL valid to V stable 59 T48 V stable to VID BSEL valid 10 T49 V stable to PWRGOOD assertion NOTES d Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All CMOS signal timings are referenced at VCCP 2 3 These si
32. to Non dirty Page May Result in Unpredictable Behavior AH44 Fixed Performance Monitor IDLE_DURING_DIV 18h Count May Not Be TA x X No Fix No Fix Values for ERU Will Be Incorrect after an Exit from SMM AH46 x x No Fix No Fix Shutdown Condition Shutdown Condition May Disable Non Bootstrap Processors Disable Non Bootstrap Processors AH47 Fixed SYSCALL Immediately after Changing EFLAGS TF May Not Behave According to the New EFLAGS TF AH48 No Fix Code Segment Limit Canonical Faults on RSM May be Serviced before Higher Priority Interrupts Exceptions and May Push the Wrong Address Onto the Stack AH49 No Fix VM Bit Is Cleared on Second Fault Handled by Task Switch from Virtual 8086 50 T Fixed IA32 FMASK Is Reset 2 Is Reset during an INIT an INIT AH51 No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception AH52 No Fix Last Branch Records LBR Updates May Be Incorrect after Task Switch AH53 No Fix IO SMI Indication in SMRAM State Save Area Be Set Incorrectly 54 ee uh No Fix INIT Does Not INIT Does Not Clear Global Entries inthe LB Global Entries in INIT Does Not Clear Global Entries inthe LB TLB AH55 Fixed Using Memory Type Aliasing with Memory Types WB WT May Lead to Unpredictable Behavior
33. unpredictable system behavior Intel has not observed this erratum with any commercially available software Workaround None identified Status For the steppings affected see the Summary Tables of Changes Specification Update 77 intel AH96 Problem Implication Workaround Status AH97 Problem Implication Workaround Status 78 Errata Performance Monitoring Event SIMD_UOP_TYPE_EXEC MUL Is Counted Incorrectly for PMULUDQ Instruction Performance Monitoring Event SIMD_UOP_TYPE_EXEC MUL Event select 0B3H Umask 01H counts the number of SIMD packed multiply micro ops executed The count for PMULUDQ micro ops might be lower than expected No other instruction is affected The count value returned by the performance monitoring event SIMD_UOP_TYPE_EXEC MUL may be lower than expected The degree of undercount depends on actual occurrences of PMULUDQ instructions while the counter is active None identified For the steppings affected see the Summary Tables of Changes Storage of PEBS Record Delayed Following Execution of MOV SS or STI When a performance monitoring counter is configured for PEBS Precise Event Based Sampling overflow of the counter results in storage of a PEBS record in the PEBS buffer The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow Due to this erratum if the counter overflow occurs after execution o
34. 2 instead of 1 Software will observe an incorrect version number in CPUID OAh EAX 7 0 in comparison to which features are actually supported Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3 System Programming Guide For the steppings affected see the Summary Tables of Changes Specification Update Errata AH87 Problem Implication Workaround Status 88 Problem Implication Workaround Status 89 Problem Implication Workaround Status Unaligned Accesses to Paging Structures May Cause the Processor to Hang When an unaligned access is performed on paging structure entries accessing a portion of two different entries simultaneously the processor may live lock When this erratum occurs the processor may live lock causing a system hang Do not perform unaligned accesses on paging structure entries For the steppings affected see the Summary Tables of Changes Microcode Updates Performed During VMX Non root Operation Could Result in Unexpected Behavior When Intel Virtualization Technology is enabled microcode updates are allowed only during VMX root operations Attempts to apply microcode updates while in VMX non root operation should be silently ignored Due to this erratum the processor may allow microcode updates dur
35. 65 V Intel Enhanced Deeper Sleep VID 0 65 0 60 V 7 Intel Core 2 Duo mobile processor Low Voltage with 4 M L2 cache 8 Vcc cone 1 1500 0 9750 V for IDA mode 1 0625 0 9750 0 9750 V for Highest Lowest Frequency Mode HFM LFM 0 90 0 85 V for Super LFM Deeper Sleep VID 0 75 0 65 V Intel Enhanced Deeper Sleep VID 0 65 V 9 Intel Core 2 Duo mobile processor Standard Voltage with 2 M L2 Cache 10 Intel Core 2 Duo mobile processor Ultra Low Voltage with 2 M L2 Cache 11 Vcc cone 1 1000 0 9750 V for IDA mode 0 9750 0 8500 0 8500 V for Highest Lowest Frequency Mode HFM LFM Deeper Sleep VID 0 75 0 65 V Intel Enhanced Deeper Sleep VID 0 65 0 60 V Table 1 Intel Celeron Processor 500 Series Component Markings QDF Processor Processor Speed Voltage S Spec Package Number Stepping GHz V QVTG Micro ET i 73 1 30 1 5 FCPGA 0 95 QVTB Micro 1 86 1 30 1 5 0 95 Specification Update 17 tel Identification Information QDF package Processor Processor m umb 5 Number Stepping GHz V 1 Intel Celeron Processor 500 series Standard Voltage based on a single core 1 L2 cache 2 Intel Celeron Processor 500 series Standard Voltage based on a fused single core 1 M L2 cache 3 Intel Celeron Processor 500 series Ultra Low Voltage based on a single core 1 M L2 cache 4 Socket M processor for Intel Centrino Duo pro
36. Bit settings in VM exit Control Field No Fix REP MOVS STOS Executing with Fast Strings Enabled and Plan Fix Sequential Code Fetch to Non canonical Address May Nondeterministic Results X X No Fix Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions X X X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation X X No Fix General Protection GP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit EIP May Be Incorrect after Shutdown in IA 32e Mode X No Fix Fault Is Not Generated on Writing IA32 MISC ENABLE 34 When Execute Disable Is Not supported X Plan Fix E CX May Get Incorrectly Updated Fast String REP MOVS or Fast String REP STOS with Large Data Structures X Plan Fix Performance Monitoring Events for Retired Loads CBH and Instructions Retired COH May Not Be Accurate X No Fix Upper 32 bits of From Address Reported through BTMs or BTSs May Be Incorrect X No Fix MSRs Actual Frequency Clock Count IA32_APERF or Maximum Frequency Clock Count IA32 MPERF May Contain Incorrect Data after a Machine Check Exception MCE X X No Fix Incorrect Address Computed for Last Byte of FXSAVE FXRSTOR Image Leads to Partial Memory Update X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware X X Fixed REP CMPS SCAS Operations May Terminate Early in 64 bit Mode When RCX gt 0X100000000 X X X X X X
37. E 1 icro E 1 Specification Update Identification Information n tel IDA HEM L Spec Number Stepping FM SLFM Specification Update 15 16 QDF Processor Processor ome Cee eee ae epee ey meres ee Identification Information IDA HEM L FM SLFM 1 33 1 20 0 8 2 T 1 0 NA 1 47 1 33 0 8 2 1 0 1 20 1 06 0 8 2 Fu 1 0 NA Huge M 1 2 3 6 1 2 3 6 1 2 3 6 1 2 3 6 123 6 SUUM 1 2 3 6 SEM 1 2 3 6 1 2 3 6 a 2 3 6 9 2 3 6 9 Specification Update Identification Information n tel Processor Processor 4L Number Stepping FM SLFM 1 80 1 60 1 2 0 0 80 The Intel Core 2 Duo Processor for Mobile Intel 965 Express Chipset Family introduces several new features The table has been changed to reflect the addition of features such as Intel Dynamic Acceleration and Intel Dynamic Front Side Bus Frequency Switching 1 Intel Core 2 Duo mobile processor Standard Voltage with 4 M L2 cache 2 Intel Dynamic Acceleration
38. For the steppings affected see the Summary Tables of Changes GP Fault Is Not Generated on Writing IA32 MISC ENABLE 34 When Execute Disable Is Not Supported A fault is not generated on writing to IA32 MISC ENABLE 34 bit in a processor which does not support Execute Disable functionality Writing to IA32 MISC ENABLE 34 bit is silently ignored without generating a fault None identified For the steppings affected see the Summary Tables of Changes E CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS with Large Data Structures When performing Fast String REP MOVS or REP STOS commands with data structures E CX Data Size larger than the supported address size structure 64 kB for 16 bit address size and 4 GB for 32 bit address size some addresses may be processed more than once After an amount of data greater than or equal to the address size structure has been processed external events such as interrupts will cause the E CX registers to be increment by a value that corresponds to 64 kB for 16 bit address size and 4 GB for 32 bit address size E CX may contain an incorrect count which may cause some of the MOVS or STOS operations to re execute Intel has not observed this erratum with any commercially available software Do not use values in E CX that when multiplied by the data size give values larger than the address space size 64 kB for 16 bit address size and 4 GB for 32
39. ITOR MWAIT Address Range May X X X Prevent Triggering of the Monitoring Hardware Px ff 98 99 100 102 103 105 A Memory Access Get a Wrong Memory Type Following GP DIMUS No Fix due to WRMSR to an MTRR Mask PMI While LBR Freeze Enabled May Result in Old Out of date LBR AH107 No Fix Information No Fix BIST Failure after Reset AH110 AH111 112 Instruction Fetch May Cause Livelock During Snoops of the L1 No Fix Data Cache No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception WB Store Following a REP STOS MOVS or FXSAVE May Lead to Memory Ordering Violations No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Performance Monitoring Event FP MMX TRANS TO MMX Not No Fix Count Some Transitions AH113 AH114 False Level One Data Cache Parity Machine Check Exceptions Fixed May Be Signaled AH116 AH117 a 2 x a x AH118 No Fix NMIs May Not Be Blocked by a VM Entry Failure 40 Specification Update Summary Tables of Changes tel Stepping Stepping Stepping Benign Exception after a Double Fault May Not Cause a Triple Fault X Shutdown Proble
40. LB Shootdown May Cause Unexpected 89 90 91 Processor Behavior Invalid Instructions May Lead to Unexpected Behavior EFLAGS CRO CR4 the EXF4 Signal May be Incorrect No Fix after Shutdown Plan Fix Performance Monitoring Counter MACRO_INSTS DECODED May Not Count Some Decoded Instructions Plan Fix The Stack May be Incorrect as a Result of VIP VIF Check on SYSEXIT and SYSRET No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC MUL is Counted Incorrectly for PMULUDQ Instruction No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI 26 Specification Update 92 x x x x x x x Xx x x x x AH93 X AH94 X 95 96 X x AH97 Summary Tables of Changes tel Stepping Stepping Stepping ERRATA aes AH98 No Fix Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code PF AH99 Plan Fix Performance Monitoring Event CPU_CLK_UNHALTED REF May Not Count Clock Cycles According to the Processors Operating Frequency AH100 Plan Fix Store Ordering May be Incorrect between WC and WP Memory Types AH101 X X Plan Fix E CX May Get Incorrectly Updated When Performing Fast String REP STOS With Large Data Structures AH102 X X X Plan Fix Performance Monitoring Event BR INST RETIRED Count CPUID Instructions as Branches AH103 X X X No Fix Performance Monitoring Event MISALIGN MEM REF May Over Count
41. Preempted When the processor encounters an instruction that is greater than 15 bytes in length a GP is signaled when the instruction is decoded Under some circumstances the GP fault may be preempted by another lower priority fault for example Page Fault PF However if the preempting lower priority faults are resolved by the operating system and the instruction retried a GP fault will occur Software may observe a lower priority fault occurring before or in lieu of a GP fault Instructions of greater than 15 bytes in length can only occur if redundant prefixes are placed before the instruction None identified For the steppings affected see the Summary Tables of Changes Pending x87 FPU exceptions MF following STI may be serviced before higher priority interrupts Interrupts that are pending prior to the execution of the STI Set Interrupt Flag instruction are serviced immediately after the STI instruction is executed Because of this erratum if following STI an instruction that triggers a MF is executed while STPCLK Enhanced Intel SpeedStep Technology transitions or Thermal Monitor 1 events occur the pending MF may be serviced before higher priority interrupts Software may observe MF being serviced before higher priority interrupts None Identified For the steppings affected see the Summary Tables of Changes The Processor May Report a TS Instead of a GP Fault A jump to a busy TSS Task State Segme
42. Software Developer s Manual Volume 3A Exception and Interrupt Reference if another exception occurs while attempting to call the double fault handler the processor enters shutdown mode However due to this erratum only Contributory Exceptions and Page Faults will cause a triple fault shutdown whereas a benign exception may not If a benign exception occurs while attempting to call the double fault handler the processor may hang or may handle the benign exception Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Table of Changes Specification Update Errata AH120 Problem Implication Workaround Status 121 Problem Implication Workaround Status 122 Problem Implication Workaround IA32 MC1 STATUS MSR Bit 60 Does Not Reflect Machine Check Error Reporting Enable Correctly 2 MC1 STATUS MSR 405H bit 60 EN Error Enabled is supposed to indicate whether the enable bit in the IA32 1 MSR 404H was set at the time of the last update to the IA32 1 STATUS MSR Due to this erratum IA32 MC1 STATUS MSR bit 60 instead reports the current value of the IA32 1 MSR enable bit 2 1 STATUS MSR bit 60 may not reflect the correct state of the enable bit in the IA32 MC1 MSR at the time of the last update None identified For the steppings affect
43. Tables of Changes Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses each with different memory types Memory type aliasing with a cacheable memory type and WC write combining may cause the processor to perform incorrect operations leading to memory ordering violations for WC operations Software that uses aliasing between cacheable and WC memory types may observe memory ordering errors within WC memory operations Intel has not observed this erratum with any commercially available software None identified Intel does not support the use of cacheable and WC memory type aliasing and WC operations are defined as weakly ordered For the steppings affected see the Summary Tables of Changes Specification Update 87 117 Problem Implication Workaround Status 118 Problem Implication Workaround Status AH119 Problem Implication Workaround Status 88 Errata RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results RSM instruction execution under certain conditions triggered by a complex sequence of internal processor micro architectural events may lead to processor hang or unexpected instruction execution results In the above sequence the processor may live l
44. a are design defects or errors Errata may cause the processor s behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specifications These changes will be incorporated in the next release of the specifications Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in the next release of the specifications Documentation Changes include typos errors or omissions from the current published specifications These changes will be incorporated in the next release of the specifications Errata remain in the specification update throughout the product s lifecycle or until particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes Specification Update n tel are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals etc Specification Update 9 tel Identification I
45. a greater than or equal to the address size structure has been processed external events such as interrupts will cause the E CX registers to be incremented by a value that corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit address size E CX may contain an incorrect count which may cause some of the STOS operations to re execute Intel has not observed this erratum with any commercially available software Do not use values in E CX that when multiplied by the data size give values larger than the address space size 64K for 16 bit address size and 4G for 32 bit address size For the steppings affected see the Summary Tables of Changes Performance Monitoring Event BR_INST_RETIRED May Count CPUID Instructions as Branches Performance monitoring event BR INST RETIRED counts retired branch instructions Due to this erratum two of its sub events mistakenly count for CPUID instructions as well Those sub events are BR INST RETIRED PRED TAKEN Umask 01H and BR INST RETIRED ANY Umask The count value returned by the performance monitoring event BR INST RETIRED PRED TAKEN or BR INST RETIRED ANY may be higher than expected The extent of over counting depends on the occurrence of CPUID instructions while the counter is active None Identified For the steppings affected see the Summary Tables of Changes Specification Update 81 103 Problem Implication Wor
46. affected see the Summary Tables of Changes BTM BTS Branch From Instruction Address May Be Incorrect for Software Interrupts When BTM Branch Trace Message or BTS Branch Trace Store is enabled a software interrupt may result in the overwriting of BTM BTS branch from instruction address by the LBR Last Branch Record branch from instruction address A BTM BTS branch from instruction address may get corrupted for software interrupts None identified For the steppings affected see the Summary Tables of Changes REP Store Instructions in a Specific Situation May Cause the Processor to Hang During a series of REP repeat store instructions a store may try to dispatch to memory prior to the actual completion of the instruction This behavior depends on the execution order of the instructions the timing of a speculative jump and the timing of an uncacheable memory store All types of REP store instructions are affected by this erratum When this erratum occurs the processor may live lock and or result in a system hang It is possible for BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update 71 AH78 Problem Implication Workaround Status AH79 Problem Implication Workaround Status 80 Problem Implication Workaround Status 72 Errata Performance Monitor SSE Retired Instructions May Return Incorrect
47. al Core Intel Xeon processor 7000 sequence C Intel Celeron processor D Dual Core Intel Xeon processor 2 80 GHz E Intel Pentium processor F Intel Pentium processor Extreme Edition and Intel Pentium D processor I Dual Core Intel Xeon processor 50007 series J 64 bit Intel Xeon processor MP with 1 MB L2 cache K Mobile Intel Pentium 11 processor L Intel Celeron D processor M Mobile Intel Celeron processor N Intel Pentium 4 processor O Intel Xeon processor MP P Intel 9 Xeon processor Q Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology R Intel Pentium 4 processor on 90 nm process S 64 bit Intel Xeon processor with 800 MHz system bus 1 MB and 2 MB L2 cache versions T Mobile Intel Pentium 4 processor M U 64 bit Intel Xeon processor MP with up to 8 MB L3 cache V Mobile Intel Celeron processor on 13 Micron Process in Micro FCPGA Package W Intel Celeron M processor X Intel Pentium M processor on 90 nm process with 2 MB L2 cache and Intel Processors A100 and A110 with 512 kB L2 cache Y Intel Pentium M processor Z Mobile Intel Pentium 4 processor with 533 MHz system bus AA Intel Pentium D Processor 900 Sequence and Intel Pentium processor Extreme Edition 9554 9654 AB Intel Pentium 4 processor 6x1 Sequence AC Intel Celeron p
48. als a floating point exception rather than a MOV r e SP r e BP instruction This results in a debug exception being signaled on an unexpected instruction boundary since the MOV SS POP SS and the following instruction should be executed atomically This can result in incorrect signaling of a debug exception and possibly a mismatched Stack Segment and Stack Pointer If MOV SS POP SS is not followed by a MOV r e SP r e BP there may be a mismatched Stack Segment and Stack Pointer on any exception Intel has not observed this erratum with any commercially available software or system As recommended in the Inte 64 and IA 32 Architectures Software Developer s Manual the use of MOV SS POP SS in conjunction with MOV r e SP r e BP will avoid the failure since the MOV r e SP r e BP will not generate a floating point exception Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum For the steppings affected see the Summary Tables of Changes Last Branch Records LBR Updates May Be Incorrect after a Task Switch A Task State Segment TSS task switch may incorrectly set the LBR_FROM value to the LBR_TO value The LBR_FROM will have the incorrect address of the Branch Instruction None Identified For the steppings affected see the Summary Tables of Changes Specification Update 61 AH53 Problem Implication Workaround Status AH54 Problem Imp
49. as not observed this erratum with any commercially available software Software should not attempt to set reserved bits of IA32 MTRR PHYSMASKn MSRs For the steppings affected see the Summary Tables of Changes PMI While LBR Freeze Enabled May Result in Old Out of Date LBR Information When Precise Event Based Sampling PEBS is configured with Performance Monitoring Interrupt PMI on PEBS buffer overflow enabled and Last Branch Record LBR Freeze on PMI enabled by setting FREEZE LBRS ON PMI flag bit 11 to 1 in IA32 DEBUGCTL MSR 1D9H the LBR stack is frozen upon the occurrence of a hardware PMI request Due to this erratum the LBR freeze may occur too soon i e before the hardware PMI request Following a PMI occurrence the PMI handler may observe old out of date LBR information that does not describe the last few branches before the PEBS sample that triggered the PMI None identified For the steppings affected see the Summary Tables of Changes Specification Update 83 108 Problem Implication Workaround Status AH109 Problem Implication Errata Overlap of an Intel VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Logging of a branch record or a PEBS precise event based sampling record to the DS debug store save area that overlaps with the APIC access page may lead to unpredictable behavior Guest software configured to log branch records
50. ata Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang or to report a machine check exception MCE This would occur if one of the addresses is non cacheable and used in a code segment and the other is a cacheable address If the cacheable address finds its way into the instruction cache and the non cacheable address is fetched in the IFU the processor may invalidate the non cacheable address from the fetch unit Any micro architectural event that causes instruction restart will be expecting this instruction to still be in the fetch unit and lack of it will cause a system hang or an MCE This erratum has not been observed with commercially available software Although it is possible to have a single physical page mapped by two different linear addresses with different memory types Intel has strongly discouraged this practice as it may lead to undefined results Software that needs to implement memory aliasing should manage the memory type consistency For the steppings affected see the Summary Tables of Changes A WB Store Following a REP STOS MOVS or FXSAVE May Lead to Memory Ordering Violations Under certain conditions as described in the Software Developers Manual section Out of Order Stores For String Operati
51. atus Will Not Be Indicated Unless 2 DEBUGCTL 12 Is Set The BS Flag DR6 May Be Set for Non Single Step DB Exception An Asynchronous MCE during a Far Transfer May Corrupt ESP Fixed In Single Stepping on Branches Mode the BS Bit in the Pending Debug Exceptions Field of the Guest State Area will be Incorrectly AH70 Fixed CPL Qualified BTS May Report Incorrect Branch From Instruction Address AH72 AH73 AH74 Set by VM Exit on a MOV to CR8 Instruction No Fix BO B3 Bits in DR6 May Not Properly Cleared after Code Breakpoint No Fix BTM BTS Branch From Instruction Address May Be Incorrect for Software Interrupts Fixed Store Instructions in a Specific Situation May Cause the Processor to Hang No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values No Fix Performance Monitoring Events for L1 L2 Miss May Not Be Accurate N Fix Store to WT Memory Data May Be Seen in Wrong Order by Two Subsequent Loads AH75 AH76 AH77 AH78 AH79 AH80 AH81 Leave Bits 63 16 of the Destination Register Unmodified A MOV Instruction from CR8 Register with 16 Bit Operand Size Will 32 Specification Update Summary Tables of Changes Stepping Stepping Stepping ERRATA AH83 AH82 Fixed Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction followed by SYSRET 84 X X No Fix Non Temporal Data Store May Be Observed
52. ause unexpected Instruction Execution Results No Fix MSRs Actual Frequency Clock Count IA32 APERF or Maximum X X Frequency Clock Count 2 MPERF May Contain Incorrect Data after a Machine Check Exception MCE No Fix Incorrect Address Computed for Last Byte of FXSAVE FXRSTOR X X X Image Leads to Partial Memory Update No Fix Split Locked Stores May Not Trigger the Monitoring Hardware A T T pr did When RCX gt 0X100000000 AH38 Fixed FXSAVE FXRSTOR Instructions which Store to the End of the X Segment and Cause a Wrap to a Misaligned Base Address Alignment lt 0x10h May Cause FPU Instruction or Operand Pointer Corruption AH39 Fixed Cache Data Access Request from One Core Hitting a Modified Line X in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior 40 x Fixed PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock Specification Update 37 i Summary Tables of Changes MD om Check AC Is Enabled Memory Image May Be Unexpectedly All 1 5 after FXSAVE Unpredictable Behavior Accurate Values for LBR BTS BTM Will Be Incorrect after an Exit from SMM 41 42 4 44 45 47 According to the New EFLAGS TF Virtual 8086 VM86 IA32_FMASK Is Reset during an INIT AH49 i No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS POP SS Instruction if it is Followed b
53. ay Not Be Executed When Alignment Check AC Is Enabled PREFETCHTO PREFETCHT1 PREFETCHT2 and PREFETCHNTA instructions may not be executed when Alignment Check is enabled PREFETCHh instructions may not perform the data prefetch if Alignment Check is enabled Clear the AC flag bit 18 in the EFLAGS register and or the AM bit bit 18 of Control Register CRO to disable alignment checking For the steppings affected see the Summary Tables of Changes Upper 32 Bits of the FPU Data Operand Pointer in the FXSAVE Memory Image Be Unexpectedly All 1 s after FXSAVE The upper 32 bits of the FPU Data Operand Pointer may incorrectly be set to all 1 s instead of the expected value of all O s in the FXSAVE memory image if all of the following conditions are true e The processor is in 64 bit mode e The last floating point operation was in compatibility mode e Bit 31 of the Data Operand Pointer is set e An FXSAVE instruction is executed Software depending on the full FPU Data Operand Pointer may behave unpredictably None identified For the steppings affected see the Summary Tables of Changes Concurrent Multi processor Writes to Non dirty Page May Result in Unpredictable Behavior When a logical processor writes to a non dirty page and another logical processor either writes to the same non dirty page or explicitly sets the dirty bit in the corresponding page table entry complex interaction with internal pro
54. ay occur if a memory address exceeds the 64KB limit while the processor is operating in 16 bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32 bit mode FXSAVE FXRSTOR will incur a GP fault due to the memory limit violation as expected but the memory state may be only partially saved or restored Software should avoid memory accesses that wrap around the respective 16 bit and 32 bit mode memory limits For the steppings affected see the Summary Tables of Changes Split Locked Stores May Not Trigger the Monitoring Hardware Logical processors normally resume program execution following the MWAIT when another logical processor performs a write access to a WB cacheable address within the address range used to perform the MONITOR operation Due to this erratum a logical processor may not resume execution until the next targeted interrupt event or O S timer tick following a locked store that spans across cache lines within the monitored address range The logical processor that executed the MWAIT instruction may not resume execution until the next targeted interrupt event or O S timer tick in the case where the monitored address is written by a locked store which is split across cache lines Do not use locked stores that span cache lines in the monitored address range For the steppings affected see the Summary Tables of Changes REP CMPS SCAS Operations May Terminate Early in 64 bit Mode When RCX
55. brand names April 2007 4 Specification Update Document Number Revision Version Description Date e Updated Summary Table of changes e Revised Errata AH14 AH25 AH26 e Added new Microcode Updates for B2 and L2 stepping e Added Errata AH105 e Added Specification Clarification AH3 594274 011 1 0 e Updated the following to include Intel Core 2 Duo processors on platforms based on the Mobile Intel 965 Express Chipset Family Added Table 2 Intel Core 2 Duo Processor for Mobile Intel 965 Express Chipset Family Component Markings Added Table 4 Intel Core 2 Duo Processor for Mobile Intel 965 Express Chipset Family Microcode Update Guide Added section Erratum for Intel Core 2 Duo Processors for Platforms Based on Mobile Intel 965 Express Chipset Family e Removed Specification Clarification AH1 and AH2 e Removed AH3S Fixed e Updated Specification Clarification AH3 e Updated Figure 1 and added Figure 2 e Added table linking processor stepping to CPU signature in the Component Identification Via the Programming Interface e Added Errata AH106 AH107 105 2007 594274 012 1 0 e Updated Hyperlinks for the SDM Collateral under the Related Documents section e Added 1 and G 0 Stepping to the Component Marking section e Added U2100 and U2200 A 1 stepping SKUs QDF to 945 based platform list e Added G 0
56. cessor activity may cause unpredictable system behavior This erratum may result in unpredictable system behavior and hang It is possible for BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update Errata AH44 Problem Implication Workaround Status AH45 Problem Note Implication Workaround Status AH46 Problem Implication Workaround Status Performance Monitor IDLE_DURING_DIV 18h Count May Not Be Accurate Performance monitoring events that count the number of cycles the divider is busy and no other execution unit operation or load operation is in progress may not be accurate The counter may reflect a value higher or lower than the actual number of events None identified For the steppings affected see the Summary Tables of Changes Values for LBR BTS BTM Will Be Incorrect after an Exit from SMM After a return from SMM System Management Mode the CPU will incorrectly update the LBR Last Branch Record and the BTS Branch Trace Store hence rendering their data invalid The corresponding data if sent out as a BTM on the system bus will also be incorrect This issue would only occur when one of the 3 above mentioned debug support facilities are used The value of the LBR BTS and BTM immediately after an RSM operation should not be used None identified For the steppings affected s
57. cessor technology Napa Refresh Platform 5 Socket P processor for Intel Centrino Duo processor technology Santa Rosa Platform Specification Update Summary Tables of Changes tel Summary Tables of Changes The following table indicates the Specification Changes Errata Specification Clarifications or Documentation Changes which apply to the listed CPU steppings Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted This table uses the following notations Codes Used in Summary Table Stepping X Erratum Specification Change or Clarification that applies to this stepping No mark or Blank Box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Status Doc Document change or update that will be implemented Plan Fix This erratum may be fixed in a future stepping of the product Fixed This erratum has been previously fixed No Fix There are no plans to fix this erratum Row Shaded This item is either new or modified from the previous version of the document Specification Update 19 Summary Tables of Changes Note Each Specification Update item is prefixed with a capital letter to distinguish the 20 product The key below details the letters that are used in Intel s microprocessor Specification Updates Du
58. chitectures Software Developer s Manual in conjunction with a complex sequence of internal processor micro architectural events may lead to unexpected processor behavior This erratum may lead to livelock shutdown or other unexpected processor behavior Intel has not observed this erratum with any commercially available system None Identified For the steppings affected see the Summary Tables of Changes BTS Message Be Lost When the STPCLK Signal Is Active STPCLK is asserted to enable the processor to enter a low power state Under some circumstances when STPCLK becomes active the BTS Branch Trace Store message may be either lost and not written or written with corrupted branch address to the Debug Store area BTS messages be lost or be corrupted in the presence of STPCLK assertions None Identified For the steppings affected see the Summary Tables of Changes Specification Update 63 58 Problem Implication Workaround Status 64 Errata MOV To From Debug Registers Causes Debug Exception When in V86 mode if a MOV instruction is executed to from a debug register a general protection exception GP should be generated However in the case when the general detect enable flag GD bit is set the observed behavior is that a debug exception DB is generated instead With debug register protection enabled that is the GD bit set when attempting to execute a MOV on debug regi
59. completed DTLB eviction requires at least three load operations that have linear address bits 15 12 equal to each other and address bits 31 16 different from each other in close physical proximity to the arithmetic operation 2 The page table entry for the store address must have its permissions tightened during the very small window of time between the DTLB eviction and execution of the store Examples of page permission tightening include from Present to Not Present or from Read Write to Read Only etc 3 Another processor without corresponding synchronization and TLB flush must cause the permission change This scenario may only occur on a multiprocessor platform running an operating system that performs lazy TLB shootdowns The memory image of the EFLAGS register on the page fault handler s stack prematurely contains the final arithmetic flag values although the instruction has not yet completed Intel has not identified any operating systems that inspect the arithmetic portion of the EFLAGS register during a page fault nor observed this erratum in laboratory testing of software applications No workaround is needed upon normal restart of the instruction since this erratum is transparent to the faulting code and results in correct instruction behavior Operating systems may ensure that no processor is currently accessing a page that is scheduled to have its page permissions tightened or have a page fault handler that ignores any incorrect
60. correct AH33 Fixed Unsynchronized Cross Modifying Code Operations Can Cause unexpected Instruction Execution Results AH34 No Fix MSRs Actual Frequency Clock Count IA32_APERF or Maximum Frequency Clock Count IA32 MPERF May Contain Incorrect Data after a Machine Check Exception MCE AH35 Image Leads to Partial Memory Update EIP May Be Incorrect after Shutdown in IA 32e Mode Incorrect Address Computed for Last Byte of FXSAVE FXRSTOR AH36 Split Locked Stores May Not Trigger the Monitoring Hardware AH37 Fixed REP CMPS SCAS Operations May Terminate Early in 64 bit Mode When RCX gt 0X100000000 Fixed FXSAVE FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address AH38 Alignment lt 0x10h May Cause Instruction or Operand Pointer Corruption 30 Specification Update Summary Tables of Changes tel Stepping Stepping Stepping AH39 Fixed Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior AH40 Fixed PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock AH41 Fixed PREFETCHh Instructions May Not Be Executed when Alignment Check AC Is Enabled AH42 Fixed Upper 32 Bits of the FPU Data Operand Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1 s after FXSAVE AH43 Fixed Concurrent Multi processor Writes
61. d For the steppings affected see the Summary Tables of Changes CPL Qualified BTS May Report Incorrect Branch From Instruction Address CPL Current Privilege Level qualified BTS Branch Trace Store may report incorrect branch from instruction address under the following conditions e Either BTS OFF OS 9 or BTS OFF USR 10 is selected IA32 DEBUGCTLC MSR 1D9H Privilege level transitions occur between CPL gt 0 and CPL 0 or vice versa Due to this erratum the From address reported by BTS may be incorrect for the described conditions None Identified For the steppings affected see the Summary Tables of Changes PEBS Does Not Always Differentiate Between CPL Qualified Events Performance monitoring counter configured to sample PEBS Precise Event Based Sampling events at a certain privilege level may count samples at the wrong privilege level Performance monitoring counter may be higher than expected for CPL qualified events Do not use performance monitoring counters for precise event sampling when the precise event is dependent on the CPL value For the steppings affected see the Summary Tables of Changes Specification Update Errata AH70 PMI May Be Delayed to Next PEBS Event Problem After a PEBS Precise Event Based Sampling event the PEBS index is compared with the PEBS threshold and the index is incremented with every event If PEBS index is equal to the PEBS threshold a PMI
62. d IA 32 Architecture Software Developer s Manual Volume 3A section Buffering of Write Combining Memory Locations will operate correctly For the steppings affected see the Summary Tables of Changes Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame The ENTER instruction is used to create a procedure stack frame Due to this erratum if execution of the ENTER instruction results in a fault the dynamic storage area of the resultant stack frame may contain unexpected values i e residual stack data as a result of processing the fault Data in the created stack frame may be altered following a fault on the ENTER instruction Please refer to Procedure Calls For Block Structured Languages in the Intel 64 and IA 32 Architectures Software Developer s Manual Vol 1 Basic Architecture for information on the usage of the ENTER instructions This erratum is not expected to occur in ring 3 Faults are usually processed in ring O and stack switch occurs when transferring to ring 0 Intel has not observed this erratum on any commercially available software None identified For the steppings affected see the Summary Tables of Changes CPUID Reports Architectural Performance Monitoring Version 2 Is Supported When Only Version 1 Capabilities Are Available CPUID leaf OAh reports the architectural performance monitoring version that is available in EAX 7 0 Due to this erratum CPUID reports the supported version as
63. d not rely on the value reported in MCi_ADDR for Single bit L2 ECC errors None identified For the steppings affected see the Summary Tables of Changes Specification Update ert intel AH4 Exception Record LER MSRVERW VERR LSL LAR Instructions May Unexpectedly Update the Last Exception Record LER MSR Problem The LER MSR may be unexpectedly updated if the resultant value of the Zero Flag ZF is zero after executing the following instructions 1 VERR ZF 0 indicates unsuccessful segment read verification 2 VERW 7 0 indicates unsuccessful segment write verification 3 LAR ZF 0 indicates unsuccessful access rights load 4 151 ZF 0 indicates unsuccessful segment limit load Implication The value of the LER MSR may be inaccurate if VERW VERR LSL LAR instructions are executed after the occurrence of an exception Workaround Software exception handlers that rely on the LER MSR value should read the LER MSR before executing VERW VERR LSL LAR instructions Status For the steppings affected see the Summary Tables of Changes 5 Address Match on MOVD MOVQ MOVNTQ Memory Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired Event CFH Problem Performance monitoring for Event CFH normally increments on saturating SIMD instruction retired Regardless of DR7 programming if the linear address of a retiring memory store MOVD MOVQ MOVNTQ instruction
64. date 75 90 Problem Implication Workaround Status AH91 Problem Implication Workaround Status 92 Implication Workaround Status 76 Errata Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault If code segment limit is set close to the end of a code page then due to this erratum the memory page Access bit A bit may be set for the subsequent page prior to general protection fault on code segment limit When this erratum occurs a non accessed page present in memory following a page that contains the code segment limit may be tagged as accessed Non present or non executable page can be placed after the limit of the code segment to prevent this erratum For the steppings affected see the Summary Tables of Changes Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Updating a page directory entry or page map level 4 table entry or page directory pointer table entry in IA 32e mode by changing R W U S or P bits without immediate TLB shootdown as described by the 4 step procedure in Propagation of Page Table and Page Directory Entry Changes to Multiple Processors In Volume 3A of the Inte 64 and IA 32 Architectures Software Developer s Manual in conjunction with a complex sequence of internal processor micro architectural events may lead to unexpected processor behavior This e
65. dentified by software with its CPU signature 10 Specification Update Identification Information tel Table 2 CPU Signature for the Intel Celeron Processor Stepping CPU Signature E 1 O6FAh M 1 O6FDh Component Marking Information Figure 1 Intel Core 2 Duo Mobile Processor Micro FCPGA FCBGA Sample Markings Group 1 Line 1 See mere SAMPLE MARK EXAMPLE Group 1 Line 1 Unit Identifier Group 1 Line 2 FPO QDF ES Group 2 Line 1 INTEL 05 Group 2 Line 2 ATPO Serial Number For Pb Free Group 2 Line 1 INTEL 05 1 P Group 2 Line 1 Li Group 2 Line 2 Intel Core 2 Duo mobile processors have a unit identifier of LF80537 for Micro FCPGA parts and LE80537 for Micro FCBGA parts Specification Update 11 Identification Information Figure 2 Intel Core 2 Duo Mobile Processor Micro FCPGA FCBGA Production Markings Group 1 Line 1 Group 1 Line 2 Group 2 Line 1 L Group 2 Line 2 Production MARK EXAMPLE Group 1 Line 1 Unit Identifier Processor Group 1 Line 2 FPO SSPEC Group 2 Line 1 Frequency L2 Cache FSB Speed Group 2 Line 2 INTEL m 06 For Pb Free Group 2 Line 2 INTEL m 06 e1 Intel Core 2 Duo mobile processors have a unit identifier of LF80537 for Micro FCPGA parts and LE80537 for Micro FCBGA parts Figure 3 Intel Celeron Processor 500 Series Micro FCPGA Markings Group 1 Line 1 Gr
66. different rates and therefore will not be comparable Calculate the ratio of the rates at which the TSC and the CPU CLK UNHALTED REF performance monitoring event count this can be done by measuring simultaneously their counted value while executing code and adjust the CPU CLK UNHALTED REF event count to the maximum resolved boot frequency using this ratio For the steppings affected see the Summary Tables of Changes Store Ordering May Be Incorrect between WC and WP Memory Types According to Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A Methods of Caching Available WP Write Protected stores should drain the WC Write Combining buffers in the same way as UC Uncacheable memory type stores do Due to this erratum WP stores may not drain the WC buffers Memory ordering may be violated between WC and WP stores None Identified For the steppings affected see the Summary Tables of Changes Specification Update Errata AH101 Problem Implication Workaround Status AH102 Problem Implication Workaround Status E CX May Get Incorrectly Updated When Performing Fast String REP STOS with Large Data Structures When performing Fast String REP STOS commands with data structures E CX Data Size larger than the supported address size structure 64K for 16 bit address size and 4G for 32 bit address size some addresses may be processed more than once After an amount of dat
67. e Directory Attributes without TLB Invalidation May Result in Improper Handling of Code PF Fixed Performance Monitoring Event CPU_CLK_UNHALTED REF May Not Count Clock Cycles According to the Processors Operating Frequency AH100 X X X Plan Fix Store Ordering May be Incorrect between WC and WP Memory Types AH101 Fixed E CX Get Incorrectly Updated When Performing Fast String REP STOS With Large Data Structures Specification Update 33 i Summary Tables of Changes ERRATA Fixed Performance Monitoring Event BR INST RETIRED May Count CPUID Instructions as Branches No Fix Performance Monitoring Event MISALIGN MEM REF May Over Count No Fix A REP STOS MOVS to a MONITOR MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Fixed False Level One Data Cache Parity Machine Check Exceptions May be Signaled Stepping Stepping Stepping AH102 AH103 AH104 AH105 AH106 No Fix A Memory Access May Get a Wrong Memory Type Following a GP due to WRMSR to an MTRR Mask No Fix PMI While LBR Freeze Enabled May Result in Old Out of date LBR Information AH107 AH108 Fixed Overlap of an Intel VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior AH109 X X X No Fix VTPR Write Access During Event Delivery May Cause an APIC Access VM Exit No Fix BIST Failure After Reset X X X No Fix Performance Monitoring Event FP MMX TRANS TO MMX May
68. e precision exception FST m32real FST m64real FSTP m32real FSTP m64real FSTP m80real FIST mi6int FIST m32int FISTP mi6int FISTP m32int FISTP m64int FISTTP mi6int FISTTP m32int FISTTP m64int Even if this combination of instructions is encountered there is also a dependency on the internal pipelining and execution state of both instructions in the processor Inexact result exceptions are commonly masked or ignored by applications as it happens frequently and produces a rounded result acceptable to most applications The PE bit of the FPU status word may not always be set upon receiving an inexact result exception Thus if these exceptions are unmasked a floating point error exception handler may not recognize that a precision exception occurred Note that this is a sticky bit i e once set by an inexact result condition it remains set until cleared by software This condition can be avoided by inserting either three NOPs or three non floating point non Jcc instructions between the two floating point instructions For the steppings affected see the Summary Tables of Changes 49 intel AH21 Problem Implication Workaround Status AH22 Problem Implication Workaround Status AH23 Problem Implication Workaround Status 50 Errata Global Pages in the Data Translation Look Aside Buffer DTLB May Not Be Flushed by RSM instruction before Restoring the Architectural State f
69. ed see the Summary Table of Changes Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode During the transition from real mode to protected mode if an SMI System Management Interrupt occurs between the MOV to CRO that sets PE Protection Enable bit 0 and the first far JMP the subsequent RSM Resume from System Management Mode may cause the lower two bits of CS segment register to be corrupted The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first far JMP Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Part 1 in the section titled Switching to Protected Mode recommends the far JMP immediately follows the write to CRO to enable protected mode Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Table of Changes FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4 Gbyte Boundary in Code That Uses 32 Bit Address Size in 64 bit Mode The FP Floating Point Data Operand Pointer is the effective address of the operand associated with the last non control FP instruction executed by the processor If an 80 bit FP access load or store uses a 32 bit address size in 64 bit mode and the
70. ed see the Summary Tables of Changes Specification Update Errata AH81 Problem Implication Workaround Status AH82 Problem Implication Workaround Status AH83 Problem Implication Workaround Status A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63 16 of the Destination Register Unmodified Moves to from control registers are supposed to ignore REW W and the 66H operand size prefix In systems supporting Intel Virtualization Technology when the processor is operating in VMX non root operation and use TPR shadow VM execution control is set to 1 a MOV instruction from CR8 with a 16 bit operand size REX W 0 and 66H prefix will only store 16 bits and leave bits 63 16 at the destination register unmodified instead of storing zeros in them Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction Followed by SYSRET In IA 32e mode if a MOVSS or POPSS instruction with a debug breakpoint is followed by the SYSRET instruction incorrect information may exist in the Debug Status Register DR6 When debugging or when developing debuggers this behavior should be noted This erratum does not occur under normal usage of the MOVSS or POPSS instructions that is following the
71. ee the Summary Tables of Changes Shutdown Condition May Disable Non Bootstrap Processors When a logical processor encounters an error resulting in shutdown non bootstrap processors in the package may be unexpectedly disabled Non bootstrap logical processors in the package that have not observed the error condition may be disabled and may not respond to INIT SMI NMI SIPI or other events When this erratum occurs RESET must be asserted to restore multi core functionality For the steppings affected see the Summary Tables of Changes Specification Update 59 47 Problem Implication Workaround Status 48 Problem Implication Workaround Status AH49 Problem Implication Workaround Status 60 Errata SYSCALL Immediately after Changing EFLAGS TF May Not Behave According to the New EFLAGS TF If a SYSCALL instruction follows immediately after EFLAGS TF was updated and IA32_FMASK TF bit 8 is cleared then under certain circumstances SYSCALL may behave according to the previous EFLAGS TF When the problem occurs SYSCALL may generate an unexpected debug exception or may skip an expected debug exception Mask EFLAGS TF by setting IA32_FMASK TF bit 8 For the steppings affected see the Summary Tables of Changes Code Segment Limit Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts Exceptions and May Push the Wrong Address Onto the Stack
72. es For the steppings affected see the Summary Tables of Changes Code Segment Limit Violation May Occur On 4 Gigabyte Limit Check Code Segment limit violation may occur on 4 Gigabyte limit check when the code stream wraps around in a way that one instruction ends at the last byte of the segment and the next instruction begins at 0x0 Implication This is a rare condition that may result in a system hang Intel has not observed this Workaround Status 48 erratum with any commercially available software or system Avoid code that wraps around segment limit For the steppings affected see the Summary Tables of Changes Specification Update Errata AH20 Problem Note Implication Workaround Status Specification Update ntel FP Inexact Result Exception Flag May Not Be Set When the result of a floating point operation is not exactly representable in the destination format 1 3 in binary form for example an inexact result precision exception occurs When this occurs the PE bit bit 5 of the FPU status word is normally set by the processor Under certain rare conditions this bit may not be set when this rounding occurs However other actions taken by the processor invoking the software exception handler if the exception is unmasked are not affected This erratum can only occur if one of the following FST instructions is one or two instructions after the floating point operation which causes th
73. f either MOV SS or STI storage of the PEBS record is delayed by one instruction When this erratum occurs software may observe storage of the PEBS record being delayed by one instruction following execution of MOV SS or STI The state information in the PEBS record will also reflect the one instruction delay None identified For the steppings affected see the Summary Tables of Changes Specification Update Errata 98 Problem Problem Problem Problem Implication Workaround Status Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code PF Code PF Page Fault exception is normally handled in lower priority order relative to both code DB Debug Exception and code Segment Limit Violation GP General Protection Fault Due to this erratum code PF may be handled incorrectly if all of the following conditions are met A PDE Page Directory Entry is modified without invalidating the corresponding TLB Translation Look aside Buffer entry Code execution transitions to a different code page such that both The target linear address corresponds to the modified PDE PTE Page Table Entry for the target linear address has A Accessed bit that is clear One of the following simultaneous exception conditions is present following the code transition Code DB and code PF Code Segment Limit Violation GP and code PF Softwa
74. g Stepping Affecting Only Intel Core 2 Duo Mobile Processor on Mobile Intel 965 Chipset Family LE Plan Fix VM Exit due to Virtual APIC Access VM Exit due to Virtual APIC Access Clear RF Clear RF AH2P Fixed VMCALL Failure Due to Corrupt MSEG Location May Cause VM Exit to Load the Machine State Incorrectly Fixed Fixed Function Performance Counters MSR PERF FIXED CTR1 30AH and MSR_PERF_FIXED 30BH are Not Cleared When the Processor is Reset AH4P No Fix Multi Core Processors Configured for Single Core Operation May Not be Able to Enter Intel Enhanced Sleep AHSP HEEL E Fixed Access May Lead to Access May Lead to a System Hang 0 Hang AH6P No Fix Activation of Intel Adaptive Thermal Monitor While Intel Dynamic Front Side Bus Frequency Switching is Active May lead to an Incorrect Operating Point Frequency NOTES 1 Errata with a P designation are specific to the Intel Core 2 Duo Mobile Processor for the Mobile Intel 965 Express Chipset Family Specification Update 35 b tel Summary Tables of Changes Errata for Intel Celeron Processor 500 Series for Platforms Based on Mobile Intel 965 Express Chipset Family ea ee 000000 0000 Fix Writing the Local Vector Table LVT When Interrupt Is Pending May Cause an Unexpected Interrupt AH1 X X No Fix OCK Asserted During a Special C
75. gnals may be driven asynchronously 4 Refer to the PWRGOOD definition for more details regarding the behavior of this signal 5 Length of assertion for PROCHOT does not equal thermal control circuit TCC activation time Time is required after the assertion or deassertion of PROCHOT for the processor to enable or disable the Additionally time is allocated after the assertion or deassertion of PROCHOT for the processor to complete current instruction execution This specification applies to PROCHOT as both an input if enabled and an output Equivalent to 2 PCI clocks duration 27 Measured between 0 3 VCCP and 0 7 VCCP 8 This specification requires thatthe VID BSEL signals sampled no earlier than 10 ps after V at V voltage and Vece are stable 9 STPCLK SLP DPSLP must be inactive and must toggle 10 This signal defines the latest time between Voca Veco and Vec cope ramp to stable VID valid 11 Parameter must be measured after the last of Vcc Voca and Vecs are stable and there is no ringing around the measured voltage 12 It may take up to 250 ys to identify the assertion of the external PROCHOT signal and additional 250 ps to reach the low power state after identifying its assertion 13 THERMTRIP functionality not guaranteed if PWRGOOD is not asserted 14 Customer platform must handle thermal control this period and should not use the THERMTRIP functi
76. hen all of the following conditions occur The processor is running in VMX non root as a 64 bit mode guest e The CR8 load existing VM execution control is 0 and the use TPR shadow VMexecution is 1 e Both BTF Single Step On Branches bit 1 of the IA32_DEBUGCTL MSR 1D9H Register and the TF Trap Flag bit 8 of the RFLAGS Register are set e MOV CR8 reg attempts to program a TPR Task Priority Register value that is below the TPR threshold and causes a VM exit A Virtual Machine will sample the BS bit and will incorrectly inject a Single Step trap to the guest A Virtual Machine Monitor must manually disregard the BS bit in the Guest State Area in case of a VM exit due to a TPR value below the TPR threshold For the steppings affected see the Summary Tables of Changes Specification Update Errata AH75 Problem Implication Workaround Status AH76 Problem Implication Workaround Status AH77 Problem Implication Workaround Status BO B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint BO B3 bits breakpoint conditions detect flags bits 3 0 in DR6 may not be properly cleared when the following sequence happens 1 instruction to SS Stack Segment selector 2 Next instruction is FP Floating Point that gets FP assist followed by code breakpoint BO B3 bits in DR6 may not be properly cleared None identified For the steppings
77. hermal Interrupts No Fix Count Value for Performance Monitoring Counter PMH PAGE WALK May Be Incorrect LER MSRs May be Incorrectly Updated X No Fix Performance Monitoring Events for Retired Instructions COH May Not Be Accurate No Fix Performance Monitoring Event For Number Of Reference X Cycles When The Processor Is Not Halted 3CH Does Not Count According To The Specification x Fixed Using 2M 4M Pages When A20M 15 Asserted May Result Incorrect Address Translations No Fix Writing Shared Unaligned Data that Crosses a Cache Line X X X without Proper Semaphores or Barriers May Expose a Memory Ordering Issue 22 Specification Update ERE X Event CFH BE f X X X X X X X X X X X X X X X X Summary Tables of Changes tel Stepping Stepping Stepping ERRATA X X No Fix Code Segment Limit Violation May Occur On 4 Gigabyte Limit Check X X X Plan Fix FP Inexact Result Exception Flag May Not Be Set X X Plan Fix Global Pages in the Data Translation Look Aside Buffer DTLB May Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM i X X Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory Ordering Violations Fixed VMCALL to Activate Dual monitor Treatment of SMIs and SMM Ignores Reserved
78. hronized XMC operation would be terminated by the operating system In order to avoid this erratum programmers should use the XMC synchronization algorithm as detailed in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3 System Programming Guide Section Handling Self and Cross Modifying Code Fixed For the steppings affected see the Summary Tables of Changes MSRs Actual Frequency Clock Count IA32 APERF or Maximum Frequency Clock Count IA32 MPERF May Contain Incorrect Data after a Machine Check Exception MCE When an MCE occurs during execution of a RDMSR instruction for MSRs Actual Frequency Clock Count IA32_APERF or Maximum Frequency Clock Count IA32_MPERF the current and subsequent RDMSR instructions for these MSRs may contain incorrect data After an MCE event accesses to the IA32 APERF IA32 MPERF MSRs may return incorrect data A subsequent reset will clear this condition None identified For the steppings affected see the Summary Tables of Changes Specification Update 55 5 Problem Implication Workaround Status AH36 Problem Implication Workaround Status AH37 Problem Implication Workaround Status 56 Errata Incorrect Address Computed For Last Byte of FXSAVE FXRSTOR Image Leads to Partial Memory Update A partial memory state save of the 512 byte FXSAVE image or a partial memory state restore of the FXRSTOR image m
79. in Wrong Program Order X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Fix Single Step Interrupts with Floating Point Exception Pending Be Mishandled AH85 Fixed CPUID Reports Architectural Performance Monitoring Version 2 is Supported When Only Version 1 Capabilities are Available AH86 AH87 X No Fix Unaligned Accesses to Paging Structures May Cause the Processor to Hang X X AH89 X X No Fix INVLPG Operation for Large 2 4 Pages be Incomplete under Certain Conditions AH90 X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault AH91 X Fixed Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior AH92 Fixed Invalid Instructions May Lead to Unexpected Behavior AH93 X No Fix EFLAGS CRO CR4 and the EXF4 Signal May be Incorrect after Shutdown Fixed Performance Monitoring Counter MACRO INSTS DECODED May Not Count Some Decoded Instructions Fixed The Stack May be Incorrect as a Result of VIP VIF Check on SYSEXIT and SYSRET AH96 No Fix Performance Monitoring Event SIMD UOP TYPE EXEC MUL is AH94 i Counted Incorrectly for PMULUDQ Instruction i No Fix Microcode Updates Performed During VMX Non root Operation Could Result in Unexpected Behavior AH95 AH97 No Fix of PEBS Record Delayed Following Execution of MOV SS AH98 No Fix Updating Code Pag
80. ing VMX non root operations if not explicitly prevented by the host software Microcode updates performed in non root operation may result in unexpected system behavior Host software should intercept and prevent loads to IA32_BIOS_UPDT_TRIG MSR 79H during VMX non root operations There are two mechanism that can be used 1 Enabling MSR access protection in the VM execution controls or 2 Enabling selective MSR protection of IA32_BIOS_UPDT_TRIG MSR For the steppings affected see the Summary Tables of Changes INVLPG Operation for Large 2M 4M Pages May Be Incomplete under Certain Conditions The INVLPG instruction may not completely invalidate Translation Look aside Buffer TLB entries for large pages 2 M 4 M when both of the following conditions exist e Address range of the page being invalidated spans several Memory Type Range Registers MTRRs with different memory types specified e INVLPG operation is preceded by a Page Assist Event Page Fault PF or an access that results in either A or D bits being set in a Page Table Entry PTE Stale translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior Intel has not observed this erratum with any commercially available software Software should ensure that the memory type specified in the MTRRs is the same for the entire address range of the large page For the steppings affected see the Summary Tables of Changes Specification Up
81. intel Intel Core 2 Duo and Intel Core 2 Solo Processor for Intel Centrino Duo Processor Technology Intel Celeron Processor 500 Series Specification Update Including Intel Core 2 Duo Extreme Edition Processors March 2010 Revision 024 Doc 314079 024 INFORMATION THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
82. ions AH117 No Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Specification Update 27 tel Summary Tables of Changes Stepping Stepping Stepping ERRATA Ear NMIs may not be blocked by a VM Entry failure X X No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Problem X X No Fix IA32 1 STATUS MSR Bit 60 Does Not Reflect Machine Check Error Reporting Enable Correctly X X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode No Fix FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4 Gbyte Boundary in Code That Uses 32 Bit Address Size in 64 bit Mode ER 28 Specification Update Summary Tables of Changes tel Errata for Intel Core 2 Duo Processors for Platforms Based on Mobile Intel 965 Express Chipset Family Stepping Stepping Stepping ERRATA mf No Fix Writing the Local Vector Table LVT When an Interrupt Is Pending May Cause an Unexpected Interrupt X No Fix LOCK Asserted During a Special Cycle Shutdown Transaction May Unexpectedly Deassert No Fix Address Reported by Machine Check Architecture MCA on Single bit L2 ECC Errors May Be Incorrect No Fix VERW VERR LSL LAR Instructions May Unexpectedly Update the Last Exception Record LER MSR Instruction May Inco
83. irtualization Technology can execute VMCALL from within the Virtual Machine Monitor VMM to activate dual monitor treatment of SMIs and SMM Due to this erratum if reserved bits are set to values inconsistent with VMX Capability MSRs VMCALL may not VMFail VMCALL executed to activate dual monitor treatment of SMIs and SMM may not VMFail due to incorrect reserved bit settings in VM Exit control field Software should ensure that all VMCS reserved bits are set to values consistent with VMX Capability MSRs For the steppings affected see the Summary Tables of Changes Specification Update Errata AH24 Problem Implication Workaround Status AH25 Problem Problem Implication Workaround Status REP MOVS STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory Ordering Violations Under certain conditions as described in the Intel 64 and IA 32 Architectures Software Developer s Manual section Out of Order Stores For string operations in Pentium 4 Intel Xeon and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings Due to this erratum fast string REP MOVS REP STOS instructions that cross page boundaries from WB WC memory types to UC WP WT memory types may start using an incorrect data size or may observe memory ordering violations Upon crossing the page boundary the following
84. karound Status AH104 Problem Implication Workaround Status AH105 Problem Implication Workaround Status 82 Errata Performance Monitoring Event MISALIGN_MEM_REF May Over Count Performance monitoring event MISALIGN_MEM_REF 05H is used to count the number of memory accesses that cross an 8 byte boundary and are blocked until retirement Due to this erratum the performance monitoring event MISALIGN_MEM_REF also counts other memory accesses The performance monitoring event MISALIGN_MEM_REF may over count The extent of the over counting depends on the number of memory accesses retiring while the counter is active None Identified For the steppings affected see the Summary Tables of Changes A REP STOS MOVS to a MONITOR MWAIT Address Range May Prevent Triggering of the Monitoring Hardware The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction The hardware is triggered on subsequent memory store operations to the monitored address range Due to this erratum REP STOS MOVS fast string operations to the monitored address range may prevent the actual triggering store to be propagated to the monitoring hardware A logical processor executing an MWAIT instruction may not immediately continue program execution if a REP STOS MOVS targets the monitored address range Software can avoid this erratum by not using REP STOS MOVS store operations within the moni
85. l Volume 3B System Programming Guide Doc 253669 IA 32 Intel Architecture Optimization Reference Manual Doc 248966 Intel Processor Identification and the CPUID Instruction Application Note AP 485 Doc 241618 Intel 64 and IA 32 Architectures Application Note TLBs Paging Structure Caches and Their Invalidation Doc 317080 http www intel com products processor manuals index htm http www intel com products processor manuals index htm http www intel com products processor manuals index htm http developer intel com design processor applnots 241618 htm http www intel com design processor applnots 317080 pdf Nomenclature Note S Spec Number is a five digit code used to identify products Products are differentiated by their unique characteristics for example core speed L2 cache size package type etc as described in the processor identification information table Care should be taken to read all notes associated with each S Spec number QDF Number is a several digit code that is used to distinguish between engineering samples These processors are used for qualification and early design validation The functionality of these parts can range from mechanical only to fully functional The NDA specification update has a processor identification information table that lists these QDF numbers and the corresponding product sample details Errat
86. less LAN access points is limited wireless functionality may vary by country and some hotspots may not support Linux based Intel Centrino mobile technology systems See www intel com products centrino for more information Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Intel Core2 Duo Intel Core2 Solo Intel Centrino Duo Intel SpeedStep MMX and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2006 2010 Intel Corporation All rights reserved 2 Specification Update Contents zoe p 7 Identification Information 1 ner neben Rer rei ix REBEL a EA 10 Summary Tables of Changeset PERDRE d PER Cid 19 c p TP aE san 42 Specification CHANGES vies sk essai gia a EEEO REEE 94 Specification ClarificatiOns xe E OE EE PINDOT 96 Documentation Changes OU URS 97 Specification Update 3 Revision History Document Revision Version Description Date Number 594274 001 1 0 Initial release of Intel Core 2 Duo Proces
87. lication Workaround Status 62 Errata IO SMI Indication in SMRAM State Save Area May Be Set Incorrectly The IO SMI bit in SMRAM s location 7FA4H is set to 1 by the CPU to indicate System Management Interrupt SMI occurred as the result of executing an instruction that reads from an I O port Due to this erratum the IO SMI bit may be incorrectly set by e Anon I O instruction e SMI is pending while a lower priority event interrupts e REP I O read e An I O read that redirects to MWAIT e systems supporting Intel Virtualization Technology a fault in the middle of an IO operation that causes a VM Exit SMM handlers may get false IO SMI indication The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I O port The SMM handler must not restart an I O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I O port address For the steppings affected see the Summary Tables of Changes INIT Does Not Clear Global Entries in the TLB INIT may not flush a TLB entry when e The processor is in protected mode with paging enabled and the page global enable flag is set PGE bit of CR4 register e G bit for the page table entry is set e TLB entry is present TLB when INIT occurs Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left
88. ly AH63 Removed Erratum AH64 X X X No Fix Returning to Real Mode from SMM with EFLAGS VM Set May Result in Unpredictable System Behavior AH65 X X Plan Fix VMLAUNCH VMRESUME May Not Fail When VMCS Is Programmed to Cause VM Exit to Return to a Different Mode AH66 X X X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception AH67 X X X No Fix Performance Monitoring Event FP ASSIST May Not Be Accurate AH68 X X X Plan Fix CPL Qualified BTS May Report Incorrect Branch From Instruction Address X PEBS Does Not Always Differentiate Between CPL Qualified Events PMI May Be Delayed to Next PEBS Event X Plan Fix PEBS Buffer Overflow Status Will Not Be Indicated Unless 2 DEBUGCTL 12 Is Set No Fix The BS Flag in DR6 May Be Set for Non Single Step DB Exception AH73 EN Asynchronous MCE during a Far Transfer Corrupt ESP 69 70 71 X X will be Incorrectly Set by VM Exit on a MOV to CR8 Instruction No Fix BO B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint X X AH74 X Plan Fix In Single Stepping on Branches Mode the BS Bit in the Pending Debug Exceptions Field of the Guest State Area AH75 X X AH76 No Fix BTM BTS Branch From Instruction Address May Be Incorrect for Software Interrupts AH77 X Plan Fix REP Store Instructions in a Specific Situation May Cause the Processor to Hang Specification Update 25 AH72
89. m AH120 X x X No Fix IA32 MC1 STATUS MSR Bit 60 Does Not Reflect Machine Check Error Reporting Enable Correctly Code Segment Limit Canonical Faults on RSM May be Serviced X X X No Fix before Higher Priority Interrupts Exceptions and May Push the Wrong Address Onto the Stack FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4 Gbyte Boundary in Code That Uses 32 Bit Address Size in 64 bit Mode Number SPECIFICATION CHANGES mere are no Specification Changes in this Specification Update revision Number SPECIFICATION CLARIFICATIONS AH3 Clarification of TRANSLATION LOOKASIDE BUFFERS TLBS Invalidation Number DOCUMENTATION CHANGES rere are no Documentation Changes in this Specification Update revision Specification Update 41 Errata Errata AH1 Problem Implication Workaround Status AH2 Problem Implication Workaround Status AH3 Problem Implication Workaround Status 42 Writing the Local Vector Table LVT When an Interrupt Is Pending May Cause an Unexpected Interrupt If a local interrupt is pending when the LVT entry is written an interrupt may be taken on the new interrupt vector even if the mask bit is set An interrupt may immediately be generated with the new vector when a LVT entry is written even if the new LVT entry has the mask bit set If there is no Interrupt Service Routine ISR se
90. m with a MOV ESP instruction Do not attempt to put a breakpoint on MOVSS and POPSS instructions that are followed by a SYSRET For the steppings affected see the Summary Tables of Changes Single Step Interrupts with Floating Point Exception Pending May Be Mishandled In certain circumstances when a floating point exception MF is pending during single step execution processing of the single step debug exception DB may be mishandled When this erratum occurs DB will be incorrectly handled as follows e DB is signaled before the pending higher priority MF Interrupt 16 e DB is generated twice on the same instruction None Identified For the steppings affected see the Summary Tables of Changes Specification Update 73 AH84 Problem Implication Workaround Status AH85 Problem Implication Workaround Status AHS6 Problem Implication Workaround Status 74 Errata Non Temporal Data Store May Be Observed in Wrong Program Order When non temporal data is accessed by multiple read operations in one thread while another thread performs a cacheable write operation to the same address the data stored may be observed in wrong program order i e later load operations may read older data Software that uses non temporal data without proper serialization before accessing the non temporal data may observe data in wrong program order Software that conforms to the Intel 64 an
91. memory access wraps a 4 Gbyte boundary and the FP environment is subsequently saved the value contained in the FP Data Operand Pointer may be incorrect Due to this erratum the FP Data Operand Pointer may be incorrect Wrapping an 80 bit FP load around a 4 Gbyte boundary in this way is not a normal programming practice Intel has not observed this erratum with any commercially available software If the FP Data Operand Pointer is used in a 64 bit operating system which may run code accessing 32 bit addresses care must be taken to ensure that no 80 bit FP accesses are wrapped around a 4 Gbyte boundary Specification Update 89 intel Pu Status For the steppings affected see the Summary Table of Changes 90 Specification Update Errata Erratum Affecting Only Intel Core 2 Duo Mobile Processors on Mobile Intel 965 Express Chipset Family Problem Implication Workaround Status AH2P Problem Implication Workaround Status AH3P Problem Implication Workaround Status VM Exit Due to Virtual APIC Access May Clear RF RF Resume Flag bit 16 of the EFLAGS RFLAGS register is used to restart instruction execution without getting an instruction breakpoint on the instruction following a debug breakpoint exception Due to this erratum in a system supporting Intel Virtualization Technology when a VM Exit occurs due to Virtual APIC Access Advanced Programmable Interrupt
92. ndler the processor will no longer be in VM86 mode Normally operating systems should prevent interrupt task switches from faulting thus the scenario should not occur under normal circumstances None Identified For the steppings affected see the Summary Tables of Changes Specification Update Errata 50 Problem Implication Workaround Status AH51 Problem Implication Workaround Status AH52 Problem Implication Workaround Status intel IA32 FMASK Is Reset during an INIT IA32 FMASK MSR 0xC0000084 is reset during INIT If an INIT takes place after IA32 FMASK is programmed the processor will overwrite the value back to the default value Operating system software should initialize IA32 FMASK after INIT For the steppings affected see the Summary Tables of Changes An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception A MOV SS POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction This is intended to allow the sequential execution of MOV SS POP SS and MOV r e SP r e BP instructions without having an invalid stack during interrupt handling However an enabled debug breakpoint or single step trap may be taken after MOV SS POP SS if this instruction is followed by an instruction that sign
93. nformation Identification Information Component Identification via Programming Interface The Intel Core 2 Duo mobile processor and Intel Celeron Processor 500 series stepping can be identified by the following register contents 0110 1111 10000 1 The family corresponds to bits 11 8 of the EDX register after RESET bits 11 8 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the generation field of the Device ID registers accessible through boundary scan 2 The model corresponds to bits 7 4 of the EDX register after RESET bits 7 4 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the model field of the device ID registers accessible through boundary scan Cache and TLB descriptor parameters are provided in the EAX EBX ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register Refer to the Intel Processor Identification and the CPUID Instruction Application Note AP 485 and the latest Inte Core 2 Duo Mobile Processor BIOS Writer s Guide for further information on the CPUID instruction Each stepping of the Intel Core 2 Duo mobile processor can be identified by software with its CPU signature Table 1 CPU Signature for the Intel Core 2 Duo Mobile Processor Stepping CPU Signature B 2 O6F6h L 2 O6F2h G 2 O6FBh Each stepping of the Intel Celeron Processor 500 series can be i
94. ng back from SMM mode into real mode while EFLAGS VM is set in SMRAM may result in unpredictable system behavior If SMM software changes the values of the EFLAGS VM in SMRAM it may result in unpredictable system behavior Intel has not observed this behavior in commercially available software SMM software should not change the value of EFLAGS VM in SMRAM For the steppings affected see the Summary Tables of Changes VMLAUNCH VMRESUME May Not Fail when VMCS Is Programmed to Cause VM Exit to Return to a Different Mode VMLAUNCH VMRESUME instructions may not fail if the value of the host address space size VM exit control differs from the setting of IA32 EFER LMA Programming the VMCS to allow the monitor to be in different modes prior to VMLAUNCH VMRESUME and after VM exit may result in undefined behavior Software should ensure that host address space size VM exit control has the same value as IA32_EFER LMA at the time of VMLAUNCH VMRESUME For the steppings affected see the Summary Tables of Changes IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception In IA 32e mode it is possible to get an Alignment Check Exception AC on the IRET instruction even though alignment checks were disabled at the start of the IRET This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code IRETs from CPLO 1 2 are not affected This erratum can occur if the EFLAGS value on the stack has the
95. ng out of reset For the steppings affected see the Summary Tables of Changes Performance Monitoring Event FP MMX TRANS TO Not Count Some Transitions Performance Monitor Event FP MMX TRANS TO MMX Event CCH Umask O1H counts transitions from x87 Floating Point FP to MMX instructions Due to this erratum if only a small number of MMX instructions including EMMS are executed immediately after the last FP instruction a FP to MMX transition may not be counted The count value for Performance Monitoring Event FP MMX TRANS TO MMX may be lower than expected The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active Intel has not observed this erratum with any commercially available software None Identified For the steppings affected see the Summary Tables of Changes Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops Due to this erratum a livelock may occur Intel has not observed this erratum with any commercially available software It is possible for BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update 85 AH113 Problem Implication Workaround Status AH114 Problem Implication Workaround Status 86 Err
96. nt may cause a TS invalid TSS exception instead of a GP fault general protection exception Operation systems that access a busy TSS may get invalid TSS fault instead of a GP fault Intel has not observed this erratum with any commercially available software None Identified For the steppings affected see the Summary Tables of Changes Removed Erratum Specification Update Errata AH11 Problem Implication Workaround Status AH12 Problem Implication Workaround Status 13 Problem Implication Workaround Status A Write to an APIC Register Sometimes May Appear to Have Not Occurred With respect to the retirement of instructions stores to the uncacheable memory based APIC register space are handled in a non synchronized way For example if an instruction that masks the interrupt flag for example CLI is executed soon after an uncacheable write to the Task Priority Register TPR that lowers the APIC priority the interrupt masking operation may take effect before the actual priority has been lowered This may cause interrupts whose priority is lower than the initial TPR but higher than the final TPR to not be serviced until the interrupt enabled flag is finally set that is by STI instruction Interrupts will remain pending and are not lost In this example the processor may allow interrupts to be accepted but may delay their service This non synchronization can be av
97. nter MACRO INSTS DECODED May Not Count Some Decoded Instructions Problem MACRO INSTS DECODED performance monitoring counter Event OAAH Umask O1H counts the number of macro instructions decoded but not necessarily retired The event is undercounted when the decoded instructions are a complete loop iteration that is decoded in one cycle and the loop is streamed by the LSD Loop Stream Detector as described the Optimizing the Front End section of the Intel 64 and IA 32 Architectures Optimization Reference Manual Implication The count value returned by the performance monitoring counter MACRO INST DECODED may be lower than expected The degree of undercounting is dependent on the occurrence of loop iterations that are decoded in one cycle and whether the loop is streamed by the LSD while the counter is active Workaround None identified Status For the steppings affected see the Summary Tables of Changes AH95 The Stack May Be Incorrect as a Result of VIP VIF Check on SYSEXIT and SYSRET Problem The stack size may be incorrect under the following scenario Problem 1 The stack size was changed due to a SYSEXIT or SYSRET Problem 2 PVI Protected Mode Virtual Interrupts mode was enabled CR4 PVI 1 Problem 3 Both the VIF Virtual Interrupt Flag and VIP Virtual Interrupt Pending flags of the EFLAGS register are set Implication If this erratum occurs the stack size may be incorrect consequently this may result in
98. ock or hang or RSM instruction may restart the interrupted processor context through a nondeterministic EIP offset in the code segment resulting in unexpected instruction execution unexpected exceptions or system hang Intel has not observed this erratum with any commercially available software It is possible for the BIOS to contain a workaround for this erratum Please contact your Intel sales representative for availability For the steppings affected see the Summary Tables of Changes NMIs May Not Be Blocked by a VM Entry Failure The Intel 64 IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Part 2 specifies that following a VM entry failure during or after loading guest state the state of blocking by NMI is what it was before VM entry If non maskable interrupts NMIs are blocked and the virtual NMIs VM execution control set to 1 this erratum may result in NMIs not being blocked after a VM entry failure during or after loading guest state VM entry failures that cause NMIs to become unblocked may cause the processor to deliver an NMI to software that is not prepared for it VMM software should configure the virtual machine control structure VMCS so that VM entry failures do not occur For the steppings affected see the Summary Tables of Changes Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown According to the Intel 64 and IA 32 Architectures
99. oided by issuing an APIC register read after the APIC register write This will force the store to the APIC register before any subsequent instructions are executed No commercial operating system is known to be impacted by this erratum For the steppings affected see the Summary Tables of Changes Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected Thermal Interrupts Software can enable DTS thermal interrupts by programming the thermal threshold and setting the respective thermal interrupt enable bit When programming DTS value the previous DTS threshold may be crossed This generates an unexpected thermal interrupt Software may observe an unexpected thermal interrupt occur after reprogramming the thermal threshold In the ACPI OS implement a workaround by temporarily disabling the DTS threshold interrupt before updating the DTS threshold value For the steppings affected see the Summary Tables of Changes Count Value for Performance Monitoring Counter PMH_PAGE_WALK May Be Incorrect Performance Monitoring Counter PMH_PAGE_WALK is used to count the number of page walks resulting from Data Translation Look Aside Buffer DTLB and Instruction Translation Look Aside ITLB misses Under certain conditions this counter may be incorrect There may be small errors in the accuracy of the counter None identified For the steppings affected see the Summary Tables of Changes Specification Update 45 14
100. on The BS flag may be incorrectly set for non single step DB exception Workaround None identified Status For the steppings affected see the Summary Tables of Changes Specification Update 69 AH73 Problem Implication Workaround Status AH74 Problem Implication Workaround Status 70 Errata An Asynchronous MCE During a Far Transfer May Corrupt ESP If an asynchronous machine check occurs during an interrupt call through gate FAR RET or IRET and in the presence of certain internal conditions ESP may be corrupted If the MCE Machine Check Exception handler is called without a stack switch then a triple fault will occur due to the corrupted stack pointer resulting in a processor shutdown If the MCE is called with a stack switch for example when the CPL Current Privilege Level was changed or when going through an interrupt task gate then the corrupted ESP will be saved on the stack or in the TSS Task State Segment and will not be used Use an interrupt task gate for the machine check handler For the steppings affected see the Summary Tables of Changes In Single Stepping on Branches Mode the BS Bit in the Pending Debug Exceptions Field of the Guest State Area Will Be Incorrectly Set by VM Exit on a MOV to CR8 Instruction In a system supporting Intel Virtualization Technology the BS bit bit 14 of the Pending Debug Exceptions field in the guest state area will be incorrectly set w
101. onality of the processor 15 For Penryn processor Vec soor stable to PWRGOOD assertion should not exceed 510ms Please refer to the Penryn Processor in Santa Rosa Electrical Mechanical and Thermal Specification for more details Specification Update 95 Specification Clarifications Specification Clarifications AH1 AH2 96 Removed Removed Clarification of TRANSLATION LOOKASIDE BUFFERS TLBS Invalidation Section 10 9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS TLBS of the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide will be modified to include the presence of page table structure caches such as the page directory cache which Intel processors implement This information is needed to aid operating systems in managing page table structure invalidations properly Intel will update the Inte 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide in the coming months Until that time an application note TLBs Paging Structure Caches and Their Invalidation http www intel com products processor manuals index htm is available which provides more information on the paging structure caches and TLB invalidation In rare instances improper TLB invalidation may result in unpredictable system behavior such as system hangs or incorrect data Developers of operating systems should take this documentation into account when
102. ons in Pentium 4 Intel Xeon and P6 Family Processors the processor may perform REP MOVS or REP STOS as write combining stores referred to as fast strings for optimal performance FXSAVE may also be internally implemented using write combining stores Due to this erratum stores of a WB write back memory type to a cache line previously written by a preceding fast string FXSAVE instruction may be observed before string FXSAVE stores A write back store may be observed before a previous string or FXSAVE related store Intel has not observed this erratum with any commercially available software Software desiring strict ordering of string FXSAVE operations relative to subsequent write back stores should add an MFENCE or SFENCE instruction between the string FXSAVE operation and following store order sensitive code such as that used for synchronization For the steppings affected see the Summary Tables of Changes Specification Update Errata AH115 Problem Implication Workaround Status 116 Problem Implication Workaround Status VM Exit with Exit Reason TPR Below Threshold Can Cause the Blocking by MOV POP SS and Blocking by STI Bits to Be Cleared in the Guest Interruptibility State Field As specified in Section VM Exits Induced by the TPR Shadow in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B a VM exit occurs immediately after any VM entry performed
103. or PEBS records cannot specify the DS debug store save area within the APIC access page Under any expected usage model this type of overlap is not expected to exist One should be aware of the fact that the specified DS address is of linear form while the APIC access page is of a physical form Any solution that wishes to avoid this condition will need to comprehend the linear to physical translation of the DS related address pointers with respect to the mapping of the physical APIC access page to avoid such an overlap Under normal circumstances for correctly written software such an overlap is not expected to exist Intel has not observed this erratum with any commercially available software For a fully comprehensive workaround the VMM should not allow the logging of branch or PEBS records while guest software is running if the virtualize APIC accesses VM execution control is 1 For the steppings affected see the Summary Tables of Changes VTPR Write Access during Event Delivery May Cause an APIC Access VM Exit VTPR write accesses should not cause APIC access VM exits but instead should cause data to be written to the virtual APIC page Due to this erratum a VTPR write access during event delivery may cause an APIC access VM exit with no data being written to the virtual APIC page VTPR accesses are accesses to offset 80H on the APIC access page VTPR write accesses can occur during event delivery when pushing data on the stack Beca
104. oup 1 Line 2 pa Group 2 Line 1 Group 2 Line 2 SAMPLE MARK EXAMPLE Group 1 Line 1 Unit Identifier Group 1 Line 2 FPO S Spec Group 2 Line 1 INTEL 05 Group 2 Line 2 ATPO Serial Number For Pb Free Group 2 Line 1 INTEL m 05 e1 12 Specification Update Identification Information D Table 3 Intel Core 2 Duo Processor Mobile Intel 945 Express Chipset Family Component Markings Processor Package Processor Number Stepping T7600 Micro FCPGA T7600 Micro FCBGA T7400 Micro FCPGA T5500 Micro FCPGA Specification Update 13 tel Identification Information 14 QDF Processor Package Processor S Spec Number Stepping 1 Intel Core 2 Duo processor Standard Voltage with 4 L2 cache 2 Intel Core 2 Duo processor Standard Voltage with 2 L2 cache 3 Vcc cone 1 250 1 075 0 95 0 85 V for Highest Lowest HFM LFM Deeper Sleep VID 0 75 0 65 V Intel Enhanced Deeper Sleep VID 0 65 V Intel Core 2 Duo processor Low Voltage with 4 M L2 cache Intel Core 2 Duo processor Ultra Low Voltage with 2 L2 cache Intel Core 2 Solo processor Ultra Low Voltage with 1 M L2 cache oe Table 2 Intel Core 2 Duo Processor Mobile Intel 965 Express Chipset Family Component Markings Speed Processor Processor IDA HFM L Number Stepping FM SLFM QXJJ T7700 Micro FCPGA QXJK T7500 Micro FCPGA icro
105. ppings affected see the Summary Tables of Changes Specification Update 51 26 Problem Implication Workaround Status AH27 Problem Implication Workaround Status 52 Errata Premature Execution of a Load Operation Prior to Exception Handler Invocation If any of the below circumstances occur it is possible that the load portion of the instruction is executed before the exception handler is entered 1 If an instruction that performs a memory load causes a code segment limit violation 2 Ifa waiting X87 floating point FP instruction or MMX technology instruction that performs a memory load has a floating point exception pending 3 If an MMX or SSE SSE2 SSE3 SSSE3 extensions SSE instruction that performs a memory load and has either CRO EM 1 Emulation bit set or a floating point Top of Stack FP TOS not equal to 0 or a DNA exception pending In normal code execution where the target of the load operation is to write back memory there is no impact from the load being prematurely executed or from the restart and subsequent re execution of that instruction by the exception handler If the target of the load is to uncached memory that has a system side effect Particularly while CRO TS bit 3 is set MOVD MOVQ with MMX XMM register operands may issue a memory load before getting the DNA exception Code which performs loads from memory that has side effects can effectively workaround this beha
106. r the latest Chipset Family Electrical Mechanical and Thermal revision Specification EMTS Intel Core 2 Duo Mobile Processor for Intel Centrino Contact your Intel Duo Technology Electrical Mechanical and Thermal representative for the latest Specification EMTS revision Intel Celeron Processor 500 Series for Platforms Based on 316205 Mobile Intel 965 Express Chipset Family Datasheet Related Documents Document Title Location Doc number http www intel com design processor specupdt 252046 htm Intel 64 and IA 32 Architectures Software Developer s http www intel com Manual Volume 1 Basic Architecture Doc 253665 products processor manuals Intel 64 and IA 32 Architectures Software Developer s Manual Documentation Changes Doc 252046 index htm Intel 64 and IA 32 Architectures Software Developer s http www intel com Manual Volume 2A Instruction Set Reference A M manuals Doc 253666 index htm Intel 64 IA 32 Architectures Software Developer s http www intel com Manual Volume 2B Instruction Set Reference N Z products processor manuals Doc 253667 index htm Specification Update 7 Document Title Location Doc number Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Doc 253668 Intel 64 and IA 32 Architectures Software Developer s Manua
107. re may observe either incorrect processing of code PF before code Segment Limit Violation GP or processing of code PF in lieu of code DB None identified For the steppings affected see the Summary Tables of Changes Specification Update 79 AH99 Problem Implication Workaround Status AH100 Problem Implication Workaround Status 80 Errata Performance Monitoring Event CPU CLK UNHALTED REF Not Count Clock Cycles According to the Processors Operating Frequency Performance Counter PERF FIXED CTR2 MSR 30BH that counts CPU UNHALTED REF clocks should count these clock cycles at a constant rate that is determined by the maximum resolved boot frequency as programmed by BIOS Due to this erratum the rate is instead set by the maximum core clock to bus clock ratio of the processor as indicated by hardware No functional impact as a result of this erratum If the maximum resolved boot frequency as programmed by BIOS is different from the frequency implied by the maximum core clock to bus clock ratio of the processor as indicated by hardware then the following effects may be observed Performance Monitoring Event CPU CLK UNHALTED REF will count at a rate different than the TSC Time Stamp Counter e When running a system with several processors that have different maximum core clock to bus clock ratios CPU CLK UNHALTED REF monitoring events at each processor will be counted at
108. references a large page e A20M is enabled When A20M is enabled and an address references a large page the resulting translated physical address may be incorrect This erratum has not been observed with any commercially available operating system Operating systems should not allow A20M to be enabled if the masking of address bit 20 could be applied to an address that references a large page 20 is normally only used with the first megabyte of memory For the steppings affected see the Summary Tables of Changes Specification Update 47 18 Problem Implication Workaround Status AH19 Problem Errata Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter Exposure to this problem requires the use of a data write which spans a cache line boundary This erratum may cause loads to be observed out of order Intel has not observed this erratum with any commercially available software or system Software should ensure at least one of the following is true when modifying shared data by multiple agents e The shared data is aligned e Proper semaphores or barriers are used in order to prevent concurrent data access
109. rocessor in 478 pin package AD Intel Celeron D processor on 65 nm process AE Intel Core Duo processor and Intel Core Solo processor on 65 nm process AF Dual Core Intel Xeon processor LV AG Dual Core Intel Xeon processor 51004 series AH Intel Core 2 Duo Solo processor for Intel Centrino Duo processor technology AI Intel Core 2 Extreme processor X6800 and Intel Core 2 Duo Desktop processor E6000 and E4000 sequence AJ Quad Core Intel Xeon processor 5300 series AK Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 Quad processor 06000 sequence AL Dual Core Intel Xeon processor 7100 series Specification Update Summary Tables of Changes tel AM Intel Celeron processor 400 sequence AN Intel Pentium Dual Core processor AO Quad Core Intel Xeon processor 3200 series AP Dual Core Intel Xeon processor 30007 series AQ Intel Pentium Dual Core Desktop processor E2000 sequence AR Intel Celeron Processor 500 series AS Intel Xeon processor 7200 7300 series AT Intel Celeron processor 200 series AV Intel Core 2 Extreme Processor QX9000 Sequence and Intel Core 2 Quad Processor Q9000 Sequence processor AX Quad Core Intel Xeon Processor 5400 Series AY Wolfdale DP 4 Intel processor numbers are not a measure of performance Processor numbers differentiate features within
110. rom SMRAM The Resume from System Management Mode RSM instruction does not flush global pages from the Data Translation Look Aside Buffer DTLB prior to reloading the saved architectural state If SMM turns on paging with global paging enabled and then maps any of linear addresses of SMRAM using global pages RSM load may load data from the wrong location Do not use global pages in system management mode For the steppings affected see the Summary Tables of Changes Sequential Code Fetch to Non canonical Address May Have Nondeterministic Results If code sequentially executes off the end of the positive canonical address space falling through from address 00007fffffffffff to non canonical address 0000800000000000 under some circumstances the code fetch will be converted to a canonical fetch at address ffff800000000000 Due to this erratum the processor may transfer control to an unintended address The result of fetching code at that address is unpredictable and may include an unexpected trap or fault or execution of the instructions found there If the last page of the positive canonical address space is not allocated for code 4K page at 00007ffffffffO00 or 2M page at 00007fffffe00000 then the problem cannot occur For the steppings affected see the Summary Tables of Changes VMCALL to Activate Dual monitor Treatment of SMIs and SMM Ignores Reserved Bit Settings in VM exit Control Field Processors supporting Intel V
111. rrata table e Updated Specification Clarifications Table e Added G 2 L7500 T7400 T7500 L7400 Processors e Added M 1 U7500 Processor e Added M 1 573 Processor e Added M 1 and G 2 stepping MCU for Intel Core 2 Duo Processors for Platforms based on the Intel 945 Express Chipset Family e Added M 1 stepping MCU for Intel Celeron Processor 500 series for Platforms based on the Intel 965 Express Chipset Family Added 0 07700 Processor e Updated 0 07500 07600 Processor 355615 024 1 0 e Added 122 March 2010 6 Specification Update Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents Related Documents table It is a compilation of device and document errata and specification clarifications and changes and is intended for hardware system manufacturers and for software developers of applications operating system and tools Information types defined in the Nomenclature section of this document are consolidated into this update document and are no longer published in other documents This document may also contain information that has not been previously published Affected Documents Document Title Document Number Location Intel Core 2 Duo Processors and Intel Core 2 Extreme Contact your Intel Processors for Platforms Based on Mobile Intel 965 Express representative fo
112. rratum may lead to livelock shutdown or other unexpected processor behavior Intel has not observed this erratum with any commercially available system It is possible for BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Invalid Instructions May Lead to Unexpected Behavior Invalid instructions due to undefined opcodes or instructions exceeding the maximum instruction length due to redundant prefixes placed before the instruction may lead under complex circumstances to unexpected behavior The processor may behave unexpectedly due to invalid instructions Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes Specification Update AH93 EFLAGS CRO CR4 and the EXF4 Signal May Be Incorrect after Shutdown Problem When the processor is going into shutdown due to an RSM inconsistency failure EFLAGS and 4 may be incorrect In addition the EXF4 signal may still be asserted This may be observed if the processor is taken out of shutdown by NMI Implication A processor that has been taken out of shutdown may have an incorrect EFLAGS CRO and CR4 In addition the EXF4 signal may still be asserted Workaround None identified Status For the steppings affected see the Summary Tables of Changes AH94 Performance Monitoring Cou
113. rrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired Event CFH Fixed SYSRET May Incorrectly Clear RF Resume Flag in the RFLAGS Register T No Fix DR3 Address Match on MOVD MOVQ MOVNTQ Memory Store No Fix General Protection Fault GP for Instructions Greater than 15 Bytes May Be Preempted No Fix Pending x87 FPU Exceptions MF Following STI May Be Serviced Before Higher Priority Interrupts Removed Erratum X No Fix A Write to APIC Register Sometimes May Appear to Have Not Occurred AH12 X X X No Fix Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected Thermal Interrupts AH13 No Fix Count Value for Performance Monitoring Counter PMH PAGE WALK E Se SL Be Incorrect ania Er No Fix LER MSRs May be LER MSRs be Incorrectly Updated Updated AH15 No Fix Performance Monitoring Events for Retired Instructions COH May Not Be Accurate AH16 No Fix Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted 3CH Does Not Count According To The Specification AH17 No Fix Using 2M 4M Pages When A20M Is Asserted May Result in Incorrect Address Translations AH18 No Fix Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Specification Update 29 Hf ff The Processor May Report a TS Instead of a GP Fault i
114. sor July 2006 Preliminary Specification Update NDA 594274 002 1 0 e Updated Sample Identification Table August 2006 e Updated Errata AH19 AH20 AH29 AH38 AH40 and AH62 e Added Errata AH63 to AH75 AH5S 594274 003 1 0 e Updated Errata AH68 AH69 AH71 AH74 September 2006 e Added Errata AH76 to AH82 AH6S e Added Specification Clarification on T75 T76 Specification Maximum delta between Intel Enhanced Deeper Sleep State and LFM on Intel Core 2 Duo Mobile Processor for Intel Centrino Duo Mobile Technology production parts based on B 2 stepping 594274 004 1 0 e Updated Errata AH46 AH53 and AH78 October 2006 e Added Errata AH83 AH84 AH85 and AH7S e Removed Erratum AH10 e Updated Related Documents Table Updated Component Marking Information Table 594274 005 1 0 e Updated Errata AH8 AH74 AH84 15 November 2006 e Added Errata AH86 AH87 AH88 AH89 and 90 Removed Erratum AH63 594274 006 1 0 e Updated Erratum AH7S December 2006 e Added Errata AH91 AH94 e Updated Summary Tables of Changes 594274 007 1 0 e Added Errata AH95 AH97 January 2007 e Updated Erratum AH69 e Added Erratum AH8S 594274 008 1 0 e Added Errata 98 100 February 2007 e Added L 2 stepping processor SKUs errata and MCU e Added Erratum AH9S 594274 009 1 0 e Corrected MCU for B 2 L 2 stepping March 2007 e Updated Erratum AH30 AH33 e Added Errata AH101 AH104 e Added new processor SKUs 594274 010 1 0 e Updated
115. state For the steppings affected see the Summary Tables of Changes Specification Update 65 60 Problem Implication Workaround Status AH61 Problem Implication Workaround Status AH62 Problem Implication Workaround Status 66 Errata LBR BTS BTM May Report a Wrong Address When an Exception Interrupt Occurs in 64 bit Mode An exception interrupt event should be transparent to the LBR Last Branch Record BTS Branch Trace Store and BTM Branch Trace Message mechanisms However during a specific boundary condition where the exception interrupt occurs right after the execution of an instruction at the lower canonical boundary 0x00007FFFFFFFFFFF in 64 bit mode the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1 s Subsequent BTS and BTM operations which report the LBR will also be incorrect LBR BTS and BTM may report incorrect information in the event of an exception interrupt None identified For the steppings affected see the Summary Tables of Changes A Thermal Interrupt Is Not Generated When the Current Temperature Is Invalid When the DTS Digital Thermal Sensor crosses one of its programmed thresholds it generates an interrupt and logs the event IA32_THERM_STATUS MSR 019Ch bits 9 7 Due to this erratum if the DTS reaches an invalid temperature as indicated IA32_THERM_STATUS MSR bit 31 i
116. sters in V86 mode a debug exception will be generated instead of the expected general protection fault In general operating systems do not set the GD bit when they are in V86 mode The GD bit is generally set and used by debuggers The debug exception handler should check that the exception did not occur in V86 mode before continuing If the exception did occur in V86 mode the exception may be directed to the general protection exception handler For the steppings affected see the Summary Tables of Changes Specification Update Errata AH59 Problem Implication Workaround Status intel EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown This erratum may occur when the processor executes one of the following read modify write arithmetic instructions and a page fault occurs during the store of the memory operand ADD AND BTC BTR BTS CMPXCHG DEC INC NEG NOT OR ROL ROR SAL SAR SHL SHR SHLD SHRD SUB XOR and XADD In this case the EFLAGS value pushed onto the stack of the page fault handler may reflect the status of the register after the instruction would have completed execution rather than before it The following conditions are required for the store to generate a page fault and call the operating system page fault handler 1 The store address entry must be evicted from the DTLB by speculative loads from other instructions that hit the same way of the DTLB before the store has
117. t does not generate an interrupt even if one of the programmed thresholds is crossed and the corresponding log bits become set When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is crossed None identified For the steppings affected see the Summary Tables of Changes CMPSB LODSB or SCASB in 64 bit Mode with Count Greater or Equal to 245 May Terminate Early In 64 bit Mode CMPSB LODSB or SCASB executed with a repeat prefix and count greater than or equal to 248 may terminate early Early termination may result in one of the following e The last iteration not being executed Signaling of a canonical limit fault GP on the last iteration While in 64 bit mode with count greater or equal to 248 repeat string operations CMPSB LODSB or SCASB may terminate without completing the last iteration Intel has not observed this erratum with any commercially available software Do not use repeated string operations with RCX greater than or equal to 2 For the steppings affected see the Summary Tables of Changes Specification Update Errata AH63 AH64 Problem Implication Workaround Status AH65 Problem Implication Workaround Status AH66 Problem Implication Workaround Status Removed Erratum Returning to Real Mode from SMM with EFLAGS VM Set May Result in Unpredictable System Behavior Returni
118. t up for that vector the system will GP fault If the ISR does not do an End of Interrupt EOI the bit for the vector will be left set in the in service register and mask all interrupts at the same or lower priority Any vector programmed into an LVT entry must have an ISR associated with it even if that vector was programmed as masked This ISR routine must do an EOI to clear any unexpected interrupts that may occur The ISR associated with the spurious vector does not generate an EOI therefore the spurious vector should not be used when writing the LVT For the steppings affected see the Summary Tables of Changes LOCK Asserted During a Special Cycle Shutdown Transaction May Unexpectedly Deassert During a processor shutdown transaction when LOCK is asserted and if a DEFER is received during a snoop phase and the Locked transaction is pipelined on the front side bus FSB LOCK may unexpectedly deassert When this erratum occurs the system may hang during shutdown Intel has not observed this erratum with any commercially available systems or software None identified For the steppings affected see the Summary Tables of Changes Address Reported by Machine Check Architecture MCA on Single bit L2 ECC Errors May Be Incorrect When correctable Single bit ECC errors occur in the L2 cache the address is logged in the MCA address register MCi_ADDR Under some scenarios the address reported may be incorrect Software shoul
119. ter corruption and may lead to unexpected operations in the floating point exception handler Avoid segment base misalignment and address wrap around at the segment boundary For the steppings affected see the Summary Tables of Changes Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior When request for data from Core 1 results in a L1 cache miss the request is sent to the L2 cache If this request hits a modified line in the L1 data cache of Core 2 certain internal conditions may cause incorrect data to be returned to the Core 1 This erratum may cause unpredictable system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock PREFETCHh instruction execution after a split load and dependent upon ongoing store operations may lead to processor livelock Due to this erratum the processor may livelock It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update 57 AH41 Problem Implication Workaround Status AH42 Problem Implication Workaround Status AH43 Problem Implication Workaround Status 58 Errata PREFETCHh Instructions M
120. tored address range For the steppings affected see the Summary Tables of Changes False Level One Data Cache Parity Machine Check Exceptions May Be Signaled Executing an instruction stream containing invalid instructions data may generate a false Level One Data Cache parity machine check exception The false Level One Data Cache parity machine check exception is reported as an uncorrected machine check error An uncorrected machine check error is treated as a fatal exception by the operating system and may cause a shutdown and or reboot It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update Errata AH106 Problem Implication Workaround Status AH107 Problem Implication Workaround Status A Memory Access Get a Wrong Memory Type Following GP due to WRMSR to an MTRR Mask The TLB Translation Lookaside Buffer may indicate a wrong memory type on a memory access to a large page 2M 4M Byte following the recovery from GP General Protection Fault due to a WRMSR to one of the IA32 MTRR PHYSMASKn MSRs with reserved bits set When this erratum occurs a memory access may get an incorrect memory type leading to unexpected system operation As an example an access to a memory mapped I O device may be incorrectly marked as cacheable become cached and never make it to the I O device Intel h
121. use event delivery performs multiple stack pushes an event delivery that includes a VTPR write access will also include at least one other write to the APIC access page That other write will cause an APIC access VM exit Thus even in the presence of this erratum any event delivery that includes a VTPR write access will cause an APIC access VM exit The only difference with respect to correct behavior will be with regard to page offset saved in the exit qualification by the APIC access VM exit A VMM should be able to emulate the event delivery correctly even with the incorrect offset Workaround The VMM should emulate any event delivery that causes an APIC access VM exit in the Status 84 same way regardless of the offset saved in the exit qualification For the steppings affected see the Summary Tables of Changes Specification Update Errata AH110 Problem Implication Workaround Status AH111 Problem Implication Workaround Status AH112 Problem Implication Workaround Status intel BIST Failure after Reset The processor may show an erroneous BIST built in self test result in bit 17 of EAX register when coming out of reset When this erratum occurs an erroneous BIST failure will be reported in EAX bit 17 This failure can be ignored since it is not accurate It is possible for BIOS to workaround this erratum by masking off bit 17 of the EAX register after comi
122. vior by using simple integer based load instructions when accessing side effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side effect memory For the steppings affected see the Summary Tables of Changes General Protection ZGP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit In 32 bit mode memory accesses to flat data segments base 00000000h that occur above the 4 limit Offffffffh may not signal a GP fault When such memory accesses occur in 32 bit mode the system may not issue a GP fault Software should ensure that memory accesses in 32 bit mode do not occur above the 4 G limit Offffffffh For the steppings affected see the Summary Tables of Changes Specification Update Errata AH28 Problem Implication Workaround Status AH29 Problem Implication Workaround Status AH30 Problem Implication Workaround Status intel EIP May Be Incorrect after Shutdown in IA 32e Mode When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be incorrect This may be observed if the processor is taken out of shutdown state by NMI A processor that has been taken out of the shutdown state may have an incorrect EIP The only software which would be affected is diagnostic software that relies on a valid EIP None identified
123. with the use TPR shadow activate secondary controls and virtualize APIC accesses VM execution controls all set to 1 and with the value of the TPR shadow bits 7 4 in byte 80H of the virtual APIC page less than the TPR threshold VM execution control field Due to this erratum such a VM exit will clear bit 0 blocking by STI and bit 1 blocking by MOV POP SS of the interruptibility state field of the guest state area of the VMCS bit 0 blocking by STI and bit 1 blocking by MOV POP SS should be left unmodified Since the STI MOV SS and POP SS instructions cannot modify the TPR shadow bits 1 0 of the interruptibility state field will usually be zero before any VM entry meeting the preconditions of this erratum behavior is correct in this case However if VMM software raises the value of the TPR threshold VM execution control field above that of the TPR shadow while either of those bits is 1 incorrect behavior may result This may lead to VMM software prematurely injecting an interrupt into a guest Intel has not observed this erratum with any commercially available software VMM software raising the value of the TPR threshold VM execution control field should compare it to the TPR shadow If the threshold value is higher software should not perform a VM entry instead it could perform the actions that it would normally take in response to a VM exit with exit reason TPR below threshold For the steppings affected see the Summary
124. y an 50 51 Instruction That Signals Floating Point Exception No Fix Last Branch Records LBR Updates May Be Incorrect after a Task Switch No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly INIT Does Not Clear Global Entries in the TLB Fixed Using Memory Type Aliasing with Memory Types WB WT May Lead to Unpredictable Behavior Fixed Update of Read Write R W or User Supervisor 0 5 or Present P Bits without TLB Shootdown May Cause Unexpected Processor 52 ier ma S T _ T f LX LX 56 57 58 BTS Message Lost When the STPCLK Signal Is Active MOV To From Debug Registers Causes Debug Exception No Fix EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown No Fix LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode No Fix A Thermal Interrupt Is Not Generated when the Current Temperature Is Invalid No Fix CMPSB LODSB or SCASB in 64 bit Mode with Count Greater or Equal to 2 May Terminate Early AH59 AH60 AH61 AH62 Result in Unpredictable System Behavior No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception AH66 38 Specification Update Summary Tables of Changes tel Performance Monitoring Event FP_ASSIST May Not Be Accurate
125. ycle Shutdown Transaction May Unexpectedly Deassert No Fix Erratum Removed Instructions May Unexpectedly Update the Last Exception Record LER MSR No Fix DR3 Address Match on MOVD MOVQ MOVNTQ Memory Store X Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired Event CFH Register Bytes May Be Preempted Before Higher Priority Interrupts The Processor May Report a TS Instead of a GP Fault No Fix Write to an APIC Register Sometimes May Appear to Have Not Occurred No Fix Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected Thermal Interrupts No Fix Count Value for Performance Monitoring Counter PMH PAGE WALK May Be Incorrect LER MSRs May Be Incorrectly Updated No Fix Performance Monitoring Events for Retired Instructions COH May Not Be Accurate N Fix Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted 3CH Does Not Count According To The Specification Using 2M 4M Pages When 20 4 Is Asserted May Result in Incorrect Address Translations No Fix Writing Shared Unaligned Data that Crosses a Cache Line without X X X Proper Semaphores or Barriers May Expose a Memory Ordering Issue No Fix Code Segment Limit Violation May Occur On 4 Gigabyte Limit x x Check FP Inexact Result Exception Flag Not Be Set ESES ESES ESES ESES EN 2 aes ee

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