Samsung M395T2863QZ4
Contents
1. Vss 51 53 50 52 DQSO 0080 t 7 DM CS Das DM CS 005 DOSI CS 098 DM CS bas 005 00 1 0 0 1 0 0 DQ1 101 DO 10 1 D36 101 18 101 D54 DQ2 1 0 2 2 VO2 02 DQ3 4 1 03 1 0 3 1 0 3 1 0 3 DQS9 0959 t t DM CS pas Das DM CS Das DM CS 098 DM CS bas 005 DQ4 1 00 00 00 00 005 1 01 D1 101 D37 1 0 1 D19 10 1 D55 DQ6 1 02 2 2 2 007 1 03 1 0 3 1 0 3 1 0 3 DQS1 0951 t t DM CS Das DM CS Das CS 009 CS 095 695 008 100 1 0 0 1 0 0 1 0 0 DQ9 34 1 01 D2 101 D38 10 1 20 10 1 D56 DQ2. M395T5160QZ4 133 35 2 3 25 126 85 gt _ 2x 2 50 gt pts 7 NP V 2 V 2 m E o amp S Y ES a a 2 2 11 i _ frm 20 A Ja gt lt 67 Rl 7751 5 175 lt 123 gt JO U ol 2 C 7 O gcc 75 5 0 gt 5 18 11197 SIS i 5 120 lt Era 3 80 1 0
3. 221 8 2 CT 10 n of 67 51 123 gt 1 27 0 10 4 Back 4 3 0 max U JO OL D D 40 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 8 5 256Mbx4 based 1Gx72 Module 4 Ranks
4. M395T5163QZ4 133 35 2 3 25 126 85 gt _ 2x 2 50 gt pts 7 NP t z 473 m E 5 Y 2x DIA 2 0 0170 ES a a T 2 11 i _ jt COE y A Ja gt lt 67 Rl 7751 5 175 lt 123 gt JO U ol 2 C 7 O gcc 75 5 0 gt 5 18 11197 SIS i 5 120 lt Era 3 80 1 00 A 1 25 1 50 MAX 0 178 DETAIL a DETAIL b DETAIL c DETAIL d DETAIL e Rev 1 4 May 2009 39 of 42 y ELECTRONICS FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units Millimeters 133 35 gt 8 2 max
5. WS p a EB Units Millimeters la 8 2 127 010 94 Back gt r4 3 0 ELECTRONICS 42 of 42 Rev 1 4 May 2009
6. 51 50 DQSO t DQS4 DQSO 0954 0959 7 DQS13 7 DM NU CS DQS DQS DW NU CS 09 095 NU CS DQS DQS DM NU CS DQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS 000 00 00 DQ32 00 1 0 0 DQ1 1 01 DO 1 D9 DQ33 4 1 01 D4 10 1 13 DQ2 102 2 DQ34 4 1 02 2 1 03 0035 1 03 DQ4 1 04 1 0 4 DQ36 1 04 104 005 105 1 05 DQ37 1 05 105 DQ6 106 1 0 6 DQ38 1 06 1 0 6 DQ7 4 1 07 1 07 DQ39 4 07 l O 7 DQS1 DQS5 DQS1 DQS5 e DQS10 t DQS14 t DM NU CS DQS DQS DW NU CS 09 095 DM NU CS DQS DQS DM NU CS 00 RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS 008 00 00 DQ40 1 00 1 0 0 009 1 01 D1 1 10 DQ41 101 D5 1 D14 DQ10 4 1 02 2 DQ42 4 1 02 2 0011 4 1 03 1 03 DQ43 1 03 DQ12 0 4 1 0 4 0044 1 0 4 104 DQ13 4 1 05 1 05 DQ45 1 05 105 0014 1 06 06 DQ46 4 1 06 0015 4 07 1 07 DQ47 4 07 107 0052 t DOS6 t DQS2 DQS6 DQS11 t DQS15 1 NU CS
7. 10x2 10x2 NORTH Southbound Southbound Data In Data Out Bs Data Merge Re Time 1 1 2 Re synch PLL Y 7 Ref Clock gt demux PISO 10 2 102 4 Link Init SM Reset and Control Reset and CSRs Control Init patterns 4 DRAM Clock IBIST RX IBIST TX 4 7 DRAM Clock command failover ecoder LAI Logi CRC Check 4 Pae 29 N DRAM Address 13 1 DRAM amp Thermal 2 o pi DRAM Address Sensor DDR State f Command Copy 2 Controller a and CSRs Y Data Out Core Control gt 3 and CSRs 36 5 Write Data 72 18x2 DRAM FIFO External MEMBIST Data strob DDR calibration amp DDR IOBIST DFX 1 Data In LAI Controller Sync amp Idie NB LAI Buffer Pattern Generator SMbus SMbus IBIST TX IBIST RX Controller mux Link Init SM and Control and CSRs failover 145672 1442 PISO demux Re synch Y Y Re Time Data Merge 4 Northbound Northbound Data Out 14x2 14 2 Data In Figure 11 Advanced Memory Buffer Block Diagram 11 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 2 8 Interfaces
8. M395T1G60QJ4 133 35 2 3 25 126 85 gt _ 2x 2 50 gt pts 7 NP V 2 V 2 m E o amp S Y ES a a 2 2 11 i _ frm 20 A Ja gt lt 67 Rl 7751 5 175 lt 123 gt JO U ol 2 C 7 O gcc 75 5 0 gt 5 18 11197 SIS i 5 120 lt Era 3 80 1 00 A 1 25 1 50 MAX 0 178 DETAIL a DETAIL b DETAIL c DETAIL d DETAIL e Rev 1 4 May 2009 41 of 42 y ELECTRONICS FBDIMM DDR2 SDRAM Heat Spreader Design Guide
9. Vss 51 50 DQSO DQS9 0050 0059 DM CS 005 Das DM CS 005 098 CS pas DM CS 095 095 00 1 0 0 DQ4 100 1 0 0 DQ1 101 DO 101 18 DQ5 1 01 09 10 1 D27 DQ2 4 1 02 2 DQ6 1 02 2 1 03 DQ7 1103 1 0 3 DQS1 DQS10 DQS1 DQS10 DM CS 005 005 DM CS 005 005 DM CS 005 0081 DM cs 005 095 008 00 00 DQ12 14 00 00 DQ9 101 D1 10 1 19 DQ13 34 101 D10 101 D28 DQ10 1 02 VO 2 DQ14 _ 1 0 2 2 0911 44 1 03 3 DQ15 _F 1 03 0082 09511 0052 DM CS 005 DM CS pas DM CS 005 0981 cs 005 095 DQ16 1 00 1 0 0 DQ20 00 1 0 0 DQ17 1 01 D2 101 20 021 1 01 11 VO 1 D29 09018 102 2 DQ22 1 02 2 09019 1 03 10 3 DQ23 1 03 DQS3 DQS12 0083 DQS12 DM CS 005 595 DM CS 005 005 CS pas 608 DM CS 005 005 DQ24 4 1 00 1 0 0 DQ28 1 00 1 0 0 DQ25 1 01 D3 VO 1 D21 DQ29 101 D12 1 D30 DQ26 4 1 0 2 2 DQ30 1 02 2 DQ27 1 03 1 0 3 DQ31 1 03 3 DQS4 DQS13 DQS4 DQS13 DM CS 09 095 CS 005 008 DM CS 005 DASI DM CS 09 DQS DQ32 _ 1 0 0 1 0 0 DQ36 1 00 1 0 0 DQ33 _ 1 01 D4
10. 6 2 3 FB DIMM Clocking Scheme 7 2 4 01 uper Mee 7 2 5 Southbound Command Delivery 8 26 Timing Diagram 9 2 7 Advanced Memory Buffer Block Diagram 2 0 11 2 8 1065 2255 555525 LI LIE 12 3 0 FBD HIGH SPEED DIFFERENTIAL POINT TO POINT LINK at 1 5 V INTERFACE 12 3 1 DDR2 Channel Me M 12 3 2 SMBus Sl ve Interface aedade apanak EEKi 12 3 3 FBD Channel Latency sassen 13 3 4 Peak Theoretical Throughput En nga Pasco kk 13 3 5 M dec causa deca 13 3 8 Hot remova REPE TEE 13 3 7 Hotreplac oo EUNDI IEEE UM MM IMEEM ML A 13 4 0 PIN CONFIGUREATION 14 5 0 FBDIMM FUNCTIONAL BLOCK DIAGRAM 2 2 44422 441111
11. DQS5 0955 09514 50 51 52 53 L 11 2 1 L DM NU 098 005 CS NU DOS 098 CS NU DOS DQS CS DM NU 5 098 CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ40 1 00 1 0 0 1 0 0 1 0 0 DQ41 1 01 D5 1 D14 I O 1 D23 1 2 DQ42 1 02 I O 2 2 2 DQ43 1 03 10 3 0044 1 04 4 4 104 45 4 1 05 5 5 5 0046 1 06 06 06 6 DQ47 1 07 VO7 VO7 10 7 DQS6 0956 DQS15 NU 5 DQS CS NU 098 DQS CS DM NU DQS 05 CS NU 098 DQS CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS 0048 1 00 1 0 0 1 0 0 1 0 0 49 4 1 01 D6 1 D15 1 024 1 033 00950 1 0 2 o2 2 2 DQ51 1 0 3 10 3 DQ52 1 04 4 104 104 DQ53 1 05 1 05 5 5 00954 1 06 06 06 6 DQ55 4 107 VO7 VO7 1 07 0087 2 DQS7 DQS16 NU 095 005 CS NU 098 05 CS DQS 095 CS NU 098 DQS CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ56 1 00 1 0 0 1 0 0 1 0 0 DQ57 1 01 D7 1 D16 1 D25 1 D34 58 4 1 02 VO2 VO2 2 DQ59 10 3 4 1 04 4 I O 4 104 00961 1 05 5 5 5 0062 4 1 06 06 06 6 DQ63 1 07 VO7 VO7 10
12. 21 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM Vss 51 53 50 52 DQS4 DQS4 t 1 CS 098 DM CS 005 DM CS 009 DM CS 005 005 DQ32 vo 0 00 Vo 0 VO 0 033 vo 1 D9 101 045 10 1 027 10 1 D63 0034 1102 102 102 102 0035 1 03 3 3 10 3 DQS13 00513 1 1 CS Das DM CS 005 Das DM CS 005 595 DM CS 005 099 36 4 00 00 00 037 101 10 10 1 46
13. Write Data B CMD Command with Address Fal or Write Data in C CMD Figure 4 Southbound Northbound Frame format Southbound consists of 10 differential signal pairs lane physically 20 signaling line Southbound Format has 10x12 10 IO or Lane x 1210 switching frame format which deliver 10x12 bit information per one DRAM clock One south bound frame is divided into three com mand slot See Figure 5 Command slot A delivers command with address Command slot B and C delivers command with address or write data into DRAM zora Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM Southbound Command Frame Format Bit 9 E CLK_REF T 2 CMD 7 CLK_DRAM 3 4 0 0 0 5 0 0 0 Packet T F B CMD 6 0 0 0 7 0 0 0 9 0 0 0 11 0 0 0 12 transfers Note 1 aE 0 12 CRC Checksum of the A Command 2 F 0 1 Frame Type 3 FE 0 21 CRC Checksum of 72bit data 4 CRC Cyclic Redundancy Check Figure 5 FBDIMM Command Encoding amp SB Frame DRAM Cmnds 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 Activate DS2 DS1 DSO 1 DRAM Addr DRAM Bank amp Address Write DS2 DS1 DSO 0 1 1 DRAM Bank amp Address Read 0 2 0 1 0 0
14. NOP NOP cmd data DIMM 1 cmd DIMM 1 data DIMM 2 cmd DIMM 2 data northbound Figure 8 Back to Back DRAM Read Data Transfers Rev 1 4 May 2009 9 of 42 ELECTRONICS FBDIMM CTA FBD southbound cmd data NOP Wdata Wdata Wdata Wdat WR1 NOP NOP me NOP Wdata Wdata Wdata 10 11 DDR2 SDRAM 12 13 DIMM 1 cmd DIMM 1 data WR1 DIMM 2 cmd Fixed fall through ti DIMM 2 data FBD northbound data Figure 9 2 cmd data DIMM 1 cmd 3 4 Basic DRAM Write Data Transfers on FBD 11 12 i Status 13 DIMM 1 data DIMM 2 data FBD northbound data southbound 2 ACT3 RD1 i i Wdata Wdata Wdata Wdata NOP T Wdata Wdata Wdata NOP NOP i i i i 7 i DIMM 2 cmd aui ELECTRONICS Figure 10 Simultaneous RD WR Data Transfers 10 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 2 7 Advanced Memory Buffer Block Diagram Advance Memory Buffer Block Diagram
15. EL Y 2 TO AMB 8 882 90 N 2x DIA 2 0 0 1 0 T b Y M j T ir A Ja gt 4 67 gt 751 gt 5 175 123 JO ol 2 C 2 C O O po N 5 75 119 0 595 5 0 i 2 50 2 50 0 8 0 05 lt 1 gt gt N EL 1119 SN 9 NE a j t 6 0 Sja 120 aas t Y lt 3 80 1 00 A 1 25 1 50 MAX 0 178 DETAIL a DETAIL b DETAIL c DETAIL d DETAIL e Rev 1 4 May 2009 33 of 42 y ELECTRONICS FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units Millimeters 133 35 gt 8 2 max 30 35 0 15 U 5 C 10 n of 67 le 51 g
16. Figure 12 illustrates the Advanced Memory Buffer and all of its interfaces They consist of two FBD links one DDR2 channel and an SM Bus interface Each FBD link connects the Advanced Memory Buffer to a host memory controller or an adjacent FBD The DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM MEMORY INTERFACE g lt Out Link em _ NBFBD 55 C 4 tik 5 D oe AMB DE Sc Eg gt SBFBD 865 I Out Link 08 SB FBD 9 Link SMB Figure 12 Advanced Memory Buffer Interface Block Diagram The FBDIMM channel uses a daisy chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM On the southbound data path each DIMM receives the data and again redrives the data to the next DIMM until the last DIMM receives the data The last DIMM in the chain initiates the transmission of data in the direction of the host a k a northbound On the northbound data path each DIMM receives the data and re drives the data to the next DIMM until the host is reached 3 0 FBD HIGH SPEED DIFFERENTIAL POINT TO POINT LINK at 1 5 V INTERFACE The Advanced Memory Buffer supports one FBD Channel consisting of two bidirectional link interfaces using high speed
17. idle 0 7 73 8 05 Idle 1 2600 2800 1 5V mA Idd_Idle_1 2660 2660 1 8V mA P_idle_1 9 15 9 46 Ww 1 active 1 3200 3600 1 5V mA Idd_active_1 5001 5241 1 8V mA P_active_1 14 54 15 63 Ww active 2 2600 2800 1 5V mA 199 active 2 2660 2660 1 8V mA P_active_2 9 15 9 46 Icc_training 2500 2700 1 5V mA Idd_training 2660 2660 1 8V mA P_training 8 99 9 31 Ww Note 1 FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet 27 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM Table 11 Currents Description Symbol Typ MAX Units Idle current DDR2 SDRAM device power down ITT1 500 700 mA Active power 50 DDR2 SDRAM BW ITT2 500 700 mA Table 12 Reference Clock Input Specifications Parameter Symbol Units Note MIN MAX uo eee fRefolk 3 2 126 67 133 40 MHz 1 2 1 fRefclk 4 0 158 33 166 75 MHz 1 2 Rise time fall time Tsck RISE SCK FALL 175 700 ps 3 Voltage high Vsck HIGH 660 850 mV Voltage low Vsck LOW 150 mV Absolute crossing point VcRoss ABS 250 550 mV 4 Relative crossing VcROSS REL calculated calculated 4 5 Percent mismatch between rise and iR _ 10 fall times 2 Duty cycle of reference clock Tsck DUTYCYCLE 40 60 Clock leakage current 10 10 uA 6 7 Clock input capacitance 0 5 2 7 Clock input capacitance delt
18. 05 DM CS 005 009 CB4 00 100 VO 0 VO 0 CB5 1 01 D17 101 053 10 1 D35 10 1 071 CB6 1 02 02 102 102 CB7 1 03 V0 3 10 3 10 3 All address command control clock Serial PD PNO PN13 SNO SN13 PNO PN13 SNO SN13 PS0 PS9 550 559 4 5 50 59 550 559 WP AO 4 2 000 0063 50 gt 5 036 053 7 S1 CS D54 D71 DQSO0 DQS17 52 gt 5 00 017 50 00517 53 gt 5 018 35 SAO SA1 SA2 CKEO gt D0 D17 D36 D53 1 gt 018 035 053 071 Vn Terminators B gt 036 071 ne SCL 2 all SDRAMs T 1 3 5 7 13 SDRAMs pv mm A2 A6 00 07 D9 D16 D18 D25 D27 D34 036 043 D45 D52 D54 D61 D63 D70 2 6 08 017 026 035 044 053 062 071 lx 7 I RAS all SDRAMs 4 SPD AMB SCK CAS all SDRAMs 5 5 EA WE all SDRAMs 00 071 CK CK all SDRAMs L Note VREF 00 071 1 DQ to I O wiring may be changed within a nibble T Vss 4 4 4 D0 D71 SPD AMB 2 There are two physical copies of each address command control excluding CS 3 There are four physical copies of each clock 4 ODT 00 035 is connected to Vss ELECTRONICS 22 of 42 Rev 1 4 May 2009 FBDIMM 6 0 Electrical Characteristics Table 6 Absolute Maximum Ratings DDR2 SDRAM
19. DQS DW CS Das DM NU CS 095 DM NU CS 095 RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ16 1 0 0 1 0 0 DQ48 1 0 0 00 DQ17 1 01 D2 1 01 D11 DQ49 101 D6 1 D15 DQ18 1 02 02 DQ50 1 02 2 DQ19 4 1 03 0951 1 03 DQ20 4 1 04 1 0 4 DQ52 1 04 104 DQ21 4 105 r2 1 0 5 DQ53 4 1 05 105 DQ22 1 06 r 1 0 6 DQ54 1 06 1 0 6 DQ23 4 1 07 1 07 DQ55 107 DQS3 t DQS7 DQS3 9 DQS7 00512 09516 1 DM NU CS DQS DW CS Das DM NU CS 09 05 DM NuU CS 09 DQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ24 4 1 00 00 0056 1 00 00 0925 1 0 1 D3 1 12 0957 1 01 07 1 D16 DQ26 1 02 2 0958 1 02 2 DQ27 1 03 DQ59 1 03 0028 1 04 1 0 4 0060 1 04 1 0 4 DQ29 4 1 05 1 05 DQ61 4 1 05 1 05 DQ30 4 1 06 06 DQ62 4 1 06 06 0031 07 1 07 DQ63 1 07 1 07 13 SNO SN13 0058 PNO PN13 5 0 5 13 DQS8 PSO PS9 SS0 SS9 DQS17 1 50 59 550 559 4 NU CS 05 DW NU CS 005 005 290 0063 50 gt 5 00 08 RDQS RDQS RDQS RDQS CBO CB7 gt 00 08 00 00 DQS0 DQS17 A 51 gt 5 09 017 CB1 101 8 VO 1 D17 0050 0058 CKE1 gt CKE D9 D17 2 1 02 2 B SCL ODT
20. SDA 0050 0058 CKE1 gt CKE D18 D35 B WP AO 1 A2 SCL ODT gt ODT all SDRAMs Vir 4 Terminators SDA 2 SDRAMs SA1 SA2 0 15 SDRAMs SAO SDRAMs F SA1 SA2 SDRAMs SDRAMs 5 5 CK CK all SDRAMs Vppspp e SPD AMB 00 035 VREF T 00 035 Vss e D0 D35 SPD AMB 1 DQ to I O wiring may be changed within a byte 2 There are two physical copies of each address command control clock 3 There are four physical copies of each clock 18 of 42 ELECTRONICS Rev 1 4 May 2009 FBDIMM 5 4 4GB 512Mx72 Module M395T5163QZ4 populated as 4 ranks of x8 DDR2 SDRAMs DQSO DQSO DQS9 50 51 52 53 ob b DM 00 DQS CS DM NU 05 CS DM 005 095 CS NU 098 05 CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS 00 100 00 1 0 0 DQ1 1 01 DO 101 D9 1 D18 10 1 DO 002 102 02 2 2 003 103 10 3 DQ4 1 04 104 4 104 DQ5 105 105 1 05 105 DQ6 1 06 10 6 06 06 007 1 07 107 1 07 VO7 0081 DQS1 09510 DM NU 5 095 CS DM NU 05 CS DM NU 005 095 CS NU 05 CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS 00 00 00 1 0 0 DQ9 1 01 D1 101 10 1 19 10 1 D28 DQ10 4 1 02 102 2 2 DQ11 4
21. 49 52 55 58 61 64 67 PS 9 0 Input Primary Southbound Data positive lines 70 73 76 79 82 90 93 96 99 102 PS 9 0 Input Primary Southbound Data negative lines 71 74 77 80 83 91 94 97 100 103 SN 13 0 Output Secondary Northbound Data positive lines 142 145 148 151 194 157 100 168 FOR DOR 177 180 183 186 SN 13 0 Output Secondary Northbound Data negative lines 14 146 149 152 155 158 161 16 172 15 178 181 184 187 SS 9 0 Input Secondary Southbound Data positive lines 190 193 196 199 202 210 213 216 219 222 SS 9 0 Input Secondary Southbound Data negative lines 191 194 197 200 203 211 214 217 220 223 SCL Input Serial Presence Detect SPD Clock Input 120 SDA Input SPD Data Input Output 119 SA 2 0 Input SPD Address Inputs also used to select the DIMM number in 118 239 240 the AMB Voltage ID These pins must be unconnected for DDR2 based Fully Buffered DIMMs Viplt 0 Me Vip 0 is Vpp value OPEN 1 8 V GND 1 5 V Vip 1 is Vcc 19780 value OPEN 1 5V GND 1 2V RESET Input AMB reset signal 17 19 20 44 45 86 87 105 106 139 140 164 165 RFU RFU Reserved for Future Use 206 207 225 226 Vcc PWR AMB Core Power and AMB Channel Interface Power 1 5 Volt 9 10 12 13 129 130 132 133 1 2 3 5 6 7 108 109 111 112 113 115 116 121 Vpp PWR DRAM Power and DRAM Power 1 8Volt 122 123 125 126 127 231 232 233 235 236 Vit PWR DRAM
22. Parameter Symbol MIN MAX Units Note Voltage on any pin relative to Vss Vin Vout 0 3 1 75 V 1 Voltage on Vec pin relative to Vss Vcc 0 3 1 75 V 1 Voltage Vpp pin relative to Vsg Vpp 0 5 2 3 V 1 Voltage on pin relative to Vas Vit 0 5 2 3 V 1 Storage temperature 55 100 1 DDR2 SDRAM device operating temperature Ambient TCASE 1 2 AMB device operating temperature Ambient TCASE 0 110 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability 2 DDR2 SDRAMs of FBDIMM should require this specification Parameter Symbol DRAM Units 0 lt lt 85 C 7 8 us Average periodic refresh interval tREFI 85 lt lt 95 3 9 us Table 7 Input DC Operating Conditions Parameter Symbol MIN Nom MAX Units Notes AMB supply voltage 1 455 1 50 1 575 V DDR2 SDRAM supply voltage Vpp 1 7 1 8 1 9 V Termination voltage 0 48 x Vpp 0 50 x Vpp 0 52 x Vpp V EEPROM supply voltage VppsPp 3 0 3 3 3 6 V SPD Input HIGH logic 1 voltag
23. 1 0 1 D22 DQ37 1 01 D13 101 D31 DQ34 1 0 2 1 0 2 DQ38 1 02 2 DQ35 41 1 0 3 1 0 3 DQ39 103 DQS5 DQS14 DQS5 DQS14 DM CS 005 595 DM CS 005 5 DM CS 005 005 DM cs 095 095 DQ40 41 100 1 0 0 DQ44 100 1 0 0 DQ41 _ 1 0 1 D5 101 D23 45 101 D14 1 D32 DQ42 4 1 0 2 1 02 DQ46 102 2 43 4103 1 0 3 DQ47 1 03 1 0 3 DQS6 DQS15 DQS6 DQS15 DM CS 005 595 DM CS 005 005 CS 005 DQS DM CS bas 095 048 1 00 1 0 0 DQ52 1 00 1 0 0 DQ49 101 D6 1 D24 DQ53 34 101 D15 VO 1 D33 0050 44 1 0 2 2 DQ54 1 02 2 DQ51 1 03 10 3 55 4 1 03 DQS7 DQS16 DQS7 DQS16 DM CS 005 DM CS pas DM CS 005 0081 DM cs 005 095 DQ56 1 00 1 0 0 DQ60 00 1 0 0 DQ57 _ 1 01 D7 10 1 025 061 1 Vo 1 D16 101 D34 DQ58 1 0 2 2 062 1 1 02 VO2 059 4 1 03 10 3 DQ63 1 1 03 DQS8 DQS17 DQS8 DQS17 DM CS DOS 095 DM CS 005 005 DM CS 005 005 DM CS 005 005 1 0 0 CB4 1 00 1 0 0 CB1 1 01 D8 1 D26 CB5 1 01 D17 1 D35 CB2 102 2 6 1 02 2 103 1 0 3 CB7 1 03 13 All address command control clock Vir PNO PN13 5 0 5 13 50 59 550 559 50 59 550 559 090 0063 80 gt 5 0 017 Serial PD 7 gt 00 017 0050 00517 S1 CS D18 D35 scL
24. 1 03 10 3 1 0 3 DQ12 4 1 04 104 4 104 DQ13 105 105 1 05 105 DQ14 4 1 06 10 6 06 06 DQ15 4 1 07 107 1 07 VO7 0052 e 0952 9 09511 DM 00 095 CS DM NU 05 CS DM NU 005 095 CS NU 05 CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ16 1 00 0 1 0 0 1 0 0 DQ17 101 D2 1 11 1 20 10 1 D29 DQ18 1 02 VO 2 2 2 DQ19 4 1 03 10 3 1 0 3 DQ20 4 1 04 104 4 104 DQ21 4 1 05 105 1 05 105 DQ22 4 106 10 6 06 06 DQ23 1 07 107 1 07 VO7 DQS3 DQS3 DQS12 DM 5 095 CS DM NU 05 CS DM NU 005 095 CS NU 05 CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ24 1 00 1 0 0 1 0 0 1 0 0 DQ25 101 D3 101 D12 01 D21 10 1 030 0026 102 102 2 2 0927 1 03 10 3 1 0 3 0028 1 04 104 4 104 DQ29 4 105 105 1 05 105 DQ30 4 106 10 6 06 06 DQ31 4 1 07 107 1 07 107 0054 0954 DQS13 DM NU 5 DQS CS DM NU 05 CS DM NU 005 095 CS NU 05 CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ32 4 1 00 1 0 0 1 0 0 1 0 0 DQ33 101 D4 101 D13 1 D22 10 1 D31 DQ34 4 1 02 I O 2 2 2 0935 1 03 10 3 1 0 3 DQ36 1 04 104 4 104 DQ37 4 105 105 1 05 105 DQ38 1 06 10 6 06 06 DQ39 4 1 07 107 1 07 107
25. 101 028 101 064 DQ38 02 102 102 102 DQ39 1 03 10 3 103 103 DQS5 0985 1 7 DM CS pas DQS DM CS 09 DQS DM CS pas 695 DM CS DOS DQS 00940 io 0 00 VO 0 DQ41 101 D11 Vo 1 D47 101 29 10 1 065 DQ42 102 102 102 102 DQ43 110 3 10 3 103 10 3 DQS10 00510 t t 1 DM CS Das DM CS 005 0081 CS Das DM CS pas DOS DQ44 1 00 VO 0 100 100 DQ45 101 12 10 1 048 101 D30 10 1 D66 DQ46 102 Vo 2 102 102 DQ47 1 1 03 10 3 10 3 10 3 DQS6 0056 t DM cs Das DM CS 005 005 CS Das Das DM CS 005 099 048 1 00 VO 0 100 100 049 4 101 13 10 1 49 101 D31 VO 1 D67 050 4 102 VO 2 102 102 051 1 03 10 3 V0 3 10 3 DQS11 DQS11 DM CS Das DM CS 005 DM CS Das DM CS 005 69 2952 100 100 Vo 0 VO 0 DQ53 1 01 D14 10 1 D50 VO 1 D32 10 1 D68 0054 1 0 2 102 Vo 2 102 DQ55 03 103 10 3 10 3 DQS7 os DM CS 095 095 DM CS 09 008 DM CS 005 005 CS 005 095 056 4 1 00 VO 0 100 100 DQ57 3 01 15 VO 1 D51 101 D33 10 1 D69 DQ58 102 102 102 102 DQ59 103 10 3 10 3 10 3 DQS16 09516 CS 005 095 DM CS pas Das DM CS Das Das DM CS 005 099 DQ60 00 00 VO 0 VO 0 DQ61 1 0 1 D16 Vo 1 D52 101 D34 101 070 DQ62 1 0 2 102 102 102 DQ63 103 10 3 103 103 DQS17 00517 7 CS pas Das DM CS pas Das DM CS 005
26. 12 5 60 4 97 9 16 5 91 9 16 active 1 3900 3900 2900 2000 4700 3300 4700 1 5 mA Idd active 1 2605 4221 2505 2005 2826 2726 2826 1 8V mA P active 1 11 09 14 16 9 33 6 96 12 77 10 38 12 77 active 2 3700 3700 2400 1900 4500 2600 4500 1 5 mA 184 active 2 1240 1980 1040 1240 1340 1040 1340 1 8 mA P active 2 8 18 9 59 5 76 5 35 9 63 6 07 9 63 training 4000 4000 2300 1900 4600 2400 4600 1 5v mA Idd training 1240 1980 940 1040 1340 940 1340 1 8 mA P training 8 66 10 06 5 41 4 97 9 79 5 57 9 79 Note 1 FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet 25 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM Vdd Max 1 900V Vcc Max 1 575V 4GB M395T5160QZ4 Symbol E66 E65 E68 E63 F76 E76 Notes Unit PC2 5300 PC2 6400 cc Idle 0 2600 2600 1700 1500 3200 3200 1 5V mA dd Idle 0 1980 1980 1580 1580 2080 2080 1 8V mA P idle 0 7 86 7 86 5 68 5 36 8 99 8 99 cc Idle 1 3400 3400 2600 1900 4200 4200 1 5V mA dd_Idle_1 1980 1980 1580 1580 2080 2080 1 8V mA P_idle_1 9 12 9 12 7 10 5 99 10 57 10 57 cc active 1 3900 3900 3200 2000 4700 4700 1 5V mA Idd active 1 4221 4221 3921 3321 4661 4661 1 8V mA P_active_1 14 16 14 16 12 49 9 46 16 26 16 26 lcc active 2 3700 3700 2600 1900 4500 4500 1 5V mA Idd_active_2 1980 1980 1580 1880 2080 2080 1
27. 16 5 1 1GB 128Mx72 Module M395T2863QZ4 16 5 2 2GB 256Mx72 Module M395T5663QZA 17 5 3 4GB 512Mx72 Module M395T5160QZ4 0 18 5 4 4GB 512 72 Module M395T5163QZ4 19 5 5 8GB 1 72 Module 39511 60044 21 6 0 ELECTRICAL CHARACTERISTIGS RE cS Subs Men sp E seu VE 23 7 0 CHANNEL INITIALIZATION Occo de Saa puo 32 2 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM Revision History DDR2 SDRAM Revision Month Year History 1 0 March 2008 Initial Spec Release 1 1 March 2008 Added 4Rank Products based on Low Power AMB 1 11 March 2008 Corrected Typo 1 12 April 2008 Corrected mechanical Dimension 1 2 August 2008 Changed the ordering information 1 3 December 2008 Updated the IDD current specification 1 4 May 2009 Added new products on the line up Based on Montage D3 AMB ELECTRONICS
28. 6 illustrates the deliv ery of the three potential commands in a frame to three separate DRAM channels Command A is delivered in this case to the DRAM devices on DIMM 3 as soon as the command can traverse the AMB buffer The B and C commands are delayed and presented to two other DRAM channels on the following clock See below figure7 10 for Basic Read amp Write Operations Northbound consists of 14 differential signal pairs lane physically 28 signaling line Southbound Format has 14x12 14 IO or Lane x 12 10 switching frame format which deliver 14x12 bit information per one DRAM clock One north bound frame is divided into two Both frame deliver read data from DRAM 1 2 3 4 5 Ea i FBD southbound p i i 1 CMD A transferred immediately cmd data 2 CMD cannot target the same DIMM DIMM 1 cmd 3 Host is responsible for scheduling CMD DIMM 2 cmd _ RINGS ES DIMM 3 cmd DIMM 4 cmd northbound i i cmd data Figure 6 FBDIMM Command Delivery Rules 8 of 42 Rev 1 4 May 2009 ELECTRONICS DDR2 SDRAM FBDIMM 2 6 Basic Timing Diagram 13 12 11 10 FBD southbound cmd data DIMM 1 cmd DIMM 1 data DIMM 2 cmd DIMM 2 data northbound Figure 7 Basic DRAM Read Data Transfers on FBD 13 12 11 10 FBD southbound NOP NOP
29. 7 0083 053 9 09512 NU 095 DQS CS DM NU DOS 095 CS DM NU DQS DQS CS DM NU 008 DQS CS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS 1 00 1 0 0 1 0 0 1 0 0 101 D8 1 D17 I O 1 D26 1 D35 CB2 02 1 0 2 2 2 CB3 1 0 3 10 3 4 1 04 4 4 104 CB5 105 1 05 VO5 1 05 CB6 1 06 1 0 6 06 6 CB7 07 VO7 VO7 10 7 13 SNO SN13 Serial PD PNO PN13 5 0 5 13 50 59 550 559 SCL gt 4 5 50 59 550 659 CKO gt 00 017 WP A0 1 2 DQ0 DQ63 CK1 gt CKE 018 035 CBU OBI ODTO gt ODT 00 017 29500951 ODT1 gt ODT D18 D26 L 2950 5958 ODT2 ODT D27 D35 SAO SA1 SA2 So B BAO BA2 all SDRAMs SDA A0 A1 A3 A5 A7 A15 all SDRAMs SA1 SA2 A2 ECC A6 ECC D8 D17 D26 D35 RAS all SDRAMs RESET CAS all SDRAMs All address command control clock L all SDRAMs SCK SCK CK CK all SDRAMs VIT Terminators SPD AMB 00 017 Note 1 DQ to I O wiring may be changed within a byte TL 00 017 2 There are two physical copies of each address command control clock a Vss D0 D17 SPD AMB ELECTRONICS 20 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 5 5 8GB 1Gx72 Module M395T1G60QJ4 populated as 4 ranks of x4 DDR2 SDRAMs
30. P2P Int rconnect DIMM Topology LYDS Reliability Clock Recovery Is Fly by CLK CMD De Emphasis CRC fail over DRAM FIFO Buffer L Figure 1 FBDIMM Memory system Overview 5 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 2 2 FBDIMM Channel Frequency Scaling There are many frequency parameters including reference clock frequency DRAM clock frequency DRAM data transfer rate channel transfer rate and channel unit interval All of frequency parameters are scaled with a certain gear ratio External clock source provides reference clock input to AMB and Host External clock source is relatively slower than channel and DRAM frequency Thus AMB dou bles external clock input and generates clock inputs to DRAMs DRAM use clock input from AMB which is two times faster than refer ence clock for DRAM operation DRAM data transfer rate is two times faster than DRAM clock input with nature of double data rate operation and four times faster than external clock source Channel speed is represented by unit interval average time interval between voltage transitions of a signal in the FBD channel It is six times faster than DRAM data transfer rate For example external clock source gives 6ns clock 166 2 AMB doubles it and gives 3ns clock 333MHz to DRAM and channel communicate with unit interval 250ps 4 0Gbps transfer rate Figure 2 shows frequency scale ratio over
31. frequency parameters in FBD memory system DDR667 Ex 6ns REF 3ns DRAM DRAM 250ps Packet T F 00003000 12 Uls in one DRAM H DQs ADDR CLK CMD SB ADDR CMD Wdata Rx Tx Host i RE NB Rdata Ref DRAM Reference CLK DRAM L Clock 4 CLK_DRAM CLK_REF Frequency DDR2 533 312 5ps 266MHz 133MHz 3 2Gb s DDR2 667 250ps 333MHz 166MHz 4 0Gb s DDR2 800 208 33ps 400MHz 200MHz 4 8Gb s Figure 2 FBDIMM Speed Scaling ELECTRONICS 6 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 2 3 FBDIMM Clocking Scheme In FB DIMM platform design phase adjustment among reference clock inputs to each individual AMB and host is not taken account Thus clock synchronization is made by using both external reference clock and channel data stream in FB DIMM memory system Host and each individual AMB has a each individual basis clock recovery circuitry for channel data communication It runs with inputs from PLL inside chip and data stream from the other AMB or Host Because data stream itself involves data communication process no sig naling switching or data communication may loss clock synchronization between transmitter and receiver Thus min transition density is defined for this purpose In FBD channel a density of 6 transitions within 512 transfers or unit intervals UI
32. 0 1 0 DRAM Bank amp Address Precharge All 052 0 1 0 0 0 0 1 1 1 Precharge Single 52 051 050 0 0 1 DRAM Bank 1 1 X Auto CBR Refresh 052 051 0 0 0 0 1 1 0 1 Enter Self Refresh 052 051 0 0 0 0 1 X X X 1 0 0 X Ext Self Retosty ps2 ps1 pso o 4 1 10114 1 Exit Power Down Enter Power Down 052 051 0 0 0 0 1 X X X 0 1 0 X X X reserved X X 0 0 1 X X X 0 0 X X Note The values in X fields in non reserved commands above may be driven onto the DRAM device pins 2 5 Southbound Command Delivery A DRAM command located in the A command may be delivered to the DRAM devices as soon as the 14 bit 10 bits in fail over CRC is checked This minimizes DRAM access latency by allowing the command to be delivered after the first 4 transfers of the frame have been received The A command is transferred immediately to the DRAM pins with minimum delay whereas the B and C command are delivered one DRAM clock later To minimize memory access latency the read related Activate Read if the page is open and explicit Precharge commands to a rank of DRAM devices should be placed in the A command if possible Figure
33. 0 A 1 25 1 50 MAX 0 178 DETAIL a DETAIL b DETAIL c DETAIL d DETAIL e Rev 1 4 May 2009 37 of 42 y ELECTRONICS FBDIMM DDR2 SDRAM Heat Spreader Design Guide WS p a EB Units Millimeters la 8 2 127 010 94 Back gt r4 3 0 ELECTRONICS 38 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 8 4 128Mbx8 based 512Mx72 Module 4 Ranks
34. 10 4 1 02 VO2 02 02 DQ11 1 03 1 0 3 0510 00510 t t DM CS Das DM CS 005 Das DM CS 005 005 cs 005 095 DQ12 1 00 00 1 0 0 1 0 0 DQ13 101 D3 1 D39 10 1 D21 1 057 DQ14 4 1 02 02 2 2 0915 44 1 03 1 0 3 1 0 3 DQS2 DM CS pas Das DM CS pas Das DM CS 005 DAS DM CS 005 29 DQ16 _ 1 00 1 0 0 1 0 0 1 0 0 DQ17 101 D4 1 D40 1 01 D22 101 D58 DQ18 102 2 2 2 DQ19 10 3 1 0 3 DQS11 DM CS 005 Das DM CS 595 DM CS DOSI DM CS pas 099 20 00 1 0 0 1 0 0 1 0 0 DQ21 _J 1 01 D5 1 41 1 23 101 D59 002 1 0 2 2 2 2 0023 4 1 0 3 1 0 3 1 0 3 1 0 3 DQS3 5053 1 DM CS pas Das DM CS Das DM CS 098 DM cs 09 095 DQ24 1 00 00 00 00 DQ25 101 06 1 042 1 024 10 1 D60 DQ26 4 1 0 2 2 2 2 0927 44 1 03 1 0 3 DQS12 09512 1 t t DM CS 005 bas DM CS pas Das DM CS pas DASI DM cs 095 DOS DQ28 1 00 1 0 0 1 0 0 1 00 029 1 101 7 101 43 1 025 10 1 D61 DQ30 1 1 02 VO2 02 02 103 1 03 DQS8 058 1 1 CS 005 005 DM CS Das DQS DM CS 005 008 DM CS 005 095 1 00 1 0 0 1 0 0 1 0 0 CB1 1 01 08 01 D44 1 26 101 2 CB2 102 2 2 2 4 1 03 1 0 3 1 0 3
35. 3 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 1 0 Features 240 fully buffered dual in line memory module FB DIMM 3 2Gb s 4 0Gb s link transfer rate 1 8V 0 1V Power Supply for DRAM 1 5V 0 075 0 045V Power Supply for AMB Vcc 3 3V 0 3V Power Supply for Vppspp Buffer Interface with high speed differential point to point Link at 1 5 volt Channel error detection amp reporting Channel fail over mode support Table 1 Ordering Information 8 Banks Posted CAS Programmable CAS Latency 3 4 5 6 Programmable Additive Latency 0 1 2 3 4 5 Automatic DDR2 DRAM bus and channel calibration MBIST and IBIST Test functions Serial presence detect with EEPROM Hot add on and Hot Remove Capability Transparent mode for DRAM test support Number Type ct Part Number Density Organization Component Composition AMB Heat Height of Rank Spreader M395T2863QZ4 CE66 F76 E76 IDT C1 M395T2863QZ4 CE65 Intel D1 1GB 128M 72 128Mx8 K4T1G084QQ 9EA 1 M395T2863QZ4 CE68 F78 IDT L4 M395T2863QZ4 CE63 Montage D3 M395T5663QZ4 CE66 F76 E76 IDT C1 M395T5663QZ4 CE65 Intel D1 2GB 256M 72 128Mx8 K4T1G084QQ 18EA 2 M395T5663QZ4 CE68 F78 IDT L4 M395T5663QZ4 CE63 Montage D3 Full Module 30 35mm M395T5160QZ4 CE66 F
36. 6 172 SN6 81 Vss 201 Vss 112 232 23 143 SNO 53 Vss 173 Vss 82 PS4 202 554 113 233 24 Vss 144 Vss 54 PN7 174 SN7 83 PS4 203 554 114 Vss 234 Vss 25 PN1 145 SN1 55 PN7 175 SN7 84 Vss 204 Vss 115 235 26 146 SN1 56 Vss 176 Vss 85 Vss 205 Vss 116 236 27 Vss 147 Vss 57 PN8 177 SN8 86 RFU 206 RFU 117 Vir 237 Vir 28 PN2 148 SN2 58 PN8 178 SN8 87 RFU 207 RFU 118 SA2 238 29 2 149 SN2 59 Vss 179 Vss 88 Vss 208 Vss 119 SDA 239 SA0 30 Vss 150 Vss 60 PN9 180 SN9 89 Vss 209 Vss 120 SCL 240 SA1 90 PS9 210 559 RFU Reserved Future Use These pin positions are reserved for forwarded clocks to be used in future module implementations These pin positions are reserved for future architecture flexibility 1 The following signals are CRC bits and thus appear out of the normal sequence PN12 PN12 SN12 SN12 PN13 PN13 SN13 SN12 59 59 559 559 14 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM Table 5 Pin Description Pin Name Type Pin Description Pin Numbers SCK Input System Clock Input positive line 228 SCK Input System Clock Input negative line 229 PN 13 0 Output Primary northbound Data positive lines 22 25 28 31 34 37 40 48 51 54 57 60 63 66 PN 13 0 Output Primary northbound Data negative lines 23 26 29 32 35 38 41
37. 76 E76 IDT C1 M395T5160QZ4 CE65 Intel D1 256Mx4 K4T1G044QQ 36EA 2 M395T5160QZ4 CE68 4GB 512M x 72 IDT L4 M395T5160QZ4 CE63 Montage D3 M395T5163QZ4 CE68 F78 E78 128Mx8 K4T 1G084QQ 36 4 IDT L4 M395T 1G60QJ4 CE68 F78 8GB 1G 72 DDP duc 4 IDT L4 Note 1 Z of Part number 11th digit stands for Lead Free and RoHS compliant products 2 J of Part number 11th digit stands for Dual Die Package based Lead Free and RoHS compliant products 3 The last digit stands for AMB Table 2 Performance range F7 DDR2 800 E7 DDR2 800 E6 DDR2 667 Unit DDR2 DRAM Speed 800 800 667 Mbps CL tRCD tRP 6 6 6 5 5 5 5 5 5 CK Table 3 Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 128Mx8 1Gb based Module 0 13 0 9 BAO BA2 A10 256Mx4 1Gb based Module 0 13 0 9 11 BAO BA2 A10 ELECTRONICS 4 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 2 0 FBDIMM Generals 2 1 FBDIMM Operation Overview FB DIMM Fully Buffered Dual in Line Memory Module is designed for the applications which require higher data transfer bandwidth and scalable memory capacity The memory slot access rate per channel decreases as the memory bus speed increases resulting in limited density build up as channel speeds increase with memory system having the stub bus architecture FB DIMM solution is intended to eliminate this stub bus channel bottleneck by using point to point lin
38. 8V mA P_active_2 9 59 9 59 7 10 6 56 11 04 11 04 lcc training 4000 4000 2500 1900 4600 4600 1 5V mA Idd training 1980 1980 1580 1580 2080 2080 1 8V mA P_training 10 06 10 06 6 94 5 99 11 20 11 20 1 FBDIMM Power was calculated on the basis of DRAM Values in datasheet Vdd 1 900V Vcc Max 1 575V 4GB M395T5163QZ4 Symbol E68 F78 E78 Notes Unit PC2 5300 PC2 6400 PC2 6400 Icc_Idle_O 1600 1700 1700 1 5V mA Idle 0 1580 1580 1580 1 8V mA idle 0 5 52 5 68 5 68 Ww lcc Idle 1 2300 2500 2500 1 5V mA Idd_Idle_1 1580 1580 1580 1 8V mA P_idle_1 6 62 6 94 6 94 lcc active 1 2900 3300 3300 1 5V mA Idd_active_1 3045 3266 3266 1 8V mA P_active_1 10 35 11 40 11 40 2 2400 2600 2600 1 5V mA Idd_active_2 1580 1580 1580 1 8V mA P_active_2 6 78 7 10 7 10 Icc_training 2300 2400 2400 1 5V mA Idd_training 1480 1480 1480 1 8V mA P_training 6 43 6 59 6 59 Note 1 FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet 26 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM Vdd Max 1 900V Vcc Max 1 575V 8GB M395T1G60QJ4 Symbol E68 F78 Notes Unit PC2 5300 PC2 6400 Idle 0 1700 1900 1 5V mA Idd_Idle_O 2660 2660 1 8V mA
39. 9 DQS13 DM CS 095 DM NU CS 095 RDQS RDQS RDQS RDQS DQ0 00 DQ32 1 00 DQ1 1 01 DO DQ33 4 1 01 4 DQ2 1 02 DQ34 1 02 DQ3 1 03 DQ35 1 03 DQ4 104 DQ36 1 04 0905 05 0037 1 05 006 1 06 0038 1 06 107 0039 07 0051 0055 DQS1 DQS5 DQS10 I DQS14 DM NU CS 095 DM NU CS 095 RDQS RDQS RDQS RDQS 00 0040 1 00 DQ9 1 01 D1 0041 101 05 09010 1 02 0042 4 1 02 0011 1 03 DQ43 1 03 DQ12 104 DQ44 1 04 DQ13 1 05 DQ45 1 05 DQ14 1 06 DQ46 1 06 DQ15 1 07 DQ47 1 07 Das2 0056 0082 0056 DQS15 DM CS 095 DM NU CS 095 RDQS RDQS RDQS RDQS DQ16 1 00 DQ48 4 1 00 DQ17 101 D2 0049 101 06 DQ18 102 DQ50 4 1 02 DQ19 1 03 DQ51 4 1 03 DQ20 104 DQ52 104 DQ21 4 1 05 DQ53 1 05 DQ22 106 DQ54 3 1 06 DQ23 07 0055 1 07 0083 0087 0983 0057 00512 00516 DM NU CS 095 DM NU CS DQS DQS RDQS RDQS RDQS RDQS DQ24 00 56 4 1 00 0025 101 03 0057 101 07 0926 1 02 0058 1 02 0927 1 03 0059 0028 1 04 0060 1 04 0929 1 05 DQ61 4 1 05 DQ30 1 0 6 DQ62 4 1 06 02031 07 0063 1 07 D
40. Address Command Clock Termination Power Vpp 2 15 117 135 237 Vppspp PWR SPD Power 238 4 8 11 14 18 21 24 27 30 33 36 39 42 43 46 47 50 53 56 59 62 65 68 69 72 75 78 81 84 85 88 89 92 95 98 101 104 107 110 114 124 128 Vss GND Ground 131 134 138 141 144 147 150 153 156 159 162 163 166 167 170 173 176 179 182 185 188 189 192 195 198 201 204 205 208 209 212 215 218 221 224 227 230 234 The DNU M_Test pin provides an external connection R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It is not intended to be used in normal DNU M_Test DNU system operation and must not be connected DNU in a sys 137 tem This test pin may have other features on future card de signs and if it does will be included in this specification at that time ELECTRONICS 15 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 5 0 FBDIMM Functional Block Diagram 5 1 1GB 128Mx72 Module M395T2863QZ4 populated as 1 rank of x8 DDR2 SDRAMs 50 4 DQSO 0080 0054 DQS
41. FBDIMM DDR2 SDRAM DDR2 Fully Buffered DIMM 240pin FBDIMMs based on 1Gb Q die 60FBGA with Lead Free and Halogen Free ROHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUB JECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANT ING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar ap plications where Product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Samsung Electronics reserves the right to change products or specification without notice Rev 1 4 May 2009 1 of 42 ELECTRONICS FBDIMM DDR2 SDRAM Table of Contents 1 0 FEATURES ee 4 2 0 FBDIMM GENERALS 5 2 1 FB DIMM Operation Overview 4 5 2 2 FB DIMM Channel Frequency Scaling
42. ML 0 2 UI 4 5 Differential RX output rise fall time TRX RISE TRX FALL 50 ps 20 80 voltage Common mode of input voltage 120 400 EQ 6 Note1 10 AC peak to peak common mode of input voltage VRX CN ACp p 270 mV EQ 7 Note 1 Ratio of to minimum Vgx piEFp p VRX CM EH RATOP 45 11 Differential return loss RLgx piFF 9 dB 1GHz 2 4 GHz Note 12 Common mode return loss RLgx cM 6 dB 1GHz 2 4 GHz Note 12 RX termination impedance 41 55 13 D D RX Impedance difference RRX MATCH DC 4 EQ8 Lane to lane PCB skew at RX Laces See 6 2111 Minimum RX drift tolerance TRx DRIFT 400 ps 15 Minim data tracking 3dB bandwidth 0 2 MHz 16 Electrical idle entry detect time TELENTRY DETECT 60 ns 17 Electrical idle exit detect time TELEXIT DETECT 30 ns Bit Error Ratio BER 101 18 Notes 1 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad will be lower than at the pin 2 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Worst case mar gins are determined for the case with transmitter using small voltage swing 3 Multiple lanes need to detect the El condition before the device can act upon the EI detection Specified at the package pins into a timing and voltage compliance test setup 5 The single pulse mask provides sufficient symbol ene
43. R2 SDRAM Symbol Conditions Power Units Supply Idle 0 Idle Current single or last DIMM 1 5V mA LO state idle 0 BW Primary channel enabled Secondary Channel Disabled 0 high Command and address lines stable 1 8V mA DRAM clock active 0 Total Power Icc Idle 1 Idle Current first DIMM 1 5V mA LO state idle 0 BW Primary and Secondary channels enabled Idd Idle 1 CKE high Command and address lines stable 1 8V mA DRAM clock active Idd_Idle_1 Total Power Icc_Active_1 Active Power 1 5V mA LO state 50 DRAM BW 67 read 33 write 194 Active 1 Primary and Secondary channels enabled 1 8V mA DRAM clock active CKE high Idd_Active_1 Total Power Active 2 Active Power data pass through 1 5V mA LO state 50 DRAM BW to downstream DIMM 67 read 33 write Idd Active 2 Primary and Secondary channels enabled 1 8V mA n CKE high Command and address lines stable DRAM clock active 144 Active 2 Total Power Idd_Training Training for AMB spec Not in Primary and Secondary channels enabled 1 5V mA SPD 100 toggle on all channel lanes 199 Training DRAMs idle 0 BW for AMB spec Not in CKE high Command and address lines stable 1 8V mA SPD DRAM clock active 199 Training Total Power 24 0142 ELECTRONICS Rev 1 4 May 2009 FBDIMM DDR2 SDRAM Table 10 Pow
44. Rev 1 4 2009 19 of 42 DDR2 SDRAM ELECTRONICS FBDIMM DDR2 SDRAM
45. Rl 751 gt 5 175 123 JO U ol 2 C 2 C SS y 119 80595 5 0 2 50 2 50 08 0 054 lo lt gt Sho gt 1119 i e 120 6 0 Y jo 3 80 gt lt 1 00 1 25 150 MAX 0 178 DETAIL a DETAIL b DETAIL c DETAIL d DETAIL e Rev 1 4 May 2009 35 of 42 y ELECTRONICS FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units Millimeters 133 35 gt 8 2 max 221 8 2 CT 10 n of 67 51 123 gt 1 27 0 10 4 Back 4 3 0 max U JO OL D D 36 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 8 3 256Mbx4 based 512Mx72 Module 2 Ranks
46. a Ci 0 25 0 25 pF 8 Transport delay T1 5 ns 9 10 Phase jitter sample size NSAMPLE 1016 Periods 11 Reference clock jitter filtered TREF JITTER 40 ps 12 13 Reference clock deterministic jitter TREF DJ TBD ps Note 1 133MHz for PC2 4200 166MHz for PC2 5300 Measured with SSC disabled ak wh Measured differentially through the range of 0 175V to 0 525V The crossing point must meet the absolute and relative crossing point specification simultaneously 8 REL MIN and VCROSS are derived using the following calculation Min 0 5 0 710 0 250 Max 0 5 Vhavg 0 710 0 550 where Vhavg is the average of Vsck HIGHM Difference between SCK and SCK input output parameter TREF JITTER Measured with a single ended input voltage of 1V Applies to reference clocks SCK and SCK T1 Tdatapath Tclockpath excluding PLL loop delays This parameter is not a direct clock output parameter but in indirectly determines the clock 10 The net transport delay is the difference in time of flight between associated data and clock paths The data path is defined from the reference clock source through the TX to data arrival at the data sampling point in the RX The clock path is defined from the reference clock source to clock arrival at the same sampling point The path delays are caused by copper trace routes on chip routing on chip buffer
47. ansmitter termination impender 41 55 12 4 Boundaries are applied sepa D D TX Impedance difference RTX MATCH DC 4 rately to high and low output voltage states Lane to lane skew at TX LTX SkEW1 100 301 ps 13 15 Lane to lane skew at TX LTX SKEW2 100 201 ps 14 15 Rev 1 4 May 2009 29 of 42 y ELECTRONICS FBDIMM DDR2 SDRAM Table 14 Differential Receiver Input Specifications Parameter Symbol Units Comments MIN MAX Differential peak to peak input voltage for large voltage swing VRX DIFFp p 170 TBD mV EQ 5 Note1 Maximum single ended voltage in El condition VRX IDLE SE 75 mV 2 3 Maximum single ended voltage in Ei condition DC only VRX IDLE SE DC 50 mV 2 3 Maximum peak to peak differential voltage in El condition VRXIDLE DIFFp p 65 mV Single ended voltage w r t Vgs on D D VRX SE 300 900 mV 4 Single pulse peak differential input voltage VRx DIFF PULSE 85 mV 4 5 Amplitude ratio between adjacent symbols VRX DIFF ADJ RATIO TBD 4 6 Maximum RX inherent timing error 3 2 and 4 0 Gb x TRX TJ MAX 0 4 UI 4 7 8 Maximum RX inherent deterministic timing error 3 2 and 4 8 Gb s TRX TJ MAX4 8 TBD UI 4 7 8 Single pulse width as zero voltage crossing VRX DJ DD 0 3 UI 4 7 8 9 Single pulse width at minimum level crossing VRX DJ DD 4 8 TBD UI 4 7 8 9 Differential RX input rise fall time TRx PW ZC 0 55 UI 4 5 Common mode of the input voltage TRX PW
48. ass DQS8 13 SN0 SN13 DQS17 PNO PN13 5 0 5 13 50 59 550 559 NU CS DQS DQS 50 59 550 559 RDQS RDQS 100 090 0063 50 gt 5 SDRAMs CB1 1 01 08 7 CKE0 gt CKE all SDRAMs 2 1 0 2 050 00817 1 03 0050 0058 CB4 04 CB5 105 SCL ODT gt ODT all SDRAMs CB6 106 SDA BAO BA2 all SDRAMs CB7 107 SA1 SA2 0 15 SDRAMs r RAS all SDRAMs RESET CAS all SDRAMs SDRAMs Serial PD SCK SCK CK CK all SDRAMs SCL SDA TT 1 All address command control clock w v WP 0 1 A2 Vcc SA1 SA2 a Vpp Note VREF 7 1 DQ to I O wiring may be changed within a byte Ves 11141174 2 are two physical copies of each address command control clock Terminators AMB SPD AMB 00 08 AMB 0 08 DO D8 SPD AMB ELECTRONICS 16 of 42 Rev 1 4 May 2009 FBDIMM 5 2 2GB 256Mx72 Module M395T5663QZ4 populated as 2 ranks of x8 DDR2 SDRAMs DDR2 SDRAM
49. d through some means of the addition of one or more new FBDIMMs so that specific commands can be sent to the host controller to initialize the newly added FBDIMM s and perform a hot add reset to bring them into the channel timing domain It should be noted that the power to the FBDIMM socket must be removed before a hot add FBDIMM is inserted or removed Applying or removing the power to a FBDIMM socket is a system platform function 3 6 Hot remove In order to accomplish removal of FBDIMMs the host must perform a fast reset sequence targeted at the last FBDIMM that will be retained on the channel The fast reset re establishes the appropriate last FBDIMM so that the southbound transmission outputs of the last active FBDIMM and the southbound and northbound outputs of the FBDIMMs beyond the last active FBDIMM are disabled Once the appropriate outputs are disabled the system can coordinate the procedure to remove power in preparation for physical removal of the FBDIMM if needed Note that the power to the FBDIMM socket must be removed before a hot add FBDIMM is inserted or removed Applying or re moving the power to a FBDIMM socket is a system platform function 3 7 Hot replace Hot replace of FBDIMM is accomplished through combining the hot remove and hotadd processes Rev 1 4 2009 ELECTRONICS FBDIMM DDR2 SDRAM 4 0 Pin Configuration Table 4 DDR2 240 Pin FBDIMM Configurations Front side Back side P
50. differential point to point electrical signaling The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM in the host direction The southbound output link forwards this same data to the next FBD The northbound input link is 14 lanes wide and carries read return data or status information from the next FBDIMM in the chain back towards the host The northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally 3 1 DDR2 Channel The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs The DDR2 channel supports two ranks of eight banks with 16 row column request 64 data signals and eight check bit signals There are two copies of address and com mand signals to support DIMM routing and electrical requirements Four transfer bursts are driven on the data and check bit lines at 800 MHz Propagation delays between read data check bit strobe lanes on a given channel can differ Each strobe can be calibrated by hardware state machines using write read trial and error or equivalent implementation Hardware aligns the read data and check bits to a single core clock The Advanced Memory Buffer provides four copies of the command clock phase references CLK 3 0 and write data check bit 3 2 SMBus Slave Interface The Advanced Memory Buffer suppo
51. e 2 1 Vppspp V 1 SPD Input LOW logic 0 voltage Vi DC 0 8 V 1 RESET Input HIGH logic 1 voltage Viu DC V 2 RESET Input LOW logic 0 voltage Vi DC 0 5 V 1 Leakage Current RESET IL 90 90 uA 2 Leakage Current link IL 5 5 uA 3 Note 1 Applies for SMB and SPD bus signals 2 Applies for AMB CMOS signal RESET 3 For all other AMB related DC parameters please refer to the high speed differential link interface specification Table 8 Timing Parameters Parameter Symbol MIN Typ Max Units Notes EI Assertion Pass Thru Timing tEI Propagatet 4 clks EI Deassertion Pass Thru Timing tEID Bitlock clks 2 El Assertion Duration tEI 100 clks 1 2 FBD to DDR out that latches 8 1 ns 3 FBD Cmd to DDR Write TBD ns DDR Read to FBD last DIMM 5 0 ns 4 Resample Pass Thru time 1 075 ns ResynchPass Thru time 2 075 ns Bit Lock Interval tBitLock 119 frames 1 Frame Lock Interval tFrameLock 154 frames 1 Note 1 Defined in FB DIMM Architecture and Protocol Spec 2 Clocks defined as core clocks 2x SCK input 3 DDR2 667 measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to the DRAMs 4 DDR2 667 measured from latest DQS input AMB TO start of matching data frame at northbound FB DIMM outputs ELECTRONICS 23 of 42 Rev 1 4 May 2009 FBDIMM Table 9 Power specification parameter and test condition DD
52. er specification Vdd 1 900V Vcc Max 1 575V 1GB M395T2863QZ4 Symbol E66 E65 E68 F76 F78 E76 Notes Unit PC2 5300 PC2 6400 Idle 0 2600 2600 1600 3200 1700 3200 1 5 mA Idd Idle 0 970 970 770 1070 770 1070 Q1 8V mA P idle 0 5 94 5 94 3 98 7 07 4 14 7 07 w 1 3400 3400 2300 4200 2500 4200 1 5v mA Idd Idle 1 970 970 770 1070 770 1070 Q1 8V mA P idle 1 7 20 7 20 5 09 8 65 5 40 8 65 active 1 3900 3900 2900 4700 3300 4700 1 5 mA Idd active 1 2335 2335 2235 2556 2456 2556 Q1 8V mA P active 1 10 58 10 58 8 81 12 26 9 86 12 26 active 2 3700 3700 2400 4500 2600 4500 1 5 mA 144 active 2 970 970 770 1070 770 1070 Q1 8V mA P active 2 7 67 7 67 5 24 9 12 5 56 9 12 W training 4000 4000 2300 4600 2400 4600 Q1 5V mA Idd training 970 970 670 1070 670 1070 Q1 8V mA P training 8 14 8 14 4 90 9 28 5 05 9 28 Vdd Max 1 900V Vcc 1 575V 2GB M395T5663QZ4 Symbol E66 E65 E68 E63 F76 F78 E76 Notes Unit PC2 5300 PC2 6400 Idle 0 2600 2600 1600 1500 3200 1700 3200 1 5 mA Idd Idle 0 1240 1980 1040 1040 1340 1040 1340 1 8 mA P idle 0 6 45 7 86 4 50 4 34 7 59 4 65 7 59 Idle 1 3400 4000 2300 1900 4200 2500 4200 1 5v mA Idd Idle 1 1240 1980 1040 1040 1340 1040 1340 1 8V mA idle 1 7 71 9
53. gt ODT all SDRAMs CB4 104 04 SDA BAO BA2 all SDRAMs 50 so sone 25800 SDRAMS cB7 1 07 07 RESET CAS all SDRAMs WE all SDRAMs SCK SCK CK CK all SDRAMs All address command control clock V Terminators Serial PD PE Vcc AMB WP A0 A1 A2 VppsPp dL Vpp 00 017 AMB SAO 5 1 5 2 VREF 00 017 Note 1 4 4 D0 D17 SPD AMB 1 DQ to I O wiring may be changed within a byte 2 There are two physical copies of each address command control clock ELECTRONICS 17 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM 5 3 4GB 512Mx72 Module M395T5160 populated as 2 ranks of x4 DDR2 SDRAMs
54. in Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 121 31 PN3 151 SN3 61 PN9 181 SN9 91 PS9 211 559 2 122 32 PN3 152 SN3 62 Vss 182 Vss 92 Vss 212 Vss 3 123 33 Vss 153 Vss 63 PN10 183 SN10 93 PS5 213 SS5 4 Vss 124 Vss 34 PN4 154 SN4 64 PN10 184 SN10 94 PS5 214 555 5 125 35 4 155 584 65 Vss 185 Vss 95 Vss 215 Vss 6 Vpp 126 Vpp 36 Vss 156 Vss 66 PN11 186 SN11 96 PS6 216 556 7 127 37 5 157 SN5 67 187 SN11 97 PS6 217 556 8 Vss 128 Vss 38 PN5 158 SN5 68 Vss 188 Vss 98 Vss 218 Vss 9 Vcc 129 Voc 39 Vss 159 Vss KEY 99 PS7 219 SS7 10 130 40 13 160 SN13 69 Vss 189 Vss 100 PS7 220 557 11 Vss 131 Vss 41 13 161 SN13 70 PSO 190 sso 101 Vss 221 Vas 12 Voc 132 42 Vss 162 Vss 71 50 191 550 102 58 222 558 13 133 43 Vss 163 Vss 72 Vss 192 Vss 103 PS8 223 558 14 Vss 134 Vss 44 RFU 164 RFU 73 PS1 193 551 104 Vss 224 Vss 15 Vor 135 45 RFU 165 RFU 74 51 194 551 105 225 16 VID1 136 VIDO 46 Vss 166 Vss 75 Vss 195 Vss 106 226 RFU 17 RESET 137 DNU M Test 47 Vss 167 Vss 76 PS2 196 552 107 Vss 227 Vss 18 Vss 138 Vss 48 PN12 168 SN12 77 PS2 197 552 108 228 5 19 RFU 139 49 12 169 SN12 78 Vss 198 Vss 109 229 5 20 RFU 140 RFU 50 Vss 170 Vss 79 PS3 199 553 110 Vss 230 Vas 21 Vss 141 Vss 51 PN6 171 SN6 80 PS3 200 553 111 231 22 142 SNO 52 PN
55. ing etc They include the time of flight of interpolators or other clock adjustment mechanisms They do not include the phase delays caused by finite PLL loop bandwidth because these de lays are modeled by the PLL transfer functions 11 Direct measurement of phase jitter records over 1016 periods is impractical It is expected that the jitter will be measured over a smaller yet statistically significant sample size and the total jitter at 1018 samples extrapolated from an estimate of the sigma of the random jitter components 12 Measured with SSC enabled on reference clock generator 13 As measured after the phase jitter filter This number is separate from the receiver jitter budget that is defined by the TRXTotal MIN parameters ELECTRONICS 28 of 42 Rev 1 4 May 2009 FBDIMM DDR2 SDRAM Table 13 Differential Transmitter Output Specifications Values Parameter Symbol Units Comments MIN MAX Differential peak to peak output voltage for large voltage swing VIX DIFFp p_L 900 1 300 EQ1 3 1 Differential peak to output voltage for regu lar voltage swing VTX DIFFPp p 800 mV EQ Note1 Differential peak to peak output voltage for small voltage swing VIX DIFFp p_S 520 mV EQ1 Note1 DC common code output voltage for large voltage 375 mV EQ2 Note1 swing DC common code output
56. ks that enable multiple memory modules to be connected serially to a given channel Memory system architecture perspective FB DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM A lot of new technologies are integrated into this solution in order to achieve this scalable higher speed memory solution Serial link interface with packet data format and dedicated read write paths are key attribute in FB DIMM protocol Point to Point interconnect with fully differential signaling and de emphasis scheme are key attribute in FBD channel link Clock recovery by using data stream is key attribute in FBD clocking FB DIMM supports both clock and resampling mode options CRC Cyclic Redundancy Check bits are transferred with data stream for reliability at high speed data transaction Failover mechanism supports system running with dynamic IO failure Finally all FB DIMM is connected in daisy chain manner Thus every interconnection between AMB advanced memory buffer to AMB AMB to Host and AMB to DRAM is point to point interconnection which allows higher data transfer bandwidth Figure 1 shows a lot of new technologies integrated with FBD solution Two unidirectional links Northbound Protocol Packet ADDR CMD DATA CMD Daisy Chain SB ADDR CMD Wdata Connection Upto 8 Host pre p ADDR A NB Rdata Rer 008 CLK
57. on the FBD Southbound command and data connection via Command Wdata frames 72 bits of data are trans ferred for every FBD Command Wdata frame Two Command Wdata frames match the 18 byte data transfer of an ECC DDR DRAM a single DRAM command clock A DRAM burst of 8 transfers from a single channel or a burst of 4 from two lock step channels provides a total of 72 bytes of data 64 bytes plus 8 bytes ECC When the FBD frame rate matches the DRAM command clock the Southbound command and data connection will exhibit one half the peak theoretical throughput of a single DRAM channel For example when using DDR2 533 DRAMs the peak theoretical bandwidth of the Southbound command and data connection is 2 133 GB sec The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical throughput of the Northbound data connection and the Southbound command and data connection When the FBD frame rate matches the DRAM command clock this is equal to 1 5 times the peak theoretical throughput of a single DRAM channel For example when using DDR2 533 DRAMs the peak theoretical throughput of a DDR2 533 channel would be 4 267 GB sec while the peak theoretical throughput of an FBD 533 channel would be 6 4 GB sec 3 5 Hot add The FBDIMM channel does not provide a mechanism to automatically detect and report the addition of a new FBDIMM south of the cur rently active last FBDIMM It is assumed the system will be notifie
58. on the channel is required for interpolator training Min Transition Density Using Reference CLK Not in Phase DRAM 6 Transitions Adjust edge phase by Min Transition Density 4 4 DRAM J utt DQs ADDR CLK CMD Rx Tx SB ADDR CMD Wdata ANB 512 Transfers Host NB Rdata gt Clk_Ref 4 i i Clock Reference CLK Recovery DRAM LLLI 210058 Figure 3 FB DIMM Clocking 2 4 FBDIMM Protocol FB DIMM channel has two unidirectional communication paths south bound and north bound South bound and north bound use phys ically different signal path South and north mean direction of signal transaction Southbound means direction of signals running from the host controller toward the DIMMs North is the opposite of south Due to nature of memory operation southbound carries information in cluding command to DRAM address to DRAM and write data to DRAM while north bound carries read data from DRAM In channel pro tocol point of view southbound and northbound have different data frame formats and frame format size is optimized to ratio of read and write Data transfer perspective read data transfer rate of north bound is twice faster than write data transfer Higher channel utilization achieves with asymmetric read and write data transfer rate Sout bound Northbound Command with Address CMD R Data x72bits Command with Address
59. rgy for reliable RX reception Each symbol must comply with both the single pulse mask and the cumulative eyemask 6 The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference in the RX Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols This number does not include the effects of SSC or reference clock jitter This number includes setup and hold of the RX sampling flop Defined as the dual dirac deterministic timing error 0 Allows for 15 mV DC offset between transmit and receive devices A gt 30 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 11 The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if Vax pierp p is 200 mV the maximum AC peak to peak common mode is the lesser of 200 mV 0 45 90 mV and 12 One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed 13 The termination small signal resistance tolerance across voltage from 100 mV to 400 mV shall not exceed 5 W with regard to the average of the values measured at 100 mV and at 400 mV for that pin 14 This number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component of
60. rts an SMBus interface to allow system access to configuration registers independent of the FBD link The Advanced Memory Buffer will never be a master on the SMBus only a slave Serial SMBus data transfer is supported at 100 kHz SMBus access to the Advanced Memory Buffer may be a requirement to boot a system This provides a mechanism to set link strength frequency and other parameters needed to insure robust operation given platform specific configurations It is also required for diagnostic support when the link is down The SMBus address straps located on the DIMM connector are used by the Advanced Memory Buffer to get its unique ID 12 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 3 3 FBD Channel Latency FBD channel latency is measured from the time a read request is driven on the FBD channel pins to the time when the first 16 bytes 2nd chunk of read completion data is sampled by the memory controller When not using the Variable Read Latency capability the latency for a specific FBDIMM on an FBD channel is always equal to the latency for any other FBDIMM on that channel However the latency for each FBDIMM in a specific configuration with some number of FBDIMMs installed may not be equal to the latency for each FBDIMM in a configuration with some different number of FBDIMMs installed As more DIMMs are added to the FBD channel additional latency is required to read from each DIMM on the channel Because the FBD channel i
61. s based on the point to point interconnection of buffer components between DIMMs memory requests are required to travel through N 1 buffers before reaching the Nth buffer The result is that a four DIMM channel configuration will have greater idle read latency compared to a one DIMM channel configuration The Variable Read Latency capability can be used to reduce latency for DIMMs closer to the host The idle latencies listed in this section are representative of what might be achieved in typical AMB designs Actual implementations with latencies less than the values listed will have higher application performance and vice versa 3 4 Peak Theoretical Throughput An FBD channel transfers read completion data on the FBD Northbound data connection 144 bits of data are transferred for every FBD Northbound data frame This matches the 18 byte data transfer of an ECC DDR DRAM in a single DRAM command clock A DRAM burst of 8 from a single channel or a DRAM burst of four from two lock stepped channels provides a total of 72 bytes of data 64 bytes plus 8 bytes ECC The FBD frame rate matches the DRAM command clock because of the fixed 6 1 ratio of the FBD channel clock to the DRAM command clock Therefore the Northbound data connection will exhibit the same peak theoretical throughput as a single DRAM channel For ex ample when using DDR2 533 DRAMs the peak theoretical bandwidth of the Northbound data connection is 4 267 GB sec Write data is transferred
62. sable Calibrate El 1 s d A Training 180 A Testing 181 Polling TS2 4 Config TS3 LO r c d 105 Recalibrate NOP2 gt Figure 13 AMB Initialization Flow Diagram The states in the AMB Initialization Flow diagram are Disable The channel is inactive and the interface signals are in a low power Electrical Idle condition Training The initial bit alignment and frame alignment training is done in this state Testing Each bit lane is individually tested in this state Polling The channel capabilities of the individual AMB devices are communicated in this state Config The channel width configuration is communicated to the AMB devices in this state LO The channel is active and frames of information are flowing between the host and the AMB devices Recalibrate The channel is momentarily idled to allow TX and Rx circuits to be recalibrated LOs The channel is in a low latency power saving condition Optional Each bit lane is initialized mosly independently to support fault tolerance The transitions in the figure represent the transitions of the AMB core logic state machine and are taken when the transition event is detected on the minimum required number of thousand bit lanes The chain of FBD links connecting the host the AMBs must each be initialized to esabish the timing for broadcasting data frames in the so
63. t 4 123 gt 1 27 0 10 gt 4 Back 4 3 0 max Jo ls ol D D 34 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 8 2 128Mbx8 based 256Mx72 Module 2 Ranks M395T5663QZ4 E 133 35 gt 2x3 25 gt 126 85 gt 2x 2 50 MIN gt 5 EN V 8 5 D fo o o o H o o 2 gt E 2x DIA 2 0 0 1 0 XS 5 a Y b ac 4 o 1 1 lt 67 gt
64. the end to end channel skew in the AMB specification 15 Measured from the reference clock edge to the center of the input eye This specification must be met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver 16 This bandwidth number assume the specified minimum data transition density Maximum jitter at 0 2 MHz is 0 05 UI 17 The specified time includes the time required to forward the El entry condition 18 BER per differential lane VRX DIFFp p 2X Vgx p Vnx p 5 DC avg of Vax p 1 2 EQ 6 Vax p 2 Min Vax p 2 EQ 7 2 EQ 8 31 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 7 0 CHANNEL INITIALIZATION This chapter defines the process of initializing the FBD channel The FBD initialization process generally follows the top to bottom se quence of state transitions shown in the high level AMB Initialization Flow diagram in Figure The host must sequence the AMB devices through the Disable back to Disable Training Testing and Polling states in order to transition the AMBs into the active channel LO state The value in parenthesis in each state bubble indicates the condition activity of the links during these states Power up Di
65. uthbound direction and for merging data frame in the northbound direction The AMBs on the channel are generally initialized as a group but because each AMB is individually addressable many alternate may alternate initialization sequences may be employed 32 of 42 Rev 1 4 May 2009 ELECTRONICS FBDIMM DDR2 SDRAM 8 0 Physical Dimensions 8 1 128Mbx8 based 128Mx72 Module 1 Rank E 133 35 2 3 25 126 85 2 2 50 MN 5 Nu U e
66. voltage for small volt ee 135 280 mV EQ2 Note1 2 age swing De emphasized differential output voltage ratio _ for 3 5 dB de emphasis VrX DE 3 5 Ratio 30 0 dB 1 3 4 De emphasized differential output voltage ratio 5 for 6 0 dB de emphasis VTX DE 6 0 Ratio 5 0 10 48 peak to peak common mode output voltage for large swing VTX CM ACp p L 90 mV EQ7 Note1 5 AC peak to peak common mode output voltage regular swing VTX CM ACp p R 80 mV EQ7 Note1 5 AC peak to peak common mode output voltage small swing VTX CM ACp p S 70 EQ7 Note1 5 Maximum single ended voltage in El condition DC AC g VTX IDLE SE 50 mV 6 Maximum single ended voltage in El condition DC AC 9 8 VTX IDLE SE DC 20 6 Maximum peak to peak differential voltage El condition 3 VTX IDLE DIFFp p 40 Single ended voltage w r t VSS on D D VTX SE 75 750 mV 1 7 Minimum TX eye width 3 2 and 4 0 Gb s UI 1 8 Minimum TX eye width 4 8 Gb s TTX EYE MIN4 8 UI 1 8 Maximum TX deterministic jitter 3 2 and 4 8Gb s Trx DJ DD 02 UI 1 8 9 Maximum TX deterministic jitter 4 8 Gb s 0 00 4 8 TBD UI 1 8 9 Insantaneous pulse width TTX PULSE 0 85 Ul 10 Differential TX output rise fall time TTX RISE TTX FALL 30 90 ps 20 80 voltage Note1 Mismatch between rise and fall times TTX RF MISMATCH 20 ps Differential return loss RLTTXx DIFF dB 1 GHz 2 4 GHz Note 11 Common mode return loss 1 GHz 2 4 GHz Note 11 Tr
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