Samsung M393T2950GZ3-CD5 memory module
Contents
1. f 1 27 0 10 m A B 63 00 n k B _ 55 00 J TH Eb 3 00 400 p S 080005 N i 2 80 0 20 5 70x Py 2 90 4 00 ae 1 50 0 10 1 00 B Detail A Detail B The used device is 64M x8 DDR2 SDRAM FBGA DDR2 SDRAM Part K4T51083QG 23 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 14 2 64Mbx8 128Mbx4 based 128Mx72 Module 2 1 Ranks2. VSS RS1 RSO DQSO NW DMO DQS9 DQSO NC DQS9 DM CS 09 Das DM CS Das Das DM CS 09 Das DM CS Das Das DQ0 w 1 0 0 0 804 w 1 00 0 DQ1 w 1 0 1 DO 1 0 1 D18 DQ5 w 1 0 1 DO 0 1 D27 DQ2 w 1 02 I O 2 DQ6 w 1 0 2 02 DQ3 w 1 0 3 3 DQ7 w 1 0 3 1 03 0051 W DM1 DQS10 e DQS1 NC DQS10 DM CS DOS DM CS Das DAs DM CS pas Das DM CS 09 Das DQ8 w 1 00 O 0 DQ12 w 1 00 I O 0 DQ9 1 0 1 D1 1 D19 DQ13 wY 1 0 1 D10 0 1 D28 0010 1 0 2 2 DQ14 w 1 02 __ 1 02 DQ11 1 03 O 3 DQ15 w 1 0 3 __ 0 3 5052 DM2 DQS11 MW DQS2 t NC DQS11 DM CS Das Das DM CS Das DOS DM CS pas Das DM CS Das 1 0 0 O 0 1 0 0 1 0 0 DQ17 A 1 0 1 D2 O 1 020 DQ21 w 1 0 1 D11 1 D29 DQ18 1 0 2 O 2 DQ22 w 1 0 2 2 DQ19 A 1 0 3 O 3 DQ23 1 0 3 5053 DM3 DQS12 0053 NC DQS12
3. M393T5750GZ3 M393T5750GZA ane Vill nits Millimeters lt 133 35 4 00 x PLL 2 C 30100 2 1 0 max 4 1 7 1 27 0 1 A B Bersm lt 63 00 AV k E 55 00 UI 2 5 C 3 00 5 00 9 4 00 400 S _ 0 80 0 05 gt gt d ei L 2 80 0 20 4 1 1 A i as 4 00 1 50 0 10 1 00 Detail A Detail B The used device is 128M x4 DDR2 SDRAM FBGA DDR2 SDRAM Part K4T51043QG 25 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 15 0 240 Pin DDR2 Registered DIMM Clock Topology Ons nominal PLL DDR2 SDRAM OUT1 120 ohms 120 ohms IN DDR2 SDRAM CKO Reg A 120 ohms OUTN 120 ohms 7 Feedback In Feedback Out Reg B Note 1 The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to Ons nominal 2 Input output and feedback clock lines are terminated from line to l
4. M393T2953GZ3 M393T2953GZA M393T2950GZ3 M393T2950GZA Units Millimeters 133 35 4 00 2 2 PLL C N Y 47 max I A B Ec 63 00 Fw zm u 55 00 2 E 2 5 C 3 00 5 00 9 7 4 00 0 80 0 05 gt _ X b i 3 80 Jr 0 20 1 EN 250 A 4 00 Jc 1 50 0 10 44 00 _ Detail A Detail B The used device is 64M x8 128M x4 DDR2 SDRAM FBGA DDR2 SDRAM Part NO K4T51083QG KAT51043QG Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 14 3 128Mbx4 based 256Mx72 Module 2 Ranks
5. DDR2 SDRAM Vss RSO DQSO W 0 0059 DQSO NC DQS9 VW DM CS 005 DM CS 005 DOS DQ0 w 1 00 DQ4 w 1 00 DQ1 70 1 DO DQ5 w 1 0 1 D9 DQ2 WY 1 0 2 wH 1 02 w 1 0 3 DQ7 w 1 03 DQS1 WwW DM1 DQS10 DQS1 NC DQS10 DM CS DASI DM CS DQ8 w 1 00 DQ12 w 1 0 0 DQ9 w 1 01 D1 DQ13 Ww 1 01 D10 DQ10 w 1 02 DQ14 w 1 0 2 0011 1 0 3 DQ15 w 1 03 DQS2 DM2 DQS11 WS DQS2 NW NC DQS11 DM CS DOSI DM CS 005 005 DQ16 w 1 00 DQ20 w_ 1 0 0 DQ17w_ 1 01 D2 DQ21 A 1 01 D11 DQ18B w 1 0 2 922 0 2 DQ19 w 1 0 3 DQ23 w 1 0 3 DQS3 DM3 DQS12 NN DQS3 MW NC DQS12 M DM CS 005 DOS DM CS bas DQS DQ24 1 00 DQ28 1 0 0 DQ25 A 1 01 D3 DQ29 w 1 01 D12 1 02 DQ30 1 02 027 1 03 DQ31 w 1 03 DQS4 DM4A DQS13 WS DQS4 WwW NC DQS13 DM CS DOSI DM CS DOSI 1 0 0 DQ36 w 1 00 DQ33 1 0 1 04 DQ37 Ww 1 0 1 D13 DQ34 1 02 DQ38 1 0 2 DQ35 A 4 1 0 3 DQ39 1 03 DQS5 WwW DM5 DQS14 NS DQS5 NAE NC DQS14 DM CS DOSI DM CS pas 005 DQ40 w 1 0 0 44 0 0 DQ
6. 4 4 0 Pin Configurations Front side Back side 2 24 1 5 5 0 Pin Description 5 6 0 Input Output Functional Description 6 7 0 Functional Block e eo een ee 7 7 1 512MB 64Mx72 Module M393T6553GZ3 M393T6553GZA 2 7 7 2 1GB 128Mx72 Module M393T2953GZ3 M393T2953GZA nnn nn 8 7 3 1GB 128Mx72 Module M393T2950GZ3 M393T2950GZA 9 7 4 2GB 256Mx72 Module M393T5750GZ3 M393T5750GZA 10 8 0 Absolute Maximum DC Ratings 11 90 AC amp DC Operating Conditions 11 9 1 Recommended DC Operating Conditions SSTL 1 8 11 9 2 Operating Temperature Condition 4 4 12 9 3 input DC Logic Level M 12 CEN Pemex 12 9 5 AC Input Test Conditions n Res reu Dad 12 10 0 IDD Specification Parameters Definition 13 11 0 Operating Current Table LE 14 11 1 M393T6553GZ3 M393T6553GZA 512
7. defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BA1 to control which bank s to precharge If AP is high all banks will be pre charged regardless of the state of BAO If AP is low BAO and are used to define which bank to precharge DQ0 63 CBO CB7 In Out Data and Check Bit Input Output pins DMO DM8 input Masks write data when high issued concurrently with input data Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM Vpp Vss Supply and ground for the DDR SDRAM input buffers and core logic DQS0 DQS17 In Out Positive line of the differential data strobe for input and output data DQS0 DQS17 In Out Negative line of the differential data strobe for input and output data SA0 SA2 Input These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA SDA bus line to to act as a pullup This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time m Input to Vppspp to act as a pullup Serial EEPROM positive power supply wired to a separate power pin at the connector which supp
8. 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 1355 1175 1085 950 mA IDD1 1495 1360 1225 1135 mA IDD2P 552 512 472 432 mA IDD2Q 845 775 660 590 mA IDD2N 840 780 675 615 mA IDD3P F 820 740 660 580 mA IDD3P S 658 578 498 418 mA IDD3N 1080 965 850 780 mA IDDAW 1510 1350 1145 1030 mA 12048 1850 1680 1375 1205 IDD5B 1660 1495 1375 1210 mA IDD6 72 72 72 72 IDD7 2580 2155 2045 1935 mA DD6 DRAM current standby current of and Register Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap ELECTRONICS 14 of 26 Rev 1 0 July 2008 RDIMM 11 3 M393T2953GZ3 M393T2953GZA 1GB 64Mx8 18 Module DDR2 SDRAM 0 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 1125 1035 990 945 mA IDD1 1215 1170 1080 1080 mA IDD2P 144 144 144 144 mA IDD2Q 630 630 540 540 mA IDD2N 720 720 630 630 mA IDD3P F 540 540 540 540 mA IDD3P S 216 216 216 216 mA IDD3N 900 855 765 765 mA IDDAW 1350 1260 1080 1035 mA IDD4R 1620 1530 1260 1170 mA IDD5B 1350 1305 1260 1215 mA IDD6 144 144 144 144 mA IDD7 2250 1935 1890 1890 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loa
9. 3 of Part number 12th digit stands for Dummy Pad PCB products 3 A of Part number 12th digit stands for Parity Register products 2 0 Features Performance range F7 DDR2 800 E6 DDR2 667 D5 DDR2 533 CC DDR2 400 Unit Speed CL3 400 400 400 Mbps Speed CL4 533 533 533 400 Mbps Speed CL5 667 667 533 Mbps Speed CL6 800 Mbps CL tRCD tRP 6 6 6 5 5 5 4 4 4 3 3 3 CK standard 1 8V 0 1V Power Supply 1 8 0 1V 200 MHz fcx for 400Mb sec pin 267 MHz fc for 533Mb sec pin 3334 Hz fc for 667Mb sec pin 400MHz for 800Mb sec pin 4Banks Posted CAS Programmable CAS Latency 3 4 5 6 Programmable Additive Latency 0 1 2 3 4 and 5 Write Latency WL Read Latency RL 1 Burst Length 4 8 Interleave Nibble sequential Programmable Sequential Interleave Burst Mode Bi directional Differential Data Strobe Single ended data strobe is an optional feature Off Chip Driver OCD Impedance Adjustment On Die Termination with selectable values 50 75 150 ohms or disable Average Refresh Period 7 8us at lower than a Tease 85 3 9us at 85 lt Tease lt 95 Support High Temperature Self Refresh rate enable feature Serial presence detect with EEPROM DDR2 SDRAM Package 60ball FBGA 128Mx4 64Mx8 All of base components are Lead Free Halogen Free and RoHS compliant Note For detailed DDR2 SDRAM operation
10. CS Das DM CS Das DM CS 09 Das DM CS Das 005 024 1 0 0 00 DQ28 A 00 00 025 4 01 1 021 DQ29 w 1 0 1 D12 O 1 D30 026 4 1 02 2 DQ30 w 1 0 2 O 2 DQ27W 1 03 DQ31 A 1 03 O 3 0054 DM4 DQS13 0054 VW NC DQS13 DM CS 09 005 DM CS 005 DM CS 09 Das DM CS Das 005 2 1 0 0 __ 1 00 DQ36 A 1 00 O 0 DQ33 1 0 1 D4 __ 01 022 DQ37 1 0 1 D13 O 1 D31 DQ34 w 1 02 __ 1 02 DQ38 A 1 0 2 O2 DQ35 1 03 I DQ39 1 0 3 O 3 DQS5 DM5 DQS14 DQS5 NC DQS14 DM CS 09 005 DM CS Das Das DM CS Das DM CS Das 005 DQ40 w _ 1 0 0 O 0 DQ44 w 1 00 O 0 DQ41 A 1 0 1 D5 O 1 023 DQ45 1 0 1 D14 O 1 D32 DQ42 1 02 O 2 0046 1 0 2 2 DQ43 1 0 3 O 3 DQ47 W 1 03 O 3 5056 MM DM6 DQS15 e DQS6 NC DQS15 VN DM CS 09 Das DM CS 09 Das DM CS 09 505 DM CS Das 005 048 1 00 __ 1 00 DQ52 w 0 0 O 0 DQ49 1 0 1 I 1 024 DQ53 1 0 1 D15 O 1 D33 DQ50 1 02 __ O2 DQ54 w 1 0 2 O 2 DQ51 W 1 03 03 0055 4 1 0 3 3 Serial PD DQS7 WM 0 709516 WS 0057 NC DQS16 SCL le spa DM CS Das 595 DM CS 005 DM CS pas Das DM CS 09 005 WP AO 1 A2 0956 1 0 0 O 0 DQ60 A 1 0 0 00 DQ57 w 1 0 1 D7 O 1025 DQ61 1 0 1 D16 VO 1 D34 HR 0058 1 0 2 O 2 DQ62
11. Parameter Min Max Min Max Min Max Min Max Pare Number Symbol M393T6553GZ3 M393T2953GZ3 M393T2950GZ3 M393T5750GZ3 Units M393T6553GZA M393T2953GZA M393T2950GZA M393T5750GZA Input capacitance CK and CK CCK 11 11 11 11 Input capacitance CKE and cs 12 12 12 12 pF Input capacitance Address RAS CAS WE 12 12 12 12 12 Input output capacitance DQ DM 905 29 10 10 10 10 DMis internally loaded to match DQ and DQS identically 13 0 Electrical Characteristics amp AC Timing for DDR2 800 667 533 400 0 lt Toper lt 95 1 8V 0 1V Vpp 1 8V 0 1V 13 1 Refresh Parameters by Device Density Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active Refresh command time tRFC 75 105 127 5 195 327 5 ns 0 lt Tease lt 85 7 8 7 8 7 8 7 8 7 8 us Average periodic refresh interval tREFI 85 lt Tease lt 95 3 9 3 9 3 9 3 9 3 9 us 13 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin Speed DDR2 800 F7 DDR2 667 E6 DDR2 533 D5 DDR2 400 CC Bin CL tRCD tRP 6 6 6 5 5 5 4 4 4 3 3 3 Units Parameter min max min max min max min max tCK CL 3 5 5 ns tCK CL 4 3 75 8 3 75 3 75 5 ns tCK CL 5 3 8 3 75 ns tCK CL 6 2 5 8 ns tRCD 15 15 15 15 ns tRP 15 15 15 15 ns tRC 60 60 60 55 ns tRAS 45 70000 45 70000 45 70000 40 70000 ns Ban Rev 1 0 July 2008 ELECTRONICS RDIMM 13 3 Timin
12. gt DDR2 SDRAMs 00 035 S0 connects to DCS and S1 connects to CSR on a pair of Registers P 51 connects to DCS and 50 connects to CSR on another pair of Registers __ L CKO L PCK8 9 gt DDR2 SDRAMs 00 035 RESET PCK7 and PCK7 connects to all Registers RESET PCK7 gt Register Other signals connect to one pair of four Registers PCK7 gt CK Register 10 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 8 0 Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes Vpp Voltage on Vpp pin relative to Vss 10V 23V V 1 VDDQ Voltage on pin relative to Vss 0 5V 2 3V V 1 Voltage pin relative to Vss 0 5V 2 3V V 1 Vin Vout Voltage on any pin relative to Vss 0 5V 2 3V V 1 TsrG Storage Temperature 55 to 100 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 9 0 AC amp DC Operating Conditions
13. 9 1 Recommended DC Operating Conditions SSTL 1 8 Rating Symbol Parameter Units Notes Min Typ Max Supply Voltage 1 7 1 8 1 9 V Supply Voltage for DLL 1 7 1 8 1 9 4 Vppo Supply Voltage for Output 1 7 1 8 1 9 4 VREF Input Reference Voltage 0 49 Vppaq 0 50 Vppaq 0 51 1 2 Vit Termination Voltage 0 04 VREF Vggr 0 04 V 3 Note There is no specific device Vpp supply voltage requirement SSTL 1 8 compliance However under all conditions must be less than or equal to Vpp 1 The value of Vgge may be selected by the user to provide optimum noise margin in the system Typically the value of Vref is expected to be about 0 5 X Of the transmitting device and is expected to track variations in 2 Peak to peak AC noise on Vgge may not exceed 2 Vgge DC 3 of transmitting device must track of receiving device 4 AC parameters are measured with Vpp and Vpp tied together 11 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 9 2 Operating Temperature Condition Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 1 2 Note 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 2 At 85 95 C operation temperature range
14. 192 RAS 103 Vss 223 DM6 DQS15 14 Vss 134 DM1 DQS10 44 Vss 164 DM8 DQS17 73 WE 193 50 104 0056 224 NC DQS15 15 DQS1 135 NC DQS10 45 5058 165 0517 74 CAS 194 105 0056 225 Vss 16 DQS1 136 Vss 46 DQS8 166 Vss 75 195 106 Vss 226 DQ54 17 Vss 137 RFU 47 Vss 167 CB6 76 514 196 A13 107 DQ50 227 DQ55 18 RESET 138 RFU 48 CB2 168 CB7 77 ODT1 197 108 0051 228 Vss 19 NC 139 Vss 49 CB3 169 Vss 78 198 Vss 109 Vss 229 DQ60 20 Vss 140 DQ14 50 Vss 170 79 Vss 199 DQ36 110 0056 230 0061 21 2010 141 2015 51 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 Vss 22 142 Vss 52 CKEO 172 Vpp 81 DQ33 201 Vss 112 Vss 232 DM7 DQS16 23 Vss 143 DQ20 53 173 NC 82 Vss 202 DM4 DQS13 113 DQS7 233 0516 24 DQ16 144 DQ21 54 NC 174 NC 83 0054 203 NC DQS13 114 DQS7 234 Vss 25 DQ17 145 Vss 55 175 Vppo 84 DQS4 204 Vss 115 Vss 235 DQ62 26 Vss 146 DM2 DQS11 56 176 12 85 Vss 205 DQ38 116 DQ58 236 DQ63 27 0052 147 NC DQS11 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 Vss 28 DQS2 148 Vss 58 A7 178 Vpp 87 DQ35 207 Vss 118 Vss 238 VppsPp 29 Vss 149 DQ22 59 179 A8 88 Vss 208 DQ44 119 SDA 239 30 2018 150 2023 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1 90 DQ41 210 Vss NC No Connect RFU Reserved for Future Use 1 RESET Pin 18 is connected to both OE of PLL and Reset of register 2 The Test pin Pin 102 is reserved for bus analysis probes and is not connected o
15. DDR2 SDRAMs 00 017 100K ohms QERR ODTO R RODTO ODTO DDR2 SDRAMs 00 017 RST The resistors on A13 A14 A15 BA2 and the 7 Note signal line of Err_Out refer to the section Register PCK7 1 DQ to I O wiring may be changed per nibble Options for Unused Address inputs 2 Unless otherwise noted resister values are 22 Ohms 5 T CKO PCKO PCK6 PCK8 PCK9 gt DDR2 SDRAMs 00 08 S0 connects to DCS of Register CSR of Register2 CSR of P register 1 and DCS of register 2 connects to VDD E L CKO L PCK8 PCK9 gt DDR2 SDRAMs 00 08 RESET PCK7 and 7 connects to both Registers Other RESET PCK7 gt CK Register signals connect to one of two Registers 51 CKE1 and ODT1 are NC PCK7 gt Register 9 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 7 4 2GB 256Mx72 Module M393T5750GZ3 M393T5750GZA populated as 2 rank of x4 DDR2 SDRAMs
16. RESET __0 7 PCK7 gt Register 3 Unless otherwise noted resister values are 22 Ohms 5 PCK7 gt CK Register ELECTRONICS 7 of 26 Rev 1 0 July 2008 RDIMM DDR2 SDRAM 7 2 1GB 128Mx72 Module M393T2953GZ3 M393T2953GZA populated as 2 rank of x8 DDR2 SDRAMs RS1 RSO DQSO WS DQS4 0050 5054 0 0059 AW DM4 DQS13 NC DQS9 M gt NC DQS13 DM NU CS 00 DQS DW CS 005 DOSI DM NU CS 00 59 DM CS 005 DQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ0 1 00 O 0 DQ32 1 0 0 1 0 0 001 w4 1 01 DO O 1 D9 D
17. VopsPp Serial PD DQS8 WS nz DQS8 NAVAS Serial PD DM8 DQS17 A 4 B POSES NC DQS17 w SCL SDA 7 gt V 00 08 DW CS 505 REF RDQS RDQS WP A0 A1 wH 1 00 CB w 01 SA1 SA2 Vss CB2 102 w 1 03 w 4 1 04 CB5 w 5 Signals for Address and Command Parity Function M393T6553GZA CB6 w4 1 06 CB7 w 07 Ves CO Register 1 1 ene LEE 2 508 R RSO CS DDR2 SDRAMs 00 08 PAR IN PAR IN BAO BA1 E RBAO RBA1 gt 1 DDR2 SDRAMs 00 08 QERR Err Out A0 A13 wt RAO RA13 gt A0 A13 DDR2 SDRAMs 00 08 RAS wd RRAS gt RAS DDR2 SDRAMs 00 08 The resistors on Par_In A13 A14 A15 BA2 and the CAS wg S RORS CAS DDRA SDRAMS signal line of Err_Out refer to the section Register WE T RWE gt DDR2 SDRAMs 00 08 oh i CKEO0 w j E gt DDR2 SDRAMs 00 08 Options for Unused Address inputs ODTO R RODTO gt DDR2 SDRAMs D0 D8 RESET RST S0 connects to DCS and VDD connects to CSR on the register 51 CKE1 and ODT1 are NC 7 PCK7 PCKO PCK6 PCK8 gt DDR2 SDRAMs 00 08 P Note L 1 DQ to I O wiring may be changed within a byte L PCKO PCK6 PCK8 gt DDR2 SDRAMs 00 08 2 DQ DQS DM CKE S relationships must be maintained as shown
18. doubling refresh commands in frequency to 32ms period tREFI 3 9 us is required and to enter to self refresh mode at this temperature range an EMRS command is required to change internal refresh rate 9 3 Input DC Logic Level Symbol Parameter Min Max Units Notes Vig DC DC input logic high 0 125 Vppa 0 3 V Vi DC DC input logic low 0 3 Vrer 0 125 V 9 4 Input AC Logic Level DDR2 400 DDR2 533 DDR2 667 DDR2 800 Symbol Parameter Units Min Max Min Max AC input logic high Vrer 0 250 Vrer 0 200 V Vii AC AC input logic low 0 250 Vrer 0 200 V 9 5 AC Input Test Conditions Symbol Condition Value Units Notes VREF Input reference voltage 0 5 V 1 VswiNG MAX Input signal maximum peak to peak swing 1 0 V 1 SLEW Input signal minimum slew rate 1 0 Vins 2 3 Note 1 Input waveform timing is referenced to the input signal crossing through the AC level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from Vggr to Vi AC min for rising edges and the range from Vggr to Vi AC max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from AC to Vi AC on the positive transitions and Vj AC to Vj AC on the negative transitions
19. min min VSWING MAX VREF DC Vii AC max Vss delta TF delta TR V VL AC min V Falling Slew Rising Slew VHAC Ver delta TF delta TR lt AC Input Test Signal Waveform gt 12 0126 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 10 0 IDD Specification Parameters Definition IDD values are for full operating range of Voltage and Temperature Symbol Proposed Conditions Units Note Operating one bank active precharge current IDDO tCK IDD tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands mA Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating one bank active read precharge current IOUT BL 4 CL CL IDD AL 0 tCK IDD tRC tRC 100 tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDDAW IDD1 mA Precharge power down current IDD2P All banks idle tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs mA FLOATING Precharge quiet standby current m IDD2Q banks idle tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data mA bus inputs are FLOATING Precharge standby current IDD2N banks
20. Notes min max min max DQ output access time from CK CK tAC 500 500 600 600 ps DQS output access time from CK CK tDQSCK 450 450 500 500 ps CK HIGH pulse width tCH 0 45 0 55 0 45 0 55 tCK CK LOW pulse width tCL 0 45 0 55 0 45 0 55 tCK CK half pulse period tHP Min tCL tCH x Min tCL tCH x ps 11 12 Clock cycle time CL x tCK 3750 8000 5000 8000 ps 15 DQ and DM input hold time differential strobe tDH base 225 275 6 7 8 21 28 DQ and DM input setup time differential strobe tDS base 100 x 150 x ps 6 7 8 20 28 DQ and DM input hold time single ended strobe tDH1 base 25 25 x ps 6 7 8 26 DQ and DM input setup time single ended strobe tDS1 base 25 x 25 x ps 6 7 8 25 Control amp Address input pulse width for each input tIPW 0 6 x 0 6 x tCK DQ and DM input pulse width for each input tDIPW 0 35 x 0 35 x tCK Data out high impedance time from CK CK tHZ x tAC max x14 tAC max ps 18 DQS DQS low impedance time from CK CK tLZ DQS tAC min tAC max tAC min tAC max ps 18 DQ low impedance time from CK CK tLZ DQ 2 tAC min tAC max 2 tAC min tAC max ps 18 DQS DQ skew for DQS and associated DQ signals tDQSQ x 300 x 350 ps 13 DQ hold skew factor tQHS x 400 x 450 ps 12 DQ DQS output hold time from DOS tQH tHP tQHS x tHP tQHS x ps DQS latching rising transitions to associated clock edges tDQSS 0 25 0 25 0 25 0 25 tCK 005 input HIGH pulse width tDQSH 0 35 x 0 35 tCK 005 input LOW pulse width tDQSL 0 35 x 0 35 tCK DQS fallin
21. please refer to Samsung s Device operation amp Timing diagram 3 0 Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 128Mx4 512Mb based Module A0 A13 0 9 11 BAO BA1 A10 64Mx8 512Mb based Module A0 A13 0 9 BAO BA1 A10 id Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 4 0 Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 121 Vss 31 DQ19 151 Vss 61 A4 181 91 Vss 211 DM5 DQS14 2 Vss 122 DQ4 32 Vss 152 DQ28 62 182 92 0055 212 NC DQS14 3 DQO 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 Vss 4 DQ1 124 Vss 34 DQ25 154 Vss 64 184 94 Vss 214 DQ46 5 Vss 125 DMO DQS9 35 Vss 155 DM3 DQS12 KEY 95 DQ42 215 DQ47 6 5950 126 NC DQS9 36 5053 156 NC DQS12 65 Vss 185 CKO 96 DQ43 216 Vss 7 0050 127 Vss 37 DQS3 157 Vss 66 Vss 186 97 Vss 217 DQ52 8 Vss 128 006 38 Vss 158 DQ30 67 187 98 DQ48 218 DQ53 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC Par In 188 A0 99 DQ49 219 Vss 10 DQ3 130 Vss 40 DQ27 160 Vss 69 189 100 Vss 220 RFU 11 Vss 131 DQ12 41 Vss 161 CB4 70 A10 AP 190 BA1 101 SA2 221 RFU 12 DQ8 132 DQ13 42 CBO 162 CB5 71 BAO 191 102 222 Vss 13 DQ9 133 Vss 43 CB1 163 Vss 72
22. 0 2 DQ3 w 4 1 03 DQ35 w 1 0 3 DQ4 w 04 6 1 0 4 DQ5 w 1 05 DQ37w 1 05 DQ6 wH 1 06 DQ38_ 1 06 DQ7 w4 7 00394 4 7 DQS1 0055 VW DQS1 NAE DQS5 DM1 DQS10 4 DM5 DQS14 A 3 4 NC DQS10 NC DQS14 M DM NU CS 09 005 DM NU CS Das RDQS RDQS RDQS RDQS DQ8 1 00 040 4 1 00 DQ9 w 1 0 1 01 DQ41 w 1 0 1 D5 DQ10 Ww 1 02 042 1 0 2 DQ11 A 1 0 3 DQ43_ w 1 0 3 DQ12 w 04 DQ44_ 04 DQ13 wr 5 DQ45 A4 1 05 DQ14 wr 1 06 046 0 6 DQ15 wr 7 047 7 5052 DQS6 M DQS2 DQS6 MAS DM2 DQS11 4 DM6 DQS15 A 4 NC DQS11 NC DQS15 WS DM NU CS 598 DM NU CS DQS DQS RDQS RDQS RDQS RDQS DQ16 _ 1 0 0 DQ48_ w 1 0 0 DQ17 w 1 01 D2 DQ49 w 1 01 06 DQ18 1 02 DQ50 w_ 1 0 2 DQ19 w 51 1 0 3 1 0 4 52 1 0 4 DQ21_ w 1 05 DQ53 w 1 05 DQ22 4 1 06 DQ54 1 06 DQ23 1 07 DQ55 7 5053 WW DQS7 M 053 DQS7 DM3 DQS12 v DM7 DQS16 A 4 NC DQS12 NC DQS16 DM NU CS 09 DQS DM NU CS 09 005 RDQS RDQS RDQS RDQS 024 4 1 0 0 056 4 1 00 DQ25 I O 1 D3 DQ57 A 00 1 07 DQ26 1 0 2 DQ58 w 1 0 2 027 1 03 59 1 03 DQ28 l O4 DQ60 w 1 0 4 DQ29 wH 1 05 DQ61 A 1 05 DQ30 1 06 062 1 06 DQ31 1 07 DQ63 7
23. 10 1710 1530 1530 mA IDDAW 2790 2520 1980 1980 mA 12048 2970 2700 2160 2160 15058 2790 2700 2520 2520 mA IDD6 288 288 288 288 mA IDD7 4500 3870 3780 3780 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 11 8 M393T5750GZ3 M393T5750GZA 2GB 128Mx4 36 Module considering Register and PLL current value TA 0 C 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 3180 2940 2700 2550 mA IDD1 3500 3250 3000 2840 mA IDD2P 1238 1148 1058 968 mA IDD2Q 2320 2180 1860 1720 mA IDD2N 2240 2140 1860 1760 mA IDD3P F 2170 2020 1870 1720 mA IDD3P S 1522 1372 1222 1072 mA IDD3N 2500 2400 2120 2020 mA IDDAW 3780 3370 2690 2550 mA IDD4R 4060 3640 2950 2800 mA IDD5B 4010 3700 3300 3080 mA IDD6 288 288 288 288 mA 1007 6210 5320 4970 4710 1006 DRAM current standby current of and Register Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 17 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 12 0 Input Output Capacitance 1 8 Vppg71 8V TA 259C
24. 3150 3150 3150 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 11 6 M393T2950GZ3 M393T2950GZA 1GB 128Mx4 18 Module considering Register and PLL current value 0 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 2130 1940 1840 1740 mA IDD1 2390 2190 2080 1970 mA IDD2P 784 724 664 604 mA IDD2Q 1340 1250 1070 980 mA IDD2N 1290 1220 1060 990 mA IDD3P F 1270 1170 1070 970 mA IDD3P S 946 846 746 646 mA IDD3N 1550 1480 1320 1250 mA IDDAW 2720 2360 1820 1730 mA 12048 3040 2660 2100 1990 IDD5B 2900 2660 2420 2270 mA IDD6 144 144 144 144 mA IDD7 4810 4020 3860 3700 mA DD6 DRAM current standby current of and Register Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 16 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 11 7 M393T5750GZ3 M393T5750GZA 2GB 128Mx4 36 Module TA 09C 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 2160 2070 1980 1980 mA IDD1 2340 2250 2160 2160 mA IDD2P 288 288 288 288 mA IDD2Q 1260 1260 1080 1080 mA IDD2N 1440 1440 1260 1260 mA IDD3P F 1080 1080 1080 1080 mA IDD3P S 432 432 432 432 mA IDD3N 17
25. 41_ wY 70 1 D5 DQ45 I O 1 D14 DQ42 N 1 0 2 DQ46 w 1 0 2 DQ43_w 1 03 047 4 1 0 3 DQS6 DM6 DQS15 VN DQS6 MM NC DQS15 DM CS bas Das DM CS 09 DQS i DQ48 A 1 0 0 952 1 0 0 DQ49 A I O 1 D6 DQ53 I O 1 D15 0950 102 DQ54 w 102 icm DQ51 1 0 DQ55 A 1 0 3 WP AO A1 A2 DQS7 w DM7DQS16 w DQS7 NC DQS16 SA1 SA2 DM CS DaS DOS DM CS DQ56 1 0 0 DQ60 w 1 0 0 DQ57 w 1 0 1 07 DQ61 1 01 D16 58 1 0 2 DQ62 1 02 DQ63 1 0 3 DQS8 w DMB8 DQS17 VppsPD 4 Serial PD DQS8 NW NC DQS17 WS DM CS DM CS DOS Vpp Vppa 00 017 w 1 00 CB4 w 1 00 CB1 w 1 01 D8 CB5 w 1 01 D17 CB2 w 102 Ww 102 VREF t 05017 w 4 1 03 CB7 w 1 03 T Vss 4 00 017 1 2 50 A gt DDR2 SDRAMs 00 017 Signals for Address and Command Parity Function M393T2950GZA BAO BA1 w L RBAO RBA1 gt BAO BA1 DDR2 SDRAMs 00 017 A0 A13 Ww G 3 gt A0 A13 DDR2 SDRAMs 00 017 Vas CO Register A Vpp _ Co Register B RAS 1 RRAS gt RAS DDR2 SDRAMs 00 017 Vpp C1 C1 Bad CAS M S gt CAS DDR2 SDRAMs 00 017 ATE mU _ WE WwW T RWE gt WE DDR2 SDRAMs DO D17 PALIN PARIN QERR Out w gt
26. 64 8 9 Module 14 11 2 M393T6553GZ3 M393T6553GZA 512 64 8 9 Module 14 11 3 M393T2953GZ3 M393T2953GZA 1 64 8 18 Module 2 15 11 4 M393T2953GZ3 M393T2953GZA 1 64 8 18 Module 15 11 5 M393T2950GZ3 M393T2950GZA 1GB 128Mx4 18 Module 16 11 6 M393T2950GZ3 M393T2950GZA 1GB 128Mx4 18 Module 16 11 7 M393T5750GZ3 M393T5750GZA 2GB 128Mx4 36 Module 1 17 11 8 M393T5750GZ3 M393T5750GZA 2GB 128Mx4 36 Module 17 12 0 Input Output Capacitance 18 13 0 Electrical Characteristics 8 AC Timing for DDR2 800 667 533 400 18 13 1 Refresh Parameters by Device Density 44 1 1 18 13 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin 2 21 18 13 3 Timing parameters by speed grade DDR2 800 and 2 667 11122 19 13 4 Timing parameters by speed grade DDR2 533 and 2 400 11122 21 14 0 Physical Dimensions 23 14 1 64Mbx8 based 64 72 Module 1 Ran
27. CK at OV CKE x 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING Low Power mA Operating bank interleave read current All bank interleaving reads IOUT BL 4 CL CL IDD AL tRCD IDD 1 tCK IDD tCK IDD tRC 1207 tRC IDD tRRD tRRD IDD tFAW tFAW IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid mA commands Address bus inputs are STABLE during DESELECTS Data pattern is same as IDD4R Refer to the fol lowing page for detailed timing conditions 13 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 11 0 Operating Current Table 11 1 M393T6553GZ3 M393T6553GZA 512 64 8 9 Module 0 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 765 675 675 630 mA IDD1 855 810 765 765 mA IDD2P 72 72 72 72 mA IDD2Q 315 315 270 270 mA IDD2N 360 360 315 315 mA IDD3P F 270 270 270 270 mA IDD3P S 108 108 108 108 mA IDD3N 540 495 450 450 mA IDDAW 990 900 765 720 mA 12048 1260 1170 945 855 IDD5B 990 945 945 900 mA IDD6 72 72 72 72 mA IDD7 1890 1575 1575 1575 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 11 2 M393T6553GZ3 M393T6553GZA 512MB 64Mx8 9 Module considering Register and PLL current value 0
28. DQS7 DM3 DQS12 DM7 DQS16 NC DQS12 NC DQS16 DM NU CS DQS DQS DW CS 59 DM NU CS 005 DM CS DQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ24 w_ 1 0 0 0 0 DQ56 1 0 0 1 0 0 DQ25 1 01 D3 O 1 D12 DQ57 1 01 D7 1 D16 DQ26 1 0 2 O 2 DQ58 w_ 1 0 2 VO 2 027 1 03 O 3 DQ59 A 1 0 3 DQ28 1 0 4 0 4 DQ60 1 0 4 4 DQ29 A 1 05 O 5 DQ61 A 1 05 1 05 DQ30 A 1 06 O 6 DQ62 w 1 06 DQ31 1 07 O 7 DQ63 1 0 7 7 DQS8 MN E Vi 2 Seal PD DQS8 MW DDSPD DM8 DQS17 ESSE T NC DQS17 w tt 1 sc 00 017 DM NU CS Das 5 DW CS Das DAS RDQS RDQS RDQS RDQS WP AO A1 A2 Ww 1 00 0 0 VREF 1 CB w 017 b T 2 WH 1 02 O 2 SA0 SA1 SA2 Vss 00 017 w 1 03 O 3 CB4 w 1 04 O 4 CBS w 05 O 5 Signals for Address and Command Parity Function M393T2953GZA CB6 w4 1 06 O 6 CB7 w4 07 O 7 Vas CO Register A Vpp Co Register B 505 wH RSO gt CS DDR2 SDRAMs 00 08 Vpp C1 Vpp C1 51 wH 1 2 1 gt CS DDR2 SDRAMs 09 017 PAR IN PAR IN PPO PAR IN PPO w R RBAO RBAM gt BAO BA1 DDR2 SDRAMs 00 017 GERR QERR Out A0 A13 RAO RA13 gt A0 A13 DDR2 SDRAMs 00 017 100K ohms Q RAS G RRAS RAS DD
29. Q33 Ww I O 1 04 1 0 1 013 002 w 1 02 O 2 DQ34 w 00 2 2 DQ3 w 10 3 O 3 DQ35_ Ww 1 0 3 1 0 3 004 w 1 04 O 4 4 1 0 4 005 w 1 05 O 5 DQ37w 1 05 5 006 wH 1 06 O 6 DQ38_ 1 0 6 1 0 6 DQ7 w 1 07 O 7 DQ39_ r 7 1 07 DQS1 M 5055 09581 MM 5055 NAE DM1 DQS10 DMS5 DQS14 NC DQS10 NC DQS14 DM NU CS Das DOS CS 005 29 DM NU CS 00 DQS DM CS 005 DQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS DQ8 w 1 00 O 0 DQ40 w 1 0 0 1 0 0 DQ9 w 1 01 D1 O 1 D10 DQ41w I O 1 D5 1 0 1 D14 DQ10 w 1 0 2 O 2 DQ42 A 1 02 2 DQ11 w 1 03 O 3 2043 1 03 DQ12 1 0 4 O 4 DQ44 w 1 04 1 0 4 DQ13 A 1 05 O 5 DQ45 w 1 05 1 05 DQ14_ wr 1 06 O 6 DQ46 w 1 0 6 1 0 6 DQ15 w 1 07 O7 DQ47 A 1 07 1 07 DQS2 M DQS6 5052 DQS6 DM2 DQS11 DM6 DQS15 NC DQS11 NC DQS15 DM NU CS 59 CS 005 DOSI DM NU CS 00 DQS DM CS 005 DQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS RDQS 1 1 00 O 0 DQ48 00 1 0 0 DQ17 70 1 D2 O 1 D11 049 I O 1 D6 1 D15 DQ18 w 1 0 2 2 DQ50 w 1 0 2 2 009019 1 0 3 DQ51 w 1 0 3 1 0 4 0 4 DQ52 4 1 0 4 1 0 4 DQ21 4 1 05 O 5 DQ53 w 5 1 05 DQ22 4 1 06 O 6 DQ54 A 0 6 1 0 6 DQ23_ 1 07 0 7 55 7 1 07 DQS3 NAE e DQS7 VM DQS3
30. R2 SDRAMs D0 D17 CAS RCAS gt CAS DDR2 SDRAMs 00 047 The resistors on Par In A13 A14 A15 BA2 and the WE WW S RWE WE DDR2 SDRAMs 00 017 signal line of Err Out refer to the section Register CKEO w 4 RCKEO DDR2 SDRAMs 00 08 Options for Unused Address inputs CKE1 Ws E RCKE1 gt CKE DDR2 SDRAMs D9 D17 ODTO WH R gt DDR2 SDRAMs 00 08 ODT1 RODT1 gt ODT1 DDR2 SDRAMs 09 017 CKO PCKO PCK6 PCK8 PCK9 gt DDR2 SDRAMs 00 017 NEN P RESET RST L PCK7 CKO L PCKO PCK6 PCK8 gt DDR2 SDRAMs 00 017 reser POG Z Fens S0 connects to DCS and S1 connects to CSR on a Register S1 connects to DCS and 50 connects to CSR on another Register Note 1 DQ to I O wiring may be changed per nibble RESET PCK7 and PCK7 connects to both Registers 2 Unless otherwise noted resister values are 22 Ohms 5 Other signals connect to one of two Registers 3 RSO and RS1 alternate between the back and front sides of the DIMM 8 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM 7 3 1GB 128Mx72 Module M393T2950GZ3 M393T2950GZA populated as 1 rank of x DDR2 SDRAMs
31. RDIMM DDR2 SDRAM DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb G die 72 bit ECC 60FBGA with Lead Free and Halogen Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUBJECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHER WISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL OGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Samsung Electronics reserves the right to change products or specification without notice Rev 1 0 July 2008 1 of 26 ELECTRONICS RDIMM DDR2 SDRAM Table of Contents 1 0 DDR2 Registered DIMM Ordering Information 4 2 0 UI OS 4 3 0 Address Configuration
32. ding cap 11 4 M393T2953GZ3 M393T2953GZA 1GB 64Mx8 18 Module considering Register and PLL current value 0 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 1815 1625 1480 1335 mA IDD1 1985 1830 1630 1520 mA IDD2P 784 724 664 604 mA IDD2Q 1340 1250 1070 980 mA IDD2N 1290 1220 1060 990 mA IDD3P F 1270 1170 1070 970 mA IDD3P S 946 846 746 646 mA IDD3N 1460 1345 1185 1115 mA IDD4w 2000 1820 1550 1415 mA IDD4R 2410 2210 1830 1630 mA IDD5B 2180 1985 1790 1595 mA IDD6 144 144 144 144 mA IDD7 3280 2805 2600 2440 mA 1006 DRAM current standby current of PLL and Register Module IDD was calculated on the basis of component IDD and can be differently measured according to loading cap ELECTRONICS 15 of 26 Rev 1 0 July 2008 RDIMM 11 5 M393T2950GZ3 M393T2950GZA 1GB 128Mx4 18 Module DDR2 SDRAM 0 1 9V Symbol F7 800 CL 6 E6 667 CL 5 D5 533 CL 4 CC 400 CL 3 Units Notes IDDO 1440 1350 1350 1350 mA IDD1 1620 1530 1530 1530 mA IDD2P 144 144 144 144 mA IDD2Q 630 630 540 540 mA IDD2N 720 720 630 630 mA IDD3P F 540 540 540 540 mA IDD3P S 216 216 216 216 mA IDD3N 990 990 900 900 mA IDDAW 2070 1800 1350 1350 mA 12048 2250 1980 1530 1530 IDD5B 2070 1980 1890 1890 mA IDD6 144 144 144 144 mA IDD7 3780
33. g edge to CK setup time tDSS 0 2 x 0 2 x tCK DQS falling edge hold time from CK tDSH 0 2 x 0 2 x tCK Mode register set command cycle time tMRD 2 x 2 x tCK MRS command to ODT update delay tMOD 0 12 0 12 ns Write postamble tWPST 0 4 0 6 0 4 0 6 tCK 10 Write preamble tWPRE 0 35 x 0 35 x tCK Address and control input hold time tlH base 375 x 475 x ps 5 7 9 23 Address and control input setup time tlS base 250 x 350 x ps 5 7 9 22 Read preamble tRPRE 0 9 0 9 1 1 tCK 19 Read postamble tRPST 0 4 0 6 0 4 0 6 tCK 19 Active to active command period for 1KB page size products tRHRD 7 5 x 7 5 x ns 4 Active to active command period for 2KB page size products tRRD 10 x 10 x ns 4 me Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM DDR2 533 DDR2 400 Parameter Symbol Units Notes min max min max Four Activate Window for 1KB page size products tFAW 37 5 x 37 5 x ns Four Activate Window for 2KB page size products tFAW 50 x 50 x ns CAS to CAS command delay tCCD 2 x 2 x tCK Write recovery time tWR 15 x 15 x ns Auto precharge write recovery precharge time tDAL WR RP x x tCK 14 Internal write to read command delay tWTR 7 5 x 10 x ns 24 Internal read to precharge command delay 7 5 x 7 5 x ns 3 Exit self refresh to a non read command tXSNR tRFC 10 x tRFC 10 x ns Exit self refresh to a read command tXSRD 200 x 200 x tCK Exit prechar
34. g parameters by speed grade DDR2 800 and DDR2 667 Refer to notes for informations related to this table at the component datasheet DDR2 SDRAM DDR2 800 DDR2 667 Parameter Symbol Units Notes min max min max DQ output access time from CK CK tAC 400 400 450 450 ps 40 DQS output access time from CK CK DQSCK 350 350 400 400 ps 40 Average clock HIGH pulse width CH avg 0 48 0 52 0 48 0 52 tCK avg 35 36 Average clock LOW pulse width CL avg 0 48 0 52 0 48 0 52 tCK avg 35 36 CK half pulse period HP 37 Average clock period CK avg 2500 8000 3000 8000 ps 35 36 DQ and DM input hold time DH base 125 x 175 x ps 6 7 8 21 28 31 DQ and DM input setup time DS base 50 x 100 x ps 6 7 8 20 28 31 Control amp Address input pulse width for each input IPW 0 6 x 0 6 x tCK avg DQ and DM input pulse width for each input DIPW 0 35 x 0 35 x tCK avg Data out high impedance time from CK CK HZ x tAC max x tAC max ps 18 40 DQS DQS low impedance time from CK CK LZ DQS tAC min tAC max tAC min tAC max ps 18 40 DQ low impedance time from CK CK LZ DQ 2 tAC min tAC max 2 tAC min tAC max ps 18 40 DQS DQ skew for DQS and associated DQ signals DQSQ x 200 x 240 ps 13 DQ hold skew factor QHS x 300 x 340 ps 38 DQ DQS output hold time from 005 tHP tQHS x tHP tQHS x ps 39 00 latching rising trans
35. ge power down to any non read command 2 x 2 x tCK Exit active power down to read command tXARD 2 x 2 x tCK 1 ae 2 readicommang tXARDS 6 AL x 6 AL x tCK 12 CKE minimum pulse width HIGH and LOW pulse width tCKE 3 x 3 x tCK 27 ODT turn on delay tAOND 2 2 2 2 tCK 16 ODT turn on tAON tAC min 1 tAC min tAC max 1 ns 16 ODT turn on Power Down mode tAONPD tAC min 2 ns ODT turn off delay tAOFD 2 5 2 5 2 5 2 5 tCK 17 44 ODT turn off tAOF tAC min tAC min REA ns 17 44 ODT turn off Power Down mode tAOFPD tAC min 2 Kena tAC min 2 121 ns ODT to power down entry latency tANPD 3 x 3 x tCK ODT power down exit latency tAXPD 8 x 8 x tCK OCD drive mode output delay tOIT 0 12 0 12 ns 32 clocks remains ON after CKE asynchronously tDelay tISHtCK tlH x tISHtCK tlH x ns 15 T Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 14 0 Physical Dimensions 14 1 64Mbx8 based 64Mx72 Module 1 Rank M393T6553GZ3 M393T6553GZA Units Millimeters 2 70 133 35 gt 1 30100 NUN Register PLL 1 0 max gt
36. ial pair of system clock inputs that drives input to the on DIMM PLL CKO Input Negative line of the differential pair of system clock inputs that drives the input to the on DIMM PLL 1 Input Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated SDRAM command decoder when low and disables decoder when high When decoder is disabled new commands are ignored but previous operations continue sem Input These input signals also disable all outputs except CKE and ODT of the register s on the DIMM when both inputs are high ODTO ODT1 Input bus impedance control signals RAS CAS WE Input When sampled at the positive rising edge of the clock CAS RAS and WE define the operation to be executed by the SDRAM VREF Supply Reference voltage for SSTL_18 inputs Supply Isolated power supply the DDR SDRAM output buffers to provide improved noise immunity BAO BA1 Input Selects which SDRAM bank of four is activated During a Bank Activate command cycle Address defines the row address During a Read or Write command cycle Address defines the column address In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected PAPIAS Input and
37. idle tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING mA Data bus inputs are SWITCHING Active power down current Fast Exit MRS 12 mA IDD3P banks open tCK IDD is LOW Other control and address bus _ inputs are STABLE Data bus inputs are FLOATING Slow PDN Exit MRS 12 1mA mA Active standby current __ IDD3N All banks open tCK IDD tRAS tRASmax IDD tRP IDD CKE is HIGH CS is HIGH between valid mA commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating burst write current All banks open Continuous burst writes BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP IDDAW s tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus mA inputs are SWITCHING Operating burst read current IDD4R All banks open Continuous burst reads IOUT BL 4 CL CL IDD AL 0 tCK IDD tRAS tRAS d max IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCH ING Data pattern is same as IDDAW Burst auto refresh current IDD5B tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands mA Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Self refresh current Normal mA IDD6 CK and
38. ine as shown and not from line to ground 3 Only one PLL output is shown per output type Any additional PLL outputs will be wired in a similar manner 4 Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible 26 of 26 Rev 1 0 July 2008 ELECTRONICS
39. itions to associated clock edges DQSS 0 25 0 25 0 25 0 25 tCK avg 30 DQS input HIGH pulse width DQSH 0 35 x 0 35 x tCK avg DQS input LOW pulse width DQSL 0 35 0 35 tCK avg DQS falling edge to CK setup time DSS 0 2 x 0 2 x tCK avg 30 005 falling edge hold time from CK DSH 0 2 x 0 2 x tCK avg 30 Mode register set command cycle time MRD 2 x 2 x nCK MRS command to ODT update delay MOD 0 12 0 12 ns 32 Write postamble WPST 0 4 0 6 0 4 0 6 tCK avg 10 Write preamble WPRE 0 35 x 0 35 x tCK avg Address and control input hold time IH base 250 x 275 x ps 5 7 9 23 29 Address and control input setup time IS base 175 x 200 x ps 5 7 9 22 29 Read preamble RPRE 0 9 1 1 0 9 1 1 tCK avg 19 41 Read postamble RPST 0 4 0 6 0 4 0 6 tCK avg 19 42 Activate to activate command period for 1KB page size products tRRD 7 5 x 7 5 x ns 4 32 Activate to activate command period 2KB page size products tRRD 10 x 10 x ns 4 32 m Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM DDR2 800 DDR2 667 Parameter Symbol Units Notes min max min max Four Activate Window for 1KB page size products FAW 35 x 37 5 x ns 32 Four Activate Window for 2KB page size products FAW 45 x 50 x ns 32 CAS to CAS command delay CCD 2 x 2 x nCK Write recovery time WR 15 x 15 x ns 32 Auto precharge write recovery precharge time DAL WR tnRP x WR tnRP x nCK 33 I
40. k 11 23 14 2 64Mbx8 128Mbx4 based 128Mx72 Module 2 1 Ranks 24 14 3 128Mbx4 based 256Mx72 Module 2 Ranks 25 15 0 240 Pin DDR2 Registered DIMM Clock Topology 26 2 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM Revision History Revision Month Year History 1 0 July 2008 Initial Release ELECTRONICS 3 of 26 Rev 1 0 July 2008 RDIMM 1 0 DDR2 Registered DIMM Ordering Information DDR2 SDRAM Part Number Density Organization Component Composition Number of Rank Parity Register Height M393T6553GZ3 CD5 CC 512MB 64Mx72 64Mx8 K4T51083QG 9EA 1 X 30 00mm M393T6553GZA CF7 E6 512MB 64Mx72 64Mx8 K4T51083QG 9EA 1 30 00mm M393T2953GZ3 CD5 CC 1GB 128Mx72 64Mx8 K4T51083QG 18EA 2 X 30 00mm M393T2953GZA CF7 E6 1GB 128Mx72 64Mx8 K4T51083QG 18EA 2 30 00mm M393T2950GZ3 CD5 CC 1GB 128Mx72 128Mx4 K4T51043QG 18EA 1 X 30 00mm M393T2950GZA CF7 E6 1GB 128Mx72 128Mx4 K4T51043QG 18EA 1 30 00mm M393T5750GZ3 CD5 CC 2GB 256Mx72 128Mx4 K4T51043QG 36EA 2 X 30 00mm M393T5750GZA CF7 E6 2GB 256Mx72 128Mx4 K4T51043QG 36EA 2 30 00mm Note 1 7 of Part number 11th digit stands for Lead Free and RoHS compliant products 2
41. n normal memory modules DIMMs 3 NC Err_Out Pin 55 and NC Par Pin 68 are for optional function to check address and command parity 4 1 51 Pin is used for double side Registered DIMM 5 0 Pin Description Pin Name Description Pin Name Description CKO Clock Inputs positive line ODTO ODT1 On die termination CKO Clock inputs negative line DQ0 DQ63 Data Input Output CKEO CKE1 Clock Enables CBO CB7 Data check bits Input Output RAS Row Address Strobe DQS0 DQS8 Data strobes CAS Column Address Strobe DQS0 DQS8 Data strobes negative line WE Write Enable DM 0 8 DQS 9 17 Data Masks Data strobes Read 50 51 Chip Selects DQS9 DQS17 Data strobes Read negative line A0 A9 A11 A13 Address Inputs RFU Reserved for Future Use A10 AP Address Input Autoprecharge NC No Connect Memory bus test tool BAO BA1 DDR2 SDRAM Bank Address TEST Not Connect and Not Useable on DIMMs SCL Serial Presence Detect SPD Clock Input Vpp Core Power SDA SPD Data Input Output VDDQ Power SA0 SA2 SPD address Vss Ground Par In Parity bit for the Address and Control bus VREF Input Output Reference Err_Out Parity error found in the Address and Control bus Vppspp SPD Power RESET Register and PLL control pin The Vpp and pins are tied to the single power plane on PCB 5 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 6 0 Input Output Functional Description Symbol Type Function CKO Input Positive line of the different
42. nternal write to read command delay WTR 7 5 x 7 5 x ns 24 32 Internal read to precharge command delay RTP 7 5 7 5 ns 3 32 Exit self refresh to a non read command XSNR tRFC 10 x tRFC 10 x ns 32 Exit self refresh to a read command XSRD 200 x 200 x nCK Exit precharge power down to any command XP 2 x 2 x nCK Exit active power down to read command XARD 2 x 2 x nCK 1 ds 1 XARDS 8 AL x 7 AL x nCK 12 CKE minimum pulse width HIGH and LOW pulse width CKE 3 x 3 x nCK 27 ODT turn on delay tAOND 2 2 2 2 nCK 16 ODT turn on tAON tAC min tAC max 0 7 tAC min tAC max 0 7 ns 6 16 40 ODT turn on Power Down mode AONPD tAC min 2 ens tAC min 2 ns ODT turn off delay AOFD 2 5 2 5 2 5 2 5 17 45 ODT turn off tAOF tAC min tAC max 0 6 tAC min tAC max 0 6 ns 17 43 45 ODT turn off Power Down mode AOFPD tAC min 2 tAC min 2 poc ns ODT to power down entry latency ANPD 3 x 3 x nCK ODT power down exit latency AXPD 8 x 8 x nCK OCD drive mode output delay OIT 0 12 0 12 ns 32 clocks remains ON after CKE asynchronously tDelay x x ns 15 T Rev 1 0 July 2008 ELECTRONICS RDIMM DDR2 SDRAM 13 4 Timing parameters by speed grade DDR2 533 and DDR2 400 Refer to notes for informations related to this table at the component datasheet DDR2 533 DDR2 400 Parameter Symbol Units
43. orts from 1 7 Volt to 3 6 VppsPD Supply Volt operation The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL When low all register outputs RESET Input will be driven low and the PLL clocks to the DRAMs and register s will be set to low level The PLL will remain synchro nized with the input clock Par In Input Parity bit for the Address and Control bus 414 0 Even Err Out Input Parity error found in the Address and Control bus TEST In Out Used by memory bus analysis tools unused on memory DIMMs 6 of 26 Rev 1 0 July 2008 ELECTRONICS RDIMM 7 0 Functional Block Diagram 7 1 512MB 64Mx72 Module M393T6553GZ3 M393T6553GZA populated as 1 rank of x8 DDR2 SDRAMs DDR2 SDRAM RSO DQSO WS DQS4 DQSO 0954 DMO DQS9 wv DM4 DQS13 A 4 NC DQS9 NC DQS13 WS DM NU CS DOSI DM NU CS 005 RDQS RDQS RDQS RDQS DQ0 w 1 00 DQ32 w _ 1 0 0 DQ1 w 1 01 DO DQ33 w 1 0 1 D4 DQ2 w 0 2 DQ34 w 1
44. w 2 2 SA1 SA2 DQ59 w I O 3 O 3 2963 1 0 3 V Seri DDSPD erial PD DQS8 DM8 DQS17 J 0058 NC DQS17 t 00 035 DM CS DAs DM CS 09 Das DM CS DOS DM CS Das DAs L wY 1 00 00 CB4 w 1 00 O 0 V 00 035 w4 1 01 D8 1 1 D26 CB5 w I O 1 D17 O 1 D35 REF D CB2 w 1 02 02 CB6 1 02 2 T w 1 03 CB7 w 1 03 O 3 Vss 00 035 50 we RSO gt CS DDR2 SDRAMs DO D17 S1 wH 12 RS1 CS DDR2 SDRAMs D18 D35 Signals for Address and Command Parity Function M393T5750GZA w RBAO RBAl gt DDR2 SDRAMs 00 035 0 13 wA RAO RA13 gt A0 A13 DDR2 SDRAMs 00 035 Register A Register B RAS w G RRAS gt RAS DDR2 SDRAMs D0 D35 E a 3 CAS We 1 RCAS gt CAS DDR2 SDRAMs 00 035 bb DD PPO WE ws RWE gt WE DDR2 SDRAMs D0 D35 PAR_IN PAR_IN PPO PAR_IN CKEO w T RCKEO gt DDR2 SDRAMs 00 017 400K ohms GERR QERR Err Out CKE1 E RCKE1 gt CKE DDR2 SDRAMs 018 035 ODTO wR gt DDR2 SDRAMs 00 017 The resistors on Par_In A13 A14 A15 BA2 and the ODT1 RODT1 gt ODT1 DDR2 SDRAMs 018 035 TA DANCER signal line of Err_Out refer to the section Register RESET RST 7 Options for Unused Address inputs PCK7 EN _ CKO PCKO PCK6 PCK8
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