ADATA 3GB DDR3 PC3-16000 TC Kit
Contents
1. ves is 15 25 Dos s Dos se poe 16 vss ie voo ar pov ves vo as ar ves s se as o ves 198 pos 18 as poo se poe 139 vss i voo e pos too Doo 220 vss 21 poe 6 a im ves 221 om por e vss 12 voo 22 wo ves 63 ckinc 1 pose 1 183 voo 22 vss 24 masz 64 icxino 104 ves se 24 pow 25 Dose es von 105 paso 145 vss 185 25 pos vss tos Dos 146 poo 186 voo 26 vss _27 Dom 67 107 ves 147 ser NC EVENT 227 0060 Dor No tos pase 8 vss 188 ao 28 pos 20 ves pasz 149 19 voo ze vss 30 Dom w no ves 150 190 20 DW pos 7 bw m mosz isi vss se vo ar s 72 152 om se mas 232 vss _ mass 78 na vss iss 93 so zo poo cas n4 154 vss 19 voo 254 Doo ves 75 ns pos 155 pos 195 255 vss _ does 76 ne vs2. SDA 1 For each DRAM a unique ZQ resistor is connected to A1 A2 ground The 20 resistor is 240 Ohm 196 SA1 SA2 EL67I1A08 DDR3 2000X CL 29 IGB 128Mx8 Pb free Rev 0 2009 01 16 Page 5 of 7 PONTA Absolute Maximum Ratings Voltage on VDD supply relative to Vss 0 4 2 15 Voltage on VDDQ pin relative to Vss VDDQ 0 4 2 15 Voltage on any relative to Vss VIN Vout 0 4 2 15 Storage temperature TStg 55 4100 Note DDR3 SDRAM component specification Operation Temperature Condition sma ve m mae Extended Temperature Range Optional 485 7495 Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 5V 0 075V Tc 0 to 85 Wee 1 v Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 The AC peak noise on VREF may not allow VREF to deviate from VREF DC by more than 1 VDD for reference approx 15mV 4 For reference approx VDD 2 15 EL6711A08_DDR3 2000X CL 9 _1GB 128Mx8_Pb free Rev 0 2009 01 16 Page 6 of 7 Package Dimensions uo ui Wiz us 1 48 48 240 169 168 133 35 250 00 Hole El 30 0041181 107 Paena S 5175 203
3. 74X 2 0 47 0061850 39 5 1 5 lt 203 7 42 2 gt 4 7 0001850 392 R1 00 39 3 X28 X f e o Od 4 Oo ATO In 9 00 ON CU 0 89 0 05 3150 1 97 Detail 3 800149 61 EL6711A08_DDR3 2000X CL 9 _1GB 128Mx8_Pb free 128 957 076 77 PE 10 82 68 4X Note 12 006472 44 us U6 ur 121 ag gt CU c Pies oog aj lt diis y 0 aJ 3 00 0 10 118 11 3 94 4X 9 530 374 02 2X 1 Tolerance 0 15mm 5 91mils Detail Rev 0 59 06 3 94 gt PT 00000 5 00 196 85 gt 1 50 0 10 r R DAT A Wondertul 0 50019 69 min 1 27 0 10 50 00 3 94 AS gt lt eu CO N i 0 20MMCMa x2 0 05MM CMin 0 2 0MMCMao x 0 05MMCMin 2009 01 16 UP TIONAL Page 7 of 7
4. S VREFDQ VREFCA V ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device EL67I1A08 DDR3 2000X CL 29 IGB 128Mx8 Pb free 0 2009 01 16 Page 4 of 7 e DATA Block Diagram 50 0050 0054 DASO an DQS4 DMO a DM4 CS 005 DOSE 000 0032 DQ 001 0033 002 0034 DQ DQ3 DQ35 DA 004 0036 DQ 005 0037 DQ DQ6 DQ38 DQ DQ7 DQ39 DQ 10 0051 Vss 00 5 Vss 0051 0055 DM1 DM5 008 NI CS DAS 005 DQ9 0041 DQ 0010 0042 DQ DQ11 0043 DQ 0012 0044 DQ DQ13 0045 DQ 0014 0046 DQ DQ15 0047 DQ 10 00 2 Vss DOSG Vss 0052 0056 dn DM6 DM CS DOS DOS DQ16 0048 0017 0049 DQ 0018 0050 DQ 0019 0051 DQ 0020 0052 po U6 0021 0053 DQ DQ22 DQ54 DQ DQ23 DQ55 DQ Vss V za 0053 Das7 0053 0057 DM7 DQ24 T 005 005 0025 0057 DQ DQ26 0058 DQ 0027 0059 DQ 0028 0060 DQ U7 DQ29 0061 0030 0062 DQ 0031 0063 DQ Vss Vs 10 2 2 SDRAMs U7 SPD A0 A13 AQ0 A13 SDRAMs UO U7 UO U7 RAS RAS SDRAMs U7 T UO 07 CAS _ CAS SDRAMs U0 U7 Ms UO 07 CKE SDRAMs UO U7 TN i UO 07 U7 ODT SDRAMs 0 U7 I PORS SDRAM CK SDRAMs UO U7 CK1 Serial PD SCL Note WP
5. e DATA Memory Module Data Sheet A Wonderful Memory EL6 11A08 DDR3 2000X CL9 240 Pin XMP U DIMM 1GB 128M x 64 bits General Description The ADATA s EL6711A08 is a 128Mx64 bits 1GB 1024MB DDR3 2000 CL9 SDRAM XMP memory module The SPD is programmed to standard latency 1333Mbps timing of 9 9 9 24 at 1 5V The module is composed of eight 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package ona 240pin glass epoxy printed circuit board The EL6711A068 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply Normal VDD VDDQ 1 5V 0 075V e 1 5V SSTL 15 compatible I O XMP Extreme Memory Profile support Timing Reference DDR3 1333 CL9 9 9 24 at 1 5V DDR3 2000 CL9 9 9 24 at 2 05V XMP Profile 1 Burst Length 4 8 Programmable Additive Latency 0 CL 2 or CL 1 clock Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and transition with CK transition Average Refresh Per
6. iod 7 8us at lower then TCASE 85 C 3 9us at 85 lt TCASE s 95 8 bit pre fetch On Die Termination using ODT pin e Internal self calibration Internal self calibration through ZQ RZQ 240 ohm 1 e EEPROM VDDSPD 3 3V Typical PCB Height 30 00mm 1 181 Single sided component Clock Cycle Time tCK DDR3 1333 tCK 1 5ns DDR3 2000 tCK 1 0ns Refresh to Active Refresh Command Time tRFC 110ns Lead free products are RoHS compliant EL67I1A08 DDR3 2000X CL 9 IGB 128Mx8 Pb free 0 2009 01 16 Page 2 of 7 Pin Assignment VREFDQ pase 121 161 DM8 201 DOS Com ew e ww pe x ws 4 cor vss js 104 vss 164 204 NO 5 noose vase 125 165 zs vss 6 maso 4e noces vss 126 18 vss 26 Dos 7 pos 47 vss 107 vss No 207 poo 8 ves 48 No bos 108 168 meser 2081 vss 9 a vss par 169 209 ckeo o poo 180 vss 10 20 bos ves si vo je bow in As zn vss 2 Dos 52 bw o ves 12 poo 12 Aw are oms pis s mo moss vss a zs NO ves vo poss pw 2 ara vss _ mas ss an os
7. s 156 196 2 voosro 57 pom 77 omnc nz sw 157 vss 197 voo zv SM _ vss z ne so 158 198 No as soa 79 ne saz 159 085 vss 29 vss _ vss 160 vss 20 20 vr 67 08 DDR3 2000X CL 9 IGB 128Mx8 Pb free 0 2009 01 16 Page 3 of 7 PONTA Pin Description FUNCTION System Clock Active on the positive and negative edge to sample all inputs CKO CKO Masks system clock to freeze operation from the next clock cycle CKE should be enabled at CKEO Clock Enable least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and S0 Chip Select L U DQM Row Column address are multiplexed on the same pins A0 A13 Address Row Address AO A13 Column Address AO A9 Auto precharge 10 Selects bank to be activated during row address latch time BAO BA2 Banks Select Selects bank for read write during column address latch time Data Data and check bit inputs outputs are multiplexed on the same pins Data Strobe When high termination resistance is enabled for all DQ DQ and DM pins assuming the DQ0 DQ63 DQSO DQS7 Bi directional Data Strobe DQS0 DQS7 DMO DM7 RAS CAS VDD VS
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