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HP Intel Xeon X5560

1. v 8 I5 DID 31125101 00 ITE 9 941911 wi 3937909 M S N 0022 y LR TETTE 1 was J vu 20 nm 8 vo eon 601 ly Esp ayas 3 qr en SLN3KKOD SUL AIK 108815 2 j 11 130 335 3jnj jez 0 N 4 18938 103004800 n N 1 UL Ts 9 4 n E 1 gt _ 19 y3uv QVd 1531 39 3815 j r 5 5 Hd 9 000000 AN 12666 5 va o o 1 uy ri e n lt Kasay d mH 3s 9 H NOI1VMO4NOO 13141 40 1839802 8311144 IHL 100811 63121004 YO 031Y14810 70320008438 035012510 38 LON AVA A 1N31N02 SLI 39N3014N09 035012510 SI 11 NOILYWSOJNI TV11N3014N02 1804809 131NI SNIVLNOD 5NIMYBO STHL 3 2 921910 mal T 2 v 9 E 1 Intel Xeon Processor 5500 Series Datasheet Volume 1 46 e Package Mechanical Specifications n tel 3 1 2 Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out z
2. 47 Package Handling Guidelin S dll ana kan ni a bar kanin raa ny 47 Processor Materials t kasi i is 48 Land Listing by Land Name s ic ds e xin sela kar n hok renta i i a cages i 49 Land Listing by Land Number 2 4 44 2 4 72 esse enn nnns 67 rns 85 Intel Xeon Processor W5580 Thermal Specifications 91 Intel Xeon Processor W5580 Thermal Profile kk kk kk kk kk aaa mmm 92 Intel Xeon Processor 5500 Series Advanced SKU Thermal Specifications 92 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile 94 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile 94 Intel Xeon Processor 5500 Series Standard Basic SKUs Thermal Specifications 95 Intel Xeon Processor 5500 Series Standard Basic SKUs Thermal Profile 96 Intel Xeon Processor 5500 Series Low Power SKU Thermal Specifications 96 Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile 98 Intel Xeon Processor L5518 Thermal 98 Intel Xeon Processor 15518 Thermal Profile kk kk kk kk 100 Intel Xeon Processor L5508 Thermal
3. 100 Intel Xeon Processor 15508 Thermal Profile kaka aaa aaa aaa mmm 102 Summary of Processor specific Commands 108 GetTemp Response Definition 11 2 1 kk kk 112 Intel Xeon Processor 5500 Series Datasheet Volume 1 6 16 PCIConfigRd Response Definition LL kaka kk k kk k mmm nnns 113 6 17 PCIConfigWr Device Function 5 4 114 6 18 PCIConfigWr Response 1 1 2 mmm menn nn nns 115 6 19 Mailbox Command Summary 1 aa ka ak a al 116 6 20 Counter Definition ceste rrr a VARY TERRE ERA da W b da 117 6 21 Machine Check Bank Definitions 1 1 0 0 eene nnn 119 6 22 ACPI T state Duty Cycle 0 kek 120 6 23 MbxSend Response Definition kaka een mene nnn 122 6 24 MbxGet Response 1 1 1 enn nn 123 6 25 Domain ID Definition ccc mene mener nnne nnn 125 6 26 Multi Domain Command Code Reference 125 6 27 Completion Code Pass Fail
4. Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 9 of 35 Sheet 10 of 35 Land Name Butrer Direction Lana Land Name Buffer Direction No Type No Type AM12 VCC PWR AN9 VID 2 MSI D 2 CMOS 0 AM13 VCC PWR 10 VID 4 CSC 1 CMOS O AM14 VSS GND AN11 VSS GND 15 PWR AN12 VCC PWR AM16 VCC PWR AN13 VCC PWR AM17 VSS GND AN14 VSS GND AM18 VCC PWR AN15 VCC PWR AM19 VCC PWR AN16 VCC PWR AM20 VSS GND AN17 VSS GND AM21 VCC PWR AN18 VCC PWR AM22 VSS GND AN19 VCC PWR AM23 VSS GND AN20 VSS GND AM24 VCC PWR AN21 VCC PWR AM25 VCC PWR AN22 VSS GND AM26 VSS GND AN23 VSS GND AM27 VCC PWR AN24 VCC PWR AM28 VCC PWR AN25 VCC PWR AM29 VSS GND AN26 VSS GND PWR AN27 VCC PWR AM31 VCC PWR AN28 VCC PWR AM32 VSS GND AN29 VSS GND AM33 VCC PWR AN30 VCC PWR AM34 VCC PWR AN31 VCC PWR AM35 VSS GND AN32 VSS GND AM36 RSVD AN33 VCC PWR AM37 VSS GND AN34 VCC PWR AM38 RSVD AN35 VSS GND AM39 VSS GND AN36 RSVD AM40 QPIO_DRX_DN 15 QPI AN37 VSS GND AM41 QPIO_DRX_DN 16 QPI AN38 RSVD AM42 QPIO DP 16 QPI AN39 DP 18 AM43 QPIO_DRX_DN 14 QPI 40 DP 15 AN1 QPI1_DRX_DP 13 QPI AN41 VSS GND AN2 QPI1_DRX_DN 12 QPI AN42
5. kk nmm 125 6 28 Device Specific Completion Code CC 126 6 29 Originator Response Guidelines 0 126 6 30 Error Codes and eene 128 6 31 Client Response During Power Up During Data Not Ready 128 6 32 Power Impact of Commands versus C states 130 6 33 Client Response During 51 emen 130 7 1 Power On Configuration Signal 00 131 7 2 Coordination of Thread Power States at the Core 133 7 3 Processor C State Power Specifications 135 7 4 Processor S States Ab Kan 136 8 1 Fan Frequency Specifications For 4 Pin Active Thermal Solution 151 8 2 Fan Specifications For 4 Pin Active Thermal 5 2 151 8 3 Fan Cable Connector Pin Out for 4 Pin Active Thermal 151 Intel Xeon Processor 5500 Series Datasheet Volume 1 7 intel Revision History Document Revision Description Dat Number Number P aue 321321 001 Initial release March 2009 8 Intel Xeon Processor 5500 S
6. R DDR3 Clock Buffer On 21 3L 5 ON Resistance R DDR3 Command Buffer 16 24 5 ON On Resistance R DDR3 Reset Buffer On 25 75 5 Resistance R DDR3 Control Buffer 21 31 5 ON On Resistance R DDR3 Data Buffer On 21 31 Q 5 ON Resistance On Die Termination for 45 55 Q 7 Data ODT pata Signals 90 110 On Die Termination for 60 80 Q ParErr ODT Parity Error bits Intel Xeon Processor 5500 Series Datasheet Volume 1 39 intel Intel Xeon Processors 5500 Series Electrical Specifications Table 2 12 DDR3 Signal Group DC Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Units Notes Input Leakage Current N A N A x 500 mA DDR Resistance 99 100 101 Q 8 DDR COMP1 COMP Resistance 24 65 24 9 25 15 Q 8 DDR COMP2 COMP Resistance 128 7 130 131 3 Q 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 is the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 is the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 and may experience excursions above 5 This is the pull down driver resistance Refer to processor signal integrity models for I V characteristics 6 hRyrr IS the termination on the DIMM and not controlled by the Intel Xeon Processor 5500
7. Table 4 1 Land Listing by Land Name Sheet 11 of 36 Land Name pos 1 Direction DDR1_CS 7 E12 CMOS DDR1 ODT 5 DDR1_DQ 0 AA37 CMOS 1 0 DDR1_DQ 1 AA36 CMOS 1 0 DDR1_DQ 10 P39 CMOS 1 0 DDR1_DQ 11 N39 CMOS 1 0 DDR1_DQ 12 R34 CMOS 1 0 DDR1 001131 R35 CMOS 1 0 DDR1 001141 N37 CMOS 1 0 DDR1 001151 N38 CMOS 1 0 DDR1 DG 16 M35 CMOS 1 0 DDR1_DQ 17 M34 CMOS 1 0 DDR1 DG 18 K35 CMOS 1 0 DDR1 001191 135 5 DDR1_DQ 2 Y35 CMOS 1 0 DDR1_DQ 20 N34 CMOS 1 0 DDR1_DQ 21 M36 CMOS 1 0 DDR1_DQ 22 136 CMOS 1 0 DDR1_DQ 23 H36 CMOS 1 0 DDR1 DG 24 H33 CMOS 1 0 DDR1_DQ 25 L33 CMOS 1 0 DDR1 DG 26 K32 CMOS 1 0 DDR1_DQ 27 132 5 DDR1 001281 134 5 DDR1_DQ 29 H34 CMOS 1 0 DDR1 00131 Y34 CMOS 1 0 DDR1 DG 30 L32 CMOS 1 0 DDR1_DQ 31 K30 CMOS 1 0 DDR1 001321 E9 CMOS 1 0 DDR1 DQI 33 E8 CMOS 1 0 DDR1 001341 E5 CMOS 1 0 DDR1 DQI 35 F5 CMOS 1 0 DDR1 DQI 36 F10 CMOS 1 0 DDR1 001371 G8 CMOS 1 0 DDR1 001381 D6 CMOS 1 0 DDR1 DQI 39 F6 CMOS 1 0 DDR1_DQ 4 AA35 CMOS 1 0 DDR1 DG 40 H8 CMOS 1 0 DDR1_DQ 41 16 5 DDR1 DG 42 G4 CMOS 1 0 DDR1 DQI 43 H4 CMOS 1 0 54 Table 4 1 Land Listing by Land Name Sheet 12 of 36 Land Name po Ta Direction DDR1_DQ 44 G9 CMOS 1 0 DDR1 DQ 45 H9 CMOS 1 0 DDR1 001461 G5 CMOS 1 0 DDR1_DQ 47 15 CMOS 1 0 DDR1_DQ 4
8. 5 vss AH37 GND vss A35 GND vss AH39 GND vss A39 GND vss AH7 GND vss 4 GND VSS 34 GND VSS A41 GND VSS 36 GND vss A6 GND VSS AJ41 GND VSS GND 5 5 GND VSS AA34 GND VSS AK10 GND vss AA38 GND vss AK14 GND Ivss Jano vss AK17 GND vss AA9 GND vss AK20 GND vss AB37 GND VSS AK22 GND vss AB4 GND vss AK23 GND VSS AB40 GND VSS AK26 GND 55 42 GND vss AK29 GND vss AB7 GND vss AK3 GND vss AC2 GND vss AK32 GND vss AC36 GND VSS AK34 GND VSS AC5 GND VSS AK39 GND vss AC7 GND VSS AK43 GND vss 9 GND VSS AK9 GND Ivss vss ALL GND vss AD33 GND vss AL11 GND vss AD37 GND VSS AL14 GND VSS AD41 GND VSS AL17 GND VSS AD43 GND VSS AL2 GND vss AE2 GND vss AL20 GND VSS AE39 GND vss AL22 GND vss AE7 GND vss AL23 GND vss AF35 GND vss AL26 GND vss AF38 GND VSS AL29 GND vss AF41 GND vss AL32 GND vss AF5 GND vss AL35 GND vss AG11 GND VSS AL36 GND vss AG3 GND vss AL37 GND vss AG33 GND vss AL42 GND VSS AG GND 5 AL7 GND 62 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 29 of 36 Sheet 30 of 36 Land Name 4 4 Direction Land Name i pes Direction VSS AM11 GND VSS AP36 GND VSS AM14 GND VSS AP37
9. Vtt VttPwrGd Ssapy lt ___ 7 k Bclk VccPwrGd RESET we TTT CSI pins CSI training idle running uOp execution Reset uCode Boot BIOS PECI Client Status In Reset Data Not Rdy Fully Operational NodeiD X roro 6 3 7 2 Device Discovery The PECI client is available on all processors and positive identification of the PECI revision number be achieved by issuing the GetDIB command Please refer to Section 6 3 2 2 for details on GetDIB response formatting 6 3 7 3 Client Addressing The PECI client assumes a default address of 0x30 If nothing special is done to the processor all PECI clients will boot with this address For DP enabled parts a special ID pin is available to strap each socket to a different node ID The package pin strap is evaluated at the assertion of VCCPWRGOOD as depicted in Figure 6 27 Since ID is active low tying the pin to ground results in a client address of 0x31 and tying it to results in a client address of 0x30 The client address may not be changed after VCCPWRGOOD assertion until the next power cycle on the processor Removal of a processor from its socket or tri stating a processor in a DP configuration will have no impact to the remaining non tri stated PECI client address 6 3 7 4 C States The Intel Xeon processor 5500 series PECI client is fully functional under all core and package C state
10. 137 8 1 1 Available Boxed Thermal Solution Configurations 137 8 1 2 An Intel Combo Boxed Passive Active Combination Heat Sink Solution 137 8 1 3 Intel Boxed Active Heat Sink Solution 4 2222 2 138 8 1 4 Intel Boxed 25 5mm Tall Passive Heat Sink 139 8 2 Mechanical 5 5 aa 140 8 2 1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones 140 8 2 2 Boxed Processor Retention Mechanism and Heat Sink Support URS s cc si k y n Wi GER YR UC RA RD E KEY REGERE REFER ER EAE ER d 149 8 3 Fan Power Supply Combo and Active Solution 1 1 nnn 150 8 3 1 Boxed Processor Cooling 2 151 8 4 Boxed Processor 5 44 1 160 EEE kak nn nn nnn 153 Intel Xeon Processor 5500 Series Datasheet Volume 1 Figures 2 1 Active ODT for a Differential Link akanai aaa kaka aaa 13 2 2 input Device Elysteresis tH RR ia i a as 14 2 3 VCC Static and Transient Tolerance 51 2 3 4 31 2 4 Overshoot Example 2 nee emnes
11. Response Meaning Bad FCS Electrical error or AW FCS failure Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Error causing a response timeout Either due to a rare internal timing condition or a processor RESET condition or processor S1 state Retry is appropriate outside of the RESET or S1 states Mailbox The PECI mailbox Mbx is a generic interface to access a wide variety of internal processor states A Mailbox request consists of sending a 1 byte request type and 4 byte data to the processor followed by a 4 byte read of the response data The following sections describe the Mailbox capabilities as well as the usage semantics for the MbxSend and MbxGet commands which are used to send and receive data Intel Xeon Processor 5500 Series Datasheet Volume 1 115 intel 6 3 2 6 1 Capabilities Table 6 19 Mailbox Command Summary Thermal Specifications Command MbxSend MbxGet Data Data Description Mame dword dword byte Ping 0x00 0x00 0x00 Verify the operability existence of the Mailbox Thermal 0x01 Log bit clear Thermal Read the thermal status register and optionally clear any log bits Status mask Status The thermal status has status and log bits indicating the state of Read Clear Register processor TCC activation external PROCHOT assertion and Critical Tempera
12. kk kk kk kak ka 26 2 5 Absolute Maximum and Minimum 05 meme 26 2 6 Processor DC Specifications usan kanc b ku sar al nan Wan d da Dae CARRY T RENE er REDENEER 28 2 6 1 VCC Overshoot 5 150 31 2 6 2 Die Voltage cicer een arbori pra ba n n ba s 32 3 Package Mechanical Specifications 43 3 1 Package Mechanical Specifications sss nemen memes 43 3 1 1 Package Mechanical 0 kk kak kk ake 44 3 1 2 Processor Component Keep Out 2 47 3 1 3 Package Loading Specifications cece eee eee ee eee aaa 47 3 1 4 Package Handling 1 0 mme 47 3 1 5 Package Insertion 47 3 1 6 Processor Mass 5 1800 48 3 1 7 Processor Materials dec x D A UP DU RYE 48 3 158 Processor Markiligs enemies RE a Akan AA kay nA hu a 48 3 1 9 Processor Land Coordinates yiy la l lak xua kulla dik ba Wa kla kaka wa Hak 48 4 Land NEEDLE 49 4 1 Intel Xeon Processors 5500 Series Pin
13. kk kk kk kk emen nemen nnne 17 Power On Configuration POC 7 0 Decode 22 VTT Voltage Identification emnes 23 cresce 23 Signals With On Die Termination 2 1 25 Processor Absolute Minimum and Maximum 5 27 Voltage and Current 28 VCC Static and Transient 2 1 nemen nn 30 Overshoot 5 eee memes enn 31 VTT Static and Transient Tolerance kaka kk kk kk kk kk 37 DDR3 Signal Group DC Specifications ccc kk enn 39 DC Electrical kk kk kk kk kk kk kk kk kk kak k kk kya aka nnn nnn nnn 40 RESET Signal DC Specifications dayik bam kla ya nina 41 TAP Signal Group DC 5 0 04 2 2 4 404 2 1 0 kaka 41 PWRGOOD Signal Group DC Specifications sss 41 Control Sideband Signal Group DC Specifications 42 Processor Loading 5
14. 0x8000 General Sensor Error GSE Client Management Power up Sequencing client is fully reset during processor RESET assertion This means that transactions on the bus will be completely ignored and the host will read the response from the client as all zeroes After processor RESET Z deassertion the Intel Xeon processor 5500 series PECI client is operational enough to participate in timing negotiations and respond with reasonable data However the client data is not guaranteed to be fully populated until approximately 500 uS after processor RESET is deasserted Until that time data may not be ready for all commands The client responses to each command are as follows PECI Client Response During Power Up During Data Not Ready Command Response Ping Fully functiona GetDIB Fully functiona GetTemp Client responds with a hot reading or 0x0000 PCI ConfigRd Fully functiona PCI ConfigWr Fully functiona MbxSend Fully functiona MbxGet Client responds with Abort FCS if MbxSend has been previously issued In the event that the processor is tri stated using power on configuration controls the PECI client will also be tri stated Processor tri state controls are described in Section 7 Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel Figure 6 27 PECI Power up Timeline
15. C 0 51 8 5 53 3 10 54 8 15 56 3 20 57 9 25 59 4 30 60 9 35 62 4 40 63 9 45 65 4 50 67 0 55 68 5 60 70 0 65 71 5 70 73 0 75 74 5 80 76 0 Table 6 8 Intel Xeon Processor 5500 Series Low Power SKU Thermal Specifications Core Thermal Design Power Minimum TCASE Maximum TCASE Notes Frequency W C C Launch to FMB 60 5 See Figure 6 4 1 2 3 4 5 Table 6 9 Notes 1 These values are specified at Vcc for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified cc Please refer to the loadline specifications in Section 2 6 7 2 Thermal Design Power should be used for processor thermal solution design targets is not the maximum power that the processor dissipate TDP is measured at maximum Tease 3 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon processor 5500 series Low Power SKU may be shipped under multiple VIDs for each frequency 5 or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specificat
16. dissipate is measured at maximum Tease 3 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon Processor L5518 may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor 98 frequency requirements Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications Figure 6 5 I ntel Xeon Processor L5518 Thermal Profile 90 Short term Thermal Profile may only be used for short term excursions to higher ambient temperatures not to exceed 360 80 hours per year 4 Short Term Thermal Profile Tc 0 302 P 66 8 c eo Tcase C Nominal Thermal Profile Tc 0 302 P 51 9 0 5 10 15 20 25 30 35 4 45 50 55 60 Power W Notes 1 2 Intel Xeon Processor L5518 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 11 for discrete points that constitute the thermal profile Implementation of Intel Xeon Processor L5518 nominal and short term thermal profiles should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet this Thermal
17. Figure 8 14 Table 8 3 8 3 1 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it The fan power header identification and location must be documented in the suppliers platform documentation or on the baseboard itself The baseboard fan power header should be positioned within 177 8 mm 7 in from the center of the processor socket PWM Fan Frequency Specifications For 4 Pin Active Thermal Solution Description Min Frequency Nominal Frequency Max Frequency Unit PWM Control Frequency Range 21 000 25 000 28 000 Hz Fan Specifications For 4 Pin Active Thermal Solution Typ Max Max Description Min Steady Steady Startup Unit 12 V 12 volt fan power supply 10 8 12 12 13 2 V IC Fan Current Draw N A 1 25 1 5 2 2 A Pulses fan SENSE SENSE frequency 2 2 2 2 revolution Fan Cable Connector Pin Out For 4 Pin Active Thermal Solution PIN 3 PIN4 PIN 2 PIN 1 je Fan Cable Connector Pin Out for 4 Pin Active Thermal Solution Pin Number Signal Color 1 Ground Black 2 Power 12 V Yellow 3 Sense 2 pulses per revolution Green 4 Control 21 KHz 28 KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will have three cooling solutions available Each configuration will require uniqu
18. QPI1 DTX 0 161 AJ2 QPI DDRO CLK N 2 E18 CLOCK QPI1 DTX DNI7 AJ1 QPI DDRO CLK N 3 E19 CLOCK QPI1 DTX 0 181 AHA QPI DDRO CLK P O 119 CLOCK QPI1 DTX DNI 9 AG2 QPI DDRO CLK P 1 D19 CLOCK GPI1 DTX DP 0 AG8 GPI DDRO CLK P 2 F18 CLOCK QPI1 DTX DP 1 AJ8 QPI DDRO CLK P 3 E20 CLOCK QPI1 DTX DP 10 AF2 QPI DDRO 5 101 G15 CMOS QPI1 DTX DP 11 AE1 GPI DDRO_CS 1 B10 CMOS QPI1 DTX DP 12 AD2 QPI DDRO_CS 2 C13 CMOS QPI1 DTX DP 13 AC3 QPI DDRO_CS 3 B9 CMOS QPI1 DTX DP 14 QPI DDRO 5 141 15 CMOS QPI1 DTX DP 15 ACA QPI DDRO_CS 5 A7 CMOS QPI1 DTX DP 16 AB6 QPI DDRO CS 6 C11 CMOS QPI1 DTX DP 17 AD6 QPI OPTY Intel Xeon Processor 5500 Series Datasheet Volume 1 51 intel Land Listing Table 4 1 Land Listing by Land Name Sheet 7 of 36 Land Name pow Direction DDRO_CS 7 B8 CMOS DDRO ODT 5 DDRO_DQ 0 W41 CMOS 1 0 DDRO_DQ 1 41 CMOS 1 0 DDRO_DQ 10 K42 CMOS 1 0 DDRO_DQ 11 K43 CMOS 1 0 DDRO_DQ 12 P42 CMOS 1 0 DDRO_DQ 13 P41 CMOS 1 0 DDRO 001141 L43 CMOS 1 0 DDRO DQ 15 L42 CMOS 1 0 DDRO_DQ 16 H41 CMOS 1 0 DDRO_DQ 17 H43 CMOS 1 0 DDRO_DQ 18 E42 CMOS 1 0 DDRO 001191 E43 CMOS 1 0 DDRO_DQ 2 R43 CMOS 1 0 DDRO_DQ 20 142 5 DDRO 001211 141
19. 0 1 0 0 0 1 1 0 1 175V 1 195V 0 1 0 0 il 0 1 0 1 150V 1 170V 0 1 0 0 1 1 1 0 1 125V 1 145V 0 1 0 1 0 0 1 0 1 100V 1 120V 0 1 0 1 0 1 1 0 1 075V 1 095V 0 1 0 1 Ji 0 1 0 1 050V 1 070V 0 1 0 1 1 di 1 0 1 025V 1 045V Reserved or Unused Signals All Reserved RSVD signals must remain unconnected Connection of these signals to Vcc Vita Vro or any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 for the land listing and the location of all Reserved signals For reliable operation connect unused inputs or bidirectional signals to an appropriate signal level Unused Intel QuickPath Interconnect input and output pins can be left floating Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground including a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace unless otherwise noted in the appropriate platform design guidelines TAP signals do not include on die termination however they may include resistors on package refer to Section 2 1 6 for details Inputs and utilized outputs mu
20. Thermal Status Read Clear The Thermal Status Read provides information on package level thermal status Data includes The status of TCC activation Bidirectional PROCHOTZ assertion Critical Temperature Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel These status bits are a subset of the bits defined in the IA32 THERM STATUS MSR on the processor and more details on the meaning of these bits may be found in the Intel 64 and 32 Architectures Software Developer s Manual Vol Both status and sticky log bits are managed in this status word All sticky log bits are set upon a rising edge of the associated status bit and the log bits are cleared only by Thermal Status reads or a processor reset A read of the Thermal Status Word always includes a log bit clear mask that allows the host to clear any or all log bits that it is interested in tracking A bit set to ObO in the log bit clear mask will result in clearing the associated log bit If a mask bit is set to ObO and that bit is not a legal mask a failing completion code will be returned A bit set to Ob1 is ignored and results in no change to any sticky log bits For example to clear the TCC Activation Log bit and retain all other log bits the Thermal Status Read should send a mask of OxFFFFFFFD Figure 6 19 Thermal Status Word 1 6543210 Reserved lt Critical Temperature Log Critical Temperature
21. 4 Max 39 1 mm Min 38 9 mm 5 C2 Max 36 6 mm Min 36 4 mm 6 C3 Max 2 3 mm Min 2 2 mm 7 C4 2 3 mm Min 2 2 mm Intel Xeon Processor 5500 Series Datasheet Volume 1 103 n tel Thermal Specifications 6 2 6 2 1 Note 6 2 2 104 Processor Thermal Features Processor Temperature A new feature in the Intel Xeon processor 5500 series is a software readable field in the IA32 TEMPERATURE TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT will be asserted The TCC activation temperature is calibrated on a part by part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register TCC activation temperatures may change based on processor stepping frequency or manufacturing efficiencies There is no specified correlation between DTS temperatures and processor case temperatures therefore it is not possible to use this feature to ensure the processor case temperature meets the Thermal Profile specifications Adaptive Thermal Monitor The Adaptive Thermal Monitor feature provides an enhanced method for controlling the processor temperature when the processor silicon reaches its maximum operating temperature Adaptive Thermal Monitor uses Thermal Control Circuit TCC activation to reduce processor power via a combination of methods The first method Frequency VI
22. 49 4 1 1 Land Listing by Land 49 4 1 2 Land Listing by Land 67 5 Signal Definitions co be ia e EYE Ek daa Lee 85 5l Signal D fihilEIOlis edad a ia tiat a a i a k i a all k 85 6 Thermal Specifications ii i i i i a es TR i 89 6 1 Package Thermal 5 11 aka kaka memes 89 6 1 1 Thermal Specifications ee eet i i a RETE i EE 89 6 1 2 Thermal Metrology 103 6 2 Processor Thermal ee eee sese 104 6 2 1 Processor Temperature 104 6 2 2 Adaptive Thermal 11 104 6 2 3 On Demand 00000 0 1 106 6 2 4 PROCHOT3 Signal cierra tene W danin niasn E ee a 106 6 2 5 THERMIRIP Signal reset erret clesia ai Rd e tex exar IR KR QUE Kd 107 6 3 Platform Environment Control Interface PECI cssssese mne 107 6 3 1 Client Capabilities sese 108 6 3 2 Client Command Suite sal x kan rr rate nina an kara ad k k 109 Intel Xeon Processor 5500 Series Datasheet Volume 1 3 em 3 6 3 3 Mult
23. 78 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 25 of 35 Sheet 26 of 35 Land Name Butrer Direction Lana Land Name Buffer Direction No Type No Type G24 DDR1_MA 9 CMOS 0 H21 DDR2_CLK_P 2 CLOCK 0 G25 DDR2_MA 15 CMOS H22 DDR2 MA 9 CMOS O G26 DDR2 CKE 1 CMOS O H23 DDR2_MA 11 CMOS O G27 VDDQ PWR H24 DDR2 MA 14 CMOS O G28 RSVD H25 VDDQ PWR G29 DDR2 DOS P 8 CMOS 26 DDR1 MA 14 CMOS O G30 DDR2 DQS N 8 CMOS H27 DDR1 BA 2 CMOS G31 DDR2 DQS N 17 CMOS H28 DDR1 CKE 0 CMOS O G32 VSS GND H29 RSVD G33 DDR1 DOS P 8 CMOS H30 55 GND G34 DDR1 DOS 8 CMOS 1 0 H31 DDR2 DQS P 17 CMOS 1 0 G35 DDR1 ECC 7 CMOS H32 DDR2_ECC 0 CMOS 1 0 G36 DDR1_ECC 3 CMOS H33 DDR1 DQ 24 CMOS 1 0 G37 VSS GND H34 DDR1_DQ 29 CMOS G38 DDR2 DQS N 12 CMOS H35 55 GND G39 DDR2 001291 CMOS 6 DDR1 0001231 CMOS 1 0 G40 DDR2_DQ 24 CMOS H37 DDR2_DQ 27 CMOS 1 0 G41 DDRO DOS 21 CMOS 1 0 H38 DDR2 DOS P 12 CMOS 1 0 G42 VSS GND H39 DDR2_DQ 28 CMOS 1 0 G43 DDRO_DQS_N 11 CMOS H40 VSS GND H1 DDRO DQ 41 CMOS H41 DDRO 001161 CMOS 1 0 H2 DDRO DQ 40 CMOS H42 DDRO 005 P 11 CMOS 1 0 H3 DDRO DQ 45 CMOS H43
24. AA7 DDR1_DQ 62 CMOS 1 0 AA8 DDR COMP O Analog AA9 VSS GND AA10 VTTD PWR 11 VTTD PWR AA33 VTTD PWR Intel Xeon Processor 5500 Series Datasheet Volume 1 Table 4 2 Land Listing by Land Number Sheet 2 of 35 Land Name Tv Direction AA34 VSS GND AA35 DDR1 DQI4 CMOS AA36 DDR1 0011 CMOS AA37 DDR1 0001 CMOS 1 0 AA38 VSS GND AA39 VSS GND AA40 DDR1 005 P 9 CMOS 1 0 AA41 DDR1 005 N 9 CMOS 1 0 AB3 QPI1 DTX DN 13 QPI O AB4 VSS GND AB5 DDR CMOS AB6 QPI1 DTX DP 16 QPI O AB7 VSS GND AB8 VTTD PWR AB9 VTTD PWR AB10 VTTD PWR AB11 VITD PWR AB33 VITD PWR AB34 VITD PWR AB35 VITPWRGOOD Asynch AB36 DDR1_DQ 5 CMOS 1 0 AB37 VSS GND AB38 QPIO_DTX_DN 17 QPI O AB39 QPIO DTX DP 17 QPI O AB40 VSS GND AB41 COMPO Analog AB42 VSS GND AB43 QPIO_DTX_DN 13 QPI O AC1 DDR COMP 2 Analog AC2 VSS GND GPI1 DTX DP 13 QPI 4 QPI1 DTX DP 15 QPI AC5 VSS GND AC6 GPI1 DTX DN 16 QPI 7 VSS GND AC8 QPI1_DTX_DP 19 QPI AC9 VSS GND AC10 VTTD PWR AC11 VITD PWR 67 intel T Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 3 of 35 Sheet 4 of 35 pou Land Name 2 Direction p Land Name S Direction ACG33 VTTD ewR AE8 VTTD PWR AC34 VTTD PWR AE9 VTTD
25. BCLK DP AJ35 CMOS BCLK DN AAA CMOS BCLK ITP DP AAS CMOS 0 B3 GTL 1 0 BPM 1 A5 GTL 1 0 BPM 2 C2 GTL 1 0 131 BA GTL 1 0 141 D1 GTL 1 0 BPM 5 C3 GTL 1 0 161 D2 GTL 1 0 171 E2 GTL 1 0 CAT_ERR AC37 GTL 1 0 COMPO AB41 Analog QPIO CLKRX DN AR42 QPI QPIO CLKRX DP AR41 QPI QPIO CLKTX DN AF42 QPI QPIO CLKTX DP AG42 QPI 0 COMP AL43 Analog QPIO DN O AU37 QPI QPIO DRX DN 1 AV38 QPI QPIO DRX DN 10 42 QPIO DRX DN 11 AR43 QPI QPIO DRX DN 12 AR40 QPI QPIO DRX DN 13 AN42 QPI QPIO DRX DN 14 AM43 QPI QPIO DRX DN 15 AM40 QPI Intel Xeon Processor 5500 Series Datasheet Volume 1 Table 4 1 Land Listing by Land Name Sheet 2 of 36 Land Name de Direction QPIO DRX DN 16 AM41 QPI QPIO DRX DN 17 AP40 QPI QPIO DRX DN 18 AP39 QPI QPIO DRX DN 19 AR38 QPI QPIO DN 2 AV37 QPI QPIO DRX DN 3 AY36 QPI QPIO DRX DN 4 BA37 QPI QPIO DRX DN 5 AW38 QPI QPIO DRX DN 6 AY38 QPI QPIO DRX DN 7 AT39 QPI QPIO DRX DN 8 AV40 QPI QPIO DN 9 AU41 QPI QPIO DP 0 AT37 QPI QPIO DRX DP 1 AU38 QPI 0 DRX DP 10 AU42 GPI QPIO DRX DP 11 AT43 QPI QPIO DRX DP 12 AT40 QPI QPIO DRX DP 13 AP42 QPI QPIO DP 14 AN43 QPI GPIO DRX DP 15 AN40 QPI QPIO DRX DP 16 AM42 QPI QPIO DRX DP 17 AP41 QPI QPIO DP 18 A
26. E un 38 WU LIA ENDE 119130 TIS 100 0 4 ONY SIOISNONIO 1 38483181 cure 3937709 soissin 00 2 G 1 03112345 35103310 552080 iso fg 2 460 880 200 1 n 21998 910 1 Ust 31025 sx ERY 101 Ip 1VIOn014 1N3ANDI1V 310815815 1 02 31025 3 a o roz o 26702 2 wu g EM y rore L7 c 127 INVTV3S SHI 1 39004 oia ver 01999 219729 ls sme md n 017 SHI 2 m 2 y 11130 3 5 Per 011935 OANE 2 rel re ee n een lg S z saz 8 1 130 335 2 SUIT 0095 r ja wt rar dn a 1 411 SHI fon od So gu wet ee Tq K SS 8 1 130 335 z 2 EL Y Y 2 8 11 130 335 J mum 338 tj 8 11v130 315 8 1 130 338 Bre NO 1y304809 T31NI 40 1835802 NILLIYM IHL LAOHLIM 63121004 YO 031Y14810 032008438 035012510 38 LON AVA S1N31N02 11 ONY 39N3014N09 NI 035012510 SI 11 NOILYHYOINT VIINJQI4NOO NOI1VHOdHOO 13141 SNIVINOD SNIMYBO SIHL 3 921910 an L 8 45 Intel Xeon Processor 5500 Series Datasheet Volume 1 Package Mechanical Specifications intel
27. Icc A 0 10 9 3 4 7 9 10 110 120 130 140 150 Notes The Vcc min Vcc max loadlines represent static and transient limits Please see Section 2 6 1 for Vcc 1 overshoot specifications 2 Refer to Table 2 9 for Vcc Static and Transient Tolerance 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC SENSE and VSS SENSE lands Please refer to the appropriate platform design guide for further details on regulator and decoupling implementations 4 Processor core current Icc ranges are valid up to Icc of the processor SKU as defined in Table 2 8 Voltage and Current Specifications 2 6 1 Vcc Overshoot Specifications The Intel Xeon Processor 5500 Series can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS SENSE lands Table 2 10 Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vcc overshoot above VID 50 mV 2 4 Tos MAX Time duration of Vcc overshoot above VID 25 us 2 4 Intel Xe
28. VCC PWR AK25 VCC PWR AL22 VSS GND AK26 VSS GND AL23 VSS GND A27 vec ew AL24 PWR AK28 VCC PWR AL25 VCC PWR 29 VSS GND AL26 VSS GND AGO ew AL27 vcc PWR AK31 VCC PWR AL28 VCC PWR AK32 VSS GND AL29 VSS GND AK33 VCC PWR AL30 VCC PWR AK34 VSS GND AL31 VCC PWR AK35 PECI_ID Asynch AL32 VSS GND AK36 RSVD AL33 VCC PWR AK37 QPIO_DTX_DP 2 QPI AL34 VCC PWR AK38 DTX DN 2 QPI AL35 VSS GND AK39 VSS GND AL36 VSS GND 40 QPIO_DTX_DP 5 QPI AL37 VSS GND AK41 QPIO DTX DN 5 QPI AL38 RSVD 2 QPIO_DTX_DPI7 o AL39 RESET Asynch AK43 VSS GND AL40 RSVD AL1 VSS GND AL41 RSVD AL2 VSS GND AL42 VSS GND AL3 RSVD AL43 QPIO_COMP Analog AL4 RSVD AM1 QPI1_DRX_DN 13 QPI ALS RSVD AM2 QPI1_DRX_DP 14 QPI AL6 1 COMP Analog AM3 QPI1_DRX_DN 14 QPI AL7 VSS GND AM4 QPI1_DRX_DP 16 QPI AL8 1 DN 19 QPI 5 VSS GND AL9 VID 1 MSID 1 CMOS AM6 GPI1 DRX DP 18 QPI AL10 VID O MSID O CMOS 7 QPI1_DRX_DN 18 QPI AL11 VSS GND AM8 GPI1 DRX DP 19 QPI AL12 VCC PWR 9 VSS GND AL13 VCC PWR 10 VID 3 CSC 0 CMOS vss Gn AM11 vss GND 70 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel
29. 5 44 4 10 45 3 15 46 2 20 47 1 25 48 0 30 48 9 35 6 49 9 40 50 7 45 51 6 50 52 6 55 53 5 60 54 4 65 55 3 70 56 2 75 57 1 80 58 0 85 58 9 90 59 8 95 60 7 100 61 6 105 62 5 110 63 4 115 64 3 120 65 2 125 66 1 130 67 0 I ntel Xeon Processor 5500 Series Advanced SKU Thermal Specifications Core Thermal Design Minimum Maximum Power TCASE TCASE Notes Frequency W C C Launch to FMB 95 5 See Figure 6 2 Table 6 4 1 2 3 4 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified ICC Please refer to the loadline specifications in Section 2 6 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon processor 5500 series may be shipped under multiple VIDs for each frequency FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Intel Xeon Processor 5500 Series Datasheet V
30. A N and P after a signal name refers to a differential pair Commonly used terms are explained here for clarification 1366 land FC LGA package The Intel Xeon Processor 5500 Series is available in a Flip Chip Land Grid Array FC LGA package consisting of processor mounted on a land grid array substrate with an integrated heat spreader IHS DDR3 Double Data Rate 3 synchronous dynamic random access memory SDRAM is the name of the new DDR memory standard that is being developed as the successor to DDR2 SDRAM Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows the operating system to reduce power consumption when performance is not needed Intel Turbo Boost Technology Intel Turbo Boost Technology is a way to automatically run the processor core faster than the marked frequency if the part is operating under power temperature and current specifications limits of the Thermal Design Power TDP This results in increased performance of both single and multi threaded applications Execute Disable Bit Execute Disable allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the sy
31. CMOS O AY17 VSS GND B16 DDRO BA O0 CMOS O AY18 VCC PWR B17 VDDQ PWR AY19 VCC PWR B18 DDR2_MA_PAR CMOS 20 VSS GND B19 DDRO MA 10 CMOS O AY21 VCC PWR B20 DDRO_MA_PAR CMOS AY22 VSS GND aS B21 DDRO MA 1 CMOS AY23 VSS GND B22 VDDQ PWR AY24 VCC PWR B23 DDRO MA 4 CMOS O AY25 VCC PWR B24 DDRO MA 5 CMOS AY26 VSS GND B25 DDRO MA 8 CMOS O AY27 VCC PWR B26 DDRO_MA 12 CMOS O AY28 VCC PWR B27 VDDQ PWR AY29 VSS GND B28 DDRO_PAR_ERR 1 Asynch Intel Xeon Processor 5500 Series Datasheet Volume 1 75 intel T Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 19 of 35 Sheet 20 of 35 pou Land Name Butfer Direction Land Name ae Direction B29 M15 CMOS o BA36 DRX DP 4 B30 DDRO_CKE 2 CMOS 7 QPIO DRX DN 4 QPI B31 DDRO CKE 3 CMOS e BA38 QPIO DRX DP 6 QPI B32 VDDQ PWR BA39 VSS GND B33 RSVD BA40 RSVD B34 DDRO_ECC 6 CMOS 1 0 C2 BPM 2 GTL 1 0 B35 DDRO DOS N 17 CMOS 1 0 C3 BPM 5 GTL 1 0 B36 DDRO DOS P 17 CMOS 1 0 DDRO DG 33 CMOS 37 55 GND C5 vss GND B38 cmos wo ce DoR Dq3 CMOS mo B39 DDRO DQS PI 3 CMOS 1 0
32. DDR2 DOS P 9 U35 CMOS PECI_ID AK35 Asynch DDR2 ECC O0 H32 CMOS PRDY B41 GTL O DDR2 ECC 1 F33 CMOS PREQ C42 GTL DDR2 ECC 2 E29 CMOS AG35 GTL 1 0 DDR2_ECC 3 E30 CMOS PSI AP7 CMOS 0 DDR2_ECC 4 131 5 RESET AL39 Asynch DDR2 ECC 5 J30 CMOS RSVD A31 DDR2 ECC 6 F31 CMOS RSVD A40 DDR2 ECC 7 F30 CMOS RSVD AF1 DDR2 MA 0 A18 CMOS O RSVD AF4 DDR2 MA 1 K17 CMOS O RSVD 1 DDR2 MA 10 H17 CMOS O RSVD AG4 DDR2 MA 11 H23 CMOS O RSVD AG5 DDR2 MA 12 G23 CMOS O RSVD AK2 DDR2 MA 13 F15 CMOS O RSVD AK7 DDR2 MA 14 H24 CMOS O RSVD AK36 DDR2 MA 15 G25 CMOS O RSVD AL3 DDR2 MA 2 G18 CMOS O RSVD AL38 DDR2 MA 3 120 CMOS O RSVD AL4 DDR2 MA 4 F20 CMOS O RSVD AL40 Intel Xeon Processor 5500 Series Datasheet Volume 1 57 intel T Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 19 of 36 Sheet 20 of 36 Land Name po 1 Direction Land Name po Direction A4Aa RSVD K15 RSVD AL5 RSVD K24 RSVD AM36 RSVD K25 RSVD AM38 RSVD K27 RSVD AN36 RSVD K29 RSVD AN38 RSVD L15 RSVD AR36 RSVD U11 RSVD AR37 RSVD 11 RSVD AT36 SKTOCC AG36 GTL TCK AH10 TAP RSVD 5 AJ9 TAP RSVD AU2 TDO AJ 10 TAP THERMTRIP AG37 GTL RSVD AV2 TMS AG10 TAP RSVD AV35 TRS
33. Figure 6 20 6 3 2 6 8 Figure 6 21 118 I cc TDC Read Icc TDC is the Intel Xeon processor 5500 series TDC current draw specification This data may be used to confirm matching Icc profiles of processors in DP configurations It may also be used during the processor boot sequence to verify processor compatibility with motherboard Icc delivery capabilities This command returns Icc TDC in units of 1 Amp TCONTROL Read TCONTROL is used for fan speed control management The TCONTROL limit may be read over PECI using this Mailbox function Unlike the in band MSR interface this TCONTROL value is already adjusted to be in the native PECI temperature format of a 2 byte 2 s complement number Thermal Data Config Read Write The Thermal Data Configuration register allows the PECI host to control the window over which thermal data is filtered The default window is 256 ms The host may configure this window by writing a Thermal Filtering Constant as a power of two E g sending a value of 9 results in a filtering window of 29 or 512 ms Thermal Data Configuration Register HU 43 0 Reserved Thermal Filter Const Machine Check Read PECI offers read access to processor machine check banks 0 1 6 and 8 Because machine check bank reads must be delivered through the Intel Xeon processor 5500 series Power Control Unit it is possible that a fatal error in that unit will prevent access to other m
34. Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 21 of 35 Sheet 22 of 35 Land Land Name Buffer Direction Land Land Name Butter Direction No Type No Type C36 DDRO 01 CMOS 033 55 GND C37 DDRO ECC 4 CMOS 1 0 D34 DDRO_DQS_P 8 CMOS 1 0 C38 DDRO_DQ 30 CMOS 035 DDRO 005 N 8 CMOS 1 0 C39 DDRO DOS N 12 CMOS 036 1 01 CMOS 1 0 C40 VSS GND D37 DDRO_DQ 27 CMOS 1 0 C41 DDRO_DQ 25 CMOS 038 55 GND C42 PREQ GTL D39 DDRO DQS P 12 CMOS 1 0 C43 VSS GND D40 DDRO_DQ 24 CMOS 1 0 D1 BPM 4 GTL 041 DDRO 001281 CMOS 1 0 D2 BPM 6 GTL 042 DDRO 001291 CMOS 1 0 D3 VSS GND D43 VSS GND D4 DDRO_DQS_N 13 CMOS 1 0 El VSS GND D5 DDRO DQS P 13 CMOS 1 0 E2 BPM 7 GTL 1 0 D6 DDR1_DQ 38 CMOS DDRO DOS P 4 CMOS 1 0 D7 DDR1_DQS_N 4 CMOS 1 0 E4 DDRO DQS NIA CMOS D8 VSS GND E5 DDR1_DQ 34 CMOS 1 0 09 DDR2 5 151 CMOS O E6 VSS GND D10 DDR2 ODT 3 CMOS E7 DDR1 DQS P 4 CMOS 1 0 D11 DDR1_ODT 0 CMOS E8 DDR1 DQ 33 CMOS 1 0 D12 DDR1_CS 0 CMOS O E9 DDR1 DQ 32 CMOS 1 0 D13 VDDQ PWR E10 DDR1_CS 5 CMOS D14 DDR1_ODT 2 CMOS 11 VDDQ PWR D15 DDR2_ODT 2 CMOS 12 DDR1_CS 7 CMOS DDR1 ODT 5 D16 DDR2_CS 2 CMOS O E13 DDR1_CS 3 CMOS O D17 DDR2_RAS CMOS O E14 DDR1_CAS CMOS D18 VDDQ PWR E15 DDR1_CS 2 CMOS D19 DDRO P 1 CLOCK E16 VDDQ PWR D20 1 MA PAR CMOS 17 DDR2_CS 4 CM
35. M30 VSS GND L33 DDR1_DQ 25 CMOS M31 VCC PWR L34 VSS GND M32 VSS GND L35 DDR1 DQS P 2 CMOS 1 0 M33 vcc PWR L36 DDR1_DQS_N 2 CMOS M34 DDR1_DQ 17 CMOS 137 DDR1 005 P 11 CMOS 1 0 M35 DDR1 DQ 16 CMOS 138 DDR2 005 N 11 CMOS M36 DDR1_DQ 21 CMOS 1 0 L39 vss GND M37 vss GND 140 DDR2 0001221 CMOS M38 DDR2_DQS_P 11 CMOS 1 0 L41 DDRO DQS P 1 CMOS 1 0 M39 DDR2_DQ 16 CMOS 1 0 L42 DDRO DQ 15 CMOS 1 0 M40 DDR2_DQ 17 CMOS 143 DDRO 0014 CMOS 1 0 M41 005 1 CMOS 1 0 M1 DDRO DQ 43 CMOS 1 0 zx M42 vss GND M2 VSS GND M43 DDRO DQS N 10 CMOS 1 0 M3 DDRO_DQ 52 CMOS N1 DDRO 001481 CMOS MA DDR1 DQS N 15 CMOS 1 0 N2 DDRO_DQ 49 CMOS 1 0 M5 DDR1_DQS_P 15 CMOS 1 0 N3 DDRO_DQ 53 CMOS 1 0 M6 DDR1 DQ 53 CMOS 1 0 NA DDR2 005 P 15 CMOS 1 0 M7 VSS GND N5 VSS GND M8 DDR2_DQ 47 CMOS 1 0 Intel Xeon Processor 5500 Series Datasheet Volume 1 81 intel T Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 31 of 35 Sheet 32 of 35 Land Land Name Buffer Direction Land Land Name Butfer Direction No Type No Type N6 2 cmos wo R2 DDRO DOS 61 CMOS 1 0 N7 DDR2 001531 CMOS 1 0 R3 DDRO DOS N 6 CMOS 1 0 N8 DDR2_DQ 52 CMOS
36. Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications n tel Description Returns the data maintained in the PCI configuration space at the PCI configuration address sent The Read Length dictates the desired data return size This command supports byte word and dword responses as well as a completion code All command responses are prepended with a completion code that includes additional pass fail status information Refer to Section 6 3 4 2 for details regarding completion codes Figure 6 17 PCI ConfigRd Byte 0 1 2 3 t s Client Address dr u Code 4 5 6 7 8 LSB PCI Configuration Address MSB FCS 8 RL 9 RL 9 10 Completion Note that the 4 byte PCI configuration address defined above is sent in standard PECI ordering with LSB first and MSB last 6 3 2 4 2 Supported Responses The typical client response is a passing FCS a passing Completion Code CC and valid Data Under some conditions the client s response will indicate a failure Table 6 16 PCI ConfigRd Response Definition Response Meaning Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Error causing a response timeout Either due to a rare internal timing condition or a RESET or processor 51 state Retry is appropriate outside of the RESET or 6 3 2 5 PCI ConfigWr Intel Xeon Processor 5500 Series
37. that exceeds the specified maximum temperature which may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the appropriate Thermal Mechanical Design Guide for information on designing a compliant thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines The following sections provide more details on the different TCC mechanisms used by Intel Xeon processor 5500 series Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications 6 2 2 1 Figure 6 8 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel The processor uses Frequency VID control whereby TCC activation causes the processor to adjust its operating frequency via the core ratio multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption Frequency VI D Control This method includes multiple operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor The remaining points consist of both lower oper
38. 0 41 VSS GND 84 Land Listing Intel Xeon Processor 5500 Series Datasheet Volume 1 Signal Definitions 5 Signal Definitions 5 1 Signal Definitions Table 5 1 Signal Definitions Sheet 1 of 4 Name Type Description Notes BCLK DN Differential bus clock input to the processor BCLK DP BCLK ITP DN O Buffered differential bus clock pair to ITP BCLK ITP DP BPM 7 0 1 0 BPM 7 0 are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 7 0 should be connected in a wired OR topology between all packages on a platform CAT_ERR 1 0 Indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors other internal unrecoverable error It is expected that every processor in the system will have this hooked up in a wired OR configuration Since this is an I O pin external agents are allowed to assert this pin which will cause the processor to take a machine check exception On Intel Xeon Processor 5500 Series CAT_ERR is used for signalling the following types of errors Legacy MCERR s CAT_ERR is pulsed for 16 BCLKs Legacy IERR s CAT ERR remains asserted until warm or cold reset COMPO Impedance Compensat
39. 0 Single ended Analog Input DDR VREF DDR_COMP 2 0 DDR3 Data Signals Single ended CMOS Input Output DDR 0 1 2 DQ 63 0 DDR 0 1 2 ECC 7 0 Differential CMOS Input Output DDR 0 1 2 DOS N P 17 0 Single ended Asynchronous Input DDR 0 1 2 _PAR_ERR 2 0 DDR_THERM Platform Environmental Control I nterface Single ended Asynchronous Input Output PECI Processor Sideband Signals Single ended GTL Input Output BPM 7 0 CAT_ERR Single ended Asynchronous Input PECI_ID Single ended Asynchronous GTL Output PRDY THERMTRIP Single ended Asynchronous GTL Input PREQ Single ended Asynchronous GTL Input Output PROCHOT Single ended Asynchronous CMOS Output PSI Single ended CMOS Output VID 7 6 VID 5 3 CSC 2 0 VID 2 0 MSID 2 0 VIT VID 4 2 System Reference Clock Differential Input BCLK DP BCLK_DN Test Access Port TAP Signals Differential CMOS Output BCLK ITP DP BCLK ITP DN Single ended Input TCK TDI TMS TRST Single ended GTL Output TDO PWRGOOD Signals Single ended Asynchronous Input CCPWRGOOD VDDPWRGOOD VTTPWRGOOD RESET Signal Single ended Asynchronous Input RESET Power Other Signals Power Ground Analog Input VccpLL Vss COMPO ISENSE Sense Points Other VCCSENSE VSSSENSE VSS SENSE VTTD VTTD SENSE SKTOCC DBR Intel Xeo
40. 0 0 1 23750 0 0 il il 1 1 0 1 1 23125 0 0 1 il al il 1 0 1 22500 0 0 1 1 1 1 1 1 1 21875 0 0 0 0 0 0 0 1 21250 0 1 0 0 0 0 0 1 1 20625 0 il 0 0 0 0 1 0 1 20000 0 il 0 0 0 0 1 1 1 19375 0 1 0 0 0 1 0 0 1 18750 0 0 0 0 1 0 1 1 18125 0 1 0 0 0 T 1 0 1 17500 0 il 0 0 0 1 1 1 1 16875 18 Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications Table 2 2 Voltage Identification Definition Sheet 3 of 5 Intel Xeon Processor 5500 Series Datasheet Volume 1 VID7 VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc MAX 0 1 0 0 1 0 0 0 1 16250 0 1 0 0 1 0 0 1 1 15625 0 1 0 0 1 0 1 0 1 15000 0 1 0 0 1 0 1 1 1 14375 0 1 0 0 1 1 0 0 1 13750 0 1 0 0 1 1 0 1 1 13125 0 1 0 0 1 1 1 0 1 12500 0 1 0 0 1 1 1 1 1 11875 0 1 0 1 0 0 0 0 1 11250 0 1 0 1 0 0 0 1 1 10625 0 1 0 1 0 0 1 0 1 10000 0 1 0 1 0 0 1 1 1 09375 0 1 0 1 0 1 0 0 1 08750 0 1 0 1 0 1 0 1 1 08125 0 1 0 1 0 1 1 0 1 07500 0 1 0 1 0 1 1 1 1 06875 0 1 0 1 1 0 0 0 1 06250 0 1 0 1 1 0 0 1 1 05625 0 1 0 1 1 0 1 0 1 05000 0 1 0 1 1 0 1 1 1 04375 0 1 0 1 1 1 0 0 1 03750 0 1 0 1 1 1 0 1 1 03125 0 1 0 1 1 1 1 0 1 02500 0 1 0 1 1 1 1 1 1 01875 0 1 1 0 0 0 0 0 1 01250 0 1 1 0 0 0 0 1 1 00625 0 1 1 0 0 0 1 0 1 00000 0 1 1 0 0 0 1 1 0 99375 0 1 1 0 0 1 0 0 0 98
41. 32 2 5 Load Current Versus Time 130W 2 0 4 0 20002 33 2 6 Load Current Versus Time 95W Processor 2 0 0 34 2 7 Load Current Versus Time 80W TDP 2 2 27 2 2 2 35 2 8 Load Current Versus Time 60W Processor 2 0 0 k 36 2 9 Load Current Versus Time 38W Processor 2 kk 37 2 10 VIT Static and Transient Tolerance 39 3 1 Processor Package Assembly Sketch 000 k 43 3 2 Processor Package Drawing Sheet 1 of 2 45 3 3 Processor Package Drawing Sheet 2 of 2 46 3 4 Processor Top Side 5 1 48 6 1 Intel Xeon Processor W5580 Thermal Profile 2 2 2 4 91 6 2 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile 93 6 3 Intel Xeon Processor 5500 Series Standard Basic SKUs Thermal Profile 95 6 4 Intel Xeon Processor 5500 Series Low Power SKU Thermal 97 6 5 Intel Xeon Processor L5518 Thermal Profile 22 k 99 6 6 Intel
42. AE2 VSS GND AF41 VSS GND AE3 QPI1_DTX_DP 14 QPI AF42 QPIO CLKTX DN QPI AE4 QPI1_DTX_DN 14 QPI 0 DTX DP 10 5 GPI1 DTX DN 18 QPI AG1 RSVD AE6 GPI1 CLKTX DN QPI AG2 1 DTX DN 9 QPI AE vss AG3 VSS GND 68 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 5 of 35 Sheet 6 of 35 Land Name Butrer Direction mand Land Name Buffer Direction No Type No Type AG4 RSVD AH43 QPIO DTX DNI 8 QPI O AG5 RSVD AJ1 QPI1_DTX_DN 7 QPI 0 AG6 1 DTX DN 5 QPI AJ2 GPI1 DTX DN 6 GPI AG7 1 DTX DP 5 QPI QPI1_DTX_DP 6 QPI AG8 1 DTX DP O QPI 4 1 DTX DP 4 QPI AG9 VSS GND AJ5 VSS GND AG10 TMS TAP AJ6 QPI1 DTX DN 2 QPI O AG11 VSS GND AJ7 QPI1 DTX DN 1 QPI O AG33 VSS GND AJ8 QPI1 DTX DP 1 QPI O AG34 VITA PWR AJ9 TDI TAP AG35 PROCHOT GTL 1 0 AJ10 TDO TAP O AG36 SKTOCC GTL O AJ11 VCC PWR AG37 THERMTRIP GTL O AJ33 VCC PWR AG38 QPIO DTX DP 0 QPI O AJ34 VSS GND AG39 QPIO_DTX_DN 1 QPI O AJ35 BCLK_DP CMOS 40 QPIO DTX DP 9 QPI O AJ36 VSS GND AG41 QPIO DTX DNI 9 QPI O AJ37 GTLREF Analog AG4
43. CLK N 1 CLOCK 124 DDR2 CMOS K21 VDDQ PWR 125 DDR2 PAR ERRZ 1 Asynch K22 DDR2_MA 6 CMOS 126 DDR2_CKE 0 CMOS K23 DDR2_MA 5 CMOS 127 DDR1 MA 6 CMOS K24 RSVD 128 VDDQ PWR K25 RSVD 129 RSVD K26 VDDQ PWR 130 DDR2 ECC 5 CMOS 1 0 K27 RSVD 131 DDR2_ECC 4 CMOS 1 0 K28 DDR1_MA 4 CMOS 132 DDR1_DQ 27 CMOS 1 0 K29 RSVD 133 VSS GND K30 DDR1_DQ 31 CMOS 1 0 J34 DDR1_DQ 28 CMOS 1 0 K31 VSS GND 135 DDR1 01191 CMOS 1 0 K32 DDR1_DQ 26 CMOS 1 0 136 DDR1 DQI22 CMOS 1 0 DDR1_DQS_N 12 CMOS 1 0 137 DDR2 001261 CMOS 1 0 k34 DDR1_DQS_P 12 CMOS 1 0 138 VSS GND K35 DDR1 DG 18 CMOS 1 0 139 DDR2 DG 19 CMOS 1 0 K36 VSS GND 140 DDR2 001181 CMOS 1 0 K37 DDR1_DQS_N 11 CMOS 1 0 J41 DDRO_DQ 21 CMOS 1 0 K38 DDR2_DQ 23 CMOS 1 0 142 DDRO DG 20 CMOS 1 0 K39 DDR2 DQS NI2 CMOS 1 0 143 VSS GND K40 DDR2_DQS_P 2 CMOS 1 0 VSS GND K41 VSS GND K2 J DDRO_DQS_P 5 CMOS 1 0 K42 DDRO_DQ 10 CMOS 1 0 K3 DDRO DQS 5 CMOS 1 0 K43 DDRO_DQ 11 CMOS 1 0 k4 DDR1_DQ 48 CMOS 1 0 11 DDRO DG 42 CMOS 1 0 K5 DDR1 DG 49 CMOS 1 0 L2 DDRO DG 47 CMOS 1 0 VSS GND 13 DDRO 001461 CMOS 1 0 K7 DDR2 DQS NI 5 CMOS 1 0 L4 vss GND DDR2_DQS_N 14 5 L5 DDR1 005 NI6 CMOS 1 0 k9 DDR2 DOS P 14 CMOS 1 0 16 DDR1 DOS P 6 CMOS 1 0 K10 DDR2_DQ 41 CMOS 1 0 L7 DDR2 DOS P 5 CMOS 1 0 K11 55 GND L8 DDR2 DG 46 CMOS 1 0 K12 D
44. DDRO DQ 17 CMOS 1 0 H4 DDR1 DQ 43 CMOS J1 DDRO DQS N 14 CMOS 1 0 H5 VSS GND J2 DDRO DQS P 14 CMOS 1 0 H6 DDR1 DOS P 5 CMOS J3 VSS GND H7 DDR1 DQS P 14 CMOS DDR1 DQ 52 CMOS 1 0 H8 DDR1 DQ 40 CMOS 15 DDR1 0091471 CMOS 1 0 H9 DDR1 DQ 45 CMOS 16 DDR1 DQ 41 CMOS 1 0 H10 VSS GND J7 DDR1 DQS N 14 CMOS 1 0 H11 DDR2 DQS P 13 CMOS 18 55 GND H12 DDR2 001381 CMOS 19 DDR2 DQS N 4 CMOS 1 0 H13 DDR2_DQ 34 CMOS J10 DDR2 DQS P 4 CMOS 1 0 H14 DDR1 MA 10 CMOS O J11 DDR2 DQS N 13 CMOS 1 0 H15 VDDQ PWR J12 DDR2_DQ 33 CMOS 1 0 H16 DDR2_CS 3 CMOS O J13 VSS GND H17 DDR2 MA 10 CMOS O J14 DDR1 MA 0 CMOS O H18 DDR1_CLK_P 3 CLOCK O J15 DDR2_CS 7 CMOS H19 DDR1_CLK_N 3 CLOCK ER H20 VDDO BWR 16 DDR1 CMOS O J17 DDR1 MA 2 CMOS Intel Xeon Processor 5500 Series Datasheet Volume 1 79 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 27 of 35 Sheet 28 of 35 po Land Name Butter Direction Land Land Name Butfer Direction 118 VDDQ PWR K15 RSVD 119 DDRO 01 CLOCK K16 VDDQ PWR 120 DDR2_MA 3 CMOS K17 DDR2 11 CMOS 121 CLK 0 CLOCK DDR1_CLK_P 2 CLOCK 122 DDR2 CLK 0 CLOCK K19 DDRO CLOCK 123 VDDQ PWR K20 DDR2
45. Intel Xeon Processor 5500 Series Datasheet Volume 1 137 n tel Boxed Processor Specifications 8 1 3 Figure 8 1 Figure 8 2 138 I ntel Boxed Active Heat Sink Solution The Boxed Active solution will be available for purchase for processors with TDP s of 80W and lower and will be an aluminum extrusion This heat sink solution is intended to be used as an active heat sink only for pedestal chassis Figure 8 1 is a representation of the heat sink solution Both active solutions will utilize a fan capable of 4 pin pulse width modulated PWM control Use of a 4 pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the baseboard s ability to directly control the RPM of the processor heat sink fan See Section 8 3 for more details on fan speed control also see Section 6 3 for more on the PWM and PECI interface along with Digital Thermal Sensors DTS Boxed Active Heat Sink Boxed Passive Active Combination Heat Sink With Removable Fan Intel Xeon Processor 5500 Series Datasheet Volume 1 Boxed Processor Specifications n tel Figure 8 3 Boxed Passive Active Combination Heat Sink with Fan Removed Figure 8 4 Intel Boxed 25 5 mm Tall Passive Heat Sink Solution 8 1 4 I ntel Boxed 25 5mm Tall Passive Heat Sink Solution The boxed 25 5 mm Tall heatsink solution will be available fo
46. PWR AC35 VITD PWR AE10 VITA PWR AC36 VSS GND AE11 VITA PWR AC37 CAT_ERR GTL 1 0 AE33 VITA PWR AC38 DTX DN 16 QPI AE34 PWR AC39 QPIO DTX DP 16 QPI AE35 VTTD PWR AC40 QPIO_DTX_DN 15 QPI AE36 VTTD SENSE Analog AC41 QPIO DTX DP 15 QPI 7 VSS SENSE VTTD Analog 42 DTX DN 12 QPI AE38 QPIO DTX DN 18 QPI 0 DTX DP 13 QPI AE39 VSS GND AD1 GPI1 DTX DN 11 GPI AE40 QPIO DTX DP 19 QPI AD2 QPI1_DTX_DP 12 QPI 41 QPIO DTX DN 11 QPI 1 DTX DN 12 GPI AE42 QPIO_DTX_DP 11 QPI AD4 GPI1 DTX DN 15 GPI AE43 QPIO DTX DN 10 QPI AD5 QPI1_DTX_DP 18 QPI 1 RSVD AD6 QPI1_DTX_DP 17 QPI AF2 GPI1 DTX DP 10 QPI AD7 QPI1_DTX_DN 17 QPI AF3 QPI1_DTX_DN 10 QPI AD8 1 DTX DN 19 QPI AF4 RSVD AD9 VTTD PWR AF5 VSS GND AD10 VITA PWR AF6 GPI1 CLKTX DP QPI AD11 vss GND AF7 VIT VID3 CMOS AD33 VSS GND AF8 VTTD PWR AD34 VTTD PWR AF9 VTTD PWR apzss vmro gt T Pm AF10 DBR Asynch AD36 VTTD PWR AF11 VTTA PWR AD37 VSS GND AF33 VTTA PWR AD38 QPIO DTX DP 18 QPI AF34 PWR AD39 QPIO DTX DN 14 QPI 5 VSS GND AD40 QPIO DTX DP 14 QPI AF36 VTTD PWR AD41 vss GND AF37 VTTD AD42 QPIO DTX DP 12 QPI AF38 VSS GND AD43 VSS GND AF39 QPIO_DTX_DP 1 QPI 1 QPI1_DTX_DP 11 QPI AF40 QPIO DTX 0 1191 QPI
47. Series Please refer to the applicable DIMM datasheet 7 The minimum and maximum values for these signals are programmable by BIOS to one of the pairs 8 COMP resistance must be provided the system board with 1 resistors DDR COMP 2 0 resistors to Vss Table 2 13 PECI DC Electrical Limits 40 Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 150 Vttp 0 150 Vuysteresis Hysteresis 0 100 V VN Negative edge threshold voltage 0 275 0 500 Vip V 2 6 Vp Positive edge threshold voltage 0 550 0 725 V 2 6 Rpullup Pullup Resistance N A 50 Q Vou 0 75 lii gak High impedance state leakage to N A 50 A 3 Vrrp Vieak VoU High impedance leakage to N A 25 HA 3 Vieak Vou Bus capacitance per node N A 10 pF 4 5 VNoise Signal noise immunity above 300 MHz 0 100 Vp N A Vp p Note 1 Vp supplies the interface behavior does not affect V rp min max specifications 2 Itis expected that the driver will take into account the variance in the receiver input thresholds and consequently be able to drive its output within safe limits 0 150 V to 0 275 for the low level and 0 725 Vqrp to Vrrp 40 150 for the high level 3 Theleakage specification applies to powered devices on the PECI bus 4 One node is counted for
48. TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon Processor L5508 may be shipped under multiple VIDs for each frequency 5 or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements 102 Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications n tel 6 1 2 Thermal Metrology The minimum and maximum case temperatures are specified in Table 6 6 through Table 6 13 and are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 7 illustrates the location where temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Intel amp Xeon Processor 5500 Series Thermal Mechanical Design Guide Figure 6 7 Case Temperature Measurement Location Measure Tcase geometric center of the top surface of the IHS j Notes Figure is not to scale and is for reference only 2 B1 Max 45 07 mm Min 44 93 mm 3 B2 Max 42 57 mm Min 42 43 mm
49. VCC AP31 PWR VCC AM16 PWR VCC AP33 PWR VCC AM18 PWR VCC AP34 PWR VCC AM19 PWR VCC AR10 PWR VCC AM21 PWR VCC AR12 PWR VCC AM24 PWR VCC AR13 PWR VCC AM25 PWR VCC AR15 PWR VCC AM27 PWR VCC AR16 PWR VCC AM28 PWR VCC AR18 PWR VCC AM30 PWR VCC AR19 PWR VCC AM31 PWR VCC AR21 PWR VCC AM33 PWR VCC AR24 PWR VCC AM34 PWR VCC AR25 PWR VCC AN12 PWR VCC AR27 PWR VCC AN13 PWR VCC AR28 PWR VCC AN15 PWR VCC AR30 PWR VCC AN16 PWR VCC AR31 PWR VCC AN18 PWR VCC AR33 PWR VCC AN19 PWR VCC AR34 PWR VCC AN21 PWR VCC AT10 PWR VCC AN24 PWR VCC AT12 PWR VCC AN25 PWR VCC AT13 PWR VCC AN27 PWR VCC AT15 PWR VCC AN28 PWR VCC AT16 PWR VCC AN30 PWR VCC AT18 PWR VCC AN31 PWR VCC AT19 PWR VCC AN33 PWR VCC AT21 PWR VCC AN34 PWR VCC AT24 PWR VCC AP12 PWR VCC AT25 PWR Intel Xeon Processor 5500 Series Datasheet Volume 1 59 intel T Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 23 of 36 Sheet 24 of 36 Land Name ro 1 Direction Land Name po Ta Direction vcc arz pwr vcc AV9 PWR 28 PWR AW10 PWR PWR AW12 PWR AT31 PWR AW13 PWR PWR AW15 PWR 4 PWR AW16 PWR PWR VCC AW18 PWR VCC AU10 PWR VCC AW19 PWR VCC AU12 PWR VCC AW21 PWR Ive mm AUS PWR vcc AW24 PWR AU15 PWR AW25 PWR AU16 PW
50. VSS B2 GND vss AUS GND vss B37 GND vss AV11 GND vss B42 GND VSS AV14 GND VSS BA11 GND vss AV17 GND VSS BA14 GND AVO GND 1 vss BA17 GND VSS AV22 GND VSS BA20 GND vss AV23 GND vss BA26 GND VSS Jas GND 5 BA29 GND vss AV29 GND vss BA3 GND vss AV32 GND VSS BA35 GND vss AV39 GND vss BA39 GND VSS AV4 GND VSS BA5 GND 55 AV41 GND vss C35 GND vss AW1 GND vss C40 GND vss AW11 GND vss C43 GND vss AW14 GND vss C5 GND VSS AW17 GND VSS D3 GND vss AW20 GND VSS D33 GND vss AW22 GND vss D38 GND vss aw23 GND 1 55 D43 GND vss AW26 GND VSS D8 GND VSS AW29 GND VSS 1 GND VSS AW32 GND VSS E36 GND VSS AW35 GND VSS E41 GND vss AW6 GND vss E6 GND VSS AW8 GND vss F29 GND vss AY11 GND vss F34 GND vss AY14 GND vss F39 GND vss AY17 GND VSS F4 GND vss AY2 GND vss F9 GND vss AY20 GND vss G12 GND vss AY22 GND VSS G2 GND vss AY23 GND vss G32 GND vss AY26 GND vss G37 GND VSS GND vss G42 GND 64 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 33 of 36 Sheet 34 of 36 Land Name poa 7 Direction Land Name n ped Direction VSS G7 GND VSS N40 GND VSS H10 GND VSS N5 GND VSS H30 GND VSS P11 GND VSS H35 GND VSS P3 GND VSS H40 GND VSS P33 GND
51. VSS H5 GND VSS P38 GND VSS 13 GND VSS P43 GND VSS J3 GND VSS P8 GND VSS 133 GND VSS R1 GND VSS 138 GND VSS R36 GND VSS 143 GND VSS R41 GND VSS 18 GND VSS R6 GND VSS K1 GND VSS T34 GND VSS K11 GND VSS T39 GND VSS K31 GND VSS T4 GND VSS K36 GND VSS T9 GND VSS K41 GND VSS U2 GND VSS K6 GND VSS U37 GND VSS L29 GND VSS U42 GND VSS L34 GND VSS U7 GND VSS L39 GND VSS V10 GND VSS LA GND VSS V35 GND VSS L9 GND VSS V40 GND VSS M12 GND VSS V5 GND VSS M14 GND VSS W3 GND VSS M16 GND VSS W38 GND VSS M18 GND VSS W43 GND VSS M2 GND VSS ws GND VSS M20 GND VSS Y1 GND VSS M22 GND VSS Y11 GND VSS M24 GND VSS Y33 GND VSS M26 GND VSS Y36 GND VSS M28 GND VSS Y41 GND VSS M30 GND VSS Y6 GND VSS M32 GND VSS_SENSE AR8 Analog VSS M37 GND VSS_SENSE_VTTD AE37 Analog VSS M42 GND VTT_VID2 AV3 CMOS 0 VSS M7 GND VTT_VID3 AF7 CMOS VSS N10 GND VTT_VID4 AV6 CMOS O VSS N35 GND VTTA AD10 PWR Intel Xeon Processor 5500 Series Datasheet Volume 1 65 intel Table 4 1 Sheet 35 of 36 Land Listing by Land Name Table 4 1 Sheet 36 of 36 Land Listing Land Listing by Land Name Land Buffer Land Buffer Land Name No Type Direction Land Name No Type Direction VTTA AE10 PWR VTTD AC11 PWR VTTA AE11 PWR VTTD AC33 PWR VTTA AE33 PWR VTTD AC34 PWR VTTA AF11 PWR VTTD AC35 PWR VTTA AF33 PWR VTTD AD34 PWR VTTA AF34 PWR VTTD AD35 PWR VTTA AG34 PWR VTTD AD36 PW
52. Xeon Processor L5508 Thermal Profile kaka kaka aaa aaa kaka mnn 101 6 7 Case Temperature TCASE Measurement Location 103 6 8 Frequency and Voltage emen 105 6 05 109 6 10 Ping Example ER REA TAREA AGERE E LERRA T ED dd ad 109 6 11 GetDI BO REREERRRYAEXRERARRXAS a dad TAE 110 6 12 Device Info Field 2 0 27 7 22 2 2 110 6 13 Revision Number 2 2 1 7 7 7 42 2 2 04 4444 ka 110 6 14 Getremp accetti en RR Ebo ere dj dd O pd 111 6 15 GetTemp gt lt 00 eee kk kk kk kk ka kaka k k k kk k k ka ka 111 6 16 PCI Configuration 4 a al meses a a ak ak aa kara a a la ak 112 6 17 6 k na na T n baja do al As yda y n 113 6 18 PGIConfi QWE i i i Ua band RR da W b an A ad RED FIRE 115 6 19 Thermal Status 2 0 0 0 0 0 0 0 0 00 00 kak ka kk kk aka 117 6 20 Thermal Data Configuration 118 6 21 Machine Check Read MbxSend Dat
53. a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltages provided to the processor remains within the specifications listed in Table 2 8 Failure to do so can result in timing violations or reduced lifetime of the processor Processor Vcc Voltage Identification VID Signals The voltage set by the VID signals is the maximum reference voltage regulator VR output to be delivered to the processor Vcc lands VID signals are CMOS push pull outputs Please refer to Table 2 17 for the DC specifications for these and other processor sideband signals Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings The Intel Xeon Processor 5500 Series uses eight voltage identification signals VID 7 0 to support automatic selection of core power supply voltages Table 2 2 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a O refers to a low voltage level If the processor Socket is empty SKTOCC high or the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications intel The Intel Xeon Proc
54. and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 6 Refer to Table 2 9 and corresponding Figure 2 3 The processor should not be subjected to any static Vcc level that exceeds the Vcc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 7 Minimum Vcc and maximum are specified at the maximum processor case temperature TcAsg shown Table 6 1 is specified at the relative Vcc point on the Vcc load line The processor is capable of Intel Xeon Processor 5500 Series Datasheet Volume 1 29 e n tel Intel Xeon Processors 5500 Series Electrical Specifications drawing cc max for up to 10 ms Refer to Figure 2 5 through Figure 2 8 for further details on the average processor current draw over various time durations 8 Refer to Table 2 11 and corresponding Figure 2 10 The processor should not be subjected to any static Vr level that exceeds the V max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 9 This specification represents the Vcc reduction due to each VID transition See Section 2 1 7 3 10 Baseboard bandwidth is limited to 20 MHz 11 FMB is the flexible motherboard guidelines See Section 2 4 for FMB details 12 1CC_TDC Thermal Design Current is
55. any static Vcc and combination wherein Vcc exceeds Vcc max at specified cc Please refer to the loadline specifications in Section 2 6 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon processor 5500 series may be shipped under multiple VI Ds for each frequency 5 or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Table 6 10 I ntel Xeon Processor L5518 Thermal Specifications Core Thermal Design Power Minimum TCASE Maximum TCASE N o otes Frequency W 9C Launch to FMB 60 5 See Figure 6 5 1 2 3 4 5 Table 6 11 Notes 1 These values are specified at Vcc for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified cc Please refer to the loadline specifications in Section 2 6 2 Thermal Design Power should be used for processor thermal solution design targets TDP is not the maximum power that the processor
56. based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon Processor L5508 may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor 100 frequency requirements Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications Figure 6 6 Intel Xeon Processor L5508 Thermal Profile 90 Short term Thermal Profile may only be used for short term d excursions to higher ambient temperatures not to exceed 360 7 80 hours per year M e Short term Thermal Profile Tease 0 532 P 65 Tcase C Nominal Thermal Profile Tease 0 532 P 50 e 40 0 5 10 15 20 25 30 35 Power W Notes 1 2 Intel Xeon Processor L5508 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 13 for discrete points that constitute the thermal profile Implementation of Intel Xeon Processor L5508 nominal and short term thermal profiles should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet this Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss The Nominal
57. common clock signal SKTOCC Socket occupied platform must sense a VSS at this pin to enable POWER_ON TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support THERMTRIP Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Once activated the processor will stop all execution and shut down all PLLs To further protect the processor its core voltage Vcc Vrrp and Vppg must be removed following the assertion of THERMTRIP Once activated THERMTRIP remains latched until RESET is asserted While the assertion of the RESET signal may de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted after RESET is de asserted TMS TMS Test Mode Select is a J TAG specification support signal used by debug tools TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during p
58. each client and one node for the system host Extended trace lengths might appear as additional nodes 5 Excessive capacitive loading on the PECI line may slow down the signal rise fall times and consequently limit the maximum bit rate at which the interface can operate 6 Please refer to Figure 2 2 for further information Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications n tel Table 2 14 RESET Signal DC Specifications Symbol Parameter Min Typ Max Units Notes Input Low Voltage 0 60 V 2 3 Vin Input High Voltage 0 70 Vita V 2 3 5 RoN Processor Sideband Buffer 10 18 Q On Resistance lu Input Leakage Current 200 4 Notes Unless otherwise noted all specifications in this table apply to all processor frequencies The V a referred to in these specifications refers to instantaneous Based on a test load of 50 Q to Vrra For between 0 V and Measured when the driver is tristated Vin experience excursions above Vyr Urbe tor ross Table 2 15 TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VIL Input Low Voltage 0 40 Vita V 2 3 Vin Input High Voltage 0 60 Vita V 2 3 5 VoL Output Low Voltage Vita V 2 6 Ron Rsys TERM Vou Output High Voltage V 2 5 RoN P
59. format is as follows Write Length 1 Read Length 2 Command 0x01 Multi Domain Support Yes see Table 6 26 Description Returns the current temperature for addressed processor PECI client Figure 6 14 GetTemp Byte 0 1 2 3 Write Length Read Length Cmd Code Definition 4 5 6 7 FCS Temp 7 0 Temp 15 8 FCS Example bus transaction for a thermal sensor device located at address 0x30 returning a value of negative 10 C Figure 6 15 GetTemp Example Byte 0 1 2 3 Byte 0x30 0x01 0x02 0x01 Definition 4 5 6 7 Intel Xeon Processor 5500 Series Datasheet Volume 1 111 n tel Thermal Specifications 6 3 2 3 2 Table 6 15 6 3 2 4 Figure 6 16 Supported Responses The typical client response is a passing FCS and good thermal data Under some conditions the client s response will indicate a failure GetTemp Response Definition Response Meaning General Sensor Error GSE Thermal scan did not complete in time Retry is appropriate 0x0000 Processor is running at its maximum temperature or is currently being reset All other data Valid temperature reading reported as a negative offset from the TCC activation temperature PCI ConfigRd The PCI ConfigRd command gives sideband read access to the entire PCI configuration space maintained in the processor This capability does not include support for route through to downstream devices or sibling
60. only a single outstanding Transaction ID is supported Therefore it is recommended that all devices requesting actions or data from the Mailbox complete their requests and release their semaphore in a timely manner In order to accommodate future designs software or hardware utilizing the PECI mailbox must be capable of supporting Transaction IDs between 0 and 15 Releasing the Mailbox The mailbox associated with a particular Transaction ID is only unlocked released upon successful transmission of the last bit of the Read FCS If the originator aborts the transaction prior to transmission of this bit presumably due to an FCS failure the semaphore is maintained and the MbxGet command may be retried Mailbox Timeouts The mailbox is a shared resource that can result in artificial bandwidth conflicts among multiple querying processes that are sharing the same originator interface The interface response time is quick and with rare exception back to back MbxSend and MbxGet commands should result in successful execution of the request and release of the mailbox In order to guarantee timely retrieval of response data and mailbox release the mailbox semaphore has a timeout policy If the PECI bus has a cumulative O time of 1ms since the semaphore was acquired the semaphore is automatically cleared In the event that this timeout occurs the originating agent will receive a failed completion code upon issuing a MbxGet command or ev
61. processors The exact listing of supported devices functions and registers can be found in the Intel Xeon Processor 5500 Series Datasheet Volume 2 PECI originators may conduct a device function register enumeration sweep of this space by issuing reads in the same manner that BIOS would A response of all 1 s indicates that the device function register is unimplemented PCI configuration addresses are constructed as shown in the following diagram Under normal in band procedures the Bus number including any reserved bits would be used to direct a read or write to the proper device Since there is a one to one mapping between any given client address and the bus number any request made with a bad Bus number is ignored and the client will respond with a pass completion code but all 05 in the data The only legal bus number is 0x00 The client will return all 15 in the data response and pass for the completion code for all of the following conditions Unimplemented Device Unimplemented Function Unimplemented Register PCI Configuration Address 31 28 27 20 19 15 14 12 11 0 Reserved Bus Device Function Register PCI configuration reads may be issued in byte word or dword granularities 6 3 2 4 1 Command Format 112 The PCI ConfigRd format is as follows Write Length 5 Read Length 2 byte data 3 word data 5 dword data Command Oxc1 Multi Domain Support Yes see Table 6 26 Intel
62. regulator thermal protection circuitry should not trip for load currents greater than TDC 2 Not 1004 tested Specified by design characterization Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications n tel Figure 2 9 Load Current Versus Time 38W TDP Processor 12 45 40 35 30 Sustained Current A 25 20 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than lc C TDC 2 Not 10096 tested Specified by design characterization Table 2 11 Vy Static and Transient Tolerance Sheet 1 of 2 lr A VrT V Typ V Vrr Min V Notes 2 3 4 0 VIT VID 0 0315 VIT VID 0 0000 VIT VID 0 0315 1 VIT VID 0 0255 VIT VID 0 0060 VIT VID 0 0375 2 VIT VID 0 0195 VIT VID 0 0120 VIT VID 0 0435 3 VIT VID 0 0135 VIT VID 0 0180 VIT VID 0 0495 4 VIT VID 0 0075 VIT VID 0 0240 VIT VID 0 0555 5 VIT VID 0 0015 VIT VID 0 0300 VIT VID 0 0615 6 VIT VID 0 0045 VIT VID 0 0360 VIT VID 0 0675 7 VIT VID 0 0105 VIT VID 0 0420 VIT VID 0 0735 8 VIT VID 0 0165 VIT VID 0 0480 VIT VID 0 0795 9 VIT VID 0 0225 VIT VID 0 0540 VIT VID 0 0855 10 VIT VID 0 0285 VIT VID 0 0600 VIT VID 0 0915 11 VIT VID 0 0
63. screws should be tightened until they will no longer turn easily This should represent approximately 8 inch pounds of torque More than that may damage the retention mechanism components Intel Xeon Processor 5500 Series Datasheet Volume 1 149 n tel Boxed Processor Specifications Figure 8 13 Thermal Solution Installation 8 3 150 M3 SHOULDER SCREW COMPRESSION SPRING RETENTION CUP ILM amp SOCKET MOTHERBOARD BACKPLATE UNIF WITH INSULATOR T r O ILM ATTACH STUDS 6 32 HEAT SINK ATTACH STUDS M3 b TES gt Fan Power Supply and Active Solution The 4 pin PWM controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics This is achieved though more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors Fan RPM is modulated through the use of an ASIC located on the baseboard that sends out a PWM control signal to the 4th pin of the connector labeled as Control This thermal solution requires a constant 12 V supplied to pin 2 of the active thermal solution and does not support variable voltage control or 3 pin PWM control See Table 8 1 through Table 8 3 for details on the 4 pin active heat sink solution connectors Intel Xeon Processor 5500 Series Datasheet Volume 1 Boxed Processor Specifications Table 8 1 Table 8 2
64. specified I cc Please refer to the loadline specifications in Section 2 6 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon Processor L5518 may be shipped under multiple VIDs for each frequency 5 or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Table 6 12 Intel Xeon Processor L5508 Thermal Specifications Core Thermal Design Power Minimum TCASE Maximum TCASE N o otes Frequency W Launch to FMB 38 5 See Figure 6 6 1 2 3 4 5 6 Table 6 13 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified I cc Please refer to the loadline specifications in Section 2 6 2 Thermal Design Power should be used for processor thermal solution design targets TDP is not the maximum power that the processor dissipate TDP is measured at maximum Tease 3 These specifications are
65. that the processor can dissipate TDP is measured at maximum 3 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon processor 5500 series may be shipped under multiple VIDs for each frequency 5 or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Intel Xeon Processor W5580 Thermal Profile Y 0 181 43 5 Temperature C 0 5 10 15 20 25 30 35 4 45 50 55 60 65 70 75 80 85 90 95 100105 110115 120 125 130 Power M Notes 1 Intel Xeon Processor W5580 Thermal Profile is representative of a volumetrically unconstrained platform 2 3 Please refer to Table 6 2 for discrete points that constitute the thermal profile Implementation of Intel Xeon Processor W5580 Thermal Profile should result in virtually no TCC activation Refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 5500 Series Datasheet Volume 1 91 intel Table 6 2 Table 6 3 92 Thermal Specifications Intel Xeon Processor W5580 Thermal Profile Power W C 0 43 5
66. the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals become valid The VID signals are needed to support the processor voltage specification variations The VR must supply the voltage that is requested by the signals or disable itself VI D7 and VI D6 should be tied separately to Vss via 1kOhm resistors during reset this value is latched on the rising edge of VITPWRGOOD MSID 2 0 Market Segment ID or MSID are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying In addition MSID protects the platform by preventing a higher power processor from booting in a platform designed for lower power processors This value is latched from the platform in to the CPU on the rising edge of VTTPWRGOOD during the cold boot power up sequence CSC 2 0 Current Sense Configuration bits are output signals for ISENSE gain setting This value is latched on the rising edge of VTTPWRGOOD SENSE Vss sENSE VIT VTTPWRGOOD sense ahd Vss sense vrr Provide an isolated low impedance connection to the processor power and ground They can used to sense or measure power near the silicon The processor requires this input signal to be a clean indication that the VTT power supply is stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage curr
67. 0 51 m3 hr at 51 1 Pa of flow impedance For processors with a TDP of 130 W it is assumed that a 40 C T is met This requires a superior chassis design to limit the at or below 5 C with an external ambient temperature of 35 C For processors with TDP of 95W it is assumed that 55 C Tj is met Active Heat Sink Solution Pedestal only This active solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting It may be still be necessary to implement some form of chassis air guide or air duct to meet the T temperature of 49 C depending on the pedestal chassis layout Use of this active solution in a 2U rackmount chassis has not been validated It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor thermal solution should not be preheated by other system components Meeting the processor s temperature specification is the responsibility of the system integrator This thermal solution is for use with processor SKUs no higher than 80W 25 5mm Tall Passive Heat Sink Solution Blade 1U 2U Rack 95 W SKU s using the 25 5 mm Tall passive HS are only intended for use in 1U rack configurations Thermal Profile B For use in 2U configurations see Section 8 3 1 2 for details In the Blade 1U and 2U configurations it is assumed that a chassis duct will be implemente
68. 0 0 0 1 1 1 0 1 52500 0 0 0 0 1 1 1 1 1 51875 0 0 0 1 0 0 0 0 1 51250 0 0 0 1 0 0 0 1 1 50625 0 0 0 1 0 0 1 0 1 50000 0 0 0 1 0 0 1 1 1 49375 0 0 0 1 0 1 0 0 1 48750 0 0 0 1 0 1 0 1 1 48125 0 0 0 1 0 1 1 0 1 47500 0 0 0 1 0 1 1 1 1 46875 0 0 0 1 1 0 0 0 1 46250 0 0 0 1 1 0 0 1 1 45625 0 0 0 1 1 0 1 0 1 45000 0 0 0 1 1 0 1 1 1 44375 0 0 0 1 1 1 0 0 1 43750 0 0 0 1 1 1 0 1 1 43125 17 m n tel Intel Xeon Processors 5500 Series Electrical Specifications Table 2 2 Voltage Identification Definition Sheet 2 of 5 VID7 VID6 VID5 VIDA VID3 VID2 VID1 VIDO MAX 0 0 0 1 1 1 1 0 1 42500 0 0 0 1 1 1 1 1 1 41875 0 0 1 0 0 0 0 0 1 41250 0 0 1 0 0 0 0 1 1 40625 0 0 1 0 0 0 1 0 1 40000 0 0 1 0 0 0 1 1 1 39375 0 0 1 0 0 1 0 0 1 38750 0 0 1 0 0 1 0 1 1 38125 0 0 1 0 0 1 1 0 1 37500 0 0 1 0 0 1 1 1 1 36875 0 0 1 0 1 0 0 0 1 36250 0 0 1 0 1 0 0 1 1 35625 0 0 1 0 1 0 1 0 1 35000 0 0 1 0 1 0 1 1 1 34375 0 0 1 0 1 1 0 0 1 33750 0 0 1 0 1 1 0 1 1 33125 0 0 1 0 1 T 1 0 1 32500 0 0 1 0 1 il 1 1 1 31875 0 0 1 1 0 0 0 0 1 31250 0 0 1 1 0 0 0 T 1 30625 0 0 1 1 0 0 1 0 1 30000 0 0 1 1 0 0 1 1 1 29375 0 0 1 il 0 1 0 0 1 28750 0 0 1 1 0 il 0 1 1 28125 0 0 1 1 0 1 1 0 1 27500 0 0 1 il 0 il 1 1 1 26875 0 0 1 1 1 0 0 0 1 26250 0 0 1 1 al 0 0 1 1 25625 0 0 1 1 1 0 1 0 1 25000 0 0 1 1 1 0 1 1 1 24375 0 0 1 1 1 1
69. 0 114 110 VID 0 088 VID 0 103 VID 0 118 115 VID 0 092 VID 0 107 VID 0 122 120 VID 0 096 VID 0 111 VID 0 126 125 VID 0 100 VID 0 115 VID 0 130 130 VID 0 104 VID 0 119 VID 0 134 135 VID 0 108 VID 0 123 VID 0 138 140 VID 0 112 VID 0 127 VID 0 142 145 VID 0 116 VID 0 131 VID 0 146 150 VID 0 120 VID 0 135 VID 0 150 Notes 1 The Vcc Vcc max loadlines represent static and transient limits Please see Section 2 6 1 for Vcc overshoot specifications 30 Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications intel 2 This table is intended to aid in reading discrete points on Figure 2 3 3 loadlines specify voltage limits at the die measured at the SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC SENSE and VSS SENSE lands Please refer to the appropriate platform design guide for further details on regulator and decoupling implementations 4 Processor core current Icc ranges are valid up to Icc max of the processor SKU as defined in Table 2 8 Voltage and Current Specifications 2 Figure 2 3 Vcc Static and Transient Tolerance Loadlines 2 3 4 VID VID VID VID VID VID VID VID 0 000 0 020 0 040 4 0 060 0 080 4 0 100 4 0 120 4 0 140 5 0 160 0 180
70. 000 1 0 0 1 0 0 1 1 0 69375 1 0 0 1 0 1 0 0 0 68750 1 0 0 1 0 1 0 1 0 68125 1 0 0 1 0 1 1 0 0 67500 1 0 0 1 0 1 1 1 0 66875 1 0 0 1 1 0 0 0 0 66250 1 0 0 1 1 0 0 1 0 65625 1 0 0 1 1 0 1 0 0 65000 1 0 0 1 1 0 1 1 0 64375 20 Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications n tel Table 2 2 Voltage Identification Definition Sheet 5 of 5 VID7 VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc MAX 1 0 0 1 1 1 0 0 0 63750 1 0 0 1 1 T 0 1 0 63125 1 0 0 1 1 1 1 0 0 62500 1 0 0 1 1 1 1 1 0 61875 1 0 1 0 0 0 0 0 0 61250 1 0 1 0 0 0 0 1 0 60625 1 0 1 0 0 0 1 0 0 60000 1 0 1 0 0 0 1 1 0 59375 1 0 1 0 0 1 0 0 0 58750 1 0 1 0 0 1 0 1 0 58125 1 0 1 0 0 1 1 0 0 57500 1 0 1 0 0 1 1 1 0 56875 1 0 1 0 1 0 0 0 0 56250 1 0 1 0 1 0 0 1 0 55625 1 0 1 0 1 0 1 0 0 55000 1 0 1 0 1 0 1 1 0 54375 1 0 1 0 1 1 0 0 0 53750 1 0 1 0 1 1 0 1 0 53125 1 0 1 0 1 1 1 0 0 52500 1 0 1 0 1 1 1 1 0 51875 1 0 1 1 0 0 0 0 0 51250 1 0 1 1 0 0 0 1 0 50625 1 0 1 1 0 0 1 0 0 50000 1 1 1 1 1 1 1 0 OFF 1 1 1 1 1 1 1 1 OFF Notes 1 When the 11111111 VID pattern is observed or when the SKTOCC pin is high the voltage regulator output should be disabled 2 Shading denotes the expected VI D range of the Intel Xeon Processor 5500 Series 3 The VID range includes V
71. 02 NOISSIN 0002 G 1511 518 4 M ps ri Te 82530 W38MnN LUVA OH ML 7790 Teo 401 ISNY 34 9NI2NYHU3101 ONY 9NINOISN3HIQ P 0 Are JO 9NIIVU ALITIGVNHVT3 Th WAWINIW JAVH TIVHS 18 4 Q3HSINIJ ALLTI GVHWVTI E AMOAI u0102 IWIYILYN I S3LON 4311 8402 77042971 YS 0 V Y N01123S 011404402 13101 JO 1935402 N3LLIM 0114 n 30 03114510 0320003434 025012510 39 LON AVA 324301102 NI 035012510 51 i Figure 8 11 4 Pin Fan Cable Connector For Active Heat Sink Boxed Processor Specifications 147 Intel Xeon Processor 5500 Series Datasheet Volume 1 Boxed Processor Specifications ntel Figure 8 12 4 Pin Base Baseboard Fan Header For Active Heat Sink 6119 25056 VMVT VINYS 9809 61185 xot 04 OAIB 3031102 NOISSIM 0022 319NY dIHL 200 T Yn SOFA SOF SOF x 5539883101 5431381 11A NI FUY SNOISNSMIO bobi NG PIA MSV NL im 39NVQ4022V NI S30MY43101 ONY SNOLSN3MIQ 138d83NI 031312345 35 1 SETIN ASSY W3d 110 ON T n NG I NY 434 9NI2NVU3101 ONY ONINOISNINIG v ii 0 610 JO ONILYY ALITIGVHWYTJ IN WONINIM V 3AYH 11YHS LYVd Q3HSINIJ ALITIGVNAY TJ 13010272 WIYJLYW 1 6310N5310N Nid e s 00 F e r0 xr y 20 F Am si 1381840
72. 1 0 RA DDRO_DQ 54 CMOS 1 0 9 DDR2_DQ 43 CMOS 1 0 R5 DDRI1 001501 CMOS 1 0 N10 vss GND R6 VSS GND N11 PWR R7 DDR1 001551 CMOS 1 0 N33 VCC PWR R8 DDR1_DQ 54 CMOS 1 0 N34 DDR1_DQ 20 CMOS 1 0 R9 2 001551 CMOS 1 0 N35 VSS GND R10 DDR2 DQ 54 CMOS 1 0 N36 DoR2 0021 CMOS mo R11 vcc PWR N37 DDR1_DQ 14 CMOS 1 0 R33 VCC PWR N38 DDR1_DQ 15 CMOS 1 0 R34 DDR1_DQ 12 CMOS 1 0 N39 DDRI DoI CMOS R35 DDR1 DQ 13 CMOS 1 0 N40 vss GND R36 VSS GND N41 DDRO 00181 CMOS 1 0 R37 DDR1 DOS 1 CMOS 1 0 N42 DDRO_DQS_P 10 CMOS 1 0 R38 DDR1_DQS_P 1 CMOS 1 0 N43 DDRO DQ 9 CMOS 1 0 R39 DDR2 DQ 10 CMOS 1 0 P1 DDRO_DQS_N 15 CMOS 1 0 R40 DDR2 DQ 15 CMOS 1 0 P2 DDRO_DQS P 15 CMOS 1 0 R41 VSS GND VSS GND R42 DDRO_DQ 3 CMOS 1 0 DDR2_DQS_N 15 CMOS 1 0 R43 DDRO_DQ 2 CMOS 1 0 P5 DDR2 005 61 CMOS 1 0 T1 DDRO_DQ 50 CMOS 1 0 P6 DDR2 DOS P 6 CMOS 1 0 2 DDRO_DQ 51 CMOS 1 0 P7 DDR2_DQ 48 CMOS 1 0 T3 DDRO DQ 55 CMOS 1 0 ps vs Gn TA vss GND P9 DDR2_DQ 50 CMOS 1 0 T5 DDR1_DQ 51 CMOS 1 0 P10 DDR2 001511 CMOS 1 0 T6 DDR2 DQ 60 CMOS 1 0 P11 55 GND T7 DDR2 DQ 61 CMOS 1 0 P33 VSS GND DDR2_DQS_NI 7 CMOS 1 0 P34 DDR1 00181 CMOS 1 0 T9 VSS GND P35 DDR1 0019 CMOS 1 0 DDR2 001581 CMOS 1 0 P36 DDR1 DOS P 10 CMOS 1 0 T11 VCC PWR P37 DDR1 005 N 10 CMOS 1 0 T33 PWR P38 VSS GND T34 VSS G
73. 12 Current VccPLL 11 A Intel Xeon Processor V 9 A L5518 DDQ TDP 60W Vita 6 A Launch FMB 20 Thermal Design Vcc 28 A 11 12 Current VccPLL 11 A Intel Xeon Processor V 9 A L5508 38W Vita 6 A Launch FMB 20 Ippo 53 DDR3 System Memory VDDQ 1 0 A 13 14 J Interface Supply Current in Standby State Notes 1 Unless otherwise noted all specifications in this table apply to all processors These specifications are based on pre silicon characterization and will be updated as further data becomes available 2 Individual processor VID and or VIT VID values may be calibrated during manufacturing such that two devices at the same speed may have different settings 3 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required 4 The Vcc voltage specification requirements are measured across vias on the platform for the VCCSENSE and VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 5 The Vy voltage specification requirements are measured across vias on the platform for the VITD SENSE and VSS SENSE lands close to the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance
74. 2 QPIO CLKTX DP QPI 38 QPIO DTX DP 3 QPI AG43 VSS GND AJ39 QPIO_DTX_DN 3 QPI O AH1 VSS GND 40 DTX DN 4 QPI O AH2 QPI1 DTX DP 9 QPI AJ41 VSS GND QPI1_DTX_DP 8 QPI 42 QPIO DTX DN 7 QPI AH4 1 DTX DN 8 QPI 43 QPIO DTX DP 8 QPI AH5 FC AH5 AK1 QPI1 DTX DP 7 QPI AH6 QPI1 DTX DP 2 QPI O AK2 RSVD AH7 VSS GND AK3 VSS GND AH8 QPI1 DTX DN 0 QPI O AK4 QPI1 DTX DN 4 QPI AH9 TRST TAP 5 QPI1 DTX 3 O AH10 TCK TAP AK6 QPI1 DTX DP 3 QPI AH11 VCC PWR AK7 RSVD AH33 VCC PWR AK8 ISENSE Analog AH34 VSS GND AK9 VSS GND AH35 BCLK_DN CMOS 10 VSS GND AH36 PECI Asynch 1 0 AK11 VCC PWR AH37 VSS GND AK12 VCC PWR AH38 QPIO_DTX_DN 0 QPI O AK13 VCC PWR AH39 VSS GND AK14 VSS GND 40 QPIO_DTX_DP 4 15 VCC PWR AH41 QPIO DTX DP 6 QPI AK16 VCC PWR AH42 DTX 0 161 QPI AK17 VSS GND Intel Xeon Processor 5500 Series Datasheet Volume 1 69 intel T Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 7 of 35 Sheet 8 of 35 pow Land Name 2 Direction pda Land Name 4 Direction A8 vce pwr AL15 VCC PWR AK19 VCC PWR AL16 VCC PWR AK20 VSS GND AL17 VSS GND AK21 VCC PWR AL18 VCC PWR AK22 VSS GND AL19 VCC PWR AK23 VSS GND AL20 VSS GND AK24 VCC PWR AL21
75. 2 785 2704291 x 62 1 go s NO11V4OdN02 TILNI 30 ANZSNOD WJLLIXM NOlNd JHA LNOHLIM 03 4100N 0 3491419 032000N433 035012514 30 LON SINBINOD SLI ANV 32830140 NI 35012610 SI LI NOILVMEOINI T11N30I INO NOILVYOJYOJ TIANI SNIYINOO ONIMYAO SIHI I 4 me A y Intel Xeon Processor 5500 Series Datasheet Volume 1 148 Boxed Processor Specifications n tel 8 2 2 Boxed Processor Retention Mechanism and Heat Sink Support URS Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor Refer to Figure 8 5 for mounting hole dimensions Figure 8 13 illustrates the Unified Retention System URS and the Unified Backplate Assembly The URS is designed to extend air cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass URS retention transfers load to the baseboard via the Unified Backplate Assembly The URS spring captive in the heatsink provides the necessary compressive load for the thermal interface material For specific design details on the URS and the Unified Backplate please refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide All components of the URS heat sink solution will be captive to the heat sink and will only require a Phillips screwdriver to attach to the Unified Backplate Assembly When installing the URS the
76. 2 9 1 Acquiring the Mailbox The MbxSend command is used to acquire control of the PECI mailbox and issue information regarding the specific request The completion code response indicates whether or not the originator has acquired a lock on the mailbox and that completion code always specifies the Transaction ID associated with that lock see Section 6 3 2 9 2 Once a mailbox has been acquired by an originating agent future requests to acquire that mailbox will be denied with an interface busy completion code response The lock on a mailbox is not achieved until the last bit of the MbxSend Read FCS is transferred in other words it is not committed until the command completes If the host aborts the command at any time prior to that bit transmission the mailbox lock will be lost and it will remain available for any other agent to take control Intel Xeon Processor 5500 Series Datasheet Volume 1 123 n tel Thermal Specifications 6 3 2 9 2 6 3 2 9 3 6 3 2 9 4 6 3 2 9 5 124 Transaction 10 For all MbxSend commands that complete successfully the passing completion code 0x4X includes a 4 bit Transaction ID X That ID is the key to the mailbox and must be sent when retrieving response data and releasing the lock by using the MbxGet command The Transaction ID is generated internally by the processor and has no relationship to the originator of the request On Intel Xeon processor 5500 series
77. 345 VIT VID 0 0660 VIT VID 0 0975 12 VIT VID 0 0405 VIT VID 0 0720 VIT VID 0 1035 Intel Xeon Processor 5500 Series Datasheet Volume 1 37 intel Intel Xeon Processors 5500 Series Electrical Specifications Table 2 11 V Static and Transient Tolerance Sheet 2 of 2 A V Typ V Min V 51 2 3 4 13 VIT VID 0 0465 VIT VID 0 0780 VIT VID 0 1095 14 VIT VID 0 0525 VIT VID 0 0840 VIT VID 0 1155 15 VIT VID 0 0585 VIT VID 0 0900 VIT VID 0 1215 16 VIT VID 0 0645 VIT VID 0 0960 VIT VID 0 1275 17 VIT VID 0 0705 VIT VID 0 1020 VIT VID 0 1335 18 VIT VID 0 0765 VIT VID 0 1080 VIT VID 0 1395 19 VIT VID 0 0825 VIT VID 0 1140 VIT VID 0 1455 20 VIT VID 0 0885 VIT VID 0 1200 VIT VID 0 1515 21 VIT VID 0 0945 VIT VID 0 1260 VIT VID 0 1575 22 VIT VID 0 1005 VIT VID 0 1320 VIT VID 0 1635 23 VIT VID 0 1065 VIT VID 0 1380 VIT VID 0 1695 24 VIT VID 0 1125 VIT VID 0 1440 VIT VID 0 1755 25 VIT VID 0 1185 VIT VID 0 1500 VIT VID 0 1815 26 VIT VID 0 1245 VIT VID 0 1560 VIT VID 0 1875 27 VIT VID 0 1305 VIT VID 0 1620 VIT VID 0 1935 28 VIT VID 0 1365 VIT VID 0 1680 VIT VID 0 1995 Note 1 Iy listed in this table is the sum of Iqra and I 2 This table is intended to aid in reading discrete points on Figure 2 10 3 The V
78. 500 Series Datasheet Volume 1 41 intel Intel Xeon Processors 5500 Series Electrical Specifications Table 2 17 Control Sideband Signal Group DC Specifications 42 Symbol Parameter Min Typ Max Units Notes VIL Input Low Voltage 0 64 Vita V 2 3 Input Low Voltage for 0 15 Vita V 2 3 PECI ID signal Vin Input High Voltage 0 76 2 3 Vin Input High Voltage for 0 85 Vita 2 3 PECI ID signal VoL Output Low Voltage Ron V 2 4 Ron Rsys TERM Vou Output High Voltage Vita V 2 ODT On Die Termination 45 55 5 RoN Processor Sideband Buffer 10 18 Q On Resistance RoN Buffer On Resistance for 100 Q VID 7 0 Input Leakage Current 200 6 lu Input Leakage Current for 50 6 DDR THERMZ signal COMPO COMP Resistance 49 4 49 9 50 4 Q 7 Notes design guide for implementation details COMPO resistors are to VSS 8 Unless otherwise noted all specifications in this table apply to all processor frequencies The Va referred to in these specifications refers to instantaneous Vra Based on a test load of 50 to Vra Rsys term is the termination on the system and is not controlled by the Intel Xeon Processor 5500 Series Applies to all Processor Sideband signals unless otherwise mentioned in Table 2 5 For between 0 V and V ra Measured when the driver is tristated COMP resistance must be provided on the system bo
79. 6 4 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile A Power W TcasE Max C 0 57 8 5 58 7 10 59 6 15 60 5 20 61 4 25 62 3 30 63 2 35 6 64 2 40 65 0 45 65 9 50 66 9 55 67 8 60 68 7 65 69 6 70 70 5 75 71 4 80 72 3 85 73 2 90 74 1 95 75 0 Table 6 5 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile B Power W TcasE C 0 57 8 5 59 0 10 60 2 15 61 5 20 62 7 25 63 9 30 65 1 35 66 3 40 67 6 45 68 8 50 70 0 55 71 2 60 72 4 65 73 7 70 74 9 75 76 1 80 77 3 85 78 5 90 79 8 95 81 0 94 Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications Table 6 6 Figure 6 3 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel I ntel Xeon Processor 5500 Series Standard Basic SKUs Thermal Specifications Cor Thermal Minimum Maximum Design Power TCASE TCASE Notes Frequency W C C Launch to FMB 80 5 See Figure 6 3 1 2 3 4 5 Table 6 7 Notes 1 These values specified at Vcc for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified Icc Please refer to the loadline specifications in Section 2 6 7 Thermal Design Power TDP should be used for proc
80. 750 0 1 1 0 0 1 0 1 0 98125 0 1 1 0 0 1 1 0 0 97500 0 1 1 0 0 1 1 1 0 96875 0 1 1 0 1 0 0 0 0 96250 0 1 1 0 1 0 0 1 0 95625 0 1 1 0 1 0 1 0 0 95000 0 1 1 0 1 0 1 1 0 94375 0 1 1 0 1 1 0 0 0 93750 0 1 1 0 1 1 0 1 0 93125 0 1 1 0 1 1 1 0 0 92500 0 1 1 0 1 1 1 1 0 91875 0 1 1 1 0 0 0 0 0 91250 0 1 1 1 0 0 0 1 0 90625 19 m n tel Intel Xeon Processors 5500 Series Electrical Specifications Table 2 2 Voltage Identification Definition Sheet 4 of 5 VID7 VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc 0 il il 1 0 0 1 0 0 90000 0 T 1 il 0 0 1 1 0 89375 0 1 1 1 0 1 0 0 0 88750 0 il 1 di 0 1 0 1 0 88125 0 1 1 T 0 1 1 0 0 87500 0 il il 1 0 il 1 1 0 86875 0 1 di 1 1 0 0 0 0 86250 0 1 1 1 1 0 0 1 0 85625 0 1 1 1 1 0 1 0 0 85000 0 1 1 1 1 0 1 1 0 84375 0 1 1 1 1 0 0 0 83750 0 1 1 il 1 1 0 1 0 83125 0 1 1 1 1 0 0 82500 0 1 1 1 1 T 1 1 0 81875 1 0 0 0 0 0 0 0 0 81250 1 0 0 0 0 0 0 1 0 80625 1 0 0 0 0 0 1 0 0 80000 1 0 0 0 0 0 1 1 0 79375 1 0 0 0 0 di 0 0 0 78750 1 0 0 0 0 1 0 T 0 78125 1 0 0 0 0 il 1 0 0 77500 1 0 0 0 0 1 1 1 0 76875 1 0 0 0 1 0 0 0 0 76250 1 0 0 0 1 0 0 1 0 75625 1 0 0 0 1 0 1 0 0 75000 1 0 0 0 1 0 1 1 0 74375 1 0 0 0 1 1 0 0 0 73750 1 0 0 0 1 1 0 1 0 73125 1 0 0 0 1 1 1 0 0 72500 1 0 0 0 1 1 1 1 0 71875 1 0 0 1 0 0 0 0 0 71250 1 0 0 1 0 0 0 1 0 70625 T 0 0 1 0 0 1 0 0 70
81. 8 K4 CMOS 1 0 DDR1 001491 K5 CMOS 1 0 DDR1 DQ 5 AB36 CMOS 1 0 DDR1_DQ 50 R5 CMOS 1 0 DDR1 001511 T5 CMOS 1 0 DDR1_DQ 52 J4 CMOS 1 0 DDR1 DQ 53 M6 CMOS 1 0 DDR1 DQ 54 R8 CMOS 1 0 DDR1 001551 R7 CMOS 1 0 DDR1 DQ 56 W6 CMOS 1 0 DDR1 001571 W7 CMOS 1 0 DDR1 001581 Y10 CMOS 1 0 DDR1 001591 10 5 1 0 DDR1 DQ 6 Y40 CMOS 1 0 DDR1_DQ 60 v9 CMOS 1 0 DDR1 001611 W5 CMOS 1 0 DDR1_DQ 62 AAT CMOS 1 0 DDR1 001631 w9 CMOS 1 0 DDR1 DQ 7 Y39 CMOS 1 0 DDR1 DQ 8 P34 CMOS 1 0 DDR1 DQ 9 P35 CMOS 1 0 DDR1 DQS 0 Y37 CMOS 1 0 DDR1 DOS N 1 R37 CMOS 1 0 DDR1 005 N 10 P37 CMOS 1 0 DDR1 DOS N 11 K37 CMOS 1 0 DDR1 DOS N 12 K33 CMOS 1 0 DDR1 005 N 13 F7 CMOS 1 0 DDR1 DQS N 14 7 CMOS 1 0 DDR1 DQS N 15 M4 CMOS 1 0 DDR1 DQS N 16 Y5 CMOS 1 0 DDR1 DOS N 17 E35 CMOS 1 0 DDR1 DOS 2 L36 CMOS 1 0 DDR1 DOS 1 L31 CMOS 1 0 DDR1 DQS N 4 D7 CMOS 1 0 DDR1 DQS N 5 G6 CMOS 1 0 DDR1 DQS NI6 L5 CMOS 1 0 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 13 of 36 Sheet 14 of 36 Land Name pa T Direction Land Name 2 po Direction DDR1 DOS N 7 Y9 CMOS 1 0 DDR1 MA 5 F22 CMOS DDR1 DOS N 8 G34 CMOS 1 0 DDR1 MA 6 127 5 DDR1 DOS N 9 AA41 CMOS 1 0 DDR1 D22 CMOS DDR1 DOS P O0
82. AIT instructions Note that when I O instructions are used no MWAIT substates can be defined as therefore the request defaults to have a sub state or zero but always assumes the break on EFLAGS IF 0 control that can be selected using ECX with an MWAIT instruction Power States MWAIT C1 HLT MWAIT C6 C6 2 MWAIT C1 HLT enabled MWAIT C3 1 No transition to is needed to service a snoop when in C1 2 Transitions back to CO occur on an interrupt or on access to monitored address if state was entered via MWAIT Thread and Core Power State Descriptions Individual threads may request low power states as described below Core power states are automatically resolved by the processor as shown in Table 7 2 Coordination of Thread Power States at the Core Level Core State Thread 1 State Thread 0 State co 11 C6 CO CO CO CO CO cil CO Gi Gil c1 c3 CO C3 C3 C6 CO C3 C6 Notes 1 If enabled state will be C1E CO State This is the normal operating state in the processor 133 intel 7 2 1 2 7 2 1 3 7 2 1 4 7 2 2 7 2 2 1 7 2 2 2 134 C1 CIE State C1 CIE is a low power state entered when all threads within a core execute a HLT or MWAIT CIE instruction The processor thread will transition to the CO state upon occurrence of an interrupt or an access t
83. C7 DDRO ODT 3 CMOS B40 DDRO DQS NI3 CMOS 1 0 DDR1 ODT 1 CMOS Proy Gm o co DDRO 11 CMOS B42 VSS GND C10 VDDQ PWR BA3 VSS GND C11 DDRO CS 6 CMOS e DDRO ODT 4 E ES C12 DDRO_CAS CMOS BA6 GPI1 DRX DN 4 QPI ids BA7 QPI1_DRX_DP 4 QPI x agri x GPI1 DRX DN 2 QPI C15 VDDQ PWR BA9 VCC PWR C16 DDR2_WE CMOS 10 VCC PWR C17 DDR1 CS 4 CMOS 11 55 GND C18 BA 0 CMOS 12 VCC PWR C19 DDRO_CLK_N 1 CLOCK C20 PWR 14 VSS GND C21 DDR1_CLK_P 0 CLOCK 15 VCC PWR C22 DDR1_PAR_ERR 0 Asynch 16 VCC PWR C23 DDRO CMOS 17 VSS GND C24 DDRO 6 CMOS BA18 VCC PWR C25 VDDQ PWR 19 VCC PWR C26 DDRO MA 9 CMOS 20 VSS GND C27 DDR1_CKE 3 CMOS 24 VCC PWR C28 BA 2 CMOS 25 VCC PWR C29 DDRO CMOS 26 VSS GND C30 VDDQ PWR BA27 VCC PWR C31 RSVD BA28 VCC PWR C32 RSVD BA29 VSS GND C33 DDRO_ECC 3 CMOS 1 0 BA30 VCC PWR C34 DDRO_ECC 7 CMOS 1 0 Baas vss eo X C35 vss GND 76 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel
84. CMOS 1 0 DDRO_DQ 22 F43 CMOS 1 0 DDRO_DQ 23 F42 CMOS 1 0 DDRO_DQ 24 D40 CMOS 1 0 DDRO_DQ 25 C41 CMOS 1 0 DDRO DG 26 A38 CMOS 1 0 DDRO_DQ 27 D37 CMOS 1 0 DDRO_DQ 28 D41 CMOS 1 0 DDRO_DQ 29 D42 CMOS 1 0 DDRO 00131 R42 CMOS 1 0 DDRO_DQ 30 C38 CMOS 1 0 DDRO DQI 31 B38 CMOS 1 0 DDRO 001321 B5 CMOS 1 0 DDRO DQI 33 C4 CMOS 1 0 DDRO DQI 34 F1 CMOS 1 0 DDRO_DQ 35 G3 CMOS 1 0 DDRO_DQ 36 B6 CMOS 1 0 DDRO DQI 37 C6 CMOS 1 0 DDRO DQI 38 F3 CMOS 1 0 DDRO DQI 39 F2 CMOS 1 0 DDRO_DQ 4 W40 CMOS 1 0 DDRO_DQ 40 H2 CMOS 1 0 DDRO 001411 Hl CMOS 1 0 DDRO_DQ 42 L1 CMOS 1 0 DDRO DG 43 M1 CMOS 1 0 52 Table 4 1 Land Listing by Land Name Sheet 8 of 36 Land Name po Direction DDRO DQ 44 G1 CMOS 1 0 DDRO DQ 45 H3 CMOS 1 0 DDRO 001461 L3 CMOS 1 0 DDRO_DQ 47 L2 CMOS 1 0 DDRO_DQ 48 CMOS 1 0 DDRO DQ 49 N2 CMOS 1 0 DDRO DQ 5 W42 CMOS 1 0 DDRO DQ 50 T1 CMOS 1 0 DDRO DQ 51 T2 CMOS 1 0 DDRO DQ 52 M3 CMOS 1 0 DDRO DQ 53 N3 CMOS 1 0 DDRO DQ 54 R4 CMOS 1 0 DDRO DQ 55 T3 CMOS 1 0 DDRO DQ 56 U4 CMOS 1 0 DDRO 001571 vi CMOS 1 0 DDRO DQ 58 Y2 CMOS 1 0 DDRO DQ 59 Y3 CMOS 1 0 DDRO DQ 6 U41 CMOS 1 0 DDRO_DQ 60 01 5 1 0 DDRO 001611 U3 CMOS 1 0 DDRO_DQ 62 V4 CMOS 1 0 DDRO_DQ 63 WA CMOS 1 0 DDRO DQ 7 T42 CMOS 1 0 DDRO DQ 8 N41 CMOS 1 0 DDRO DQ 9 N43 CMOS 1 0 DDRO DQS N O0 U43 CMOS 1 0 DDRO DOS N 1 M41 CM
85. D control involves the processor adjusting its operating frequency via the core ratio multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption The second method clock modulation reduces power consumption by modulating starting and stopping the internal processor core clocks The processor intelligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method as with previous generation processors supporting TM1 or TM2 The Adaptive Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Adaptive Thermal Monitor activates the Thermal Control Circuit is not user configurable and is not software visible Snooping and interrupt processing are performed in the normal manner while the TCC is active With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a T
86. DN 4 AJ40 QPI QPI1 DN 17 AN6 QPI QPIO DTX DNI 5 AK41 QPI QPI1 DRX DN 18 AM7 QPI QPIO DTX DN 6 AH42 GPI QPI1 DRX DN 19 AL8 QPI QPIO DTX DN 7 AJ42 QPI QPI1 DNI2 BA8 GPI QPIO DTX DNI 8 AH43 QPI QPI1 DNI 3 AWS QPI QPIO DTX DN 9 AG41 QPI QPI1 DN 4 BA6 GPI QPIO DTX DP 0 AG38 QPI QPI1 DNI 5 AY5 GPI QPIO DTX DP 1 AF39 QPI GPI1 DRX DN 6 AUG QPI QPIO DTX DP 10 AF43 QPI QPI1 DNI 7 AW3 QPI QPIO DTX DP 11 AE42 QPI QPI1 DNI 8 AU3 QPI QPIO DTX DP 12 AD42 QPI QPI1 DN 9 AT2 QPI QPIO DTX DP 13 AC43 QPI QPI1_DRX_DP 0 AU8 QPI QPIO DTX DP 14 AD40 QPI QPI1 DRX DP 1 AV7 GPI QPIO DTX DP 15 AC41 QPI QPI1 DP 10 QPI QPIO DTX DP 16 AC39 QPI GPI1 DRX DP 11 AR4 GPI QPIO DTX DP 17 AB39 QPI QPI1 DRX DP 12 AP2 QPI QPIO DTX DP 18 AD38 QPI QPI1 DRX DP 13 AN1 GPI QPIO DTX DP 19 AE40 GPI QPI1 DRX DP 14 AM2 QPI QPIO DTX DP 2 AK37 QPI QPI1 DRX DP 15 AP3 QPI 0 DTX DP 3 AJ38 QPI QPI1 DRX DP 16 AMA QPI QPIO DTX DP 4 AH40 QPI QPI1 DP 17 AN5 GPI 50 Intel Xeon Processor 5500 Series Datasheet Volume 1 Land Listing l n Le Table 4 1 Land Listing by Land Table 4 1 Land Listing by Land Name Sh
87. DNI 13 VSS GND AN43 QPIO_DRX_DP 14 QPI AN4 QPI1 DRX DN 16 QPI AP1 VSS GND AN5 1 DRX DP 17 QPI 2 1 DRX DP 12 QPI AN6 QPI1 DRX DN 17 QPI QPI1 DRX DP 15 QPI AN7 VSS GND AP4 QPI1 DRX DN 15 QPI 8 VID 7 CMOS O AP5 VSS GND Intel Xeon Processor 5500 Series Datasheet Volume 1 71 intel T Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 11 of 35 Sheet 12 of 35 pod Land Name pode Direction pda Land Name SU Direction 6 Vss ew AR3 VSS GND AP7 PSI CMOS ARA QPI1 DRX DP 11 QPI VIDI6 CMOS AR5 GPI1 DRX DN 11 QPI AP9 VID 5 CSCI2 CMOS AR6 1 CLKRX DN QPI 10 VSS GND AR7 VCCPWRGOOD Asynch AP11 VSS GND AR8 VSS_SENSE Analog AP12 VCC PWR ARQ VCC_SENSE Analog AP13 VCC PWR AR10 VCC PWR AP14 VSS GND AR11 VSS GND apis vcc AR12 PWR AP16 VCC PWR AR13 VCC PWR AP17 VSS GND AR14 VSS GND apis VCC ewR ARIS PWR AP19 VCC PWR AR16 VCC PWR AP20 VSS GND AR17 VSS GND AP21 VCC PWR AR18 VCC PWR AP22 VSS GND AR19 VCC PWR AP23 VSS GND AR20 VSS GND AP24 VCC PWR AR21 VCC PWR AP25 VCC PWR AR22 VSS GND AP26 VSS GND AR23 VSS GND AP27 VCC PWR AR24 VCC PWR AP28 VCC PWR AR25 VCC PWR AP29 VSS GND A
88. DQ C25 PWR VCC BA30 PWR VDDQ C30 PWR VCC BA9 PWR VDDQ D13 PWR VCC M11 PWR VDDQ D18 PWR VCC M13 PWR VDDQ D23 PWR VCC M15 PWR VDDQ D28 PWR VCC M19 PWR VDDQ E11 PWR VCC M21 PWR VDDQ E16 PWR VCC M23 PWR VDDQ E21 PWR VCC M25 PWR VDDQ E26 PWR VCC M29 PWR VDDQ E31 PWR VCC M31 PWR VDDQ F14 PWR VCC M33 PWR VDDQ F19 PWR VCC N11 PWR VDDQ F24 PWR VCC N33 PWR VDDQ G17 PWR VCC R11 PWR VDDQ G22 PWR VCC R33 PWR VDDQ G27 PWR VCC T11 PWR VDDQ H15 PWR VCC T33 PWR VDDQ H20 PWR VCC wil PWR VDDQ H25 PWR VCC_SENSE ARQ Analog VDDQ J18 PWR VCCPLL U33 PWR VDDQ 123 PWR VCCPLL V33 PWR VDDQ 128 PWR VCCPLL W33 PWR VDDQ K16 PWR VCCPWRGOOD AR7 Asynch VDDQ K21 PWR VDDPWRGOOD AA6 Asynch VDDQ K26 PWR VDDQ A14 PWR VDDQ L14 PWR VDDQ A19 PWR VDDQ L19 PWR VDDQ A24 PWR VDDQ L24 PWR VDDQ A29 PWR VDDQ M17 PWR VDDQ A9 PWR VDDQ M27 PWR VDDQ B12 PWR VID 0 MSID 0 AL10 CMOS VDDQ B17 PWR VID 1 MSID 1 ALY CMOS VDDQ B22 PWR VID 2 MSID 2 AN9 CMOS VDDQ B27 PWR VID 3 CSC O0 AM10 CMOS Intel Xeon Processor 5500 Series Datasheet Volume 1 61 intel T Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 27 of 36 Sheet 28 of 36 Land Name po 1 Direction Land Name po 7 Direction VID 41 CSC 1 AN10 CMOS vss AGO GND VID 5 CSC 2 AP9 CSMO vss AH1 GND VI D 6 AP8 CMOS VSS AH34 GND VID 7
89. DR2_DQ 32 CMOS 1 0 19 55 GND K13 DDR1_BA 1 CMOS 110 DDR2 DG 40 CMOS 1 0 K14 DDR2_CS 1 CMOS L11 DDR2 DG 44 CMOS 1 0 80 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 29 of 35 Sheet 30 of 35 Land Land Name Buffer Direction Land Land Name Butter Direction No Type No Type L12 DDR2 DQI 39 CMOS M9 DDR2 DQ 42 CMOS 1 0 L13 DDR2_DQ 35 CMOS 1 0 M10 DDR2 DQ 45 CMOS L14 VDDQ PWR M11 VCC PWR L15 RSVD M12 VSS GND L16 DDR2_ODT 0 CMOS M13 vcc PWR L17 DDR2_CS 6 CMOS M14 vss GND DDR2 ODT 4 M15 VCC PWR L18 DDR1_CLK_N 2 CLOCK O M16 VSS GND L19 VDDQ PWR M17 VDDQ PWR L20 DDR2 CLK P 1 CLOCK O 18 VSS GND L21 DDR2_CLK_N 3 CLOCK O EE M19 PWR L22 DDR2 CLK P 3 CLOCK O M20 VSS GND L23 DDR_VREF Analog M21 VCC PWR L24 VDDQ PWR M22 VSS GND L25 DDR2 MA 8 CMOS O M23 VCC PWR L26 DDR2_BA 2 CMOS O E M24 VSS GND L27 DDR2 CKE 3 CMOS O M25 VCC PWR L28 DDR1_MA 3 CMOS O M26 VSS GND L29 VSS GND M27 VDDQ PWR L30 DDR1 DQS P 3 CMOS M28 VSS GND L31 DDR1 005 3 CMOS 1 0 M29 VCC PWR L32 DDR1_DQ 30 CMOS
90. DR3 operating speeds and cache sizes 25 m n tel Intel Xeon Processors 5500 Series Electrical Specifications 2 4 2 5 26 N Processors must operate at the same core frequency Note processors within the same power optimization segment supporting different maximum core frequencies e g a 2 93 GHz 95 W and 2 66 GHz 95 W can be operated within a system However both must operate at the highest frequency rating commonly supported Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel 3 Processors must share symmetry across physical packages with respect to the number of logical processors per package number of cores per package but not necessarily the same subset of cores within the packages number of Intel QuickPath interfaces and cache topology 4 Mixing dissimilar steppings is only supported with processors that have identical Extended Family Extended Model Processor Type Family Code and Model Number as indicated by the function 1 of the CPUID instruction Mixing processors of different steppings but the same model as per CPUID instruction is supported Details regarding the CPUID instruction are provided in the AP 485 Intel Processor Identification and the CPUID Instruction application note and the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A 5 After AND ing the feature flag and extended feature flags
91. Datasheet Volume 1 The PCI ConfigWr command gives sideband write access to the PCI configuration space maintained in the processor The exact listing of supported devices functions is defined below in Table 6 17 PECI originators may conduct a device function register enumeration sweep of this space by issuing reads in the same manner that BIOS would 113 n tel Thermal Specifications Table 6 17 PCI ConfigWr Device Function Support 6 3 2 5 1 114 Writable Description Device Function 2 1 Intel QuickPath Interconnect Link 0 Intel IBIST 2 5 Intel QuickPath Interconnect Link 1 Intel IBIST 3 4 Memory Controller Intel BIST 4 3 Memory Controller Channel 0 Thermal Control Status 5 3 Memory Controller Channel 1 Thermal Control Status 6 3 Memory Controller Channel 2 Thermal Control Status Notes 1 Currently not available for access through the PECI PCIConfigWr command PCI configuration addresses are constructed as shown in Figure 6 16 and this command is subject to the same address configuration rules as defined in Section 6 3 2 4 PCI configuration reads may be issued in byte word or dword granularities Because a PCI ConfigWr results an update to potentially critical registers inside the processor it includes an Assured Write FCS AW FCS byte as part of the write data payload In the event that the AW FCS mismatches with the client calculated FCS the client
92. ECC 5 CMOS 1 0 E41 vss GND F38 DDR2_DQ 30 CMOS 1 0 E42 DDRO 001181 CMOS 1 0 9 VSS GND E43 DDRO 001191 CMOS 1 0 F40 DDR2_DQ 25 CMOS 1 0 F1 DDRO DG 34 CMOS 1 0 F41 DDRO_DQS_P 2 CMOS 1 0 F2 DDRO DG 39 CMOS 1 0 F42 DDRO_DQ 23 CMOS 1 0 DDRO 001381 CMOS 1 0 F43 DDRO_DQ 22 CMOS 1 0 FA VSS GND G1 DDRO_DQ 44 CMOS 1 0 F5 DDR1_DQ 35 CMOS 1 0 G2 55 GND F6 DDR1_DQ 39 CMOS 1 0 G3 DDRO DG 35 CMOS 1 0 F7 DDR1_DQS_N 13 CMOS G4 DDR1_DQ 42 CMOS 1 0 F8 DDR1_DQS_P 13 CMOS 1 0 G5 DDR1_DQ 46 CMOS 1 0 F9 55 GND G6 DDR1 DOS N 5 CMOS 1 0 F10 DDR1_DQ 36 CMOS 1 0 G7 55 F11 DDR1 0017131 CMOS DDR1 001371 CMOS 1 0 F12 DDRO ODT 0 CMOS G9 DDR1 DG 44 CMOS 1 0 F13 DDR2_ODT 1 CMOS G10 DDR2 001371 CMOS 1 0 14 VDDQ PWR G11 DDR2 DQ 36 CMOS 1 0 F15 DDR2_MA 13 CMOS G12 VSS GND F16 DDR2_CAS CMOS G13 DDR1_WE CMOS F17 DDR2_BAT1 CMOS G14 DDR1_RAS CMOS F18 DDRO_CLK_P 2 CLOCK G15 DDRO_CS 0 CMOS F19 VDDQ PWR G16 DDR2_CS 0 CMOS F20 DDR2_MAI4 CMOS G17 VDDQ PWR F21 DDR2 PAR ERRZ 0 Asynch G18 DDR2 MA 2 5 F22 DDR1_MAI5 CMOS G19 DDR1 CLK P 1 CLOCK F23 DDR2 PAR ERR 2 Asynch 620 DDR1_CLK_N 1 CLOCK F24 VDDQ PWR 621 DDR2_CLK_N 2 CLOCK F25 DDRI1 PAR ERRZ 2 Asynch 622 VDDQ PWR F26 DDR1 MA 15 CMOS G23 DDR2_MA 12 CMOS
93. GND VSS AM17 GND VSS AP43 GND VSS AM20 GND VSS AP5 GND VSS AM22 GND VSS AP6 GND VSS AM23 GND VSS AR11 GND VSS AM26 GND VSS AR14 GND VSS AM29 GND VSS AR17 GND VSS AM32 GND VSS AR2 GND VSS AM35 GND VSS AR20 GND VSS AM37 GND VSS AR22 GND VSS AM39 GND VSS AR23 GND VSS AM5 GND VSS AR26 GND VSS AM9 GND VSS AR29 GND VSS AN11 GND VSS AR3 GND VSS AN14 GND VSS AR32 GND VSS AN17 GND VSS AR35 GND VSS AN20 GND VSS AR39 GND VSS AN22 GND VSS AT11 GND VSS AN23 GND VSS AT14 GND VSS AN26 GND VSS AT17 GND VSS AN29 GND VSS AT20 GND VSS AN3 GND VSS AT22 GND VSS AN32 GND VSS AT23 GND VSS AN35 GND VSS AT26 GND VSS AN37 GND VSS AT29 GND VSS AN41 GND VSS AT32 GND VSS AN7 GND VSS AT35 GND VSS AP1 GND VSS AT38 GND VSS AP10 GND VSS AT41 GND VSS AP11 GND VSS AT7 GND VSS AP14 GND VSS AT8 GND VSS AP17 GND VSS AUI GND VSS AP20 GND VSS AU11 GND VSS AP22 GND VSS AU14 GND VSS AP23 GND VSS AU17 GND VSS AP26 GND VSS AU20 GND VSS AP29 GND VSS AU22 GND VSS AP32 GND VSS AU23 GND VSS AP35 GND VSS AU26 GND Intel Xeon Processor 5500 Series Datasheet Volume 1 63 intel T Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 31 of 36 Sheet 32 of 36 Land Name po pod Direction Land Name po 17 Direction VSS GND 5 AY32 GND VSS AU32 GND vss AY37 GND 55 AU35 GND vss AY42 GND vss AU36 GND VSS AY7 GND VSS AU43 GND
94. ID transitions that may be initiated by thermal events Extended HALT state transitions see Section 7 2 higher C States see Section 7 2 or Enhanced Intel SpeedStep Technology transitions see Section 7 5 The Extended HALT state must be enabled for the processor to remain within its specifications 4 Once the VRM EVRD is operating after power up if either the Output Enable signal is de asserted or a specific VID off code is received the VRM EVRD must turn off its output the output should go to high impedance within 500 ms and latch off until power is cycled 2 1 7 3 1 Power On Configuration POC Logic VI D 7 0 signals also serve a second function During power up Power On Configuration POC 7 0 functionality is multiplexed onto these signals via 1 5 kQ pull up or pull down resistors located on the baseboard These values provide voltage regulator keying VID 7 inform the processor of the platforms power delivery capabilities MSID 2 0 and program the gain applied to the ISENSE input CSC 2 0 Table 2 3 maps VID signals to the corresponding POC functionality Intel Xeon Processor 5500 Series Datasheet Volume 1 21 intel Intel Xeon Processors 5500 Series Electrical Specifications Table 2 3 Power On Configuration POC 7 0 Decode Function Bits POC Settings Description VR Key VID 7 Ob for VR11 1 Electronic safety key distinguishing VR11 1 Spare VID 6 Ob default Reserved for f
95. Intel Xeon Processor 5500 Series Datasheet Volume 1 March 2009 Document Number 321321 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITI ONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Xeon Processor 5500 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel processor numbers are not a measure of performance Processor numb
96. N 5 K7 CMOS 1 0 DDR2 DQS NI6 P5 CMOS 1 0 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 17 of 36 Sheet 18 of 36 Land Name pha T Direction Land Name 2 pes Direction DDR2 DOS 71 T8 CMOS DDR2 MA 5 K23 CMOS O DDR2_DQS_N 8 G30 CMOS DDR2 MA 6 K22 CMOS O DDR2 DOS N 9 T35 CMOS DDR2 MA 7 124 CMOS O DDR2 DOS P 0 W37 CMOS DDR2 MA 8 L25 CMOS O DDR2 DOS P 1 T37 CMOS DDR2 MA 9 H22 CMOS O DDR2_DQS_P 10 U40 CMOS 1 0 DDR2_MA_PAR B18 CMOS DDR2 DQS P 11 M38 CMOS DDR2 0071101 116 5 O DDR2_DQS_P 12 H38 CMOS DDR2 ODT 1 F13 CMOS O DDR2 DOS P 13 H11 CMOS DDR2 0071121 015 CMOS DDR2 DQS P 14 K9 CMOS 1 0 DDR2_ODT 3 D10 CMOS O DDR2 DQS P 15 N4 CMOS DDR2 PAR ERRZ O F21 Asynch DDR2 DQS P 16 V6 CMOS 1 0 DDR2_PAR_ERR 1 125 Asynch DDR2 DQS P 17 H31 CMOS 1 0 DDR2_PAR_ERR 2 F23 Asynch DDR2 DOS P 2 K40 CMOS DDR2 5 017 CMOS O DDR2_DQS_P 3 E39 CMOS DDR2_RESET E32 CMOS O DDR2_DQS_P 4 J10 CMOS DDR2_WE C16 CMOS O DDR2_DQS_P 5 L7 CMOS 1 0 AH5 AH5 DDR2 DOS P 6 P6 CMOS GTLREF AJ37 Analog DDR2 DOS P 7 U8 CMOS 15 5 Analog DDR2 DOS P 8 G29 CMOS PECI AH36 Asynch
97. N39 QPI QPIO DRX DP 19 AP38 QPI QPIO DP 2 AV36 QPI QPIO DRX DP 3 AW36 QPI QPIO DP A BA36 QPI 49 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 3 of 36 Sheet 4 of 36 Land Name Ne 1 Direction Land Name pos e Direction QPIO DP 5 AW37 QPI QPIO DTX DP 5 AK40 QPI QPIO DP 6 BA38 QPI QPIO DTX DP 6 AH41 GPI QPIO DP 7 AU39 QPI QPIO DTX DP 7 AK42 QPI QPIO DP 8 AW40 GPI QPIO DTX DP 8 AJ 43 QPI QPIO_DRX_DP 9 AU40 QPI QPIO DTX DP 9 AG40 QPI GPIO DTX DN 0 AH38 GPI QPI1 CLKRX DN AR6 QPI QPIO DTX DN 1 AG39 QPI QPI1 CLKRX DP AT6 QPI QPIO DTX DN 10 AE43 QPI QPI1 CLKTX DN AE6 QPI QPIO DTX DN 11 AE41 QPI QPI1 CLKTX DP AF6 QPI QPIO DTX DN 12 AC42 QPI QPI1 COMP AL6 Analog QPIO DTX DN 13 AB43 QPI QPI1 AV8 QPI QPIO DTX DN 14 AD39 QPI QPI1 DRX DN 1 AW7 GPI QPIO DTX DN 15 AC40 QPI QPI1 DN 10 AR1 QPI QPIO DTX DN 16 AC38 QPI QPI1_DRX_DN 11 AR5 QPI QPIO DTX DN 17 AB38 QPI QPI1 DRX DN 12 AN2 QPI QPIO DTX DN 18 AE38 QPI QPI1 DRX DN 13 AM1 QPI QPIO DTX DN 19 AF40 QPI QPI1 DRX DN 14 AM3 QPI QPIO DTX DN 2 AK38 QPI QPI1 DRX DN 15 AP4 QPI QPIO DTX AJ39 QPI QPI1 DRX DN 16 ANA QPI QPIO DTX
98. ND P39 DDR1_DQ 10 CMOS 1 0 T35 DDR2_DQS_N 9 CMOS 1 0 P40 DDR2_DQ 20 CMOS 1 0 T36 DDR2 DQ 11 CMOS 1 0 P41 DDRO 001131 CMOS 1 0 T37 DDR2_DQS P 1 CMOS 1 0 P42 DDRO_DQ 12 CMOS 1 0 T38 DDR2_DQS_N 1 CMOS 1 0 P43 VSS GND T39 VSS GND m vs cw ppRbaosN30 cvs wo 82 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 33 of 35 Sheet 34 of 35 Land Name Bunter Direction mand Land Name Buffer Direction No Type No Type T41 DDR2_DQ 14 CMOS V37 DDR2 00161 CMOS 1 0 T42 DDRO 0071 CMOS V38 DDR2_DQ 7 CMOS 1 0 T43 DDRO DOS P 0 CMOS v39 DDR2_DQ 13 CMOS 1 0 01 DDRO 001601 CMOS 40 55 GND U2 VSS GND V41 DDRO_DQ 1 CMOS 1 0 U3 DDRO_DQ 61 CMOS V42 DDRO DQS N 9 CMOS 1 0 U4 DDRO_DQ 56 CMOS V43 DDRO DQS P 9 CMOS 1 0 U5 DDR2_DQ 56 CMOS W1 DDRO_DQS_NI 7 CMOS 1 0 U6 DDR2_DQ 57 CMOS W2 DDRO 005 P 7 CMOS 1 0 U7 VSS GND W3 VSS GND U8 DDR2 DOS P 7 CMOS W4 DDRO 001631 CMOS 1 0 U9 DDR2 DQ 63 CMOS W5 DDR1 DQ 61 CMOS 1 0 U10 DDR2_DQ 59 CMOS W6 DDR1 DQ 56 CMOS U11 RSVD W7 DDR1 DQ 57 CMOS U33 VCCPLL PWR ws VSS GND U34 DDR2 DQ 4 CMOS W9 DDR1 DQ 63 CMOS 1 0
99. ND AU5 VSS GND AT9 VCC PWR 06 1 DRX DN 6 QPI 10 PWR AU7 QPI1 DP 6 QPI 11 VSS GND AU8 QPI1 DP 0 QPI 12 VCC PWR 09 VCC PWR AT13 VCC PWR AU10 VCC PWR AT14 VSS GND AU11 VSS GND AT15 VCC PWR AU12 VCC PWR AT16 VCC PWR AU13 VCC PWR AT17 VSS GND AU14 VSS GND AT18 VCC PWR 015 VCC PWR AT19 VCC PWR AU16 VCC PWR AT20 VSS GND AU17 VSS GND AT21 VCC PWR AU18 VCC PWR AT22 VSS GND AU19 VCC PWR AT23 VSS GND AU20 VSS GND AT24 VCC PWR AU21 VCC PWR AT25 VCC PWR AU22 VSS GND AT26 VSS GND AU23 VSS GND AT27 VCC PWR AU24 VCC PWR AT28 VCC PWR AU25 VCC PWR 29 VSS GND AU26 VSS GND AT30 VCC PWR AU27 VCC PWR AT31 VCC PWR AU28 VCC PWR AT32 VSS GND AU29 VSS GND AT33 VCC PWR AU30 VCC PWR AT34 VCC PWR AU31 VCC PWR AT35 VSS GND AU32 VSS GND AT36 RSVD AU33 VCC PWR AT37 QPIO_DRX_DP 0 QPI AU34 VCC PWR AT38 VSS GND AU35 VSS GND AT39 QPIO_DRX_DN 7 QPI AU36 VSS GND Intel Xeon Processor 5500 Series Datasheet Volume 1 73 intel T Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 15 of 35 Sheet 16 of 35 pod Land Name 2 Direction pda Land Name S Direction AU37 GPIO DNO VCC PWR AU38 QPIO DP 1 QPI AV35
100. O DOS P 3 B39 CMOS 1 0 DDRO_RESET D32 CMOS DDRO DOS P 4 E3 CMOS 1 0 DDRO_WE B13 CMOS DDRO DOS P 5 K2 CMOS 1 0 DDR1 BA 0 C18 CMOS DDRO DOS P 6 R2 CMOS 1 0 DDR1 BA 1 K13 CMOS DDRO DOS P 7 w2 CMOS 1 0 DDR1_BA 2 H27 CMOS DDRO DOS P 8 D34 CMOS 1 0 DDR1_CAS E14 CMOS DDRO DQS P 9 V43 CMOS 1 0 DDR1_CKE 0 H28 CMOS DDRO ECC 0 C36 CMOS 1 0 DDR1_CKE 1 E27 CMOS DDRO_ECC 1 A36 CMOS 1 0 DDR1_CKE 2 D27 CMOS DDRO ECC 2 F32 CMOS 1 0 DDR1_CKE 3 C27 CMOS DDRO ECC 3 C33 CMOS 1 0 DDR1 CLK N 0 D21 CLOCK DDRO ECC 4 C37 CMOS 1 0 DDR1 CLK N 1 G20 CLOCK DDRO_ECC 5 A37 CMOS 1 0 DDR1_CLK_N 2 L18 CLOCK DDRO_ECC 6 B34 CMOS 1 0 DDR1_CLK_N 3 H19 CLOCK DDRO ECC 7 C34 CMOS 1 0 DDR1 CLK P O C21 CLOCK DDRO MA 0 A20 CMOS DDR1 CLK P 1 G19 CLOCK DDRO B21 CMOS DDR1 CLK P 2 K18 CLOCK DDRO MA 10 B19 CMOS DDR1 CLK P 3 H18 CLOCK DDRO MA 11 A26 CMOS DDR1 5 101 D12 CMOS DDRO MA 12 B26 CMOS DDR1_CS 1 A8 CMOS DDRO MA 13 A10 CMOS DDR1_CS 2 E15 CMOS DDRO MA 14 A28 CMOS DDR1_CS 3 E13 CMOS DDRO_MA 15 B29 CMOS DDR1 5 141 C17 CMOS DDRO MA 2 C23 CMOS DDR1_CS 5 E10 CMOS DDRO MA 3 D24 CMOS DDR1 CS 6 C14 CMOS DDRO MA 4 B23 CMOS POR us Intel Xeon Processor 5500 Series Datasheet Volume 1 53 intel Land Listing
101. OCK DDR1 MA 11 E23 CMOS DDR2_CS 0 G16 CMOS DDR1 MA 12 E24 CMOS DDR2_CS 1 K14 CMOS DDR1 MA 13 B14 CMOS DDR2_CS 2 D16 CMOS DDR1 MA 14 H26 CMOS DDR2_CS 3 H16 CMOS DDR1 MA 15 F26 CMOS DDR2 5 141 E17 CMOS DDR1 MA 2 117 5 DDR2 5 151 D9 CMOS DDR1 MA 3 L28 CMOS DDR2 CS 6 L17 CMOS DDR1 MA 4 K28 CMOS PPR ZORTA Intel Xeon Processor 5500 Series Datasheet Volume 1 55 intel Land Listing Table 4 1 Land Listing by Land Name Sheet 15 of 36 Land Name ro 1 Direction DDR2_CS 7 115 CMOS DDR2 ODT 5 DDR2_DQ 0 W34 CMOS 1 0 DDR2_DQ 1 W35 CMOS 1 0 DDR2_DQ 10 R39 CMOS 1 0 DDR2_DQ 11 T36 CMOS 1 0 DDR2_DQ 12 W39 CMOS 1 0 DDR2 DG 13 v39 CMOS 1 0 DDR2_DQ 14 T41 CMOS 1 0 DDR2_DQ 15 R40 CMOS 1 0 DDR2_DQ 16 M39 CMOS 1 0 DDR2_DQ 17 M40 CMOS 1 0 DDR2_DQ 18 J40 CMOS 1 0 DDR2_DQ 19 J39 CMOS 1 0 DDR2_DQ 2 v36 CMOS 1 0 DDR2_DQ 20 P40 CMOS 1 0 DDR2_DQ 21 N36 CMOS 1 0 DDR2_DQ 22 L40 CMOS 1 0 DDR2 DQI23 K38 CMOS 1 0 DDR2 DG 24 G40 CMOS 1 0 DDR2_DQ 25 F40 CMOS 1 0 DDR2_DQ 26 137 5 DDR2 DQI27 H37 CMOS 1 0 DDR2_DQ 28 H39 CMOS 1 0 DDR2_DQ 29 G39 CMOS 1 0 DDR2 00131 U36 CMOS 1 0 DDR2_DQ 30 F38 CMOS 1 0 DDR2_DQ 31 E38 CMOS 1 0 DDR2 001321 K12 CMOS 1 0 DDR2 00133 112 5 DDR2 001341 H13 CMO
102. OS 1 0 DDRO 005 N 10 M43 CMOS 1 0 DDRO_DQS_N 11 G43 CMOS 1 0 DDRO DQS N 12 C39 CMOS 1 0 DDRO DOS N 13 D4 CMOS 1 0 DDRO DQS N 14 Ji CMOS DDRO 005 N 15 P1 CMOS 1 0 DDRO DQS N 16 v3 CMOS 1 0 DDRO DOS N 17 B35 CMOS 1 0 DDRO DOS N 2 G41 CMOS 1 0 DDRO DOS N 3 B40 CMOS 1 0 DDRO DQS N 4 E4 CMOS 1 0 DDRO DQS N 5 K3 CMOS 1 0 DDRO DQS N 6 R3 CMOS 1 0 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 9 of 36 Sheet 10 of 36 Land Name pa Direction Land Name n pes Direction DDRO DOS N 7 CMOS 1 0 DDRO MA 5 B24 CMOS DDRO DOS N 8 D35 CMOS 1 0 DDRO MA 6 C24 CMOS DDRO DQS N 9 V42 CMOS 1 0 DDRO MA 7 A25 CMOS DDRO DOS P 0 T43 CMOS 1 0 DDRO MA 8 B25 CMOS DDRO DQS P 1 L41 CMOS 1 0 DDRO MA 9 C26 CMOS DDRO 005 P 10 N42 CMOS 1 0 DDRO_MA_PAR B20 CMOS DDRO 005 P 11 H42 CMOS 1 0 DDRO ODT 0 F12 CMOS DDRO 005 P 12 D39 CMOS 1 0 DDRO_ODT 1 C9 CMOS DDRO_DQS_P 13 D5 CMOS 1 0 DDRO_ODT 2 B11 CMOS DDRO_DQS_P 14 12 CMOS 1 0 DDRO ODT 3 C7 CMOS DDRO 005 P 15 P2 CMOS 1 0 DDRO PAR ERR 0 D25 Asynch DDRO 005 P 16 v2 CMOS 1 0 DDRO_PAR_ERR 1 B28 Asynch DDRO DQS P 17 B36 CMOS 1 0 DDRO_PAR_ERR 2 A27 Asynch DDRO DOS P 2 F41 CMOS 1 0 DDRO_RAS A15 CMOS DDR
103. OS O D21 1 N 0 CLOCK E18 DDRO CLK 21 CLOCK O D22 DDR1 MA 7 CMOS E19 DDRO_CLK_N 3 CLOCK O D23 VDDQ PWR E20 DDRO_CLK_P 3 CLOCK O D24 DDRO MA 3 CMOS O E21 VDDQ PWR D25 DDRO_PAR_ERR 0 Asynch 22 DDR1 MA 8 CMOS O D26 DDR2 CKE 2 CMOS E23 DDR1_MA 11 CMOS 27 DDR1 CKE 2 CMOS O E24 DDR1_MA 12 CMOS 28 VDDQ PWR E25 DDR1_PAR_ERR 1 Asynch 029 DDR1 5 CMOS E26 VDDQ PWR D30 RSVD E27 DDR1 CKE 1 CMOS D31 RSVD E28 RSVD D32 DDRO_RESET CMOS 29 DDR2 ECC 2 CMOS 1 0 Intel Xeon Processor 5500 Series Datasheet Volume 1 77 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 23 of 35 Sheet 24 of 35 Land Land Name Buffer Direction Land Land Name Butfer Direction No Type No Type E30 DDR2 CMOS 1 0 F27 RSVD VDDQ PWR F28 RSVD E32 DDR2_RESET CMOS F29 VSS GND E33 DDR1_ECC 2 CMOS 1 0 F30 DDR2_ECC 7 CMOS 1 0 E34 DDR1_ECC 6 CMOS 1 0 F31 DDR2_ECC 6 CMOS 1 0 E35 DDR1_DQS_N 17 CMOS 1 0 F32 DDRO_ECC 2 CMOS 1 0 E36 VSS GND F33 DDR2_ECC 1 CMOS 1 0 E37 DDR1_ECC 4 CMOS 1 0 4 VSS GND E38 DDR2 001311 CMOS 1 0 F35 DDR1_DQS_P 17 CMOS 1 0 E39 DDR2 005 CMOS 1 0 F36 DDR1_ECC 1 CMOS 1 0 E40 DDR2_DQS_N 3 CMOS 1 0 F37 DDR1
104. Part 2 Intel 64 and IA 32 Architectures Optimization Reference Manual 248966 1 Intel virtualization Technology Specification for Directed 1 0 D51397 001 1 Architecture Specification Intel Xeon Processor 5500 Series Datasheet Volume 2 321322 1 Intel Xeon Processor 5500 Series Thermal Mechanical Design 321323 1 Guide Intel Xeon Processor 5500 Series Specification Update 321324 1 Entry Level Electronics Bay Specifications A Server System www ssiforum org Infrastructure SSI Specification for Entry Pedestal Servers and Workstations ACPI Specifications www acpi info Notes 1 Document is available publicly at http www intel com 12 Intel Xeon Processor 5500 Series Datasheet Volume 1 m e Intel Xeon Processors 5500 Series Electrical Specifications n tel 2 2 1 2 1 1 Figure 2 1 2 1 2 Intel Xeon Processors 5500 Series Electrical Specifications Processor Signaling Intel Xeon Processor 5500 Series include 1366 lands which utilize various signaling technologies Signals are grouped by electrical characteristics and buffer type into various signal groups These include Intel QuickPath Interconnect DDR3 Reference Clock Command Control and Data Platform Environmental Control Interface PECI Processor Sideband System Reference Clock Test Access Port TAP and Power Other signals Refer to Table 2 5 for details Detailed layout routing and termination guidelines corresponding to these
105. Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 17 of 35 Sheet 18 of 35 Land Land Name Buffer Direction Land Land Name Butter Direction No Type No Type AW31 VCC PWR AY30 VCC PWR AW32 VSS GND AY31 VCC PWR AW33 VCC PWR 2 VSS GND AW34 VCC PWR AY33 VCC PWR AW35 VSS GND AY34 VCC PWR AW36 QPIO_DRX_DP 3 QPI AY35 RSVD AW37 QPIO_DRX_DP 5 QPI AY36 QPIO DNI 3 QPI AW38 QPIO DRX DN 5 QPI AY37 VSS GND AW39 RSVD AY38 0 161 AW40 QPIO DRX DP 8 QPI AY39 RSVD AW41 RSVD AY40 RSVD AW42 RSVD AY41 RSVD AY2 VSS GND 42 VSS GND AY3 RSVD B2 VSS GND AY4 RSVD B3 BPM 0 GTL 1 0 AY5 QPI1_DRX_DN 5 4 BPM 3 GTL 1 0 AY6 QPI1 DP 5 5 DDRO 001321 CMOS AY7 VSS GND B6 DDRO DQ 36 CMOS 1 0 AY8 QPI1_DRX_DP 2 7 VDDQ PWR AY9 VCC PWR B8 DDRO_CS 7 CMOS DDRO ODT 5 AY10 VCC PWR B9 DDRO_CS 3 CMOS O AY11 VSS GND B10 DDRO_CS 1 CMOS AY12 VCC PWR 11 DDRO 0017121 CMOS AY13 VCC PWR B12 VDDQ PWR AY14 VSS GND B13 DDRO_WE CMOS AY15 VCC PWR B14 DDR1 MA 13 CMOS AY16 PWR B15 DDRO_CS 4
106. Profile will result in increased probability of TCC activation and may incur measurable performance loss The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance The Short Term Thermal Profile may only be used for short term excursions to higher ambient operating temperatures not to exceed 96 hours per instance 360 hours per year and a maximum of 15 instances per year as compliant with NEBS Level 3 Operation at the Short Term Thermal Profile for durations exceeding 360 hours per year violate the processor thermal specifications and may result in permanent damage to the processor Refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 5500 Series Datasheet Volume 1 99 intel Thermal Specifications Table 6 11 Intel Xeon Processor L5518 Thermal Profile Power W Nominal TcasE MAX Short term TcasE MAX C 0 51 9 66 9 5 53 4 68 4 10 54 9 69 9 15 56 4 71 4 20 57 9 72 9 25 59 5 74 5 30 61 0 76 0 35 62 5 77 5 40 64 0 79 0 45 65 5 80 5 50 67 0 82 0 55 68 5 83 5 60 70 0 85 0 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc Icc combination wherein Vcc exceeds Vcc max at
107. R 27 PWR Ive Tans PWR vcc AW28 PWR AU19 PWR AW30 PWR AU21 PWR AW31 PWR AU24 PWR AW33 PWR AU25 PWR AW34 PWR AU27 PWR VCC AW9 PWR VCC AU28 PWR VCC AY10 PWR VCC AU30 PWR VCC AY12 PWR VCC AU31 PWR VCC AY13 PWR VCC AU33 PWR VCC AY15 PWR VCC AU34 PWR VCC AY16 PWR VCC AU9 PWR VCC AY18 PWR Ivec mm Tawo PWR vcc AY19 PWR 12 PWR AY21 PWR AV13 PWR AY24 PWR 15 PWR AY25 PWR AV16 PWR AY27 PWR 18 PWR AY28 PWR 19 PWR AY30 PWR 21 PWR AY31 PWR 24 PWR AY33 PWR 25 PWR AY34 PWR 27 PWR 9 PWR VCC AV28 PWR PWR PWR BA12 PWR AV31 PWR VCC BA13 PWR VCC AV33 PWR VCC BA15 PWR vce avaa PWR vcc BA16 PWR 60 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 25 of 36 Sheet 26 of 36 Land Name pa pcd Direction Land Name 2 ped Direction VCC BA18 PWR VDDQ B32 PWR VCC BA19 PWR VDDQ B7 PWR VCC BA24 PWR VDDQ C10 PWR VCC BA25 PWR VDDQ C15 PWR VCC BA27 PWR VDDQ C20 PWR VCC BA28 PWR VD
108. R VTTD AA10 PWR VTTD AD9 PWR VTTD AA11 PWR VTTD AE34 PWR VTTD AA33 PWR VTTD AE35 PWR VTTD AB10 PWR VTTD PWR VTTD AB11 PWR VTTD AE9 PWR VTTD AB33 PWR VTTD AF36 PWR VTTD AB34 PWR VTTD AF37 PWR VTTD AB8 PWR VTTD AF8 PWR VTTD AB9 PWR VTTD AF9 PWR VTTD AC10 PWR VTTD SENSE AE36 Analog VTTPWRGOOD AB35 Asynch 66 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing 4 1 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 1 of 35 rand Land Name Butter Direction No Type A4 VSS GND A5 BPM 1 GTL 1 0 A6 VSS GND A7 DDRO 5 151 CMOS A8 DDR1_CS 1 CMOS A9 VDDQ PWR A10 DDRO MA 13 CMOS 14 VDDQ PWR A15 DDRO_RAS CMOS A16 DDRO_BA 1 CMOS A17 DDR2 01 CMOS A18 DDR2 MA 0 CMOS A19 VDDQ PWR A20 DDRO MA 0 CMOS A24 VDDQ PWR A25 DDRO MA 7 CMOS A26 DDRO MA 11 CMOS A27 DDRO PAR ERR 2 Asynch A28 DDRO MA 14 CMOS A29 VDDQ PWR A30 DDRO_CKE 1 CMOS A31 RSVD A35 VSS GND A36 DDRO_ECC 1 CMOS 1 0 A37 DDRO_ECC 5 CMOS 1 0 A38 DDRO_DQ 26 CMOS 1 0 A39 VSS GND 40 RSVD 41 VSS GND AA3 VSS GND AA4 BCLK ITP DN CMOS AA5 ITP DP CMOS AA6 VDDPWRGOOD Asynch
109. R26 VSS GND vec AR27 VCC PWR AP31 VCC PWR AR28 VCC PWR AP32 VSS GND AR29 VSS GND AP33 VCC PWR AR30 VCC PWR AP34 VCC PWR AR31 VCC PWR AP35 VSS GND AR32 VSS GND AP36 VSS GND AR33 VCC PWR AP37 VSS GND AR34 VCC PWR AP38 QPIO DRX DP 19 QPI AR35 VSS GND AP39 QPIO_DRX_DN 18 QPI AR36 RSVD AP40 QPIO DRX DN 17 QPI AR37 RSVD AP41 QPIO DRX DP 17 QPI AR38 QPIO_DRX_DN 19 QPI AP42 QPIO DRX DP 13 QPI AR39 VSS GND AP43 VSS GND AR40 QPIO DRX DN 12 QPI AR1 1 DRX DN 10 QPI AR41 QPIO CLKRX DP QPI AR2 vws cv 1 72 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 13 of 35 Sheet 14 of 35 pos Land Name pes Direction pond Land Name 2 Direction AR43 QPIO DNI 11 QPI 40 DP 12 AT1 QPI1 DRX DP 10 QPI 41 VSS GND AT2 1 DRX DN 9 QPI AT42 QPIO_DRX_DN 10 QPI QPI1 DRX DP 9 QPI QPIO DP 11 AT4 RSVD AU1 VSS GND AT5 RSVD AU2 RSVD AT6 QPI1 CLKRX DP QPI AU3 QPI1 DRX DN 8 QPI 7 VSS GND AUA QPI1 DP 8 QPI AT8 VSS G
110. RAM will be put into self refresh Intel Xeon Processor 5500 Series C State Power Specifications Table 7 3 lists C State power specifications for various Intel Xeon processor 5500 series SKUs Processor C State Power Specifications 130W 95W sow 60w3 38W 35 W 30 W 30 40 W 22 W 16 W C3 30W 26 W 26 35 W 18 W 12 W C6 12W 10 W 10 15 W 8 W 8 W Notes 1 Specifications are at Tease 50C with all cores in the specified C State 2 Standard Basic SKUs 3 Applies to Low Power SKU and Intel Xeon Processor L5518 Intel Xeon Processor 5500 Series Datasheet Volume 1 135 intel 7 3 Sleep States The processor supports the ACPI sleep states SO S1 53 and S4 S5 as shown in For information on ACPI S states and related terminology refer to ACPI Specification The S state transitions are coordinated by the processor in response PM Request PMReq messages from the chipset The processor itself will never request a particular S state Table 7 4 Processor S States S State Power Reduction Allowed Transitions 50 Normal Code Execution 51 via PMReq S1 Cores in CIE like state processor responds with SO via reset or PMReq CmpD S1 message 53 54 via PMReq S3 Memory put into self refresh processor responds with SO via reset CmpD S3 message 54 55 Processor responds with CmpD S4 S5 message SO via reset Notes T If the chipset request
111. RSVD AU39 QPIO DRX DP 7 QPI AV36 QPIO_DRX_DP 2 QPI 040 QPIO DRX DP 9 QPI AV37 0 0 121 QPI AU41 QPIO DRX 9 QPI AV38 QPIO_DRX_DN 1 QPI 042 QPIO DRX DP 10 QPI AV39 VSS GND AU43 VSS GND AV40 QPIO DNI 8 QPI AV1 RSVD AV41 55 AV2 RSVD AV42 RSVD Ivm vo cmos o RSVD VSS GND AW1 VSS GND AV5 GPI1 DRX DP 3 QPI AW2 RSVD ave vwa cvs o AW3 QPI1_DRX_DN 7 QPI 7 1 DRX DP 1 QPI AW4 1 DRX DP 7 QPI AV8 1 DRX DN O QPI 5 QPI1_DRX_DN 3 9 VCC PWR AW6 VSS GND 10 VCC PWR AW7 QPI1_DRX_DN 1 QPI 11 55 GND AW8 VSS GND AV12 VCC PWR AW9 VCC PWR AV13 VCC PWR AW10 VCC PWR AV14 VSS GND AW11 VSS GND AV15 VCC PWR AW12 VCC PWR AV16 VCC PWR AW13 VCC PWR AV17 VSS GND AW14 VSS GND avis vce pwr AW15 VCC PWR AV19 VCC PWR AW16 VCC PWR AV20 VSS GND AW17 VSS GND AV21 VCC PWR AW18 VCC PWR AV22 VSS GND AW19 VCC PWR AV23 VSS GND AW20 VSS GND AV24 VCC PWR AW21 VCC PWR AV25 VCC PWR AW22 VSS GND AV26 VSS GND AW23 VSS GND AV27 VCC PWR AW24 VCC PWR AV28 VCC PWR AW25 VCC PWR AV29 VSS GND AW26 VSS GND AV30 VCC PWR AW27 VCC PWR AV31 VCC PWR AW28 VCC PWR AV32 VSS GND AW29 VSS GND Av33 vcc ew AW30 VCC PWR 74 Intel Xeon
112. S 1 0 DDR2_DQ 35 L13 CMOS 1 0 DDR2 001361 11 5 1 0 DDR2_DQ 37 G10 CMOS 1 0 DDR2_DQ 38 H12 CMOS 1 0 DDR2 DQI 39 L12 CMOS 1 0 DDR2 00141 U34 CMOS 1 0 DDR2 DG 40 L10 CMOS 1 0 DDR2 DQI41 K10 CMOS 1 0 DDR2_DQ 42 M9 CMOS 1 0 DDR2_DQ 43 N9 CMOS 1 0 56 Table 4 1 Land Listing by Land Name Sheet 16 of 36 Land Name po Ta Direction DDR2_DQ 44 L11 CMOS 1 0 DDR2 DQ 45 M10 CMOS 1 0 DDR2 001461 L8 CMOS 1 0 DDR2_DQ 47 M8 CMOS 1 0 DDR2_DQ 48 P7 CMOS 1 0 DDR2 001491 N6 CMOS 1 0 DDR2 DQ 5 4 5 1 0 DDR2_DQ 50 P9 CMOS DDR2 001511 P10 CMOS 1 0 DDR2_DQ 52 N8 CMOS DDR2 001531 N7 CMOS 1 0 DDR2 DQ 54 R10 CMOS 1 0 DDR2 DQ 55 R9 CMOS 1 0 DDR2 DQ 56 U5 CMOS 1 0 DDR2 DQ 57 U6 CMOS 1 0 DDR2 001581 T10 CMOS 1 0 DDR2 DQ 59 U10 CMOS 1 0 DDR2 DQ 6 v37 CMOS 1 0 DDR2 001601 T6 CMOS 1 0 DDR2 001611 T7 CMOS 1 0 DDR2_DQ 62 v8 CMOS 1 0 DDR2_DQ 63 U9 CMOS 1 0 DDR2 DQ 7 v38 CMOS 1 0 DDR2 DQ 8 U38 CMOS 1 0 DDR2 DQ 9 U39 CMOS 1 0 DDR2 DOS 0 W36 CMOS 1 0 DDR2_DQS_N 1 T38 CMOS 1 0 DDR2 DOS N 10 T40 CMOS 1 0 DDR2_DQS_N 11 L38 CMOS 1 0 DDR2 DQS N 12 G38 CMOS 1 0 DDR2 005 N 13 J11 CMOS 1 0 DDR2 DQS N 14 K8 CMOS 1 0 DDR2 DQS N 15 P4 CMOS 1 0 DDR2 DOS N 16 V7 CMOS 1 0 DDR2 005 N 17 G31 CMOS 1 0 DDR2_DQS_N 2 K39 CMOS 1 0 DDR2_DQS_N 3 E40 CMOS 1 0 DDR2 DQS N 4 J9 CMOS 1 0 DDR2 DQS
113. Status Bidirectional PROCHOT Log Bidirectional PROCHOT Status TCC Activation Log TCC Activation Status 6 3 2 6 4 Counter Snapshot Read Clear A reference time and Thermally Constrained time are managed in the processor These two counters are managed via the Mailbox These counters are valuable for detecting thermal runaway conditions where the TCC activation duty cycle reaches excessive levels The counters may be simultaneously snapshot simultaneously cleared or independently read The simultaneous snapshot capability is provided in order to guarantee concurrent reads even with significant read latency over the PECI bus Each counter is 32 bits wide Table 6 20 Counter Definition Counter Counter Name Definition Number Total Time 0x00 Counts the total time the processor has been executing with a resolution of approximately 1ms This counter wraps at 32 bits Thermally Constrained Time 0x01 Counts the total time the processor has been operating at a lowered performance due to TCC activation This timer includes the time required to ramp back up to the original P state target after TCC activation expires This timer does not include TCC activation time as a result of an external assertion of PROCHOT Intel Xeon Processor 5500 Series Datasheet Volume 1 117 n tel Thermal Specifications 6 3 2 6 5 6 3 2 6 6 6 3 2 6 7
114. T AH9 TAP RSVD AV42 AH11 PWR RSVD AV43 VCC AH33 PWR RSVD AW2 VCC AJ11 PWR RSVD AW39 VCC AJ 33 PWR RSVD AW41 AK11 PWR RSVD AW42 VCC AK12 PWR RSVD AY3 AK13 PWR RSVD AY35 15 PWR RSVD AY39 AK16 PWR _ ava AK18 PWR RSVD AY40 AK19 PWR RSVD AY41 AK21 PWR RSVD B33 AK24 PWR RSVD BA4 25 PWR RSVD 4 AK27 PWR RSVD C31 AK28 PWR RSVD C32 PWR RSVD D30 AK31 PWR RSVD D31 AK33 PWR RSVD E28 AL12 PWR RSVD F27 AL13 PWR RSVD F28 AL15 PWR RSVD G28 VCC AL16 PWR RSVD H29 VCC AL18 PWR Rvo ae AL19 PWR 58 Intel Xeon Processor 5500 Series Datasheet Volume 1 Land Listing Table 4 1 Sheet 21 of 36 Land Listing by Land Name Table 4 1 intel Sheet 22 of 36 Land Listing by Land Name Land Buffer Land Buffer Land Name No Type Direction Land Name No Type Direction VCC AL21 PWR VCC AP13 PWR VCC AL24 PWR VCC AP15 PWR VCC AL25 PWR VCC AP16 PWR VCC AL27 PWR VCC AP18 PWR VCC AL28 PWR VCC AP19 PWR VCC AL30 PWR VCC AP21 PWR VCC AL31 PWR VCC AP24 PWR VCC AL33 PWR VCC AP25 PWR VCC AL34 PWR VCC AP27 PWR VCC AM12 PWR VCC AP28 PWR VCC AM13 PWR VCC AP30 PWR VCC AM15 PWR
115. TCC via PROCHOT can provide a means for thermal protection of system components As an output PROCHOT will go active when the processor temperature monitoring sensor detects that one or more cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled for all cores TCC activation due to PROCHOT assertion by the system will result in the processor immediately transitioning to the minimum frequency and corresponding voltage using Freq VID control Clock modulation is not activated in this case The TCC will remain active until the system de asserts PROCHOT Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel 6 2 5 6 3 PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on PROCHOTZ only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that PROCHOT will only be asserted for very short periods of time when running the most power intensive applications A
116. Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance The Short Term Thermal Profile may only be used for short term excursions to higher ambient operating temperatures not to exceed 96 hours per instance 360 hours per year and a maximum of 15 instances per year as compliant with NEBS Level 3 Operation at the Short Term Thermal Profile for durations exceeding 360 hours per year violate the processor thermal specifications and may result in permanent damage to the processor Refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 5500 Series Datasheet Volume 1 101 n tel Thermal Specifications Table 6 13 Intel Xeon Processor L5508 Thermal Profile Power W Nominal Tcase_max C Short Term Tcase_ max C 0 50 0 65 0 5 52 7 67 7 10 55 3 70 3 15 58 0 73 0 20 60 6 75 6 25 63 3 78 3 30 66 0 81 0 35 68 6 83 6 38 70 2 85 2 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc combination wherein Vcc exceeds Vcc max at specified cc Please refer to the loadline specifications in Section 2 6 2 Thermal Design Power TDP should be used for processor thermal solution design targets
117. U35 DDR2 DOS P 9 CMOS W10 DDR1 DQ 59 CMOS 1 0 U36 DDR2_DQ 3 CMOS W11 Vcc PWR U37 VSS GND W33 VCCPLL PWR U38 DDR2_DQ 8 CMOS W34 DDR2 00101 CMOS 1 0 U39 DDR2_DQ 9 CMOS W35 DDR2_DQ 1 CMOS 1 0 040 DDR2 DOS P 10 CMOS 1 0 W36 DDR2 DOS N 0 CMOS 1 0 U41 DDRO 00161 CMOS W37 DDR2 DOS P 0 CMOS 1 0 U42 VSS GND W38 VSS GND U43 DDRO DQS N 0 CMOS W39 DDR2 0001121 CMOS 1 0 V1 DDRO DQ 57 CMOS W40 DDRO DQ 4 CMOS 1 0 V2 DDRO DQS P 16 CMOS W41 DDRO_DQ 0 CMOS 1 0 DDRO 005 N 16 CMOS W42 DDRO 00151 CMOS 1 0 V4 DDRO 001621 CMOS W43 55 GND V5 VSS GND Y1 VSS GND V6 DDR2 DQS P 16 CMOS Y2 DDRO 001581 CMOS 1 0 V7 DDR2 005 N 16 CMOS Y3 DDRO DQ 59 CMOS 1 0 V8 DDR2 001621 CMOS Y4 DDR1 DQS P 16 CMOS 1 0 v9 DDR1_DQ 60 CMOS Y5 DDR1 DQS N 16 CMOS 1 0 V10 VSS GND Y6 VSS GND V11 RSVD Y7 DDR_COMP 1 Analog V33 VCCPLL PWR Y8 DDR1 DOS P 7 CMOS 1 0 V34 DDR2 DQ 5 CMOS Y9 DDR1 005 N 7 CMOS V35 VSS GND Y10 DDR1 001581 CMOS 1 0 V36 DDR2_DQ 2 CMOS 11 VSS GND Intel Xeon Processor 5500 Series Datasheet Volume 1 83 intel Table 4 2 Land Listing by Land Number Sheet 35 of 35 Land Land Name Butrer Direction No Type v33 vss cw Y34 00131 CMOS 1 0 Y35 DDR1_DQ 2 CMOS 1 0 Y36 VSS GND Y37 DDR1 DQS N 0 CMOS 1 0 Y38 DDR1 005 P 0 CMOS 1 0 Y39 DDR1_DQ 7 CMOS 1 0 Y40 DDR1 DG 6 CMOS 1
118. Y38 CMOS 1 0 DDR1 MA 8 E22 CMOS DDR1 DQS P 1 R38 CMOS 1 0 DDR1 MA 9 G24 CMOS DDR1 005 P 10 P36 CMOS 1 0 DDR1_MA_PAR D20 CMOS DDR1 005 P 11 L37 CMOS 1 0 DDR1 ODT 0 D11 CMOS DDR1 005 P 12 K34 CMOS 1 0 DDR1 ODT 1 C8 CMOS DDR1 005 P 13 F8 CMOS 1 0 DDR1 ODT 2 D14 CMOS DDR1 005 P 14 H7 CMOS 1 0 DDR1 ODT 3 F11 CMOS DDR1 DQS P 15 M5 CMOS 1 0 DDR1_PAR_ERR 0 C22 Asynch DDR1 DQS 1161 Y4 CMOS 1 0 DDR1_PAR_ERR 1 E25 Asynch DDR1 005 P 17 F35 CMOS 1 0 DDR1_PAR_ERR 2 F25 Asynch DDR1 DOS P 2 L35 CMOS 1 0 DDR1_RAS G14 CMOS DDR1 DOS P 3 L30 CMOS 1 0 DDR1_RESET D29 CMOS DDR1 DOS P 4 E7 CMOS 1 0 DDR1_WE G13 CMOS DDR1 DQS P 5 H6 CMOS 1 0 DDR2 BA 0 A17 CMOS DDR1 DQS P 6 L6 CMOS 1 0 DDR2 BA 1 F17 CMOS DDR1 DQS P 7 Y8 CMOS 1 0 DDR2 BA 2 L26 CMOS DDR1 DOS P 8 G33 CMOS 1 0 DDR2_CAS F16 CMOS DDR1 DQS P 9 AA40 CMOS 1 0 DDR2_CKE 0 126 5 DDR1 ECC 0 D36 CMOS 1 0 DDR2_CKE 1 G26 CMOS DDR1_ECC 1 F36 CMOS 1 0 DDR2_CKE 2 D26 CMOS DDR1 ECC 2 E33 CMOS 1 0 DDR2_CKE 3 L27 CMOS DDR1 ECC 3 G36 CMOS 1 0 DDR2 CLK N 0 121 CLOCK DDR1 ECC 4 E37 CMOS 1 0 DDR2 CLK N 1 K20 CLOCK DDR1_ECC 5 F37 CMOS 1 0 DDR2_CLK_N 2 G21 CLOCK DDR1 ECC 6 E34 CMOS 1 0 DDR2 CLK N 3 L21 CLOCK DDR1 ECC 7 G35 CMOS 1 0 DDR2 CLK P 0 122 CLOCK DDR1 01 J14 CMOS DDR2 CLK P 1 L20 CLOCK DDR1 116 5 DDR2 CLK P 2 H21 CLOCK DDR1 MA 10 H14 CMOS DDR2 CLK P 3 L22 CL
119. a 2 2 2 2 2 7 2 2 2 118 6 22 ACPI T state Throttling Control Read Write 4 120 6 23 MbxSend Command Data nne nnn 121 6 24 Waa Wa ker ya ERE awa UR LP MEER 121 65 25 MbXQGet E FE rkAK 123 6 26 Temperature Sensor Data 1121 127 6 27 PECI Power up Timellrie i ban n rna aa n an n dm aa a 129 7 1 POC Timing Requirements ene nemen 132 4352 POWelStatess a a i EAE PERDERE RU RUE 744 0 0 133 8 1 Boxed Active 2 2 0 0 0 a a kala nn 138 8 2 Boxed Passive Active Combination Heat Sink With Removable Fan 138 8 3 Boxed Passive Active Combination Heat Sink with Fan Removed 139 8 4 Intel Boxed 25 5 mm Tall Passive Heat Sink Solution 139 8 5 Side Baseboard Keep Out Zones sss nmn 141 8 6 Side Baseboard Mounting Hole Keep Out ZONES 142 8 7 Bottom Side Baseboard Keep Out Zones aaa 143 Intel Xeon Processor 5500 Series Datash
120. a host or originator to manage different command suites or response codes from the client Revision Number is always reported in the second byte of the GetDIB response The Revision Number always maps to the revision number of this document Figure 6 13 Revision Number Definition Major Revision Minor Revision For a client that is designed to meet the specification the Revision Number it returns will be 0010 0000b 110 Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel GetTemp The GetTemp command is used to retrieve the temperature from a target PECI address The temperature is used by the external thermal management system to regulate the temperature on the die The data is returned as a negative value representing the number of degrees centigrade below the Thermal Control Circuit Activation temperature of the PECI device Note that a value of zero represents the temperature at which the Thermal Control Circuit activates The actual value that the thermal management system uses as a control set point Tcontrol is also defined as a negative number below the Thermal Control Circuit Activation temperature TCONTROL may be extracted from the processor by issuing a PECI Mailbox MbxGet see Section 6 3 2 8 or using a RDMSR instruction Please refer to Section 6 3 6 for details regarding temperature data formatting Command Format The GetTemp
121. able 2 9 Each processor includes a dedicated VR11 1 regulator igure 2 3 VccPLL 1 80 V Each processor includes dedicated and PLL circuits VDDQ 1 50 V Each processor and DDR3 stack shares a dedicated voltage regulator Each processor includes a dedicated VR11 0 regulator 11 Vr Vra P1V1_Vtt is VID 4 2 controlled V ra VTTD a 2 VID range is 1 0255 1 2000 20 offset see Table 2 4 igure 2 represents a typical voltage Vrr and max loadlines represent a 31 5 mV offset from typ 7 Note 1 Refer to Table 2 8 for voltage and current specifications Further platform and processor power delivery details can be found in the Intel Xeon Processor 5500 Platform Design Guide PDG Intel Xeon Processor 5500 Series Datasheet Volume 1 15 m n tel Intel Xeon Processors 5500 Series Electrical Specifications 2 1 7 1 2 1 7 2 2 1 7 3 16 Power and Ground Lands For clean on chip power distribution processors include lands for all required voltage supplies These include 210 each Vcc 271 ea lands must be supplied with the voltage determined by the VID 7 0 signals Table 2 2 defines the voltage level associated with each core VID pattern Table 2 9 and Figure 2 3 represent Vcc static and transient limits e 3 each lands connected to a 1 8 V supply power the Phase Lock Loop PLL clock generation circuitry An on di
122. achine check banks Host controllers may read Power Control Unit errors directly by issuing a PCI ConfigRd command of address 0x000000B0 Machine Check Read MbxSend Data Format Byte 0 1 2 3 4 Request Type Data 31 0 Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications Table 6 21 Machine Check Bank Definitions Bank Number Bank I ndex Meaning o o MCO CTL 31 0 MCO CTL 63 32 MCO STATUS 31 0 MCO STATUS 63 32 MCO ADDR 31 0 MCO ADDR 63 32 MCO MISC 31 0 MCO MISC 63 32 MC1 CTL 31 0 MC1 CTL 63 32 MC1 STATUS 31 0 MC1 STATUS 63 32 MC1 ADDR 31 0 MC1 ADDR 63 32 MC1 MISC 31 0 MC1 MISC 63 32 MC6 CTL 31 0 MC6 CTL 63 32 MC6 STATUS 31 0 MC6 STATUS 63 32 MC6 ADDR 31 0 MC6 ADDR 63 32 MC6 MISC 31 0 MC6 MISC 63 32 MC8 CTL 31 0 MC8 CTL 63 32 MC8 STATUS 31 0 MC8 STATUS 63 32 MC8 ADDR 31 0 MC8 ADDR 63 32 MC8 MISC 31 0 co co CW DW DW DID AL DID A aj OD 2 BT PL PF FL FL R O oj of of Of O NL DO D Niej O TL oO L PN T O UL BY WEN RF OF NI OD R MC8 MISC 63 32 6 3 2 6 9 T state Throttling Control Read Write PECI offers the ability to enable and configure ACPI T state core clock modulation throttling ACPI T state thro
123. ard with 196 resistors See the applicable platform Intel Xeon Processor 5500 Series Datasheet Volume 1 Package Mechanical Specifications n tel 3 3 1 Figure 3 1 Package Mechanical Specifications Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array FC LGA6 package that interfaces with the motherboard via an LGA1366 socket The package consists of a processor mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the Processors and Socket in the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide TMDG for complete details on the LGA1366 socket The package components shown in Figure 3 1 include the following 1 Integrated Heat Spreader IHS 2 Thermal Interface Material TI M 3 Processor core die 4 Package substrate 5 Capacitors Processor Package Assembly Sketch Die TAM Substrate __ ku Capacitors ed LGA1366 Socket System Boar Note 1 Socket and motherboard are included for reference and are not part of processor package Intel Xeon Processor 5500 Series Datasheet Volume 1 43 n tel Package Mechanical Speci
124. ating frequencies and voltages When the TCC is activated the processor automatically transitions to the new operating frequency This transition occurs very rapidly on the order of 2 us Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps to support this method During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will be one VID table entry see Table 2 2 The processor continues to execute instructions during the voltage transition Operation at the lower voltages reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point via the intermediate VI D frequency points Transition of the VID code will occur first to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 8 for an illustration of this ordering Frequency and Voltage Ordering R Temperature fmax f as ne Frequen
125. cessor This diagram is to aid in the identification of the processor Processor Top Side Markings Legend Mark Text Engineering Mark GRPILINE1 INTEL M C YY GRP1LINE2 INTEL CONFIDENTIAL GRPILINE3 ES XXXXX GRPILINE4 FORECAST NAME GRPILINE5 FPO 4 GRP1LINE1 GRP1LINE2 GRP1LINE3 GRP1LINE4 GRP1LINE5 Legend Mark Text Production Mark GRP1LINE1 INTEL M C YY PROC GRP1LINE2 SUB BRAND GRP1LI SSPEC XXXXX GRP1LINE4 SPEED CACHE INTC GRP1LINE5 FPO e4 Processor Land Coordinates Please refer to Figure 3 3 which shows the bottom view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Intel Xeon Processor 5500 Series Datasheet Volume 1 Land Listing 4 Land Listing Intel Xeon Processors 5500 Series Pin This section provides sorted land list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor lands ordered alphabetically by land name Table 4 2 is a listing of all Note A land name prefixed with a FC denotes a Future Connect land 4 1 Assignments processor lands ordered by land number 4 1 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 1 of 36 Land Name um isl Direction BCLK_DN AH35 CMOS
126. chanism to limit the processor temperature If bit 4 of the IA32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same IA32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 596 on 87 596 off to 87 596 on 12 596 off in 12 596 increments On Demand mode may be used in conjunction with the Adaptive Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If Adaptive Thermal Monitor is enabled note it must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOTZ The PROCHOT signal is bi directional in that it can either signal when the processor any core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the
127. cifications n tel 6 3 6 Temperature Data 6 3 6 1 Format The temperature is formatted in a 16 bit 2 s complement value representing a number of 1 64 degrees centigrade This format allows temperatures in a range of 512 C to be reported to approximately a 0 016 C resolution Figure 6 26 Temperature Sensor Data Format MSB MSB LSB LSB Upper nibble Lower nibble Upper nibble Lower nibble S X X X X X X X X X X X X X X X Sign Integer Value 0 511 Fractional Value 70 016 6 3 6 2 I nterpretation The resolution of the processor s Digital Thermal Sensor DTS is approximately 1 C which be confirmed by a RDMSR from IA32 THERM STATUS MSR 0x19C where it is architecturally defined PECI temperatures are sent through a configurable low pass filter prior to delivery in the GetTemp response data The output of this filter produces temperatures at the full 1 64 C resolution even though the DTS itself is not this accurate Temperature readings from the processor are always negative in a 2 s complement format and imply an offset from the reference TCC activation temperature As an example assume that the TCC activation temperature reference is 100 C A PECI thermal reading of 10 indicates that the processor is running approximately 10 C below the TCC activation temperature or 90 C PECI temperature readings are not reliable at temperatures above TCC activati
128. condition or a processor RESET condition or processor S1 state Retry is appropriate outside of the RESET or S1 states CC 0x86 Mailbox interface is unavailable or busy If the MbxSend response returns a bad Read FCS the completion code can t be trusted and the semaphore may or may not be taken In order to clean out the interface an MbxGet must be issued and the response data should be discarded MbxGet The MbxGet command is utilized for retrieving response data from the generic Mailbox interface as well as for unlocking the acquired mailbox Please refer to Section 6 3 2 7 for details regarding the MbxSend command Many of the fundamental concepts of Mailbox ownership release and management are discussed in Section 6 3 2 9 Write Data The MbxGet command is designed to retrieve response data from a previously deposited request In order to guarantee alignment between the temporally separated request MbxSend and response MbxGet commands the originally granted Transaction ID sent as part of the passing MbxSend completion code must be issued as part of the MbxGet request Any mailbox request made with an illegal or unlocked Transaction ID will get a failed completion code response If the Transaction ID matches an outstanding transaction ID associated with a locked mailbox the command will complete successfully and the response data will be returned to the originator Unlike MbxSend no Assure
129. cy VIDE gt nis VID 777777 VID PROCHOT Time 105 n tel Thermal Specifications 6 2 2 2 6 2 3 6 2 4 106 Clock Modulation Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor factory configured to 37 596 on and 62 596 off The period of the duty cycle is configured to 32 microseconds when the TCC is active Cycle times are independent of processor frequency A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the TCC activation when the Frequency VID targets are at their minimum settings It may also be initiated by software at a configurable duty cycle On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Adaptive Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Intel Xeon processor 5500 series must not rely on software usage of this me
130. d Due to the complexity of the number of chassis and baseboard configurations several airflow and flow impedance values exist Please refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide for detailed mechanical drawings and specific airflow and impedance values applicable to your use conditions It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C Intel Xeon Processor 5500 Series Datasheet Volume 1 m e Boxed Processor Specifications n tel 8 4 Boxed Processor Contents The Boxed Processor and Boxed Thermal Solution contents are outlined below Boxed Processor Contents ntel Xeon processor 5500 series Installation and warranty manual ntel Inside Logo Boxed Thermal Solution Heat sink assembly solution Thermal interface material pre applied on heat sink if included Installation and warranty manual Intel Xeon Processor 5500 Series Datasheet Volume 1 153 e n tel Boxed Processor Specifications 154 Intel Xeon Processor 5500 Series Datasheet Volume 1
131. d and is cleared on a passing command Completion Code Pass Fail Mask Oxxx xxxxb Command passed lxxx xxxxb Command failed Intel Xeon Processor 5500 Series Datasheet Volume 1 125 intel Table 6 28 Note 6 3 5 Table 6 29 126 Thermal Specifications Device Specific Completion Code CC Definition Completion Code Description 0x00 0x3F Device specific pass code 0x40 Command Passed 4 Command passed with a transaction ID of X 0x40 Transaction ID 3 0 0x50 0x7F Device specific pass code CC 0x80 Error causing a response timeout Either due to a rare internal timing condition or a processor RESET condition or processor S1 state Retry is appropriate outside of the RESET or S1 states CC 0x81 Thermal configuration data was malformed or exceeded limits CC 0x82 Thermal status mask is illegal CC 0x83 Invalid counter select CC 0x84 Invalid Machine Check Bank or Index CC 0x85 Failure due to lack of Mailbox lock or invalid Transaction ID CC 0x86 Mailbox interface is unavailable or busy CC OxFF Unknown Invalid Mailbox Request The codes explicitly defined in this table may be useful in PECI originator response algorithms All reserved or undefined codes may be generated by a PECI client device and the originating agent must be capable of tolerating any code The Pass Fail mask defined in Table 6 27 applies to all codes and
132. d Write protocol is necessary for this command because this is a read only function Command Format The MbxGet format is as follows Write Length 2 Read Length 5 Command 0xd5 Multi Domain Support Yes see Table 6 26 Description Retrieves response data from mailbox and unlocks releases that mailbox resource Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications n tel Figure 6 25 MbxGet Byte 0 1 2 3 wt 4 5 6 7 8 9 10 11 LSB Response Data 31 0 MSB FCS Note that the 4 byte data response defined above is sent in standard PECI ordering with LSB first and MSB last Table 6 24 MbxGet Response Definition Response Meaning Aborted Write FCS Response data is not ready Command retry is appropriate CC 0x40 Command passed data is valid CC 0x80 Error causing a response timeout Either due to a rare internal timing condition or a processor RESET condition or processor S1 state Retry is appropriate outside of the RESET or S1 states CC 0x81 Thermal configuration data was malformed or exceeded limits CC 0x82 Thermal status mask is illegal CC 0x83 Invalid counter select CC 0x84 Invalid Machine Check Bank or Index CC 0x85 Failure due to lack of Mailbox lock or invalid Transaction ID CC 0x86 Mailbox interface is unavailable or busy CC OxFF Unknown Invalid Mailbox Request 6 3 2 9 Mailbox Usage Definition 6 3
133. d time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP instead of the maximum processor power consumption The Adaptive Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications Table 6 1 Figure 6 1 intel designed to the Flexible Motherboard FMB guidelines even if a processor with lower power dissipation is currently planned The Adaptive Thermal Monitor feature must be enabled for the processor to remain within its specifications Intel Xeon Processor W5580 Thermal Specifications Care Thermal Design Minimum Maximum Frequency Power TCASE TCASE Notes W C Launch to 130 5 See Figure 6 2 Table 6 4 1 2 3 4 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified Please refer to the loadline specifications in Section 2 6 7 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power
134. e PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices The Intel Xeon Processor 5500 Series contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read processor temperature perform processor manageability functions and manage processor interface tuning and diagnostics Please refer to Section 6 for processor specific implementation details for PECI interface operates at a nominal voltage set by Vrp The set of DC electrical specifications shown in Table 2 13 is used with devices normally operating from a interface supply I nput Device Hysteresis The PECI client and host input buffers must use a Schmitt triggered input design for improved noise immunity Please refer to Figure 2 2 and Table 2 13 Input Device Hysteresis Vrp Maximum Vp s Minimum Vp Minimum s Valid Input Hysteresis Signal Range Maximum Vy J PECI Low Range Minimum PECI Ground Processor Sideband Signals Intel Xeon Processor 5500 Series include sideband signals that provide a variety o
135. e PLL filter solution is implemented within the Intel Xeon Processor 5500 Series 45 each Vppg 17 ea Vss lands connected to a 1 50 V supply provide power to the processor DDR3 interface This supply also powers the DDR3 memory subsystem e 7 each Vra 5 Vss and 26 17 ea Vss lands must be supplied with the voltage determined by the VIT VID 4 2 signals Coupled with a 20 mV offset this corresponds to a VIT VID pattern of 010 10 Table 2 4 specifies the voltage levels associated with each VTT VID pattern Table 2 11 and Figure 2 10 represent V static and transient limits All Vcc and Vrrp lands must be connected to their respective processor power planes while all Vss lands must be connected to the system ground plane Refer to the Intel Xeon Processor 5500 Platform Design Guide PDG for decoupling voltage plane and routing guidelines for each power supply voltage Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the Intel Xeon Processor 5500 Series is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cpy K such as electrolytic capacitors supply current during longer lasting changes in current demand for example coming out of an idle condition Similarly they act as
136. e VR controller does not currently need to be able to provide ICC above 204A and the VR controller can use this information to move to more efficient operation point This signal will de assert at least 3 3us before the current consumption will exceed 20A The minimum PSI assertion time is 1 BCLK The minimum 51 de assertion time is 3 3us This pin does not require a pull down For platforms which could experience false PSI assertions during power up if this pin is left floating a pull up may be used 1K 5K Otherwise it can be left floating For boards currently pulling this signal to Vss this is not a critical change to make immediately but it is recommended for production builds Notes RESET Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents Note some PLL Intel QuickPath Interconnect and error states are not effected by reset and only VCCPWRGOOD forces them to a known state For a power on Reset RESET must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications RESET must not be kept asserted for more than 10 ms while VCCPWRGOOD is asserted RESET must be held deasserted for at least one millisecond before it is asserted again RESET must be held asserted before VCCPWRGOOD is asserted This signal does not have on die termination and must be terminated on the system board RESET is a
137. e design considerations Meeting the processor s temperature specifications is also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specifications are found in Section 6 of this document 151 n tel Boxed Processor Specifications 8 3 1 1 8 3 1 2 8 3 1 3 Note 152 2U Passive Active Combination Heat Sink Solution Active Configuration The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting It may be still be necessary to implement some form of chassis air guide or air duct to meet the T 4 temperature of 40 C depending on the pedestal chassis layout Use of the active configuration in a 2U rackmount chassis is not recommended It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor thermal solution should not be preheated by other system components Meeting the processor s temperature specification is the responsibility of the system integrator This thermal solution is for use with 95 W and 130 W TDP processor SKUs Passive Configuration In the passive configuration it is assumed that a chassis duct will be implemented Processors with a TDP of 130 W or 95 W must provide a minimum airflow of 30 CFM at 0 205 H2
138. ection provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide TMDG The boxed processor will ship with a component thermal solution Refer to Section 8 for details on the boxed processor Thermal Specifications To allow optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature specifications as defined by the applicable thermal profile See Table 6 2 and Figure 6 1 for Intel Xeon Processor W5580 130W TDP Table 6 4 and Table 6 5 and Figure 6 2 for Intel Xeon processor 5500 series Advanced SKU 95W TDP Table 6 7 and Figure 6 3 for Intel Xeon processor 5500 series Standard Basic SKUs 80W TDP Table 6 9 and Figure 6 4 for Intel Xeon processor 5500 series Low Power SKU 60W TDP Table 6 11 and Figure 6 5 for Intel Xeon Processor L5518 60W TDP supporting NEBS thermals Table 6 13 and Figure 6 6 for Intel Xeon Processor L5508 38W TDP supporting NEBS thermals Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to this processor s TMDG The Intel Xeon processor 5500 series implement a methodology for managing process
139. ed on the static load requirement 5 See Intel8 Xeon Processor 5500 Series Thermal Mechanical Design Guide TMDG for minimum socket load to engage processor within socket 3 1 4 Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Table 3 2 Package Handling Guidelines Parameter Maximum Recommended Notes Shear 70 Ibs Tensile 25 Ibs Torque 35 in lbs 3 1 5 Package Insertion Specifications The processor can be inserted into and removed from a LGA1366 socket 15 times The socket should meet the LGA1366 requirements detailed in the TMDG Intel Xeon Processor 5500 Series Datasheet Volume 1 47 n tel Package Mechanical Specifications Table 3 3 3 1 8 Figure 3 4 3 1 9 48 Processor Mass Specification The typical mass of the processor is 35 grams This mass weight includes all the components that are included in the package Processor Materials Table 3 3 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 3 4 shows the topside markings on the pro
140. eet Volume 1 5 1000 0 04 0 04 0 04 0 0 04 0 1 0 0 0 0 0 0 0 0 Y 0 0 Y 0 aa FA HR HF HB HH 0 N QI UJ N IB N UJ N P H I2 R3 ID Q QU N HN 0 UJ UJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ H ES U N CH Primary and Secondary Side 3D Height Restriction 20 144 Volumetric Height 2 12 4 2 2 2 11 66 145 Volumetric Height 4 1 4 11 1 1 11 4 nena 146 4 Pin Fan Cable Connector For Active Heat Sink 147 4 Pin Base Baseboard Fan Header For Active Heat Sink 148 Thermal Solution lt 222222 aaa aaa aa EEE kk EE EE nenne 150 Fan Cable Connector Pin Out For 4 Pin Active Thermal 151 Intel Xeon Processor 5500 Series Feature Set Overview sess 10 i RR RENE ELI PA PR ETE RI PER ERAN 12 Processor Power Supply Voltages1 0 0 00 cc cece emen nennen enn 15 Voltage Identification Definition
141. eet 5 of 36 Sheet 6 of 36 Land Name pha T Direction Land Name 2 posed Direction DRX ame ae GPI1 DTX DP 18 ADS QPI QPI1 DRX DP 19 AM8 QPI QPI1 DTX DP 19 QPI QPI1 DP 2 AY8 QPI QPI1 DTX DP 2 AH6 QPI QPI1 DP 3 AV5 GPI QPI1 DTX DP 3 AK6 QPI QPI1 DP 4 BA7 QPI QPI1 DTX DP 4 4 QPI1 DP 5 AY6 QPI QPI1 DTX DP 5 AG7 QPI GPI1 6 AUT QPI QPI1 DTX DP 6 AJ3 QPI QPI1 DP 7 AW4 GPI QPI1 DTX DP 7 AK1 QPI QPI1 DP 8 AUA QPI QPI1 DTX DP 8 AH3 QPI QPI1 DP 9 AT3 QPI QPI1 DTX DP 9 AH2 QPI QPI1 DTX QPI DBR AF10 Asynch QPI1 DTX DNI 1 AJ7 QPI _ 0 AA8 Analog QPI1 DTX DN 10 AF3 QPI _ 1 7 Analog QPI1 DTX DN 11 AD1 QPI DDR COMP 2 AC1 Analog GPI1 DTX DN 12 AD3 GPI DDR_THERM AB5 CMOS QPI1 DTX DN 13 AB3 QPI DDR VREF L23 Analog QPI1 DTX DN 14 AE4 QPI DDRO BA 0 B16 CMOS QPI1 DTX DN 15 AD4 QPI DDRO BA 1 A16 CMOS QPI1 DTX DN 16 AC6 QPI DDRO BA 2 C28 CMOS QPI1 DTX DN 17 AD7 QPI DDRO_CAS C12 CMOS QPI1 DTX DN 18 AES QPI DDRO CKE 0 C29 CMOS QPI1 DTX DN 19 AD8 GPI DDRO CKE 1 A30 CMOS QPI1 DTX DNI2 AJ6 QPI DDRO CKE 2 B30 CMOS QPI1 DTX DNI3 AK5 QPI DDRO CKE 3 B31 CMOS QPI1 DTX DNIA AK4 QPI DDRO CLK N O0 K19 CLOCK QPI1 DTX DN 5 AG6 QPI DDRO CLK N 1 C19 CLOCK
142. en worse it may receive corrupt data if this MbxGet command so happens to be interleaved with an MbxSend from another process Please refer to Table 6 24 for more information regarding failed completion codes from MbxGet commands Timeouts are undesirable and the best way to avoid them and guarantee valid data is for the originating agent to always issue MbxGet commands immediately following MbxSend commands Alternately mailbox timeout can be disabled BIOS may write MSR MISC POWER MGMT 0x1AA bit 11 to Ob1 in order to force a disable of this automatic timeout Response Latency The PECI mailbox interface is designed to have response data available within plenty of margin to allow for back to back MbxSend and MbxGet requests However under rare circumstances that are out of the scope of this specification it is possible that the response data is not available when the MbxGet command is issued Under these circumstances the MbxGet command will respond with an Abort FCS and the originator should re issue the MbxGet request Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel 6 3 3 Table 6 25 Table 6 26 6 3 4 6 3 4 1 6 3 4 2 Table 6 27 Multi Domain Commands The Intel Xeon processor 5500 series does not support multiple domains but it is possible that future products will and the following tables are included as a reference for domain specific def
143. ent without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state to determine that the VTT voltage is stable and within specification Note it is not valid for VTTPWRGOOD to be deasserted while VCCPWRGOOD is asserted Vss The processor ground Notes 1 DDR 0 1 2 refers to DDR3 Channel 0 DDR3 Channel 1 and DDR3 Channel 2 2 VID 7 0 is an Input only during Power On Configuration It is an Output signal during normal operation 88 8 Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel 6 6 1 Note 6 1 1 Thermal Specifications Package Thermal Specifications The Intel Xeon processor 5500 series requires a thermal solution to maintain temperatures within operating limits Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This s
144. eries Datasheet Volume 1 33 m n tel Intel Xeon Processors 5500 Series Electrical Specifications Figure 2 6 Load Current Versus Time 95W TDP Processor 1 2 125 0 120 0 115 0 110 0 105 0 100 0 95 0 Sustained Current A 90 0 85 0 80 0 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than 2 Not 1004 tested Specified by design characterization 34 Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications Figure 2 7 Load Current Versus Time 80W TDP Processor 12 105 100 Sustained Current A 8 75 65 0 01 0 1 1 10 Time Duration S 100 1000 Notes 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than lec TDC 2 Not 100 tested Specified by design characterization Intel Xeon Processor 5500 Series Datasheet Volume 1 35 36 m n tel Intel Xeon Processors 5500 Series Electrical Specifications Figure 2 8 Load Current Versus Time 60W TDP Processor 12 8 al 8 Sustained Current A 3 60 55 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or voltage
145. eries Datasheet Volume 1 I ntroduction 1 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Introduction The Intel Xeon Processor 5500 Series is the first generation server workstation multi core processor to implement key new technologies Integrated Memory Controller Point to point link interface based on Intel QuickPath Technology The processor is optimized for performance with the power efficiencies of a low power microarchitecture to enable smaller quieter systems This document provides DC electrical specifications differential signaling specifications pinout and signal definitions package mechanical specifications and thermal requirements and additional features pertinent to implementation and operation of the processor For information on register descriptions refer to the Intel Xeon Processor 5500 Series Datasheet Volume 2 Intel Xeon Processor 5500 Series are multi core processors based on 45 nm process technology The processor family features a range of thermal design power TDP envelopes from 38W TDP up to 130W TDP These processors feature two Intel QuickPath Interconnect point to point links capable of up to 6 4 GT s up to 8 MB of shared cache and an Integrated Memory Controller The processors support all the existing Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 SSE4 The processors support several Advanced Technologies E
146. ers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel com products ht hyperthreading_more htm Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more informatio
147. ess the new transition is deferred until the previous transition completes The processor controls voltage ramp rates internally to ensure smooth transitions Low transition latency and large number of transitions possible per second Processor core including shared cache is unavailable for less than 2us during the frequency transition 8 136 Intel Xeon Processor 5500 Series Datasheet Volume 1 Boxed Processor Specifications n tel 8 8 1 8 1 1 8 1 2 Boxed Processor Specifications I ntroduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The Intel Xeon processor 5500 series will be offered as an Intel boxed processor however the thermal solution will be sold separately Unlike previous generation boxed processors Intel Xeon processor 5500 series boxed processors will not include thermal solution in the box Intel will offer boxed thermal solutions separately through the same distribution channels Please reference Section 8 1 1 Section 8 1 4 for more details on Boxed Processor Thermal Solutions Available Boxed Thermal Solution Configurations Intel will offer three different Boxed Heat Sink solutions to support the boxed Processors Boxed Intel Combo Thermal Solution The Passive Active Combination Heat Sink Solution is intended for processors with a TDP up to 130W in a pedestal or 2U chass
148. essor 5500 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This is represented by a DC shift in the loadline It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the maximum specified VID are not permitted Table 2 8 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 9 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 8 and Table 2 9 Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Table 2 2 Voltage Identification Definition Sheet 1 of 5 Intel Xeon Processor 5500 Series Datasheet Volume 1 VID7 VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc MAX 0 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 0 1 OFF 0 0 0 0 0 0 1 0 1 60000 0 0 0 0 0 0 1 1 1 59375 0 0 0 0 0 1 0 0 1 58750 0 0 0 0 0 1 0 1 1 58125 0 0 0 0 0 1 1 0 1 57500 0 0 0 0 0 1 1 1 1 56875 0 0 0 0 1 0 0 0 1 56250 0 0 0 0 1 0 0 1 1 55625 0 0 0 0 1 0 1 0 1 55000 0 0 0 0 1 0 1 1 1 54375 0 0 0 0 1 1 0 0 1 53750 0 0 0 0 1 1 0 1 1 53125 0
149. essor Current Vcc 80 A 11 Intel Xeon Processor VccPLL 11 A 5500 Series Low Power V 9 A SKU DBQ TDP 60W Vita 6 A Launch FMB 20 Max Processor Current Vcc 80 A 11 Intel Xeon Processor 11 15518 V 9 A TDP 60W E Launch FMB Max Processor Current Vcc 40 A 11 Intel Xeon Processor VccPLL 1 1 A L5508 V 9 A TDP 38W DDO B Launch FMB A 28 Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications n tel Table 2 8 Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Voltage Min Typ Max Unit Notes Plane lcc TDC Thermal Design Vcc 110 A 11 12 Current VccPLL 1 1 A Ippo Intel Xeon Processor V 9 A W5580 130W Vita 6 A Launch FMB 22 Thermal Design Vcc 85 A 11 12 Current 11 Intel Xeon Processor V 9 A 5500 Series Advanced SKU Vita 6 A TDP 95W VTD 22 A Launch FMB Thermal Design Vcc 70 A 11 12 Current VccPLL 11 A Intel Xeon Processor V 9 A 5500 Series Standard Basic SKU Vita 6 A TDP 80W En A Launch FMB Thermal Design Vcc 60 A 11 12 Current VccPLL 11 A Intel Xeon Processor V 9 A 5500 Series Low Power SKU Vita 6 A TDP 60W Vitp 20 A Launch FMB Thermal Design Vcc 60 A 11
150. essor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available Power specifications are defined at all VIDs found in Table 2 2 The Intel Xeon processor 5500 series may be shipped under multiple VIDs for each frequency FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Intel Xeon Processor 5500 Series Standard Basic SKUs Thermal Profile Temperature C Y 0 303 x 451 8 0 5 10 159 20 25 30 33 40 45 90 55 60 65 40 75 80 Power W Notes 1 Intel Xeon processor 5500 series Standard Basic SKUs processor Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 7 for discrete points that constitute the thermal profile 2 Implementation of Intel Xeon processor 5500 series Standard Basic SKUs Thermal Profile should result in virtually no TCC activation 3 Refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide for system and environmental implementation details 95 Table 6 7 96 intel Thermal Specifications I ntel Xeon Processor 5500 Series Standard Basic SKUs Thermal Profile Power W TcasE
151. f functions Details can be found in Table 2 5 and the applicable platform design guide All Asynchronous Processor Sideband signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Table 2 17 for DC specifications System Reference Clock The processor core processor uncore Intel QuickPath Interconnect link and DDR3 memory interface frequencies are generated from BCLK DP and BCLK DN signals There is no direct link between core frequency and Intel QuickPath Interconnect link frequency e g no core frequency to Intel QuickPath Interconnect multiplier The processor maximum core frequency Intel QuickPath Interconnect link frequency and Intel Xeon Processor 5500 Series Datasheet Volume 1 m e Intel Xeon Processors 5500 Series Electrical Specifications n te D 2 1 6 Note Note 2 1 7 Table 2 1 DDR3 memory frequency are set during manufacturing It is possible to override the processor core frequency setting using software This permits operation at lower core frequencies than the factory set maximum core frequency The processor core frequency is configured during reset by using values stored within the device during manufacturing The stored value sets the lowest core multiplier at which the particular processor can operate If higher speeds are desired the appropriate ratio can be configured via the 2 PERF MSR C
152. fications 44 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include 1 Package reference with tolerances total height length width etc IHS parallelism and tilt Land dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm N OO uU E UN Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the TMDG Intel Xeon Processor 5500 Series Datasheet Volume 1 intel Package Mechanical Specifications Processor Package Drawing Sheet 1 of 2 Figure 3 2 Y 5 9 1 8 15 I9 own Yos 100 00 aum 9 921914 ao is isi ONIMVEC SLW3 401337044 TION WAL I ERT n sei TIN MI SOLON was
153. finition GetDI B The processor PECI client implementation of GetDIB includes an 8 byte response and provides information regarding client revision number and the number of supported domains All processor PECI clients support the GetDIB command Command Format The GetDIB format is as follows Write Length 1 Read Length 8 Command Oxf7 Intel Xeon Processor 5500 Series Datasheet Volume 1 109 n tel Thermal Specifications Figure 6 11 GetDI B Byte Write Length Read Length Cmd Code Byte Client Address 0x01 0x08 Oxf7 Definition Revision Device Info Number Reserved Reserved Reserved 10 11 12 13 Reserved Reserved Reserved FCS 6 3 2 2 2 Device I nfo The Device Info byte gives details regarding the PECI client configuration At a minimum all clients supporting GetDIB will return the number of domains inside the package via this field With any client at least one domain Domain 0 must exist Therefore the Number of Domains reported is defined as the number of domains in addition to Domain 0 For example if the number 061 is returned that would indicate that the PECI client supports two domains Figure 6 12 Device I nfo Field Definition 76543210 Reserved of Domains Reserved 6 3 2 2 3 Revision Number All clients that support the GetDIB command also support Revision Number reporting The revision number may be used by
154. for these processors have been developed based on Intel s reliability goals at a reference use condition In addition the processor validation and production test conditions have been optimized based on these conditions Operating Workstation processors in a server environment or other application could impact reliability performance which means Intel s reliability goals may not be met For further details on use condition assumptions or reliability performance please refer to the latest Product Release Qualification PRQ Report available via your Customer Quality Engineer CQE contact NEBS Network Equipment Building System NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States Intel Xeon Processor 5500 Series Datasheet Volume 1 11 References Introduction Platform designers are strongly encouraged to maintain familiarity with the most up to date revisions of processor and platform collateral Table 1 2 References Document Location Notes AP 485 Intel Processor Identification and the CPUID Instruction 241618 1 1 Intel 64 and IA 32 Architecture Software Developer s Manual 253665 Volume 1 Basic Architecture 253666 Volume 2A Instruction Set Reference A M 253667 Volume 2B Instruction Set Reference N Z 253668 Volume 3A System Programming Guide Part 1 253669 Volume 3B Systems Programming Guide
155. from the installed processors any processor whose set of feature flags exactly matches the AND ed feature flags can be selected by the BIOS as the BSP If no processor exactly matches the AND ed feature flag values then the processor with the numerically lower CPUID should be selected as the BSP 6 Intel requires that the proper microcode update be loaded on each processor operating within the system Any processor that does not have the proper microcode update loaded is considered by Intel to be operating out of specification 7 Customers are fully responsible for the validation of their system configuration Flexible Motherboard Guidelines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the Intel Xeon Processor 5500 Series will have over certain time periods The values are only estimates and actual specifications for future processors may differ Processors may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future Intel Xeon Processor 5500 Series Absolute Maximum and Minimum Ratings Table 2 7 specifies absolute maximum and minimum ratings which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maxi
156. general response policies may be based on that limited information Originator Responses The simplest policy that an originator may employ in response to receipt of a failing completion code is to retry the request However certain completion codes or FCS responses are indicative of an error in command encoding and a retry will not result in a different response from the client Furthermore the message originator must have a response policy in the event of successive failure responses Please refer to the definition of each command in Section 6 3 2 for a specific definition of possible command codes or FCS responses for a given command The following response policy definition is generic and more advanced response policies may be employed at the discretion of the originator developer Originator Response Guidelines Response After 1 Attempt After 3 attempts Bad FCS Retry Fail with PECI client device error Abort FCS Retry Fail with PECI client device error May be due to illegal command codes CC Fail Retry Either the PECI client doesn t support the current command code or it has failed in its attempts to construct a response None all O s Force bus idle Fail with PECI client device error Client may be dead or otherwise non 1ms low retry responsive in RESET or S1 for example CC Pass Pass n a Good FCS Pass n a Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Spe
157. i Domain 5 4 nnns 125 6 3 4 Client RESPONSES cce rte kuni kas skio d n i is D KK age te is 125 6 3 5 Originator Sira wan x vate i RE PvE dE 126 0 3 06 Temperature h na ani aa ROSE A XU RO i ROCA REC aa a c ka 127 6 3 7 Client Managemeht ioca sere messe tta exor interpr i n dhana 128 DEN m CEN NE RU CREE 131 7 1 Power On Configuration 71 1 4 1 016 131 7 2 Clock Control Low Power 201 24 2 110 132 7 2 1 Thread and Core Power State Descriptions 133 7 2 2 Package Power State 134 7 2 3 Intel Xeon Processor 5500 Series C State Power Specifications 135 7 3 States use utet aa up i E aa i a 136 7 4 Intel Turbo Boost 1 ene n enn 136 7 5 Enhanced Intel SpeedStep Technology cesee Hee 136 Boxed Processor 5 5 2 21 4 424 137 8L
158. initions Domain 10 Definition Domain ID Domain Number 0501 0 0b10 Multi Domain Command Code Reference Command Name 0 n GetTemp 0x01 0x02 PCI ConfigRd OxC1 0 2 PCI ConfigWr OxC5 0xC6 MbxSend OxD1 OxD2 MbxGet OxD5 OxD6 Client Responses Abort FCS The Client responds with an Abort FCS under the following conditions The decoded command is not understood or not supported on this processor this includes good command codes with bad Read Length or Write Length bytes Data is not ready Assured Write FCS AW FCS failure Note that under most circumstances an Assured Write failure will appear as a bad FCS However when an originator issues a poorly formatted command with a miscalculated AW FCS the client will intentionally abort the FCS in order to guarantee originator notification Completion Codes Some PECI commands respond with a completion code byte These codes are designed to communicate the pass fail status of the command and also provide more detailed information regarding the class of pass or fail For all commands listed in Section 6 3 2 that support completion codes each command s completion codes is listed in its respective section What follows are some generalizations regarding completion codes An originator that is decoding these commands can apply a simple mask to determine pass or fail Bit 7 is always set on a failed comman
159. ion 3 HERI Because a particular MbxSend command may specify an update to potentially critical registers inside the processor it includes an Assured Write FCS AW FCS byte as part of the write data payload In the event that the AW FCS mismatches with the client calculated FCS the client will abort the write and will always respond with a bad Write FCS 6 3 2 7 2 Command Format The MbxSend format is as follows Write Length 7 Read Length 1 Command 0xd1 Multi Domain Support Yes see Table 6 26 Description Deposits the Request Type and associated 4 byte data in the Mailbox interface and returns a completion code byte with the details of the execution results Refer to Section 6 3 4 2 for completion code definitions Figure 6 24 MbxSend Byte 0 1 2 3 Byte Write Length Read Length Cmd Code Definition Client Address 0x01 0xd1 4 5 6 7 8 Reguest Type LSB Data 31 0 MSB 9 10 11 12 AW FCS FCS EODD FCS Code Intel Xeon Processor 5500 Series Datasheet Volume 1 121 n tel Thermal Specifications Note that the 4 byte data defined above is sent in standard PECI ordering with LSB first and MSB last Table 6 23 MbxSend Response Definition 6 3 2 8 6 3 2 8 1 6 3 2 8 2 122 Response Meaning Bad FCS Electrical error CC 0x4X Semaphore is granted with a Transaction ID of X CC 0x80 Error causing a response timeout Either due to a rare internal timing
160. ion must be terminated on the system board using precision resistor QPIO CLKRX DN Intel amp QuickPath Interconnect received clock is the input clock that corresponds QPIO CLKRX DP to Intel QuickPath Interconnect portO received data QPIO CLKTX DN O Intel QuickPath Interconnect forwarded clock sent with Intel QuickPath QPIO CLKTX DP Interconnect port 0 outbound QPIO COMP Must be terminated on the system board using precision resistor QPIO DRX DN 19 0 QPIO DRX DN 19 0 QPIO DP 19 0 comprise the differential receive QPIO DRX DP 19 0 data for Intel QuickPath Interconnect 0 The inbound 20 lanes are connected Y to another component s outbound lanes QPIO DTX DN 19 0 O QPIO DTX DN 19 0 and QPIO DTX DP 19 0 comprise the differential transmit QPIO DTX DP 19 0 data for Intel QuickPath Interconnect 0 The outbound 20 lanes are connected to another component s inbound lanes QPI1 CLKRX DN Intel QuickPath Interconnect received clock is the input clock that corresponds to QPI1 CLKRX DP Intel QuickPath Interconnect 1 port received data QPI1_CLKTX_DN O Intel QuickPath Interconnect forwarded clock sent with Intel QuickPath QPI1 CLKTX DP Interconnect port1 outbound data 1 COMP Must be terminated the system board using precision resistor QPI1 DRX DN 19 0 1 QPI1 DRX DN 19 0 and 1 DP 19 0 comprise the differential receive QPI1 DRX DP 19 0 data for In
161. ions Figure 6 4 Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile 74 12 70 68 5 66 64 62 5 Y 0 302 x 51 9 60 58 56 54 52 50 10 15 20 25 30 35 40 45 50 55 60 Power W Notes 1 Intel Xeon processor 5500 series Low Power SKU Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 9 for discrete points that constitute the thermal profile 2 Implementation of Intel Xeon processor 5500 series Low Power SKU Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet Intel Xeon processor 5500 series Low Power SKU Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss 3 Refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 5500 Series Datasheet Volume 1 97 intel Thermal Specifications Table 6 9 Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile Power W TcasE Max CC 0 51 9 5 53 4 10 54 9 15 56 4 20 57 9 25 59 5 30 61 0 35 62 5 40 64 0 45 65 5 50 67 0 55 68 5 60 70 0 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to
162. is always guaranteed to be operational under SO and S1 sleep states Under S3 and deeper sleep states the PECI client response is undefined and therefore unreliable PECI Client Response During S1 Command Response Ping Fully functiona GetDIB Fully functiona GetTemp Fully functiona PCI ConfigRd Fully functiona PCI ConfigWr Fully functiona MbxSend Fully functiona MbxGet Fully functiona Processor Reset The Intel Xeon processor 5500 series PECI client is fully reset on all RESET assertions Upon deassertion of RESET where power is maintained to the processor otherwise known as a warm reset the following are true The PECI client assumes a bus Idle state The Thermal Filtering Constant is retained PECI Node ID is retained GetTemp reading resets to 0x0000 Any transaction in progress is aborted by the client as measured by the client no longer participating in the response The processor client is otherwise reset to a default configuration Intel Xeon Processor 5500 Series Datasheet Volume 1 Features 7 7 1 Table 7 1 intel Features Power On Configuration POC Several options can be configured by hardware Power On configuration POC functionality is provided by strapping VID signals see Table 2 3 or sampled on the active to inactive transition of RESET Z For specifics on these options please refer to Table 7 1 Plea
163. is with appropriate ducting Boxed Intel Active Thermal Solution The Active Heat Sink Solution is intended for processors with a TDP of 80W or lower in pedestal chassis Boxed Intel Passive Thermal Solution The 25 5mm tall Passive Heat Sink Solution is intended for processors with a TDP of 95W or lower in Blades 1U or 2U chassis with appropriate ducting An Intel Combo Boxed Passive Active Combination Heat Sink Solution The Passive Active combination solution based on a 2U passive heat sink with a removable fan is intended for use with processors with TDP s up to 130 W This heat pipe based solution is intended to be used as either a passive heat sink in a 2U or larger chassis or as an active heat sink for pedestal chassis Figure 8 2 and Figure 8 3 are representations of the heat sink solution Although the active combination solution with the removable fan installed mechanically fits into a 2U keepout its use has not been validated in that configuration The Passive Active combination solution in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present The Passive Active combination solution with the fan removed as with any passive thermal solution will require the use of chassis ducting and are targeted for use in rack mount or ducted pedestal servers The retention solution used for these products is called Unified Retention System URS
164. itoring registers within the processor s PCI configuration space It also provides insight into thermal monitoring functions such as TCC activation timers and thermal error logs The exact list of RAS related registers in the PCI configuration space can be found in the Intel Xeon Processor 5500 Series Datasheet Volume 2 Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel 6 3 1 3 6 3 2 6 3 2 1 6 3 2 1 1 Figure 6 9 Figure 6 10 6 3 2 2 6 3 2 2 1 Processor nterface Tuning and Diagnostics Intel Xeon processor 5500 series Intel IBIST allows for in field diagnostic capabilities in Intel QuickPath Interconnect and memory controller interfaces PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities Client Command Suite Ping Ping is a required message for all PECI devices This message is used to enumerate devices or determine if a device has been removed been powered off etc A Ping sent to a device address always returns a non zero Write FCS if the device at the targeted address is able to respond Command Format The Ping format is as follows Write Length 0 Read Length 0 Ping Byte 0 1 2 3 Write Length Read Length 0x00 0x00 pies Byte Client Address Definition An example Ping command to PECI device address 0x30 is shown below Ping Example Byte 0 1 2 3 De
165. lock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK DP BCLK DN input with exceptions for spread spectrum clocking Test Access Port TAP Signals Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TDO TMS and TRST Two copies of each signal may be required with each driving a different voltage level Processor TAP signal DC specifications can be found in Table 2 17 While TDI TMS and TRST do not include On Die Termination ODT these signals are weakly pulled up via 1 5 resistor to V3 While TCK does not include ODT this signal is weakly pulled down via a 1 5 kQ resistor to Vss Power Other Signals Processors also include various other signals including power ground sense points and analog inputs Details can be found in Table 2 5 and the applicable platform design guide Table 2 1 outlines the required voltage supplies necessary to support Intel Xeon Processor 5500 Series Processor Power Supply Voltages Power Rail Nominal Voltage Notes T
166. ls on the processor mass Intel Xeon Processor 5500 Series Datasheet Volume 1 Boxed Processor Specifications n tel Figure 8 5 Top Side Baseboard Keep Out Zones THURLEY amp GAINESTOWN ENABLING KEEPIN LEGEND THIS SHEET ONLY gt gt AS VIEWED FROM PRIMARY SIDE OF THE MOTHERBOARD Intel Xeon Processor 5500 Series Datasheet Volume 1 141 m n tel Boxed Processor Specifications Figure 8 6 Top Side Baseboard Mounting Hole Keep Out Zones 7B LEGEND THIS SHEET ONLY AS VIEWED FROM PRIMARY SIDE OF THE MOTHERBOARD DETAILS 142 Intel Xeon Processor 5500 Series Datasheet Volume 1 Boxed Processor Specifications n tel Figure 8 7 Bottom Side Baseboard Keep Out Zones LEGEND THIS SHEET ONLY 000 DETAILS AS VIEWED FROM SECONDARY SIDE OF THE MOTHERBOARD Intel Xeon Processor 5500 Series Datasheet Volume 1 143 m n tel Boxed Processor Specifications Figure 8 8 Primary and Secondar
167. mum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications Table 2 7 intel At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Minimum and Maximum Ratings for sensing Core current consumption Symbol Parameter Min Nominal Max Unit Notes Vcc Processor core voltage with respect to Vss 0 300 1 350 V Processor PLL voltage with respect to Vss 1 800 V 4 VDDQ Processor I O supply v
168. n Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see www intel com Enhanced Intel SpeedStep Technology See the http processorfinder intel com or contact your Intel representative for more information Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order 12 is a two wire communications bus protocol developed by Philips SMBus is a subset of the 12 bus protocol and was developed by Intel Implementations of the 12 bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Intel Xeon Enhanced Intel SpeedStep Technology and the Intel logo are trademarks of Intel Corpo
169. n Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications n tel Table 2 6 2 3 Note Intel Xeon Processor 5500 Series Datasheet Volume 1 Notes 1 Refer to Section 4 for land assignments and Section 5 for signal definitions 2 DDR 0 1 2 refers to DDR3 Channel 0 DDR3 Channell and DDR3 Channel 2 Signals that include on die termination ODT are listed in Table 2 6 Signals With On Die Termination ODT Intel QuickPath Interface Signal Group GPI 1 0 DRX DP 19 0 QPI 1 0 DN 19 0 QPI 1 0 TRX DP 19 0 1 0 TRX DN 19 0 QPI 0 1 CLKRX D N P GPI 0 1 CLKTX D N P DDR3 Signal Group DDR 0 1 2 _DQ 63 0 DDR 0 1 2 _DQS_IN P 17 0 DDR 0 1 2 _ECC 7 0 DDR 0 1 2 _PAR_ERR 2 0 Processor Sideband Signal Group BPM 7 0 10 7 PREQ Test Access Port TAP Signal Group TDI TMS TRST gt Power Other Signal Group VCCPWRGOOD VDDPWRGOOD VITPWRGOOD Notes 1 Unless otherwise specified signals have ODT in the package with a 50 pull down to Vss 2 Unless otherwise specified all DDR3 signals are terminated to 2 3 DDR 0 1 2 _PAR_ERR 2 0 are terminated to 4 does not include ODT this signal is weakly pulled down via 1 5 resistor to 5 TDI TMS TRST do not include ODT these signals are weakly pulled up via 1 5kQ resistor
170. n under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the appropriate platform design guide and for details on implementing the bi directional PROCHOT feature THERMTRI P Signal Regardless of whether Adaptive Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 THERMTRIP activation is independent of processor activity and does not generate any Intel QuickPath Interconnect transactions The temperature at which THERMTRIP asserts is not user configurable and is not software visible Platform Environment Control Interface The Platform Environment Control Interface PECI uses a single wire for self clocking and data transfer The bus requires no additional control lines The physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a logic 0 or logic 1 also includes variable data transfer rate established with every message In this way it is highly flexible even though underlying logic is simple The interface design was optimized for interfacing to Intel processor and chi
171. o the monitored address if the state was entered via the MWAIT instruction RESET will cause the processor to initialize itself and return to CO A System Management Interrupt SMI handler will return execution to either Normal state or the C1 C1E state See the Intel 64 and 32 Architectures Software Developer s Manual Volume III System Programmer s Guide for more information While in C1 C1E state the processor will process bus snoops and snoops from the other threads To operate within specification BIOS must enable the CIE feature for all installed processors C3 State Individual threads of the processor can enter the state by initiating a P LVL2 I O read to the P BLK or an MWAIT C3 instruction Before entering core C3 the core flushes the contents of its caches Except for the caches the processor core maintains all its architectural state while in the C3 state All of the clocks in the processor core are stopped in the C3 state Because the core s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the Intel QuickPath Interconnect Link or when another logical processor in the same package accesses cacheable memory The processor core will transition to the CO state upon occurrence of an interrupt RESET will cause the processor core to initialize itself C6 State Individual threads of the processor can enter the C6 state by initiating a P LVL3 read to the P BLK
172. ocks on 62 5 clocks off 0x4 50 clocks on 50 clocks off 0x5 62 5 clocks on 37 5 clocks off 0x6 75 clocks on 25 clocks off 0x7 87 5 clocks on 12 5 clocks off The T state control word is defined as follows Figure 6 22 ACPI T state Throttling Control Read Write Definition 6 3 2 7 6 3 2 7 1 120 Byte 0 1 2 3 4 Request Type Request Data r lI 1 7 7 543 10 Data Reserved Enable Duty Cycle MbxSend The MbxSend command is utilized for sending requests to the generic Mailbox interface Those requests are in turn serviced by the processor with some nominal latency and the result is deposited in the mailbox for reading MbxGet is used to retrieve the response and details are documented in Section 6 3 2 8 The details of processor mailbox capabilities are described in Section 6 3 2 6 1 and many of the fundamental concepts of Mailbox ownership release and management are discussed in Section 6 3 2 9 Write Data Regardless of the function of the mailbox command a request type modifier and 4 byte data payload must be sent For Mailbox commands where the 4 byte data field is not applicable e g the command is a read the data written should be all zeroes Intel Xeon Processor 5500 Series Datasheet Volume 1 m Thermal Specifications n tel Figure 6 23 MbxSend Command Data Format Byte 0 1 2 3 4 Definit
173. of the command and address DDR 0 1 2 _DQ 63 0 1 0 DDR3 Data bits DDR 0 1 2 _DQS_N 17 0 Differential pair Data ECC Strobe Differential strobes latch data ECC for each DDR 0 1 2 DQS P 17 0 DRAM Different numbers of strobes are used depending on whether the E connected DRAMs are x4 x8 Driven with edges in center of data receive edges are aligned with data edges DDR 0 1 2 _ECC 7 0 Check Bits An Error Correction Code is driven along with data on these lines for DIMMs that support that capability DDR 0 1 2 _MA 15 0 O Selects the Row address for Reads and writes and the column address for activates Also used to set values for DRAM configuration registers DDR 0 1 2 MA PAR O Odd parity across Address and Command DDR 0 1 2 ODT 3 0 O Enables various combinations of termination resistance in the target and non target DIMMs when data is read or written DDR 0 1 Parity Error detected by Registered DIMM one for each DIMM 2 PAR ERRZ 2 0 DDR 0 1 2 RAS O Row Address Strobe DDR 0 1 2 RESET Resets DRAMs Held low on power up held high during self refresh otherwise controlled by configuration register DDR VREF Voltage reference for DDR3 DDR 0 1 2 _WE O Write Enable GTLREF Voltage reference for GTL signals ISENSE Current sense for VRD11 1 PECI 1 0 PECI Platform Environment Control Interface is the serial sideband interface to the processor and is used primarily for thermal power and err
174. oltage for DDR3 1 500 V 4 with respect to Vss Processor uncore analog voltage with 0 825 1 350 V 3 respect to Vss VTD Processor uncore digital voltage with 0 825 1 350 V 3 respect to Vss TcasE Processor case temperature See See Section 6 Section 6 TsroRAGE Storage temperature 40 85 5 6 7 V sENSE Analog input voltage with respect to Vss 0 30 1 150 V Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Vrr and Vro should be derived from the same voltage regulator VR 4 5 tolerance 5 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 6 This rating applies to the processor and does not include any tray or packaging 7 Failure to adhere to this specification can affect the long term reliability of the processor Intel Xeon Processor 5500 Series Datasheet Volume 1 27 Intel Xeon Processors 5500 Series Electrical Specifications 2 6 Processor DC Specifications DC specifications are defined at the processor pads
175. olume 1 Thermal Specifications n tel Figure 6 2 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile B 80 TCASE_MAX is a thermal solution design point In actuality units will not significantly exceed TCASE MAX A due to TCC activation 75 74 Thermal Profile B 5 Y 0 244 p 57 8 6 ES Thermal Profile A Y 0 181 57 8 LE 4 50 45 4 0 5 0 HAA 30 3547 45 5 006 7075 88 9 9 Power M Notes 1 Intel Xeon processor 5500 series Advanced SKU Thermal Profile is representative of a volumetrically unconstrained platform Please refer to Table 6 4 for discrete points that constitute thermal profile A 2 Implementation of Intel Xeon processor 5500 series Advanced SKU Thermal Profile A should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet Profile A will result in increased probability of TCC activation and may incur measurable performance loss 3 Intel Xeon processor 5500 series Advanced SKU Thermal Profile B is representative of a volumetrically constrained platform Please refer to Table 6 5 for discrete points that constitute thermal profile B 4 Refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 5500 Series Datasheet Volume 1 93 n tel Thermal Specifications Table
176. on Processor 5500 Series Datasheet Volume 1 31 intel Intel Xeon Processors 5500 Series Electrical Specifications Figure 2 4 Vcc Overshoot Example Waveform 2 6 2 32 Example Overshoot Waveform VID 0 050 Vos 2 o Ss o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID Notes 1 Vos is the measured overshoot voltage 2 Togs is the measured time duration above VID Die Voltage Validation Core voltage Vcc overshoot events at the processor must meet the specifications in Table 2 10 when measured across the VCC_SENSE and VSS_ SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications Figure 2 5 Load Current Versus Time 130W TDP Processor 12 155 150 145 140 135 130 125 Sustained Current A 120 115 110 105 0 01 0 1 1 10 Time Duration s 100 1000 Notes 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than lc C 2 Not 10096 tested Specified by design characterization Intel Xeon Processor 5500 S
177. on since the processor is operating out of specification at this temperature Therefore the readings are never positive 6 3 6 3 Temperature Filtering The processor digital thermal sensor DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals Coupled with the fact that typical fan speed controllers may only read temperatures at 4 Hz it is necessary for the thermal readings to reflect thermal trends and not instantaneous readings Therefore PECI supports a configurable low pass temperature filtering function By default this filter results in a thermal reading that is a moving average of 256 samples taken at approximately 1msec intervals This filter s depth or smoothing factor may be configured to between 1 sample and 1024 samples in powers of 2 See the equation below for reference where the configurable variable is X Ty Ty 1 1 2 1 Please refer to Section 6 3 2 6 7 for the definition of the thermal configuration command Intel Xeon Processor 5500 Series Datasheet Volume 1 127 n tel Thermal Specifications 6 3 6 4 Table 6 30 6 3 7 6 3 7 1 Table 6 31 128 Reserved Values Several values well out of the operational range are reserved to signal temperature sensor errors These are summarized in the table below Error Codes and Descriptions Error Code Description
178. ones Do not contact the Test Pad Area with conductive material Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 3 2 and Figure 3 3 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in 3 1 3 Package Loading Specifications Table 3 1 provides load specifications for the processor package These maximum limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Exceeding these limits during test may result in component failure The processor substrate should not be used as a mechanical reference or load bearing surface for thermal solutions Table 3 1 Processor Loading Specifications Parameter Maximum Notes Static Compressive Load 890 N 200 Ibf 1 2 3 5 Dynamic Compressive Load 1779 N 400 Ibf max static 1 3 4 5 compressive dynamic load Notes 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum static force that can be applied by the heatsink and Independent Loading Mechanism ILM 3 These specifications are based on limited testing for design characterization Loading limits are for the package constrained by the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimpos
179. or an MWAIT C6 instruction Before entering core C6 the processor saves it state The processor achieves additional power savings in the core C6 state Package Power State Descriptions The package supports CO C1 CIE C3 and C6 power states The package power state is automatically resolved by the processor depending on the core power states and permission from the rest of the system as described below Package CO State This is the normal operating state for the processor The processor remains in the Normal state when at least one of its cores is in the CO or C1 state or when another component in the system has not granted permission to the processor to go into a low power state Individual components of the processor may be in low power states while the package in CO Package 1 State The package will enter the C1 C1E low power state when at least one core is in the C1 C1E state and the rest of the cores are in the C1 C1E or lower power state The processor will also enter the C1 C1E state when all cores are in a power state lower Intel Xeon Processor 5500 Series Datasheet Volume 1 Features 7 2 2 3 7 2 2 4 7 2 3 7 3 intel than C1 C1E but the package low power state is limited to 1 the CST CONFIG CONTROL MSR In the CIE state the processor will automatically transition to the lowest power operating point lowest supported voltage and associated frequency When entering
180. or management PECI_ID ID is the client address identifier Assertion of this pin results in a PECI client address of 0x31 versus the default 0x30 client address This pin is primarily useful for PECI client address differentiation in DP platforms One of the two processors must be pulled down to VSS to strap to the address of 0x31 PRDY PRDY is processor output used by debug tools to determine processor debug readiness PREQ 1 0 PREQ is used by debug tools to request debug operation of the processor PROCHOT 1 0 PROCHOT will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal can also be driven to the processor to activate the Thermal Control Circuit If PROCHOT is asserted at the deassertion of RESET the processor will tri state its outputs This signal does not have on die termination and must be terminated on the system board 86 Intel Xeon Processor 5500 Series Datasheet Volume 1 Signal Definitions Table 5 1 intel Signal Definitions Sheet 3 of 4 PSI Name Type O Description Processor Power Status Indicator signal This signal is asserted when maximum possible processor core current consumption is less than 20A Assertion of this signal is an indication that th
181. or temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI as described in Section 6 3 If PECI is less than TCONTROL then the case temperature is permitted to exceed the Thermal Profile but PECI must remain at or below TCONTROL If PECI gt TCONTROL then the case temperature must meet the Thermal Profile The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 6 2 Processor Thermal Features Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications Intel Xeon Processor 5500 Series Datasheet Volume 1 89 n tel Thermal Specifications The Intel Xeon Processor W5580 see Figure 6 1 Table 6 2 supports a single Thermal Profile For this processor it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to the Intel Xeon Processor 5500 Series Thermal Mechanical Design Guide TMDG for details on system thermal solution design the
182. ough to meet the Power On Configuration Hold Time PROCHOT Failure to do so may result in false tri state Intel Xeon Processor 5500 Series Datasheet Volume 1 131 intel aa Figure 7 1 7 2 Note 132 PROCHOT POC Timing Requirements Min Setup 2 Min Hold 106 BCLK CPURESET Tri State POC xxPROCHOT Non FRB assertion of xxPROCHOT during this window can trigger false tri state xxPROCHOT deassertion is not required for FRB Power On Configuration POC logic levels are MUX ed onto the VID 7 0 signals with 1 5 KQ pull up and pull down resistors located on the baseboard These include VID 2 0 MSID 2 0 Market Segment ID VID 5 3 CSC 2 0 Current Sense Configuration VID 6 Reserved VID 7 VR11 1 Select Pull up and pull down resistors on the baseboard eliminate the need for timing specifications After the voltage regulator s OUTEN signal is asserted the VID 7 0 CMOS drivers typically 500 up down impedance override the POC pull up down resistors located on the baseboard and drive the necessary VID pattern Please refer to Table 2 3 for further details Clock Control and Low Power States The processor supports low power states at the individual thread core and package level for optimal power management The processor implements software interfaces for requesting low power states MWAIT instruction extensions with sub state hints
183. ower on Reset Vcc sENSE Vss SENSE Vcc sense and Vss sense provide an isolated low impedance connection to the processor core voltage and ground They can used to sense or measure power near the silicon with little noise Power for processor core VCCPWRGOOD VCCPWRGOOD Power Good is processor input The processor requires this signal to be a clean indication that BCLK Vcc VrrA supplies stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state VCCPWRGOOD can be driven inactive at any time but BCLK and power must again be stable before a subsequent rising edge of VCCPWRGOOD In addition at the time VCCPWRGOOD is asserted RESET must be active The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Analog Power for Clocks VDDQ Power supply for the DDR3 interface Intel Xeon Processor 5500 Series Datasheet Volume 1 87 intel Table 5 1 Signal Definitions Signal Definitions Sheet 4 of 4 Name VIT VID 4 2 Type O Description VTT_VID 4 2 i
184. pset components in both single processor and multiple processor environments The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information The PECI bus offers A wide speed range from 2 Kbps to 2 Mbps CRC check byte used to efficiently and atomically confirm accurate data delivery Synchronization at the beginning of every message minimizes device timing accuracy requirements Note that the PECI commands described in this document apply to the I ntel Xeon processor 5500 series only Refer to Table 6 14 for the list of PECI commands supported by the Xeon processor 5500 series PECI client Intel Xeon Processor 5500 Series Datasheet Volume 1 107 n tel Thermal Specifications Table 6 14 Summary of Processor specific PECI Commands 6 3 1 6 3 1 1 6 3 1 2 108 Command Supported on Intel Xeon Processor 5500 Series CPU Ping Yes GetDI B Yes GetTemp Yes PCI ConfigRd Yes PCI ConfigWr Yes MbxSend 1 Yes MbxGet Yes Note 1 Refer to Taaie 6 19 for a summary of mailbox commands supported by the Intel Xeon processor 5500 PECI Client Capabilities The Intel Xeon processor 5500
185. r use with boxed processors that have TDP s of 95 W and lower The 25 5 mm Tall passive solution is designed to be used in Blades 1U and 2U chassis where ducting is present The use of a 25 5 mm Tall heatsink in a 2U chassis is recommended to achieve a lower heatsink Tj A and a more optimized heatsink design Figure 8 4 is a representation of the heat sink solution The retention solution used for these products is called Unified Retention System URS Intel Xeon Processor 5500 Series Datasheet Volume 1 139 n tel Boxed Processor Specifications 140 Mechanical Specifications This section documents the mechanical specifications of the boxed processor solution Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones The boxed processor and boxed thermal solution will be sold separately Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling Baseboard keepout zones are shown in Figure 8 5 through Figure 8 8 Physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8 9 Mechanical drawings for the 4 pin fan header and 4 pin connector used for the active fan heat sink solution are represented in Figure 8 11 and Figure 8 12 None of the heat sink solutions exceed a mass of 550 grams Note that this is per processor a dual processor system will have up to 1100 grams total mass in the heat sinks See Section 3 for detai
186. ration in the United States and other countries Other brands and names are the property of their respective owners Copyright O 2009 Intel Corporation 2 Intel Xeon Processor 5500 Series Datasheet Volume 1 Contents 1 e siai i i ia ae i EA REET 9 1 1 TERMINOLOGY 555556 ais aa E a a a n o wn 10 1 2 References TT 12 2 Intel Xeon Processors 5500 Series Electrical Specifications 13 2 1 ay SIQNALING 13 2 1 Intel QuickPath eese 13 2 1 gt 13 2 1 3 Platform Environmental Control Interface 14 2 1 4 Processor Sideband 510 lt kk kaka 14 2 1 5 System Reference 222 14 2 1 6 Test Access Port 5 1 4 nnns 15 2 1 7 Power Other 5 0 2 2 2 sese meminisse 15 2 1 8 Reserved or Unused Signals sss 23 2 2 Signal Group Sumimary se RES RE RR EE E RR ERE RE Ed MERE 23 2 3 Mixing Processor S us koxa ake ke w n ka oya iai i NIRE MATER ssid i i a i nA Ahaa Aa n 25 2 4 Flexible Motherboard Guidelines FMB
187. rmal profiles and environmental considerations The Intel Xeon processor 5500 series Advanced SKU supports two thermal profiles either of which can be implemented Both ensure adherence to Intel reliability requirements Thermal Profile A see Figure 6 2 Table 6 4 is representative of a volumetrically unconstrained thermal solution that is industry enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Thermal Profile B see Figure 6 2 Table 6 5 is indicative of a constrained thermal environment that is 1U form factor Because of the reduced cooling capability represented by this thermal solution the probability of TCC activation and performance loss is increased Additionally utilization of a thermal solution that does not meet Thermal Profile B will violate the thermal specifications and may result in permanent damage to the processor Refer to this processor s TMDG for details on system thermal solution design thermal profiles and environmental considerations The upper point of the thermal profile consists of the Thermal Design Power TDP and the associated value It should be noted that the upper point associated with the Intel Xeon processor 5500 series Advanced SKU Thermal Profile B x TDP and y Tcase TDP represents a thermal solution design point In actuality
188. rocessor Sideband Buffer 10 18 On Resistance lu Input Leakage Current x 200 4 Notes Unless otherwise noted all specifications in this table apply to all processor frequencies The V a referred to in these specifications refers to instantaneous Based on a test load of 50 Q to Vrra For between 0 V and Measured when the driver is tristated Vin Voymay experience excursions above Rsys Term is the termination on the system and is not controlled by the Intel Xeon Processor 5500 Series LNB BN Table 2 16 PWRGOOD Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage for 0 25 Vita V 2 3 VTTPWRGOOD and VCCPWRGOOD signals Input Low Voltage for 0 29 V 3 VDDPWRGOOD signal Vin Input High Voltage for 0 75 Vita V 2 3 VTTPWRGOOD and VCCPWRGOOD signals Vin Input High Voltage for 0 87 V 3 VDDPWRGOOD signal ODT On Die Termination 45 55 Ron Processor Sideband Buffer 10 18 Q On Resistance lu Input Leakage Current x 200 uA 4 Notes Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The V a referred to in these specifications refers to instantaneous 3 Based on a test load of 50 O to Vra 4 For between 0 V V ra Measured when the driver is tristated 5 Vin experience excursions above Intel Xeon Processor 5
189. rr and max loadlines represent static and transient limits Each is characterized by 31 5 mV offset from Vr 4 The loadlines specify voltage limits at the die measured at the VITD SENSE and VSS SENSE VTTD lands Voltage regulation feedback for regulator circuits must also be taken from VTTD_SENSE and VSS_SENSE_VTTD lands 38 Intel Xeon Processor 5500 Series Datasheet Volume 1 Intel Xeon Processors 5500 Series Electrical Specifications Figure 2 10 Static and Transient Tolerance Loadlines 0 0500 4 0 0375 4 0 0250 5 0 0125 5 0 0000 4 0 0125 4 0 0250 4 0 0375 4 0 0500 4 0 0625 4 0 0750 4 0 0875 4 0 1000 4 1125 4 1250 4 375 4 500 4 625 4 1750 4 0 1875 4 0 2000 4 0 2125 VTT VID Devlatlon 65502525256 In rr A 15 20 Notes 1 The Vt min and Vyr max loadlines represent static and transient limits Each is characterized by a 31 5 mV offset from Vr typ 2 Refer to Table 2 4 for processor VTT VID information 3 Refer to Table 2 11 for Static and Transient Tolerance Table 2 12 DDR3 Signal Group DC Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Units Notes Input Low Voltage 0 43 VDDQ V 2 Vin Input High Voltage 0 57 Vppq V 3 4 V Output Low Voltage 2 Ron V 6 25 Ron Rvtt_term V Output High Voltage Vppo Vppo 2 V 4 6 OH
190. s Support for package C states is a function of processor SKU and platform capabilities All package C states C1 C1E C3 and C6 are annotated here for completeness but actual processor support for these C states may vary Because the Intel Xeon processor 5500 series takes aggressive power savings actions under the deepest C states C1 C1E C3 and C6 PECI requests may have an impact to platform power The impact is documented below Ping GetDIB GetTemp and MbxGet have no measurable impact on processor power under C states Intel Xeon Processor 5500 Series Datasheet Volume 1 129 intel Thermal Specifications MbxSend PCI ConfigRd and PCI ConfigWr usage under package C states may result in increased power consumption because the processor must temporarily return to a CO state in order to execute the request The exact power impact of a pop up to CO varies by product SKU the C state from which the pop up is initiated and the negotiated Table 6 32 Power Impact of PECI Commands versus C states 6 3 7 5 Table 6 33 6 3 7 6 130 Command Power I mpact Ping Not measurable GetDIB Not measurable GetTemp Not measurable PCI ConfigRd Requires a package pop up to a CO state PCI ConfigWr Requires a package pop up to a CO state MbxSend Requires a package pop up to a CO state MbxGet Not measurable S States The PECI client
191. s an S state transition which is not allowed a machine check error will be generated by the processor 7 4 Intel Turbo Boost Technology The processor supports ACPI Performance States P States The P state referred to as PO will be a request for Intel Turbo Boost Technology Intel TBT Intel TBT opportunistically and automatically allows the processor to run faster than the marked frequency if the part is operating below power temperature and current limits Max Turbo Boost frequency is dependent on the number of active cores and varies by processor line item configuration Intel TBT doesn t need special hardware support and can be enabled or disabled by BIOS 7 5 Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology Following are the key features of Enhanced Intel SpeedStep Technology Multiple voltage and frequency operating points provide optimal performance at the lowest power Voltage and frequency selection is software controlled by writing to processor MSRs f the target frequency is higher than the current frequency Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progr
192. s used to support automatic selection of power supply voltages V r The voltage supply for this signal must be valid before the VR can supply to the processor Conversely the VR output must be disabled until the voltage supply for the VID signal become valid The VID signal is needed to support the processor voltage specification variations The VR must supply the voltage that is requested by the signal Notes Vita Power for the analog portion of the Intel QuickPath Interconnect and Shared Cache Power for the digital portion of the Intel QuickPath Interconnect and Shared Cache VDDPWRGOOD VDDPWRGOOD is an input that indicates the Vddq power supply is good The processor requires this signal to be a clean indication that the Vddq power supply is stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the Vddq supply is turned on until it come within specification The signals must then transition monotonically to a high state The PwrGood signal must be supplied to the processor This signal is used to protect internal circuits against voltage sequencing issues VID 7 6 VID 5 3 CSC 2 0 VID 2 0 MSI D 2 0 1 0 VID 7 0 Voltage I D are output signals that are used to support automatic selection of power supply voltages Vcc The voltage supply for these signals must be valid before
193. se note that requests to execute Built In Self Test BIST not selected by hardware but rather passed across the Intel QuickPath Interconnect link during initialization Processors sample VID 2 0 MSID 2 0 and VID 5 3 CSC 2 0 around the asserting edge VTTPWRGOOD Power On Configuration Signal Options Configuration Option Signal Reference Output tristate PROCHOT 2 Section 6 2 4 PECI ID ODT PECI_ID 3 Section 6 3 7 3 MSID VID 2 0 MSID 2 0 3 Table 2 3 CSC VID 5 3 CSC 2 0 3 Table 2 3 Notes 1 Asserting this signal during RESET de assertion will select the corresponding option Once selected this option cannot be changed except via another reset The processor does not distinguish between a warm reset and a power on reset Output tri state via the PROCHOT power on configuration option is referred to as Fault Resilient Boot FRB 2 Latched when VITPWRGOOD is asserted and all internal power good conditions are met 3 See the signal definitions in Table 5 1 for the description of PECI_ID MSID and CSC Assertion of the PROCHOT signal through RESET de assertion also referred to as Fault Resilient Boot FRB will tri state processor outputs Figure 7 1 outlines timing requirements when utilizing PROCHOT as a power on configuration option In the event an FRB is desired PROCHOT and RESET should be asserted simultaneously Furthermore once asserted PROCHOT should remain low long en
194. series PECI client is designed to support the following sideband functions Processor and DRAM thermal management Platform manageability functions including thermal power and electrical error monitoring Processor interface tuning and diagnostics capabilities Intel Interconnect BIST Intel IBIST Thermal Management Processor fan speed control is managed by comparing PECI thermal readings against the processor specific fan speed control reference point or Tcontro_ Both TeonTROL and PECI thermal readings are accessible via the processor PECI client These variables are referenced to a common temperature the TCC activation point and are both defined as negative offsets from that reference Algorithms for fan speed management using thermal readings and the TcowrRo reference are documented in Section 6 3 2 6 PECI based access to DRAM thermal readings and throttling control coefficients provide a means for Board Management Controllers BMCs or other platform management devices to feed hints into on die memory controller throttling algorithms These control coefficients are accessible using PCI configuration space writes via PECI The PECI based configuration write functionality is defined in Section 6 3 2 5 and the DRAM throttling coefficient control functions are documented in the Intel Xeon Processor 5500 Series Datasheet Volume 2 Platform Manageability PECI allows full read access to error and status mon
195. signal groups can be found in the applicable platform design guide Refer to Section 1 2 Intel strongly recommends performing analog simulations of all interfaces Please refer to Section 1 2 for signal integrity model availability Intel QuickPath nterconnect Intel Xeon Processor 5500 Series provide two Intel QuickPath Interconnect ports for high speed serial transfer between other enabled components Each port consists of two uni directional links for transmit and receive A differential signaling scheme is utilized which consists of opposite polarity D P D N signal pairs On die termination ODT is included on the processor silicon and terminated to Vss Intel chipsets also provide ODT thus eliminating the need to terminate on the system board Figure 2 1 illustrates the active ODT Active ODT for a Differential Link Example x Signal Ry DDR3 Signal Groups The memory interface utilizes DDR3 technology which consists of numerous signal groups These include Reference Clocks Command Signals Control Signals and Data Signals Each group consists of numerous signals which may utilize various signaling technologies Please refer to Table 2 5 for further details Intel Xeon Processor 5500 Series Datasheet Volume 1 13 intel 2 1 3 1 Figure 2 2 2 1 4 2 1 5 14 Intel Xeon Processors 5500 Series Electrical Specifications Platform Environmental Control Interfac
196. st be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal Group Summary Signals are combined in Table 2 5 by buffer type and characteristics Buffer Type denotes the applicable signaling technology and specifications Signal Groups Sheet 1 of 2 Signal Group Buffer Type Signals Intel QuickPath I nterconnect Signals Differential Intel QuickPath Interconnect Input QPI 0 1 DRX D N P 19 0 QPI 0 1 CLKRX DP QPI 0 1 CLKRX DN Differential Intel QuickPath Interconnect Output QPI 0 1 DTX_D N P 19 0 QPI 0 1 CLKTX DP QPI 0 1 CLKTX DN Single ended Analog Input QPI 0 1 COMP DDR3 Reference Clocks Differential Output DDR 0 1 2 CLK P N 3 0 Intel Xeon Processor 5500 Series Datasheet Volume 1 23 intel Table 2 5 24 Intel Xeon Processors 5500 Series Electrical Specifications Signal Groups Sheet 2 of 2 Signal Group Buffer Type DDR3 Command Signals Signals Single ended CMOS Output DDR 0 1 2 RAS DDR 0 1 2 _CAS DDR 0 1 2 _WE DDR 0 1 2 MA 15 0 DDR 0 1 2 BA 2 0 DDR 0 1 2 MA PAR Single ended Asynchronous Output DDR 0 1 2 RESET DDR3 Control Signals Single ended CMOS Output DDR 0 1 2 _CS 7 0 DDR 0 1 2 _ODT 5 0 DDR 0 1 2 _CKE 3
197. stem See the Intel 64 and IA 32 Architecture Software Developer s Manuals for more detailed information Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC signal quality mechanical and thermal are satisfied Intel Xeon Processor 5500 Series Datasheet Volume 1 I ntroduction intel I ntel Xeon Processor 5500 Series Includes processor substrate and integrated heat spreader IHS Integrated Memory Controller I MC As the term implies the Memory Controller is integrated on the processor die Intel QuickPath I nterconnect Intel QPI A cache coherent link based Interconnect specification for Intel processors chipsets and 1 bridge components Intel 64 Architecture An enhancement to Intel s A 32 architecture allowing the processor to execute operating systems and applications written to take advantage of Intel 64 I ntel Virtualization Technology Intel VT A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions VT provides a foundation for widely deployed virtualization solutions and enables more robust hardware assisted virtualization solution Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Jitter Any
198. tel QuickPath Interconnect port1 The inbound 20 lanes are connected to another component s outbound lanes QPI1 DTX DN 19 0 O QPI1 DTX DN 19 0 and QPI1_DTX_DP 19 0 comprise the differential transmit QPI1 DTX DP 19 0 data for Intel QuickPath Interconnect port1 The outbound 20 lanes are connected to another component s inbound lanes DBR DBR is used only in systems where debug port is implemented the system board DBR is used by a debug port interposer so that an in target probe can drive system reset DDR COMP 2 0 Must be terminated on the system board using precision resistors Intel Xeon Processor 5500 Series Datasheet Volume 1 85 intel Signal Definitions Table 5 1 Signal Definitions Sheet 2 of 4 Name Type Description Notes DDR DDR is used for imposing duty cycle throttling on all memory channels The platform should ensure that DDR THERM is exerted when any DIMM is over T64 85 C DDR 0 1 2 BA 2 0 O Defines the bank which is the destination for the current Activate Read Write 1 or Precharge command DDR 0 1 2 _CAS O Column Address Strobe DDR 0 1 2 _CKE 3 0 Clock Enable DDR 0 1 2 _CLK_N 3 0 O Differential clocks to the DIMM All command and control signals are valid on the DDR 0 1 2 P 3 0 rising edge of clock DDR 0 1 2 _CS 7 0 O Each signal selects one rank as the target
199. the HLT instruction for C1 and CIE and P LVLx reads to the ACPI P BLK register block mapped in the processor s I O address space The P LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads to the system The P LVLx I O Monitor address does not need to be set up before using the P LVLx I O read interface Software may make C state requests by using a legacy method involving I O reads from the ACPI defined processor clock control registers referred to as P LVLx This feature is designed to provide legacy support for operating systems that initiate C state transitions via access to pre defined CH registers The base P LVLx register is P LVL2 corresponding to request P LVL3 is C6 and all P_LVL4 are demoted to a C6 P LVLx is limited to a subset of C states supported on the processor E g P LVL8 is not supported and will not cause an I O redirection to a C8 request Instead it will fall through like a normal I O instruction The range of I O addresses that may be converted into C state requests is also defined in the PMG IO CAPTURE MSR in the Intel Xeon Processor 5500 Series Datasheet Volume 1 Features Figure 7 2 7 2 1 Table 7 2 7 2 1 1 Intel Xeon Processor 5500 Series Datasheet Volume 1 intel C state Range field This field maybe written by BIOS to restrict the range of I O addresses that are trapped and redirected to MW
200. the processor case temperature will not reach this value due to TCC activation see Figure 6 2 for Intel Xeon processor 5500 series Advanced SKU The Intel Xeon processor 5500 series Standard Basic SKUs see Figure 6 3 Table 6 7 support a single Thermal Profile For this processor it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to this processor s TMDG for details on system thermal solution design thermal profiles and environmental considerations The Intel Xeon processor 5500 series Low Power SKU see Figure 6 4 Table 6 9 supports a single Thermal Profile For this processor it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to this processor s TMDG for details on system thermal solution design thermal profiles and environmental considerations The Intel Xeon Processor L5518 and Intel Xeon Processor L5508 both support Thermal Profiles with nominal and short term conditions designed to meet NEBS level 3 compliance see Figure 6 5 and Figure 6 6 respectively For these SKU s operation at either the nominal or short term thermal profiles should result in virtually no TCC activation Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustaine
201. the CIE state the processor will first switch to the lowest bus ratio and then transition to the lower VID No notification to the system occurs upon entry to C1 CIE To operate within specification BIOS must enable the feature for all installed processors Package C3 State The package will enter the C3 low power state when all cores are in the C3 or lower power state and the processor has been granted permission by the other component s in the system to enter the C3 state The package will also enter the C3 state when all cores are in an idle state lower than C3 but other component s in the system have only granted permission to enter C3 If Intel QuickPath Interconnect L1 has been granted the processor will disable some clocks and PLLs and for processors with an Integrated Memory Controller the DRAM will be put into self refresh Package C6 State The package will enter the C6 low power state when all cores are in the C6 or lower power state and the processor has been granted permission by the other component s in the system to enter the C6 state The package will also enter the C6 state when all cores are in an idle state lower than C6 but the other component s have only granted permission to enter C6 If Intel QuickPath Interconnect L1 has been granted the processor will disable some clocks and PLLs and the shared cache will enter a deep sleep state Additionally for processors with an Integrated Memory Controller the D
202. the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion 13 Specification is at TcAsg 50 C 14 Characterized by design not tested Table 2 9 Static and Transient Tolerance Vcc max V V min V Notes 2 3 4 0 VID 0 000 VID 0 015 VID 0 030 5 VID 0 004 VID 0 019 VID 0 034 10 VID 0 008 VID 0 023 VID 0 038 15 VID 0 012 VID 0 027 VID 0 042 20 VID 0 016 VID 0 031 VID 0 046 25 VID 0 020 VID 0 035 VID 0 050 30 VID 0 024 VID 0 039 VID 0 054 35 VID 0 028 VID 0 043 VID 0 058 40 VID 0 032 VID 0 047 VID 0 062 45 VID 0 036 VID 0 051 VID 0 066 50 VID 0 040 VID 0 055 VID 0 070 55 VID 0 044 VID 0 059 VID 0 074 60 VID 0 048 VID 0 063 VID 0 078 65 VID 0 052 VID 0 067 VID 0 082 70 VID 0 056 VID 0 071 VID 0 086 75 VID 0 060 VID 0 075 VID 0 090 80 VID 0 064 VID 0 079 VID 0 094 85 VID 0 068 VID 0 083 VID 0 098 90 VID 0 072 VID 0 087 VID 0 102 95 VID 0 076 VID 0 091 VID 0 106 100 VID 0 080 VID 0 095 VID 0 110 105 VID 0 084 VID 0 099 VID
203. timing variation of a transition edge or edges from the defined Unit Interval UI LGA1366 Socket The 1366 land FC LGA package mates with the system board through this surface mount 1366 contact socket Server SKU A processor Stock Keeping Unit SKU to be installed in either server or workstation platforms Electrical power and thermal specifications for these SKU s are based on specific use condition assumptions Server processors may be further categorized as Advanced Standard Basic and Low Power SKUs For further details on use condition assumptions please refer to the latest Product Release Qualification PRQ Report available via your Customer Quality Engineer CQE contact Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any 1 05 biased or receive any clocks Unit Interval UI Signaling convention that is binary and unidirectional In this binary signaling one bit is sent for every edge of the forwarded clock whether it be a rising edge or a falling edge If a number of edges are collected at instances ty t2 t then the UI at instance n is defined as Workstation SKU A processor SKU to be installed in workstation platforms only Electrical power and thermal specifications
204. to Vy 6 BPM 7 0 and PREQ signals have ODT in package with 35 Q pull ups to 7 ID has ODT in package with a 1 5 pull up to Vy 8 VCCPWRGOOD VDDPWRGOOD and VTTPWRGOOD have ODT in package with a 5 20 pull down to Vss Mixing Processors Intel supports dual processor DP configurations consisting of processors 1 from the same power optimization segment 2 that support the same maximum Intel QuickPath Interconnect and DDR3 memory speeds 3 that share symmetry across physical packages with respect to the number of logical processor per package number of cores per package number of Intel QuickPath interfaces and cache topology 4 that have identical Extended Family Extended Model Processor Type Family Code and Model Number as indicated by the function 1 of the CPUID instruction Processors must operate with the same Intel QuickPath Interconnect DDR3 memory and core frequency While Intel does nothing to prevent processors from operating together some combinations may not be supported due to limited validation which may result in uncharacterized errata Coupling this fact with the large number of Intel Xeon Processor 5500 series attributes the following population rules and stepping matrix have been developed to clearly define supported configurations 1 Processors must be of the same power optimization segment This insures processors include the same maximum Intel QuickPath interconnect and D
205. ttling forces all CPU cores into duty cycle clock modulation where the core toggles between CO clocks on and C1 clocks off states at the specified duty cycle This throttling reduces CPU performance to the duty cycle specified and more importantly results in processor power reduction The Intel Xeon processor 5500 series software initiated T state throttling and automatic T state throttling as part of the internal Thermal Monitor response mechanism upon TCC activation The PECI T state throttling control register read write capability is Intel Xeon Processor 5500 Series Datasheet Volume 1 119 n tel Thermal Specifications Table 6 22 managed only in the domain software may not manipulate or read the PECI T state control setting In the event that multiple agents are requesting T state throttling simultaneously the CPU always gives priority to the lowest power setting or the numerically lowest duty cycle On Intel Xeon processor 5500 series the only supported duty cycle is 12 596 12 596 clocks on 87 596 clocks off It is expected that T state throttling will be engaged only under emergency thermal or power conditions Future products may support more duty cycles as defined in the following table ACPI T state Duty Cycle Definition Duty Cycle Code Definition 0x0 Undefined 0x1 12 5 clocks on 87 5 clocks off 0x2 25 clocks on 75 clocks off 0x3 37 5 cl
206. ture threshold crossings Counter 0x03 0x00 0x00 Snapshots all PECI based counters Snapshot Counter Clear 0x04 0x00 0x00 Concurrently clear and restart all counters Counter Read 0x05 Counter Counter Data Returns the counter number requested Number 0 Total reference time 1 Total TCC Activation time counter Icc TDC Read 0x06 0x00 Icc TDC Returns the specified of this part in Amps Thermal Config 0x07 0x00 Thermal Reads the thermal averaging constant Data Read config data Thermal Config 0x08 Thermal 0x00 Writes the thermal averaging constant Data Write Config Data Tcontrol Read 0x09 0x00 Tcontrol Reads the fan speed control reference temperature Tcontrol in PECI temperature format Machine Check Ox0A Bank Register Data Read CPU Machine Check Banks Read Number Index T state OxB 0x00 ACPI T state Reads the PECI ACPI T state throttling control word Throttling Control Word Control Read T state OxC ACPI T 0x00 Writes the PECI ACPI T state throttling control word Throttling state Control Write Control Word 6 3 2 6 2 6 3 2 6 3 116 Any MbxSend request with a request type not defined in Table 6 19 will result in a failing completion code More detailed command definitions follow Ping The Mailbox interface may be checked by issuing a Mailbox Ping command If the command returns a passing completion code it is functional Under normal operating conditions the Mailbox Ping command should always pass
207. ulator will supply all and Vrrp lands VIT VID signals are CMOS push pull outputs Please refer to Table 2 17 for the DC specifications for these signals Individual processor VIT VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings The Intel Xeon Processor 5500 Series utilizes three voltage identification signals to support automatic selection of power supply voltages These correspond to VTT VID 4 2 The voltage level delivered to the processor lands must also encompass 20 mV offset See Table 2 4 above the voltage level corresponding to the state of the VTT VID 7 0 signals See Table 2 4 VR 11 0 Voltage Table 2 11 and Figure 2 10 provide the resulting static and transient tolerances Please note that the maximum and minimum electrical loadlines are defined by a 31 5 mV tolerance band above and below values Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Intel Xeon Processor 5500 Series Datasheet Volume 1 m e Intel Xeon Processors 5500 Series Electrical Specifications n te D Table 2 4 2 1 8 2 2 Table 2 5 Vr1 Voltage Identification Definition VID7 VID6 VID5 VIDA VID3 VID2 VID1 VIDO 2 un 0 1 0 0 0 0 1 0 1 200 1 220
208. unless otherwise noted DC specifications are only valid while meeting specifications for case temperature Specified in Section 6 clock frequency and input voltages Care should be taken to read all notes associated with each specification Table 2 8 Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter MM Min Typ Max Unit Notes VID Vcc VID Range 0 750 1 350 V 2 3 Vcc Core Voltage Vcc 3 4 6 7 11 Launch See Table 2 9 and Figure 2 3 Vvip step VID step size during a 6 250 mV 9 d transition VccPLL PLL Voltage a VccPLL 0 95 Vccpi L 1 800 1 05 VccepLL V 10 DC AC specification Typ Typ Voltage for DDR3 0 95 1 500 1 05 V 10 DC AC specification Typ Typ VIT VID VID Range 1 045 1 220 2 3 Vit Uncore Voltage Vit See Table 2 11 and Figure 2 10 V 3 5 8 11 Launch FMB lec MAX Max Processor Current Vcc 150 A 11 IccpiL Intel Xeon Processor VccPLL 1 1 A l MAX TDP 130W Launch FMB Max Processor Current Vcc 120 A 11 Intel Xeon Processor 1 1 A 5500 Series Advanced V 9 A SKU DDQ TDP 95W Vita 6 A Launch FMB Vip 22 A Max Processor Current Vcc 100 A 11 Intel Xeon Processor V 1 1 A 5500 Series 2 5 9 Standard Basic SKU TDP 80W Vita 6 A Launch FMB 22 Max Proc
209. uture use CSC 2 0 VID 5 3 000 Feature Disabled Current Sensor Configuration 001 ICC MAX 40A Ar pi Ee gain _ 1 applied to the ISENSE A D 010 IEC MAX S0A output ISENSE data is then 011 ICC_MAX 80A used to dynamically calculate 100 100A current and power 101 ICC MAX 120A 111 ICC MAX 150A MSID 2 0 VID 2 0 001 38W TDP 40A ICC MAX MSID 2 0 signals are provided 011 60W TDP 80A ICC MAX to indicate the Market Segment 100 80W TDP 100A ICC MAX for the processor and may be used for future processor 101 95W 120A ICC MAX compatibility or keying See 110 130W 150A ICC MAX Figure 7 1 for platform timing requirements of the MSID 2 0 signals Notes 1 This setting is defined for future use no specific Intel Xeon Processor 5500 Series SKU is defined with ICC MAX 50A 2 General rule Set PWM IMON slope to 900mV I MAX where IccMAX with one exception for Intel Xeon Processor W5580 set MON slope to 900mV 180A but for all other SKUs they have to match as shown above Consult your PWM data sheet for the IMON slope setting Some POC signals include specific timing requirements Please refer to Section 7 1 for further details 2 1 7 4 Processor Voltage Identification VTT VID Signals 22 The voltage set by the VIT VID signals is the typical reference voltage regulator VR output to be delivered to the processor V ra and lands It is expected that one reg
210. vers comms and storage markets Intel Xeon Processor L5508 with 38W TDP and elevated case temperatures The elevated case temperatures are intended to meet the short term thermal profile requirements of NEBS Level 3 These 2 Socket processors are ideal for thermally constrained form factors in embedded servers comms and storage markets intel Note Table 1 1 1 1 10 Introduction 1 Socket Workstation Platforms support Intel Xeon Processor 5500 Series SKUs These platforms enable a wide range of options for either the performance power or cost sensitive customer All references to chipset in this document pertain to the Intel 5520 chipset and Intel 5500 chipset unless specifically stated otherwise I ntel Xeon Processor 5500 Series Feature Set Overview Feature Intel Xeon Processor 5500 Series Cache Sizes Instruction Cache 32 KB per core Data Cache 32 KB per core 256 KB Mid Level Cache per core 8 MB shared among cores up to 4 Data Transfer Rate Two 2 full width I ntel QuickPath Interconnect links up to 6 4 GT s in each direction Multi Core Support Up to 4 Cores per processor Dual Processor Support Up to 2 processors per platform Package 1366 land FCLGA Terminology symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESETZ is low a reset has been requested
211. will abort the write and will always respond with a bad Write FCS Command Format The PCI ConfigWr format is as follows Write Length 7 byte 8 word 10 dword Read Length 1 Command 5 Multi Domain Support Yes see Table 6 26 Description Writes the data sent to the requested register address Write Length dictates the desired write granularity The command always returns a completion code indicating the pass fail status information Write commands issued to illegal Bus Numbers or unimplemented Device Function Register addresses are ignored but return a passing completion code Refer to Section 6 3 4 2 for details regarding completion codes Intel Xeon Processor 5500 Series Datasheet Volume 1 Thermal Specifications n tel Figure 6 18 PCI ConfigWr 6 3 2 5 2 Table 6 18 6 3 2 6 Byte 0 1 2 3 Write Length Read Length Cmd Code i TOR Eva Tue 10X07 Definition 4 5 6 7 LSB PCI Configuration Address MSB 8 WL 1 LSB Data 1 2 or 4 bytes MSB WL WL 1 WL 2 WL 3 Completion AW FCS FCS Code FCS Note that the 4 byte PCI configuration address and data defined above are sent in standard PECI ordering with LSB first and MSB last Supported Responses The typical client response is a passing FCS a passing Completion Code and valid Data Under some conditions the client s response will indicate a failure PCI ConfigWr Response Definition
212. xecute Disable Bit Intel 64 Technology Enhanced Intel SpeedStep Technology Intel virtualization Technology Intel VT Intel Hyper Threading Technology Intel HT Technology and Intel Turbo Boost Technology Intel TBT The Intel Xeon Processor 5500 Series family supports multiple platform segments 2 Socket Workstation Platforms support Intel Xeon Processor W5580 a 130W Thermal Design Power TDP SKU These platforms provide optimal overall performance and reliability in addition to high end graphics support Note specific platform usage conditions apply when implementing these processors 2 Socket High Performance Server and High Performance Computing HPC Platforms support Intel Xeon Processor 5500 Series Advanced SKU 95W TDP These platforms provide optimal overall performance 2 Socket Volume Server Platforms support Intel Xeon Processor 5500 Series Standard Basic SKUs 80W TDP These platforms provide optimal performance per watt for rack optimized platforms Ultra Dense Platforms implement Intel Xeon Processor 5500 Series Low Power SKU 60W TDP These processors are intended for dual processor server blades and embedded servers Intel Xeon Processor L5518 with 60W TDP and elevated case temperatures The elevated case temperatures are intended to meet the short term thermal profile requirements of NEBS Level 3 These 2 Socket processors are ideal for thermally constrained form factors in embedded ser
213. y Side 3D Height Restriction Zones REVISION HISTORY PRIMARY SIDE 3D HEIGHT RESTRICTION ZONES SECONDARY SIDE 3D HEIGHT RESTRICTION ZONES 144 Intel Xeon Processor 5500 Series Datasheet Volume 1 Boxed Processor Specifications Figure 8 9 Volumetric Height Keep l ns AIRFLOW DIRECTION a HE TOP VIEW VOLUMETRIC HEAT SINK 2U TALL Intel Xeon Processor 5500 Series Datasheet Volume 1 145 intel Boxed Processor Specifications Figure 8 10 Volumetric Height Keep I ns 146 a 2 x n ex X gt gt 5 2 E E 5 p gt 2 N 8 L 71 4 C t O j 2 WN 4 LJ e TT x E T lt Intel Xeon Processor 5500 Series Datasheet Volume 1 ntel t 301 133HS 9NIMY8O 3105 10 00 1 0 31 25 INO Nid j k Mo 6118 2505 VI VI 1 VINYS dHO9 NI 34 SNOISNINIO 61185 X08 04 0418 39311

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