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Intel Core 2 Extreme QX9300

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1. Table 13 Pin Listing by Pin Table 13 Pin Listing by Pin Number Number Pin Signal Pin Signal Pin Name Buffer Direction Pin Name Buffer Direction Type Type J6 VCCP Power Other L25 D 29 Source Synch dist 121 VCCP Power Other Input 122 vss Power Other L26 DSTBN 1 Source Synch oe Input Input 123 D 11 Source Synch Output M1 ADSTB 0 Source Synch OU Input M2 vss Power Other j24 D 10 Source Synch Output Input IER vss Power Other M3 AL7 Source Synch Output Input C 26 DSTBN 0 Source Synch ommon J 0 y Output M4 BPM_2 1 Output K1 vss Power Other M5 vss Power Other K2 REQ 2 Source Synch ut M6 VCCP Power Other U M21 VCCP Power Other npu K3 REQ 0 Source Synch Output M22 VSS Power Other ET ces Rewer Ones M23 D 23 Source Synch eae Input K5 A 6 Source Synch Output M24 D 21 Source Synch E K6 VCCP Power Other M25 VSS Power Other K21 VCCP Power Other Input M26 DSTBP 1 Source Synch K22 D 14 Source Synch Ge ni n Output utput N1 VSS Power Other K23 VSS Power Other Input N2 A 8 Source Synch Input K24 8 4 Source Synch Output utput Input Input N3 A 10 Source Synch Output K25 D 17 Source Synch Output p N4 VSS Power Other K26 VSS Power Other Common Input Input N5 BPM 2101
2. Figure 8 Quad Core Processor Pinout Top Package View Left Side 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSS smi vss FERR A20M amp VCC VSS vcc VSS vcc vcc A B acta INIT LINT DPSLP vec VSS VSS vss C RESET amp vss O NE VSS THERM vss vcc vcc vss vcc vec c D vss Toom vss STRELK PWRGO sip rsvp vcc vcc vss vcc vss D E DBSY BNR vss name DPRSTP vss vcc vss vcc vcc vss vcc vec E GTLREF F BRO vss Rstol Rs 1l vss moim vec CONT vec vec vss vcc vss G VSS TRDY amp RS 2 vss HIT G H aps PEO vss Lock DEFER vss H J 9 4 vss REGIS aas VCCP J K vss REQ 2 REQ 0 vss A 6 f VCCP K L reoraj aale vss ADS 413 VSS L M ADSTBLO vss ane VSS VCCP M N vss ais arioj vss 0 N P atisi Anz2 vss an4a Anis vss P R anei vss atigi Apa vss VCCP R T vss THRMD 2618 vss 2513 VCCP T u A23 aol vss Api aisle vss U v ADSIBI yss ee vss VCCP v w vss 2713 3211 vss Ap28 amp A 20 4 w v compr3 ati7i vss arzoj 2214 vss Y AA coMP 2 vss A 35 amp A 33 vss TDI BRi RSVD vcc VSS wc 5 vss A 34 amp TDO VS
3. 39 0 9998 zJoz Z I066G D A S Z SEET ti 10660 n v v a a MIIA dOL M3IA WOLLOS SN S Xv aw 433 H3NHOO 1 1IN3NOdWOO 2 a18vMOTIV XYN CL M3IA 3GIS Blood Xv ino 433 3903 2 Et Xy N qe a a 5869 gt Gm 3 3 te ER DW 7 LL 14 f Gy 4 4 1 T 568 o m alv 5 9009 Sc 0 S0 00 5 H NOILWYOdYOD TALNI JO 1N3SNOO N3LLINM WOIHd IHL LNOHLIM G3ISIGOW YO G3AVIdSIC Q32naoud3s dSSOTDSIC 38 LON AVW 51 SLI QNV 32N3QIJNOO NI Q3SO125SIG SI LI NOLLVWH3OJNI IWLLNAGISNOD NOLLV3SOdHOO 131NI SNIVINO2 SNIMWYG SIHL P nad Z zx Z D LI S 9 Z 8 Quad Core Processor Micro FCPGA Package Drawing Sheet 2 of 2 Package Mechanical Specifications and Pin Information Figure 7 Datasheet n tel Package Mechanical Specifications and Pin I nformation Processor Pinout and Pin List Figure 8 and Figure 9 shows the processor pinout as viewed from the top of the package Table 12 provides the pin list arranged numerically by pin name Table 13 provides the pin list arranged numerically by pin number Table 14 is the signal description for processor Table 15 lists new quad core processor pins compared to the Intel Core 2 Duo processor
4. 67 5 1 Monitoring Die Temperature 68 Skl Thermal E e Le rta tna er NAT 68 5 1 2 Intel Thermal Monitor 69 5 1 3 Digital Thermal Gensor eene nen memes nnne 71 5 2 PROCHOT Signal PIN wis cipe erbe erii NEEN ses ce Ree ANE de deg 72 Figures l Core Low Power States eurian e ERAN EE SEENEN EEN EERSTEN EE Ee Ea 12 2 Package Low Power States 13 3 PSI 2 Functionality Logic DIagFatm edu EES ESERREAENNERESE SEENEN ENEE ANEREN ENER SEENEN 19 4 Active VCC and ICC Loadline for Quad Core Extreme Mobile 5 33 5 Deeper Sleep VCC and ICC Loadline for Quad Core Extreme Mobile Processor 34 6 Quad Core Processor Micro FCPGA Package Drawing Sheet 1 2 38 7 Quad Core Processor Micro FCPGA Package Drawing Sheet 2 of 2 39 8 Quad Core Processor Pinout Top Package View Left Side 40 9 Quad Core Processor Pinout Top Package View Right Side s sse 41 Tables E lee 9 2 Coordination of Core Low Power States at the Package Level 13 3 Voltage Identification Definition Hmmm seen nnn nnn 23 4 BSEL 2 0 Encoding for BCLK Frequency mme e emnes 27 5b ESB Pin GhOUPS EE 28 6 Processor Absolute Maximum Rating 29 7 Voltage and Current Specifications for the Quad Core
5. Table 8 Voltage and Current Specifications for the Quad Core Mobile Processors Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Notes I cc for Processors Processor Number Core Frequency Voltage lec Q9100 2 26 GHz amp Vecuem 64 3 4 1 60 GHz amp VCCLFM 47 Q9000 2 0 GHz VccurM 64 3 4 1 60 GHz amp VecLEM 47 Icc Auto Halt Stop Grant e HFM 32 4 A 3 4 SONT LFM 30 0 lec Sleep Isi p HFM 31 8 A 3 4 LFM 29 7 Icc Deep Sleep Ipsi HFM 30 1 A 3 4 LFM 28 8 DPRSLP lcc Deeper Sleep 20 5 A 3 4 Vcc Power Supply Current Slew Rate u dl cc or at Processor Package Pin 600 JAS rz lecca lec for Veca Supply 130 mA Icc for Vccp Supply before Vcc Stable 4 5 8 9 d Icc for Vccp Supply after Vcc Stable 2 5 A f NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State 2 The voltage specifications are assumed to be measured across Vcc sense and Vss sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capaci
6. A HFM LFM Note 1 Vcc cone Set Point Error Tolerance is per below Tolerance Voc core VID Voltage Range 1 5 Vcc cone gt 0 7500V 11 5mV 0 5000V lt Vcc core lt 0 75000V 33 Figure 5 Table 9 34 Electrical Specifications Deeper Sleep Vcc and I cc Loadline for Quad Core Extreme Mobile Processor Voc core V Slope 2 1 mV A at package VccSense VssSense pins Differential Remote Sense required Voo cone max HFM LFM Vcc cone oo max HFM LFM Voc core nom HFM LFM Vco cone pc min HFM LFM Vec core min HFM LFM Voc core Tolerance VR St Pt Error 1 lcc conE 0 lcc cone max A HFMILFM Note 1 Vcc cone Set Point Error Tolerance is per below Tolerance Vcc cone VID Voltage Range VID 1 5 3mV Vcc cone gt 0 7500V 11 5mV 3mV 0 5000V lt Vcc cone lt 0 7500V 0 3000V lt Vcc conE lt 0 5000V NOTE Deeper Sleep mode tolerance depends on VID value AGTL Signal Group DC Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Notes Vccp 1 0 Voltage 1 00 1 05 1 10 V GTLREF Reference Voltage 0 65 0 70 0 72 V GTLREF 2 Reference Voltage 2 0 653 0 67 0 7 V Rcomp Compensation Resistor 24 75 25 25 25 Q 10 Termination Resistor 45 50 55 Q 11 12 RoDT A Address SE Resistor 45 50 55 11 13 Termination Resistor Ropr cntrl Control 4
7. AE2 CMOS Output Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 12 Pin Listing by Pin Name Table 12 Pin Listing by Pin Name ns T Bons Direction lama E Ge Direction VSS A2 Power Other VSS AD19 Power Other VSS A4 Power Other VSS AD22 Power Other VSS A8 Power Other VSS AD25 Power Other VSS A11 Power Other VSS Power Other VSS A14 Power Other VSS AE4 Power Other VSS A16 Power Other VSS AE11 Power Other VSS A19 Power Other VSS AE14 Power Other vss A23 Power Other VSS AE16 Power Other vss A25 Power Other VSS AE19 Power Other vss AA2 Power Other VSS AE23 Power Other VSS AA5 Power Other VSS AE26 Power Other VSS AA11 Power Other VSS AF2 Power Other VSS AA14 Power Other VSS AF6 Power Other VSS AA16 Power Other VSS AF8 Power Other VSS AA19 Power Other VSS AF11 Power Other VSS AA22 Power Other VSS AF13 Power Other VSS AA25 Power Other VSS AF16 Power Other VSS AB1 Power Other VSS AF19 Power Other VSS AB4 Power Other VSS AF21 Power Other VSS AB8 Power Other VSS AF25 Power Other VSS AB11 Power Other VSS B6 Power Other VSS AB13 Power Other VSS B8 Power Other VSS AB16 Power Other VSS B11 Power Other VSS AB19 Power Other VSS B13 Power Other VSS AB23 Power Other VSS B16 Power Other VSS AB26 Powe
8. Clock Output L1 REQ 4 Source Synch Output p U N6 VCCP Power Other npu L2 A 13 Source Synch Output N21 VCCP Power Other L3 VSS Power Other N22 D 16 Source Synch GER Input L4 A 5 Source Synch Output N23 VSS Power Other Input Input L5 A 4 Source Synch Output N24 DINV 1 Source Synch Output L6 MSS Power Other N25 D 31 Source Synch Ae L21 VSS Power Other N26 VSS Power Other 122 2214 Source Synch Put y Output Input P1 A 15 Source Synch o T utput L23 D 20 Source Synch Output Input P2 A 12 Source Synch o utput L24 VSS Power Other P3 VSS Power Other Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 13 Pin Listing by Pin Table 13 Pin Listing by Pin Number Number Pin Signal Pin Signal Pin Name Buffer Direction Pin Name Buffer Direction Type Type Input Input P4 A 14 Source Synch Output T24 D 27 Source Synch Output Input Input P5 A 11 Source Synch Output T25 D 30 Source Synch Output P6 VSS Power Other T26 VSS Power Other m VSS Power Other Ul A 23 Source Synch oa Input P22 D 26 Source Synch Output Input U2 A 30 Source Synch input utput P23 D 25 4 Source Synch Output U3 VSS Power Other dodi VSS Power Other U4 A 21 Source Synch aa Input P25 D 24 Source Synch
9. Document Number Intel Core 2 Extreme Quad Core Mobile Processor Intel Core 2 Quad Mobile Processor Intel Core 2 Extreme Mobile Processor Intel 320121 Core 2 Duo Mobile Processor and Intel Core 2 Solo Mobile Processors on 45 nm Process Specification Update Mobile Intel amp 4 Series Express Chipset Family Datasheet 320122 Mobile Intel amp 4 Series Express Chipset Family Specification Update 320123 Intel I O Controller Hub 9 ICH9 I O Controller Hub 9M ICH9M 316972 Datasheet Intel Controller Hub 9 ICH9 I O Controller Hub 9M ICH9M 316973 Specification Update See http Intel 64 and IA 32 Architectures Software Developer s Manuals EE products processor manuals index htm Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 NOTES Contact your Intel representative for the latest revision and document number of this document 10 Introduction Datasheet m Low Power Features l n tel 2 2 1 Datasheet Low Power Features Clock Control and Low Power States The processor supports low power states both at the individual core level and the package level for optimal power management A core may independently enter the C1 AutoHALT C1 MWAIT C2 C3 and C4 low power states When all cor
10. Package Mechanical Specifications and Pin I nformation Package Mechanical Specifications The processor is available in a 478 pin Micro FCPGA package The package mechanical dimensions are shown in Figure 6 and Figure 7 The mechanical package pressure specifications are in a direction normal to the surface of the processor This requirement protects the processor die from fracture risk due to uneven die pressure distribution under tilt stack up tolerances and other similar conditions These specifications assume that a mechanical attach is designed specifically to load one type of processor The processor package substrate should not be used as a mechanical reference or load bearing surface for the thermal or mechanical solution 37 Package Mechanical Specifications and Pin Information intel Quad Core Processor Micro FCPGA Package Drawing Sheet 1 of 2 Figure 6 T0 19998 TJ0T ZTO66C T E v 4 S 9 6 8 zs m majl s maen Fee Pal 610660 mm HG v awa s
11. 0 1 2750 0 0 1 0 0 1 1 1 2625 0 0 1 0 1 0 0 1 2500 0 0 1 0 1 0 il 1 2375 0 0 1 0 1 1 0 1 2250 0 0 1 0 1 1 1 1 2125 0 0 1 1 0 0 0 1 2000 0 0 1 1 0 0 1 1 1875 0 0 1 1 0 1 0 1 1750 0 0 1 1 0 1 1 1 1625 0 0 1 1 1 0 0 1 1500 0 0 1 1 1 0 1 1 1375 0 0 1 1 1 1 0 1 1250 0 0 1 1 1 1 1 1 1125 0 1 0 0 0 0 0 1 1000 0 1 0 0 0 0 1 1 0875 0 1 0 0 0 1 0 1 0750 0 1 0 0 0 1 1 1 0625 0 L 0 0 1 0 0 1 0500 23 intel Table 3 24 Voltage Identification Definition Sheet 2 of 4 Electrical Specifications VI D6 VID5 VIDA VID3 VI D2 VID1 VIDO Vcc V 0 1 0 0 1 0 1 1 0375 0 1 0 0 1 1 0 1 0250 0 1 0 0 1 1 i 1 0125 0 1 0 1 0 0 0 1 0000 0 1 0 1 0 0 1 0 9875 0 1 0 1 0 1 0 0 9750 0 1 0 1 0 1 1 0 9625 0 1 0 1 1 0 0 0 9500 0 I 0 1 1 0 1 0 9375 0 1 0 1 1 1 0 0 9250 0 1 0 1 1 1 1 0 9125 0 1 1 0 0 0 0 0 9000 0 1 1 0 0 0 1 0 8875 0 1 1 0 0 1 0 0 8750 0 1 1 0 0 1 1 0 8625 0 1 1 0 T 0 0 0 8500 0 1 1 0 1 0 1 0 8375 0 1 1 0 1 1 0 0 8250 0 1 1 0 1 1 1 0 8125 0 1 1 1 0 0 0 0 8000 0 1 1 1 0 0 1 0 7875 0 1 1 1 0 1 0 0 7750 0 1 1 1 0 1 1 0 7625 0 1 1 1 1 0 0 0 7500 0 1 1 1 1 0 1 0 7375 0 1 1 1 d 1 0 0 7250 0 1 1 1 1 1 1 0 7125 1 0 0 0 0 0 0 0 7000 L 0 0 0 0 0 1 0 6875 1 0 0 0 0 1 0 0 6750 I 0 0 0 0 1 1 0 6625 1 0 0 0 1 0 0 0 6500 1 0 0 0 1 0 1 0 6375 1 0 0 0 1 1 0 0 6250 I 0 0 0 1 1 1
12. 0 6125 1 0 0 1 0 0 0 0 6000 1 0 0 1 0 0 1 0 5875 1 0 0 1 0 1 0 0 5750 Datasheet Electrical Specifications Table 3 Datasheet Voltage Identification Definition Sheet 3 of 4 VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc V 1 0 0 1 0 1 1 0 5625 1 0 0 1 1 0 0 0 5500 1 0 0 1 1 0 1 0 5375 1 0 0 1 1 1 0 0 5250 1 0 0 1 1 1 1 0 5125 1 0 1 0 0 0 0 0 5000 1 0 1 0 0 0 1 0 4875 1 0 1 0 0 1 0 0 4750 1 0 1 0 0 1 1 0 4625 1 0 1 0 1 0 0 0 4500 1 0 1 0 1 0 1 0 4375 1 0 1 0 1 1 0 0 4250 1 0 1 0 1 1 1 0 4125 1 0 1 1 0 0 0 0 4000 1 0 1 1 0 0 1 0 3875 1 0 1 1 0 1 0 0 3750 1 0 1 1 0 1 1 0 3625 1 0 1 1 1 0 0 0 3500 1 0 1 1 1 0 1 0 3375 1 0 1 1 1 1 0 0 3250 1 0 L 1 L 1 1 0 3125 1 1 0 0 0 0 0 0 3000 1 1 0 0 0 0 1 0 2875 1 1 0 0 0 1 0 0 2750 1 1 0 0 0 1 1 0 2625 1 1 0 0 1 0 0 0 2500 1 1 0 0 1 0 1 0 2375 1 1 0 0 1 1 0 0 2250 1 1 0 0 1 1 1 0 2125 1 1 0 1 0 0 0 0 2000 1 1 0 1 0 0 1 0 1875 1 1 0 1 0 1 0 0 1750 1 1 0 1 0 1 1 0 1625 1 1 0 1 1 0 0 0 1500 1 1 0 1 1 0 1 0 1375 1 1 0 1 1 1 0 0 1250 1 1 0 1 1 1 1 0 1125 1 1 1 0 0 0 0 0 1000 25 II n tel Electrical Specifications Table 3 3 4 3 5 26 Voltage Identification Definition Sheet 4 of 4 VI D6 VID5 VIDA VID3 VI D2 VID1 VIDO Vcc V 1 1 1 0 0 0 1 0 0875 1 1 1 0 0
13. 1 0 0 0750 1 1 1 0 0 1 1 0 0625 t 1 1 0 1 0 0 0 0500 1 1 1 0 1 0 1 0 0375 1 1 1 0 1 1 0 0 0250 1 1 1 0 1 1 1 0 0125 1 1 1 1 0 0 0 0 0000 1 1 1 1 0 0 1 0 0000 1 1 1 1 0 1 0 0 0000 1 1 1 1 0 1 1 0 0000 1 1 1 1 1 0 0 0 0000 1 1 1 1 1 0 1 0 0000 1 1 1 1 1 0 0 0000 1 1 1 1 1 1 1 0 0000 Catastrophic Thermal Protection The processor supports the THERMTRIP signal for catastrophic thermal protection An external thermal sensor should also be used to protect the processor and the system against excessive temperatures Even with the activation of THERMTRIP which halts all processor internal clocks and activity leakage current can be high enough that the processor cannot be protected in all conditions without the removal of power to the processor If the external thermal sensor detects a catastrophic processor temperature of 125 C maximum or if the THERMTRIP signal is asserted the Vcc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor THERMTRIP functionality is not ensured if the PWRGOOD signal is not asserted Reserved and Unused Pins All RESERVED RSVD pins must remain unconnected Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 2 for a pin listing of the processor and the location of all RSVD p
14. Extreme Mobile Processors 30 8 Voltage and Current Specifications for the Quad Core Mobile 65 31 9 AGTL Signal Group DC Specifications 1 2 0 emen enemies 34 10 CMOS Signal Group DC Specifications enn eee neta 36 11 Open Drain Signal Group DC Specifications cece eee teenie 36 12 Pin Listing by Pifi Nares uus vox sorore pt EES 42 I3 Pin Listing by Pin Number mcer EEN E EDENDI GRE UE ARE FNLPCEL ANE 49 14 Signal DescripEbloOli semi sieve diene ir exc uu RN eessen 57 15 New Pins for the Quad Core Mobile Processor emen nee 66 16 Processor Power Specifications 0 enemies einen nn 67 17 Thermal Diode Interface iio epe ener ecc ee eda dE ven ced nte peni ERR FT FOE gege 69 18 Thermal Diode Parameters Using Transistor Model 69 Datasheet Revision History Document Revision SES Number Number Description Date 320390 001 Initial Release August 2008 320390 002 Updated Table 8 Added Q9000 information January 2009 Updated Table 16 Added Q9000 information Datasheet Datasheet Introduction 1 1 1 Datasheet intel Introduction The Intel Core 2 Extreme quad core processor and Intel Core V2 quad processor on 45 nanometer process technology for platforms based on Mobile Intel 4 Series Express Chipset Family is the first low power mobile quad core processor based on the Intel Core
15. HFM and Lowest Frequency Mode LFM refer to the highest and lowest core operating frequencies supported on the processor Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states Vcc poor is the default voltage driven by the voltage regulator at power up in order to set the VID values Unless specified otherwise all specifications for the processor are at 100 C Read all notes associated with each parameter Voltage and Current Specifications for the Quad Core Extreme Mobile Processors Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Notes Vcc in Intel Dynamic Acceleration u VCCDAM Technology Mode 0 30 1 30 Y Ces VccHFM Vcc at Highest Frequency Mode HFM 0 90 1 25 V 1 2 VccLFM Vcc at Lowest Frequency Mode LFM 0 85 1 10 V 1 2 Verbo Vcc Voltage for Initial Power 1 20 v 2 5 6 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VCCA PLL Supply Voltage 1 425 1 5 1 575 V VccpPRSLP Vcc at Deeper Sleep 0 65 0 85 V 1 2 I cc for Processors Recommended CCDES Design Target 64 A 5 10 Icc for Processors Processor Icc Numb r Core Frequency Voltage QX9300 2 53 GHz amp Vecuem 64 3 4 1 60 GHz amp VCcCLFM 47 Icc Auto Halt Stop Grant IS HFM 32 4 A 3 4 SGNT LFM 30 0 Icc Sleep Isi p HFM 31 8 A 3 4 LFM 29 7 Icc Deep Sleep IpsiP HFM 30 1 A 3 4 LFM 28 8 DPRSLP lcc Deeper Sle
16. Input A 30 U2 Source Synch Input Input Output BRO F1 Common Clock Output Input A 31 Ke Source Synch Output BR1 7 Common Clock eu 32 4 w3 Source Synch BSEL 0 B22 CMOS Output Input BSEL 1 B23 CMOS Output A 33 AA4 Source Synch 33 i Output BSEL 2 C21 CMOS Output A 34 AB2 Source Synch Olea Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 12 Pin Listing by Pin Name Table 12 Pin Listing by Pin Name Pin Pin Signal Pin Pin Signal Name Buffer Type pirecnon Name Buffer Type Direction COMP 0 826 Power Other SE D 29 L25 Source Synch COMP 1 26 Power Other Seet D 2 4 E26 Source Synch COMP 2 Power Other en D 30 T25 Source Synch UE COMP 3 Y1 Power Other Oout D 31 N25 Source Synch t D O 4 E22 Source Synch s DI32 Y22 Source Synch D 10 124 Source Synch ou D 33 AB24 Source Synch Set D 11 123 Source Synch GE D 34 V24 Source Synch D 12 H22 Source Synch DUE D 35 V26 Source Synch ae D 13 F26 Source Synch Guat DI36 V23 Source Synch D 14 K22 Source Synch onan D 37 T22 Source Synch D 15 H23 Source Synch E D 38 U25 Source Synch Ge D 16 N22 Source Synch DI39 U23 Source Synch D 17 K25 Source Synch but D 3 G22 Source Synch D 18 P26 Source Sy
17. Output HE pum SEDES Input i y y Output npu F26 D 18 Source Synch Output U6 VSS Power Other R1 A 16 Source Synch u21 bis ower Other Input R2 VSS Power Other U22 Source Synch Output Input Input R3 A 19 Source Synch Output U23 D 39 Source Synch Output R4 24 4 Source Synch u24 VSS Power Other Input R5 VSS Power Other U25 D 38 Source Synch Output NN Banca Power Other U26 COMP 1 Power Other TUA R21 VCCP Power Other Input R22 vss Power Other v1 ADSTB 1 Source Synch get R23 D 19 Source Synch lees V2 vss Power Other utput i y v3 THRMDC_2 Power Other npu R24 D 28 Source Synch Output Input V4 A 31 Source Synch Output R25 VSS Power Other i V5 VSS Power Other npu R26 COMP 0 Power Other Output V6 VCCP Power Other T1 VSS Power Other V21 VCCP Power Other T2 THRMDA_2 Power Other V22 VSS Power Other Input Input T3 A 26 Source Synch Output V23 D 36 Source Synch Output T4 kids Power Other V24 D 34 Source Synch DUE Input TS A 25 Source Synch Output V25 VSS Power Other T6 VCCP Power Other V26 D 35 Source Synch Aone T21 VCCP Power Other W1 VSS Power Other T22 D 37 Source Synch Input Output Input W2 A 27 Source Synch Output T23 VSS Power Other 55 intel Package Mechanical Specifications and Pin Information Table 13 Pin Listing by Pin Number Pin Signal Pin Name Buffer Direction Type Input w3 A 32 S
18. RESERVED and must be left unconnected on the board However it is recommended that routing channels to these pins on the board be kept open for possible future use SLP Input SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If an SMI is asserted during the deassertion of RESET then the processor will tristate its outputs STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Gra
19. Vcc Measured at the bulk capacitors on the motherboard Vcc Boor tolerance shown in Figure 4 and Figure 5 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested This is a power up peak current specification which is applicable when Vccp is high and coRE is low This is a steady state I cc current specification which is applicable when both Vccp and Vcc CORE are high Instantaneous current Icc core inst Of 85 A has to be sustained for short time tiys1 of 35ys Average current will be less than maximum specified ccpgs VR OCP threshold should be high enough to support current levels described herein Voltage and Current Specifications for the Quad Core Mobile Processors Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Notes Vcc in Intel Dynamic Acceleration EN VCCDAM Technology Mode SH 1 30 y Bee VccHFM Vcc at Highest Frequency Mode HFM 0 90 1 25 V 1 2 VccLFM Vcc at Lowest Frequency Mode LFM 0 85 E 1 10 V 1 2 Bee gue Vcc Voltage for Initial Power 1 20 2 5 6 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VCCA PLL Supply Voltage 1 425 1 5 1 575 V VccpPRSLP Vcc at Deeper Sleep 0 65 0 85 V 1 2 I cc for Processors Recommended CCDES Design Target 9t 5 10 31 m 8 n tel Electrical Specifications
20. a break event from the package low power state control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs The advantage of this feature is that it significantly reduces leakage while in the Stop Grant and Deeper Sleep states Long term reliability cannot be assured unless all the Extended Low Power States are enabled The processor implements two software interfaces for requesting enhanced package low power states MWAIT instruction extensions with sub state hints and via BIOS by configuring 1A32 MISC ENABLES MSR bits to automatically promote package low power states to enhanced package low power states Extended Stop Grant must be enabled via the BI OS for the processor to remain within specification As processor technology changes enabling the extended low power states becomes increasingly crucial when building computer systems Maintaining the proper BIOS configuration is key to reliable long term system operation Not complying to this guideline may affect the long term reliability of the processor Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states Extended Deeper Sleep is an exception to this rule when the Hard C4E configuration is enabled in the 32 MI
21. asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state When FERR PBE is asserted indicating a break event it will remain asserted until STPCLK is deasserted Assertion of PREQ when STPCLK is active will also cause an FERR break event For additional information on the pending break event functionality including identification of support of the feature and enable disable information refer to Volumes 3A and 3B of the Intel 64 and IA 32 Architectures Software Developer s Manuals and the Intel Processor Identification and CPUID Instruction application note GTLREF Input GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 Vocp GTLREF is used by the AGTL receivers to determine if a signal is a logical O or logical 1 Refer to the appropriate platform design guide for details on GTLREF implementation GTLREF_2 Input GTL reference level for AGTL input pins of the second die Refer to the appropriate platform design guide for details on GTLREF implementation GTLREF_CONT ROL Input Output This pin can be used as GTLREF_2 disconnect circuit control signal GTLREF 2 maps out to a reserved pin on Intel Core 2 Duo Processor for Dual Core and quad core interchangeable motherboard GTLREF CONTROL can be used
22. is enabled PROCHOT will be asserted regardless of which core is above its TCC temperature trip point and all cores will have their core clocks modulated If TM2 is enabled then regardless of which core s are above the TCC temperature trip point all cores will enter the lowest programmed TM2 performance state It is important to note that Intel recommends both TM1 and TM2 to be enabled When PROCHOT is driven by an external agent if only TM1 is enabled on all cores then all processor cores will have their core clocks modulated If TM2 is enabled on all cores then all processor cores will enter the lowest programmed TM2 performance state It should be noted that Force TM1 on TM2 enabled via BIOS does not have any effect on external PROCHOT If PROCHOT is driven by an external agent when TM1 TM2 and Force TM1 on TM2 are all enabled then the processor will still apply only TM2 PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi directional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in cas
23. maximum supported operating temperature of the processor Ty max It is the responsibility of software to convert the relative temperature to an absolute temperature The temperature returned by the DTS will always be at or below max Catastrophic temperature conditions are detectable via an Out Of Specification status bit This bit is also part of the DTS MSR When this bit is set the processor is operating out of specification and immediate shutdown of the system should occur The processor operation and code execution is not ensured once the activation of the Out of Specification status bit is set The DTS relative temperature readout corresponds to the Thermal Monitor TM1 TM2 trigger point When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism will activate The DTS and TM1 TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and there is a thermal gradient between the individual core DTS Additionally the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power mechanical and thermal attach and software application The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications 71 m e n tel Thermal Specifications and Design Considerations 72 Changes to the
24. platform power savings and extended battery life The algorithm that the processor uses for determining when to assert PSI 4 is different from the algorithm used in previous mobile processors PSI 2 functionality improves overall voltage regulator efficiency over a wide power range based on the C state and P state of the four cores The combined C state of all cores are used to dynamically predict processor power The PSI 2 functionality logic diagram is shown in Figure 3 PSI 2 Functionality Logic Diagram Asserted to 0 when CPU in C4 DPRSTP PSI Idle Curren 00 2A 2 Bits HVM 01 2 3A fuses 10 3 4A 11 4 5A LimitsetCR BIOS PSI Idle Limit nu 2 Bit CR 10 4A 11 Always on no limit 19 20 Low Power Features Datasheet m Electrical Specifications n tel 3 3 1 3 2 3 2 1 3 2 2 3 2 3 Datasheet Electrical Specifications Power and Ground Pins For clean on chip power distribution the processor will have a large number of Vec power and Vss ground inputs All power pins must be connected to Vcc power planes while all Vss pins must be connected to system ground planes Use of multiple power and ground planes is recommended to reduce I R drop Refer to the platform design guides for more details The processor Vcc pins must be supplied the voltage determined by the VID Voltage ID pins Decoupling Guidelines Due to its large number of transistors and hi
25. refers to the AGTL output group as well as the AGTL I O group when driving With the implementation of a source synchronous data bus two sets of timing parameters need to be specified One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 5 identifies which signals are common clock source synchronous and asynchronous 27 Electrical Specifications intel Input to BCLK 1 0 Table 5 FSB Pin Groups Signal Group Type Signals AGTL Common Clock Synchronous BPRI DEFER PREQ RESET RS 2 0 TRDY AGTL Common Clock I O Synchronous to BCLK 1 0 ADS BNR BPM 3 0 BPM_2 3 0 3 BRO BR1 DBSY DRDY HIT HITM LOCK PRDY DPWR AGTL Strobes Signals Associated Strobe REQ 4 0 A 16 3 ADSTB 0 z 35 17 4 ADSTB 1 AGTL Source SyMENTONOUS Synchronous 1 0 Ge SES D 15 0 DINVO DSTBPO DSTBNO strobe D 31 16 DINV1 DSTBP1 DSTBN1 D 47 32 DINV2 DSTBP2 DSTBN2 D 63 48 DINV3 DSTBP3 DSTBN3 Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 A20M DPRSTP DP
26. software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Pentium Intel Core Duo Intel SpeedStep MMX and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2008 2009 Intel Corporation All rights reserved 2 Datasheet Contents Datasheet 1 Bud e e TT d e BEER H Euge t EE EE SE es H 1 2 Refefences coercere ada bin aes PLE RONG AER Eee 9 2 Low Power e RR SES EUER IARE FREUE UE AE 11 2 1 Clock Control and Low Power States sssssssssssssssseee emnes 11 2 1 1 Core Low Power State Description 13 2 111 Gore CO EE 13 2 1 1 2 Core C1 AutoHALT Powerdown State 13 2 1 1 3 Core C1 MWAIT Powerdown State 14 2 1 1 4 Core C2 Eug ET 14 2 1 1 5 COKE C3 EE 14 2 1 1 6 Core C4 State os oda ERE RO Ee YAT T DUE 14 2 1 2 Package Low Power State 5 e 14 2 1 2 1 Normal State em e be RR VERRE KR EUER ELA RUE 14 2 1 2 2 Stop Grant State Kn Er tenors 15 2 1 2 3 Stop Grant Snoop State sess nennen nnn 15 211 2 4 EE EE 15 2 1 2 5 Deep Sleep State NEE ERENNERT x Rr ee 16 2 1 2 6 Deeper Gle
27. 5 50 55 Q 11 14 Vin Input High Voltage 0 82 1 05 1 20 V 3 6 Vu Input Low Voltage 0 10 0 0 55 V 2 4 VoH Output High Voltage 0 90 Vccp 1 10 V 6 Datasheet Electrical Specifications n tel Table 9 AGTL Signal Group DC Specifications Sheet 2 of 2 Termination Resistance Rrr A Address 45 50 55 Q 7 12 Termination Resistance Rrr p Data 45 50 55 Q 7 13 Termination Resistance Control 45 50 55 Q 7 14 Buffer On Resistance Address 8 25 8 33 12 25 Q 5 12 Buffer On Resistance Row p Data 8 25 8 33 12 25 Q 5 13 Buffer On Resistance RON Cntri Control 8 25 8 33 12 25 Q 5 14 lu Input Leakage Current 100 HA Cpad Pad Capacitance 1 80 2 30 2 75 pF NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Vip is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vig and Vou may experience excursions above Vccp However input signal drivers must comply with the signal quality specifications 5 This is the pulldown driver resistance Refer to processor I O Buffer Models for I V characteristics Measured at 0 31 Vccp Roy min 0 418 Rmn Ron typ 0 455 Rm Ron max 0 527 Rz1 Rr typical value of 55 Q is used for Roy typ min max calculation
28. 6 D 2 Source Synch Output G5 BPRI Clock Input Common Input Common Input S SSES Clock Output G6 ule Clock Output F2 VSS Power Other G21 VCCP Power Other Common Input F3 RS 0 Clock Input G22 D 3 Source Synch Output FA RS 1 common Input G23 VSS Power Other Input F5 VSS Power Other G24 Ss Source Synch Output F6 CMos Input G25 D 5 Source Synch DUE F7 VCC Power Other G26 VSS Power Other F8 GTLREF CO CMOS Input NTROL Output H1 ADS Common Input Clock Output F9 VCC Power Other Input F10 VCC Power Other H2 REQI1 Source Synch Output F11 VSS Power Other H3 VSS Power Other F12 VCC Power Other ur F13 VSS Power Other p F14 vcc Power Other H5 DEFER CE Input EIS NEE Power Other H6 vss Power Other F16 v55 Power Other H21 VSS Power Other F17 VCC Power Other Input H22 D 12 Source Synch F18 vcc Power Other hel Output F19 VSS Power Other H23 D 15 Source Synch Geng utput F20 VCC Power Other H24 VSS Power Other Common Input F21 DRDY Clock Output H25 DINV O Source Synch ees utput F22 VSS Power Other i U npu Input H26 DSTBP 0 Source Synch Output F23 D 4 Source Synch o utput j U npu 11 9 4 Source Synch F24 D 1 Source Synch SE Output 12 VSS Power Other F25 VSS Power Other Input Input 13 REQ 3 Source Synch Output F26 D 13 Source Synch o utput i y npu G1 VSS Power Other m AL3 Source Synch Output 15 VSS Power Other 53 54 intel Package Mechanical Specifications and Pin Information
29. 9 of 9 Name Type Description TEST1 TEST2 TESTS Refer to the appropriate platform design guide for further TEST1 TEST4 Input TEST2 TEST3 TESTA TEST5 TEST6 and TEST7 termination TESTS requirements and implementation details TEST6 TEST7 The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the THERMTRIP Output normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 125 C This is signalled to the system by the THERMTRIP Thermal Trip pin THRMDA Other Thermal Diode Anode THRMDA_2 Other Thermal Diode Anode of the second die THRMDC Other Thermal Diode Cathode THRMDC_2 Other Thermal Diode Cathode of the second die TMS Input TMS Test Mode Select is a J TAG specification support signal used by debug tools TRDY Target Ready is asserted by the target to indicate that it TRDY Input is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST p must be driven low during power on Reset VCC Input Processor core power supply VCCA Input VCCA provides isolated power for the internal processor core PLLs VCCP Input Processor I O Power Supply VCCSENSE to
30. A 6 Cpad1 Pad Capacitance 1 80 2 30 2 75 pF 7 Cpad2 Pad Capacitance for CMOS 0 95 12 1 45 pF 8 Input NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccp referred to in these specifications refers to instantaneous Vccp 3 Refer to the processor I O Buffer Models for I V characteristics 4 Measured at 0 1 Vccp 5 Measured at 0 9 Vccp 6 For Vin between 0 V and Vccp Measured when the driver is tristated 7 Cpad1 includes die capacitance only for DPRSTP DPSLP PWRGOOD No package parasitics are included 8 Cpad2 includes die capacitance for all other CMOS input signals No package parasitics are included Table 11 Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vou Output High Voltage Vccp 596 Vccp Vccpt 596 V 3 VoL Output Low Voltage 0 0 20 V lo Output Low Current 16 50 mA 2 lio Output Leakage Current 200 pA 4 Cpad Pad Capacitance 1 80 2 30 2 75 pF 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 V 3 Von is determined by value of the external pull up resistor to Vccp Refer to the appropriate 36 platform design guide for details For Vin between 0 V and Voy Cpad includes die capacitance only No package parasitics are included Datasheet m e Package Mechanical Specifications and Pin I nformation n tel 4 4 1 Datasheet
31. APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of both FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock PRDY Output Probe Ready signal used by debug tools to determine processor debug readiness PREQ Input Probe Request signal used by debug tools to request debug operation of the processor 62 Datasheet m e Package Mechanical Specifications and Pin I nformation n tel Table 14 Datasheet Signal Description Sheet 7 of 9 Name Type Description PROCHOT Input Output As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if en
32. B14 VCC Power Other AA6 TDI CMOS Input AB15 VCC Power Other AAT BR1 Common Input AB16 VSS Power Other Clock Output AB17 VCC Power Other AA8 RSVD Reserved AB18 VCC Power Other AA9 VCC Power Other AB19 VSS Power Other AA10 VCC Power Other AB20 VCC Power Other AA11 VSS Power Other Datasheet 49 50 intel Package Mechanical Specifications and Pin Information Table 13 Pin Listing by Pin Table 13 Pin Listing by Pin Number Number Pin Signal Pin Signal Pin Name Buffer Direction Pin Name Buffer Direction Type Type Input Common AB21 D 52 Source Synch Output AD1 BPM 2 Clock Output AB22 D 51 Source Synch Dot AD2 925 Fower Other Common AB23 VSS Power Other AD3 BPM 1 Clock Output AB24 D 33 Source Synch Common Input Output Clock Output AB25 D 47 Source Synch ADS vss Power Other AD6 CMOS Output AB26 VSS Power Other AD7 VCC Power Other Common ACl PREQ Clock Input 8 VSS Power Other AD9 VCC Power Other PRDY ae Output AD10 VCC Power Other AS EE FEST AD11 VSS Power Other Common Input ACA BPM 3 Clock Output AD12 VCC Power Other ACS TCK CMOS Input AD13 VSS Power Other AC6 VSS Power Other AD14 VCC
33. ESET will cause the processor core to immediately initialize itself Core C4 State Individual cores of the quad core processor can enter the C4 state by initiating a P_LVL4 or P LVL5 I O read to the P BLK or an MWAIT C4 instruction The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state The only difference is that if all processor cores are in C4 the central power management logic will request that the entire processor enter the Deeper Sleep package low power state see Section 2 1 2 6 Package Low Power State Descriptions Normal State This is the normal operating state for the processor The processor remains in the Normal state when at least one of its cores is in the CO C1 AutoHALT or C1 MWAIT state Datasheet m Low Power Features n tel 2 1 2 2 2 1 2 3 2 1 2 4 Datasheet Stop Grant State When the STPCLK pin is asserted each core of the quad core processor enters the Stop Grant state within 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Processor cores that are already in the C2 C3 or C4 state remain in their current low power state When the STPCLK pin is deasserted each core returns to its previous core low power state Since the AGTL signal pins receive power from the FSB these pins should not be driven allowing the level to return to Vccp for minimum power drawn by the termination resistors in th
34. Enhanced Intel SpeedStep Technology Multiple voltage and frequency operating points provide optimal performance at the lowest power Voltage and frequency selection is software controlled by writing to processor MSRs f the target frequency is higher than the current frequency Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the Vcc is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition completes The processor controls voltage ramp rates internally to ensure glitch free transitions Low transition latency and large number of transitions possible per second Processor core including L2 cache is unavailable for up to 10 ms during the frequency transition The bus protocol BNR mechanism is used to block snooping Improved Intel Thermal Monitor mode When the on die thermal sensor indicates that the die temperature is too high the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR The processor waits for a fixed time period If the die temperature is down to acceptable levels an up transition to the previous frequency and volt
35. F12 VCC Power Other B23 BSEL 1 CMOS Output AF13 VSS Power Other B24 VSS Power Other AF14 VCC Power Other B25 THRMDC Power Other AF15 VCC Power Other B26 VCCA Power Other AF16 VSS Power Other RESET Input AF17 VCC Power Other C2 VSS Power Other AF18 VCC Power Other 51 52 intel Package Mechanical Specifications and Pin Information Table 13 Pin Listing by Pin Table 13 Pin Listing by Pin Number Number Pin Signal Pin Signal Pin Name Buffer Direction Pin Name Buffer Direction Type Type C3 TEST7 Test D15 VCC Power Other CA IGNNE CMOS Input D16 VSS Power Other C5 VSS Power Other D17 VCC Power Other C6 LINTO CMOS Input D18 VCC Power Other c7 ey P Open Drain Output D19 VSS Power Other D20 ERR Open Drain Output C8 VSS Power Other i U npu C9 VCC Power Other Der PROCHOT Open Drain Output C10 VCC Power Other D22 GTLREF_2 Power Other Input C11 VSS Power Other D23 VSS Power Other C12 VCC Power Other Common Input D24 DEWR Clock Output C13 VCC Power Other D25 TEST2 Test C14 VSS Power Other D26 VSS Power Other C15 VCC Power Other Common Input C16 VSS Power Other El DBSY Clock Output C17 VCC Power Other mm zs C18 VCC Power Other C19 VSS Power Other F3 bin Power
36. Intel Core 2 Extreme Quad Core Mobile Processor and Intel Core 2 Quad Mobile Processor on 45 nm Process Datasheet For platforms based on Mobile Intel 4 Series Express Chipset Family January 2009 Document Number 320390 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATI NG TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to chang
37. OS signals are required to be asserted for more than four BCLKs for the processor to recognize them See Section 3 10 for DC specifications for the CMOS signal groups Maximum Ratings Table 6 specifies absolute maximum and minimum ratings only and these lie outside the functional limits of the processor Only within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded At conditions exceeding the absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Sym
38. Other Common Input C20 DBR CMOS Output E4 HITM Clock Output C21 5 2 CMS Output E5 DPRSTP cmos Input C22 VSS Power Other Ce VSS Power Other C23 TESTI Test E7 VCC Power Other cee TESTS is E8 VSS Power Other C25 VSS Power Other E9 VCC Power Other C26 VCCA Power Other E10 VCC Power Other Br MSS Power Other E11 VSS Power Other D2 RSVD Reserved E12 VCC Power Other D3 TDO_M Open Drain Output E13 VCC Power Other D4 5 Power Other E14 VSS Power Other D5 STPCLK CMOS Input E15 VCC Power Other D6 PWRGOOD CMOS Input E16 vss Power Other aid SLP Input E17 VCC Power Other D8 Reserved E18 VCC Power Other D9 vec Power Other E19 VSS Power Other D10 VCC Power Other E20 VCC Power Other D11 VSS Power Other E21 VSS Power Other D12 VCC Power Other Input E22 D O Source Synch D13 VSS Power Other Output D14 VCC Power Other Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 13 Pin Listing by Pin Table 13 Pin Listing by Pin Number Number Pin Signal Pin Signal Pin Name Buffer Direction Pin Name Buffer Direction Type Type Input Common E23 D 7 Source Synch Output G2 TRDY Clock Input E24 vss Power Other G3 RSI2 4 ME Input Input E25 D 6 s Source Synch Output G4 VSS Power Other Input Common E2
39. P vss D 23 DI211 vss N VCCP D 16 4 VSS DINVI1 amp DI31 VSS P VSS D 26 DI25 amp VSS pi24j D 18 4 R VCCP vss D 19 2814 vss SE T VCCP DI371 VSS DI27 amp D 30 VSS u VSS DINVI2 amp DI39 1 vss DI38 ott v VCCP VSS D 36 amp DI34 VSS 3514 w VCCP DI411 VSS D 43 amp D 44 vss Y vss 321 D 42 vss pi4ope PSNI vss vss vec vec vss vcc D 50 vss D 45 D 46 vss Ed AB vcc vcc vss vec vec vss vcc DI52 amp DI511 VSS D 33 amp 4714 VSS AC vss vcc vss vec vec vss P Se vss 60 4 DI63 vss D 57 4 D 53 4 vec vss vec vec vss 5413 DIS vss 611 D 49 amp vss GTLREF AE vss vcc vss vec vec vss D 58 DI 55 amp VSS pi48 amp PSTBNI3 vss AF vcc vss vec vec vss VSS piezl Drseje DSTEPIS vss TESTA 14 15 16 17 18 19 20 21 22 23 24 25 26 Datasheet intel lt lt m gt 5 BPD mnm 41 42 intel Package Mechanical Specifications and Pin I nformation Table 12 Pin Listing by Pin Name Table 12 Pin Listing by Pin Name Pin Pin Signal A S Pin Pin Signal n r Name Buffer Type Direcuon Name Buffer Type Direction A20M A6 CMOS Input A 35 AA3 S
40. Power Other ACT VCC Power Other AD15 VCC Power Other AC8 RSVD Reserved AD16 VSS Power Other ACO VCC Power Other AD17 VCC Power Other AC10 VCC Power Other ROS VCG Power Other AC11 VSS Power Other ABIS p vas Power Other Input AC12 VCC Power Other AD20 D 54 Source Synch Output AC13 VCC Power Other Input AD21 D 59 Source Synch p AC14 VSS Power Other Output AC15 VCC Power Other AD22 VSS Power Other AC16 VSS Power Other Input AD23 D 61 Source Synch Output AC17 VCC Power Other i U npu AC18 VCC Power Other AD24 D 49 Source Synch Output AC19 VSS Power Other AD25 VSS Power Other AC20 DINVI31 Source Synch Bul AD26 GTLREF Power Other Input VSS Power Other AC21 VSS Power Other AE2 VID 6 CMOS Output Input AC22 6014 Source Synch Output AE3 VIDI4 CMOS Output AE4 VSS Power Other AC23 D 63 Source Synch AB p 5 VID 2 CMOS Output AC24 VSS Power Other AEG PSI CMOS Output AC25 D 57 Source Synch DUE AE7 VSSSENSE Power Other Output Common Input AC26 D 53 Source Synch Gen BPM_2 3 Clock Output utput Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 13 Pin Listing by Pin Table 13 Pin Listing by Pin Number Number Pin Signal Pin
41. RMDC_2 v3 Thermal diode cathode of the second die Thermal Diode Parameters Using Transistor Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 m 200 uA 1 lE Emitter Current 5 200 uA no Transistor deality 0 997 1 001 1 008 3 4 Beta 0 1 0 4 0 5 Rr Series Resistance 3 0 4 5 7 0 Q NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized across a temperature range of 50 100 C 3 Not 100 tested Specified by design characterization 4 The ideality factor nQ represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current lc lg e 9Vae o T 1 where ls saturation current q electronic charge Ver voltage across the transistor base emitter junction same nodes as VD k Boltzmann Constant and T absolute temperature Kelvin Intel Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC Thermal Control Circuit when the processor silicon reaches its maximum operating temperature The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active With a properly designed and characterized thermal so
42. S TMS TRST vr vss vcc vcc vss vcc vss PREQ PRDY amp vss PPMII ro VSS RSVD vec VSS vcc 2 AD BPM 2 amp vss PPMIM BPMIO vss vibroj vec VSS VSS vss A vss viote vss VIDI2 psi s ese Bigl vec vec vss vcc vcc 2 TESTS vss VIDIS VIDI3 VIDI1 vss XN vss VSS vss 2 1 2 3 4 5 6 7 8 9 10 11 12 13 40 Datasheet Package Mechanical Specifications and Pin Information Figure 9 Quad Core Processor Pinout Top Package View Right Side 14 15 16 17 18 19 20 21 22 23 24 25 26 a vss vec vss vec vec vss vcc BcLKI1 Scuto VSS THRMDA vss TEST6 B vcc vec vss vec vec vss vcc VSS BSEL 1 VSS THRMDC VCCA c vcc vss vec vcc vss DBR 2 VSS TESTI TEST3 VSS VCCA D vec vcc vss vec vcc vss ieRR amp PROCHOT ctirer 2 vss DPWR TEST2 VSS vss vec vss vec vec vss VCC VSS DI7 VSS Gas vec vec vss vec vec vss VCC DRDY VSS 4 4 Eer VSS D 13 4 G VCCP D 3 4 VSS DL9 DI5 VSS H vss D 12 14 D 15 vss Dinvroj DSTEPI J VCCP vss 11 4 DI10 vss gru K VCCP 1414 VSS D 8 amp D 17 4 VSS L VSS D 22 DI20 4 vss D 29 4 Boke M VCC
43. SC ENABLES MSR This Extended Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and upon exit will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency The transition to the lowest operating point or back to the original software requested point may not be instantaneous Furthermore upon very frequent transitions between active and idle states the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases FSB Low Power Enhancements The processor incorporates FSB low power enhancements BPRI control for address and control input buffers Dynamic Bus Parking Dynamic On Die Termination disabling e Low Vccp 1 0 termination voltage The processor incorporates the DPWR signal that controls the data bus input buffers on the processor The DPWR signal disables the buffers when not used and activates them only when data bus activity occurs resulting in significant power savings with no performance impact BPRI control also allows the processor address and control input buffers to be turned off when the BPRI signal is inactive Dynamic Bus Parking al
44. SLP IGNNE INIT CMOS Input Asynchronous LINTO INTR LINT1 NMI PWRGOOD SMI SLP STPCLK Open Drain Output Asynchronous FERR IERRZ THERMTRIP Open Drain I O Asynchronous PROCHOT CMOS Output Asynchronous PSI VID 6 0 BSEL 2 0 Synchronous CMOS Input to TCK TCK M TMS TRST Synchronous Open Drain Output to TCK TDO TDO M FSB Clock Clock BCLK 1 0 COMP 3 0 DBR 2 GTLREF GTLREF 2 RSVD Power Other TEST2 TEST1 THERMDA THERMDA 2 THERMDC THERMDC 2 VCC VCCA VCCP Vcc 5 Vss sENSE NOTES 1 Refer to Chapter 4 for signal descriptions and termination requirements 2 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 BPM 2 1 BPM_2 1 and PRDY are AGTL output only signals PROCHOT signal type is open drain output and CMOS input 5 On die termination differs from other AGTL signals Datasheet m Electrical Specifications n tel 3 8 3 9 Table 6 Datasheet CMOS Signals CMOS input signals are shown in Table 5 Legacy output FERR IERR and other non AGTL signals THERMTRIP and PROCHOT use Open Drain output buffers These signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the CM
45. SS E24 Power Other VSS P24 Power Other VSS F2 Power Other VSS R2 Power Other VSS F5 Power Other VSS R5 Power Other VSS F11 Power Other VSS R22 Power Other VSS F13 Power Other VSS R25 Power Other VSS F16 Power Other VSS TL Power Other VSS F19 Power Other VSS T4 Power Other VSS F22 Power Other VSS T23 Power Other VSS F25 Power Other VSS T26 Power Other VSS G1 Power Other VSS 03 Power Other VSS G4 Power Other VSS U6 Power Other VSS G23 Power Other VSS U21 Power Other VSS G26 Power Other VSS U24 Power Other VSS H3 Power Other VSS V2 Power Other VSS H6 Power Other VSS v5 Power Other VSS H21 Power Other VSS V22 Power Other VSS H24 Power Other VSS v25 Power Other VSS 12 Power Other VSS WI Power Other VSS 15 Power Other VSS WA Power Other VSS 122 Power Other VSS W23 Power Other VSS J25 Power Other VSS W26 Power Other VSS K1 Power Other VSS Y3 Power Other VSS K4 Power Other VSS Y6 Power Other VSS K23 Power Other VSS Y21 Power Other VSS K26 Power Other VSS Y24 Power Other VSS L3 Power Other VSSSENSE AE7 Power Other Output VSS L6 Power Other Datasheet Package Mechanical Specifications and Pin Information intel Table 13 Pin Listing by Pin Table 13 Pin Listing by Pin Number Number Pin Signal Pin Signa
46. Signal Pin Name Buffer Direction Pin Name Buffer Direction Type Type AE9 VCC Power Other AF19 VSS Power Other AE10 VCC Power Other AF20 VCC Power Other AE11 VSS Power Other AF21 VSS Power Other BEDA MES Power Other AF22 D 62 Source Synch AE13 VCC Power Other Input AE14 vss Power Other AF23 D 56 Source Synch Output AE15 VCC Power Other AF24 DSTBP 3 Source Synch cM AE16 VSS Power Other urpu AE17 VCC Power Other AF25 VSS Power Other AE18 VCC Power Other AF26 TESTA dest Common Input AE19 VSS Power Other B2 BPM_2 2 Clock Output AE20 VCC Power Other B3 INIT CMOS Input Input AE21 D 58 Source Synch Output B4 LINT1 CMOS Input Input B5 DPSLP CMOS Input AE22 D 55 Source Synch p Output B6 VSS Power Other AE23 VSS Power Other B7 VCC Power Other AE24 D 48 Source Synch pat B8 VSS Power Other utput 7 B9 VCC Power Other npu AE25 DSTBN 3 Source Synch Output B10 VCC Power Other AE26 VSS Power Other 11 VSS Power Other AF1 TEST5 Test B12 VCC Power Other AF2 VSS Power Other B13 VSS Power Other AF3 VID 5 CMOS Output B14 VCC Power Other AF4 VID 3 CMOS Output B15 VCC Power Other AF5 VID 1 CMOS Output B16 VSS Power Other AF6 VSS Power Other B17 VCC Power Other AF7 VCCSENSE Power Other B18 VCC Power Other AF8 VSS Power Other B19 VSS Power Other AF9 VCC Power Other B20 VCC Power Other AF10 VCC Power Other B21 VSS Power Other AF11 VSS Power Other B22 BSEL 0 CMOS Output A
47. abled The TCC will remain active until the system deasserts PROCHOT By default PROCHOT is configured as an output The processor must be enabled via the BIOS for PROCHOT to be configured as bidirectional Refer to the appropriate platform design guide for termination requirements This signal may require voltage translation on the motherboard PSI Output Processor Power Status Indicator signal This signal is asserted when the processor is both in the normal state HFM to LFM and in lower power states Deep Sleep and Deeper Sleep PWRGOOD REQ 4 0 Input Input Output PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal remains low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Rise time and monotonicity requirements are shown in Table 29 Figure 21 illustrates the relationship of PWRGOOD to the RESET signal PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 29 and be followed by a 2 ms minimum RESET pulse The PWRGOOD signal must be supplied t
48. age point occurs An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management Enhanced thermal management features Digital Thermal Sensor and Out of Specification detection ntel Thermal Monitor 1 TM1 in addition to Intel Thermal Monitor 2 TM2 in case of unsuccessful TM2 transition Quad core thermal management synchronization Each core in the quad core processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology but all cores must operate at the same voltage The processor has performance state coordination logic to resolve frequency and voltage requests from the four cores into a single voltage request for the package as a whole If all cores request the same frequency and voltage then the processor will transition to the requested common frequency and voltage 2 3 Extended Low Power States Extended low power states CXE optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state Instead of directly transitioning into the package low power low power state the enhanced package low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest Datasheet 17 m e n tel Low Power Features Note Caution Caution 2 4 18 operating point Upon receiving
49. as a control signal for a circuit that will automaticlly switch between Dual Core and quad core modes HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Either FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall that can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by the processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep ERR asserted until the assertion of RESET BINIT or INIT Datasheet 61 intel Table 14 Package Mechanical Specifications and Pin I nformation Signal Description Sheet 6 of 9 Name Type Description 4 Input IGNNEZ Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If GNNE is deasserted the processor generates an exception on a non control floating point instruction if a previous floating point instruction caused an error GNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signa
50. ation When TM1 is enabled and a high temperature situation exists the clocks will be modulated by alternately turning the clocks off and on at a 50 duty cycle Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase Once the temperature has returned to a non critical level modulation ceases and TCC goes inactive A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the trip point The duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardware software drivers or interrupt handling routines Processor performance will be decreased by the same amount as the duty cycle when the TCC is active When TM2 is enabled and a high temperature situation exists the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM When the processor temperature drops below the critical level the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point Intel recommends TM1 and TM2 be enabled on the processors TM1 and TM2 can co exist within the processor If both TM1 and TM2 bits are enabled in the auto throttle MSR TM2 takes precedence over TM1 However if Force TM1 over TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below the maximum operating tempera
51. bol Parameter Min Max Unit Notes TsTORAGE Processor Storage Temperature 40 85 2 3 4 Voc Any Processor Supply Voltage with Respect 0 3 1 45 v to Vss AGTL Buffer DC Input Voltage with VinAGTL Respect to Veg 0 1 1 45 V CMOS Buffer DC Input Voltage with Respect Vinasynch_CMOS pect 0 1 1 45 V to Vss NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 3 This rating applies to the processor and does not include any tray or packaging 4 Failure to adhere to this specification can affect the long term reliability of the processor 29 Table 7 30 n tel Electrical Specifications Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Table 5 for the pin signal definitions and signal pin assignments The table below lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages The Highest Frequency Mode
52. ccurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus Refers to the interface between the processor and system core logic also FSB known as the chipset components AGTL Advanced Gunning Transceiver Logic Used to refer to Assisted GTL signaling technology on some Intel processors Introduction Term Definition Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not Storage be connected to any supply voltages have any I Os biased or receive any Conditions clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Enhanced Intel SpeedStep Technology Technology that provides power management capabilities to laptops Processor Core Processor core die with integrated L1 and L2 cache All AC timing and signal integrity specifications are at the pads of the
53. ch o utput DINV 3 AC20 Source Synch Output Input REQ 1 H2 Source Synch Output DPRSTP E5 CMOS Input Input DPSLP amp B5 CMOS Input REQ 2 K2 Source Synch Output Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Table 12 Pin Listing by Pin Name Table 12 Pin Listing by Pin Name Gone T B ee Direction iama p aside Direction REQI3 13 Source Synch SE VCC A15 Power Other VCC A17 Power Other REQ 4 L1 Source Synch tput VCC A18 Power Other RESET C1 Common Clock Input VCC A20 Power Other RS 0 F3 Common Clock Input VCC AA9 Power Other RS 1 F4 Common Clock Input vcc AA10 Power Other RS 2 G3 Common Clock Input VCC AA12 Power Other RSVD D2 Reserved VCC AA13 Power Other RSVD AA8 Reserved VCC AA15 Power Other RSVD AC8 Reserved VCC AA17 Power Other RSVD D8 Reserved VCC AA18 Power Other SLP D7 CMOS Input VCC AA20 Power Other SMI X A3 CMOS Input VCC AB7 Power Other STPCLK D5 CMOS Input VCC AB9 Power Other TCK AC5 CMOS Input VCC AB10 Power Other TDI AAG CMOS Input VCC AB12 Power Other TDI M F6 CMOS Input VCC AB14 Power Other TDO AB3 Open Drain Output AB15 Power Other TDO_M D3 O
54. ction A 35 3 Input Output A 35 3 Address define a 239 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents on the processor FSB A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before RESET 2 is deasserted ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTB O A 35 17 ADSTB 1 BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Output BNR Bloc
55. die temperature Thermal Diode Intel Thermal Monitor Digital Thermal Sensor The Intel Thermal Monitor detailed in Section 5 1 2 must be used to determine when the maximum specified processor junction temperature has been reached Thermal Diode Intel s processors utilize an SMBus thermal sensor to read back the voltage current characteristics of a substrate PNP transistor Since these characteristics are a function of temperature in principle one can use these parameters to calculate silicon temperature values For older silicon process technologies i e Intel Core 2 Duo mobile processors on 65nm process it is possible to simplify the voltage current and temperature relationships by treating the substrate transistor as though it were a simple diffusion diode In this case the assumption is that the beta of the transistor does not impact the calculated temperature values The resultant diode model essentially predicts a quasi linear relationship between the base emitter voltage differential of the PNP transistor and the applied temperature one of the proportionality constants in this relationship is processor specific and is known as the diode ideality factor Realization of this relationship is accomplished with the SMBus thermal sensor that is connected to the transistor The quad core processor however is built on Intel s advanced 45 nm processor technology Due to this new highly advanced processor technology it is
56. e of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Datasheet
57. e without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel4 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Enhanced Intel SpeedStep Technology for specified units of this processor are available See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and
58. elow the thermal trip point If Thermal Monitor automatic mode is disabled the processor will be operating out of specification Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 125 C At this point the THERMTRI P signal will go active THERMTRIP activation is independent of processor activity and does not generate any bus cycles When THERMTRIP is asserted the processor core voltage must be shut down within the time specified in Chapter 3 In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor DTS that can be read via an MSR no I O interface Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Thermal Monitor The DTS is only valid while the processor is in the normal operating state the Normal package level low power state Unlike traditional thermal devices the DTS outputs a temperature relative to the
59. enpGtate memes 16 2 2 Enhanced Intel SpeedStep Technology sssssssssseee mms 17 2 3 Extended Low Power States 17 2 4 FSB Low Power Enbancements eem 18 2 4 1 Dual Intel Dynamic Acceleration sss 19 2 5 Processor Power Status Indicator PSI 2 Signal 19 3 Electrical Specifications ouod o ee a Ae RUNE Me ee Enn nnna 21 3 1 Power and Ground Pins ssssssssssssssssees ennemis 21 3 2 Decoupling Guidelines siiven te eee ee tenets seen senes 21 3 2 0 VCC EISE EDD aie anette seaman 21 3 2 2 FSB Decoupling gesi etse rx EE EE aes dee 21 3 2 3 FSB Clock BCLK 1 0 and Processor Clockimg sese 21 3 3 Voltage Identification and Power Sequencing 22 3 4 Catastrophic Thermal Protection 26 3 5 Reserved and UnUSEd Pins iced eese eret RER Deed EENEN EOE Erion E 26 3 6 FSB Frequency Select Signals BSELUT3ZOI eae mnm 27 3 77 FSB Signal Gro ps EE 27 3 9 e ee ET EE 29 3 9 Maximu mcRatLlhids EE 29 3 10 Processor DC Specifications ccc een eee eese meses nns 30 4 Package Mechanical Specifications and Pin Information 37 4 1 Package Mechanical Specifications sss nemen 37 4 2 X Processor Pinout and Pin Uert 40 5 Thermal Specifications and Design Considerations
60. ep 20 5 A 3 4 Datasheet Electrical Specifications Table 7 Table 8 Datasheet intel Voltage and Current Specifications for the Quad Core Extreme Mobile Processors Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Notes Vcc Power Supply Current Slew Rate E E 600 A us 5 7 at Processor Package Pin Icc for Veca Supply 130 mA l ccp lcc for Vccp Supply before Stable 4 5 A Icc for Vecp Supply after Vcc Stable 2 5 A NOTES T Sone w Kei 10 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State The voltage specifications are assumed to be measured across Vcc sense and Vss sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 100 C Specified at the nominal
61. er Other VCC AF9 Power Other VCC F7 Power Other VCC AF10 Power Other VCC F9 Power Other VCC AF12 Power Other VCC F10 Power Other VCC AF14 Power Other VCC F12 Power Other VCC AF15 Power Other VCC F14 Power Other VCC AF17 Power Other VCC F15 Power Other VCC AF18 Power Other VCC F17 Power Other VCC AF20 Power Other VCC F18 Power Other VCC B7 Power Other VCC F20 Power Other VCC B9 Power Other VCCA B26 Power Other VCC B10 Power Other VCCA C26 Power Other VCC B12 Power Other VCCP G21 Power Other VCC B14 Power Other VCCP J6 Power Other VCC B15 Power Other VCCP 121 Power Other VCC B17 Power Other VCCP K6 Power Other VCC B18 Power Other VCCP K21 Power Other VCC B20 Power Other VCCP M6 Power Other VCC c9 Power Other VCCP M21 Power Other VCC C10 Power Other VCCP N6 Power Other VCC C12 Power Other VCCP N21 Power Other VCC C13 Power Other VCCP R6 Power Other VCC C15 Power Other VCCP R21 Power Other VCC C17 Power Other VCCP T6 Power Other VCC C18 Power Other VCCP T21 Power Other VCC D9 Power Other VCCP V6 Power Other VCC D10 Power Other VCCP V21 Power Other VCC D12 Power Other VCCP w21 Power Other VCC D14 Power Other VCCSENSE AF7 Power Other VCC D15 Power Other VID 0 AD6 CMOS Output VCC D17 Power Other VID 1 AF5 CMOS Output VCC D18 Power Other VID 2 AE5 CMOS Output VCC E7 Power Other VID 3 AF4 CMOS Output VCC E9 Power Other VID 4 AE3 CMOS Output VCC E10 Power Other VID 5 AF3 CMOS Output VCC E12 Power Other VID 6
62. es coincide in a common core low power state the central power management logic ensures the entire processor enters the respective package low power state by initiating a P LVLx P_LVL2 P LVL3 P_LVL4 I O read to the G MCH The processor implements two software interfaces for requesting low power states MWAIT instruction extensions with sub state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor s I O address space The P_LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in reads on the processor FSB The P LVLx I O Monitor address does not need to be set up before using the P LVLx I O read interface The sub state hints used for each P LVLx read can be configured through the 32 MISC ENABLES model specific register MSR If a core encounters a GMCH break event while STPCLK is asserted it asserts the PBE output signal Assertion of PBE when STPCLK is asserted indicates to system logic that individual cores should return to the CO state and the processor should return to the Normal state Figure 1 shows the core low power states and Figure 2 shows the package low power states for the processor Table 2 maps the core low power states to package low power states 11 Figure 1 12 intel Low Power Features Core Low Power States STPCLK STPCLK deasserted asserted STPCLK STPCLK STPCLK asse
63. g cuan Saou TOW CHI OO SLWA aiva 48 030342 fau eV Iv Suid Duden a oz 3 H xvn eo g a v TIviaa 51508 det IF 49 XVN geo d OIsva Ir DISWa 548 51 d S u 5 o vszoo 2ISV8 sz8 ST H alvo lese og z l XVN 9 gt 915 8 SZ TE 9 I D2 DISVE SZ TE l 7 H Ka i aqeisqns bey ed iapun ala a a SLN3H NOD susiswrruw TOSWAS MAIA dOL um MAIA JAIS MAIA WOLLOS v 5 4 d Ze 1 8 i A 7 o H d d d 000000 960066 ERES Ss 1 JE ee pe 2L L e EN d m ii E Fo 6669069 S 000008 ii 9 600000 000000 600099 000000 000000 000000 eeeoos D 000000 j 000000 000000 5 0000000000000 0000009000000 5 0000000000000000000000000 0000000000000000000000000 0000000000000000000000000 0000000000000 0000080000000 9080090000000 0000000000008 Na n f SNId Sr T R T T Tg a H H Fo H NOLLVHOdOO JO 1N3SNOO N3LLTHM YOIYd IHL LNOHLIM Q31HIGOW YO GIAVIdSIC aaonaoudan 435 5 38 LON AVW SLN3LNOD SLI ANY 32N3GIJNOO NI 35 SI LI NOLLVW3OJNI TVLLN3GIJNOO NOILV3Od30OO T31NI SNIVLNOO SIHL D T 10660 z v S 9 Z 8 Datasheet 38 intel
64. gether with VSSSENSE are voltage feedback signals VCCSENSE Output that control the 2 1 mQ loadline at the processor die It should be used to sense voltage near the silicon with little noise VID 6 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the processor The voltage supply for these pins must be valid before VID 6 0 Output the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations See Table 3 for definitions of these pins The VR must supply the voltage that is requested by the pins or disable itself vss Input Processor core ground node VSSSENSE together with VCCSENSE are voltage feedback signals VSSSENSE Output that control the 2 1 mQ loadline at the processor die It should be used to sense ground near the silicon with little noise 65 Table 15 Package Mechanical Specifications and Pin Information New Pins for the Quad Core Mobile Processor 66 Pin Name Pin Description BPM_2 0 N5 BPM_2 3 0 Breakpoint Monitor are breakpoint and performance BPM 2 1 M4 monitor signals of the second die They are outputs from the processor that indicate the status
65. gh internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 3 Failure to do so may result in timing violations or reduced lifetime of the component Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and keep a low interconnect resistance from the regulator to the socket Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states should be provided by the voltage regulator solution depending on the specific system design FSB AGTL Decoupling The processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package Decoupling must also be provided by the system motherboard for proper AGTL bus operation FSB Clock BCLK 1 0 and Processor Clocking BCLK 1 0 direct
66. ied in the RESET pin specification then the processor will reset itself ignoring the transition through the Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin See Section 2 1 2 5 While the processor is in the Sleep state the SLP pin must be deasserted if another asynchronous FSB event needs to occur Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP pin while in the Sleep state BCLK may be stopped during the Deep Sleep state for additional platform level power savings BCLK stop restart timings on appropriate GMCH based platforms with the CK505 clock chip are as follows Deep Sleep entry the system clock chip may stop tristate BCLK within 2 BCLKs of DPSLP assertion It is permissible to leave BCLK running during Deep Sleep Deep Sleep exit the system clock chip must drive BCLK to differential DC levels within 2 3 ns of DPSLP deassertion and start toggling BCLK within 10 BCLK periods To re enter the Sleep state the DPSLP pin must be deasserted BCLK can be re started after DPSLP deassertion as described above A period of 15 microseconds to allow for PLL stabilization mu
67. ins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active low AGTL inputs may be left as no connects if AGTL termination is provided on the processor silicon Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected The TEST1 TEST2 TEST3 TESTA TEST5 TESTO TEST7 pins are used for test purposes internally and can be left as No Connects Datasheet Electrical Specifications intel 3 6 Table 4 3 7 Datasheet FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 These signals should be connected to the clock chip and the appropriate chipset on the platform The BSEL encoding for BCLK 1 0 is shown in Table 4 BSEL 2 0 Encoding for BCLK Frequency BSEL 2 BSEL 1 5 BCLK Frequency L L L 266 MHz L H RESERVED L H H RESERVED L H L RESERVED H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections AGTL input signals have differential input buffers that use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output
68. is state In addition all other input pins on the FSB should be driven to the inactive state RESET causes the processor to immediately initialize itself but the processor will stay in Stop Grant state When RESET is asserted by the system the STPCLK SLP DPSLP and DPRSTP pins must be deasserted prior to RESET deassertion as per AC Specification T45 When re entering the Stop Grant state from the Sleep state STPCLK should be deasserted after the deassertion of SLP as per AC Specification T75 While in Stop Grant state the processor will service snoops and latch interrupts delivered on the FSB The processor will latch SMI INIT and LINT 1 0 interrupts and will service only one of each upon return to the Normal state The PBE signal may be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt or Monitor event latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that the entire processor should return to the Normal state A transition to the Stop Grant Snoop state occurs when the processor detects a snoop on the FSB see Section 2 1 2 3 A transition to the Sleep state see Section 2 1 2 4 occurs with the assertion of the SLP signal Stop Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop Grant s
69. k Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BPM 2 1 BPM 3 0 Output Input Output BPM 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all processor FSB agents This includes debug or performance monitoring tools Datasheet 57 m 8 n tel Package Mechanical Specifications and Pin I nformation Table 14 Signal Description Sheet 2 of 9 Name Type Description BPM_2 3 0 Breakpoint Monitor are breakpoint and BPM 2 1 Output performance monitor signals of the second die They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor BPM_2 0 3 2 Input performance BPM_2 3 0 should connect the appropriate pins of Output all processor FSB agents This includes debug or performance monitoring tools Bus Priority Request is used to arbitrate for ownership of the FSB It must connect the appropriate pins of both FSB agents Observing BPRI active as asserted by the priority agent causes Input the other agent to stop issuing new requests
70. l Pin Name Buffer Direction Pin Name Buffer Direction Type Type A2 VSS Power Other AA12 VCC Power Other A3 SMI 4 CMOS Input AA13 VCC Power Other A4 VSS Power Other AA14 VSS Power Other A5 FERR Open Drain Output AA15 VCC Power Other A6 A20M CMOS Input AA16 VSS Power Other A7 VCC Power Other AA17 VCC Power Other A8 VSS Power Other AA18 VCC Power Other A9 VCC Power Other AA19 VSS Power Other A10 VCC Power Other AA20 VCC Power Other All VSS Power Other AA21 D 50 Source Synch mod A12 VCC Power Other AA22 VSS Power Other A13 VCC Power Other Input A14 VSS Power Other AA23 D 45 Source Synch Output A15 VCC Power Other AA24 D 46 Source Synch put A16 VSS Power Other H A17 VCC Power Other AA25 VSS Power Other A18 VCC Power Other AA26 DSTBP 2 Source Synch pon utput A19 VSS Power Other ABI VSS Power Other A20 VCC Power Other Input AB2 A 34 Source Synch p A21 BCLK 1 Bus Clock Input Output A22 BCLK O Bus Clock Input AB3 TDO Open Drain Output A23 VSS Power Other AB4 VSS Power Other A24 THRMDA Power Other ABS TMS CMOS Input A25 VSS Power Other AB6 TRST CMOS Input A26 TEST6 Test AB7 VCC Power Other AB8 vss Power Other COMP 2 Power Other AE H AB9 VCC Power Other A ys Power Other AB10 VCC Power Other Input AA3 A 35 Source Synch Output AB11 VSS Power Other Input AB12 VCC Power Other AA4 A 33 Source Synch o p utput AB13 VSS Power Other AAS VSS Power Other A
71. l following an input output write instruction it must be valid along with the TRDY assertion of the corresponding input output Write bus transaction INIT Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an input output write instruction it must be valid along with the TRDY assertion of the corresponding input output write bus transaction INIT must connect the appropriate pins of both FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the
72. lows a reciprocal power reduction in GMCH address and control input buffers when the processor deasserts its BRO pin The On Die Termination on the processor FSB buffers is disabled when the signals are driven low resulting in additional power savings The low I O termination voltage is on a dedicated voltage plane independent of the core voltage enabling low I O switching power at all times Datasheet m Low Power Features n tel 2 4 1 2 5 Figure 3 Datasheet Dual I ntel Dynamic Acceleration The processor supports Dual Intel Dynamic Acceleration For any two cores in the quad core processor the Dual Intel Dynamic Acceleration feature allows one core to operate at a higher frequency point while the other core is inactive and the operating system requests increased performance Thus quad core processor could enter Dual Intel Dynamic Acceleration when two cores are idle and the other two are active This higher frequency is called the opportunistic frequency and the maximum rated operating frequency is the ensured frequency Dual Intel Dynamic Acceleration enabling requires exposure via BIOS of the opportunistic frequency as the highest ACPI P state Processor Power Status Indicator PSI 2 Signal The processor incorporates the PSI signal that is asserted when the processor is in 8 reduced power consumption state PSI can be used to improve intermediate and light load efficiency of the voltage regulator resulting in
73. lution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously The Intel Thermal Monitor controls the processor temperature by modulating starting and stopping the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating 69 70 n tel Thermal Specifications and Design Considerations temperature The Intel Thermal Monitor uses two modes to activate the TCC automatic mode and on demand mode If both modes are activated automatic mode takes precedence There are two automatic modes called Intel Thermal Monitor 1 TM1 and Intel Thermal Monitor 2 TM2 These modes are selected by writing values to the MSRs of the processor After automatic mode is enabled the TCC will activate only when the internal die temperature reaches the maximum allowed value for oper
74. ly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio at manufacturing The processor uses a differential clocking implementation 21 II n tel Electrical Specifications 22 Voltage Identification and Power Sequencing The processor uses seven voltage identification pins VID 6 0 to support automatic selection of power supply voltages The VID pins for the processor are CMOS outputs driven by the processor VID circuitry Table 3 specifies the voltage level corresponding to the state of VID 6 0 A1 in the table refers to a high voltage level and a 0 refers to a low voltage level Datasheet Electrical Specifications Table 3 Datasheet Voltage Identification Definition Sheet 1 of 4 VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc V 0 0 0 0 0 0 0 1 5000 0 0 0 0 0 0 1 1 4875 0 0 0 0 0 1 0 1 4750 0 0 0 0 0 1 1 1 4625 0 0 0 0 1 0 0 1 4500 0 0 0 0 1 0 1 1 4375 0 0 0 0 1 1 0 1 4250 0 0 0 0 1 1 1 1 4125 0 0 0 1 0 0 0 1 4000 0 0 0 1 0 0 1 1 3875 0 0 0 1 0 1 0 1 3750 0 0 0 1 0 1 1 1 3625 0 0 0 1 1 0 0 1 3500 0 0 0 1 1 0 1 1 3375 0 0 0 1 1 1 0 1 3250 0 0 0 1 1 1 1 1 3125 0 0 1 0 0 0 0 1 3000 0 0 1 0 0 0 1 1 2875 0 0 1 0 0 1
75. me 2A Instruction Set Reference A M and Volume 2B Instruction Set Reference N Z for more information Core C2 State Individual cores of the quad core processor can enter the C2 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C2 instruction but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK pin is also asserted While in the C2 state the quad core processor will process bus snoops and snoops from the other core The processor core will enter a snoopable sub state not shown in Figure 1 to process the snoop and then return to the C2 state Core C3 State Individual cores of the quad core processor can enter the C3 state by initiating a P 31 0 read to the P BLK or an MWAIT C3 instruction Before entering C3 the processor core flushes the contents of its L1 caches into the processor s L2 cache Except for the caches the processor core maintains all its architectural states in the C3 state The Monitor remains armed if it is configured All of the clocks in the processor core are stopped in the C3 state Because the core s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual core die of quad core processor accesses cacheable memory The processor core will transition to the CO state upon occurrence of a Monitor event SMI INIT LINT 1 0 NMI INTR or FSB interrupt message R
76. me time automatic mode is enabled and a high temperature condition exists automatic mode will take precedence An external signal PROCHOT processor hot is asserted when the processor detects that its temperature is above the thermal trip point Bus snooping and interrupt latching are also active while the TCC is active Datasheet m Thermal Specifications and Design Considerations n tel 5 1 3 Datasheet Besides the thermal sensor and thermal control circuit the Intel Thermal Monitor also includes one ACPI register one performance counter register three MSR and one I O pin PROCHOT All are available to monitor and control the state of the Intel Thermal Monitor feature The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT PROCHOT will not be asserted when the processor is in the Stop Grant Sleep and Deep Sleep low power states hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification the system must initiate an orderly shutdown to prevent damage If the processor enters one of the above low power states with PROCHOT already asserted PROCHOTZ will remain asserted until the processor exits the low power state and the processor junction temperature drops b
77. microarchitecture In this document the Intel Core 2 Extreme quad core processor and Intel Core 2 quad processor are referred to as the processor or quad core processor and the Mobile Intel 4 Series Express Chipset is referred to as the G MCH Key features of the processor include Quad core mobile processor for mobile with enhanced performance Supports Intel architecture with Intel Wide Dynamic Execution Supports L1 cache to cache C2C transfer On die primary 32 kB instruction cache and 32 kB write back data cache in each core 12 MB second level shared cache with Advanced Transfer Cache architecture Streaming SIMD extensions 2 SSE2 streaming SIMD extensions 3 SSE3 supplemental streaming SIMD extensions 3 SSSE3 and SSE4 1 instruction sets Processors are offered at 1066 MHz source synchronous front side bus FSB Advanced power management features including Enhanced Intel SpeedStep Technology Digital thermal sensor DTS Intel 64 architecture Supports Enhanced Intel Virtualization Technology Supports PSI 2 functionality Execute Disable Bit support for enhanced security Half ratio support N 2 for core to bus ratio Terminology Term Definition A symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has o
78. nch BUE D 40 Y25 Source Synch Die D 19 R23 Source Synch dt D 41 W22 Source Synch uut D 1 F24 Source Synch i D 42 23 Source Synch ce D 20 L23 Source Synch D 43 W24 Source Synch eu D 21 M24 Source Synch URN D 44 W25 Source Synch SE D 22 L22 Source Synch D 45 AA23 Source Synch et D 23 M23 Source Synch D 46 AA24 Source Synch 24 4 P25 Source Synch SE D 47 AB25 Source Synch SE D 25 P23 Source Synch SE D 48 AE24 Source Synch ape D 26 P22 Source Synch Dun D 49 AD24 Source Synch ual D 27 T24 Source Synch Geer D 4 F23 Source Synch SE D 28 R24 Source Synch D 50 AA21 Source Synch GE 43 44 intel Package Mechanical Specifications and Pin I nformation Table 12 Pin Listing by Pin Name Table 12 Pin Listing by Pin Name Pin Pin Signal S Pin Pin Signal n r Name Buffer Type Direction Name Buffer Type Direction Input Input D 51 AB22 Source Synch Output DPWR D24 Common Clock Output Input Input D 52 AB21 Source Synch Output DRDY F21 Common Clock Output Input Input D 53 AC26 Source Synch Output DSTBN O J26 Source Synch Output Input Input D 54 AD20 Source Synch Output DSTBN 1 L26 Source Synch Output Input Input D 55 AE22 Source Synch Output DSTBN 2 Y26 Source S
79. no longer possible to model the substrate transistor as a simple diode To accurately calculate silicon temperature one must use a full bi polar junction transistor type model In this model the voltage current and temperature characteristics include an additional process dependant parameter which is known as the transistor beta System designers should be aware that the current thermal sensors on Santa Rosa platforms may not be configured to account for beta and should work with their SMB thermal sensor vendors to ensure they have a part capable of reading the thermal diode in BJT model Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor s automatic mode activation of the thermal control circuit This temperature offset must be taken into account when using the processor thermal diode to implement power management events This offset is different than the diode Toffset value programmed into the processor Model Specific Register MSR Table 17 to Table 18 provide the diode interface and transistor model specifications Datasheet Thermal Specifications and Design Considerations Table 17 Table 18 5 1 2 Datasheet Thermal Diode Interface ntel Signal Name Pin Ball Number Signal Description THERMDA A24 Thermal diode anode THERMDC B25 Thermal diode cathode THERMDA_2 T2 Thermal diode anode of the second die THE
80. nt state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the first die TDI provides the serial input needed for J TAG specification support TDI M Input M Test Data In transfers serial test data into the second die M provides the serial input needed for J TAG specification support Connect to TDO M on the platform TDO Output TDO Test Data Out transfers serial test data out of the second die TDO provides the serial output needed for J TAG specification support TDO M Output TDO M Test Data Out transfers serial test data out of the first die TDO M provides the serial output needed for JTAG specification support Connect to TDI M on the platform 64 Datasheet Package Mechanical Specifications and Pin Information n tel Table 14 Datasheet Signal Description Sheet
81. o the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Request Command must connect the appropriate pins of both FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 0 RESET A Input Asserting the RESET 2 signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least two milliseconds after Vcc and BCLK have reached their proper specifications On observing active RESET both FSB agents will deassert their outputs within two clocks All processor straps must be valid within the specified setup time before RESET is deasserted Refer to the appropriate platform design guide for termination requirements and implementation details There is a 55 Q nominal on die pull up resistor on this signal RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both FSB agents 63 intel Package Mechanical Specifications and Pin I nformation Table 14 Signal Description Sheet 8 of 9 Name Type Description RSVD Reserved No Connect These pins are
82. of breakpoints and programmable BPM_2 2 B2 counters used for monitoring processor performance BPM_2 3 0 should connect the appropriate pins of all processor FSB agents This BPM_2 3 AE8 includes debug or performance monitoring tools Arbitration Request signal for the second die BR1 is connected to the first die within the package allowing two BR1 AA7 dies within quad core parts to artitrite for the bus This pin is fundamentally provided for debug capabilities and should be left as a NC GTLREF_2 D22 GTL reference level for AGTL input pins of the second die This pin can be used as GTLREF_2 disconnect circuit control signal GTLREF_2 maps out to a reserved pin on Intel Core 2 Duo mobile GTLREF CONTROL rg Processor for dual core and quad core interchangeable motherboard GTLREF_CONTROL can be used as a control signal for a circuit that will automaticlly switch between Dual Core and quad core modes RSVD AES These pins are RESERVED and must be left unconnected on the RSVD AA8 board However it is recommended that routing channels to these RSVD D8 pins on the board be kept open for possible future use TDI_M Test Data In transfers serial test data into the second die TDI_M F6 TDI_M provides the serial input needed for J TAG specification support Connect to TDO_M on the platform TDO_M Test Data Out transfers serial test data out of the first die TDO_M 53 TDO_M provides the serial output needed for J TAG specification
83. on cannot be ensured in order completion Assertion of DEFER is normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins of both FSB agents Datasheet 59 intel Package Mechanical Specifications and Pin I nformation Table 14 Signal Description Sheet 4 of 9 60 Name Type Description DINV 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 Assignment To Data Bus Input DINV 3 0 Output Bus Signal Data Bus Signals DINV 3 D 63 48 DINV 2 D 47 32 DINV 1 D 31 16 DINV 0 D 15 0 DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state or DPRSTP Input C6 state To return to the Deep Sleep State DPRSTP must be deasserted DPRSTP is driven by the ICH9M chipset DPSLP when asserted on the platform causes the processor to DPSLP Gart transition from the Sleep State to the Deep Sleep state To return p to the Sleep State DPSLP must be deasserted DPSLP is driven by the ICH9M chipset Input DPWR is a control signal used by the chipset to reduce power on DPWR p the process
84. or data bus input buffers The processor drives this pin Output SH during dynamic FSB frequency switching DRDY Data Ready is asserted by the data driver on each data DRDY Input transfer indicating valid data on the data bus In a multi common Output clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of both FSB agents Data strobe used to latch in D 63 0 Signals Associated Strobe Input D 15 0 DINV O DSTBN O DSTBN 3 0 Output D 31 16 DINV 1 DSTBN 1 D 47 32 DINV 2 DSTBN 2 D 63 48 DINV 3 DSTBN 3 Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV O DSTBP O DSTBP 3 0 4 JEC utput p 31 16 amp DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 D 63 48 DINV 3 DSTBP 3 Datasheet m Package Mechanical Specifications and Pin Information n tel Table 14 Signal Description Sheet 5 of 9 Name Type Description FERR PBE Output FERR Floating point Error PBE Pending Break Event is a multiplexed signal and its meaning is qualified with STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using Microsoft MS DOS type floating point error reporting When STPCLK is
85. ource Synch Output W4 VSS Power Other Input w5 A 28 Source Synch Output Input W6 A 20 Source Synch Output W21 VCCP Power Other Input W22 D 41 Source Synch Output W23 VSS Power Other Input W24 D 43 Source Synch Output Input W25 D 44 Source Synch Output W26 VSS Power Other Input Y1 COMP 3 Power Other Output Input Y2 A 17 Source Synch Output Y3 VSS Power Other Input YA A 29 Source Synch Output Input Y5 A 22 Source Synch Output Y6 VSS Power Other Y21 VSS Power Other Input Y22 D 32 Source Synch Output Input Y23 D 42 Source Synch Output Y24 VSS Power Other Input Y25 D 40 Source Synch Output Input Y26 DSTBN 2 Source Synch Output 56 Datasheet m e Package Mechanical Specifications and Pin I nformation n tel Table 14 Signal Description Sheet 1 of 9 Name Type Description A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an input output write instruction it must be valid along with the TRDY assertion of the corresponding input output Write bus transa
86. ource Synch ee Input A 10 N3 Source Synch Output A 3 14 Source Synch Ste Input A 11 P5 Source Synch Output A 4 L5 Source Synch Output Input A 12 P2 Source Synch Output A 5 LA Source Synch UD Input A 13 L2 Source Synch Output A 6 K5 Source Synch ed Input A 14 P4 Source Synch Output A 7 M3 Source Synch yen Input A 15 P1 Source Synch Output A 8 N2 Source Synch Outpt Input A 16 R1 Source Synch Output A 9I 11 Source Synch Input A 17 Y2 Source Synch Output ADS H1 Common Clock PUE Input A 18 U5 Source Synch Output Input ADSTB 0 Source Synch Output A 19 R3 Source Synch ee utput Input ADSTB 1 V1 Source Synch Output Input A 20 W Source Synch Output BCLK 0 A22 Bus Clock Input 2114 UA Source Synch UE BCLK 1 A21 Bus Clock Input Input BNR E2 Common Clock rh A 22 Y5 Source Synch Output p Input Input BPM 0 AD4 Common Clock Output A 23 U1 Source Synch Output BPM 1 AD3 Common Clock Output Input AL 24 R4 Source Synch Output BPM 2 AD1 Common Clock Output Input A 25 T5 Source Synch BPM 3 AC4 Common Clock Input AL26 T3 Source Synch DE BPM_2 0 N5 Common Clock Output BPM 2 1 M4 Common Clock Output A 27 w2 Source Synch SE 211 id 2 2 4 B2 Common Clock DH Input Output A 28 w5 Source Synch Output BPM 2 3 4 AE8 Common Clock Output A 29 Y4 Source Synch neat BPRI G5 Common Clock
87. p VccurM 45 1 4 TDP Ww Q9000 2 0 GHz amp Vecuem 45 5 6 1 60 GHz amp VecLEM 35 Symbol Parameter Min Typ Max Unit Notes P Auto Halt Stop Grant Power AH at HFM Mee 194 w 2 5 7 PSGNT at LFM Vcc 14 5 Sleep Power Psip at HFM Vcc 18 6 VW 2 5 7 at LFM Vcc 14 1 Deep Sleep Power at HFM Vcc E 7 9 W 2 5 8 at LFM Vcc 7 1 Pppnsip Deeper Sleep Power 4 0 Ww 2 8 Tj Junction Temperature 0 100 S 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached Refer to Section 5 1 for details 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 67 m e n tel Thermal Specifications and Design Considerations Note 5 1 1 68 5 Processor TDP requirements in Intel Dynamic Acceleration mode are lesser than TDP in HFM 6 At Tj of 100 C 7 At Tj of 509C 8 At Tj of 35 C Monitoring Die Temperature The processor incorporates three methods of monitoring
88. pen Drain Output vcc AB17 Power Other TESTI C23 Test VCC AB18 Power Other TEST2 D25 Test VCC AB20 Power Other TEST3 C24 Test vcc AC7 Power Other TEST4 AF26 Test vcc AC9 Power Other TESTS Test VCC AC10 Power Other TEST6 A26 Test VCC AC12 Power Other TEST7 c3 Test VCC AC13 Power Other m Open Drain Suut VCC AC15 Power Other VCC AC17 Power Other THRMDA A24 Power Other VCC AC18 Power Other THRMDA 2 T2 Power Other vcc AD7 Power Other THRMDC B25 Power Other VCC AD9 Power Other THRMDC 2 V3 Power Other VCC AD10 Power Other TMS ABS CMOS Input VCC AD12 Power Other TRDY G2 Common Clock Input vcc AD14 Power Other TRST AB6 CMOS Input VCC AD15 Power Other vec AT Power Other vcc AD17 Power Other 9 Power Other VCC AD18 Power Other VCC A10 Power Other VCC AE9 Power Other A12 Power Other VCC AE10 Power Other A13 Power Other VCC AE12 Power Other 45 46 intel Package Mechanical Specifications and Pin I nformation Table 12 Pin Listing by Pin Name Table 12 Pin Listing by Pin Name Do e Ter A Kadette SE Se Bu Dos Brecon VCC AE13 Power Other VCC E13 Power Other VCC AE15 Power Other VCC E15 Power Other VCC AE17 Power Other VCC E17 Power Other VCC AE18 Power Other VCC E18 Power Other VCC AE20 Power Other VCC E20 Pow
89. processor core Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and 32 Architectures Software Developer s Manuals for more detailed information Intel 04 64 bit memory extensions to the 32 architecture Technology Intel Processor virtualization which when used in conjunction with Virtual Virtualization Machine Monitor software enables multiple robust independent software Technology environments inside a single platform Half ratio support N 2 for Core to Quad core processor supports the N 2 feature which allows having fractional core to bus ratios This feature provides the flexibility of having more frequency options and be able to have products with smaller Bus fein frequency steps TDP Thermal Design Power Vcc The processor core power supply Vss The processor ground Datasheet Introduction L 2 Table 1 Datasheet References intel Material and concepts available in the following documents may be beneficial when reading this document References Document
90. r Other VSS B19 Power Other VSS AC3 Power Other VSS B21 Power Other VSS AC6 Power Other VSS B24 Power Other VSS AC11 Power Other VSS C2 Power Other vss AC14 Power Other VSS C5 Power Other VSS AC16 Power Other VSS c8 Power Other VSS AC19 Power Other VSS C11 Power Other VSS AC21 Power Other VSS C14 Power Other VSS AC24 Power Other VSS C16 Power Other VSS AD2 Power Other VSS C19 Power Other VSS AD5 Power Other VSS C22 Power Other VSS AD8 Power Other VSS C25 Power Other VSS AD11 Power Other VSS D1 Power Other VSS AD13 Power Other VSS D4 Power Other VSS AD16 Power Other VSS D11 Power Other 47 48 intel Package Mechanical Specifications and Pin I nformation Table 12 Pin Listing by Pin Name Table 12 Pin Listing by Pin Name is Se wee Kadette SE ju Bu Ds Brecon VSS D13 Power Other VSS L21 Power Other vss D16 Power Other VSS L24 Power Other VSS D19 Power Other VSS M2 Power Other VSS D23 Power Other VSS M5 Power Other VSS D26 Power Other VSS M22 Power Other VSS E3 Power Other VSS M25 Power Other VSS E6 Power Other VSS N1 Power Other VSS E8 Power Other VSS N4 Power Other VSS E11 Power Other VSS N23 Power Other VSS E14 Power Other VSS N26 Power Other VSS E16 Power Other VSS P3 Power Other VSS E19 Power Other VSS P6 Power Other VSS E21 Power Other VSS P21 Power Other V
91. r asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Quad Pumped Signal Groups DSTBN DSTBP teg Data Group D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high DBR Output DBR Data Bus Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on both FSB agents DEFER Input DEFER is asserted by an agent to indicate that a transacti
92. rted deasserted deasserted STPCLK Core State asserted Break HLT instruction Halt break MWAIT C1 m 4 P LVL2 or Core State MWAIT C2 Break NN P 4 or Core State MWAIT C4 Core State Break Brea GET P_LVL3 or MWAIT C3 Halt break A20M transition INIT INTR NMI PREQ RESET SMI or APIC interrupt core state break halt break OR Monitor event AND STPCLK high not asserted STPCLK assertion and de assertion have no effect if a core is in C2 C3 or C4 Datasheet Low Power Features Figure 2 Table 2 2 1 1 2 1 1 1 2 1 1 2 Datasheet Package Low Power States STPCLK asserted SLP asserted STPCLK desserted Snoop Snoop serviced occurs SLP desserted DPSLP asserted DPSLP deasserted DPRSTP asserted DPRSTP desserted Deeper Sleep Coordination of Core Low Power States at the Package Level Package State Corel State CoreO State co Er c2 c3 c4 CO Normal Normal Normal Normal Normal cil Normal Normal Normal Normal Normal C2 Normal Normal Stop Grant Stop Grant Stop Grant C3 Normal Normal Stop Grant Deep Sleep Deep Sleep CA Normal Normal Stop Grant Deep Sleep Deeper Sleep NOTE 1 AutoHALT or MWAIT C1 Core Low Power State Descriptions Core CO State This is the normal operating state for cores in the processor Core C1 AutoHALT Powerdown State C1 A
93. s 6 GTLREF GTLREF 2 should be generated from Vccp with a 196 tolerance resistor divider The Vccp referred to in these specifications is the instantaneous Vccp 7 Ry is the on die termination resistance measured at Vo of the AGTL output driver Measured at 0 31 Vccp Rrr is connected to Vccp on die Refer to processor I O buffer models for I V characteristics 8 Specified with on die and Roy turned off Vin between 0 and Vccp 9 Cpad includes die capacitance only No package parasitics are included 10 This is the external resistor on the comp pins 11 On die termination resistance measured at 0 33 Vccp 12 Applies to Signals A 35 3 13 Applies to Signals D 63 0 14 Applies to Signals BPRI DEFER PREQ PREST RS 2 0 TRDY ADS BNR BPM 3 0 BRO DBSY DRDY HIT HITM LOCK PRDY DPWR DSTB 1 0 DSTBP 3 0 and DSTBN 3 0 Datasheet 35 Electrical Specifications intel Table 10 CMOS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vccp 1 0 Voltage 1 00 1 05 1 10 V Vu Input Low Voltage CMOS 0 10 0 00 0 3 Vccp V 2 3 Vin Input High Voltage 0 7 Vccp Vccp Vecp 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 Vccp V 2 Vou Output High Voltage 0 9 Vccp Vccp Vecpt0 1 V 2 Output Low Current 1 5 4 1 mA 4 loH Output High Current 1 5 4 1 mA 5 lu Input Leakage Current 2 E 100 p
94. st occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin must be deasserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state When the processor is in Deep Sleep state it will not respond to interrupts or snoop transactions Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state The Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep state In response to entering Deeper Sleep the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID 6 0 pins Exit from Deeper Sleep state is initiated by DPRSTP deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point Datasheet m Low Power Features n tel 2 2 Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology Following are the key features of
95. support Connect to TDI_M on the platform THRMDA_2 T2 Thermal Diode Anode of the second die THRMDC_2 V3 Thermal Diode Cathode of the second die Datasheet m Thermal Specifications and Design Considerations n tel 5 Caution Table 16 Datasheet Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits Operating the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so the processor remains within the minimum and maximum junction temperature Tj specifications at the corresponding thermal design power TDP value listed in Table 16 Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods Processor Power Specifications Processor Thermal Design Symbol Number Core Frequency amp Voltage Power Unit Notes QX9300 2 53 GHz amp VccurM 45 Q9100 2 26 GHz am
96. tance and 1 minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 Specified at 100 C Tj 4 Specified at the nominal Vcc 5 Measured at the bulk capacitors on the motherboard 6 tolerance shown in Figure 4 and Figure 5 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 8 This is a power up peak current specification which is applicable when Vccp is high and Vcc CORE is low 9 This is a steady state I cc current specification which is applicable when both Vccp and Vcc CORE are high 10 Instantaneous current Icc core inst Of 85 A has to be sustained for short time of 35ys Average current will be less than maximum specified ccpgs VR OCP threshold should be high enough to support current levels described herein 32 Datasheet Electrical Specifications Figure 4 Datasheet Active Vcc and I cc Loadline for Quad Core Extreme Mobile Processor intel Vcc cone V Slope 2 1 mV A at package VccSense VssSense pins Differential Remote Sense required Vcc core max HFM LFM Vcc core pc max HFM LFM Voc core nom HFM LFM Voc core oc min HFM LFM Vcc cone min HFM LFM Voc core Tolerance VR St Pt Error 1 lcc conE 0 loc cone max
97. tate by entering the Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB or the interrupt has been latched The processor returns to the Stop Grant state once the snoop has been serviced or the interrupt has been latched Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and stops all internal clocks The Sleep state is entered through assertion of the SLP signal while in the Stop Grant state The SLP pin should only be asserted when the processor is in the Stop Grant state SLP assertions while the processor is not in the Stop Grant state is out of specification and may result in unapproved operation In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the FSB while the processor is in Sleep state Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior 15 intel 2 1 2 5 2 1 2 6 16 If RESET is driven active while the processor is in the Sleep state and held active as specif
98. temperature can be detected via two programmable thresholds located in the processor MSRs These thresholds have the capability of generating interrupts via the core s local APIC Refer to the Intel 64 and 32 Architectures Software Developer s Manuals for specific register and programming details PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its maximum operating temperature If TM1 or TM2 is enabled then the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT Refer to the an interrupt upon the assertion or deassertion of PROCHOT Refer to the Intel 64 and 32 Architectures Software Developer s Manuals for specific register and programming details The processor implements a bi directional PROCHOT capability to allow system designs to protect various components from overheating situations The PROCHOT signal is bi directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Only a single PROCHOTZ pin exists at a package level of the processor When any core s thermal sensor trips PROCHOT signal will be driven by the processor package If only TM1
99. ture then TM1 will also activate to help cool down the processor If a processor load based Enhanced Intel SpeedStep Technology transition through MSR write is initiated when a TM2 period is active there are two possible results 1 If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the TM2 transition based target frequency the processor load based transition will be deferred until the TM2 event has been completed 2 If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is lower than the TM2 transition based target frequency the processor will transition to the processor load based Enhanced Intel SpeedStep Technology target frequency point The TCC may also be activated via on demand mode If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1 the TCC will be activated immediately independent of the processor temperature When using on demand mode to activate the TCC the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Intel Thermal Monitor control register In automatic mode the duty cycle is fixed at 5096 on 5096 off however in on demand mode the duty cycle can be programmed from 12 596 on 87 5 off to 87 596 on 12 5 off in 12 5 increments On demand mode may be used at the same time automatic mode is enabled however if the system tries to enable the TCC via on demand mode at the sa
100. unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BRO is used by the processor to request the bus The arbitration BRO laput is done between the processor Symmetric Agent and GMCH High Output d Priority Agent Arbitration Request signal for the second die Input BR1 is connected to the first die within the package allowing two BR1 Output dies within quad core parts to artitrite for the bus This pin is fundamentally provided for debug capabilities and should be left as NC BSEL 2 0 Bus Select are used to select the processor input clock frequency Table 4 defines the possible combinations of the signals BSEL 2 0 Output and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency COMP 3 0 must be terminated on the system board using Analog precision 1 tolerance resistors 58 Datasheet m e Package Mechanical Specifications and Pin I nformation n tel Table 14 Signal Description Sheet 3 of 9 Name Type Description D 63 0 Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the FSB agents and must connect the appropriate pins on both agents The data drive
101. utoHALT is a low power state entered when a core executes the HALT instruction The processor core will transition to the CO state upon occurrence of SMI INIT LINT 1 0 NMI INTR or FSB interrupt messages RESET will cause the processor to immediately initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the AutoHALT Powerdown state See the Intel 64 and 32 Architectures Software Developer s Manuals Volume 3A 3B System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the AUtoHALT Powerdown state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state 13 m 8 n tel Low Power Features 2 1 1 3 2 1 1 4 2 1 1 5 2 1 1 6 2 1 2 2 1 2 1 14 While in AutoHALT Powerdown state the due core processor will process bus snoops and snoops from the other core The processor core will enter a snoopable sub state not shown in Figure 1 to process the snoop and then return to the AutoHALT Powerdown state Core C1 MWAI T Powerdown State C1 MWAIT is a low power state entered when the processor core executes the MWAIT C1 instruction Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the CO state See the Intel 64 and 32 Architectures Software Developer s Manuals Volu
102. ynch Output Input Input D 56 AF23 Source Synch Output DSTBN 3 AE25 Source Synch Output Input Input D 57 AC25 Source Synch Output DSTBP 0O H26 Source Synch Output Input Input D 58 AE21 Source Synch Output DSTBP 1 M26 Source Synch Output Input Input D 59 AD21 Source Synch Output DSTBP 2 AA26 Source Synch Output Input Input D 5 G25 Source Synch Output DSTBP 3 AF24 Source Synch Output DI60 AC22 Source Synch UE FERR A5 Open Drain Output GTLREF AD26 Power Other Input Input D 61 4 AD23 Source Synch Output GTLREF_2 D22 Power Other Input Input GTLREF C Input D 62 4 AF22 Source Synch Output ONTROL F8 CMOS Output Input HIT G6 Clock Input D 63 AC23 Source Synch Output ommon SOCK Output Input HITM E4 Common Clock Input D 6 E25 Source Synch Output Output ERR D20 Open Drain Output D 7 E23 Source Synch Geer P P p IGNNE c4 CMOS Input Input D 8 K24 Source Synch Output INIT B3 CMOS Input LINTO C6 CMOS Input D 9 G24 Source Synch Input Output LINT1 B4 CMOS Input DBR C20 CMOS Output p LOCK H4 Common Clock A DBSY El Common Clock utput PRDY AC2 Common Clock Output DEFER H5 Common Clock Input PREQ AC1 Common Clock Input Input Input DINV O 25 Source Synch Output PROCHOT D21 Open Drain guter DINV 1 N24 Source Synch UE PSI AE6 CMOS Output PWRGOOD D6 CMOS Input DINV 2 U22 Source Synch Hid utput Input REQ 0 4 K3 Source Syn

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