Transcend JetRam 256MB SDRAM 168pin DIMM
Contents
1. CS ViIH min tcc 10ns Active Standby Current Input signals are changed one time during 30ns in non power down mode One Bank Acti One Bank Active Icc3NS__ CKE gt ViH min CLK lt ViL max tcc lt Input signals are stable Operating Current loL 0 mA Bust Mode Icc4 Page Burst tccp 2CLKs Refresh Current lege RER Self Refresh Current Icc CKE lt 0 2V Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS VIH VIL VDDQ Vssa Transcend information Inc 6 256MB 168PIN PC133 CL3 J M334S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT AC OPERATING TEST CONDITIONS von 3 3V 0 3V TA 0 to 70 C Parameter ae nit O AC Input levels VIH VIL Input rise and fall time tr tf 1 1 Output timing measurement reference level Output load condition 3 3V Vit 1 4V O 1200 Ohm 50 Ohm gt Von DC 2 4V loH 2MA Vou DC 0 4V lo 2mA 50pF 870 Ohm 71117 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note e a fs tras max Row active time Row cycle time tRC min Last data in to new col Address delay tCDL min Last data in to Active delay 2CLK ste Last data in to burst stop tBDL min Col address to col address delay eee a Number of valid output data CAS latenc2. Transcend information Inc 11
3. oem Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Vop 3 3V TA 23 C f 1MHz VREF 1 4V 200mV ner ita a Input capacitance Ao A12 BAo BA1 Input capacitance RAS CAS WE Input capacitance CKEO Input capacitance CLKO CLK2 Input capacitance CSO CS2 Input capacitance DQM0 DQM7 Data input output capacitance DQ0 DQ63 Transcend information Inc 5 256MB 168PIN PC133 CL3 J M334S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Symbol Test Condition CAS Latency Value Typ Unit Note Operating Current Burst Length 1 A A i m One Bank Active tRC2tRC min loL OmA Precharge Standby Current ICc2P___ CKE lt ViL max tcc 10ns in power down mode Icc2PS CKE amp CLK lt ViL max tcc lt CKE2 gt ViH min CS gt ViIH min tcc 10ns Icc2N Input signals are changed one time during 30ns Precharge Standby Current in non power down mode CKE2ViH min CLK lt ViL max tcc lt ICC2NS Input signals are stable Active Standby Current IccaP__ CKE lt Vimax tec 10ns in power down mode Icc3PS_ CKE amp CLK lt ViL max tcc Icc3N CKE2ViH min
4. New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 O Transcend information Inc 9 JM334S643A 75 Serial Presence Detect Specification 256MB 168PIN PC133 CL3 SDRAM DIMM With 32M X 8 3 3VOLT Serial Presence Detect Byte No Function Described Standard Vendor Part Specification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 13 oD 4 of Column Addresses on this Assembly 10 OA 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 64bit 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8
5. amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 04 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec OE R W Burst 23 SDRAM Cycle Time 2 highest CL 7 5 75 24 SDRAM Access from Clock 2 highest CL 5 4 54 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 16ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 39 CO 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location 00 73 90 Manufacturers Part Number 00 91 92 Revision Code 00 Transcend information Inc 10 256MB 168PIN PC133 CL3 J M334S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT 93 94 Manufacturing Date 00 95 98 Assembly Serial Number 00 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 3 Clock 0 3 F4 128 Unused Storage Locations Open FF
6. 32 4x8 RAS 32Mmx8 ICAS SDRAM SDRAM SDRAM BA0 BA1 DQ0 DQ7 RAS 32Mx8 RAS 32Mx8 ICAS SPRAM SDRAM IWE ICS CKE SCL SCL SDA SDA AO A1 A2 SA0 SA1 SA2 A0 A12 a BAO BA1 DQ0 DQ7 IRAS 32Mx8 ICAS SDRAM BAO BA1 DQ0 DQ7 IRAS 32Mx8 ICAS SDRAM IWE This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 256MB 168PIN PC133 CL3 J M334S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Umit Voltage on any pin relative to Vss Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symboi min Typ Max Unt Note Suppyvotlage v 30 33 se v mputowvotage w s3 o f o v f gt Output high voltage vo 24 v oem Outputiow vollage vo f oa v
7. JM334S643A 75 Description The JM334S643A 75 is a 32M x 64bits Synchronous Dynamic RAM high density for PC 133 The JM334S643A 75 consists of 8pcs CMOS 32Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The JM334S643A 75 is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Conformed to JEDEC Standard 4 clocks e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Transcend information Inc Placement 256MB 168PIN PC133 CL3 SDRAM DIMM With 32M X 8 3 3VOLT mmnm TOCOCOCCOUCUCOoo Tonnan OMR RROA MRR a Na A Ea a a ag DODANAONAOATONONANONOONNNN OMENAA RAM
8. a aA a a aa Tonan TOCOOO NOONAN TOCOCOCCOUCCo COONAN TTU DODANAONAOATONONANONOONNNN TEM PCB 09 7303 JM334S643A 75 256MB 168PIN PC133 CL3 SDRAM DIMM With 32M X 8 3 3VOLT Pin Identification Symbol Function Dimensions Side Millimeters Inches A 133 35 0 40 5 250 0 016 B 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 29 21 0 20 1 150 0 008 G 19 78 0 778 H 15 78 0 621 1 27 0 10 0 050 0 004 Refer Placement Transcend information Inc AO A12 BAO BA1 Address input DQ0 DQ63 CLKO CLK2 CKEO CSO CS2 RAS ICAS IWE DQM0 DQM7 SA0 SA2 SCL SDA Vec Vss NC Data Input Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data DQ Mask Address in EEPROM Serial PD Clock Serial PD Add Data input output 3 3 Volt Power Supply Ground No Connection Refer Block Diagram AND Pinouts 256MB 168PIN PC133 CL3 J M334S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT Pinouts Pin Name No Name No Name Transcend information Inc 3 JM334S643A 75 256MB 168PIN PC133 CL3 SDRAM DIMM With 32M X 8 3 3VOLT JM334S643A 75 Block Diagram A0 A12 BAO BA1 DQO0 DQ63 IRAS ICAS IWE CSO CKEO A0 A12 A0 A12 A0 A12 BAO BA1 DQO0 DQ7 IRAS 32Mx8 IRAS
9. recharge Disable Column Auto Precharge Enable sie 4 Auto Precharge Disable L Col ee were sal ag on Auto Precharge Enable Ao As 4 5 LE Burst Stop r Precharge Bank Selection x Both Banks X Clock Suspend or Entry Active Power Down X ENESES Precharge Power Down Mode e EEEL V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst
10. y 3 EJE Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Last data in to row precharge tRDL min E FRS Transcend information Inc 7 256MB 168PIN PC133 CL3 J M334S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol _ Min Max Unit Note CAS latency 3 tec 5 1000 ns CAS latency 3 tOH CH ns tCL i ns tss ns Input hold time tSH ns CLK to output in Low Z ns CLK to output Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 256MB 168PIN PC133 CL3 J M334S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT See ase ee TRUTH TABLE commano CKEn 1 Refresh Auto Refresh eee Self Entry EE OP CODE Refresh Ea Bank Active amp Row Addr Read amp Auto P
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