Transcend 512MB DDR333 ECC Registered Memory
Contents
1. E X Write amp Column Address Auto Precharge Enable mre Burst Stop on Eel Ent Self y Refresh Exit I Bank Active amp Row Addr Auto Precharge Disable Column Read amp Add Column Address Auto Precharge Enable id Auto Precharge Disable Column Address X Bank Selection Precharge All Banks Entry Active Power Down x m lt Precharge Power Down Mode No Operation Command EEE Note OP Code Operand Code A0 A12 amp BAO BA1 Program keys EMRS MRS EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state BAO BA1 Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected During burst write with auto precharge new read write command cannot be issued Another bank read write comman2. ns Data out high impedance time from CK CK H2 07 07 ns Data out low impedance time from CK CK tZ 07 07 ns Mode register set cycle time tMRD 12 J J ns DQ amp DMsetuptimetoDQS DS 045 ns DQ amp DMholdtimetoDQS DBH 045 ns DQ amp DMinputpulsewidth JDIPW 175 ns Exit self refresh to read command XSRD 200 J tK Refresh interval time jREFl 78 uws 1 tCLmin or DQS write postamble time j WPST 04 06 tCK Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly Transcend Information Inc g 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND CKEn 1 ICS JRAS CAS A10 AP Ao Ag A11 A12 Ext pede L OP CODE Mode Register Set Register Mode Register Set H L L L L OP CODE 1 2 Auto Refresh
3. 184 PIN DDR333 Registered DIMM TS 64M DR 2V3F 512MB With 32Mx8 CL2 5 Description Placement The TS64MDR72V3F is a 64Mx72bits Double Data Rate SDRAM high density for DDR333 The TS64MDR72V3F consists of 18pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages 2pcs drive ICs for input control signal 1pcs PLL and a 20468 bits serial EEPROM on a 184 pin printed circuit board The TS64MDR72V3F is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets LII Hn Um im F m LT E Synchronous design allows precise cycle control with the ANL nur memory system applications GEMENS Features e Power supply VDD 2 5V 0 2V VDDQ 2 5V 0 2V a m m D e Max clock Freq 166MHZ Til RAE LEE TE TEE TT use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies I programmable latencies allow the same device to be useful for a variety of high bandwidth high performance IL E Double data rate architecture two data transfers per clock cycle H e Differential clock inputs CK and CK e Burst Mode Operation e Auto and Self Refresh e Data I O transactions on both edge of data strobe E e Edge aligned data output center aligned data Input PCB 09 1590 e Serial Presence Detect SPD with serial EEPROM e SSIL 2 compatible inputs and o
4. CD 18 ns Row active to Row active delay RP 18 ns Row active to Row active delay ftRRD 12 ns f Writerecoverytime O WR 15 ns Last data in to Read command WIR 1 K Col Address to Col Address delay tCCD 1 tK Clockcycletime O Z O Z CK 6 12 ns Clockhighlevelwidth tCH 045 055 tK J Clocklowlevelwidth tCL 045 055 tK J DQS out access time from CK CK 1 tDQOSCK 06 06 ns f 0 7 7 ns p 7j Data strobe edge to output data edge DQSQ 045 ns Read Preamble RPRE 09 1 1 tK J Read Postamble RPST 04 06 tK f 1 25 t CK DQS insetuptime WPRES 0 ns 2 DQS inhodtme WPREH 025 J J tK DQS falling edge to CK rising setup time iDSS 02 J tK DQS falling edge from CK rising holdtime tDSH 02 J tK DQS inhighlevelwidth tDQSH 035 tK J DQS inlowlevelwidth DOSL 035 tK DQS incycletime tDSC 09 11 tK Address and Control input setup time IS o UE ic sa Address and Control input hold time IH 08 J
5. O BA1 RAS DQ0 DQ7 A0 A12 BAO BA1 RAS 32Mx8 DQ0 DQ7 184 PIN DDR333 Registered DIMM 512MB With 32Mx8 CL 2 5 DQ0 DQ7 32Mx8 DQ0 DQ7 A0 A12 BAO BA1 RAS 32Mx8 CAS amp E DDR ICAS ICAS WE EE EI SDRAM WE Joso sm d E KE 1m CKE Too d DQS3 PCK1 PCK1 PCK2 PCK2 PCK3 PCK3 PCK4 PCK4 Dass PCK5 PCK5 PCK7 PCK7 PCK8 PCK8 PCK9 PCK9 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 A0 A12 A0 A12 A0 A12 ES E D BAO BA1 BAO BA1 BAO BA1 RAS RAS RAS O fi E 32Mx8 32Mx8 32Mx8 ICAS DDR ICAS DDR ICAS DDR o a E SDRAM SDRAM SDRAM 4 SEE i ANE ANE ANE m ICS ICS ICS 7 S a DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 A0 A12 A0 A12 A0 A12 A0 A12 BAo BA BAO BA1 BAO BA1 BAO BA1 BAO BA1 A T IRAS 32Mx8 IRAS 32Mx8 5 IRAS 32Mx8 IRAS 32Mx8 RAS 32Mx8 DDR DDR DDR aie SERAN ICAS o OASE ln ICAS SPRAM ICAS MNE MNE MNE MNE ICS1 REI RD m TTA BR Wa Hi Sii d CKE CKE CKE DMO DM1 DM2 DM3 B DQSO past DQS2 DQS3 Cees PCK1 PCK1 PCK2 PCK2 PCK3JPCK3 PCKA PCKA4 DES PCK10 PCK10 PCK5JPCK5 PCK6 PCK6 PCK7 PCK7 PCK8 PCK8 PCK9 PCK9 A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ7 DQ0 DQ7 E DQ0 DQ7 IRAS 32Mx8 IRAS 32Mx8 ES IRAS 32Mx8 ICAS DDR ICAS DDR ICAS DDR SDRAM SDRAM MNE 5 WE ICS ICS 3 ICS CKE CKE 9 DM6 DM7 DQS6 DQS7 PCK10 PCK10 PCK1 PCK1 PCK2 PCK2 PCK3 PCK3 Serial EEPROM CKO CKO PCK4 PCK4 SCL SCL SDA SDA f PLL PCK5 PCK5 ine Ki ad PCK6 PCK6 PCKT PCK7 PCK8 PCK8 SAO SA1 SA2 PCK9 PCK9
6. Output leakage current Output High Current Normal strength driver VOUT VTT 0 84V Output Low Current Normal strength driver VOUT VTT 0 84V Output High Current Half strength driver VOUT VTT 0 45V Output High Current Half strength driver VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 DC CHARACTERISTICS Recommended operating condition unles
7. This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value X Unt Voltage on any pin relative to Vss Voltage on VDD supply to Vss torage temperature Power dissipation hort circuit current IOS Mean time between failure MTBF emperature Humidity Burning emperature Cycling Test Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol upply voltage VDD O Supply voltage VDDQ O Reference voltage VREF O Termination voltage VTT nput logic high voltage VIH DC nput logic low voltage nput Voltage Level CK and CK inputs IN nput Differential Voltage CK and CK inputs nput crossing point voltage CK and CK inputs nput leakage current
8. actual components and may be checked at either the pin or the pad in simulation the AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Value Unt Note nput reference voltage for Clock 0 5 VDDQ NE o a nput signal maximum peak swing 15 V j nput Levels VIH VIL VREF 0 31VREF 0 34 V nput timing measurement reference level VREF NE NE NENNEN Output timing measurement reference level VIT V Output load condition see Load Circuit a VTT 0 5 VDDQ 0 5 VDDQ L CLoAD 30pF Output Load circuit Input Output CAPACITANCE Voo 2 5V Vppa 2 5V TA 25 C f 1MHz Input capacitance AO A12 BAO BA1 RAS CAS ANE Input capacitance CKEO CKE1 Input capacitance CSO CS1 Input capacitance CLKO CLKO Input capacitance DMO DMB8 Data and DQS input output capacitance DQ0 DQ63 Data input output capacitance CBO0 CB7 Transcend Information Inc 7 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Unt Note Row cycle time Z RC 60 J ns J Refreshrowcycletime RFC 72 J ns 70K ns J RASto CAS delay A R
9. changing once per clock cycle CL 2 5 at IDDAW 2810 tCK tCK min DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst Auto refresh current tRC tRFC min IDD5 2900 mA IDD6 560 mA Self refresh current CKE 0 2V mA Operating current Four bank operation Four bank interleaving with BL 4 IDD7 3890 mA Refer to the following page for detailed test condition Note 1 These parameters depend on the cycle rate and these values are measured a cycle rate with the minimum values of tCK and Trc 2 These parameters depend on the output loading Specified values are obtained with the output open Transcend Information Inc 6 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 AC OPERATING CONDITIONS Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DMsignals VIHAC VREF 031 fiv 3 Input Low Logic 0 Voltage DQ DOS and DM signals VIL AC VREF 0 34 Input Differential Voltage CK and CK inputs VID AC VDDQ 0 6 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 0 2 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on
10. d can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Transcend Information Inc Q 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 Serial Presence Detect Specification Serial Presence Detect O j amp ofBytes Written into Serial Memory 128bytes 6 Data Width ofthis Assembly Tis 48 7 DataWidth of thisAssembly 0 8 VDDQandinterface Standard of this Assembly SSTL25V A 9 DDRSDRAMCydeTimeatCASlateny 25 60ns 60 11 DIMM configuration type non parity Parity ECC 13 PrimaryDDRSDRAMWidth o Z Y X8 08 O 14 _ Error Checking DDR SDRAM Width X8 208 J 15 Min Clock Delay for Back to B 7 axmawomtoumMddess Sme 21 DDR SDRAM Module Attributes control inputs and 26 on card DLL ee UN NNNM tolerance 25 DDR SDRAM Cycle Time CL 1 5 1 00 26 DDRSDRAMAccessfromClockCl 15 o o 200 O 32 Command Address Input SetupTime Bs 80 O 33 Command Address InputHol
11. dTime ns BO 36 61 Superset Information 00 O 62 SPD Data Revision Code om 00 Transcend Information Inc 10 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 63 Checksum for Bytes 0 62 oom e 64 71 Manufacturers JEDEC ID 7F 4F 72 Manufacturing Location 54 73 90 Manufacturers Part Number TS64MDR72V3F Variable Variable 99 127 Manufacturer Specific Data o Transcend Information Inc 1
12. s otherwise noted VDD 2 7V TA ES LE S Operating current One bank Active Precharge tRC tRCmin tCK tCK min 2180 DQ DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle Operating current One bank Active Read Precharge Burst 2 Ser fa fea tRC tRC min CL 2 5 tCK tCK min VIN VREF fro DQ DQS and DM Precharge power down standby current All banks idle power down mode CKE lt VIL max tCK tCK min IDD2P 560 mA VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 133Mhz for DDR266 IDD2E 1330 S Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control IDDSN 1870 mA inputs changing once per clock cycle Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at IDD4R m tCK tCK min 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs
13. utputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Information Inc TS64MDR 2V3F 184 PIN DDR333 Registered DIMM 512MB With 32Mx8 CL2 5 Dimensions Side Millimeters 133 35 0 20 72 39 6 35 2 20 30 48 0 20 19 80 4 00 12 00 1 27 0 10 I O in im J IO W Refer Placement Transcend Information Inc Inches 5 250 0 008 2 850 0 250 0 087 1 20 0 008 0 779 0 157 0 472 0 050 0 004 Pin Identification Symbol Function A0 A12 BAO BA1 Address input DQ0 DQ63 CBO CB7 DQS0 DQS8 CKO CKO CKEO CKE1 CS0 CS1 RAS ICAS IWE DMO DMS8 VDD VDDQ VREF VDDSPD SA0 SA2 SCL SDA VSS RESET NC Data Input Output Check bit Data in data out Data strobe input output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data in Mask 2 5 Voltage power supply 2 5 Voltage Power Supply for DQS Power Supply for Reference 2 5 Voltage Serial EEPROM Power Supply Address in EEPROM serial PD Clock Serial PD Add Data input output Ground Reset enable No Connection 184 PIN DDR333 Registered DIMM TS 64M D R 2V3 F 512MB With 32Mx8 CL 2 5 Pinouts Pin Name No Name Please refer Block Diagram Transcend Information Inc 3 TS64MDR 2V3F Block Diagram DQ0 DQ63 A0 A12 BA
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