Transcend 256MB SDRAM 144Pin Micro-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time RASININ 25 1 tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to new col Address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDAL 2CLK tRP 3 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccp min 1 CLK 3 Number of valid output data CAS latency 2 1 is 4 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 144PIN PC133 MICRO SO DIMM TS32M MS64V6F 256MB With 32M X 8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Min Max Unit Note CLK cycle time CAS latency 2 tcc 7 5 1000 ns 1 CLK to valid T output delay CAS latency 2 tSAC 5 4 ns 1 2 Output data hold time CAS latency 2 toH 2 7 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output Er in Hi Z CAS latency 2 tSHZ 5 4 n2. 144PIN PC133 MICRO SO DIMM TS32MMS64V6F 256MB With 32M X 8 CL3 Description Placement The TS32MMS64V6F is a 32M x 64bits Synchronous Dynamic RAM high density for PC 133 The TS32MMS64V6F consists of 8pcs CMOS 32Mx8 bits Synchronous DRAMs in SOC packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS32MMS64V6F is a Dual In Line Memory Module and IU I m is intended for mounting into 144 pin edge connector sockets AT TT Synchronous design allows precise cycle control with the use of system clock I O transactions are possible Qu on every clock cycle Range of operation frequencies iFp programmable latencies allow the same device to be E gt useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM PCB 09 1900 e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Transcend information In
3. 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Vpp 3 3V Ta 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance Ao A12 BAo BA CIN1 30 40 pF Input capacitance RAS CAS WE CIN2 30 40 pF Input capacitance CKEO CIN3 30 40 pF Input capacitance CLKO CLK2 CIN4 25 30 pF Input capacitance CSO CS2 CIN5 16 25 pF Input capacitance DQMO DQM7 CIN6 8 10 pF Data input output capacitance DQ0 DQ63 Court 6 8 pF Transcend information Inc 144PIN PC133 MICRO SO DIMM TS32M MS64V6F 256MB With 32M X 8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Typ Unit Note Operating Current T SCR DT 1 720 A 4 One Bank Active lo sOmA Precharge Standby Current CC2P CKEsViL max tcc 10ns 16 mA in power down mode Icc2PS CKE amp CLKxViL max tcc lt 16 CKE ViH min CS gt VIH min tcc 10ns Icc2N Input signals are changed one time during 30ns 160 Precharge Standby Current mA in non power down mode CKE ViH min CLKxViL max tCC Icc2NS Input signals are stable Bp Active Standby Current Icc3P CKE lt VIL max tcc 10ns 48 mA in power down mode
4. Command H x H X X X L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BAt Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BAt are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK
5. E 115 DQM2 20 DQ39 68 CKE1 116 DQM6 21 Vss 69 CSO 117 DQM3 22 Vss 70 A12 118 DQM7 23 DQMO 71 CS1 119 Vss 24 DOM4 72 A13 120 Vss 25 DOM1 73 NC 121 DQ24 26 DQM5 74 CLK1 122 DQ56 27 Vcc 75 Vss 123 DQ25 28 Vcc 76 Vss 124 DQ57 29 A0 77 CB2 125 DQ26 30 A3 78 CB6 126 DQ58 31 A1 79 CB3 127 DQ27 32 A4 80 CB7 128 DQ59 33 A2 81 Vcc 129 Vcc 34 A5 82 Vcc 130 Vcc 35 Vss 83 DQ16 131 DQ28 36 Vss 84 DQ48 132 DQ60 37 DQ8 85 DQ17 133 DQ29 38 DQ40 86 DQ49 134 DQ61 39 DQ9 87 DQ18 135 DQ30 40 DQ41 88 DQ50 136 DQ62 41 DQ10 89 DQ19 137 DQ31 42 DQ42 90 DQ51 138 DQ63 43 DQ11 91 Vss 139 Vss 44 DQ43 92 Vss 140 Vss 45 Vcc 93 DQ20 141 SDA 46 Vcc 94 DQ52 142 SCL 47 DQ12 95 DQ21 143 Vcc 48 DQ44 96 DQ53 144 Vcc Please refer Block Diagram Transcend information Inc 3 144PIN PC133 MICRO SO DIMM TS32MMS64V6F 256MB With 32M X 8 CL3 Block Diagram A0 A12 A0 A12 A0 A12 A0 A12 A0 A12 BAO BA1 a BAO BA1 BAO BA1 BAO BA1 a BAO BA1 DQ0 DQ63 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 RAS RAS AS RAS 32Mx8 ICAS ICAS SDRAM IWE IWE ICS2 CLKO CLK2 RAS ICAS SDRAM ICAS SDRAM ANE 32Mx8 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of th
6. Icc3PS ICKE amp CLK lt ViL max tcc 48 Active Standby Current Icc3N CKE ViH min CS gt VIH min tcc 10ns 240 Input signals are changed one time during 30ns in non power down mode be 9 i diss mA ORS PANG ANYS Icc3NS CKE ViH min CLK lt ViL max tcc Input signals are stable 200 loL 0 mA Operating Current ICC4 Page Burst mA 1 Bust Mod 3 880 NSUSEMOUE tccp 2CLKs Refresh Current ICC5 tRC2tRC min 1600 mA 2 C 24 Self Refresh Current ICC6 CKE lt 0 2V 1 mA Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS VIH VIL VDDQ VssqQ Transcend information Inc 6 TS32MMS64V6F 144PIN PC133 MICRO SO DIMM 256MB With 32M X 8 CL3 AC OPERATING TEST CONDITIONS Vpp 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf2 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 Oo 3 3V Vttz1 4V Output gt vin aes oe Amis Output J d4 Z0 50 Ohm _ pa vir rr Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min
7. SDRAM Access from Clock Ze highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 16ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 C2 C2 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 33 32 4D MD 73 90 Manufacturers Part Number TS32MMS64V6F 53 36 34 56 36 46 20 20 20 20 20 20 Transcend information Inc 10 144PIN PC133 MICRO SO DIMM TS32M MS64V6F 256MB With 32M X 8 CL3 91 92 Revision Code 0 93 94 Manufacturing Date By Manufactory Variable 95 98 Assembly Serial Number By Manufactory Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 F6 128 Unused Storage Locations Open FF Transcend information Inc 11
8. c 1 TS32MMS64V6F 144PIN PC133 MICRO SO DIMM 256MB With 32M X 8 CL3 Dimensions Pin Identification Side Millimeters Inches Symbol Function 38 00 0 20 1 496 0 008 A0 A12 BAO BA1 Address input B 35 50 1 398 C 0 875 0 034 DQ0 DQ63 Data Input Output 2 4 00 UOS CLKO CLK2 Clock Input E 30 00 0 20 1 181 0 008 F 17 00 0 669 CKEO Clock Enable Input G 13 00 0 512 ICSO CS2 Chip Select Input H 5 00 0 197 RAS Row Address Strobe 0 80 0 08 0 031 0 003 Refer Placement ICAS Column Address Strobe IWE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Volt Power Supply Vss Ground NC No Connection Transcend information Inc 2 144PIN PC133 MICRO SO DIMM TS32MMS64V6F 256MB With 32M X 8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 49 DQ13 97 DQ22 02 Vss 50 DQ45 98 DQ54 03 DQO 51 DQ14 99 DQ23 04 DQ32 52 DQ46 100 DQ55 05 DQ1 53 DQ15 101 Vcc 06 DQ33 54 DQ47 102 Vcc 07 DQ2 55 Vss 103 A6 08 DQ34 56 Vss 104 A7 09 DQ3 57 CBO 105 A8 10 DQ35 58 CB4 106 BAO 11 Vcc 59 CB1 107 Vss 12 Vcc 60 CB5 108 Vss 13 DQ4 61 CLKO 109 A9 14 DQ36 62 CKEO 110 BA1 15 DQ5 63 Vcc 111 A10 16 DQ37 64 Vcc 112 A11 17 DQ6 65 RAS 113 Vcc 18 DQ38 66 CAS 114 Voc 19 DQ7 67
9. cycles after Read DQM latency is 2 Transcend information Inc 9 144PIN PC133 MICRO SO DIMM TS32M MS64V6F 256MB With 32M X 8 CL3 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 13 OD 4 of Column Addresses on this Assembly 10 0A 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 64bit 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General fisci REDE 0E R W Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24
10. is product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 TS32MMS64V6F ABSOLUTE MAXIMUM RATINGS 144PIN PC133 MICRO SO DIMM 256MB With 32M X 8 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 C Power dissipation PD 8 W Short circuit current los 50 mA Mean time between failure MTBF 50 Year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 24 k V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current Iu 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns
11. s Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 144PIN PC133 MICRO SO DIMM TS32 M MS64V6F 256MB With 32M X 8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A10 AP A11 A12 Ao A9 Note Register Mode Register Set H x L L L L x OP CODE 12 Refresh Auto Refresh H 3 Self Entry H L L L 5 a B i x 3 Refresh Exit L H H H 3 L H age x Ux 3 Bank Active amp Row Addr H X L L H H X V Row Address Read amp Auto Precharge Disable L Column 4 Column H X L H L H X V Address Address Auto Precharge Enable H Ao Ao 4 5 Write amp Auto Precharge Disable L Column 4 Column H X L H L L X V Address Address Auto Precharge Enable H Ao Ao 4 5 Burst Stop H X L H H L X X 6 Precharge Bank Selection V L Both Banks H x E L H L d X H x Clock Suspend or Entry Active Power Down H L H x x X X L V V V X Exit L H X X X x X Precharge Power Entry H X X X Down Mode H L X L H H H X Exit H X X x L H X L V V V DOM H X 7 No Operation
Download Pdf Manuals
Related Search