Transcend 128MB SDRAM 144Pin SO-DIMM PC66 Unbuffer Non-ECC Memory
Contents
1. Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 24 V IOH 2mA Output low voltage VoL 0 4 V IOL 2mA Input leakage current Iu 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state outputs CAPACITANCE vmo 3 3V 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance A0 A11 BAO BA1 CIN1 25 45 pF Input capacitance RAS CAS WE CIN2 25 45 pF Input capacitance CKEO CKE1 CIN3 15 25 pF Input capacitance CLKO CLK1 CIN4 15 21 pF Input capacitance CS0 CS1 CIN5 15 25 pF Input capacitance DQM0 DQM7 CIN6 10 12 pF Data input output capacitance DQ0 DQ63 COUT 10 12 pF Transcend information Inc 5 TS16MSS64V1EC DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 Parameter Symbol Test Condition Value Unit Note Operating Current Icc1 Burst Length 1 520 mA 1 One Bank Active tRC2tRC min loLz 0mA Precharge Standby Current2. 20 50 Ohm 9 50pF MES 50pF 7T WM TM ne Fig 1 DC Output Load Circuit 870 Ohm Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 20 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 a tRAS min 50 ns 1 Row active time tRAs max 100 us Row cycle time Operation tRC min 70 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to Active delay tDAL min 2CLK 20ns 5 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccb min 1 CLK 3 Number of valid output data CAS latency 3 2 ea 4 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer Note 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop 5 For 10 tRDL 1CLK and tDAL 1CLK 20ns is also supported Transcend information Inc 7 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1EC 128MB With 8Mx16 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not
3. Icc2P CKExViL max tcc 10ns 16 mA in power down mode Icc2PS CKE amp CLK lt VIL max tcc 16 Precharge Standby Current lccaN CKE SViH min CS ViH min tcc 10ns 160 mA in non power down mode Input signals are changed one time during 20ns Icc2NS_ CKE ViH min CLKxViL max tcc lt 80 Input signals are stable Active Standby Current IccaP CKEsViL max tcc 10ns 40 mA in power down mode Icc3PS CKE amp CLK lt ViL max tcc 40 Active Standby Current IccaN CKE SViH min CS ViH min tcc 10ns 240 mA in non power down mode Input signals are changed one time during 20ns One Bank Active IccaNS CKE gt ViH min CLKxViL max tcc 200 Input signals are stable Operating Current Icc4 loL 0 mA Burst Mode Page Burst 640 mA 1 2CLKs Refresh current Icc5 tRC2tRC min 880 mA 2 Self Refresh Current lt 0 2 16 3 Note loading cap Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ Transcend information Inc 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 TS16MSS64V1EC AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V TA 0 to 70 C AC Input levels VIH VIL 2 4 0 4 Input timing measurement reference level Input rise and fall time tr tf 1 1 Output timing measurement reference level Output load condition 1200 Ohm 50 Ohm Von DC 2 4V 2 Vo DC 0 4V lo 2mA Output
4. at row precharge BAo and BA1 are ignored and all banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc TS16MSS64V1EC Serial Presence Detect Specification 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of bytes written into Serial Memory 128bytes 80 1 Total of bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A11 0C 4 of Column Addresses on this Assembly A0 A8 09 5 of Module Banks on this Assembly 2 banks 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL 3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns 10 SDRAM Access from Clock highest CL 7ns 70 11 DIMM configuration type non parity ECC n
5. 15 RAS RAS RAS RAS ICAS 8Mx16 ICAS 8 16 ICAS 8 16 ICAS 8Mx16 WE SDRAM MWE SDRAM MWE SDRAM ICS CKE 2 CLK g This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 TS16MSS64V1EC ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 Power dissipation PD 8 W Short circuit current los 50 mA Mean time between failure MTBF 50 Year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C
6. H X v Column Address Auto Precharge Enable H Uca 4 5 Write amp Auto Precharge Disable L Column 4 H X L H L L X V Address Column Address Auto Precharge Enable H Ao As 4 5 Burst Stop H X L H H L X X 6 Bank Selection L Precharge H L L H L x x Both Banks H Clock S dor H ii i ock Suspen s Entry H L Active Power Down V V V X Exit L H n X X x x x Entry H L H Precharge Power X Down Mode L H H H x Exi E H xi H X x x X L V V V DQM H X V X 7 No Operation Command H X d i B X L H Note 1 OP Code Operand Code Ao A11 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 Bank select address V Valid X Don t Care H Logic High L Logic Low If both BAo and BAt1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BAt1 are High at read write row active and precharge bank D is selected If A10 AP is High
7. TS16MSS64V1EC 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 Description The TS16MSS64V1EC is a 16M bit x 64 Synchronous Dynamic RAM high density memory modules The TS16MSS64V1EC consists of 8 piece of CMOS 8Mx16bit with 4banks Synchronous DRAMs in 400mil packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS16MSS64V1EC is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range Speed 66MHz e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page e Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Placement TLOL D D D OL OOOO C 0D D D D D LOL TOL DO D LO LOL COLO D 00D DO D N UU TT UT U
8. TU T TU U TU U TOU T UU nannnnonnnonnnmnnnnnnnnpnnor 0000000050000 B UUUUUUTUUUUUTTUUUUUTUUUUUIU TU TTU UU U T TU TOU U TU U 0 UU UT 010000000000000000000000000 f 000000000000000000000000000 lt Y j 4 UTTUUUUUUUUUTTUUTUUUUUUUUU UUTTUUUUUT TU TUUUUUUUTUUUUU F 10100000000000000000000000 1 l4 PCB 09 6750 Transcend information Inc TS16MSS64V1EC 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 Dimensions Pin Identification Side Millimeters Inches Symbol Function A 67 60 0 200 2 661 0 008 A0 A11 Address inputs B 32 80 1 291 BA1 Select Bank C 23 20 0 913 090 0063 Data inputs outputs D 4 60 0 181 CLK1 Clock Input E 3 30 0 130 CKE1 Clock Enable Input F 2 50 0 098 ICSO CS1 Chip Select Input G 2 55 0 100 IRAS Row address strobe H 4 00 0 157 ICAS Column address strobe 20 00 0 787 WE Write Enable J 26 67 0 200 1 050 0 008 DQMO 7 DQM K 1 00 0 100 0 039 0 004 Vcc Power Supply Refer Placement Vss Ground SDA Serial Address Data SCL Serial Clock NC No Connection Transcend information Inc 2 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1EC 128MB With 8Mx16 Pinouts Pin Pin Pin Pi
9. ber 00 99 125 Manufacturer Specific Data 00 126 System frequency for 66MHz 66MHz 66 127 CAS Latency for 66MHz CAS latency of both 2 amp 3 06 128 Unused Storage Locations Undefined FF Transcend information Inc 11
10. n Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 49 DQ13 97 DQ22 02 Vss 50 DQ45 98 DQ54 03 DQO 51 DQ14 99 DQ23 04 DQ32 52 DQ46 100 DQ55 05 DQ1 53 DQ15 101 Vcc 06 DQ33 54 DQ47 102 Vcc 07 DQ2 55 Vss 103 A6 08 DQ34 56 Vss 104 A7 09 DQ3 57 NC 105 8 10 DQ35 58 NC 106 BAO 11 Vcc 59 NC 107 Vss 12 Vcc 60 NC 108 Vss 13 004 61 CLKO 109 A9 14 DQ36 62 CKEO 110 15 DQ5 63 Vcc 111 A10 16 DQ37 64 Vcc 112 11 17 DQ6 65 RAS 113 Vcc 18 DQ38 66 CAS 114 Vcc 19 DQ7 67 115 DQM2 20 0039 68 CKE1 116 DQM6 21 Vss 69 CSO 117 DQM3 22 Vss 70 A12 118 DQM7 23 DQMO 71 CS1 119 Vss 24 DQM4 72 A13 120 Vss 25 DOM1 73 NC 121 DQ24 26 DQM5 74 CLK1 122 0056 27 Vcc 75 Vss 123 00925 28 Vcc 76 Vss 124 DQ57 29 77 125 09026 30 78 126 0058 31 A1 79 NC 127 0027 32 A4 80 NC 128 DQ59 33 A2 81 Vcc 129 Vcc 34 A5 82 Vcc 130 Vcc 35 Vss 83 DQ16 131 DQ28 36 Vss 84 0048 132 37 008 85 0017 133 0029 38 0040 86 0049 134 0061 39 009 87 0018 135 09030 40 0041 88 00950 136 0062 41 0010 89 0019 137 0031 42 0042 90 2051 138 00963 43 0011 91 Vss 139 Vss 44 DQ43 92 Vss 140 Vss 45 Vcc 93 DQ20 141 SDA 46 Vcc 94 DQ52 142 SCL 47 0012 95 0021 143 Vcc 48 DQ44 96 DQ53 144 Vcc Please refer Block Diagram Transcend information Inc 3 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1EC 128MB With 8Mx16 Block Diagram A0 A11 BAO BA1 A0 11 BA0 1 fs A0 11 BA0 1 EB1A0 11 BAO 1 000 15 000 15 000 15 000
11. on parity 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width None 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 banks 04 18 CAS Latency 283 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General eee en 0E Burst 23 SDRAM Cycle Time CAS latency of 2 13ns DO 24 SDRAM Access from Clock CAS latency of 2 7ns 70 25 SDRAM Cycle Time CAS latency of 1 0 00 26 SDRAM Access from Clock CAS latency of 1 0 00 27 Minimum Row Precharge Time tRP 24ns 18 28 Minimum Row Active to Row Activate delay tRRD 20ns 14 29 Minimum RAS to CAS Delay tRCD 24ns 18 30 Minimum activate precharge time tRAS 50ns 32 31 Density of Each Bank on Module 64MB 10 32 61 Superset Information 00 62 SPD Data Revision Code Version 1 0 01 63 Checksum for Bytes 0 62 F5 64 71 JEDEC ID Code Transcend TF 4F Transcend information Inc 10 TS16MSS64V1EC 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 72 Manufacturing Location T 54 54 53 31 36 40 53 73 90 Manufacturers Part Number 7516 9564 1 53 36 34 156 31 45 43 20 20 20 20 20 91 92 Revision Code 00 93 94 Manufacturing Date 00 95 98 Assembly Serial Num
12. the whole module Parameter Symbol Unit Note Min Max tcc 1000 ns 1 CLK cycle time CAS latency 3 10 i tSAC ns 1 2 SLA to valid CAS latency 3 6 output delay Output data 5 tOH ns 2 hold time CAS latency 3 3 CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tss 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z CAS latency 3 tSHZ 6 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 TS16MSS64V1EC SIMPLIFIED TRUTH TABLE 144PIN PC66 Unbuffered SO DIMM 128MB With 8Mx16 CL3 COMMAND 1 CS IRAS CAS DQM BAo 1 A1o AP Ao A9 Note Register Mode Register Set H x L L L L x OP CODE 1 2 Auto Refresh H 3 uo neres H L L x x Refresh Entry 3 Self X X Refresh Exit L H 3 H 3 Bank Active amp Row Addr H X L H H X V Row Address Read amp Auto Prech Disabl L Column 4 ea uto Precharge Disable H X L H L
Download Pdf Manuals
Related Search