Transcend 64MB SDRAM PC100 Unbuffer Non-ECC Memory
Contents
1. 64MB With 8Mx16 CL2 Dimensions Pin Identification Side Millimeters Inches Symbol Function 133 35 0 40 5 250 0 016 AO A11 BA0 BA1 Address input B 65 67 2 585 c 23 49 0 925 DQ0 DQ63 Data Input Output D 8 89 0 350 CLKO CLK2 Clock Input E 3 00 0 118 CKEO Clock Enable Input F 31 75 0 20 1 250 0 008 G 19 80 0 788 CSO CS2 Chip Select Input H 15 80 0 622 RAS Row Address Strobe VATLA saaan Aia ICAS Column Address Strobe Refer Placement IWE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vec 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend information Inc TS8MLS64V8C2 168PIN PC100 Unbuffered DIMM 64MB With 8Mx16 CL2 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 CKEO 03 DQ1 45 ICS2 87 DQ33 129 ICS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 A13 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 C2 94 DQ39 136 C6 11 DQ8 53 C3 95 DQ40 137 C7 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC2. 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 9 168PIN PC100 Unbuffered DIMM TS8MLS64V8C2 64MB With 8Mx16 CL2 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A1o AP A11 Ao A9 Note Register Mode Register Set H X L L L L X OP CODE 1 2 Auto Refresh H H L L L H x x 3 Entry L 3 Refresh Self L H H H 3 Refresh i Exit L H H X X X X x 3 Bank Active amp Row Addr H x L L H H x V Row Address Auto Precharge Disable L Column 4 Read amp g H x L H L H X V Address Column Address Auto Precharge Enable H Ao As 4 5 i Auto Precharge Disable L Column 4 Write amp g H x L H L L x Vv Address Column Address Auto Precharge Enable H Ao As 4 5 Burst Stop H X L H H L X X 6 Bank Selection V L Precharge Both Banks H X L L H L X X H x Clock Suspend or Entry H L HM x X X Active Power L V V V X Down Exit L H X xX xX xX X H xX X X Entry H L X Precharge Power L Hi 7 H x Down Mode H X xX X Exit L H X L V V V DQM H X V X 7 H xX xX No Operation Command H x x x L H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BA0o BA1 Program keys MRS 2 MRS can be
3. address delay tcDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid output data CAS latency 2 1 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop 5 Anew command may be given tRFC after self refresh exit Transcend information Inc 168PIN PC100 Unbuffered DIMM TS8MLS64V8C2 64MB With 8Mx16 CL2 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time tcc 10 1000 ns 1 CLK to valid output delay tSAC 6 ns 1 2 Output data hold time tOH 3 ns 2 CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tss 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 6 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ins tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf
4. issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA is ignored and both banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 10 TS8MLS64V8C2 Serial Presence Detect Specification 168PIN PC100 Unbuffered DIMM 64MB With 8Mx1
5. 0 14 28 Minimum Row Active to Row Activate 20 14 29 Minimum RAS to CAS Delay 20 14 30 Minimum RAS Pulse Width 50 32 31 Density of Each Bank on Module 64MB 10 32 Command Address Setup Time 2ns 20 33 Command Address Hold Time 1ns 10 34 Data Signal Setup Time 2ns 20 35 Data Signal Hold Time ins 10 36 61 Superset Information 00 62 SPD Data Revision Code Version 1 2 12 63 Checksum for Bytes 0 62 34 oD 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend 7F 4F Transcend information Inc 11 TS8MLS64V8C2 168PIN PC100 Unbuffered DIMM 64MB With 8Mx16 CL2 72 Manufacturing Location T 54 54 53 38 4D 4C 53 73 90 Manufacturers Part Number TS8MLS64V8C2 36 34 56 38 43 32 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 Clock 0 2 A6 128 Unused Storage Locations Open FF Transcend information Inc 12
6. 103 DQ46 145 NC 20 DQ15 62 Vref 104 DQ47 146 Vref 21 CO 63 CKE1 105 C4 147 REGE 22 C1 64 Vss 106 C5 148 Vss 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 Vcc 68 Vss 110 Vcc 152 Vss 27 WE 69 DQ24 111 ICAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 CS1 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 AG 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 AQ 163 CLK3 38 A10 AP 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 A11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO 84 Vcc 126 A12 168 Vcc Please refer Block Diagram Transcend information Inc 168PIN PC100 Unbuffered DIMM TS8MLS64V8C2 64MB With 8Mx16 CL2 Block Diagram A0 A11 BA0 BA1 DQ0 DQ63 RAS ICAS IWE CSO CLKO CKEO CS2 CLK2 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc TS8MLS64V8C2 ABS
7. 168PIN PC100 Unbuffered DIMM TS8MLS64V8C2 64MB With 8Mx16 CL2 Description Placement The TS8MLS64V8C2 is a 8M x 64 bits Synchronous Dynamic RAM high density for PC 100 The TS8MLS64V8C2 consists of 4pcs CMOS 8Mx16 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS8MLS64V8C2 is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 100 e Conformed to JEDEC Standard spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply PCB 09 7130 e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Transcend information Inc 1 TS8MLS64V8C2 168PIN PC100 Unbuffered DIMM
8. 6 CL2 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 12 oC 4 of Column Addresses on this Assembly 9 09 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns AO 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width x16 10 14 Error Checking SDRAM Width 64bit 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 2 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec OF R W Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 2
9. OLUTE MAXIMUM RATINGS 168PIN PC100 Unbuffered DIMM 64MB With 8Mx16 CL2 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 4 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD VDDQ 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current IIL 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 1 5V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output l
10. e Bank Active IRC RCI loL OmA Precharge Standby Current lcc2P___ CKE lt VIL max tcc 10ns 4 mA in power down mode Icc2PS_ CKE amp CLK lt ViL max tcc 4 ICCON CKE gt ViH min CS gt ViH min tcc 10ns 80 Precharge Standby Current Input signals are changed one time during 20ns mA in non power down mode Sy IccoNS CKE VIH min CLK lt VIL max tcc 28 Input signals are stable Active Standby Current Icc3P CKE lt ViL max tcc 10ns 20 mA in power down mode Icc3PS_ CKE amp CLK lt ViL max tcc 20 Active Standby Current Icc3N EE ee CS2VIH min tcc 15ns 120 nput signals are changed one time during 30ns in non power down mode mA Bank Acti One BANK Astiga Icc3NS CKE gt ViH min CLK lt ViL max tec 36 Input signals are stable lOL omA repeated ll Icc4 Page Burst 4Banks activated 720 mA 1 tcen 2CLKs Refresh Current ICc5 tRC tRC min 840 mA 2 Self Refresh Current ICC6 CKE lt 0 2V 6 mA Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 7 TS8MLS64V8C2 168PIN PC100 Unbuffered DIMM 64MB With 8Mx16 CL2 OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 20 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time IRA N oe ns 1 tRAS max 100 us Row cycle time tRC min 70 ns 1 Last data in to new col
11. eakage for all bi directional buffers with Tri State outputs Transcend information Inc 168PIN PC100 Unbuffered DIMM TS8MLS64V8C2 64MB With 8Mx16 CL2 CAPACITANCE TA 23 C f 1MHz Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA1 CIN1 25 30 pF Input capacitance RAS CAS WE CIN2 25 30 pF Input capacitance CKEO CIN3 25 30 pF Input capacitance CLKO CLK2 CIN4 15 20 pF Input capacitance CSO CS2 CIN5 15 20 pF Input capacitance DQM0 DQM7 CIN6 8 10 pF Data input output capacitance DQ0 DQ63 COUT 8 10 pF AC OPERATING TEST CONDITIONS voo 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 o own 1200 Ohm 50 Ohm gt Vox DC 2 4V lon 2mA Vor DC 0 4V loL 2mA Z 50pPF 870 Ohm 77T Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit Transcend information Inc 6 168PIN PC100 Unbuffered DIMM TS8MLS64V8C2 64MB With 8Mx16 CL2 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current i Burst Length 1 a CC1 i m On
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