Transcend 512MB SDRAM PC133 ECC Registered Memory
Contents
1. DIMM 512MB With 32M X8 CL3 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC 2 02 63 Checksum for Bytes 0 62 EQ 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 36 34 4D 4C 73 90 Manufacturers Part Number TS64MLR72V6F 52 37 32 56 36 46 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 3 Clock 0 84 128 _ Unused Storage Locations Open FF Transcend Information Inc 112. U3 H 103 U12 DQI9 104 104 DQI8 105 105 DQ17 106 106 DQI6 107 107 vas F TT DQM CS CKE DQM ICS CKE DB31 WS 1 00 100 Boa MN 102 103 102 DQ28 WN 103 U4 103 U13 DQ27 W 104 104 DQ26 w 1 05 105 DQ25 w 106 106 DQ24 AWH 107 107 DQM5 DAM DQM CS CKE DQM ICS CKE CB2 100 1o00 CB6 VO 1 1 CB3 102 U9 102 U18 CB7 103 1 03 CBI 104 104 CB5 105 105 CBO 106 1 06 CB4 107 107 VDD es ed vs _L____ 1 U1 U18 are 16Mx8 SDRAM 2 DQ to I O wiring may be changed per nibble Note 3 Unless otherwise noted resister values are 10 Ohms 5 U1 U18 ICS CKE DQM DQ39 WH 100 100 DQ38 W O 1 YO 1 DQ37 Ws 102 U5 102 DQ36 WH 103 103 DQ35 WH 104 104 DQ34 W 1 05 105 DQ33 WY 1 06 106 DQ32 WH 107 107 ICS CKE ICS CKE ICS CKE D7 w 100 100 RN p 1 DQ44 aw 1 0 3 U6 UIS D3 WN 104 B3 AA 3 DO40 AWA 107 DQM6 H DQM CS CKE DQM ICS CKE DQ55 100 100 DQ54 101 Wol DQ53 102 POs 103 U7 103 U16 DQ51 104 104 DQ50 105 L4 1 05 DQ49 106 106 D48 107 107 no ea TT DQM C CKE DQM ICS CKE DQ63 w 1 00 4 100 DQ62 ee 101 Dosi W ios U8 2 u7 DQ59 man 104 104 D58 w moa 4 105 DQ57 w I 106 Boss AN 107 I 107 SA0 SA12 ANN gt U18 SBAO SBAL w R L gt u ig SRAS w E gt U18 ISCAS w G gt u u ISWE w U18 SCKEO w gt Uw SCS
3. 17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 Vref 104 DQ47 146 Vref 21 CBO 63 CKE1 105 CB4 147 REGE 22 CB1 64 Vss 106 CB5 148 Vss 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 Vcc 68 Vss 110 Vcc 152 Vss 27 ANE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 CS1 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 AQ 163 CLK3 38 A10 AP 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 A11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO 84 Vcc 126 A12 168 Vcc Please refer Block Diagram Transcend Information Inc 3 TS64MLR 2V6F 168PIN PC133 Registered DIMM 512MB With 32M X8 CL3 Block Diagram CKE1 ICSI ICSO CKEO ICS CKE Ul ICS CKE U10 ICS CKE wry 100 100 DAIS AW 10 1 101 BBK wn 102 U2 V02 Ul po wr 103 103 Doll we 104 104 DAI w 105 105 Doo w 106 106 pos way 107 107 DQM C CKE DQM CS CKE DQ23 voo v00 DQ22 vO 1 yO DQ21 102 102 DQ20 103
4. 68PIN PC133 Registered DIMM 512MB With 32M X8 CL3 Pin Identification Dimensions Side Millimeters Inches A 133 35 0 40 5 250 0 016 B 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 15 80 0 622 F 19 80 0 780 G 43 00 0 20 1 693 0 008 H 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc Symbol Function SA0 SA12 Address Input SBA0 SBA1 Select Bank Address SD0 SD63 Data Input Output SCBO SCB7 Check bit data in data out SCKO Clock Input SCKEO Clock Enable Input SCSO0 SCS3 Chip Select Input ISRAS Row Address Strobe ISCAS Column Address Strobe SWE Write Enable SDQM0 SDQM7 Data DQ Mask SREGE Register Enable EAO EA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection 168PIN PC133 Registered DIMM TS64MLR 2V6F 512MB With 32M X8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 CKEO 03 DQ1 45 ICS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 A13 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ
5. O ANS T gt Ul U9 SCKE yn E gt 0 U18 SCS w R gt Ul0 U18 SDQM0 SDQM7 wr m U18 cKO P Hui uis L T Register RESET EEPROM SCL yp sDA t 17 am SAQ SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 168PIN PC133 Registered DIMM TS64MLR 2V6F 512MB With 32M X8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 18 W Short circuit current IOS 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Max Unt Note 3 3 E e 3 0 2 i 2 4 3 ae NN a Output
6. Standby Current Icc2N Input signals are changed one time during 30ns 288 mA 3 in non power down mode E Icc2NS CKE2VIH min CLK lt VIL max tcc 252 Input signals are stable Active Standby Current Icc3P CKE lt VIL max tcc 10ns 108 mA 3 in power down mode Icc3PS CKE amp CLK lt ViL max tcc 108 Active Standby Current Icc3N CKE ViH min CS gt ViH min tcc 10ns 540 Input signals are changed one time during 20ns in non power down mode PESSI g emg One Bank Active mA Ilcc3NS CKE gt VIH MmiIn CLK lt ViL max tCcC 3 450 Input signals are stable l IOL 0 mA Operating Current Bust Mode ICC4 Page Burst 1 530 mA 1 tcecp 2CLKs Refresh Current ICc5 tRc tRC min 2 160 mA 2 3 Self Refresh Current ICC6 CKE lt 0 2V 90 mA 3 Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend Information Inc 6 TS64MLR 2V6F AC OPERATING TEST CONDITIONS voo 3 3V 0 3V TA 0 to 70 C AC Input levels VIH VIL 2 4 0 4 Input timing measurement reference level 168PIN PC133 Registered DIMM 512MB With 32M X8 CL3 Input rise and fall time tr tf 1 1 ns Output timing measurement reference level V Output load condition See Fig 2 3 3V O 1200 Ohm Von DC 2 4V lon 2mA Output QO _Z0 50 Ohm _ Vor DC 0 4V loL 2mA 50pF aaa 870 Ohm J T1117 Fig 1 DC Output Load Circ
7. TS64MLR 2V6F Description The TS64MLR72V6F is a 64M bit x 72 Synchronous Dynamic RAM high density memory registered DIMM module The TS64MLR72V6F consists of 18pcs 16Mx8 bits Synchronous DRAMs 3pcs drive ICs for input control signal 1pc PLL and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS64MLR72V6F is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e Performance Range PC 133 e Burst Mode Operation e Auto and Self Refresh e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock 168PIN PC133 Registered DIMM 512MB With 32M X8 CL3 Placement PCB 09 0872 K g Transcend Information Inc TS64MLR 2V6F 1
8. d SBA1 is High at read write row active and precharge bank B is selected If both SBAo is High and SBA1 is Low at read write row active and precharge bank C is selected If both SBAo and SBA are High at read write row active and precharge bank D is selected If SA10 AP is High at row precharge SBAo and SBA1 is ignored and both banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 SDQM sampled at positive going edged of a CLK masks the data in at the very CLK Write SDQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read SDQM latency is 2 Transcend Information Inc 9 168PIN PC133 Registered DIMM TS64MLR 2V6F 512MB With 32M X8 CL3 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 Number of Bytes Written into Serial Memory 128bytes 80 1 Total Number of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on this Assembly 13 oD 4 Number of Column Addresses on this Assembly 10 OA 5 N
9. high voltage von 24 mao Caoc ai al Output low voltage Input leakage current Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs IOL 2mA Transcend Information Inc 5 168PIN PC133 Registered DIMM TS64MLR 2V6F 512MB With 32M X8 CL3 CAPACITANCE Voo 3 3V TA 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance SAo SA12 SBAo SBA1 CIN1 85 105 pF Input capacitance SRAS SCAS SWE CIN2 85 105 pF Input capacitance SCKEO CIN3 50 65 pF Input capacitance SCLKO CIN4 40 45 pF Input capacitance SCSO0 SCS3 CIN5 30 40 pF Input capacitance SDQM0 SDQM 7 CIN6 25 30 pF Data input output capacitance SD0 SD63 COUT 10 15 pF Data input output capacitance SCBO SCB7 CouT1 10 15 pF DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Unit Note Operating Current i Burst Length 1 ai CC1 i One Bank Active IRC RGU loL OmA Precharge Standby Current Icc2P CKE lt VIL max tcc 10ns 36 mA 3 in power down mode Icc2PS CKE amp CLK lt ViL max tec 36 CKE gt ViH min CS gt ViH min tcc 10ns Precharge
10. r amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 8 168PIN PC133 Registered DIMM TS64MLR 2V6F 512MB With 32M X8 CL3 SIMPLIFIED TRUTH a COMMAND SCKEn 4 1 Scken ISCS SRAS SCAS SWE an a Refresh Auto Refresh Refresh Self Era Bank Active amp Row Adders Auto Precharge Disable Auto Precharge Disable an H X V Column Auto Precharge Enable Address SAo SA9 SA11 i Auto Precharge Disable Column Column Address Auto Precharge Enable Address SAo SA9 SA11 Burst Stop__________ _ ded x Bank Selection Both Banks x Exit X n RARAN T i Eie ea o eee T SDM oo a a aa Command TET TEP fees a LALS V Valid X Don t Care H Logic High L Logic Low x H Clock Suspend or Entry x Active Power Down PEPPY X Note 1 OP Code Operand Code SAo SA11 SBAo SBA11 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 SBAo SBA1 Bank select address If both SBAo and SBA1 are Low at read write row active and precharge bank A is selected If both SBAo is Low an
11. uit Fig 2 AC Output Lo Vtt 1 4V 50 Ohm 50pF ad Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Row active to row active delay tRRD min Row active time Last data in to new col address delay row precharge Last data in t Last data in to burst stop Col address to col address dela Number of valid output data CAS latency 3 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write in Reg DIMM 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 7 168PIN PC133 Registered DIMM TS64MLR 2V6F 512MB With 32M X8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module CLK cycle time CAS latency 3 tcc 1000 CLK to valid CAS latency 3 tSAC output delay Output dat se as CAS latency 3 tOH hold time CLK high pulse width tCH ns CLK low pulse width tCL ns Input setup time tss ns Input hold time tSH ns CLK to output in Low Z ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ins tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time t
12. umber of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 72bits 48 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC ECC 02 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width X8 08 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 04 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 Registered DQM 16 21 SDRAM Module Attributes address control inputs and 16 on card PLL f Prec All Auto Prec R W OE 22 SDRAM Device Attributes General Burst 23 SDRAM Cycle Time 2 highest CL Ons 00 24 SDRAM Access from Clock 2 highest CL Ons 00 25 SDRAM Cycle Time 3 highest CL Ons 00 26 SDRAM Access from Clock 3 highest CL Ons 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 Transcend Information Inc 10 TS64MLR 2V6F 168PIN PC133 Registered
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