Transcend 256MB SDRAM PC133 ECC Registered Memory
Contents
1. Input capacitance SCLKO SCLK3 Input capacitance SCSO SCS2 Input capacitance SDOMO SDQM7 Data input output capacitance SDO SD63 Data input output capacitance SCBO SCB7 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Lateney Value Unit Noto Operating Current ICC1 Burst Length lt 1 One Bank Active tRC2tRC min loL OmA Icc2P CKExViL max tec 10ns min CS gt VIH min tcc 10ns Input D are PEUT one time eum 20ns Input nes are ee Active Standby Current lccaP CKEsVIL CKESVIL max tcestOons OO tcc 10ns a In power down mode lccaPS CKE 8 CLK lt VIL CKE amp CLKSVIL Max te e OO teze Active Standby Current SEIS min CS gt VIH min tcc 10ns in non power down mode Input m are PEUT one time sile 20ns Input pint are Abbie Operating Current lOL 0 mA Bust Mode Page Burst 1 610 mA 1 tccp 2CLKs Refresh Current tRC gt tRC min 2 240 Self Refresh Current CKE lt 0 2V Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Measured with 1 PLL amp 2 Drive lcs 4 Unless otherwise noticed input swing level is CMOS VIHAVIL VDDQ VSssqQ Transcend Information Inc 6 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 AC OPERATING TEST CONDITIONS Von 3 3V 0 3V TA 0 to 70 C tr tf 1 1 3 3V Vtt 1 4V AC Input levels VIH VIL 1200 Ohm 50 Oh2. 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 Description Placement The TS32MLR72VGF is a 16M x 72 bits Synchronous Dynamic RAM high density memory registered DIMM module The TS32MLR72V6F consists of 9pcs 16Mx8 bits Synchronous DRAMs 2pcs drive ICs for input control signal 1pc PLL and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS32MLR72VGF is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector pe ais AN NK ee sockets Synchronous design allows precise cycle control with EE the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies HE HE ER HH EHE RE EE E programmable latencies allow the same device to be useful for a variety of high bandwidth high performance MEN LL LLL LLLI LL icati TTT Tt a A memory system applications Features r 3 fo 7 e Performance Range PC 133 a E e Burst Mode Operation F H gt lt e Auto and Self Refresh 6 e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM PCB 09 0875 e LVITL compatible inputs and outputs e Single 3 3V t 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of th
3. 32 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 166 Name Vss SCKEO SCS3 SDQM6 SDQM7 SA13 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 Block Diagram SCBO SCB7 SDO SD63 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 SAO SATLSBAO SBA AO A11 BA0 BA1 las A0 A11 BAO BA1 e AO A11 BA0 BA1 la AO A11 BA0 BA1 as AO A11 BA0 BA1 lm AO A11 BA0 BA1 ISRAS 32Mx8 32Mx8 32Mx8 32Mx8 SCAS SDRAM SDRAM SWE SCKEO SDOM0 SDOM7 AJ m Scso SCS3 2 RCSO i RCS2 li IRCS2 a RCSO Reece s PCK3 PCK1 PCK2 m DQ0 DQ7 DQ0 DQ7 JU A0 A11 BAO BA1 A0 A11 BAO BA1 PCK1 IRAS 32Mx8 IRAS 32Mx8 CAS 9959 SDRAM SCLKO PLL PCK2 PCK3 G Y PCK4 oja PCK4 EEPROM SCL SCL SDA SDA IRCS2 PCK2 PCK3 PCK3 A0 A1 A2 EAO EA1 EA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss Voltage on VoD supply to Vss torage temperatu
4. e and precharge bank B is selected If both SBAO is High and SBA1 is Low at read write row active and precharge bank C is selected If both SBAO and SBA are High at read write row active and precharge bank D is selected If SA10 AP is High at row precharge SBAO and SBA1 is ignored and both banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 SDQM sampled at positive going edged of a CLK masks the data in at the very CLK Write SDQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read SDQM latency is 2 Transcend Information Inc 9 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 o D U rap o D 2 O D g D et D O et o O D 2 h O o et O 5 Serial Presence Detect O jfofBytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type 3 jfofRow Addresses on this Assembly B 0D 4 8 of Column Addresses on this Assembly 5 jfof Module Banks on this Assembly 6 Data Width of this Assembly 7 Data Width Continuation 0 00 8 Voltage Interface Standard of th
5. e system clock Transcend Information Inc 1 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 Dimensions Pin Identification Side Millimeters Inches Symbol Function 133 35 0 40 5 250 0 016 SAO SA1 Address Input B 65 67 2 585 SBAO SBA1 Select Bank Address C 23 49 0 925 D 8 89 0 350 SDO SD63 Data Input Output E 15 80 0 622 SCBO SCB7 Check bit data in data out E 19 80 0 780 SCK0 SCK3 Clock Input G 29 21 0 20 1 150 0 008 SCKEO Clock Enable Input H 1 27 0 10 0 050 0 004 Refer Placement SCSO SCS2 Chip Select Input ISRAS Row Address Strobe ISCAS Column Address Strobe ISWE Write Enable SDQMO SDOM 7 Data DO Mask SREGE Register Enable EAO EA2 Address in EEPROM SCL serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend Information Inc 2 TS32MLR 2V6F 168PIN PC133 Registered DIMM 256MB With 32Mx8 CL3 Pinouts Pin Name Vss SDO SD1 SD2 SD3 Vcc SD4 SD5 SD6 SD7 SD8 Vss SD9 SD10 SD11 SD12 SD13 Vcc SD14 SD15 NC SAO SA2 SA4 SA6 SA8 SA10 AP SBA1 Vcc Vcc SCLKO Please refer Block Diagram Transcend Information Inc Name Name Vss SD32 SD33 SD34 SD35 Vcc SD36 SD37 SD38 SD39 SD40 Vss SD41 SD42 SD43 SD44 SD45 Vcc SD46 SD47 SCB4 SCB5 Vss NC NC Vcc ISCAS SDQM4 SDQM5 SCS1 ISRAS Vss SA1 SA3 SA5 SAT SA9 Vcc Pin 127 128 129 130 131 1
6. f clock rising time is longer than 1ns tr 2 0 5 ns should be added to the paremeter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 8 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 SIMPLIFIED TRUTH TABLE comano sets sexen ses moo scu soo son sa sno sao sati no mmm Se MER 3 3 3 Auto Refresh Refresh x x ES NE NEMI Self zu p ER SIRE NEM CM e one e Col Add bn olumn fess Auto Precharge Enable SAo SAc A ress Column Address Auto Pun tuo Debe mL SAo SAs Bank Selection L All Banks Clock Suspend or Active Power Down Precharge Power Down Mode V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code SA0 SA11 SBAO SBA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 SBA0 SBAT1 Bank select address If both SBAO and SBA1 are Low at read write row active and precharge bank A is selected If both SBAO is Low and SBA 1 is High at read write row activ
7. is Assembly LVTTL23V 01 9 SDRAM Cycle Time highest CAS latency 75ns 75 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width X8 08 18 QcASSLlateny 0 0 0 3 3J 06 21 SDRAM Module Attributes Registered DQM address control inputs 16 22 SDRAM Device Attributes General Prec All Auto Prec R W OE a i a 23 SDRAM Cycle Time 2 highest CL J 2 0 24 SDRAM Access from Clock 2 highest CL 25 X SDRAMOydeTime 3 highest CL o 1 00 o 26 SDRAM Access from Clock 3 highestCL 00 33 Command AddressHold Time O8ns 08 35 Data Signal Hold Time Oss J 08 3661 Superset Information o Z 0 62 SPD Data Revision Code Transcend Information Inc 10 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 CA 7F 4F 54 73 90 Manufacturers Part Number TS32MLR72V6F Variable Variable 99 125 ManufactuerSpecficData o do o o 126 tel Specification Frequency 0 o FF 64 Transcend Information Inc 11
8. m Vou DC 2 4V lon 2mA Output Z0 50 Ohm Vo DC 0 4V lo 2mA _ BOpF 50pF 7711 MM GM Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Value RAS to CAS delay Row precharge time 100 mme e mw ast data in to new col address delay ast data in to row precharge 2 ast data in to Active delay tDAL 2CLK 20ns ast data in to burst stop Col address to col address delay Number of valid 870 Ohm Row cycle time CAS latency 3 output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 7 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol CLK cycle time CAS latency 2 tcc CLK to valid CAS latency 2 tSAC output delay CAS latency 2 EM CLK high pulse width CLK low pulse width nput setup time nput hold time CLK to output in Low Z CLK to output in Hi Z Note 1 Parameters depend on programmed CAS latency 2 I
9. re Power dissipation hort circuit current m Mean time between failure year emperature Humidity Burning 85 C 85 C emperature Cycling Test 0 C 125 C C Hr Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Typ Max Note Supply voltage Von 30 33 36 V Bl Input low voltage 0 08 Output high voltage vo 24 Output low voltage Vo O04 V lOl 2mA Input leakage current IL 10 10 vA Note 1 VIH max 5 6V AC The overshoot voltage duration is x 3ns 2 VIL min 7 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDO Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs IOH 2mA Transcend Information Inc 5 168PIN PC133 Registered DIMM 1332 M LR 2V6F 256MB With 32Mx8 CL3 CAPACITANCE voo 3 3V TA 23 C f 1MHz Parameter Input capacitance S Input capacitance SRAS SCAS SWE Input capacitance SCKEO Ao SA11 SBA0 SBA1
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