Transcend 512MB DDR266 ECC Registered Memory
Contents
1. OULTITITTitittirit tity ILI ILI Lea eae Ae ET ee oe SS 6 sab sath oth oth oat oat oss GN a b Sip site sep S80 Sep Sse S59 8 is Hi HH i jei HK Hi HK Jei jei jefe OSTIT eco gt gt cG FS E 0 W PCB 09 1380 o ian hh 184Pin DDR266 Registered DIMM TS64MDR72V6L5 512MB with 64Mx4 CL2 5 Dimensions Pin Identification Side Millimeters Inches Symbol Function A 133 35 0 20 __5 250 0 008 SA0 SA12 SBAO SBA1 Address input B 72 39 2 850 SDQ0 SDQ63 Data Input Output C 6 35 0 250 SCB0 SCB7 Check bit D 2 2 087 0 08 SDQS0 SDQS8 E 30 48 0 20 1 20 0 008 SDMO0 SDM8 Data strobe input output a 19 80 0 779 CKO CKO Clock Input G 4 00 0 157 SCKEO Clock Enable Input H 12 00 0 472 1 27 0 10 0 050 0 004 ISCSO Chip Select Input Refer Placement SRAS Row Address Strobe ISCAS Column Address Strobe ISWE Write Enable VDD 2 5 Voltage power supply 2 5 Voltage Power Supply VDDQ for DQS VREF Power Supply for Reference 2 5 Voltage Serial VDDSPD EEPROM Power Supply EAO EA2 Address in EEPROM SCL Serial PD Clock Serial PD Add Data SDA input output VDDID VDD Identification Flag VSS Ground RESET Reset enable NC No Connection Transcend Information Inc TS64MDR72V6L5 184Pin DDR266 Registered DIMM 512MB with2. TS64MDR72V6L5 512MB with 64Mx4 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND CKEn 1 CKEn CS RAS CAS WE BAo 1 A1o AP Ao Ag A11 A12 Note F Extended Register Mode Register Set H X L L L L OP CODE 1 2 Register Mode Register Set H X L L L L OP CODE 1 2 Auto etes H L L L H x s Refresh Self 4 R Sea gt Refresh i Exit L H H X X X x 3 Bank Active amp Row Addr H x L L H H V Row Address Read amp Auto Precharge Disable L Column 4 Column Address E i L E n E Angress Auto Precharge Enable H Ao A9 A11 4 j Auto Precharge Disable L Column 4 Write amp H x L H L L v Address Column Address Auto Precharge Enable H TASAS i 4 6 Burst Stop H X L H H L X 7 Bank Selection V L Precharge All Banks H X L L H L X H X 5 Entry H L H x X X Active Power Down L V V V X Exit L H X X X X H X X X Entry H L Precharge Power L H H H Down Mode x Exit H X X X L H L V V V DM H X X H X X X 9 No Operation Command H x x L H H H 9 Note OP Code Operand Code A0 A12 amp BAO BA1 Program keys EMRS MRS EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS Auto refresh functions are same as the CBR refresh of DRAM The automatical precharge without row
3. capacitance CBO CB7 COUT2 16 pF Transcend Information Inc TS64MDR72V6L5 184Pin DDR266 Registered DIMM 512MB with 64Mx4 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Unit Note Row cycle time tRC 65 ns Refresh row cycle time tRFC 75 ns Row active time tRAS 45 120K ns RAS to CAS delay tRCD 20 ns Row active to Row active delay tRP 20 ns Row active to Row active delay tRRD 15 ns Write recovery time tWR 15 ns Last data in to Read command tCDLR 1 tCK Col Address to Col Address delay tCCD 1 tCK Clock cycle time tCK 7 5 12 ns Clock high level width tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time from CK CK tDQSCK 0 75 0 75 ns Output data access time from CK CK TAC 0 75 0 75 ns Data strobe edge to output data edge tDQSQ 0 5 ns Read Preamble tRPRE 0 9 1 1 tCK Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 75 1 25 tCK DQS in setup time tWPRES 0 ns 2 DQS in hold time tWPREH 0 25 tCK DQS falling edge to CK rising setup time TDSS 0 2 tCK DQS falling edge from CK rising hold time TDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK DQS in cycle time TDSC 0 9 1 1 tCK Address and Control input setup time TIS 0 9 ns Address and Control
4. 64Mx4 CL2 5 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 VREF 47 SDQS8 93 VSS 139 VSS 02 SDQO 48 SAO 94 SDQ4 140 SDM8 03 VSS 49 SCB2 95 SDQ5 141 SA10 04 SDQ1 50 VSS 96 VDDQ 142 SCB6 05 SDQSO 51 SCB3 97 SDMO 143 VDDQ 06 SDQ2 52 SBA1 98 SDQ6 144 SCB7 07 VDD 53 SDQ32 99 SDQ7 145 VSS 08 SDQ3 54 VDDQ 100 VSS 146 SDQ36 09 NC 55 SDQ33 101 NC 147 SDQ37 10 RESET 56 SDQS4 102 NC 148 VDD 11 VSS 57 SDQ34 103 NC 149 SDM4 12 SDQ8 58 VSS 104 VDDQ 150 SDQ38 13 SDQ9 59 SBAO 105 SDQ12 151 SDQ39 14 DQS1 60 SDQ35 106 SDQ13 152 VSS 15 VDDQ 61 SDQ40 107 SDM 153 SDQ44 16 CK1 62 VDDQ 108 VDD 154 SRAS 17 CK1 63 SWE 109 SDQ14 155 SDQ45 18 VSS 64 SDQ41 110 SDQ15 156 VDDQ 19 SDQ10 65 ISCAS 111 SCKE1 157 SCSO 20 SDQ11 66 VSS 112 VDDQ 158 SCS1 21 SCKEO 67 SDQS5 113 NC 159 SDM5 22 VDDQ 68 SDQ42 114 SDQ20 160 VSS 23 SDQ16 69 SDQ43 115 SA12 161 SDQ46 24 SDQ17 70 VDD 116 VSS 162 SDQ47 25 SDQS2 71 NC 117 SDQ21 163 NC 26 VSS 72 SDQ48 118 SA11 164 VDDQ 27 SA9 73 SDQ49 119 SDM2 165 SDQ52 28 SDQ18 74 VSS 120 VDD 166 SDQ53 29 SA7 75 CK2 121 SDQ22 167 NC 30 VDDQ 76 CK2 122 SA8 168 VDD 31 SDQ19 77 VDDQ 123 SDQ23 169 SDM6 32 SA5 78 SDQS6 124 VSS 170 SDQ54 33 SDQ24 79 SDQ50 125 SA6 171 SDQ55 34 VSS 80 SDQ51 126 SDQ28 172 VDDQ 35 SDQ25 81 VSS 127 SDQ29 173 NC 36 SDQS3 82 NC 128 VDDQ 174 SDQ60 37 SA4 83 SDQ56 129 SDM3 175 SDQ61 38 VDD 84 SDQ57 130 SA3 176 VSS 39 SDQ26 85 VDD 131 SDQ30 177 SDM7 40 SDQ27 86 SDQS
5. 7 132 VSS 178 SDQ62 41 SA2 87 SDQ58 133 SDQ31 179 SDQ63 42 VSS 88 SDQ59 134 SCB4 180 VDDQ 43 SA1 89 VSS 135 SCB5 181 EAO 44 SCBO 90 NC 136 VDDQ 182 EA 45 SCB1 91 SDA 137 CKO 183 EA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Please refer Block Diagram Transcend Information Inc TS64MDR72V6L5 Block Diagram 184Pin DDR266 Registered DIMM 512MB with 64Mx4 CL2 5 SDQ0 SDQ63 DQ0 DQ3 j DQO0 DQ3 DQ0 DQ3 DQ0 DQ3 SA0 SA12 SBA0 SBA1 RAO RA12 RBA0 RBA1 A0 A12 A0 A12 A0 A12 A0 A12 ISRAS 7RRAS BAO BA1 777BA0 BA1 BAO BA1 T71BA0 BA1 ISCAS IRCAS IRAS gana ROS aina IRAS cama RAS pana ICAS DDR CAS DDR ICAS DDR CAS SDRAM ISWE RWE SDRAM SDRAM SDRAM SCSO RCSO Nis fal ibe ies I 3 CSO x CSO x CSO x CSO O 5 SCKEO RCKEO go g Q g S 238 CKEO 9 x CKEO BS CKEO M ckeo Zas scBo scB3 nl ae spas2 spas3 ial PCK1 PCK1 PCK2 PCK2 PCK3 PCK3 PCK4 PCK4 PCK5 PCK5 DQ0 DQ3 DQ0 DQ3 77 DQ0 DQ3 DQ0 DQ3 A0 A12 f AO A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 vo RAS RAS _ RAS RAS aa 64Mx4 64Mx4 64Mx4 64Mx4 o ICAS DDR ICAS DDR CAS DDR ICAS DDR we SPRAM H ye SPRAM E yg SDRAM me SDRAM o xH yi tS x 4 CSO aa CSO nd CS
6. CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current lI 2 2 uA Output leakage current lOZ 5 5 uA Output High Current Normal strength driver OH 16 8 mA VOUT VTT 0 84V Output Low Current Normal strength driver IOL 16 8 mA VOUT VTT 0 84V Output High Current Half strength driver IOH 9 mA VOUT VTT 0 45V Output High Current Half strength driver IOL 9 mA VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 2OMHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc lev
7. O CSO g f s gt x m ckeEo amp CKeO g CKEO AG SDAS4 sDQS5 spas6 SDQS7 PCK6 PCK6 PCK7 PCK7 PCK8 PCK8 PCK9 PCK9 DQ0 DQ3 j DQ0 DQ3 j DQ0 DQ3 DQ0 DQ3 AO A12 A0 A12 A0 A12 A0 A12 BAO BA1 T71BAO BA1 77 BAO BA1 7 1BA0 BA1 IRAS ama RAS cana IPAS ante PRAS SiN ICAS DDR CAS DDR CAS DDR CAS SDRAM awe SDRAM aye SPRAM _ hyg SDRAM Vel E 5 ICS0 5 W cso 5 cso CSO SAE gS ge g EE IRESET CKEO 9 M ckEo S g CkKE0 amp cko SAS PCK10 PCK10 ScBo scB3 _ re Spose SDQS2 J spas3 sees PCK1 PCK1 PCK2 PCK2 PCK3 PCK3 PCK4 PCK4 PCK5 PCK5 DQ0 DQ3 DQ0 DQ3 DQ0 DQ3 DQO0 DQ3 A0 A12 A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 RAS IRAS M RAS RAS 64Mx4 64Mx4 64Mx4 64Mx4 ICAS DDR ICAS DDR 7 CAS DDR ICAS DDR we SPRAM aye SPRAM yg SDRAM me SDRAM S a x x CSO oO CSO O CSO oO CSO oO gS get ge 82 CKEO amp SJ CKEO amp G T cKEO AS CKEO AG Sspas4_ spas5 spas J spas7 J PCK6 PCK6 PCK7 PCK7 PCK8 PCK8 PCK9 PCK9 PCK10 PCK10 PCK1 PCK1 PCK2 PCK2 Serial PCK3 PCK3 EEPROM ckoscko PLL pcxsypcks sct SDA PCK6 PCK6 PCK7 PCK7 AO A1 A2 En cho eht eka This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specificatio
8. TS64MDR72V6L5 184Pin DDR266 Registered DIMM 512MB with 64Mx4 CL2 5 Description The TS64MDR72V6L5 is a Low Profile 64M x 72bits Double Data Rate SDRAM high density for PC 266 The TS64MDR72V6L5 consists of 18pcs CMOS 64Mx4 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages 2pcs drive ICs for input control signal 1pcs PLL and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS64MDR72V6L5 is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Max clock Freq 133MHZ e Burst Mode Operation e Auto and Self Refresh e All inputs except data amp DM are sampled at the positive going edge of the system clock ck e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data input e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e Single 2 5V 0 2V power supply e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Information Inc Placement
9. el of the same Transcend Information Inc 184Pin DDR266 Registered DIMM TS64MDR72V6L5 512MB with 64Mx4 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin tCK tCK min DQ DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle Operating current One bank Active Read Precharge Burst 4 tRC tRC min CL 2 5 tCK tCK min VIN VREF fro DQ DQS and DM Precharge power down standby current All banks idle Power down mode CKE lt VIL max tCK tCK min IDD2P 750 mA VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 133Mhz for DDR266 Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max tCK tCK min IDD3P 1 020 mA VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min One bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle IDDO 2 280 mA IDD1 2 640 mA IDD2F 1 110 mA IDD3N 1 380 mA Operating current burst read Burst len
10. ge time tRAS 45ns 2D 31 Module ROW density 512MB 80 32 Command Address Input Setup Time 0 9ns 90 33 Command Address Input Hold Time 0 9ns 90 34 Data Signal Input Setup Time 0 5ns 50 Transcend Information Inc i 184Pin DDR266 Registered DIMM 512MB with 64Mx4 CL2 5 TS64MDR72V6L5 35 Data Signal Input Hold Time 0 5ns 50 36 61 Superset Information 00 62 SPD Data Revision Code 00 63 Checksum for Bytes 0 62 10 64 71 Manufacturers JEDEC ID Transcend TF 4F 72 __ Manufacturing Location T 54 54 53 36 34 4D 44 73 90 Manufacturers Part Number TS64MDR72V6L5 52 37 32 56 36 4C 35 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Unused Storage Locations Undefined Transcend Information Inc 11
11. gth 2 reads continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at IDD4R 3 810 mA tCK tCK min 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK tCK min DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst IDD4W 4 620 mA Auto refresh current tRC tRFC min IDD5 4 170 mA Self refresh current CKE lt 0 2V IDD6 354 mA Orerating current Four bank operation Four bank interleaving with BL 4 IDD7 7 140 mA Refer to the following page for detailed test condition Note 1 These parameters depend on the cycle rate and these values are measured a cycle rate with the minimum values of tCK and Trc 2 These parameters depend on the output loading Specified values are obtained with the output open Transcend Information Inc 184Pin DDR266 Registered DIMM TS64MDR72V6L5 512MB with 64Mx4 CL2 5 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 V 3 Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V 3 Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK
12. input hold time TIH 0 9 ns Data out high impedance time from CK CK THZ TACmin 400ps TACmax 400ps ps Data out low impedance time from CK CK TLZ TACmin 400ps TACmax 400ps ps Mode register set cycle time TMRD 15 ns DQ amp DM setup time to DQS TDS 0 5 ns DQ amp DM hold time to DQS TDH 0 5 ns DQ amp DM input pulse width tDIPW 1 75 ns Power down exit time tPDEX 10 ns Exit self refresh to write command tXSW 95 ns Exit self refresh to write command tXSA 75 ns Exit self refresh to read command tXSR 200 Cycle Refresh interval time tREF 7 8 us 1 Clock half period tHP tCLmin or ns tCHmin Data hold skew factor tQHS 0 75 ns DQS write postamble time tWPST 0 25 tCK 3 Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High_Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly 4 For registered DIMMs tCL and tCH are 45 of the period including both the half period jitter tUIT HP of the PLL and the half period jitter due to crosstalk tUIT crosstalk on the DIMM Transcend Information Inc 184Pin DDR266 Registered DIMM
13. inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 0 2 V 2 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation the AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Value Unit Note Input reference voltage for Clock 0 5 VDDQ V Input signal maximum peak swing 1 5 V Input Levels VIH VIL VREF 0 31 VREF 0 31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V Output load condition See Load Circuit VIT 0 5 VDDQ Reson Output Q ZO 500hm iz VREF 2 0 5 VDDQ CLoap 30pF Output Load circuit Input Output CAPACITANCE Von 2 5V Vopa 2 5V TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance AO A12 BAO BA1 RAS CAS WE CIN1 12 pF Input capacitance CKE0 CIN2 12 pF Input capacitance CSO CIN3 11 pF Input capacitance CLKO CLKO CIN4 12 pF Data and DQS input output capacitance DQ0 DQ63 CIN5 16 pF Input capacitance DMO DM8 CouT1 16 pF Data input output
14. ns at any time without prior notice Transcend Information Inc 184Pin DDR266 Registered DIMM TS64MDR72V6L5 512MB with 64Mx4 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 C Power dissipation PD 18 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 3 2 7 V I O Supply voltage VDDQ 2 3 2 7 V I O Reference voltage VREF VDDQ 2 50mV Vpba 2 50mV V 1 1 O Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and
15. precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAO BA1 Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected 5 If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected 6 During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM CIS TIE SI Transcend Information Inc 184Pin DDR266 Registered DIMM TS64MDR72V6L5 512MB with 64Mx4 CL2 5 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described S
16. tandard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 oD 4 of Column Addresses on this Assembly 11 0B 5 of Module Rows on this Assembly 1 bank 01 6 Data Width of this Assembly 72bits 48 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 5V 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 7 5ns 75 10 DDR SDRAM Access Time from Clock at CL 2 5 0 75ns 75 11 DIMM configuration type non parity Parity ECC ECC 02 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width x4 04 14 Error Checking DDR SDRAM Width X4 04 15 Min Clock Delay for Back to tCCD 1CLK 01 Back Random Column Address 16 Burst Lengths Supported 2 4 8 OE 17 _ of banks on each DDR SDRAM device 4 bank 04 18 CAS Latency supported 2 2 5 0C 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 Registered address amp 21 DDR SDRAM Module Attributes control inputs and 26 on card DLL 22 DDR SDRAM Device Attributes General 0 2V voltage tolerance 00 23 DDR SDRAM Cycle Time CL 2 0 10ns AO 24 DDR SDRAM Access from Clock CL 2 0 0 75ns 75 25 DDR SDRAM Cycle Time CL 1 5 00 26 DDR SDRAM Access from Clock CL 1 5 00 27 Minimum Row Precharge Time tRP 20ns 50 28 Minimum Row Active to Row Activate delay tRRD 15ns 3C 29 Minimum RAS to CAS Delay tRCD 20ns 50 30 Minimum active to Prechar
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