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Intel Core i7-2960XM

1. Table 2 7 Device 3 Function 1 Target Address Decoder Registers DID VID 00h TAD DRAM RULE 0 PCISTS PCICMD 04h TAD DRAM RULE 1 CCR RID 08h TAD DRAM RULE 2 HDR OCh TAD_DRAM_RULE_3 10h TAD_DRAM_RULE_4 14h TAD_DRAM_RULE_5 18h TAD_DRAM_RULE_6 1Ch TAD_DRAM_RULE_7 20h 24h 28h SID SVID 2Ch 30h 34h 38h 3Ch 40h TAD INTERLEAVE LIST 0 44h TAD INTERLEAVE LIST 1 48h TAD INTERLEAVE LIST 2 4Ch TAD INTERLEAVE LIST 3 50h TAD INTERLEAVE LIST 4 54h TAD INTERLEAVE LIST 5 58h TAD INTERLEAVE LIST 6 5Ch TAD INTERLEAVE LIST 7 60h 64h 68h 6Ch 70h 74h 78h 7Ch Datasheet 80h 84h 88h 8Ch 94h 98h 9Ch AOh A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh FOh F4h F8h FCh 23 intel Register Description Table 2 8 Device 4 Function 0 Integrated Memory Controller Channel 0 Control Registers DID VID 00h MC CHANNEL 0 RANK TIMING A 80h PCISTS PCICMD 04h MC CHANNEL 0 RANK TIMING B 84h CCR RID 08h MC CHANNEL 0 BANK TIMING 88h HDR OCh MC_CHANNEL_0_REFRESH_TIMING 8Ch 10h MC_CHANNEL_0_CKE_TIMING 90h 14h MC_CHANNEL_0_ZQ_TIMING 94h 18h MC_CHANNEL_0_RCOMP_PARAMS 98h 1Ch MC_CHANNEL_0_ODT_PARAMS1 9Ch 20h MC CHANNEL 0 ODT PARAMS2 24h MC_CHANNEL_0_ODT_MATRIX
2. MC CHANNEL 0 DIMM INIT STATUS MC CHANNEL 1 DIMM INIT STATUS MC CHANNEL 2 DIMM INIT STATUS cse MC CHANNEL 0 DDR3CMD MC CHANNEL 1 DDR3CMD CHANNEL 2 DDR3SCMED nt terrens MC CHANNEL 0 REFRESH THROTTLE SUPPORT MC CHANNEL 1 REFRESH THROTTLE SUPPORT MC CHANNEL 2 REFRESH THROTTLE 5 0 MC CHANNEL 0 MRS VALUE 0 1 MC CHANNEL 1 MRS VALUE 0 1 MC CHANNEL 2 MRS VALUE _1 MC CHANNEL 0 MRS VALUE 2 MC CHANNEL 1 MRS VALUE 2 MC CHANNEL 2 MRS 2 MC CHANNEL 0 RANK PRESENT MC CHANNEL 1 RANK PRESENT MC CHANNEL 2 RANK MC CHANNEL 0 RANK TIMING A MC CHANNEL 1 RANK TIMING A MC CHANNEL 2 RANK TIMING_A Hee MC CHANNEL 0 RANK TIMING B MC CHANNEL 1 RANK TIMING B MC CHANNEL 2 RANK 8 He MC CHANNEL 0 BANK TIMING MC CHANNEL 1 BANK TIMING MC CHANNEL 2 BANK MC CHANNEL 0 REFRESH_ TIMING MC_CHANNEL_1_REFRESH_ TIMING MC CHANNEL 2 5 MC_CHANNEL_ 0_CKE_TIMING MC CHANNEL 1 CKE TIMING MC CHANNEL 2 CKE ee nnne MC CHANNEL 0 20 TIMING MC CHANNEL 1 ZQ TIMING MC CHANNEL 2 ZO TIMING
3. DID VID 00h MC CHANNEL 2 RANK TIMING A 80h PCISTS PCICMD 04h MC CHANNEL 2 RANK TIMING B 84h CCR RID 08h MC CHANNEL 2 BANK TIMING 88h HDR OCh MC_CHANNEL_2_REFRESH_TIMING 8Ch 10h MC_CHANNEL_2_CKE_TIMING 90h 14h MC CHANNEL 2 ZQ TIMING 94h 18h MC CHANNEL 2 RCOMP PARAMS 98h 1Ch MC_CHANNEL_2_ODT_PARAMS1 9Ch 20h MC_CHANNEL_2_ODT_PARAMS2 AOh 24h MC CHANNEL 2 ODT MATRIX RANK 0 3 RD A4h 28h MC CHANNEL 2 ODT MATRIX RANK 4 7 RD A8h SID SVID 2Ch MC CHANNEL 2 ODT MATRIX RANK 0 3 WR ACh 30h MC CHANNEL 2 ODT MATRIX RANK 4 7 WR BOh 34h MC CHANNEL 2 WAQ PARAMS B4h 38h MC CHANNEL 2 SCHEDULER PARAMS B8h 3Ch MC CHANNEL 2 MAINTENANCE OPS BCh 40h MC CHANNEL 2 TX BG SETTINGS COh 44h C4h 48h MC CHANNEL 2 RX BGF SETTINGS C8h 4Ch MC_CHANNEL_2_EW_BGF_SETTINGS CCh MC CHANNEL 2 DIMM RESET CMD 50h MC CHANNEL 2 EW BGF OFFSET SETTINGS DOh MC CHANNEL 2 DIMM INIT CMD 54h MC CHANNEL 2 ROUND TRIP LATENCY D4h MC_CHANNEL_2_DIMM_INIT_PARAMS 58h MC_CHANNEL_2_PAGETABLE_PARAMS1 D8h MC_CHANNEL_2_DIMM_INIT_STATUS 5Ch MC_CHANNEL_2_PAGETABLE_PARAMS2 DCh MC_CHANNEL_2_DDR3CMD 60h MC_TX_BG_CMD_DATA_RATIO_SETTING_CH2 EOh 64h MC TX BG CMD OFFSET SETTINGS CH2 E4h MC CHANNEL 2 REFRESH THROTTLE SUPPORT 68h MC TX BG DATA OFFSET SETTINGS CH2 E8h 6Ch ECh MC CHANNEL 2 MRS VALUE 0 1 70h MC CHANNEL 2 ADDR MATCH FOh MC_CHANNEL_2_MRS_VALUE_2 74h F4h 78h MC_CHANNEL_2_ECC_ERROR_MASK F8h MC_CHANNEL_2_RANK_PRESENT 7Ch MC CHANNEL 2 ECC ERROR INJECT F
4. MC CHANNEL 0 RCOMP PARAMS MC CHANNEL 1 RCOMP PARAMS MC CHANNEL 2 PARAMS Fe belts e i MC CHANNEL 0 ODT 51 MC CHANNEL 1 ODT 51 MC CHANNEL 2 ODT 51 MC CHANNEL 0 ODT PARAMS2 MC CHANNEL 1 ODT PARAMS2 MC CHANNEL 2 ODT 2 Datasheet Datasheet 10 19 10 20 10 21 10 22 10 23 10 24 10 25 10 26 10 27 10 28 10 29 10 30 10 31 10 32 10 33 10 34 10 35 10 36 10 37 10 38 MC CHANNEL 0 ODT MATRIX RANK 0 3 RD MC CHANNEL 1 ODT MATRIX RANK 0 3 RD MC CHANNEL 2 ODT MATRIX RANK 0 3 RD MC CHANNEL 0 ODT MATRIX RANK 4 7 RD MC CHANNEL 1 ODT MATRIX RANK 4 7 RD MC CHANNEL 2 ODT MATRIX RANK 4 7 RD MC CHANNEL 0 ODT MATRIX RANK 0 3 WR MC CHANNEL 1 ODT MATRIX RANK 0 3 WR MC CHANNEL 2 ODT MATRIX RANK 0 MC CHANNEL 0 ODT MATRIX RANK 4 MC CHANNEL 1 ODT MATRIX RANK 4 MC CHANNEL 2 ODT MATRIX RANK 4 MC CHANNEL 0 WAQ PARAMS MC CHANNEL 1 WAQ PARAMS MC CHANNEL 2 WAQ PARAMS MC CHANNEL 0 SCHEDULER PARAMS MC CHANNEL 1 SCHEDULER PARAMS MC CHANNEL 2 SCHEDULER PARAMS MC CHANNEL 0 MAINTENANCE OPS MC CHANNEL 1 MAINTENANCE OPS MC CHANNEL 2 MAINTENANCE OPS MC CHANNEL 0 TX BG SETTINGS MC CHANNEL 1 TX BG SETTINGS MC CHANNEL 2 TX BG SETTINGS MC CHANNEL 0 RX
5. Term Description RO Read Only If a register bit is read only the hardware sets its state The bit may be read by software Writes to this bit have no effect WO Write Only The register bit is not implemented as a bit The write causes some hardware event to take place RW Read Write A register bit with this attribute can be read and written by software RC Read Clear The bit or bits can be read by software but the act of reading causes the value to be cleared RCW Read Clear Write A register bit with this attribute will get cleared after the read The register bit can be written RW1C Read Write 1 Clear A register bit with this attribute can be read or cleared by software In order to clear this bit a one must be written to it Writing a zero will have no effect RWOC Read Write Clear A register bit with this attribute can be read or cleared by software In order to clear this bit a zero must be written to it Writing a one will have no effect Read Write 1 Set A register bit can be either read or set by software In order to set RWIS this bit a one must be written to it Writing a zero to this bit has no effect Hardware will clear this bit Read Write Set A register bit can be either read or set by software In order to set RWOS this bit a zero must be written to it Writing a one to this bit has no effect Hardware will clear this bit RWL Read Write Lock A register bit wit
6. 40 2 6 SAD System Address Decoder Registers 41 2 6 1 SAD PAMO L23 lt E ERR RA RE a 41 2 6 2 SAD PAM4506 u exc per 43 2 6 3 SAD HEN reine 44 2 6 4 SAD 5 44 2 6 5 SAD PCIEXBAR 45 2 6 6 SAD DRAM RULE 0 SAD DRAM RULE 1 SAD DRAM RULE 2 SAD DRAM RULE 3 SAD DRAM RULE 4 SAD DRAM RULE 5 SAD DRAM RULE 6 SAD DRAM RULE 7 Ce nro 45 2 6 7 540 INTERLEAVE_ LIST 0 SAD_ INTERLEAVE LIST 1 SAD INTERLEAVE LIST 2 SAD INTERLEAVE LIST 3 SAD INTERLEAVE LIST 4 SAD INTERLEAVE LIST 5 SAD INTERLEAVE LIST 6 SAD INTERLEAVE LIST _7 46 2 7 Intel Link 47 2 7 1 OPI OPIECL 10 ET ha Rhe 47 2 8 Integrated Memory Controller Control Registers rr 47 2 8 1 nemen 47 2 8 2 MC STATUS L us 49 2 8 3 MC SMI SPARE DIMM ERROR 50 2 8 4 SPARE resins pinata tan RA a u qual 51 2 8 5 MC RESET CONTROL nu DU AIRE IRL S MEA
7. Device 0 Function 0 1 Offset 06h Device 2 Function 0 1 4 5 Offset 06h Device 3 Function 0 2 4 Offset 06h Device 4 6 Function 0 3 Offset 06h Reset cl Bit Type Value Description 15 RO 0 Detect Parity Error DPE The host bridge does not implement this bit and is hardwired to a O Signaled System Error SSE 14 RO 0 This bit is set to 1 when this device generates an SERR message over the bus for any enabled error condition If the host bridge does not signal errors using this bit this bit is hardwired to a 0 and is read only Received Master Abort Status RMAS This bit is set when this device generates request that receives an Unsupported 13 RO 0 Request completion packet Software clears the bit by writing 1 to it If this device does not receive Unsupported Request completion packets the bit is hardwired to 0 and is read only Received Target Abort Status RTAS This bit is set when this device generates a request that receives a Completer 12 RO 0 Abort completion packet Software clears this bit by writing a 1 to it If this device does not receive Completer Abort completion packets this bit is hardwired to 0 and read only Signaled Target Abort Status STAS 11 RO 0 This device will not generate a Target Abort completion or Special Cycle This bit is not implemented in this device and is hardwired to a DEVSEL Timing DEVT 10 9 RO 0 These bits are hardwired to 00 This device does not physic
8. 2 13 2 MC THERMAL STATUSO MC THERMAL STATUSI MC THERMAL STATUS2 Status registers for the thermal throttling logic for each channel Device 4 5 6 Function 3 Offset 4Ch Access as a Dword Bit Type Description CYCLES THROTTLED 29 4 RO 0 The number of throttle cycles in increments of 256 Dclks triggered in any rank in the last SAFE INTERVAL number of ZQs RANK TEMP a0 RO 9 The bit specifies whether the rank is above throttling threshold 92 Datasheet Register Description tel 2 13 3 2 13 4 Datasheet MC THERMAL DEFEATUREO MC THERMAL DEFEATUREI1 MC THERMAL DEFEATURE2 Thermal Throttle defeature register for each channel Device 4 5 6 Function 3 Offset 50h Access as a Dword Reset Bit Type Value Description THERM REG LOCK 0 RWIS 0 When set no further modification of all thermal throttle registers are allowed This bit must be set to the same value for all channels MC_THERMAL_PARAMS_ AO MC_THERMAL_PARAMS_ 41 MC THERMAL 5 A2 Parameters used by Open Loop Throughput Throttling OLTT and Closed Loop Thermal Throttling CLTT Device 4 5 6 Function 3 Offset 60h Access as a Dword Bit Type Description CKE_ASSERT_ENERGY 31 24 RW 0 Energy of having CKE asserted when no command is issued CKE DEASSERT ENERGY 23 16 RW 0 _ Par Energy of having CKE de asserted when n
9. Bit Type Value Description MASK DI MM RW 0 1 If set ignore DIMM address during address comparison MASK RANK 40 0 1 If set ignore RANK address during address comparison MASK BANK 39 0 1 If set ignore BANK address during address comparison MASK 38 RW 0 F i If set ignore PAGE address during address comparison MASK COL 7 RW 3 0 1 If set ignore COLUMN address during address comparison DIMM 36 RW 0 DIMM address for 1 or 2DPC For 3DPC bits 36 and 35 represent the DIMM address and bit 34 represent the RANK address RANK 35 34 RW 0 Rank address for 1 or 2DPC For 3DPC bits 36 and 35 represent the DIMM address and bit 34 represent the RANK address 33 30 RW 0 BANK Bank address 29 14 RW 0 PAGE Page address 13 0 RW 0 COLUMN Column address 81 m e n tel Register Description 2 10 37 2 10 38 82 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK MC CHANNEL 2 ECC ERROR MASK This register contains mask bits for the memory controller and specifies at which ECC bit s the error injection should occur Any bits set to a 1 will flip the corresponding ECC bit Correctable errors can be injected by flipping 1 bit or the bits within a symbol pair 2 consecutive aligned 8 bit pairs i e 7 0 and 15 8 or 23 16 and 31 24 Flipping bits in two symbol pairs will cause an uncorrectable error to be injected Device 4 5 6 Function Offset F8h Access as
10. Reset TN Bit Type Value Description 27 RW 0 ENABLEADAPTI VEPAGECLOSE 1 Enables Adaptive Page Closing 26 18 RW 0 MI NPAGECLOSELI MI T This field is the upper 9 MSBs of a 13 bit threshold limit When the mistake counter falls below this threshold a less aggressive page close interval larger is selected 17 9 RW 0 MAXPAGECLOSELI MI T This field is the upper 9 bits of a 13 bit threshold limit When the mistake counter exceeds this threshold a more aggressive page close interval smaller is selected 8 0 RW 0 MI STAKECOUNTER This field is the upper 8 MSBs of a 12 bit counter This counter adapts the interval between assertions of the page close flag For a less aggressive page close the length of the count interval is increased and vice versa for a more aggressive page close policy Datasheet 79 intel 2 10 33 2 10 34 2 10 35 80 MC TX BG CMD DATA RATIO SETTINGS CHO MC TX BG CMD DATA RATIO SETTINGS 1 MC TX BG CMD DATA RATIO SETTINGS CH2 Channel Bubble Generator ratios for CMD and DATA Device 4 5 6 Function Offset EOh Access as a Dword Bit Type Pares Description 15 8 RW 1 ALI ENRATI O DCLK to BCLK ratio 7 0 RW 4 NATI VERATI O UCLK to BCLK ratio MC TX BG CMD OFFSET SETTINGS CHO MC TX BG CMD OFFSET SETTINGS 1 MC TX BG CMD OFFSET SETTINGS CH2 Integrated Memory Controller Channel Bubble Generator Offsets for CMD FIFO The Data command FIFOs share th
11. 13 14 Introduction Datasheet Register Description tel 2 2 1 Datasheet Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification Revision 2 3 as well as the Express enhanced configuration mechanism as specified in the PCI Express Base Specification Revision 1 1 All the registers are organized by bus device function etc as defined in the Express Base Specification Revision 1 1 All processor registers appear on the PCI bus assigned for the processor socket Bus number is derived by the max bus range setting and processor socket number All multi byte numeric fields use little endian ordering i e lower addresses contain the least significant parts of the field As processor features vary by component not all of the register descriptions in this document apply to all processors This document highlights registers which do not apply to all processor components Refer to the particular processor s Specification Update for a list of features supported Register Terminology Registers and register bits are assigned one or more of the following attributes These attributes define the behavior of register and the bit s that are contained with in All bits are set to default values by hard reset Sticky bits retain their states between hard resets
12. 01 Logical channel 1 10 Logical channel 2 11 Reserved ll ll Logical ChannelO Index 000 of the Interleave List Bits determined from the matching TAD DRAM RULE mode 1 0 RW 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved ll Integrated Memory Controller Channel Control Registers MC CHANNEL 0 DIMM RESET CMD MC CHANNEL 1 DIMM RESET CMD MC CHANNEL 2 DIMM RESET CMD Integrated Memory Controller DI MM reset command register This register is used to sequence the reset signals to the DIMMs Device 4 5 6 Function Offset 50h Access as a Dword Bit Type Description BLOCK_CKE 2 RW 0 e When set will be forced to be deasserted ASSERT_ RESET 1 RW 0 a When set Reset will be driven to the DIMMs RESET 0 WO 0 Reset the DIMMs Setting this bit will cause the Integrated Memory Controller DIMM Reset state machine to sequence through the reset sequence using the parameters in MC DIMM INIT PARAMS 59 m e tel Register Description 2 10 2 MC CHANNEL 0 DIMM INIT CMD MC CHANNEL 1 DIMM INIT CMD MC CHANNEL 2 DIMM INIT CMD Integrated Memory Controller DI MM initialization command register This register is used to sequence the channel through the physical layer training required for DDR Device 4 5 6 Function Offset 54h Access as a Dword 5
13. 13 4 RW This field defines the offset used in the rank interleave This is a 2 s complement value 0 RANK This field defines which rank participates in WAY n If MC CLOSEDPAGE 1 this field defines the DRAM rank selected when MemoryAddress 7 6 n If 3 0 RW MC CLOSEDPAGE 0 this field defines which rank is selected when 1 0 are the rank within that DIMM MemoryAddress 13 12 n n is the instantiation of the register This field is organized by physical rank Bits 3 2 are the encoded DIMM ID slot Bits 89 2 12 3 90 MC_RIR_WAY_CH1_0 MC RIR WAY 1 1 MC RIR WAY CH1 2 MC RIR WAY 1 3 MC WAY CH1 4 MC RIR WAY 1 5 MC WAY 1 6 MC RIR WAY 1 7 MC RIR WAY 1 8 MC RIR WAY 1 9 MC WAY 1 10 RIR WAY 11 MC WAY 1 12 MC WAY 1 13 MC WAY 1 14 MC WAY 1 15 MC WAY 1 16 MC WAY 1 17 MC WAY 1 18 MC WAY 1 19 MC WAY CH1 20 MC RIR WAY 1 21 MC WAY CH1 22 MC WAY 1 23 MC WAY 1 24 MC WAY 1 25 MC WAY 1 26 MC WAY 1 27 MC WAY 1 28 MC WAY 1 29 MC RIR WAY CHI 30 MC RIR WAY 1 31 Register Description Channel Rank Interleave Way Range Registers These registers allow the user to define the ranks and offsets that apply to the ranges defined by the
14. 6 110 lt 7 111 gt 8 25 23 RW tdrWrTRd Minimum delay between a write followed by a read to different ranks on the same DIMM 000 1 001 2 010 3 011 4 100 5 101 6 110 lt 7 111 28 22 19 RW tsrWrTRd Minimum delay between a write followed by a read to the same rank 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 10 11 12 13 14 15 16 17 18 19 20 21 22 Datasheet Register Description Datasheet Device 4 5 6 Function 0 Offset 80h Access as a Dword tddRdTWr Minimum delay between Read followed by a Write to different DI MMs 0000 2 0001 3 0010 4 00115 0100 6 18 15 RW 0101 27 0110 8 0111 29 1000 10 1001 11 1010 12 1011 13 1100 14 tdrRdTWr Minimum delay between Read followed by a write to different ranks on the same DIMM 0000 2 0001 3 0010 4 0011 5 0100 6 14 11 RW 0101 7 0110 8 0111 gt 9 1000 10 1001 11 1010 12 1011 13 1100 14 tsrRdTWr Minimum delay between Read followed by a write to the same rank 0000 RSVD 0001 RSVD 0010 RSVD 0011 lt 5 0100 6 10 7 RW 0101 27 0110 8 0111 9 1000 10 1001 11 1010 12 1011 13 1100 14 67 68 Register Description Device 4 5 6 Function 0 Offset 80h Access as a Dword tddRdTRd Minimum delay between reads to dif
15. Device Offset 3 Function 70h Access as a Dword Bit Type Value Description 20 16 RW 3 CRDT_RD_CRIT Critical Read Credits 12 8 RW 1 CRDT_RD_HIGH High Read Credits 4 0 RW 13 CRDT_ RD Normal Read Credits Datasheet Register Description 2 8 9 2 8 10 Datasheet MC CRDT WR THLD This is the Memory Controller Write Credit Thresholds register A Write threshold is defined as the number of credits reserved for this priority or higher request It is required that High threshold be greater than or equal to Crit threshold and that both be lower than the total Write Credit init value BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform The new values take effect immediately upon being written Register programming rules CRIT threshold value must correspond to the number of critical RTIDs reserved at the IOH HIGH threshold value must correspond to the sum of critical and high RTIDs reserved at the which must not exceed 30 e Set MC Channel WAQ PARAMS I SOCENTRYTHRESHHOLD equal to 31 CRIT intel Device 3 Function Offset 74h Access as a Dword Bit Type enm Description 12 8 RW 4 HI GH High Credit Threshold 4 0 RW 3 CRIT Critical Credit Threshold MC SCRUBADDR LO This register contains part of the address of the last patrol scrub request issued When
16. TAD DRAM RULE mode 29 28 RW 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved Logical Channel6 Index 110 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 25 24 RW 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved Logical Channel5 Index 101 of the Interleave List Bits determined from the matching TAD DRAM RULE mode 21 20 RW 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved Logical Channel4 Index 100 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 17 16 RW 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved Logical Channel3 Index 011 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 13 12 RW 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved Datasheet Register Description tel 2 10 2 10 1 Datasheet Device 3 Function 1 Offset COh C8h CCh DOh D4h D8h DCh Access as a Dword Logical Channel2 Index 010 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 9 8 RW 2 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved Logical Channel1 Index 001 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 5 4 RW 00 Logical channel 0
17. This field enables a memory hole in DRAM space The DRAM that lies behind this space is not remapped 0 No Memory hole 1 Memory hole from 15 to 16 MB ll 2 6 4 SAD_SMRAM Register for legacy 9Dh address space Note both 1 and non core have this now Device 0 Function 1 Offset 4 Ch Access as a Dword Bit Type Reset Value Description 14 RW SMM Space Open D OPEN When D_OPEN 1 and D_LCK 0 the SMM space DRAM is made visible even when SMM decode is not active This is intended to help BIOS initialize SMM space Software should ensure that D OPEN 1 and D_CLS 1 are not set at the same time 13 RW SMM Space Closed D_ CLS When D_CLS 1 SMM space DRAM is not accessible to data references even if SMM decode is active Code references may still access SMM space DRAM This will allow SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range Software should ensure that D_OPEN 1 and D_CLS 1 are not set at the same time 12 RWIS SMM Space Locked D_LCK When D_LCK is set to 1 then is reset to 0 and D_LCK C_BASE_SEG G_SMRAME PCIEXBAR DRAM_RULEs and INTERLEAVE_LISTs become read only D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Reset The combination of D LCK and D OPEN provide convenience with security The BIOS can use the D OPEN function to
18. that device independent software can use to interact with the device There are no such interfaces defined for Host Bridge types and this field is hardwired to Datasheet 37 m e tel Register Description 2 5 5 HDR Header Type Register This register identifies the header layout of the configuration space Device 0 Function 0 1 Offset OEh Device 2 Function 0 1 4 5 Offset OEh Device 3 Function 0 2 4 Offset OEh Device 4 6 Function 0 3 Offset OEh Reset en Bit Type Value Description Multi function Device 7 RO 1 Selects whether this is a multi function device that may have alternative configuration layouts This bit is hardwired to 1 for devices in the processor Configuration Layout 6 0 RO 0 This field identifies the format of the configuration header layout for a PCI to PCI bridge from bytes 10h through 3Fh For all devices the default is indicating a conventional type 00h PCI header 2 5 6 SI D SVID Subsystem dentity Subsystem Vendor I dentification Register This register identifies the manufacturer of the system This 32 bit register uniquely identifies any PCI device Device 0 Function 0 1 Offset 2Ch 2Eh Device 2 Function 0 1 4 5 Offset 2Ch 2Eh Device 3 Function 0 2 4 Offset 2Ch 2Eh Device 4 6 Function 0 3 Offset 2Ch 2Eh Access as a Dword Reset Value Description Bit Type Subsystem Id
19. the value read from the corresponding in MC_RANK_VIRTUAL_TEMP register is 20h When there are more than 4 ranks attached to the channel the thermal throttle logic is shared Device 4 5 6 Function 3 Offset 98h Access as a Dword Bit Type ee Description 31 24 RO 0 RANKS Rank 3 virtual temperature 23 16 RO 0 RANK2 Rank 2 virtual temperature 15 8 RO 0 RANK1 Rank 1 virtual temperature 7 0 RO 0 RANKO Rank 0 virtual temperature MC DDR THERM COMMANDO MC DDR THERM COMMAND1 MC DDR THERM COMMAND2 This register contains the command portion of the DDR THERM functionality as described in the processor datasheet i e what an assertion of the pin does Device 4 5 6 Function 3 Offset 9Ch Access as a Dword Reset Bit Type Value Description THROTTLE 3 RW 0 Force throttling when DDR_THERM pin is asserted 2 RW 0 Reserved DISABLE_EXTTS 1 RW 0 Response to DDR_THERM pin is disabled ASSERTION and DEASSERTI ON fields in the register MC DDR THERM STATUS are frozen LOCK 0 RW 0 A When set all bits in this register are RO and cannot be written Datasheet Register Description tel 2 13 11 MC_DDR_THERM_STATUSO 2 14 2 14 1 Datasheet MC_DDR_THERM_STATUS1 MC DDR THERM STATUS2 This register contains the status portion of the DDR THERM Z functionality as described in the processor datasheet i e what is happen
20. 48h 4Ch 50h Access as a Dword Bit Type Reset Value Description 12 10 RW RANKOFFSET Rank Offset for calculating RANK This corresponds to the first logical rank on the DIMM The rank offset is always programmed to 0 for the DIMM 0 DOD registers DIMM 0 rank offset is always 0 DIMM 1 DOD rank offset is either 4 for two DIMMs per channel or 2 if there are three DIMMs per channel DIMM2 DOD rank offset is always 4 as it is only used in three DIMMs per channel case RW DI MMPRESENT DIMM slot is populated 8 7 RW NUMBANK Defines the number of real not shadow banks on these DIMMs 00 Four banked 01 Eight banked 10 Sixteen banked 6 5 RW NUMRANK Number of Ranks Defines the number of ranks on these DI MMs 00 Single Ranked 01 Double Ranked 10 Quad Ranked ll 4 2 RW NUMROW Number of Rows Defines the number of rows within these DIMMs 000 2 12 Rows 001 2 13 Rows 010 2 14 Rows 011 2 15 Rows 100 2 16 Rows 1 0 84 RW NUMCOL Number of Columns Defines the number of columns within on these DI MMs 00 2 10 columns 01 2 11 columns 10 2 12 columns 11 RSVD II Datasheet Register Description 2 11 2 Datasheet intel MC_ DOD_ CH1_ 0 MC_ DOD_ CH1_ 1 MC_ DOD_ CH1_ 2 Channel 1 DIMM Organization Descriptor Register Device 5 Function 1 Offset 48
21. 51 2 8 6 MC CHANNEL MAPPER REP vines Hinde ag Gag ud 52 2 8 7 MC MAX WEIN A 53 2 8 8 MG RD CRDT 54 2 8 9 MC WR THE Diii D S aha sa 55 2 8 10 MC SCRUBADDR 0 een neater 55 2 8 11 MC SCRUBADDR iaa erani enina venna EE ETEEN NEEE AEE ana 56 2 9 Target Address Decoder Registers rr 57 2 9 1 DRAM RULE 0 TAD DRAM RULE 1 TAD DRAM RULE 2 TAD DRAM RULE 3 TAD DRAM RULE 4 TAD DRAM RULE 5 TAD DRAM RULE 6 TAD DRAM RULE coh c E Pe cu 57 Datasheet 3 2 9 2 2 10 1 2 10 2 2 10 3 2 10 4 2 10 9 2 10 10 2 10 11 2 10 12 2 10 13 2 10 14 2 10 15 2 10 16 2 10 17 2 10 18 TAD_INTERLEAVE_LIST_0 TAD_INTERLEAVE_LIST_1 TAD INTERLEAVE LIST 2 TAD INTERLEAVE LIST 3 TAD INTERLEAVE LIST 4 TAD INTERLEAVE LIST 5 INTERLEAVE LIST 6 INTERLEAVE LIST 7 2 10 Integrated Memory Controller Channel Control Registers MC CHANNEL 0 DIMM RESET CMD MC CHANNEL 1 DIMM RESET CMD MC CHANNEL 2 DIMM RESET CMD MC CHANNEL 0 DIMM INIT CMD MC CHANNEL 1 DIMM INIT CMD MC CHANNEL 2 DIMM INIT CMD MC CHANNEL 0 DIMM INIT PARAMS MC CHANNEL 1 DIMM INIT PARAMS MC CHANNEL 2 5
22. 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh FOh F4h F8h FCh 18 Datasheet Register Description Table 2 3 Device 0 Function 1 System Address Decoder Registers DID VID 00h SAD DRAM RULE 0 PCISTS PCICMD 04h SAD DRAM RULE 1 CCR RID 08h SAD DRAM RULE 2 HDR OCh SAD_DRAM_RULE_3 10h SAD_DRAM_RULE_4 14h SAD_DRAM_RULE_5 18h SAD_DRAM_RULE_6 1Ch SAD_DRAM_RULE_7 20h 24h 28h SID SVID 2Ch 30h 34h 38h 3Ch SAD PAMO123 40h SAD INTERLEAVE LIST 0 SAD_PAM456 44h SAD_INTERLEAVE_LIST_1 48h SAD_INTERLEAVE_LIST_2 SAD_SMRAM 4Ch SAD_INTERLEAVE_LIST_3 SAD_PCIEXBAR 50h SAD_INTERLEAVE_LIST_4 54h SAD_INTERLEAVE_LIST_5 58h SAD_INTERLEAVE_LIST_6 5Ch SAD_INTERLEAVE_LIST_7 60h 64h 68h 6Ch 70h 74h 78h 7Ch Datasheet 80h 84h 88h 8Ch 94h 98h 9Ch AOh A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh FOh F4h F8h FCh 19 intel Table 2 4 Device 2 Function 0 Intel QPI Link 0 Registers Register Description DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR OCh 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h 24h A4h 28h A8h SID SVID 2Ch AC
23. BGF SETTINGS MC CHANNEL 1 RX BGF SETTINGS MC CHANNEL 2 RX BGF SETTINGS MC CHANNEL 0 EW BGF SETTINGS MC CHANNEL 1 EW BGF SETTINGS MC CHANNEL 2 EW BGF SETTINGS MC CHANNEL 0 EW BGF OFFSET SETTINGS MC CHANNEL 1 EW BGF OFFSET SETTINGS MC CHANNEL 2 BGF OFFSET SETTINGS MC CHANNEL 0 ROUND TRIP LATENCY MC CHANNEL 1 ROUND TRIP LATENCY MC CHANNEL 2 ROUND TRIP LATENCY MC CHANNEL 0 PAGETABLE 51 MC CHANNEL 1 PAGETABLE 51 MC CHANNEL 2 PAGETABLE 51 MC CHANNEL 0 PAGETABLE PARAMS2 MC CHANNEL 1 PAGETABLE PARAMS2 MC CHANNEL 2 PAGETABLE PARAMS2 MC TX BG CMD DATA RATIO SETTINGS CHO MC TX BG CMD DATA RATIO SETTINGS 1 MC TX BG CMD DATA RATIO SETTINGS CH2 MC TX BG CMD OFFSET SETTINGS CHO MC TX BG CMD OFFSET SETTINGS 1 MC TX BG CMD OFFSET SETTINGS CH2 MC TX BG DATA OFFSET SETTINGS CHO MC TX BG DATA OFFSET SETTINGS 1 MC TX BG DATA OFFSET SETTINGS 2 MC CHANNEL 0 ADDR MATCH MC CHANNEL 1 ADDR MATCH MC CHANNEL 2 ADDR MC CHANNEL 0 ECC ERROR MASK MC CHANNEL 1 ECC ERROR MASK MC CHANNEL 2 ECC ERROR MC CHANNEL 0 ECC ERROR INJECT MC CHANNEL 1 ECC ERROR INJECT MC CHANNEL 2 ECC ERROR 3 WR 7 WR 7 WR 7 WR ntel 2 10 39 Error Injection Implementation Integrated Memory Controller Channel Address Registers 2 11 1 2 11 2 2 1
24. E4h 68h MC RIR WAY CHO 26 E8h 6Ch MC RIR WAY CHO 27 ECh 70h MC RIR WAY CHO 28 FOh 74h MC RIR WAY CHO 29 F4h 78h MC RIR WAY CHO 30 F8h 7Ch MC RIR WAY CHO 31 FCh 26 Datasheet Register Description Table 2 11 Device 4 Function 3 Integrated Memory Controller Channel 0 Thermal Control Registers DID VID 00h MC COOLING COEFO PCISTS PCICMD 04h MC CLOSED LOOPO CCR RID 08h MC THROTTLE OFFSETO HDR OCh 10h 14h 18h MC_RANK_VIRTUAL_ TEMPO 1Ch MC DDR THERM COMMANDO 20h 24h MC DDR THERM STATUSO 28h SID SVID 2Ch 30h 34h 38h 3Ch 40h 44h MC THERMAL CONTROLO 48h MC THERMAL STATUSO 4 MC_THERMAL_DEFEATUREO 50h 54h 58h 5Ch MC_THERMAL_PARAMS_AO 60h MC_THERMAL_PARAMS_BO 64h 68h 6Ch 70h 74h 78h 7Ch Datasheet 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh F4h F8h FCh 27 intel Register Description Table 2 12 Device 5 Function 0 Integrated Memory Controller Channel 1 Control Registers DID VID 00h MC CHANNEL 1 RANK TIMING A 80h PCISTS PCICMD 04h MC CHANNEL 1 RANK TIMING B 84h CCR RID 08h MC CHANNEL 1 BANK TIMING 88h HDR OCh MC_CHANNEL_1_REFRESH_TIMING 8Ch 10h MC_CHANNEL_1_CK
25. Function 0 Offset 9Ch Access as a Dword Bit Type Value Description TAOFD 26 24 RW 0 ODT turn off delay MCODT DURATION 23 2 RW E Bran 5 Controls the duration of MC ODT activation BL 2 2 MCODT DELAY 19 16 RW 4 NT Controls the delay from Rd CAS to MC ODT activation This value is tCAS 1 ODT RD DURATION 15 12 RW die 3 Controls the duration of Rd activation This value is BL 2 2 ODT RD DELAY 11 8 RW 0 Controls the delay from Rd CAS to ODT activation This value is tCAS tWL ODT WR DURATION 7 4 RW 5 m Controls the duration of Wr ODT activation value is BL 2 2 ODT WR DELAY 3 0 RW 0 a T 1 Controls the delay from Wr CAS to ODT activation This value is always 0 72 Datasheet Register Description tel 2 10 18 MC CHANNEL 0 ODT PARAMS2 MC CHANNEL 1 ODT PARAMS2 MC CHANNEL 2 ODT PARAMS2 This register contains parameters that specify Forcing ODT on Specific ranks This register is used in debug only and not during normal operation Device 4 5 6 Function Offset AOh Access as a Dword Bit Type Description 9 RW 0 MCODT_ Writes Drive MC ODT on reads and writes 8 RW 0 FORCE MCODT Force MC ODT to always be asserted 7 RW 0 FORCE ODTT7 Force ODT for Rank7 to always be asserted 6 RW 0 FORCE 6 Force ODT for Rank6 to always be asserted 5 RW 0 FORCE ODTS5 Force ODT for Rank5 to alway
26. Reset Bit Type Value Description ASSERT_CKE When set all CKE will be asserted Write a 0 to this bit to stop the init block 17 WO 0 from driving This bit has no effect once MC CONTROL INIT DONE is set This bit must be used during INITIALIZATION only and be cleared out before MC CONTROL INIT DONE is set This bit must not be asserted during initialization for 53 resume DO RCOMP 16 RW 0 When set an RCOMP will be issued to the rank specified in the RANK field DO ZQCL 15 RW 0 ZQ 1 T When set a ZQCL will be issued to the rank specified in the RANK field WRDQDQS MASK 14 RW 0 _ x When set the Write DQ DQS training will be skipped WRLEVEL_MASK 13 RW 0 DN When set the Write Levelization step will be skipped RDDQDQS MASK 12 RW 0 apas When set the Read DQ DQS step will be skipped RCVEN_ MASK 11 RW 0 _ When set the RCVEN step will be skipped RESET FIFOS 10 WO 0 When set the TX and RX FIFO pointers will be reset at the next BCLK edge The Bubble Generators will also be reset IGNORE 9 RW 0 When set the read return datapath will ignore all data coming from the RX FIFOS This is done by gating the early valid bit STOP ON FAIL 8 RW 0 When set along with the AUTORESETDIS not being set the phyinit FSM will stop if a step has not completed after timing out RANK 7 5 RW 0 The rank currently being tested The Phylnit FSM must be sequenced for every rank pre
27. initialize SMM space and then use D LCK to lock down SMM space in the future so that no application software or BIOS itself can violate the integrity of SMM space even if the program has knowledge of the D OPEN function Note that TAD does not implement this lock 11 RW Global SMRAM Enable G SMRAME If set to a 1 then Compatible SMRAM functions are enabled providing 128 KB of DRAM accessible at the A0000h address while in SMM ADSB with SMM decode To enable Extended SMRAM function this bit has to be set to 1 Once D LCK is set this bit becomes read only 10 8 RO Compatible SMM Space Base Segment C BASE SEG This field indicates the location of SMM space SMM DRAM is not remapped It is simply made visible if the conditions are right to access SMM space otherwise the access is forwarded to HI Only SMM space between A0000h and BFFFFh is supported so this field is hardwired to 010 44 Datasheet Register Description 2 6 5 2 6 6 Datasheet SAD PCIEXBAR Global register for PCIEXBAR address space Device 0 Function 1 Offset 50h Access as a Qword Bit Type aeq Description ADDRESS 39 20 RW 0 Base address of PCI EXBAR Must be naturally aligned to size low order bits are ignored SIZE Size of the PCIEXBAR address space MAX bus number 000 256 MB 001 Reserved 010 Reserved 3 1 RW 0 011 Reserved 100 Reserved 101 Res
28. signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Processor Terminology Commonly used terms are explained here for clarification DDR3 Double Data Rate 3 synchronous dynamic random access memory SDRAM is the name of the new DDR memory standard that is being developed as the successor to DDR2 SDRAM Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumption Execute Disable Bit Execute Disable allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall 11 12 Introduction security of the system See the Intel Architecture Software Developer s Manual for more detailed information Refer to http developer intel com for future reference on up to date nomenclatures Eye Definitions The eye at any point along the data channel is defined to be the creation of overlapping of a large number of Unit Interval of the data signal and timing width measured with respect to the edges of a separate clock signal at any other point Each differential signal pair
29. the channel_active being set Clocks in the channel will be disabled when this bit is set CHANNEL1 DISABLED 1 RO 0 Channel 1 is disabled This can be factory configured or if Init done is written without the channel_active being set Clocks in the channel will be disabled when this bit is set CHANNELO_ DISABLED 0 0 Channel 0 is disabled This be factory configured or if Init done is written without the channel_active being set Clocks in the channel will be disabled when this bit is set 49 m e tel Register Description 2 8 3 MC SMI SPARE DIMM ERROR STATUS SMI sparing DIMM error threshold overflow status register This bit is set when the per DIMM error counter exceeds the specified threshold The bit is reset by BIOS Device 3 Function Offset 50h Access as a Dword Bit Type ran Description 13 12 RWOC 0 REDUNDANCY LOSS_ FAI LI NG_ DI MM The ID for the failing DIMM when redundancy is lost 0 DIMM_ERROR_OVERFLOW_ STATUS This 12 bit field is the per dimm error overflow status bits The organization is as follows If there are three or more DIMMS on the channel Bit 0 DIMM 0 Channel 0 Bit 1 DIMM 1 Channel 0 Bit 2 DIMM 2 Channel 0 Bit 3 DIMM 3 Channel 0 Bit 4 DIMM 0 Channel 1 Bit 5 DIMM 1 Channel 1 Bit 6 DIMM 2 Channel 1 Bit 7 DIMM 3 Channel 1 Bit 8 DIMM 0 Channel 2 Bit 9 DIMM 1 Channel 2 Bit 10 DIMM 2 Channel 2 11 0 RWOC Bit 11 DIMM 3 Channel 2 I
30. training FSM 000 IDLE 2 0 RO 0 001 RD DQ DQS 010 RcvEn Bitlock 011 Write Level 100 WR DQ DQS Datasheet Register Description tel 2 10 5 Datasheet MC CHANNEL 0 DDR3CMD MC CHANNEL 1 DDR3CMD MC CHANNEL 2 DDR3CMD DDR3 Configuration Command This register is used to issue commands to the DIMMs such as MRS commands The register is used by setting one of the VALID bits along with the appropriate address and destination RANK The command is then issued directly to the DIMM Care must be taken in using this register as there is no enforcement of timing parameters related to the action taken by a DDR3CMD write This register has no effect after MC CONTROL INIT DONE is set Device 4 5 6 Function Offset 60h Access as a Dword Bit Type ie Description PRECHARGE VALID 28 RW 0 Indicates current command is for a precharge command ACTIVATE VALID 27 RW 0 Indicates current command is for an activate command REG_VALID 26 RW 0 Indicates current command is for a registered DIMM config write Bit is cleared by hardware on issuance This bit applies only to processors supporting registered DIMMs WR_VALID 25 RW 0 Indicates current command is for a write CAS Bit is cleared by hardware on issuance RD VALID 24 RW 0 Indicates current command is for a read CAS Bit is cleared by hardware on issuance MRS_ VALID 23 RW 0 Indicates cur
31. which processors support Intel 64 or consult with your system vendor for more information Intel Virtualization Technology requires a computer system with a processor chipset BIOS virtual machine monitor and for some uses certain platform software enabled for it Functionality performance or other benefit will vary depending on hardware and software configurations Intel Virtualization Technology enabled VMM applications are currently in development Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Enhanced Intel SpeedStep Technology See the Processor Spec Finder or contact your Intel representative for more information Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see www intel com Intel Xeon Enhanced Intel SpeedStep Technology and the Intel logo are trademarks of Intel Corporation in the United States and other countries Other brands and names are the property of their respective owners Copyright 2008 2009 Intel Corporation 2 Datashee
32. 0 RW 0 HI ENABLE OECOOOh OEFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OECOOOh to OEFFFFh 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 17 16 RW 0 PAM6_LOENABLE OE8000 OEBFFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0E8000 to OEBFFF 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 13 12 RW 0 5 0E4000h 0E7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OE4000h to OE7FFFh 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 9 8 RW 0 PAM5_LOENABLE OE0000h OE3FFFh Attribute LOENABLE This field controls the steering of read and write cycles t
33. 0h MC RIR WAY CH2 16 COh MC RIR LIMIT CH2 1 44h MC RIR WAY CH2 17 C4h MC RIR LIMIT CH2 2 48h MC RIR WAY CH2 18 C8h MC RIR LIMIT CH2 3 4Ch MC RIR WAY CH2 19 CCh MC RIR LIMIT CH2 4 50h MC RIR WAY CH2 20 DOh MC RIR LIMIT CH2 5 54h MC RIR WAY CH2 21 D4h MC_RIR_LIMIT_CH2_6 58h MC RIR WAY CH2 22 D8h MC RIR LIMIT CH2 7 5Ch MC RIR WAY CH2 23 DCh 60h MC RIR WAY CH2 24 EOh 64h MC RIR WAY CH2 25 E4h 68h MC RIR WAY CH2 26 E8h 6Ch MC RIR WAY CH2 27 ECh 70h MC RIR WAY CH2 28 FOh 74h 2 29 F4h 78h MC_RIR_WAY_CH2_ 30 F8h 7Ch MC_RIR_WAY_CH2_ 31 FCh 34 Datasheet Register Description Table 2 19 Device 6 Function 3 Integrated Memory Controller Channel 2 Thermal Control Registers DID VID 00h MC COOLING COEF2 PCISTS PCICMD 04h MC CLOSED LOOP2 CCR RID 08h MC THROTTLE OFFSET2 HDR OCh 10h 14h 18h MC_RANK_VIRTUAL_TEMP2 1Ch MC_DDR_THERM_COMMAND2 20h 24h MC_DDR_THERM_STATUS2 28h SID SVID 2Ch 30h 34h 38h 3Ch 40h 44h MC_THERMAL_CONTROL2 48h MC_THERMAL_STATUS2 4Ch MC_THERMAL_DEFEATURE2 50h 54h 58h 5Ch MC THERMAL PARAMS A2 60h MC THERMAL PARAMS B2 64h 68h 6Ch 70h 74h 78h 7Ch Datasheet 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh F4h F8h FCh 35 Note 2 5 1 2 5 2 36 Register Descriptio
34. 1 3 2 11 4 2 12 1 2 12 2 2 12 3 2 12 4 MC DOD CHO 0 MC DOD CHI 0 MC DOD CHO 1 MC DOD CHO 2 MC DOD CHI 1 MC DOD CH1 2 MC DOD CH2 0 MC DOD CH2 1 MC DOD CH2 2 MC SAG CHO O0 MC SAG CHO 3 MC SAG CHO 6 MC SAG 1 1 MC SAG CH1 4 MC SAG CHI 7 MC SAG CH2 2 MC SAG CHO 1 MC SAG CHO 4 MC SAG CHO 7 MC SAG CHI 2 MC SAG CHI 5 MC SAG CH2 0 MC SAG 2 3 MC SAG CHO 2 MC SAG 5 MC SAG 1 0 MC SAG 1 3 MC SAG 1 6 MC SAG CH2 1 MC SAG CH2 4 MC 546 CH2 5 MC LIMIT CHI 0 MC LIMIT CH1 2 MC LIMIT CHI 4 MC LIMIT 6 MC LIMIT CH2 0 MC LIMIT CH2 2 MC LIMIT CH2 4 MC LIMIT CH2 6 MC WAY CHO 0 MC RIR WAY CHO 2 MC RIR WAY CHO 4 MC RIR WAY CHO 6 MC RIR WAY CHO 8 MC RIR WAY CHO 10 MC RIR WAY CHO 12 MC RIR WAY CHO 14 MC RIR WAY CHO 16 MC RIR WAY CHO 18 MC RIR WAY CHO 20 MC RIR WAY CHO 22 MC RIR WAY 24 MC RIR WAY CHO 26 MC RIR WAY CHO 28 MC RIR WAY CHO 30 MC RIR WAY 0 MC RIR WAY CHI 2 MC RIR WAY CHI 4 MC RIR WAY 6 MC RIR WAY 8 MC RIR WAY 1 10 MC RIR WAY CH1 12 MC RIR WAY CH1 14 MC RIR WAY CHI 16 MC RIR WAY CHI 18 MC RIR WAY 1 20 MC RIR WAY 1 22 MC RIR WAY CH1 24 MC RIR WAY 1 26 MC RIR WAY 28 MC RIR WAY 30 MC RIR WAY CH2 0 MC RIR WAY CH2 2 MC RIR WAY 2 4 MC SAG CH2 6 Integrated Memory Controller Channel
35. 100 Maps to physical Channel 2 WRLCH1 Mapping of Logical Channel 1 to physical channel for Writes 8 6 RW 0 001 Maps to physical Channel 0 010 Maps to physical Channel 1 100 Maps to physical Channel 2 RDLCHO Mapping of Logical Channel 0 to physical channel for Read 5 3 RW 0 001 Maps to physical Channel 0 010 Maps to physical Channel 1 100 Maps to physical Channel 2 WRLCHO Mapping of Logical Channel 0 to physical channel for Writes 2 0 RW 0 001 Maps to physical Channel 0 010 Maps to physical Channel 1 100 Maps to physical Channel 2 52 Datasheet Register Description 2 8 7 MC_MAX_DOD This register defines the MAX number of DIMMS RANKS BANKS ROWS COLS among all DIMMS populating the three channels The Memory Init logic uses this register to cycle through all the memory addresses writing all O s to initialize all locations This register is also used for scrubbing and sparing and must always be programmed if any DODs are programmed intel Device 3 Function 0 Offset 64h Access as a Dword Reset Value Description MAXNUMCOL Maximum Number of Columns 00 2410 columns 10 9 RW 0 01 2111 columns 10 2712 columns 11 RSVD MAXNUMROW Maximum Number of Rows 000 2 12 Rows 001 2413 Rows 8 6 RW 0 010 2114 Rows 011 2415 Rows 100 2 16 Rows Others RSVD MAXNUMBANK Max Number of Banks 00 Four banked 4 RW 3 x 01 Ei
36. 2 2 13 2 14 2 15 2 16 2 17 2 18 2 19 0212 13 Functions Specifically Handled by the 17 Device 0 Function 0 Generic Non core Registers 18 Device 0 Function 1 System Address Decoder 19 Device 2 Function 0 Intel Link 0 mnn 20 Device 2 Function 1 Intel Physical 0 Registers 21 Device 3 Function 0 Integrated Memory Controller Registers 22 Device 3 Function 1 Target Address Decoder Registers 23 Device 4 Function 0 Integrated Memory Controller Channel 0 Control Registers ode II M RUM RU dM ME 24 Device 4 Function 1 Integrated Memory Controller Channel 0 Address Registers t eR Ru DEDI RU 25 Device 4 Function 2 Integrated Memory Controller Channel 0 Rank Registers ce usul M NEN EM IE a 26 Device 4 Function 3 Integrated Memory Controller Channel 0 Thermal Control Registers 27 Device 5 Function 0 Integrated Memory Controller Channel 1 Control Registers ii eee pd pe DRUNK 28 Device 5 Function 1 Integrated Me
37. 4h 98h 9Ch Access as a Dword Reset Bit Type Value Description LI MIT 19 6 RW 2 DRAM rule top limit address Must be strictly greater than previous rule even if this rule is disabled unless this rule and all following rules are disabled Lower limit is the previous rule or 0 if it is the first rule MODE DRAM rule interleave mode If a DRAM_RULE hits a 3 bit number is used to index into the corresponding interleave_list to determine which channel the DRAM belongs to This mode selects how that number is computed 2 1 RW 00 Address bits 8 7 6 01 Address bits 8 7 6 XORed with 18 17 16 10 Address bit 6 MOD3 Address 39 6 Note 6 is the high order bit 11 Reserved ENABLE Enable for DRAM rule Datasheet 57 58 intel Register Description TAD INTERLEAVE LIST O TAD INTERLEAVE LIST 1 TAD INTERLEAVE LIST 2 TAD INTERLEAVE LIST 3 TAD INTERLEAVE LIST 4 TAD INTERLEAVE LIST 5 TAD INTERLEAVE LIST 6 TAD INTERLEAVE LIST 7 TAD DRAM package assignments When the corresponding DRAM RULE hits a 3 bit number determined by mode is used to index into the Interleave List Branches to determine which channel the DRAM request belongs to Device Function 1 Offset COh C4h C8h CCh DOh D4h D8h DCh Access as a Dword Bit Type Description Logical Channel7 Index 111 of the Interleave List Bits determined from the matching
38. 5 MC SAG CH2 6 MC SAG CH2 7 Channel Segment Address Registers For each of the 8 interleave ranges they specify the offset between the System Address and the Memory Address and the System Address bits used for level 1 interleave which should not be translated to Memory Address bits Memory Address is calculated from System Address and the contents of these registers by the following algorithm m 39 16 SystemAddress 39 16 sign extend Offset 23 0 m 15 6 SystemAddress 15 6 If Removed 2 bit 8 removed If Removed 1 bit 7 removed If Removed 0 bit 6 removed MemoryAddress 36 6 m 36 6 The following table summarizes the combinations of removed bits and divide by 3 operations for the various supported interleave configurations All other combinations are not supported If any of bits 8 6 are removed the higher order bits are shifted down Removed 8 6 Divide By 3 Interleave 000 0 001 0 2 Way 011 0 4 Way 000 1 3 Way 001 1 6 Way Device 4 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a Dword Bit Type Description DIVBY3 27 RW 0 This bit indicates the rule is a 3 or 6 way interleave REMOVED 26 24 RW 0 These are the bits to be removed after offset subtraction These bits correspond to System Address 8 7 6 OFFSET 23 0 RW 0 This value should be subtracted from the current system address to create a co
39. 8 MC RIR WAY CHO 9 MC WAY CHO 10 MC RIR WAY CHO 11 MC WAY CHO 12 MC WAY CHO 13 MC WAY CHO 14 MC WAY CHO 15 MC WAY CHO 16 MC WAY CHO 17 MC WAY CHO 18 MC WAY CHO 19 MC WAY CHO 20 MC RIR WAY CHO 21 MC WAY CHO 22 MC WAY CHO 23 MC WAY CHO 24 MC WAY CHO 25 MC WAY CHO 26 MC WAY CHO 27 MC WAY CHO 28 MC WAY CHO 29 MC WAY CHO 30 MC WAY CHO 31 ntel Channel Rank Interleave Way Range Registers These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC RIR LIMIT CH registers The mappings are as follows LIMIT CH1 chanj 0 gt RIR WAY CH 1chanj 3 0 RIR LIMIT CH chanj 1 gt WAY CH 1chanj 7 6 LIMIT CH chanj 2 gt WAY 11 10 RIR LIMIT CH chanj 3 gt RIR WAY 15 14 RIR LIMIT 4 gt RIR_WAY_CH chan 19 18 LIMIT 5 gt RIR_WAY_CH chan 23 22 LIMIT CH chanj 6 gt RIR_WAY_CH chan 27 26 LIMIT CH chanj3 7 gt WAY CH chan 31 28 Device 4 Function 2 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch AOh A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh D8h EOh E8h FOh F4h Access as a Dword Reset Bit Type Value Description 0 OFFSET
40. AG CHO 6 98h 1Ch MC SAG CHO 7 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h MC DOD CHO 0 48h C8h MC DOD CHO 1 4Ch CCh MC DOD CHO 2 50h DOh 54h D4h 58h D8h 5Ch DCh 60h EOh 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh Datasheet 25 Table 2 10 Device 4 Function 2 Integrated Memory Controller Channel 0 intel Rank Registers Register Description DID VID 00h MC RIR WAY CHO 0 80h PCISTS PCICMD 04h MC RIR WAY CHO 1 84h CCR RID 08h MC RIR WAY CHO 2 88h HDR OCh MC WAY CHO 3 8Ch 10h MC RIR WAY CHO 4 90h 14h MC RIR WAY CHO 5 94h 18h MC RIR WAY CHO 6 98h 1Ch MC RIR WAY CHO 7 9Ch 20h MC RIR WAY CHO 8 24h MC RIR WAY CHO 9 A4h 28h MC RIR WAY CHO 10 A8h 51 SVID 2Ch MC RIR WAY CHO 11 ACh 30h MC RIR WAY CHO 12 BOh 34h MC RIR WAY CHO 13 B4h 38h MC RIR WAY CHO 14 B8h 3Ch MC RIR WAY CHO 15 BCh MC RIR LIMIT CHO 0 40h MC RIR WAY CHO 16 COh MC RIR LIMIT CHO 1 44h MC RIR WAY CHO 17 C4h MC RIR LIMIT CHO 2 48h MC RIR WAY CHO 18 C8h MC RIR LIMIT CHO 3 4Ch MC RIR WAY CHO 19 CCh MC RIR LIMIT CHO 4 50h MC RIR WAY CHO 20 DOh MC RIR LIMIT CHO 5 54h MC RIR WAY CHO 21 D4h MC_RIR_LIMIT_CHO_6 58h MC RIR WAY 22 D8h MC RIR LIMIT CHO 7 5Ch MC RIR WAY CHO 23 DCh 60h MC RIR WAY CHO 24 EOh 64h MC RIR WAY CHO 25
41. AY CH1 20 DOh MC LIMIT CH1 5 54h MC RIR WAY CH1 21 D4h MC_RIR_LIMIT_CH1_6 58h 1 22 D8h MC_RIR_LIMIT_CH1_7 5Ch MC_RIR_WAY_CH1_ 23 DCh 60h 1 24 EOh 64h MC RIR WAY CH1 25 E4h 68h MC RIR WAY 1 26 E8h 6Ch MC RIR WAY 1 27 ECh 70h MC RIR WAY 1 28 FOh 74h MC RIR WAY 1 29 F4h 78h MC RIR WAY 1 30 F8h 7Ch MC RIR WAY 1 31 FCh 30 Datasheet Register Description Table 2 15 Device 5 Function 3 Integrated Memory Controller Channel 1 Thermal Control Registers DID VID 00h MC_COOLING_COEF1 PCISTS PCICMD 04h MC_CLOSED_LOOP1 CCR RID 08h MC THROTTLE OFFSET1 HDR OCh 10h 14h 18h MC_RANK_VIRTUAL_TEMP1 1Ch MC_DDR_THERM_COMMAND1 20h 24h MC_DDR_THERM_STATUS1 28h SID SVID 2Ch 30h 34h 38h 3Ch 40h 44h MC_THERMAL_CONTROL1 48h MC_THERMAL_STATUS1 4Ch MC_THERMAL_DEFEATURE1 50h 54h 58h 5Ch MC THERMAL PARAMS A1 60h MC THERMAL PARAMS B1 64h 68h 6Ch 70h 74h 78h 7Ch Datasheet 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh F4h F8h FCh 31 intel Register Description Table 2 16 Device 6 Function 0 Integrated Memory Controller Channel 2 Control Registers
42. CONTROL This register is the Primary control register Device 3 Function Offset 48h Access as a Dword Reset Value Description Bit Type CHANNEL2 ACTIVE 10 RW 0 When set indicates MC channel 2 is active This bit is controlled set reset by software only This bit is required to be set for any active channel when INIT DONE is set by software CHANNEL1 ACTIVE When set indicates MC channel 1 is active This bit is controlled set reset 9 RW 0 by software only This bit is required to be set for any active channel when INIT DONE is set by software Channel 0 AND Channel 1 active must both be Set for a lockstep or mirrored pair 47 48 Register Description Device 3 Function 0 Offset Access as a Dword 48h CHANNELO ACTIVE When set indicate MC channel 0 is active This bit is controlled set reset by 8 RW software only This bit is required to be set for any active channel when INIT DONE is set by software Channel 0 AND Channel 1 active must both be set for a lockstep or mirrored pair INIT DONE MC initialize complete signal Setting this bit will exit the training mode of the 7 WO Integrated Memory Controller and begin normal operation including all enabled maintenance operations Any CHANNNEL ACTIVE bits not set when writing a 1 to INIT DONE will cause the corresponding channel to be disabled DI VBY3EN 6 RW Divide By 3 enab
43. Ch 32 Datasheet Register Description tel Table 2 17 Device 6 Function 1 Integrated Memory Controller Channel 2 Address Registers DID VID 00h MC SAG CH2 0 80h PCISTS PCI CMD 04h MC SAG CH2 1 84h CCR RID 08h MC SAG CH2 2 88h HDR OCh MC SAG CH2 3 8Ch 10h MC SAG CH2 4 90h 14h MC SAG CH2 5 94h 18h MC SAG CH2 6 98h 1Ch MC SAG CH2 7 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h MC_DOD_CH2_0 48h C8h MC_DOD_CH2_1 4Ch CCh MC_DOD_CH2_2 50h DOh 54h D4h 58h D8h 5Ch DCh 60h EOh 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh Datasheet 33 Table 2 18 Device 6 Function 2 Integrated Memory Controller Channel 2 intel Rank Registers Register Description DID VID 00h MC RIR WAY CH2 0 80h PCISTS PCICMD 04h MC RIR WAY CH2 1 84h CCR RID 08h MC RIR WAY CH2 2 88h HDR OCh MC_RIR_WAY_CH2_3 8Ch 10h MC_RIR_WAY_CH2_4 90h 14h MC_RIR_WAY_CH2_5 94h 18h MC_RIR_WAY_CH2_6 98h 1Ch MC_RIR_WAY_CH2_7 9Ch 20h MC_RIR_WAY_CH2_8 AOh 24h MC_RIR_WAY_CH2_9 A4h 28h MC_RIR_WAY_CH2_10 A8h 51 SVID 2Ch MC_RIR_WAY_CH2_11 ACh 30h MC_RIR_WAY_CH2_12 BOh 34h MC RIR WAY 2 13 B4h 38h MC RIR WAY CH2 14 B8h 3Ch MC RIR WAY CH2 15 BCh MC RIR LIMIT CH2 0 4
44. E_TIMING 90h 14h MC_CHANNEL_1_ZQ_TIMING 94h 18h MC CHANNEL 1 RCOMP PARAMS 98h 1Ch MC_CHANNEL_1_ODT_PARAMS1 9Ch 20h MC_CHANNEL_1_ODT_PARAMS2 AOh 24h MC CHANNEL 1 ODT MATRIX RANK 0 3 RD A4h 28h MC CHANNEL 1 ODT MATRIX RANK 4 7 RD A8h SID SVID 2Ch MC CHANNEL 1 MATRIX RANK 0 3 WR ACh 30h MC CHANNEL 1 ODT MATRIX RANK 4 7 WR BOh 34h MC CHANNEL 1 WAQ PARAMS B4h 38h MC CHANNEL 1 SCHEDULER PARAMS B8h 3Ch MC CHANNEL 1 MAINTENANCE OPS BCh 40h MC CHANNEL 1 TX BG SETTINGS COh 44h C4h 48h MC CHANNEL 1 RX BGF SETTINGS C8h 4Ch MC_CHANNEL_1_EW_BGF_SETTINGS CCh MC CHANNEL 1 DIMM RESET CMD 50h MC CHANNEL 1 EW BGF OFFSET SETTINGS DOh MC CHANNEL 1 DIMM INIT CMD 54h MC CHANNEL 1 ROUND TRIP LATENCY D4h MC CHANNEL 1 DIMM INIT PARAMS 58h MC CHANNEL 1 PAGETABLE PARAMS1 D8h MC CHANNEL 1 DIMM INIT STATUS 5Ch MC CHANNEL 1 PAGETABLE PARAMS2 DCh MC CHANNEL 1 DDR3CMD 60h MC TX BG CMD DATA RATIO SETTING CH1 EOh 64h MC TX BG CMD OFFSET SETTINGS 1 E4h MC CHANNEL 1 REFRESH THROTTLE SUPPORT 68h MC TX BG DATA OFFSET SETTINGS 1 E8h 6Ch ECh MC CHANNEL 1 MRS VALUE 0 1 70h MC CHANNEL 1 ADDR MATCH FOh MC_CHANNEL_1_MRS_VALUE_2 74h F4h 78h MC_CHANNEL_1_ECC_ERROR_MASK F8h MC_CHANNEL_1_RANK_PRESENT 7Ch MC CHANNEL 1 ECC ERROR INJECT FCh 28 Datasheet Register Description tel Table 2 13 Device 5 Function 1 Integrated Memory Controller Channel 1 Address Registers D
45. ID VID 00h MC 546 1 0 80h PCISTS PCI CMD 04h MC 546 1 1 84h CCR RID 08h MC 546 1 2 88h HDR OCh MC 546 1 3 8Ch 10h MC SAG 1 4 90h 14h MC 546 1 5 94h 18h MC SAG 1 6 98h 1Ch MC 546 1 7 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h MC_DOD_CH1_0 48h C8h MC DOD CH1 1 4Ch CCh MC DOD CH1 2 50h DOh 54h D4h 58h D8h 5Ch DCh 60h EOh 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh Datasheet 29 Table 2 14 Device 5 Function 2 Integrated Memory Controller Channel 1 intel Rank Registers Register Description DID VID 00h MC WAY CH1 0 80h PCISTS PCICMD 04h MC WAY 1 1 84h CCR RID 08h MC WAY 1 2 88h HDR OCh MC_RIR_WAY_CH1_3 8Ch 10h MC_RIR_WAY_CH1_4 90h 14h MC_RIR_WAY_CH1_5 94h 18h MC_RIR_WAY_CH1_6 98h 1Ch MC_RIR_WAY_CH1_7 9Ch 20h MC RIR WAY CH1 8 24h MC RIR WAY CH1 9 A4h 28h MC RIR WAY 1 10 A8h 51 SVID 2Ch MC_RIR_WAY_CH1_11 ACh 30h MC_RIR_WAY_CH1_12 BOh 34h MC RIR WAY CH1 13 B4h 38h MC RIR WAY 1 14 B8h 3Ch MC RIR WAY CH1 15 BCh MC RIR LIMIT CH1 0 40h MC RIR WAY 1 16 COh MC RIR LIMIT CH1 1 44h MC RIR WAY CH1 17 C4h MC_RIR_LIMIT_CH1_2 48h MC_RIR_WAY_CH1_18 C8h MC RIR LIMIT CH1 3 4Ch MC_RIR_WAY_CH1_19 CCh MC_RIR_LIMIT_CH1_4 50h MC RIR W
46. L 2 DIMM INIT STATUS The initialization state is stored in this register This register is cleared on a new training command Device 4 5 6 Function Offset 5Ch Access as a Dword Bit Type Description RCOMP CMPLT 9 RO 0 When set indicates that RCOMP command has complete This bit is cleared by hardware on command issuance and set once the command is complete INIT CMPLT 8 RO 0 This bit is cleared when a new training command is issued It is set once the sequence is complete regardless of whether all steps passed or not ZQCL CMPLT 7 RO 0 When set indicates that ZQCL command has completed This bit is cleared by hardware on command issuance and set once the command is complete WR DQS PASS 6 RO 0 Set after a training command when the Write DQ DQS training step passes The bit is cleared by hardware when a new training command is sent WR LEVEL PASS 5 RO 0 Set after a training command when the write leveling training step passes The bit is cleared by hardware when a new training command is sent RD RCVEN PASS 4 RO 0 Set after a training command when the Read Receive Enable training step passes The bit is cleared by hardware when a new training command is sent RD DQ DQS PASS 3 RO 0 Set after a training command when the Read DQ DQS training step passes The bit is cleared by hardware when a new training command is sent PHYFSMSTATE The current state of the top level
47. LIMIT in the MC RIR LIMIT CH registers The mappings are as follows RIR_LIMIT_CH chan 0 gt RIR_WAY_CH chan 3 0 RIR_LIMIT_CH chan 1 gt RIR_WAY_CH chan 7 6 RIR_LIMIT_CH chan 2 gt RIR_WAY_CH chan 11 10 RIR_LIMIT_CH chan 3 gt RIR_WAY_CH chan 15 14 RIR_LIMIT_CH chan 4 gt RIR_WAY_CH chan 19 18 RIR_LIMIT_CH chan 5 gt RIR_WAY_CH chan 23 22 RIR_LIMIT_CH chan 6 gt RIR_WAY_CH chan 27 26 RIR_LIMIT_CH chan 7 gt RIR_WAY_CH chan 31 28 Device 5 Function 2 CCh DOh D4h D8h EOh E8h ECh FOh F4h F8h FCh Access as a Dword Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch AOh A4h A8h ACh BOh B4h B8h BCh COh complement value Bit Type Description OFFSET 13 4 RW 0 This field defines the offset used in the rank interleave This is a 2 s RANK 1 0 are the rank within that DIMM This field defines which rank participates in WAY n If MC CLOSEDPAGE 1 this field defines the DRAM rank selected when MemoryAddress 7 6 n If 3 0 RW 0 MC CLOSEDPAGE 0 this field defines which rank is selected when MemoryAddress 13 12 n n is the instantiation of the register This field is organized by physical rank Bits 3 2 are the encoded DIMM ID slot Bits Datasheet Register Description 2 12 4 Datasheet MC_RIR_WAY_CH2_0 MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_ 2 MC_RIR_WAY_CH2_ 3 2 4 MC_
48. Link Registers QPI QPILCL LO QPILCL L1 This register provides Intel QPI Link Control Device 2 Function 0 4 Offset 48h Access as a Dword Reset Value Description Bit Type L1 MASTER Indicates that this end of the link is the L1 master This link transmitter bit is an L1 power state master and can initiate an L1 power state transition If this bit is 21 RW 0 not set then the link transmitter is L1 power state slave and should respond to L1 transitions with an ACK or NACK If the link power state of L1 is enabled then there is one master and one slave per link The master may only issue single L1 requests while the slave can only issue single L1 Ack or L1 NAck responses for the corresponding request L1 ENABLE Enables L1 mode at the transmitter This bit should be ANDed with the receive 20 RW 0 L1 capability bit received during parameter exchange to determine if a transmitter is allowed to enter into L1 This is NOT a bit that determines the capability of a device LOS ENABLE Enables 105 mode at the transmitter This bit should be ANDed with the receive 18 RW 0 105 capability bit received during parameter exchange to determine if a transmitter is allowed to enter into LOs This is NOT a bit that determines the capability of a device I ntegrated Memory Controller Control Registers The registers in this section apply only to processors supporting registered DI MMs MC
49. M3 LOENABLE 0D0000h 0D3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to OD3FFFh 25 24 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM PAM2 HI ENABLE 0CCOO0h OCFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OCCOOOh to OCFFFFh 21 20 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation reads and writes are serviced by DRAM PAM2 LOENABLE 0C8000h OCBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to OCBFFFh 17 16 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM PAM1_HIENABLE 0C4000h 0C7FFFh Attribute HIENABLE This field controls the steering of read and write cycles that address the BIO
50. RIR_WAY_CH2_5 MC RIR WAY 2 6 MC RIR WAY CH2 7 MC WAY CH2 8 MC RIR WAY 2 9 MC RIR WAY 2 10 MC RIR WAY CH2 11 MC RIR WAY 2 12 MC WAY CH2 13 MC RIR WAY 2 14 MC WAY CH2 15 MC RIR WAY 2 16 MC WAY CH2 17 MC RIR WAY 2 18 MC WAY 2 19 MC RIR WAY 2 20 MC WAY CH2 21 MC RIR WAY CH2 22 MC WAY CH2 23 MC RIR WAY CH2 24 MC WAY 2 25 MC RIR WAY CH2 26 MC WAY CH2 27 MC RIR WAY CH2 28 MC WAY CH2 29 MC WAY CH2 30 MC WAY CH2 31 ntel Channel Rank Interleave Way Range Registers These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC RIR LIMIT CH registers The mappings are as follows LIMIT CH1 chanj 0 gt RIR WAY CH 1chanj 3 0 RIR LIMIT CH chanj 1 gt WAY CH 1chanj 7 6 LIMIT CH chanj 2 gt WAY 11 10 RIR LIMIT CH chanj 3 gt RIR WAY 15 14 RIR LIMIT 4 gt RIR_WAY_CH chan 19 18 LIMIT 5 gt RIR_WAY_CH chan 23 22 LIMIT CH chanj 6 gt RIR_WAY_CH chan 27 26 LIMIT CH chanj3 7 gt RIR_WAY_CH chan 31 28 Device 6 Function 2 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch AOh A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh D4h D8h EOh E8h FOh F4h F8h Access as a Dwor
51. Rank Registers MC RIR LIMIT CHO 0 MC RIR LIMIT CHO 2 MC RIR LIMIT CHO 4 MC RIR LIMIT CHO 6 MC RIR LIMIT CHO 1 MC RIR LIMIT CHO 3 MC RIR LIMIT CHO 5 MC RIR LIMIT CHO 7 MC RIR LIMIT CH1 1 MC RIR LIMIT CH1 3 MC RIR LIMIT CH1 5 MC RIR LIMIT CH1 7 MC RIR LIMIT CH2 1 MC RIR LIMIT CH2 3 MC RIR LIMIT CH2 5 MC RIR LIMIT CH2 7 MC RIR WAY CHO 1 MC RIR WAY CHO 3 MC RIR WAY 5 MC RIR WAY CHO 7 MC RIR WAY CHO 9 MC WAY 11 MC RIR WAY CHO 13 MC RIR WAY CHO 15 MC WAY 17 MC RIR WAY 19 MC RIR WAY CHO 21 MC RIR WAY CHO 23 MC RIR WAY CHO 25 MC RIR WAY 27 MC RIR WAY CHO 29 MC RIR WAY CHO 31 MC RIR WAY 1 1 MC RIR WAY 1 3 MC RIR WAY 1 5 MC RIR WAY 1 7 MC RIR WAY 1 9 MC WAY 11 MC RIR WAY 1 13 MC RIR WAY 1 15 MC RIR WAY 1 17 MC RIR WAY CH1 19 MC RIR WAY 1 21 MC RIR WAY 1 23 MC RIR WAY 1 25 MC RIR WAY CH1 27 MC RIR WAY 1 29 MC RIR WAY CH1 31 MC RIR WAY CH2 1 MC RIR WAY CH2 3 MC RIR WAY CH2 5 MC SAG CH2 7 Datasheet 2 13 1 2 13 2 2 13 3 2 13 4 2 13 5 2 13 6 2 13 7 2 13 8 2 13 9 MC_RIR_WAY_CH2_6 MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8 MC_RIR_WAY_CH2_9 MC RIR WAY 2 10 MC RIR WAY CH2 12 MC RIR WAY CH2 14 MC RIR WAY CH2 16 MC RIR WAY CH2 18 MC WAY CH2 20 MC RIR WAY CH2 22 MC RIR WAY CH2 24 MC RIR WAY CH2 26 MC RIR WAY CH2 28 MC RIR WAY 2 30 2 13 Memory Thermal C
52. S area from 0C4000h to OC7FFFh 13 12 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation reads and writes are serviced by DRAM 1 LOENABLE 0C0000h OC3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C0000h to OC3FFFh 9 8 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation reads and writes are serviced by DRAM PAMO HI ENABLE OFOOOOh OFFFFFh Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from OFOOOOh to OFFFFFh 5 4 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM Datasheet Register Description 2 6 2 SAD_PAM456 Register for legacy device 0 function 0 94h 97h address space Device 0 Function 1 Offset 44h Access as a Dword Bit Type dure Description 21 2
53. TINGS MC CHANNEL 1 TX BG SETTINGS MC CHANNEL 2 TX BG SETTINGS These are the parameters used to set the Start Scheduler for TX clock crossing This is used to send commands to the DIMMs The NATIVE RATIO is UCLK multiplier of BCLK U ALIEN RATION is DCLK multiplier of BCLK D PIPE DEPTH 8 UCLK design dependent variable MIN SEP DELAY 670ps design dependent variable Internally this is logic delay of FIFO clock skew between U and D TOTAL EFFECTIVE DELAY PIPE DEPTH UCLK PERIOD in ps MIN SEP DELAY DELAY FRACTION TOTAL EFFECTIVE DELAY D UCLK PERIOD in ps G C D U D Determine OFFSET MULTIPLE using the equation FLOOR OFFSET MULTIPLE 1 G C D U D gt DELAY FRACTION OFFSET VALUE MOD OFFSET MULTIPLE U lt Final answer for OFFSET MULTIPLE Device 4 5 6 Function Offset COh Access as a Dword Bit Type ings Description 23 16 RW 2 OFFSET TX offset setting 15 8 RW 1 ALI ENRATI O ratio to BCLK TX Alien Ratio setting 7 0 RW 4 NATIVERATIO Uclk ratio to BCLK TX Native Ratio setting MC CHANNEL O RX BGF SETTINGS MC CHANNEL 1 RX BGF SETTINGS MC CHANNEL 2 RX BGF SETTINGS These are the parameters used to set the Rx clock crossing BGF Device 4 5 6 Function Offset C8h Access as a Dword Bit Type cn Description PTRSEP 26 24 RW 2 RX FIFO pointer separation settings THIS FIELD 15 NOT USED BY HARDWARE RX Poin
54. ULER PARAMS MC CHANNEL 2 SCHEDULER PARAMS These are the parameters used to control parameters within the scheduler Device 4 5 6 Function Offset B8h Access as a Dword Reset Bit Type Value Description CS FOR CKE TRANSITI ON 12 RW 1 Specifies if chip select is to be asserted when CKE transitions with PowerDown entry exit and SelfRefresh exit FLOAT EN 11 RW 0 When set the address and command lines will float to save power when commands are not being sent out This setting may not work with RDIMMs PRECASRDTHRESHOLD 10 6 RW 7 Threshold above which Medium Low Priority reads can PRE CAS write requests 5 RW 0 DISABLE_ISOC_RBC_RESERVE When set this bit will prevent any RBC s from being reserved for ISOC 3 RW 0 ENABLE2N Enable 2n Timing PRI ORI TYCOUNTER 2 0 RW 0 Upper 3 MSB of 8 bit priority time out counter 2 10 25 MC CHANNEL 0 MAINTENANCE OPS MC CHANNEL 1 MAINTENANCE OPS MC CHANNEL 2 MAINTENANCE OPS This register enables various maintenance operations such as Refreshes ZQ RCOMP etc Device 4 5 6 Function Offset BCh Access as a Dword Reset Bit Type Value Description MAINT CNTR 12 0 RW 0 Value to be loaded in the maintenance counter This counter sequences the rate to Refreshes ZQ RCOMP 76 Datasheet Register Description tel 2 10 26 2 10 27 Datasheet MC CHANNEL 0 TX BG SET
55. _RANK_0_3_RD A4h 28h MC CHANNEL 0 ODT MATRIX RANK 4 7 RD A8h SID SVID 2Ch MC CHANNEL 0 ODT MATRIX RANK 0 3 WR ACh 30h MC CHANNEL 0 ODT MATRIX RANK 4 7 WR BOh 34h MC CHANNEL 0 WAQ PARAMS B4h 38h MC CHANNEL 0 SCHEDULER PARAMS B8h 3Ch MC CHANNEL 0 MAINTENANCE OPS BCh 40h MC CHANNEL 0 TX BG SETTINGS COh 44h C4h 48h MC CHANNEL 0 RX BGF SETTINGS C8h 4Ch MC CHANNEL 0 EW BGF SETTINGS CCh MC CHANNEL 0 DIMM RESET CMD 50h MC CHANNEL 0 EW BGF OFFSET SETTINGS DOh MC CHANNEL 0 DIMM INIT CMD 54h MC CHANNEL 0 ROUND TRIP LATENCY D4h MC CHANNEL 0 DIMM INIT 5 58h MC CHANNEL 0 PAGETABLE PARAMS1 D8h MC CHANNEL 0 DIMM INIT STATUS 5Ch MC CHANNEL 0 PAGETABLE PARAMS2 DCh MC CHANNEL 0 DDR3CMD 60h MC TX BG CMD DATA RATIO SETTING CHO EOh 64h MC TX BG CMD OFFSET SETTINGS CHO E4h MC CHANNEL 0 REFRESH THROTTLE SUPPORT 68h MC TX BG DATA OFFSET SETTINGS CHO E8h 6Ch ECh MC CHANNEL 0 MRS VALUE 0 1 70h MC CHANNEL 0 ADDR MATCH FOh MC CHANNEL 0 MRS VALUE 2 74h F4h 78h MC CHANNEL 0 ECC ERROR MASK F8h MC CHANNEL 0 RANK PRESENT 7Ch MC CHANNEL 0 ECC ERROR INJECT FCh 24 Datasheet Register Description tel Table 2 9 Device 4 Function 1 Integrated Memory Controller Channel 0 Address Registers DID VID 00h MC 546 CHO 0 80h PCISTS PCI CMD 04h MC SAG CHO 1 84h CCR RID 08h MC 546 2 88h HDR OCh MC SAG CHO 3 8Ch 10h MC SAG CHO 4 90h 14h MC 546 5 94h 18h MC S
56. a Dword Bit Type uem Description ECCMASK 31 0 RW 0 This field contains the 32 bits of MC ECC mask bit for half cacheline MC CHANNEL O ECC ERROR INJECT MC CHANNEL 1 ECC ERROR INJECT MC CHANNEL 2 ECC ERROR INJECT This register contains the control bits for the actual ECC error injection This register needs to be written after writing into MC CHANNEL X ECC ERROR MASK The INJECT ECC bit must be set to enable error injection Otherwise no error injection will take place even if the criteria programmed in the MC CHANNEL X ADDR MATCH register is met Device 4 5 6 Function Offset FCh Access as a Dword Reset Value Description Bit Type INJECT ADDR PARITY 4 RW 0 1 Forces Address Parity error injection Bit will reset after the first injection unless REPEAT EN is set INJECT ECC 3 RW 0 1 Forces ECC error injection Bit will reset after the first injection unless REPEAT EN is set MASK HALF CACHELI NE 11 Inject the ECC code word for full cacheline 2 1 RW 0 10 Inject the ECC code word for upper 32B half cacheline 01 Inject the ECC code word for lower 32B half cacheline 00 No masking will be applied REPEAT_EN 1 ECC errors will be injected on the channel until the bit is cleared Datasheet e Register Description n tel 2 10 39 Note Datasheet Error Injection Implementation The usage model is to program th
57. ally connect to PCI bus X These bits are set to 00 fast decode so that optimum DEVSEL timing for PCI bus X is not limited by this device Master Data Parity Error Detected 8 RO 0 PERR signaling and messaging are not implemented by this bridge therefore this bit is hardwired to O Fast Back to Back FB2B 7 RO 1 This bit is hardwired to 1 This device is not physically connected to a PCI bus This bit is set to 1 indicating back to back capabilities so that the optimum setting for this PCI bus is not limited by this device 6 RO 0 Reserved 66 MHz Capable 5 RO 0 Does not apply to PCI Express Hardwired to 0 Datasheet Register Description Device 0 Function 0 1 Offset 06 Device 2 Function 0 1 4 5 Offset 06 Device 3 Function 0 2 4 Offset 06h Device 4 6 Function 0 3 Offset 06 Reset Value Description Capability List CLI ST This bit is hardwired to 1 to indicate to the configuration software that this device function implements a list of new capabilities A list of new capabilities is accessed via registers CAPPTR at the configuration address offset 34h from the 4 RO TBD start of the PCI configuration space header of this function Register CAPPTR contains the offset pointing to the start address with configuration space of this device where the capability register resides This bit must be set for Express device or if the VSEC capabili
58. and previous rule is 0 RW 0 Directed to HOME channel unless overridden by other dedicated address range registers If disabled all accesses in this range are directed in MMIO to the SAD INTERLEAVE LIST O SAD INTERLEAVE LIST 1 SAD INTERLEAVE LIST 2 SAD INTERLEAVE LIST 3 SAD INTERLEAVE LIST 4 SAD INTERLEAVE LIST 5 SAD INTERLEAVE LIST 6 SAD INTERLEAVE LIST 7 This register provides SAD DRAM package assignments When the corresponding DRAM RULE hits a 3 bit number determined by mode is used to index into the interleave list to determine which package is the HOME for this address 00 01 Socket 0 10 Socket 1 11 Reserved Device Function 1 Offset C4h C8h CCh DOh D4h DCh Access as a Dword Reset idu Bit Type Value Description 29 28 RW PACKAGE7 Package for index value 7 of interleaves 25 24 RW PACKAGEG6 Package for index value 6 of interleaves 21 20 RW PACKAGES Package for index value 5 of interleaves 17 16 RW PACKAGE4 Package for index value 4 of interleaves 13 12 RW PACKAGE3 Package for index value 3 of interleaves 9 8 RW PACKAGE2 Package for index value 2 of interleaves 5 4 RW PACKAGE1 Package for index value 1 of interleaves 1 0 RW PACKAGEO Package for index value 0 of interleaves Datasheet Register Description tel 2 7 2 7 1 2 8 2 8 1 Datasheet Intel
59. are must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note that software does not need to perform a read merge write operation for the Configuration Address CONFIG_ADDRESS register Registers registers can be 8 16 or 32 bits in size Writes to Reserved registers have no effect on In addition to reserved bits within a register the processor contains address locations in the configuration space that are marked either Reserved or Intel Reserved The processor responds to accesses to Reserved address locations by completing the host Reserved cycle When a Reserved register location is read a zero value is returned Reserved the processor Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads to Intel Reserved registers may return a non zero value Default Value upon a Reset Upon a reset the processor sets all of its internal configuration registers to predetermined default states Some register values at reset are determined by external strapping options The default state represents the minimum funct
60. bit is a global enable bit for this devices SERR messaging This host bridge 8 RO 0 will not implement SERR messaging This bit is hardwired to 0 If SERR is used for error generation then this bit must be RW and enable disable SERR signaling 7 RO 0 IDSELWCC I DSEL Stepping Wait Cycle Control Per PCI 2 3 specification this bit is hardwired to 0 6 RO 0 PERRE Parity Error Response Enable Parity error is not implemented in this host bridge This bit is hardwired to O 5 RO 0 VGAPSE VGA palette snoop Enable This host bridge does not implement this bit This bit is hardwired to 0 MWIEN Memory Write and I nvalidate Enable 4 RO 0 This host bridge will never issue memory write and invalidate commands This bit is therefore hardwired to 0 3 RO 0 SCE Special Cycle Enable This host bridge does not implement this bit This bit is hardwired to a 0 2 RO 1 BME Bus Master Enable This host bridge is always enabled as a master This bit is hardwired to a 1 MSE Memory Space Enable 1 RO 1 This host bridge always allows access to main memory This bit is not implemented and is hardwired to 1 0 RO 0 1 Access Enable This bit is not implemented in this host bridge and is hardwired to 0 39 intel 2 5 8 Register Description PCI STS PCI Status Register The PCI Status register is a 16 bit status register that reports the occurrence of various error events on this device s PCI interface 40
61. by combining the D and D signals produces a signal eye 1366 land LGA package The processor is available in a Flip Chip Land Grid Array FC LGA package consisting of the processor die mounted on a land grid array substrate with an integrated heat spreader IHS Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Integrated Memory Controller IMC A memory controller that is integrated in the processor silicon Integrated Heat Spreader 1 5 A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Intel 64 Architecture An enhancement to Intel s 32 architecture allowing the processor to execute operating systems and applications written to take advantage of Intel 64 Further details on Intel 64 architecture and programming model can be found at http developer intel com technology intel64 Intel QuickPath I nterconnect A cache coherent link based interconnect specification for Intel processor chipset 1 0 bridge components Sometimes abbreviated as Intel Intel Abbreviation for Intel QuickPath Interconnect Intel Virtualization Technology Intel VT A set of hardware enhancements to Intel server and client platforms tha
62. cles in increments of 32 This is the minimum delay between ZQCL and any other command This register should be programmed to at least 512 32 16 10000 to conform to the DDR3 specification 71 m e tel Register Description 2 10 16 MC CHANNEL 0 RCOMP PARAMS MC CHANNEL 1 RCOMP PARAMS MC CHANNEL 2 RCOMP PARAMS This register contains parameters that specify Rcomp timings Device 4 5 6 Function Offset 98h Access as a Dword Bit Type cen Description RCOMP EN 16 RW 1 Enable Rcomp When set the Integrated Memory Controller will do the programmed blocking of requests and send indications RCOMP_CMD_DCLK 15 10 RW 2 Delay from the start of an RCOMP command blocking period in which the command rcomp update is done Program this field to 15 for all configurations RCOMP_ LENGTH 9 4 RW 9 Number of Dclks during which all commands are blocked for an RCOMP update Data RCOMP update is done on the last DCLK of this period Program this field to 31 for all configurations RCOMP_INTERVAL 3 0 RW 0 Duration of interval between Rcomp in increments of tRefl Register value is tRefl 1 For example a setting of 0 will produce an interval of tRefl 2 10 17 MC_CHANNEL_0O_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS1 This register contains parameters that specify ODT timings All values are in DCLK Device 4 5 6
63. contains the rank registers for Integrated Memory Controller Channel 1 and resides at DID of 2C2Ah Device 5 Function 3 contains the thermal control registers for Integrated Memory Controller Channel 1 and resides at DID of 2C2Bh Device 6 Integrated Memory Controller Channel 2 Device 6 Function 0 contains the control registers for Integrated Memory Controller Channel 2 and resides at DID of 2C30h Device 6 Function 1 contains the address registers for Integrated Memory Controller Channel 2 and resides at DID of 2C31h Device 6 Function 2 contains the rank registers for Integrated Memory Controller Channel 2 and resides at DID of 2C32h Device 6 Function 3 contains the thermal control registers for Integrated Memory Controller Channel 2 and resides at DID of 2C33h Device Mapping Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number Device Number and Function Number Device configuration is based on the PCI Type 0 configuration conventions All processor registers appear on the PCI bus assigned for the processor socket Bus number is derived by the max bus range setting and processor socket number Functions Specifically Handled by the Processor Component Register Group DID Device Function Intel QuickPath Architecture Generic Non core Registers 2C41h 0 Intel Qu
64. d Reset Bit Type Value Description OFFSET 13 4 RW 0 This field defines the offset used in the rank interleave This is a 2 s complement value RANK This field defines which rank participates in WAY n If MC CLOSEDPAGE 1 this field defines the DRAM rank selected when MemoryAddress 7 6 n If 3 0 RW 0 MC CLOSEDPAGE 0 this field defines which rank is selected when 1 0 are the rank within that DIMM MemoryAddress 13 12 n n is the instantiation of the register This field is organized by physical rank Bits 3 2 are the encoded DIMM ID slot Bits 91 m e tel Register Description 2 13 Memory Thermal Control 2 13 1 MC THERMAL CONTROLO MC THERMAL CONTROLI MC THERMAL CONTROL2 Controls for the Integrated Memory Controller thermal throttle logic for each channel Device 4 5 6 Function 3 Offset 48h Access as a Dword Bit Type Vae Description APPLY SAFE 2 RW 1 Enable the application of safe values while MC_THERMAL_PARAMS_B SAFE_INTERVAL is exceeded THROTTLE MODE 5 elects throttling mode 00 Throttle disabled 01 Open Loop Throttle when Virtual Temperature is greater than 1 0 RW 0 MC OFFSET 10 Closed Loop Throttle when MC_CLOSED_LOOP THROTTLE_NOW is set 11 Closed Loop Throttle when MC_DDR_THERM_COMMAND THROTTLE is set and the MC DDR THERM pin is asserted OR OLTT will be implemented Condition 1 II
65. e done This bit should be set if the RDIMM supports auto MRS cycles where the dimm takes care of disabling address inversion for MRS writes THREE DIMMS PRESENT 24 RW 0 Set when channel contains three DIMMs THREE DIMMS PRESENT 1 and QUAD RANK PRESENT 1 or SINGLE QUAD RANK PRESENT 1 are mutually exclusive SINGLE QUAD RANK PRESENT 23 RW 0 Q N j Set when channel contains a single quad rank DIMM UAD_RANK_PRESENT 22 RW 0 S Set when channel contains 1 2 quad rank DIMMs WRDQDQS DELAY 21 17 RW 15 9095 Specifies the delay in DCLKs between reads and writes for WRDQDQS training WRLEVEL_DELAY Specifies the delay used between write CAS indications for write leveling 16 RW 0 training 0 16 DCLKs 1 32 DCLKs REGISTERED_ DIMM 15 RW 0 Set when channel contains registered DIMMs PHY_FSM_DELAY 14 10 RW 0 Global timer used for bounding the physical layer training If the timer expires the FSM will go to the next step and the counter will be reloaded with PHY_FSM_DELAY value Units are 2 n dclk BLOCK CKE DELAY 9 5 RW 0 Delay in ns from when clocks and command are valid to the point CKE is allowed to be asserted Units are in 2 n uclk RESET ON TIME 4 RW 0 i Reset will be asserted for the time specified Units are 2 n Uclk 61 intel 2 10 4 62 Register Description MC CHANNEL 0 DIMM INIT STATUS MC CHANNEL 1 DIMM INIT STATUS MC CHANNE
66. e Cycle 7 0 RW 0 MC COOLING COEFO MC COOLING 1 MC COOLING COEF2 Heat removed from DRAM 8 DCLKs This should be scaled relative to the per command weights and the initial value of the throttling threshold This includes idle command and refresh energies If 2X refresh is supported the worst case of 2X refresh must be assumed When there are more than 4 ranks attached to the channel the thermal throttle logic is shared Device 4 5 6 Function 3 Offset 80h Access as a Dword Bit Type rae Description 31 24 RW 255 RANK3 Rank 3 Cooling Coefficient 23 16 RW 255 RANK2 Rank 2 Cooling Coefficient 15 8 RW 255 RANK1 Rank 1 Cooling Coefficient 7 0 RW 255 RANKO Rank 0 Cooling Coefficient Datasheet Register Description tel 2 13 7 2 13 8 Datasheet MC_CLOSED_LOOPO MC_CLOSED_LOOP1 MC CLOSED LOOP2 This register controls the closed loop thermal response of the DRAM thermal throttle logic It supports immediate thermal throttle and 2X refresh In addition the register is used to configure the throttling duty cycle Device 4 5 6 Function 3 Offset 84h Access as a Dword Reset Value Description Bit Type MIN THROTTLE DUTY CYC 17 8 RW 64 This parameter represents the minimum number of DCLKs of operation allowed after throttling In order to provide actual command opportunities the number of clocks between CKE de assertio
67. e MC_CHANNEL_X_ADDR_MATCH and MC_CHANNEL_X_ECC_ERROR_MASK registers before writing the command in MC CHANNEL X ECC ERROR INJECT register When writing the MC CHANNEL X ECC ERROR INJECT register the REPEAT EN and MASK HALF CACHELINE bits need to be set to the desired values To turn off the feature write to the MC CHANNEL X ECC ERROR INJECT register Address parity error injection and ECC error injection can be done either at the same time or independently They will both use the same MATCH settings if both are enabled Along with the INJECT ECC bit set software must generate the memory traffic that matches the address location programmed in the MC CHANNEL X ADDR MATCH register as described above in order for an error injection to take place Unless the REPEAT EN bit is set in the MC CHANNEL X ECC ERROR INJECT register the memory controller will only inject the error to the first location that matches the criteria programmed in the MC CHANNEL X ADDR MATCH register Errors are injected on writes only Reads will be required to detect the errors in the MC COR ECC CNT X registers Additionally all writes used to inject errors must be committed to memory to ensure the error is detected on subsequent reads 83 Register Description Integrated Memory Controller Channel Address Registers MC DOD CHO 0 MC 1 CHO 2 Channel 0 DIMM Organization Descriptor Register Device Offset 4 Function 1
68. e settings for channel across all three channels The register in Channel 0 must be programmed for all configurations Device 4 5 6 Function Offset E4h Access as a Dword Bit Type sa Description 9 8 RW 0 PTROFFSET FIFO pointer offset 7 0 RW 0 BGOFFSET BG offset MC_TX_BG_DATA_OFFSET_SETTINGS_CHO MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 MC TX BG DATA OFFSET SETTINGS CH2 Integrated Memory Controller Channel Bubble Generator Offsets for DATA FIFO Device 4 5 6 Function Offset E8h Access as a Dword Bit Type pawa Description 16 14 RW 0 RDPTROFFSET Read FIFO pointer offset 13 10 RW 0 WRTPTROFFSET Write pointer offset 9 8 RW 0 PTROFFSET FIFO pointer offset 7 0 RW 0 BGOFFSET BG offset Datasheet Register Description tel 2 10 36 Datasheet MC_CHANNEL_0_ADDR_MATCH MC CHANNEL 1 ADDR MATCH MC CHANNEL 2 ADDR MATCH This register specifies the intended address or address range where ECC errors will be injected It can be set to match memory address on a per channel basis The address fields can be masked in the Mask bits Any mask bits set to 1 will always match To match all addresses all of the mask bits can be set to 1 The MC CHANNEL X ECC ERROR INJECT register can be used to set the trigger for the error injection Device 4 5 6 Function Offset FOh Access as a Qword Reset
69. entification Number The default value specifies Intel 31 16 RWO 8086h Vendor Identification Number The default value specifies Intel 15 0 RWO 8086h 38 Datasheet Register Description 2 5 7 Datasheet intel PCI CMD Command Register This register defines the PCI 3 0 compatible command register values applicable to PCI Express space Device 0 Function 0 1 Offset 04h Device 2 Function 0 1 4 5 Offset 04h Device 3 Function 0 2 4 Offset 04h Device 4 6 Function 0 3 Offset 04h x Reset NS Bit Type Value Description 15 11 RV 0 Reserved by PCI SIG INTxDisable I nterrupt Disable Controls the ability of the PCI Express port to generate INTx messages If this device does not generate interrupts then this bit is not implemented and is RO 10 RO 0 If this device generates interrupts then this bit is RW and this bit disables the device function from asserting INTx A value of 0 enables the assertion of its INTx signal A value of 1 disables the assertion of its INTx signal 1 Legacy Interrupt mode is disabled 0 Legacy Interrupt mode is enabled FB2B Fast Back to Back Enable 9 RO 0 This bit controls whether or not the master can do fast back to back writes Since this device is strictly a target this bit is not implemented This bit is hardwired to Writes to this bit position have no effect SERRE SERR Message Enable This
70. er this number of DCLKs if no request to the rank is in the MC tXP 23 21 RW 0 Minimum delay from exit power down with DLL and any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Slow exit precharge powerdown is not supported tXSDLL 20 11 RW 0 Minimum delay between the exit of self refresh and commands that require a locked DLL tXS 10 3 RW 0 Minimum delay between the exit of self refresh and commands not requiring a DLL tCKE 2 RW 9 o CKE minimum pulse width MC CHANNEL 0 20 TIMING MC CHANNEL 1 ZQ TIMING MC CHANNEL 2 ZQ TIMING This register contains parameters that specify timing All units are DCLK unless otherwise specified The register encodings are specified where applicable Device 4 5 6 Function Offset 94h Access as a Dword Bit Type Description 30 RW 1 Parallel ZQ Enable ZQ calibration to different ranks in parallel tZQenable 29 RW 1 9 Enable the issuing of periodic ZQCS calibration commands ZQ Interval 28 RW 1641 ds 6410 Nominal interval between periodic calibration in increments of tREFI tZQCS 7 5 RW 4 This field specifies ZQCS cycles in increments of 16 This is the minimum delay between ZQCS and any other command This register should be programmed to at least 64 16 4 100 to conform to the DDR3 specification tZQI nit 4 0 RW 0 This field specifies ZQInit cy
71. erved 110 64 MB 111 128 MB ENABLE 0 RW 0 Enable for PCIEXBAR address space Editing size should not be done without also enabling range SAD DRAM RULE 0 SAD DRAM RULE 1 SAD DRAM RULE 2 SAD DRAM RULE 3 SAD DRAM RULE 4 SAD DRAM RULE 5 SAD DRAM RULE 6 SAD DRAM RULE 7 This register provides SAD DRAM rules Address Map for package determination Device 0 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a Dword Reset Bit Type Value Description 45 2 6 7 46 tel Register Description Device 0 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a Dword LIMIT DRAM rule top limit address Must be strictly greater than previous rule even if 19 6 RW this rule is disabled unless this rule and all following rules are disabled Lower limit is the previous rule or 0 if it is first rule This field is compared against MA 39 26 the memory address map MODE DRAM rule interleave mode If a DRAM RULE hits a 3 bit number is used to index into the corresponding interleave list to determine which package the DRAM belongs to This mode selects how that number is computed 2 1 RW 00 Address bits 8 7 6 01 Address bits 8 7 6 XORed with 18 17 16 10 Address bit 6 MOD3 Address 39 6 Note 6 is the high order bit 11 Reserved ENABLE Enable for DRAM rule If Enabled Range between this rule
72. es Should be set to tRFC in DCLKS Zero is an invalid encoding A value of 1 should be programmed to disable the throttling of opportunistic refreshes By setting this field to tRFC current to a single DI MM can be limited to that required to support this scenario without 29 19 RW 0 significant performance impact 8 panic refreshes in tREFI to one rank 1 opportunistic refresh every tRFC to another rank full bandwidth delivered by the third and fourth ranks Platforms that can supply peak currents to the DI MMs should disable opportunistic refresh throttling for max performance tREFI 8 Average periodic refresh interval divided by 8 tRFC Delay between the refresh command and an activate or refresh command 18 9 RW 0 8 0 RW 0 70 Datasheet Register Description tel 2 10 14 MC CHANNEL O TIMING 2 10 15 Datasheet MC CHANNEL 1 CKE TIMING MC CHANNEL 2 CKE TIMING This register contains parameters that specify the timings All units are in DCLK Device 4 5 6 Function Offset 90h Access as a Dword Reset Bit Type Value Description tRANKI DLE Rank will go into powerdown after it has been idle for the specified number of 31 24 RW 0 dclks tRANKI DLE covers max txxxPDEN Minimum value is tWRAPDEN If CKE is being shared between ranks then both ranks must be idle for this amount of time A Power Down Entry command will be requested for a rank aft
73. es to the same rank 0 24 1 6 8 6 RW tRRD Specifies the minimum time between activate commands to the same rank 5 0 RW tFAW Four Activate Window Specifies the time window in which four activates are allowed the same rank Datasheet 69 m e n tel Register Description 2 10 12 MC CHANNEL 0 BANK TIMI NG MC CHANNEL 1 BANK TIMING MC CHANNEL 2 BANK TIMING This register contains parameters that specify the bank timing parameters These values are in DCLK The values in these registers are encoded where noted All of these values apply to commands to the same rank only Device 4 5 6 Function Offset 88h Access as a Dword Reset Bit Type Value Description 21 17 RW 0 tWTPr Minimum Write CAS to Precharge command delay 16 13 RW 0 tRTPr Minimum Read CAS to Precharge command delay 12 9 RW 0 tRCD Minimum delay between Activate and CAS commands 8 4 RW 0 tRAS Minimum delay between Activate and Precharge commands 3 0 RW 0 tRP Minimum delay between Precharge command and Activate command 2 10 13 MC_CHANNEL_O_REFRESH_TIMING MC CHANNEL 1 REFRESH TIMING MC CHANNEL 2 REFRESH TIMING This register contains parameters that specify the refresh timings Units are in DCLK Device 4 5 6 Function Offset 8Ch Access as a Dword Reset Bit Type Value Description tTHROT OPPREF The minimum time between two opportunistic refresh
74. f there are one or two DIMMS on the channel Bit 0 DIMM Ranks 0 and 1 Channel 0 Bit 1 DIMM Ranks 2 and 3 Channe Bit 2 DIMM 1 Ranks 0 and 1 Channe Bit 3 DIMM 1 Ranks 2 and 3 Channe Bit 4 DIMM Ranks 0 and 1 Channe Bit 5 DIMM Ranks 2 and 3 Channe Bit 6 DIMM 1 Ranks 0 and 1 Channe Bit 7 DIMM 1 Ranks 2 and 3 Channe Bit 8 DIMM Ranks 0 and 1 Channe Bit 9 DIMM Ranks 2 and 3 Channel 2 Bit 10 DIMM 1 Ranks and 1 Channel 2 Bit 11 DIMM 1 Ranks 2 and 3 Channel 2 Fa Fa Fa OO O 50 Datasheet Register Description 2 8 4 MC_SMI_SPARE_CNTRL System Management Interrupt and Spare control register Device 3 Function 0 Offset 54h Access as a Dword 5 Value Description INTERRUPT_SELECT_NMI 1 Enable NMI signaling 16 22d 0 0 Disable NMI signaling If both NMI and SMI enable bits are set then only SMI is sent INTERRUPT_SELECT_SMI 1 Enable SMI signaling 0 Disable SMI signaling If both NMI and SMI enable bits are set then only SMI is sent This bit functions 15 RW 0 the same way in Mirror and Independent Modes The possible SMI events enabled by this bit are Any one of the error counters MC_COR_ECC_CNT_X meets the value of SMI_ERROR_THRESHOLD field of this register MC_SSRSTATUS CMPLT bit is set to 1 MC_RAS_STATUS REDUNDANCY_LOSS bit is set to 1 SMI_ERROR_THRESHOLD 14 0 RW 0 De
75. ferent DI MMs 000 22 00123 010 4 6 4 RW 011 gt 5 100 6 101 lt 7 110 lt 8 111 lt 9 tdrRdTRd Minimum delay between reads to different ranks on the same DIMM 000 2 00123 3 1 RW lt 011 5 100 6 101 7 110 8 111 9 tsrRdTRd 0 RW Minimum delay between reads to the same rank 0 4 1 6 Datasheet Register Description intel 2 10 11 MC CHANNEL 0 RANK TIMING B MC CHANNEL 1 RANK TIMING B MC CHANNEL 2 RANK TIMING B This register contains parameters that specify the rank timing used All parameters are in DCLK Device Offset Function 4 5 6 0 84h Access as a Dword Bit Type Reset Value Description 20 16 RW B2B CAS DELAY Controls the delay between CAS commands in DCLKS The minimum spacing is 4 DCLKS Values below 3 have no effect A value of 0 disables the logic Setting the value between 3 31 also spaces the read data by 0 29 DCLKS The value entered is one less than the spacing required i e a spacing of 5 DCLKS between CAS commands or 1 DCLK on the read data requires a setting of 4 15 13 RW tddWrTWr Minimum delay between writes to different DIMMs 000 2 001 3 010 4 01135 100 26 101 27 110 8 111 9 12 10 RW tdrWrTWr Minimum delay between writes to different ranks on the same DIMM 000 2 001 3 010 4 01135 100 6 101 27 110 8 111 9 RW tsrWrTWr Minimum delay between writ
76. fines the error threshold to compare against the per DI MM error counters MC_COR_ECC_CNT_X which are also 15 bits 2 8 5 MC_RESET_CONTROL DIMM Reset enabling controls Device Offset 3 Function 0 5Ch Access as a Dword Bit Type Description BIOS_RESET_ENABLE 0 WO 0 When set MC takes over control of driving RESET to the DIMMs This bit is set on S3 exit and cold boot to take over RESET driving responsibility from the physical layer Datasheet 51 tel Register Description 2 8 6 MC_CHANNEL_MAPPER Channel mapping register The sequence of operations to update this register is Read MC_Channel_ Mapper register Compare data read to data to be written If different then write Poll MC_Channel_ Mapper register until the data read matches data written Device 3 Function 0 Offset 60h Access as a Dword Bit Type pata Description RDLCH2 Mapping of Logical Channel 2 to physical channel for Reads 17 15 RW 0 001 Maps to physical Channel 0 010 Maps to physical Channel 1 100 Maps to physical Channel 2 WRLCH2 Mapping of Logical Channel 2 to physical channel for Writes 14 12 RW 0 001 Maps to physical Channel 0 010 Maps to physical Channel 1 100 Maps to physical Channel 2 RDLCH1 Mapping of Logical Channel 1 to physical channel for Reads 11 9 RW 0 001 Maps to physical Channel 0 010 Maps to physical Channel 1
77. ght banked 10 Sixteen banked MAXNUMRANK Maximum Number of Ranks 00 Single Ranked 302 x 01 Double Ranked 10 Quad Ranked MAXNUMDI MMS Maximum Number of DIMMs 00 2 1 DIMM 1 0 RW 0 01 2 DIMMs 10 2 3 DIMMs 11 RSVD Datasheet 53 intel MC_RD_CRDT_INIT These registers contain the initial read credits available for issuing memory reads TAD read credit counters are loaded with the corresponding values at reset and anytime this register is written BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform It is invalid to write this register while TAD is active has memory requests outstanding as the write will break TAD s outstanding credit count values 54 Register programming rules Total read credits CRDT_RD CRDT_RD_HIGH CRDT_RD_CRIT must not Register Description exceed 31 CRDT RD HIGH value must correspond to the number of high RTIDs reserved at the I OH CRDT RD CRIT value must correspond to the number of critical RTIDs reserved at the I OH CRDT RD HIGH CRDT RD must be less than or equal to 13 CRDT RD HIGH CRDT RD CRIT must be less than or equal to 8 CRDT RD CRIT must be less than or equal to 6 Set CRDT RD to 16 CRDT RD CRIT CRDT RD HIGH If Mirroring OR Sparing enabled then Max for CRDT RD is 14 otherwise it is 15 f Isoch not enabled then CRDT RD HIGH and CRDT RD CRIT are set to 0
78. h 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h QPI_QPILCL_LO 48h C8h 4Ch CCh 50h DOh 54h D4h 58h D8h 5Ch DCh 60h 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh 20 Datasheet Register Description tel Table 2 5 Device 2 Function 1 Intel Physical 0 Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR OCh 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h 48h C8h 4Ch CCh 50h DOh 54h D4h 58h D8h 5Ch DCh 60h EOh 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh Datasheet 21 intel Table 2 6 Device 3 Function 0 Integrated Memory Controller Registers Register Description DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR OCh 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h MC_CONTROL 48h C8h MC_STATUS 4Ch CCh MC_SMI_SPARE_DIMM_ERROR_STATUS 50h DOh MC_SMI_SPARE_CNTRL 54h D4h 58h D8h MC_RESET_CONTROL 5Ch DCh MC_CHANNEL_MAPPER 60h MC_MAX_DOD 64h E4h 68h E8h 6Ch ECh MC_RD_CRDT_INIT 70h FOh MC_CRDT_WR_THLD 74h F4h MC_SCRUBADDR_LO 78h F8h MC_SCRUBADDR_HI 7Ch FCh 22 Datasheet Register Description
79. h 4Ch 50h Access as a Dword Reset Bit Type Value Description RANKOFFSET Rank Offset for calculating RANK This field corresponds to the first logical rank on the DIMM The rank offset is 12 10 RW 0 always programmed to for the DIMM 0 DOD registers DIMM 0 rank offset is always 0 DIMM 1 DOD rank offset is either 4 for two DIMMs per channel or 2 if there are three DIMMs per channel DIMM2 DOD rank offset is always 4 as it is only used in three DIMMs per channel case 9 RW 0 DIMMPRESENT DIMM slot is populated NUMBANK Defines the number of real not shadow banks on these DIMMs 8 7 RW 0 00 Four banked 01 Eight banked 10 Sixteen banked NUMRANK Number of Ranks Defines the number of ranks on these DIMMs 00 Single Ranked 6 5 RW 0 3 01 Double Ranked 10 Quad Ranked NUMROW Number of Rows Defines the number of rows within these DIMMs 000 2 12 Rows 4 2 RW 0 001 2 13 Rows 010 2 14 Rows 011 2 15 Rows 100 2 16 Rows NUMCOL Number of Columns Defines the number of columns within on these DI MMs 00 2 10 columns 1 0 RW 0 01 2 11 columns 10 2 12 columns 11 RSVD 85 intel Register Description 2 11 3 CH2 0 MC CH2 1 MC CH2 2 Channel 2 DIMM Organization Descriptor Register 86 Offset Device Function 1 6 48h 4Ch 50h Access as a Dword Bit Type Reset Value Description 12 10 RW 0 RANKOFFSET Ra
80. h this attribute can be read or written by software Hardware or a configuration bit can lock the bit and prevent it from being updated Read Write Once A register bit with this attribute can be written to only once after power up After the first write the bit becomes read only This attribute is applied on a bit RWO by bit basis For example if the RWO attribute is applied to a 2 bit field and only one bit is written then the written bit cannot be rewritten unless reset The unwritten bit of the field may still be written once This is special case of RWL RRW Read Restricted Write This bit can be read and written by software However only supported values will be written Writes of non supported values will have no effect L Lock A register bit with this attribute becomes Read Only after a lock bit is set 15 Register Description Term Description Reserved Bit This bit is reserved for future expansion and must not be written The PCI RSVD Local Bus Specification Revision 2 2 requires that reserved bits must be preserved Any software that modifies a register that contains a reserved bit is responsible for reading the register modifying the desired bits and writing back the result Reserved Bits Some of the processor registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads softw
81. hat address the BIOS area from OE0000h to 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 5 4 RW 0 PAM4_ HI ENABLE 0DC000h 0DFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0DC000h to 0DFFFFh 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 1 0 RW 0 PAM4_LOENABLE 0D8000h ODBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to ODBFFFh 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM Datasheet 43 intel 2 6 3 SAD HEN Register for legacy Hole Enable Register Description Device 0 Function 1 Offset 4 8h Access as a Dword Bit Type None Description 7 RW 0 HEN Hole Enable
82. hat clock crossing Device 4 5 6 Function Offset D4h Access as a Dword Bit Type hahha Description 7 0 RW 0 ROUND TRIP LATENCY Round trip latency for reads Units are in UCLK This register must be programmed with the appropriate time for read data to be retuned from the pads after a READ CAS is sent to the DIMMs Datasheet Register Description tel 2 10 31 MC CHANNEL 0 PAGETABLE 51 MC CHANNEL 1 PAGETABLE 51 MC CHANNEL 2 PAGETABLE 51 These are the parameters used to control parameters for page closing policies Device 4 5 6 Function Offset D8h Access as a Dword Bit Type Description 15 8 RW 0 REQUESTCOUNTER This field is the upper 8 MSBs of a 12 bit counter This counter determines the window over which the page close policy is evaluated 7 0 RW 0 ADAPTI VETI MEOUTCOUNTER This field is the upper 8 MSBs of a 12 bit counter This counter adapts the interval between assertions of the page close flag For a less aggressive page close the length of the count interval is increased and vice versa for a more aggressive page close policy 2 10 32 MC CHANNEL O PAGETABLE PARAMS2 MC CHANNEL 1 PAGETABLE PARAMS2 MC CHANNEL 2 PAGETABLE PARAMS2 These are the parameters used to control parameters for page closing policies Device 4 5 6 Function Offset DCh Access as a Dword
83. his register These values are used for the automated MRS writes used as a part of the training FSM The remaining values of the MRS register must be specified here Device 4 5 6 Function Offset 70h Access as a Dword Bit Type ehe Description MR1 31 16 RW 0 The values to write to MR1 for 15 MRO 15 0 RW 0 The values to write to MRO for 15 Datasheet Register Description tel 2 10 8 2 10 9 Datasheet MC CHANNEL 0 MRS VALUE 2 MC CHANNEL 1 MRS VALUE 2 MC CHANNEL 2 MRS VALUE 2 The initial MRS register values for MR2 This register also contains the values used for RCO and RC2 writes for registered DIMMs These values are used during the automated training sequence when MRS writes or registered DIMM RC writes are used The RC fields do not need to be programmed if the address inversion and 3T 1T transitions are disabled Device 4 5 6 Function Offset 74h Access as a Dword 1 Reset Bit Type Value Description RC2 The values to write to the RC2 register on RDIMMS This value will be written 23 20 RW 0 whenever 3T or 1T timings are enabled by hardware For this reason bit 1 of the RC2 field bit 21 of this register will be controlled by hardware 23 22 and 20 will be driven with the RDIMM register write command for RC2 RCO The values to write to the RCO register on RDIMMS This value will be written 19 16 RW 0 whenever address inversi
84. ickPath Architecture System Address Decoder 2C01h 1 Intel Link 0 2C10h 0 Intel Physical 0 2C11 1 Integrated Memory Controller Registers 2C18h 0 Integrated Memory Controller Target Address Decoder 2C19h 1 Integrated Memory Controller RAS Registers 2C1Ah 3 21 Integrated Memory Controller Test Registers 2C1Ch 4 Integrated Memory Controller Channel 0 Control 2C20h 0 Integrated Memory Controller Channel 0 Address 2C21h 1 Processor Integrated Memory Controller Channel 0 Rank 2C22h 2 Integrated Memory Controller Channel 0 Thermal Control 2C23h 3 Integrated Memory Controller Channel 1 Control 2C28h 0 Integrated Memory Controller Channel 1 Address 2C29h al Integrated Memory Controller Channel 1 Rank 2C2Ah 2 Integrated Memory Controller Channel 1 Thermal Control 2C2Bh 3 Integrated Memory Controller Channel 2 Control 2C30h 0 Integrated Memory Controller Channel 2 Address 2C31h 1 Integrated Memory Controller Channel 2 Rank 2C32h 2 Integrated Memory Controller Channel 2 Thermal Control 2C33h 3 Notes 1 Applies only to processors supporting sparing mirroring and scrubbing RAS features 17 intel 2 4 Detailed Configuration Space Maps Table 2 2 Device 0 Function 0 Generic Non core Registers Register Description DID VID PCISTS PCICMD CCR RID HDR SID SVID 00h 04h 08 OCh 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h
85. ing or has happened with respect to the pin Device 4 5 6 Function 3 Offset A4h Access as a Dword Bit Type Mae Description 2 RO 0 ASSERTI ON An assertion edge was seen on DDR_THERM Write 1 to clear DEASSERTI ON 1 RO 0 A de assertion edge was seen on DDR Write 1 to clear STATE Present logical state of DDR THERMZ bit This is a static indication of the pin and may be several clocks out of date due to the delay between the pin and the 0 RO 0 signal STATE 0 means DDR_THERM is deasserted STATE 1 means DDR_THERM is asserted I ntegrated Memory Controller Miscellaneous Registers MC DIMM CLK RATIO STATUS This register contains status information about DIMM clock ratio Device 3 Function 4 Offset 50h Access as a Dword Bit Type Description MAX RATIO Maximum ratio allowed by the part Value 00000 RSVD 28 24 RO 0 00110 800 MHz 01000 1066 MHz 01010 1333 MHz QCLK_RATIO Current ratio of Qclk Value 00000 RSVD 4 R 0 9 00110 800 MHz 01000 1066 MHz 01010 1333 MHz 97 intel 2 14 2 98 MC DIMM CLK RATIO This register is for the Requested DIMM clock ratio Qclk This is the data rate going to the DIMM The clock sent to the DIMM is 1 2 of QCLK rate Register Description Device 3 Function 4 Offset 54h Access as a Dword Bit Type Via
86. intel Intel Core 17 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series Datasheet Volume 2 October 2009 Document Number 320835 003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined ntel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Core i7 900 desktop processor Extreme Edition series and Intel Core i7 900 desktop processor series may contain design defects or errors known as errata which may cause the produc
87. ionality feature set required to successfully bring up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the processor registers accordingly 2 2 16 ST appended The bit is sticky or unchanged by a hard reset These bits can only be cleared by a to the end of a PWRGOOD reset bit name Platform Configuration Structure The processor contains 6 PCI devices within a single physical component The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket Bus number is derived by the max bus range setting and processor socket number Device 0 Generic processor non core Device 0 Function 0 contains the generic non core configuration registers for the processor and resides at DID Device ID of 2C41h Device 0 Function 1 contains the System Address Decode registers and resides at DID of 2CO1h Device 2 Intel Device 2 Function 0 contains the Intel QuickPath Interconnect configuration registers for Intel Link 0 and resides at DID of 2C10h Device 2 Function 1 contains the physical layer registers for Intel QPI Link 0 and resides at DID of 2C11h Device 3 Integrated Memory Controller Device 3 Function 0 c
88. it is sent for every edge of the forwarded clock whether it be a rising edge or a falling edge If a number of edges are collected at instances ty t gt tk then the at instance n is defined as UI n t n t n 1 1 2 References Material and concepts available in the following documents may be beneficial when reading this document Table 1 1 References Document Location Inte Core i7 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series Specification Update http download intel com design processor specup dt 320836 pdf Inte Core i7 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series Datasheet Volume 1 http download intel com design processor datasht s 320834 pdf Inte 9 Core i7 900 Desltop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series and LGA1366 Socket Thermal and Mechanical Design Guide http download intel com design processor designe x 320837 pdf Inte 9 64 and 32 Intel Architecture Software Developer s Manual Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Part 1 Volume 3B Systems Programming Guide Part 2 http www intel com pro ducts processor manuals Datasheet
89. le When set MAD would use the longer pipeline for transactions that are 3 or 6 way interleaved and shorter pipeline for all other transactions The SAG registers must be appropriately programmed as well CHANNELRESET2 5 RW Reset only the state within the channel Equivalent to pulling warm reset for that channel CHANNELRESET1 4 RW Reset only the state within the channel Equivalent to pulling warm reset for that channel CHANNELRESETO 3 RW Reset only the state within the channel Equivalent to pulling warm reset for that channel AUTOPRECHARGE 2 RW Autoprecharge enable This bit should be set with the closed page bit If it is not set with closed page address decode will be done without setting the autoprecharge bit ECCEN ECC Enable 1 RW ECC Checking enables When this bit is set in lockstep mode the ECC checking is for the x8 SDDC ECCEN without Lockstep enables the x4 SDDC ECC checking CLOSED_ PAGE 0 RW When set the MC supports a Closed Page policy The default is Open Page but BIOS should always configure this bit Datasheet Register Description 2 8 2 Datasheet MC_ STATUS This register is the MC primary status register Device Offset 3 Function 0 4Ch Access as a Dword Bit Type Description 4 RO 1 ECC_ENABLED ECC is enabled CHANNEL2_ DISABLED 2 RO 0 Channel 2 is disabled This can be factory configured or if Init done is written without
90. m Description 4 0 RW 6 QCLK RATIO Requested ratio of Qclk Bclk 00000 RSVD 00110 800 MHz 01000 1066 MHz 01010 1333 MHz Datasheet
91. mory Controller Channel 1 Address Registers iiie teret ta tente bea a reg Pr bade 29 Device 5 Function 2 Integrated Memory Controller Channel 1 Rank Registers 30 Device 5 Function 3 Integrated Memory Controller Channel 1 Thermal Control Registers eiie neas rede E Ra E GR ER Pak 31 Device 6 Function 0 Integrated Memory Controller Channel 2 Control Registers 32 Device 6 Function 1 Integrated Memory Controller Channel 2 Address Registers cer menm tret eripe ix beri ea 33 Device 6 Function 2 Integrated Memory Controller Channel 2 Rank Reglsters esa ee 34 Device 6 Function 3 Integrated Memory Controller Channel 2 Thermal Control Registers itte tite espandi 35 Datasheet Revision History Description Date 001 Initial release November 2008 002 Updated section 2 2 and Table 2 3 November 2008 003 Updated document title and Introduction chapter October 2009 Datasheet 9 Introduction 1 Note 1 1 1 1 1 Datasheet intel Introduction The Intel Core i7 900 desktop processor Extreme Edition series and Intel Core i7 900 desktop processor series are intended for high performance high end desktop Uni processor UP server and workstation systems The processor implements key new technologies Integrated Memory Contr
92. n PCI Standard Registers These registers appear in every function for every device Reserved bit locations are not shown in the following register tables VID Vendor Identification Register The VID Register contains the vendor identification number This 16 bit register combined with the Device Identification Register uniquely identifies the manufacturer of the function within the processor Writes to this register have no effect Device Function Offset 0 0 0 Device 2 Function 0 Offset 0 Device Function Offset Function 3 0 0 Device 4 0 Offset 0 Reset Value Description Bit Type Vendor Identification Number 8086h The value assigned to Intel 15 0 RO DI D Device Identification Register This 16 bit register combined with the Vendor Identification register uniquely identifies the Function within the processor Writes to this register have no effect See Table 2 1 for the DID of each processor function Device 0 Function 0 Offset 0 Device Function Offset 2 0 0 Device 3 Function 0 2 4 Offset 0 Device 4 0 0 Function Offset Bit Reset Value Description 15 0 See Table 2 1 Device Identification Number Identifies each function of the processor Register Description intel 2 5 3 RID Revision Identification Register This register contains the revision number of the processo
93. n and first command should be considered REF 2X NOW 4 RW 0 Direct control of dynamic 2X refresh if MC THERMAL CONTROL THROTTLE MODE 2 THROTTLE NOW 3 0 RW 0 Throttler Vector to directly control throttling if MC THERMAL CONTROL THROTTLE MODE 2 MC THROTTLE OFFSETO MC THROTTLE OFFSET1 MC THROTTLE OFFSET2 Compared against bits 36 29 of virtual temperature of each rank stored in RANK VIRTUAL TEMP to determine the throttle point Recommended value for each rank is 255 When there are more than 4 ranks attached to the channel the thermal throttle logic is shared Device 4 5 6 Function 3 Offset 88h Access as a Dword Bit Type Description 31 24 RW 0 RANKS Rank 3 throttle offset 23 16 RW 0 RANK2 Rank 2 throttle offset 15 8 RW 0 RANK1 Rank 1 throttle offset 7 0 RW 0 Rank 0 throttle offset 95 m e tel Register Description 2 13 9 2 13 10 96 MC_RANK_VIRTUAL_TEMPO MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP2 This register contains the 8 most significant bits 37 30 of the virtual temperature of each rank The difference between the virtual temperature and the sensor temperature can be used to determine how fast fan speed should be increased The value stored is right shifted one bit to the right with respect to the corresponding MC_Throttle_ Offset register value For example when When a rank throttle offset is set to 40h
94. nk Offset for calculating RANK This field corresponds to the first logical rank on the DIMM The rank offset is always programmed to for the DIMM 0 DOD registers DIMM rank offset is always 0 DIMM 1 DOD rank offset is either 4 for two DIMMs per channel or 2 if there are three DIMMs per channel DIMM2 DOD rank offset is always 4 as it is only used in three DIMMs per channel case RW DIMMPRESENT DIMM slot is populated 8 7 RW NUMBANK Defines the number of real not shadow banks on these DIMMs 00 Four banked 01 Eight banked 10 Sixteen banked 6 5 RW NUMRANK Defines the number of ranks on these DIMMs 00 Single Ranked 01 Double Ranked 10 Quad Ranked 4 2 RW NUMROW Defines the number of rows within these DIMMs 000 2 12 Rows 001 2 13 Rows 010 2 14 Rows 011 2 15 Rows 100 2 16 Rows 1 0 RW NUMCOL Defines the number of columns within on these DIMMs 00 2 10 columns 01 2411 columns 10 2712 columns 11 RSVD Datasheet e Register Description n tel 2 11 4 Note Datasheet MC_SAG_CH0_0 MC_ SAG_ CH0_ 1 MC_ SAG_ CH0_ 2 SAG CHO 3 MC SAG 4 MC SAG 5 MC SAG CHO 6 MC SAG CHO 7 MC_SAG_CH1_0 MC SAG 1 1 SAG 1 2 MC SAG 1 3 MC SAG 1 4 MC SAG 1 5 MC SAG 1 6 MC SAG 1 7 MC SAG CH2 0 MC SAG CH2 1 MC SAG CH2 2 MC SAG CH2 3 MC SAG CH2 4 MC SAG 2
95. ntiguous address space within a channel BITS 9 0 ARE RESERVED AND MUST ALWAYS BE SET TO 0 87 intel 2 12 2 12 1 88 I ntegrated Memory Controller Channel Rank Registers MC RIR LIMIT CHO 0 MC RIR LIMIT CHO 1 MC RIR LIMIT CHO 2 MC RIR LIMIT CHO 3 MC RIR LIMIT CHO 4 MC RIR LIMIT CHO 5 MC LIMIT CHO 6 MC RIR LIMIT CHO 7 MC RIR LIMIT CH1 0 MC RIR LIMIT CH1 1 MC LIMIT CH1 2 MC RIR LIMIT 1 MC LIMIT CH1 4 MC RIR LIMIT 1 5 MC LIMIT CHI 6 MC RIR LIMIT 1 7 MC RIR LIMIT CH2 0 MC RIR LIMIT CH2 1 MC RIR LIMIT CH2 2 MC RIR LIMIT CH2 3 MC RIR LIMIT CH2 4 MC RIR LIMIT CH2 5 MC LIMIT CH2 6 MC RIR LIMIT CH2 7 Channel Rank Limit Range Registers Register Description Device 4 Function 2 Offset 40h 44h 48h 46 50h 54h 58h 5Ch Access as a Dword Bit Type Description LIMIT This field specifies the top of the range being mapped to the ranks specified in 9 0 RW 0 the MC_RIR_WAY_CH registers The most significant bits of the lowest address in this range is one greater than the limit field in the RIR register with the next lower index This field is compared against MA 37 28 Datasheet Register Description 2 12 2 Datasheet MC_RIR_WAY_CHO_0 MC RIR WAY CHO 1 MC WAY CHO 2 MC RIR WAY 3 MC WAY CHO 4 MC RIR WAY 5 MC WAY 6 MC RIR WAY 7 MC WAY
96. o command is issued WRCMD_ ENERGY 15 8 RW 0 m Energy of a write including data transfer RDCMD ENERGY 7 0 RW 0 z F Energy of read including data transfer 93 intel 2 13 5 2 13 6 94 Register Description MC THERMAL PARAMS BO MC THERMAL PARAMS B1 MC THERMAL PARAMS B2 Parameters used by the thermal throttling logic Device 4 5 6 Function 3 Offset 64h Access as a Dword Reset Bit Type Value Description SAFE INTERVAL Safe values for cooling coefficient and duty cycle will be applied while the SAFE INTERVAL is exceeded This interval is the number of ZQ intervals since the last time the MC COOLING COEF or MC CLOSED LOOP registers have been written A register to write to MC COOLING COEF or MC CLOSED LOOP 31 26 RW 1 will re apply the normal MC COOLING COEF and MC CLOSED LOOPMIN THROTTLE DUTY CYC values The register value written need not be different writing the current value will suffice The MC THERMAL STATUS CYCLES THROTTLED field is reloaded when the number of ZQ intervals exceeds this value This field must not be programmed to 0 this value is illegal SAFE DUTY CYC This value replaces 25 16 RW 255 CLOSED LOOP MIN THROTTLE DUTY CYC while the MC THERMAL PARAMS B SAFE INTERVAL is exceeded SAFE COOL COEF 15 8 RW 1 This value replaces MC_COOLING_COEF while the THERMAL PARAMS B SAFE INTERVAL is exceeded ACTCMD ENERGY Energy of an Activate Precharg
97. o specify the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register 7 6 RW 0 For writes to the register this field always contains the Rank For reads the following translation must be done If 3 DIMMs are on the channel then the rank is while the dimm is the concatenation of DIMM 0 and RANK 1 RANK This field contains the rank of the last scrub issued Can be written to specify the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL 5 4 RW 0 register For writes to the register this field always contains the rank id For reads the following translation must be done If 3 dimms are on the channel then the rank is while the dimm is the concatenation of DIMM 0 and RANK 1 BANK 3 0 RW 0 This field contains the bank of the last scrub issued Can be written to specify the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register Datasheet Register Description n tel 2 9 TAD Target Address Decoder Registers 2 9 1 _ TAD_DRAM_RULE_0 TAD DRAM RULE 1 TAD DRAM RULE 2 TAD DRAM RULE 3 TAD DRAM RULE 4 TAD DRAM RULE 5 TAD DRAM RULE 6 TAD DRAM RULE 7 TAD DRAM rules Address map for channel determination within a package All addresses sent to this HOME agent must hit a valid enabled DRAM RULE No error will be generated if they do not hit a valid location and memory aliasing will happen Device 3 Function 1 Offset 80h 84h 88h 8Ch 90h 9
98. oller Point to point link interface based on Intel QuickPath Interconnect Intel Reference to this interface may sometimes be abbreviated with Intel throughout this document In this document the Intel Core i7 900 desktop processor Extreme Edition series and Intel Core i7 900 desktop processor series will be referred to as the processor This datasheet provides register descriptions for some of the registers located on the processor The processor is optimized for performance with the power efficiencies of a low power microarchitecture to enable smaller quieter systems The Intel Core i7 900 desktop processor Extreme Edition series and Intel Core i7 900 desktop processor series are multi core processors based on 45 nm process technology Processor features vary by component and include up to two Intel QuickPath Interconnect point to point links capable of up to 6 4 GT s up to 8 MB of shared cache and an integrated memory controller The processors support all the existing Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 SSE4 The processor supports several Advanced Technologies Execute Disable Bit Intel 64 Technology Enhanced Intel SpeedStep Technology Intel virtualization Technology Intel VT Intel Turbo Boost Technology and Hyper Threading Technology Terminology A symbol after a signal name refers to an active low
99. on is enabled or disabled by hardware For this reason bit 0 of the RCO field bit 16 of this register will be controlled by hardware 19 17 will be driven with the RDIMM register write command for RCO MR2 15 RW 99 o The values to write to MR2 for A15 A0 MC CHANNEL O RANK PRESENT MC CHANNEL 1 RANK PRESENT MC CHANNEL 2 RANK PRESENT This register provides the rank present vector Device 4 5 6 Function Offset 7Ch Access as a Dword Reset Value Description Bit Type RANK PRESENT Vector that represents the ranks that are present Each bit represents a logical rank When two or fewer DI MMs are present 3 0 represents the four possible ranks in DIMMO and 7 4 represents the ranks that are possible in DIMM1 7 0 RW 0 When three DI MMs are present then the following applies 1 0 represents ranks 1 0 in Slot O 3 2 represents ranks 3 2 in Slot 1 5 4 represents ranks 5 4 in Slot 2 65 2 10 10 MC CHANNEL 0 RANK TIMING A MC CHANNEL 1 RANK TIMING A MC CHANNEL 2 RANK TIMING A 66 intel Register Description This register contains parameters that specify the rank timing used All parameters are in DCLK Device Offset Function 4 5 6 0 80h Access as a Dword Bit Type Reset Value 28 26 RW tddWrTRd Minimum delay between a write followed by a read to different DIMMs 000 1 001 2 010 3 011 4 100 5 101
100. ontains the general registers for the Integrated Memory Controller and resides at DID of 2C18h Device 3 Function 1 contains the Target Address Decode registers for the Integrated Memory Controller and resides at DID of 2C19h Device 3 Function 2 contains the RAS registers for the Integrated Memory Controller and resides at DID of 2C1Ah Device 3 Function 4 contains the test registers for the Integrated Memory Controller and resides at DID of 2C1Ch Function 2 only applies to processors supporting registered DIMMs Device 4 Integrated Memory Controller Channel 0 Device 4 Function 0 contains the control registers for Integrated Memory Controller Channel 0 and resides at DID of 2C20h Device 4 Function 1 contains the address registers for Integrated Memory Controller Channel 0 and resides at DID of 2C21h Device 4 Function 2 contains the rank registers for Integrated Memory Controller Channel 0 and resides Datasheet Register Description 2 3 Table 2 1 Datasheet intel at DID of 2C22h Device 4 Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2C23h Device 5 Integrated Memory Controller Channel 1 Device 5 Function 0 contains the control registers for Integrated Memory Controller Channel 1 and resides at DID of 2C28h Device 5 Function 1 contains the address registers for Integrated Memory Controller Channel 1 and resides at DID of 2C29h Device 5 Function 2
101. ontrol MC RIR WAY CH2 11 MC RIR WAY CH2 13 MC RIR WAY CH2 15 MC RIR WAY CH2 17 MC RIR WAY CH2 19 MC RIR WAY CH2 21 MC RIR WAY CH2 23 MC RIR WAY CH2 25 MC RIR WAY CH2 27 MC RIR WAY CH2 29 MC RIR WAY CH2 31 MC THERMAL CONTROLO MC THERMAL CONTROLI1 MC THERMAL CONTROL2 MC THERMAL STATUSO MC THERMAL STATUS1 MC THERMAL STATUS2 MC THERMAL DEFEATUREO MC THERMAL DEFEATURE1 MC THERMAL DEFEATURE2 MC THERMAL PARAMS AO MC THERMAL PARAMS A1 MC THERMAL PARAMS A2 MC THERMAL PARAMS BO MC THERMAL PARAMS B1 MC THERMAL PARAMS B2 MC COOLING COEFO MC COOLING COEF1 MC COOLING COEF 94 MC CLOSED LOOPO MC CLOSED LOOP1 MC CLOSED LOOP2 MC THROTTLE OFFSETO MC THROTTLE OFFSET1 MC THROTTLE OFFSET2 MC RANK VIRTUAL TEMPO MC RANK VIRTUAL TEMP1 MC RANK VIRTUAL TEMP2 2 13 10 MC DDR THERM COMMANDO MC DDR THERM 1 MC DDR THERM COMMAND2 96 2 13 11 MC_DDR_THERM_STATUSO MC DDR THERM STATUS1 MC DDR _5 52 97 2 14 Integrated Memory Controller Miscellaneous 97 2 14 1 MC DIMM RATIO STATUS isi tea say akanan deo 97 21142 RATIO u ipie ac epe rei ce 98 Datasheet 7 intel Tables NONNNNNN S P Di 2 10 2 11 2 1
102. patterns driven out onto ODT pins when Rank6 is read 15 8 RW 4 ODT RD5 Bit patterns driven out onto ODT pins when Rank5 is read 7 0 RW 4 ODT_RD4 Bit patterns driven out onto ODT pins when Rank 4 is read 2 10 21 MC CHANNEL O ODT MATRIX RANK O 3 WR MC CHANNEL 1 ODT MATRIX RANK 3 WR MC CHANNEL 2 ODT MATRIX RANK O 3 WR This register contains the ODT activation matrix for RANKS 0 to 3 for Writes Device 4 5 6 Function Offset ACh Access as a Dword Bit Type Description 31 24 RW 9 ODT WRS Bit patterns driven out onto ODT pins when Rank3 is written 23 16 RW 5 ODT WRQ2 Bit patterns driven out onto ODT pins when Rank2 is written 15 8 RW 6 ODT WhRI Bit patterns driven out onto ODT pins when Rank1 is written 7 0 RW 5 ODT_ WRO Bit patterns driven out onto ODT pins when Ranko is written 2 10 22 MC CHANNEL 0 ODT MATRIX RANK 4 7 WR MC CHANNEL 1 ODT MATRIX RANK 4 7 WR MC CHANNEL 2 ODT MATRIX RANK 4 7 WR This register contains the ODT activation matrix for RANKS 4 to 7 for Writes Device 4 5 6 Function Offset BOh Access as a Dword Bit Type ehe Description 31 24 RW 9 ODT_WR7 Bit patterns driven out onto ODT pins when Rank7 is written 23 16 RW 5 ODT WR6 Bit patterns driven out onto ODT pins when Rank6 is written 15 8 RW 6 ODT_WRS Bit patterns driven out onto ODT pins when Rank5 is written 7 0 RW 5 ODT WhRA Bit patterns driven out onto ODT
103. pins when Rank 4 is written 74 Datasheet Register Description intel 2 10 23 MC CHANNEL 0 WAQ PARAMS MC CHANNEL 1 WAQ PARAMS MC CHANNEL 2 WAQ PARAMS This register contains parameters that specify settings for the Write Address Queue Datasheet Device Offset 4 5 6 Function B4h Access as a Dword Bit Type Description PRECASWRTHRESHOLD 29 25 RW 6 Threshold above which Medium Low Priority reads cannot PRE CAS write requests PARTWRTHRESHOLD 24 20 RW 31 Threshold used to raise the priority of underfill requests in the scheduler Set to 31 to disable 1 SOCEXI TTHRESHOLD 19 15 RW 31 Write Major Mode ISOC Exit Threshold When the number of writes in the WAQ drops below this threshold the MC will exit write major mode in the presence of a read ISOCENTRYTHRESHOLD 14 10 RW 31 Write Major Mode ISOC Entry Threshold When the number of writes in the WAQ exceeds this threshold the MC will enter write major mode in the presence of a read WMENTRYTHRESHOLD 9 5 RW 22 Write Major Mode Entry Threshold When the number of writes in the WAQ exceeds this threshold the MC will enter write major mode WMEXI TTHRESHOLD 4 0 RW 22 Write Major Mode Exit Threshold When the number of writes in the WAQ drop below this threshold the MC will exit write major mode 75 m e n tel Register Description 2 10 24 MC CHANNEL 0 SCHEDULER PARAMS MC CHANNEL 1 SCHED
104. r The Revision ID RID isa traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function Device Offset Device Offset Device Offset Device Offset Function Function Function Function 1 8h Bit Tvpe Reset yp Value Description 7 0 RO Oh Revision dentification Number Refer to the Intel Core i7 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series Specification Update for the value of the Revision ID Register 2 5 4 CCR Class Code Register This register contains the Class Code for the device Writes to this register have no effect Device 0 Function 0 1 Offset 09h Device 2 Function 0 1 4 5 Offset 09h Device 3 Function 0 2 4 Offset 09h Device 4 6 Function 0 3 Offset 09h Reset eee Bit Type Value Description Base Class 23 16 RO 06 This field indicates the general device category For the processor this field is hardwired to 06h indicating it is a Bridge Device Sub Class 15 8 RO 0 This field qualifies the Base Class providing a more detailed specification of the device function For all devices the default is 00 indicating Host Bridge Register Level Programming I nterface 7 0 RO 0 This field identifies a specific programming interface if any
105. rent command is an MRS command Bit is cleared by hardware on issuance RANK 22 20 RW 0 oi Destination rank for command MRS BA 19 16 RW 0 Address bits driven to DDR BA 2 0 pins for the DRAM command being issued due to a valid bit being set in this register MRS ADDR 15 0 RW 0 Address bits driven to DDR MA pins for the DRAM command being issued due to a valid bit being set in this register 63 intel 2 10 6 2 10 7 64 Register Description MC CHANNEL REFRESH THROTTLE SUPPORT MC CHANNEL 1 REFRESH THROTTLE SUPPORT MC CHANNEL 2 REFRESH THROTTLE SUPPORT This register supports Self Refresh and Thermal Throttle functions Device 4 5 6 Function Offset 68h Access as a Dword Bit Type Pai Description INC ENTERPWRDWN RATE Powerdown rate will be increased during thermal throttling based on the following configurations 3 2 RW 0 00 tRANKIDLE Default 01 lt 16 10 lt 24 11 32 1 RW 0 DIS OP REFRESH When set the refresh engine will not issue opportunistic refresh ASR PRESENT 0 RW 0 When set indicates DRAMs on this channel can support Automatic Self Refresh If the DRAM is not supporting ASR Auto Self Refresh then Self Refresh entry will be delayed until the temperature is below the 2x refresh temperature MC CHANNEL 0 MRS VALUE 0 1 MC CHANNEL 1 MRS VALUE 1 MC CHANNEL 2 MRS VALUE 1 The initial MRS register values for MRO and MR1 can be specified in t
106. running Memtest the failing address is logged in this register on Memtest errors Software can write the next address to be scrubbed into this register Patrol scrubs must be disabled to reliably write this register Device 3 Function Offset 78h Access as a Dword Reset NT Bit Type Value Description 29 14 RW 0 PAGE next scrub address with STARTSCRUB in the MC SCRUB CONTROL register This field contains the row of the last scrub issued Can be written to specify the 13 0 RW 0 COLUMN This field contains the column of the last scrub issued Can be written to specify the next scrub address with STARTSCRUB in the MC SCRUB CONTROL register 55 56 Register Description MC SCRUBADDR HI This register pair contains part of the address of the last patrol scrub request issued When running memtest the failing address is logged in this register on memtest errors Software can write the next address into this register Scrubbing must be disabled to reliably read and write this register Device 3 Function Offset 7Ch Access as a Dword Reset 22 Bit Type Value Description CHNL 9 8 RW 0 This field can be written to specify the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register This register is not updated with channel address of the last scrub address issued DIMM This field contains the DIMM of the last scrub issued Can be written t
107. s be asserted 4 RW 0 FORCE 4 Force ODT for Rank4 to always be asserted 3 RW 0 FORCE ODT3 Force ODT for Rank3 to always be asserted 2 RW 0 FORCE 012 Force ODT for Rank2 to always be asserted 1 RW 0 FORCE 011 Force ODT for Rank1 to always be asserted 0 RW 0 FORCE Force ODT for to always be asserted 2 10 19 MC CHANNEL 0 ODT MATRIX RANK 0 3 RD Datasheet MC CHANNEL 1 ODT MATRIX RANK O 3 RD MC CHANNEL 2 ODT MATRIX RANK 0 3 RD This register contains the ODT activation matrix for RANKS 0 to 3 for Reads Device 4 5 6 Function Offset A4h Access as a Dword Bit Type 2 Description 31 24 RW L ODT RD3 Bit patterns driven out onto ODT pins when Rank3 is read 23 16 RW 1 ODT_RD2 Bit patterns driven out onto ODT pins when 2 is read 15 8 RW 4 RDI Bit patterns driven out onto ODT pins when 1 is read 7 0 RW 4 ODT RDO Bit patterns driven out onto ODT pins when is read 73 m e n tel Register Description 2 10 20 MC CHANNEL 0 ODT MATRIX RANK 4 7 RD MC CHANNEL 1 ODT MATRIX RANK 4 7 RD MC CHANNEL 2 ODT MATRIX RANK 4 7 RD This register contains the ODT activation matrix for RANKS 4 to 7 for Reads Device 4 5 6 Function O Offset A8h Access as a Dword Bit Type ure Description 31 24 RW ODT_RD7 Bit patterns driven out onto ODT pins when Rank7 is read 23 16 RW 1 RD6 Bit
108. sent in the channel The rank value is set to the rank being trained NXT PHYINIT STATE Set to sequence the physical layer state machine 000 IDLE 4 2 RW 0 001 RD DQ DQS 010 RcvEn Bitlock 011 Write Level 100 WR DQ DQS AUTODIS 1 RW 0 Disables the automatic training where each step is automatically incremented When set the physical layer state machine must be sequenced with software The training FSM must be sequenced using the NXT_PHYINIT_STATE field TRAIN 0 WO 0 TU Cycle through the training sequence for the rank specified in the RANK field 60 Datasheet Register Description tel 2 10 3 Datasheet MC CHANNEL 0 DIMM INIT PARAMS MC CHANNEL 1 DIMM INIT PARAMS MC CHANNEL 2 DIMM INIT PARAMS Initialization sequence parameters are stored in this register Each field is 2 n count Device 4 5 6 Function Offset 58h Access as a Dword Bit Type Description 5 3 When set 3T mode will not be enabled as a part of the MRS write to the 26 RW 0 RDIMM The RC2 write to switch to 3 and back to 1T timing before and after an MRS write will not be done if the bit is set This bit should be set if the RDIMM supports auto MRS cycles where the dimm takes care of the 3T switching on MRS writes DIS_Al When set address inversion will not be disabled as a part of the MRS write to 25 RW 0 the RDIMM The RCO write to disable and enable address inversion will not b
109. t Contents 1 11 1 1 qaa sa estates apaqpas 11 1 1 1 Processor Terminology teme 11 12 References eost aes N 13 2 Register Description ets Po dx eed dees 15 2 1 Register Ene 15 2 2 Platform Configuration Structure enemies e menn 16 2 3 Device 17 2 4 Detailed Configuration Space 18 2 5 PCI Standard Registers memes eee eese sens 36 2 5 1 VID Vendor Identification Register rr mme 36 2 5 2 DID Device Identification Register 36 2 5 3 RID Revision Identification 9 5 rr 37 2 5 4 CCR Class Code Register 37 2 5 5 HDR Header Type Register eee n E nee nene nnns 38 2 5 6 SID SVID Subsystem Identity Subsystem Vendor Identification Register 38 2 5 7 PCICMD Command Register sse emen 39 2 5 8 515 PCI Status
110. t can improve virtualization solutions Intel VT provides a foundation for widely deployed virtualization solutions and enables more robust hardware assisted virtualization solutions More information can be found at http www intel com technology virtualization Jitter Any timing variation of a transition edge or edges from the defined Unit Interval LGA1366 Socket The processor in the LGA 1366 package mates with the system board through this surface mount 1366 contact socket Mirror Port Pads located on the top side of the processor package used to provide logic analyzer probing access for Intel QPI signal analysis Non core The portion of the processor comprising the shared cache IMC and Intel OPI Link interface OEM Original Equipment Manufacturer Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any 1 05 biased or receive any clocks Intel Core 17 900 desktop processor Extreme Edition series and Intel Core i7 900 desktop processor series The desktop product including processor substrate and integrated heat spreader IHS Datasheet intel Introduction Unit Interval UI Signaling convention that is binary and unidirectional In this binary signaling one b
111. t to deviate from published specifications Current characterized errata are available on request A ntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel com products ht hyperthreading_more htm Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See www intel com info em64t for more information including details on
112. ter separation can be modified via the round trip setting larger value causes a larger pointer separation 23 16 RW 0 OFFSET RX offset setting 15 8 RW 1 ALI ENRATI O QcIk to BCLK ratio RX Alien Ratio setting 7 0 RW 2 NATI VERATI O Uclk to BCLK ratio RX Native Ratio setting 77 intel 2 10 28 2 10 29 2 10 30 78 MC CHANNEL 0 SETTINGS MC CHANNEL 1 EW BGF SETTINGS MC CHANNEL 2 SETTINGS These are the parameters used to set the early warning RX clock crossing BGF Device 4 5 6 Function Offset CCh Access as a Dword Reset Value Description 15 8 RW 1 ALI ENRATI O DcIk to Bclk ratio Early warning Alien Ratio setting MC CHANNEL 0 OFFSET SETTINGS MC CHANNEL 1 OFFSET SETTINGS MC CHANNEL 2 OFFSET SETTINGS These are the parameters to set the early warning RX clock crossing BGF Device 4 5 6 Function Offset DOh Access as a Dword Bit Type 22 Description 15 8 RW 2 EVENOFFSET Early warning even offset setting 7 0 RW 0 ODDOFFSET Early warning odd offset setting MC CHANNEL O ROUND TRIP LATENCY MC CHANNEL 1 ROUND TRIP LATENCY MC CHANNEL 2 ROUND TRIP LATENCY These are the parameters to set the early warning RX clock crossing the Bubble Generator FIFO BGF used to go between different clocking domains These settings provide the gearing necessary to make t
113. ty If no capability structures are implemented this bit is hardwired to 0 Interrupt Status If this device generates an interrupt then this read only bit reflects the state of the interrupt in the device function Only when the Interrupt Disable bit in the 3 RO 0 command register is a 0 and this Interrupt Status bit is a 1 will the device s function s INTx signal be asserted Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit If this device does not generate interrupts then this bit is not implemented RO and reads returns 0 2 0 RO 0 Reserved 2 6 2 6 1 SAD System Address Decoder Registers SAD PAMO123 This register is for legacy device 0 function 0 at 90h 93h address space Device 0 Function 1 Offset 40h Access as a Dword Datasheet Bit Type LPs Description PAM3 HI ENABLE 0D4000h 0D7FFFh Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh 29 28 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation reads and writes are serviced by DRAM 41 42 Register Description Device 0 Function 1 Offset 40h Access as a Dword Bit Type sad Description PA

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