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Intel Core 2 Quad Q6700

1. Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name gn Bier Pub Direction Land Name gio Bitte ione Direction vss AG20 Power Other vss AK30 Power Other vss AG23 Power Other vss AK5 Power Other vss AG24 Power Other vss AK7 Power Other vss AG7 Power Other vss AL10 Power Other VSS AH1 Power Other vss AL13 Power Other vss AH10 Power Other vss AL16 Power Other vss AH13 Power Other vss AL17 Power Other vss AH16 Power Other vss AL20 Power Other vss AH17 Power Other vss AL23 Power Other vss AH20 Power Other vss AL24 Power Other VSS AH23 Power Other vss AL27 Power Other vss AH24 Power Other vss AL28 Power Other vss AH3 Power Other vss AL7 Power Other vss AH6 Power Other vss AM1 Power Other vss AH7 Power Other vss AM10 Power Other VSS AJ10 Power Other VSS AM13 Power Other VSS AJ13 Power Other VSS AM16 Power Other VSS AJ16 Power Other VSS AM17 Power Other VSS AJ17 Power Other VSS AM20 Power Other VSS AJ20 Power Other VSS AM23 Power Other VSS AJ23 Power Other VSS AM24 Power Other VSS AJ24 Power Other VSS AM27 Power Other VSS AJ27 Power Other VSS AM28 Power Other VSS AJ28 Power Other VSS AM4 Power Other VSS AJ29 Power Other VSS AN1 Power Other VSS AJ30 Power Other VSS AN10 Power Other VSS AJ4 Power Other VSS AN13 Power Other VSS AJ7 Power Other VSS AN16 Powe
2. AN OOOOOO OOOOO O OOOOO AN AM OOOOOOOOOOOOOOO00 O OO O AM AL 2 OOO0OO0O0O0O0O0OOOOOOQOQ OC Q AL AK OOOOO OOOOOOOOOOO OC Q AK AJ OO O OOOOOOCOOOOO O AJ AH exer OO0000000000 AH QOC OQOOOOQGO 0 OOO00 00000600 OOOO OOO OOOOOOCO O OOOC 5 OOOO O 0000 OOOO JO O00 O000 O Address oe u 555 Socket 775 Common Clock O000 Quadrants O Async O x lt z 3 O OOOC op View O CAC f D UO L EP O O re E N CM O 20 O OIO Ne YN Xe O O OO O JOC OO f ay K C cooommorcecarzzvoxAac cz zb58582n28 cmoommorce arzzvom xac c z z585hn28 f s x UP No E WU N y O rN N V T M V Cy 4 rs y S Ned x x Z V OO O Cy G Tata O Lora VY I x Nas Ne cur y i ry A rrr y VAY m4 NL L ol NE AO G G NO xz NS Mah s WY OOO OD Vu MUN KU G h n 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12111009 8 7 6 5 4 3 2 1 V_ Clocks Data 55 38 Datasheet Land Listing and Signal Descriptions n tel d Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions 4 1 Processor Land Assignments This section contains the land listings for the processor The land out footprint is shown in Figure 13 and Figure 14 These figures represent the land out arranged by land number and they show the ph
3. Datasheet Land Listing and Signal Descriptions n tel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment HM Land Name Hunter Direction E Land Name i Buter Direction ype ype AL18 vcc j Poweyoter amz vss Power Other AL19 VCC Power Other AM28 VSS Power Other AL20 vss Power Other AM29 VCC Power Other AL21 VCC Power Other AM30 VCC Power Other AL22 VCC Power Other AN1 VSS Power Other AL23 vss Power Other AN2 vss Power Other AL24 vss Power Other AN3 VCC_SENSE Power Other Output AL25 VCC Power Other AN4 VSS_SENSE Power Other Output AN5 nasya na Power Other Output AL28 VSS Power Other AN6 SECURE Power Other Output AL29 VCC Power Other ANT VID SELECT Power Other Output AGo vec Powervother ans vcc Power Other AMI vss Power Other AN9 VCC Power Other AM2 VIDO Power Other Output AN10 VSS Power Other AM3 VID2 Power Other Output AN11 VCC Power Other AM4 vss Power Other AN12 VCC Power Other AM5 VID6 Power Other Output AN13 vss Power Other AM6 FC40 Power Other AN14 vcc Power Other AM7 VID7 Power Other Output AN15 vcc Power Other AM8 VCC Power Other AN16 vss Power Other AM9 VCC Power Other AN17 vss Power Other AM10 vss Power Other AN18 VCC Power Other A
4. nee e e emnes 31 3 2 Processor Component Keep Out Zones 40000000 r n n k 35 3 3 Package Loading Specifications cece eee eee eee E e eee memes nens 35 3 4 Package Handling Guidelines r meme menn 35 3 5 Package Insertion Specifications ar rr 36 3 6 Processor Mass Specification sss neta e emen nns 36 3 7 Processor Materials ecrire cokes e URP MKUEERUREPIRKR KEPARURA MURDER RU PUHKEXKRDAEE dn E 36 3 8 Processor Markings o EX Y EXERERA RATER dk ak ves eee ng RR KNIE ed RING 36 3 9 Processor Land Coordinates u L sir i aa ana u snnm memes nes 38 4 Land Listing and Signal Descriptions 0c eee m 39 4 1 Processor Land Assignments rr sse nee K K K K messen 39 4 2 Alphabetical Signals Reference enna see e esee nns 62 5 Thermal Specifications and Design Considerations rr 71 5 1 Processor Thermal Specifications mmn nemen 71 5 1 1 Thermal Specifications eorr teres eren eere neben pror der PENER IDRE 71 5 1 2 Thermal Metrology annn En an NAE EERE menses eene nemen eese 76 5 2 Processor Thermal Features c cc cece eee ee eee nena eee seem see memes ens 76 521 Thermal MOnitoring anain Pune RH PR Ene aeu rr RE Reed 76 5 2 2 Thermal Monitor 2 iore eret SR RR ERR eine dak n RIDE TRUE
5. om D SCALE 20 1 NU 000000000000000000000000000 0000 000000000000000000000000000000000 000000000000000000000000000000000 00000000000000000 0000000000000000 000000000000000000000000000000000 000000000000000000000000000000000 OO0000000000000000000000000000000 0000000000000000090000000000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 O00000000 000000000 000000000 O00000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 5 i 000000000 000000000 000000000 O00000000000000000000000000000000 000000000000000000000000000000000 000000000000000000000000000000000 000000000000000060000000000000000 000000000000000060000000000000000 000000000000000000000000000000000 O00000000000000090000000000000000 O00000000000000090000000000 900 VS A COMMENTS BOTTOM VIEW MAX MILLIMETERS WIN RI 4 BASIC RI 4 BASIC 0 2 BASIC 6 215 BASIC 0 2 BASIC 6 215 BASIC SYMBOL Ri id T T Y C l he Datasheet 33 intel Figure 9 Processor Package Drawing Sheet 3 of 3 e uL ul l a o Package Mechanical Specifications JW C88285 7 6 25 OOOOOOOOOQOOOOOO
6. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Intel 64 Architecture An enhancement to Intel s IA 32 architecture allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http www intel com technology intel64 index htm Datasheet Introduction 1 2 Table 1 Datasheet intel Enhanced Intel Technology SpeedStep Technology Enhanced Intel Technology SpeedStep Technology allows trade offs to be made between performance and power consumptions based on processor utilization This may lower average power consumption in conjunction with OS support Intel virtualization Technology Intel VT Intel Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improv
7. NOTES 1 Diagram does not show the attached hardware for the clip design and is provided only asa mechanical representation Figure 25 Space Requirements for the Boxed Processor Overall View Datasheet 89 m n tel Boxed Processor Specifications 7 2 7 2 1 90 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams Refer to Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 26 Baseboards must provide a matched power header to support the boxed processor Table 32 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull
8. If the boxed processor fan heatsink 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output CONTROL see Table 32 and remote thermal diode measurement capability the boxed processor will operate as follows As processor power has increased the required thermal solutions have generated increasingly more noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4th wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures 95 96 e n tel Boxed Processor Specifications If the new 4 pin active fan heat sink solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific moth
9. Source Synch Input Output D22 D10 Source Synch Input Output D61 A19 Source Synch Input Output D23 F11 Source Synch Input Output D62 A22 Source Synch Input Output D24 F12 Source Synch Input Output D63 B22 Source Synch Input Output D25 D13 Source Synch Input Output DBIO A8 Source Synch Input Output D26 E13 Source Synch Input Output DBI1 G11 Source Synch Input Output D27 G13 Source Synch Input Output DBI2 D19 Source Synch Input Output D28 F14 Source Synch Input Output DBI3 C20 Source Synch Input Output D29 G14 Source Synch Input Output DBR AC2 Power Other Output D30 F15 Source Synch Input Output DBSY B2 Common Clock Input Output D31 G15 Source Synch Input Output DEFER G7 Common Clock Input D32 G16 Source Synch Input Output DRDY C1 Common Clock Input Output D33 E15 Source Synch Input Output DSTBNO C8 Source Synch Input Output D34 E16 Source Synch Input Output DSTBN1 G12 Source Synch Input Output D35 G18 Source Synch Input Output DSTBN2 G20 Source Synch Input Output D36 G17 Source Synch Input Output DSTBN3 A16 Source Synch Input Output D37 F17 Source Synch Input Output DSTBP0 B9 Source Synch Input Output D38 F18 Source Synch Input Output DSTBP1 E12 Source Synch Input Output D39 E18 Source Synch Input Output DSTBP2 G19 Source Synch Input Output D40 E19 Source Synch Input Output DSTBP3 C17 Sourc
10. the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT PROCHOT allows for some protection of various components from over temperature situations The PROCHOT signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on PROCHOTZ only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized therm
11. 1 1 0 0 0 1 1 0000 0 1 0 0 1 0 1 3875 1 1 0 0 0 0 1 0125 0 1 0 0 0 1 1 4000 1 0 1 1 1 1 1 0250 0 1 0 0 0 0 1 4125 1 0 1 1 1 0 1 0375 0 0 1 1 1 1 1 4250 1 0 1 1 0 1 1 0500 0 0 1 1 1 0 1 4375 1 0 1 1 0 0 1 0625 0 0 1 1 0 1 1 4500 1 0 1 0 1 1 1 0750 0 0 1 1 0 0 1 4625 1 0 1 0 1 0 1 0875 0 0 1 0 1 1 1 4750 1 0 1 0 0 1 1 1000 0 0 1 0 1 0 1 4875 1 0 1 0 0 0 1 1125 0 0 1 0 0 1 1 5000 1 0 0 1 1 1 1 1250 0 0 1 0 0 0 1 5125 1 0 0 1 1 0 1 1375 0 0 0 1 1 1 1 5250 1 0 0 1 0 1 1 1500 0 0 0 1 1 0 1 5375 1 0 0 1 0 0 1 1625 0 0 0 1 0 1 1 5500 1 0 0 0 1 1 1 1750 0 0 0 1 0 0 1 5625 1 0 0 0 1 0 1 1875 0 0 0 0 1 1 1 5750 1 0 0 0 0 1 1 2000 0 0 0 0 1 0 1 5875 1 0 0 0 0 0 1 2125 0 0 0 0 0 1 1 6000 0 1 1 1 1 1 1 2250 0 0 0 0 0 0 OFF Datasheet 15 m n tel Electrical Specifications 16 Reserved Unused and TESTHI Signals All RESERVED lands must remain unconnected Connection of these lands to Vec Vss Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all RESERVED lands In a system level design on die termination has been included by the processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as GTL termination is provided on the processor silicon However see Table 7 for details o
12. Asserted De asserted STPCLK k SEDES Asserted STPCLK De asserted Extended HALT Snoop or HALT Snoop State BCLK running Service Snoops to cahces v Ea siiis a am State i p interrupts Snoop Event Serviced Service Snoops to cahces 6 2 1 Normal State This is the normal operating state for the processor 6 2 2 HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification The Extended HALT state is a lower power state as compared to the Stop Grant State If Extended HALT is not enabled the default Powerdown state entered will be HALT Refer to the sections below for details about the HALT and Extended HALT states 6 2 2 1 HALT Powerdown State 84 HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions When one of the processor cores executes the HALT instruction that processor core is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programm
13. DEFER DRDY DSTBN 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 TRDY A20M LINTO INTR LINT1 NMI IGNNE INIT PROCHOT PWRGOOD SMI STPCLK TCK TDI TMS TRST 2 NOTES 1 These signals also have hysteresis added to the reference voltage See Table 11 for more information 23 e n tel Electrical Specifications 2 6 2 CMOS and Open Drain Signals Legacy input signals such as A20M IGNNEZ INIT SMI and STPCLK use CMOS input buffers All of the CMOS and Open Drain signals are required to be asserted deasserted for at least four BCLKs for the processor to recognize the proper signal state See Section 2 6 3 for the DC specifications See Section 6 2 for additional timing requirements for entering and leaving the low power states 2 6 3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless otherwise stated All specifications apply to all frequencies and cache sizes unless otherwise stated Table 10 GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 10 GTLREF 0 10 V 2 3 Vin Input High Voltage GTLREF 0 10 Vaz 0 10 V 345 Vou Output High Voltage Vyr 0 10 Vat V 3 5 VTT MAX l Output Low Current N A u A RTT min 2 Ron_ min li Input Leakage Current N A 200 uA 6 Output Leakage 7 lto Current N A 2
14. In all cases the Thermal Monitor and Thermal Monitor 2 feature must be enabled for the processor to remain within specification Table 26 Processor Thermal Specifications Processor Core Thermal Extended 775_VR_ Minimun Maximum Number Frequency Design HALT Power CONFIG 05A T C Tc C Notes GHz Power W w B Guidance C 6 QX6850 3 00 130 37 See QX6800 2 93 130 37 dr 4 E Table 27 3 4 QX6700 2 66 130 50 T 5 ae See 06700 2 66 95 24 ZDN xg Table 29 3 4 IG 05A Figure 17 See 06600 2 40 105 50 IS VRBN Table 28 345 IG 05B Figure 16 See Q6600 2 40 95 24 8 Table 29 346 Figure 17 NOTES 1 Specification is at 50 C Tc and typical voltage loadline 2 775_VR_CONFIG_05B guidelines provide a design target for meeting future thermal requirements 3 Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum power that the processor can dissipate 4 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum Tc will vary depending on the TDP of the individual processor Refer to thermal profile figure and associated table for the allowed combinations of power and Tc 5 These processors have CPUID 06F7h 6 These processors have CPUID 06FBh 72 Datasheet Thermal Specifications and Design Considerations i
15. Power W Datasheet 75 n tel Thermal Specifications and Design Considerations 5 1 2 Figure 18 5 2 5 2 1 76 Thermal Metrology The maximum and minimum case temperatures Tc for the processor is specified in Table 26 This temperature specification is meant to help ensure proper operation of the processor Figure 18 illustrates where Intel recommends Tc thermal measurements should be made For detailed guidelines on temperature measurement methodology refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 Case Temperature Tc Measurement Location Measure To at this point geo metric center of the package 37 5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Therm
16. VCC MB REGULATION VSS SENSE VSS MB REGULATION DBR 2 VTT OUT LEFT VTT OUT RIGHT VIT SEL FCx PECI MSID 1 0 NOTES 1 Refer to Section 4 2 for signal descriptions 2 In processor systems where no debug port is implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 The value of these signals during the active to inactive edge of RESET defines the processor configuration options See Section 6 1 for details 4 PROCHOT signal type is open drain output and CMOS input Signal Characteristics Signals with Ry Signals with No Rrr RS 2 0 TRDY A20M BCLK 1 0 BSEL 2 0 A 35 3 ADS ADSTB 1 0 BNR BPRI COMP 8 3 0 IGNNE INIT ITP CLK 1 0 D 63 0 DBI 3 0 DBSY DEFER LINTO INTR LINT1 NMI PWRGOOD DRDY DSTBN 3 0 DSTBP 3 0 HIT RESET SMI STPCLK HITM LOCK PROCHOT REQ 4 0 TESTHI 13 11 10 7 0 VID 7 0 GTLREF 3 0 TCK TDI TMS TRST MSID 1 0 VTT SEL Open Drain Signals BPMb 3 0 BRO TDO FCx THERMTRIP FERR PBE IERR BPM 5 0 NOTES 1 Signals that do not have Ryp nor are actively driven to their high voltage level Signal Reference Voltages GTLREF Vu 2 BPM 5 0 BPMb 3 0 RESET BNR HIT HITM BRO A 35 0 ADS ADSTB 1 0 BPRI D 63 0 DBI 3 0 DBSY
17. to meet the expected load To insure compliance with the specifications various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors Datasheet 13 m n tel Electrical Specifications 14 FSB Decoupling The processor integrates signal termination on the die In addition some of the high frequency capacitance required for the FSB is included on the processor package However additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the motherboard for proper A GTL bus operation Voltage Identification The Voltage Identification VI D specification for the processor is defined by the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins see Chapter 2 5 3 for Vcc overshoot specifications Refer to Table 12 for the DC specifications for these signals Voltages for each processor frequency is provided in Table 4 Individual processor VID values may be calibrated during manufacturing such that two devices at the same co
18. uuu irna sas nme 20 2 Vee Overshoot Example Waveform sese nenne nene rne nnn 21 3 Differential Clock Waveform 0 cc ccc ccc nemen emnes nennen 29 4 Differential Clock Crosspoint Specification a mmm 30 5 Differential Measurements 0404400000000 K nennen nnn n nnn 30 6 Processor Package Assembly Sketch nee enemies 31 7 Processor Package Drawing Sheet 1 of 3 400000000 nemen 32 8 Processor Package Drawing Sheet 2 of 3 4444444000000 memes 33 9 Processor Package Drawing Sheet 3 of 3 sssssssssssssssssesenemeemene memes 34 10 Processor Top Side Markings Example for 1066 MHz Processors 36 11 Processor Top Side Markings Example for 1333 MHz Processors rr 37 12 Processor Land Coordinates and Quadrants Top View sssssseeee 38 13 land out Diagram Top View Left Side r r rr 40 14 land out Diagram Top View Right Side sss memes 41 15 Thermal Profile for 130 W Processors lt 4 4 44111 nnn nnn 73 16 Thermal Profile for 105 W Processors eee eee mmn nnne nn nnn 74 17 Thermal Profile 95 W Processors 000000000 nennen nennen nnn 75 18 Case Temperature TC Measurement Location nmm nns 76 19 Thermal Monitor 2 Frequency and Voltage Ordering nk 78 20 Conceptual Fan Control on PECI B
19. 59 5 8 44 7 36 49 8 64 54 9 92 59 9 10 45 1 38 50 1 66 55 2 94 60 3 12 45 5 40 50 5 68 55 4 96 60 6 14 45 7 42 50 9 70 55 9 98 60 9 16 46 1 44 51 2 72 56 3 100 61 3 18 46 4 46 51 6 74 56 7 102 61 7 20 46 9 48 51 9 76 57 0 104 62 0 22 47 3 50 52 3 78 57 4 105 62 2 24 47 6 52 52 7 80 57 7 26 48 0 54 53 0 82 58 1 Figure 16 Thermal Profile for 105 W Processors 74 Tcase C 65 0 60 0 m m o y 2 0 18x 48 3 50 0 40 0 n A OA SA S SA 9 9 9 9 r T 0 10 20 30 40 50 60 70 Power W 80 90 100 110 120 130 Datasheet m Thermal Specifications and Design Considerations n tel Table 29 Thermal Profile 95 W Processors Power Maximum Power Maximum Power Maximum Power Maximum W Tc C W Tc C W Tc C W Tc C 0 44 4 28 52 2 56 60 1 84 67 9 2 45 0 30 52 8 58 60 6 86 68 5 4 45 5 32 53 4 60 61 2 88 69 0 6 46 1 34 53 9 62 61 8 90 69 6 8 46 6 36 54 5 64 62 3 92 70 2 10 47 2 38 55 0 66 62 9 94 70 7 12 47 8 40 55 6 68 63 4 95 71 0 14 48 3 42 56 2 70 64 0 16 48 9 44 56 7 72 64 6 18 49 4 46 57 3 74 65 1 20 50 0 48 57 8 76 65 7 22 50 6 50 58 4 78 66 2 24 51 1 52 59 0 80 66 8 26 51 7 54 59 5 82 67 4 Figure 17 Thermal Profile 95 W Processors y7028x 444 60 0 Tcase C 55 0
20. 8 Icc max Specification is based on the Vcc max loadline Refer to Figure 1 for details 9 These Processors have CPUID 06FBh 10 The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT is the same as the maximum Icc for the processor HER i provided via a separate voltage source and not be connected to Vcc This specification is measured at the land 12 Baseboard bandwidth is limited to 20 MHz 13 This is maximum total current drawn from V plane by only the processor This specification does not include the current coming from R through the signal line Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total Iz drawn by the system This parameter is based on design characterization and is not tested Table 5 Vcc Static and Transient Tolerance Voltage Deviation from VID Setting V gt 3 4 Icc A Maximum Voltage Typical Voltage Minimum Voltage 1 30 mo 1 38 mo 1 45 mo 0 0 000 0 019 0 038 5 0 007 0 026 0 045 10 0 013 0 033 0 053 15 0 020 0 040 0 060 20 0 026 0 047 0 067 25 0 033 0 053 0 074 30 0 039 0 060 0 082 35 0 046 0 067 0 089 40 0 052 0 074 0 096 45 0 059 0 081 0 103 50 0 065 0 088 0 111 55 0 072 0 095 0 118 60 0 078 0 1
21. 8 V nS 5 5 ate T6 Slew Rate Matching N A N A 20 96 6 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor core frequencies 2 3 based on a 266 MHz BCLK 1 0 Duty Cycle High time Period must be between 40 and 60 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 Min period specification is based on 300 PPM deviation from a 3 75 ns period Max period specification is based on the summation of 300 PPM deviation from a 3 75 ns period and a 0 5 maximum variance due to spread spectrum clocking In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability Measurement taken from differential waveform Matching applies to rising edge rate for Clock and falling edge rate for Clock It is measured using a 75 mV window centered on the average cross point where Clock rising meets Clock falling The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations Datasheet Electrical Specifications n tel Table 19 FSB Differential Clock Specifications 1333 MHz FSB T Parameter Min Nom Max Unit Figure Notes BCL
22. AG3 Common Clock Input Output A10 U6 Source Synch Input Output BPMbO G1 Common Clock Input Output All T4 Source Synch Input Output BPMb1 C9 Common Clock Input Output Al2 U5 Source Synch Input Output BPMb2 G4 Common Clock Input Output A13 U4 Source Synch Input Output BPMb3 G3 Common Clock Input Output A14 V5 Source Synch Input Output BPRI G8 Common Clock Input A15 V4 Source Synch Input Output BRO F3 Common Clock Input Output A163 W5 Source Synch Input Output BSELO G29 Power Other Output Al7 AB6 Source Synch Input Output BSEL1 H30 Power Other Output A18 W6 Source Synch Input Output BSEL2 G30 Power Other Output A19 Y6 Source Synch Input Output COMPO A13 Power Other Input A20 Y4 Source Synch Input Output COMP1 T1 Power Other Input A21 AA4 Source Synch Input Output COMP2 G2 Power Other Input A224 AD6 Source Synch Input Output COMP3 R1 Power Other Input A23 AA5 Source Synch Input Output COMP8 B13 Power Other Input A24 AB5 Source Synch Input Output D0 B4 Source Synch Input Output A25 AC5 Source Synch Input Output D1 c5 Source Synch Input Output A263 AB4 Source Synch Input Output D2 A4 Source Synch Input Output A27 AF5 Source Synch Input Output D3 C6 Source Synch Input Output A28 AF4 Source Synch Input Output D4 A5 Source Synch Input Output A29 AG6 Source Synch Input Output D5 B6 Source Synch Input Output A30 AG4 Source Synch Input Output D6 B7 S
23. D 63 48 DBI3 DSTBN3 DSTBP 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe Input D 15 0 DBIO DSTBPO Output D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 DSTBP 3 0 FC signals are signals that are available for compatibility with other processors FCx Other FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note FERR PBE Output GTLREF 3 0 determine the signal reference level for GTL input GTLREF 3 0 Inp
24. GFOUpS otto ertet geek st koa las aer tan leek oe n fudit ce tab aayqa Monte de tag euis 22 8 Signal Characteristi6s iiie ce Sese ei Den E tes e Doer Fl metr ebbe Urs a Enid Rad Gee Mechel enue lepus 23 9 Signal Reference Voltages ssssssssssssssssssesenene teense nisi esa 23 10 GTL Signal Group DC Specifications ssssssssssssssee m mmm nennen 24 11 Open Drain and TAP Output Signal Group DC Specifications 24 12 CMOS Signal Group DC Specifications a rr mmm memes nenne 25 13 PECI DC Electrical LINUS lt aiU EUR ds nd REN eels mead ac bi k NR Teme dae 25 14 GTL Bus Voltage Definitions Ime emen K P K eene 26 15 Core Frequency to FSB Multiplier Configuration sess 26 16 BSEL 2 0 Frequency Table for BCLK 1 0 sss mmm 27 17 Front Side Bus Differential BCLK SpecificationsS r rr 28 18 FSB Differential Clock Specifications 1066 MHz FSB c lt lt lt csvv lt 28 19 FSB Differential Clock Specifications 1333 MHz FSB c lt c lt c lt z vrs 29 20 Processor Loading Specifications ccc n memes mememe sene emen nnne 35 21 Package Handling Guidelines sss eee K K K K KK KK KK 35 22 Processor Materl als eet u us asawa Ke nas t ela ees gala qu cni RR APER EIFE DENM Ese 36 23 Alphabetical Land AsSiQnMent cect eem enemies eene n nnn 42 24 Nu
25. OOOOOOOCOOQOOOOOO OOOOOOOOOQOOOOOO OOOOOOOOOQOOOOOO OOOOOOOOOQOOOOOO OOOOOOOOOQOOOOOO 0000000000000000 o0006999Q L 000000000 000000000 000000000 000000000 000000000 OO0000000 OOOOOOOOOQOOOOOOO0OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO oooo OOOO 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 000000000 le 660066000 000000000 000000000 000000000 000000000 900000000 0000 13 7 195 7 0 115 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO lk a asas 000000000 s 3 OOO0O000000 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOO 000 S OQO 1 5 MAX ALLOWABLE COMPONENT HEIGHT BOTTOM VIEW SIDE VIEW TOP VIEW REV C88285 DO NOT SCALE DRAWING fuEer 3 or 3 6 SIE DRAWING NUNBER 2200 MISSION COLLEGE BLVD P O BOX 581 SANTA CLARA cone intel DEPARTMENT ATD 34 Datasheet Package Mechanical Specifications 3 2 3 3 Table 20 3 4 Table 21 Datasheet intel Processor Component Keep Out Zones
26. Other AG4 A30 Source Synch Input Output AH13 VSS Power Other AG5 A31 Source Synch Input Output AH14 VCC Power Other AG6 A29 Source Synch Input Output AH15 VCC Power Other AG7 VSS Power Other AH16 VSS Power Other AG8 VCC Power Other AH17 VSS Power Other AG9 VCC Power Other AH18 VCC Power Other AG10 VSS Power Other AH19 VCC Power Other AG11 VCC Power Other AH20 VSS Power Other AG12 VCC Power Other AH21 VCC Power Other AG13 VSS Power Other AH22 VCC Power Other AG14 VCC Power Other AH23 VSS Power Other AG15 VCC Power Other AH24 VSS Power Other AG16 VSS Power Other AH25 VCC Power Other AG17 VSS Power Other AH26 VCC Power Other AG18 VCC Power Other AH27 VCC Power Other AG19 VCC Power Other AH28 VCC Power Other AG20 VSS Power Other AH29 VCC Power Other Datasheet 59 60 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction bene Land Name Signal Buffer Direction Type Type AH30 VCC Power Other AK9 VCC Power Other AJ1 BPM1 Common Clock Input Output AK10 VSS Power Other AJ2 BPMO Common Clock Input Output AK11 VCC Power Other AJ3 ITP CLK1 TAP Input AK12 VCC Power Other AJ4 VSS Power Other AK13 VSS Power Other AJ5 A34 Source Synch Input Output AK14 VCC Power Other AJ6 A35 Sour
27. Other W2 TDI_M Power Other Input AA23 VSS Power Other W3 TESTHI1 Power Other Input AA24 VSS Power Other WA VSS Power Other AA25 VSS Power Other W5 Al64 Source Synch Input Output F 2 s AA26 VSS Power Other W6 A18 Source Synch Input Output AA27 VSS Power Other W7 VSS Power Other AA28 VSS Power Other ws VCC Power Other AA29 VSS Power Other W23 VCC Power Other AA30 VSS Power Other W24 VCC Power Other AB1 VSS Power Other W25 VCC Power Other AB2 ERR Asynch CMOS Output W26 VCC Power Other AB3 FC37 Power Other W27 VCC Power Other AB4 A26 Source Synch Input Output W28 VEC Power Other AB5 A24 Source Synch Input Output W29 VCC Power Other AB6 A175 Source Synch Input Output W30 VCC Power Other AB7 VSS Power Other Y1 FCO Power Other AB8 VCC Power Other Y2 VSS Power Other AB23 VSS Power Other Y3 FC17 Power Other AB24 VSS Power Other Y4 A20 Source Synch Input Output p n o u l AB25 VSS Power Other 57 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction tand Land Name Signal Buffer Direction Type Type AB26 VSS Power Other AE3 FC18 Power Other AB27 VSS Power Other AE4 RESERVED AB28 VSS Power Other AE5 VSS Power Other AB29 VSS Power Other AE6 RESERV
28. Power Other VCC AG9 Power Other VCC AD29 Power Other VCC AH11 Power Other VCC AD30 Power Other VCC AH12 Power Other VCC AD8 Power Other VCC AH14 Power Other VCC AE11 Power Other VCC AH15 Power Other VCC AE12 Power Other VCC AH18 Power Other VCC AE14 Power Other VCC AH19 Power Other VCC AE15 Power Other VCC AH21 Power Other VCC AE18 Power Other VCC AH22 Power Other VCC AE19 Power Other VCC AH25 Power Other VCC AE21 Power Other VCC AH26 Power Other VCC AE22 Power Other VCC AH27 Power Other VCC AE23 Power Other VCC AH28 Power Other VCC AE9 Power Other VCC AH29 Power Other VCC AF11 Power Other VCC AH30 Power Other VCC AF12 Power Other VCC AH8 Power Other VCC AF14 Power Other VCC AH9 Power Other VCC AF15 Power Other VCC AJ11 Power Other VCC AF18 Power Other VCC AJ12 Power Other VCC AF19 Power Other VCC AJ14 Power Other VCC AF21 Power Other VCC AJ15 Power Other 45 46 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name E signe duos Direction Land Name z Eust aed Direction VCC AJ18 Power Other VCC AM19 Power Other VCC AJ19 Power Other VCC AM21 Power Other VCC AJ21 Power Other VCC AM22 Power Other VCC AJ22 Power Other VCC A
29. RESERVED E23 FC37 AB3 Power Other RESERVED E6 FC39 AA2 Power Other RESERVED E7 FC4 T2 Power Other RESERVED F23 FC40 AM6 Power Other RESERVED F29 FC8 AK6 Power Other RESERVED G6 FERR PBE R3 Asynch CMOS Output RESERVED N4 GTLREFO H1 Power Other Input RESERVED N5 GTLREF1 H2 Power Other Input RESERVED P5 GTLREF2 G10 Power Other Input RESERVED v2 GTLREF3 F2 Power Other Input RESET G23 Common Clock Input HIT D4 Common Clock nput Output RSO B3 Common Clock Input HITM E4 Common Clock Input Output RS1 F5 Common Clock Input IERR AB2 Asynch CMOS Output RS2 A3 Common Clock Input IGNNE N2 Asynch CMOS Input SKTOCC AE8 Power Other Output INIT P3 Asynch CMOS Input SMI P2 Asynch CMOS Input ITP_CLK0 AK3 TAP Input STPCLK M3 Asynch CMOS Input ITP_CLK1 AJ3 TAP Input TCK AE1 TAP Input LINTO K1 Asynch CMOS Input TDI AD1 TAP Input LINT1 L1 Asynch CMOS Input TDI M W2 Power Other Input LOCK C3 Common Clock Input Output TDO AF1 TAP Output MSID0 W1 Power Other Output TDO_M U1 TAP Output MSID1 V1 Power Other Output TESTHIO F26 Power Other Input PECI G5 Power Other Input Output TESTHI 1 W3 Power Other Input PROCHOT AL2 Asynch CMOS Input Output TESTHI10 H5 Power Other Input PWRGOOD N1 Power Other Input TESTHI 11 P1 Power Other Input REQO K4 Source Synch Input Output TESTHI13 L2 Power Other Input REQ1 J5 Source Synch Input Output TESTHI2 F25 Power Other Input REQ2 M6 Source Synch Input Output TESTHI3 G25 Power Othe
30. Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 30 N A N A V 3 2 VH Input High Voltage WA N A 1 15 V 3 VcRoss abs Absolute Crossing Point 0 300 N A 0 550 V i 3 4 5 AVcnoss Range of Crossing Points N A N A 0 140 V 3 4 Vos Overshoot N A N A 1 4 V 3 8 Vus Undershoot 0 300 N A N A V 6 VswING Differential Output Swing 0 300 N A N A V NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Steady state voltage not including overshoot or undershoot 3 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1 4 The crossing point must meet the absolute and relative crossing point specifications simultaneously 5 VHavg iS the statistical average of the Vy measured by the oscilloscope 6 Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage 7 Measurement taken from differential waveform FSB Differential Clock Specifications 1066 MHz FSB 28 T Parameter Min Nom Max Unit Figure Notes BCLK 1 0 Frequency 265 307 266 746 MHz 2 T1 BCLK 1 0 Period 3 74963 3 76922 ns 3 3 T2 BCLK 1 0 Period Stability 150 ps 4 T5 E 0 Rise and Fall Slew 2 5 u
31. The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 7 and Figure 8 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 20 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution The minimum loading specification must be maintained by any thermal and mechanical solutions Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N 17 Ibf 311 N 70 Ibf L2 3 Dynamic 756 N 170 Ibf 13 4 NOTES 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified loa
32. VSS V6 Power Other VSS V7 Power Other 51 52 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction tand Land Name Signal Buffer Direction Type Type A2 VSS Power Other B11 VSS Power Other A3 RS2 Common Clock Input B12 D13 Source Synch Input Output A4 D02 Source Synch Input Output B13 COMP8 Power Other Input A5 DO4 Source Synch Input Output B14 VSS Power Other A6 VSS Power Other B15 D53 Source Synch Input Output A7 D07 Source Synch Input Output B16 D55 Source Synch Input Output A8 DBI0 Source Synch Input Output B17 VSS Power Other A9 VSS Power Other B18 D57 Source Synch Input Output A10 D08 Source Synch Input Output B19 D60 Source Synch Input Output All D09 Source Synch Input Output B20 VSS Power Other A12 VSS Power Other B21 D59 Source Synch Input Output A13 COMPO Power Other Input B22 D63 Source Synch Input Output A14 D50 Source Synch Input Output B23 VSSA Power Other A15 vss Power Other B24 vss Power Other A16 DSTBN3 Source Synch Input Output B25 VTT Power Other A17 D56 Source Synch Input Output B26 VTT Power Other A18 vss Power Other B27 VTT Power Other A19 D61 Source Synch Input Out
33. Voltage 0 90 Vz Vr 0 10 V 3 5 6 loL Output Low Current 1 70 4 70 mA gl lon Output High Current 1 70 4 70 mA gt lu Input Leakage Current N A 100 uA 8 lio Output Leakage Current N A 100 HA i NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 The V4 referred to in these specifications refers to instantaneous Vr 4 Viu is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Vy and Vor may experience excursions above Vr 6 All outputs are open drain 7 lo is measured at 0 10 Vr lop is measured at 0 90 Vr 8 Leakage to Vss with land held at Vz 9 Leakage to Vy with land held at 300 mV Table 13 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 30 VTT Vhysteresis Hysteresis 0 1 VTT V 3 Vn Negative edge threshold voltage 0 275 VTT 0 500 VTT V Vp Positive edge threshold voltage 0 550 Vr 0 725 VTT V High level output source s urce i P 6 0 N A mA VoH 0 75 VT Low level output sink lsi 0 5 1 0 mA sink VoL 0 25 Vy lleak High impedance state leakage to VT N A 50 uA 2 lleak High impedance leakage to GND N A 10 uA 2 Opus Bus capacitance 10 pF Vnoise Signal noise i
34. and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 19 for an illustration of this ordering 77 n tel Thermal Specifications and Design Considerations Figure 19 5 2 3 78 Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode The Thermal Monitor TCC however can be activated through the use of the on demand mode On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is refe
35. is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is de asserted This signal must connect the appropriate pins lands on all processor FSB agents Datasheet Land Listing and Signal Descriptions n tel Table 25 Signal Description Sheet 4 of 9 Name Type Description DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is DEFER Input normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins lands of all processor FSB agents DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common DRDY 3 TRU clock data transfer DRDY may be de asserted to insert idle clocks Output pe This signal must connect the appropriate pins lands of all processor FSB agents DSTBN 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe Input D 15 0 DBIO DSTBN0 PSTBNIS 01 output D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2
36. motherboard requirements for 4 wire based fan speed control refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 The Internal chassis temperature should be kept below 39 C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the fan for the boxed processor See Table 32 for specific requirements Fan Speed Control Operation Intel Core 2 Quad processor If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figure 30 and Table 33 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature sh
37. provides improved Extreme Quad Core Processor QX6850 only cache hit rate on load store operations 775 land Package The Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 quad processor Q6000 sequence deliver Intel s advanced powerful processors for desktop PCs The processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance These applications include Internet audio and streaming video image processing video content creation speech 3D CAD games multimedia and multitasking user environments Intel 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture The processor supporting Enhanced Intel Speedstep technology allows tradeoffs to be made between performance and power consumption The Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 quad processor Q6000 sequence also include the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable The Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 quad processor Q6000 sequence support Intel Virtualization Technology Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to impr
38. remain in the lower bus ratio and VID operating point of the Extended HALT state While in the Extended HALT Snoop State snoops are handled the same way as in the HALT Snoop State After the snoop is serviced the processor will return to the Extended HALT state ss Datasheet m Boxed Processor Specifications n tel 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Figure 22 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 F
39. to be generated from Vy by a voltage divider of 1 resistors one divider for each GTLEREF land Refer to the applicable platform design guide for implementation details 3 Ry is the on die termination resistance measured at V31 3 of the GTL output driver 4 COMP resistance must be provided on the system board with 196 resistors COMP 3 0 and COMPS resistors are to Vss Clock Specifications Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor s core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing The processor uses a differential clocking implementation For more information on the processor clocking contact your Intel field representative Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency Core Frequency Core Frequency to FSB 266 MHz BCLK 333 MHz BCLK Notes 2 Frequency 1066 MHz FSB 1333 MHz FSB 1 6 1 60 GHz 2 00 GHz 1 7 1 87 GHz 2 33 GHz 1 8 2 13 GHz 2 66 GHz 1 9 2 40 GHz 3 00 GHz 1 10 2 66 GHz 3 33 GHz 1 11 2 93 GHz 3 66 GHz 1 12 3 20 GHz 4 00 GHz NOTES 1 Individual processors operate only at or below the rated frequency 2 Listed frequencies are not necessarily committed produc
40. 00 uA RoN Buffer On Resistance 10 13 Q NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 The Vy referred to in these specifications is the instantaneous Vy 4 Vig is defined as the voltage range at a receiving agent that will be interpreted as a logical high value Vin and Vor may experience excursions above VTT Leakage to Vss with land held at Vy Leakage to Vr with land held at 300 mV KO Table 11 Open Drain and TAP Output Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VoL Output Low Voltage 0 0 20 V Vou Output High Voltage Vm 0 05 Vi 0 05 V 2 lo Output Low Current 16 50 mA i lio Output Leakage Current N A 200 uA E NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Voy is determined by the value of the external pull up resister to Vy 3 Measured at V7 0 2 4 For Vin between 0 and Vor 24 Datasheet Electrical Specifications Table 12 CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 10 Vr 0 30 V 2 3 Vin Input High Voltage Vy 0 70 Vrr 0 10 V 345 VoL Output Low Voltage 0 10 Vr 0 10 V 3 Vou Output High
41. 0009 OOOOOOOOOOOOOOO 0O000000000000000Q0 O0000000000000004000000000000000 O00000000000000040000000000000000 O00000000000000000000000000000000 O0000000000000004000000000000000 OO000000000000000000000000000000 O00000000000000000000000000000009 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO 000000900 OOOOOOOOQ 00000000 9090909009 00000000 00000000 00000000 000000000 000000000 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO t OOOOOOOOQ OOOOOOOO 090000006 OOOOOOOO OOOOOOOO OOOOOOOO O00000000 O00000000000000000000000000000009 OO0000000000000000000000000000000 OOOOO000000000000 OOBO000000000000 O0000000000000000000000000000000 O0000000000000000000000000000000 O000000000000000 0000000000000000 OO00000000000000400000000000000G871 BOTTOM VIEW O00000000 GG900090 GOoe 90 IP i 5 t T o iu c I L5 SECTION E E G 8 I IHS LID TOP VIEW c IHS LID L7 0 05 o 203 4 c 0 203 Z 0 08 Z IHS SEALANT PACKAGE SUBSTRATE j x j I DETAIL A SCALE 15 1 2200 MISSION COLLEGE BLVD P O BOX 58119 CORP in
42. 02 0 125 65 0 085 0 108 0 132 70 0 091 0 115 0 140 75 0 098 0 122 0 147 78 0 101 0 126 0 151 85 0 111 0 136 0 161 90 0 117 0 143 0 169 95 0 124 0 150 0 176 100 0 130 0 157 0 183 105 0 137 0 163 0 190 110 0 143 0 170 0 198 115 0 150 0 177 0 205 120 0 156 0 184 0 212 125 0 163 0 191 0 219 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 5 3 2 This table is intended to aid in reading discrete points on Figure 1 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details 4 Adherence to this loadline specification is required to ensure reliable processor operation Datasheet 19 intel Figure 1 Electrical Specifications Vcc Static and Transient Tolerance Vcc V lt lt lt S S S lt S S S S S S S S S S SS U U U U U U U U U U U U U U U U U U U Icc A 0 10 20 30 40 50 60 70 80 90 100 110 120 0 000 i i i i i i i i i 0 013 4 0 025 4 0 038 Vcc Maximum 0 050 4 0 063 4 0 075 4 0 088 4 0 100 4 diia Vcc Typical 0 125 4 0 138 P 0
43. 10 FC35 vss GTLREF1 GTLREF0 D29 D27 DSTBN1 DBI1 wr D16 BPRI DEFER RSVD PECI BPMb2 BPMb3 COMP2 BPMb0 D28 VSS D24 D23 vss D18 D17 vss FC21 RS1 vss BR0 GTLREF3 VSS D26 DSTBP1 VSS D21 D19 VSS RSVD RSVD FC20 HITM TRDY vss RSVD D25 VSS D15 D22 vss D12 D20 VSS VSS HIT VSS ADS RSVD D52 VSS D14 D114 VSS BPMb1 DSTBNO VSS D34 Di VSS LOCK BNR DRDY vss comps D13 vss Dio psrBPos vss D64 D54 vss D0 Rso DBSY vss pso COMPO vss pes pe amp vss pBo D74 vss D4 D2 RS2 vss 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Datasheet AN AM AL AK AJ AH AG AF AE AD AC 5 A C lt lt v o Um m 41 42 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name e No eee Direction Land Name Buses vd Direction A3 L5 Source Synch Input Output BNR C2 Common Clock Input Output A4 P6 Source Synch Input Output BPM0 AJ2 Common Clock Input Output A5 M5 Source Synch Input Output BPM1 AJ1 Common Clock Input Output A6 L4 Source Synch Input Output BPM2 AD2 Common Clock Input Output A7 M4 Source Synch Input Output BPM3 AG2 Common Clock Input Output A8 R4 Source Synch Input Output BPM4 AF2 Common Clock Input Output A9 T5 Source Synch Input Output BPM5
44. 11 4 12 12 6 V IC Maximum fan steady state current draw 1 2 A Average fan steady state current draw 0 5 A Maximum fan start up current draw 2 2 A Fan start up current draw maximum 1 0 Second duration pulses per SENSE SENSE frequency 2 fan 1 revolution CONTROL 21 25 28 Hz 23 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor 2 Open drain type pulse width modulated 3 Fan will have pull up resistor to 4 75 V maximum of 5 25 V Datasheet 91 intel Figure 27 7 3 7 3 1 92 Boxed Processor Specifications Baseboard Power Header Placement Relative to Processor Socket Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is in Chapter 5 The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 26 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Air
45. 150 4 Vcc Minimum 0 163 4 0 175 4 0 188 4 0 200 4 0 213 4 0 225 4 20 NOTES 1 2 3 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 5 3 This loadline specification shows the deviation from the VID set point The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details Datasheet m Electrical Specifications n tel 2 5 3 Table 6 Figure 2 2 5 4 Datasheet Vcc Overshoot The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos max Tos max is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS SENSE lands Vcc Overshoot Specifications Symbol Parameter Min Max Unit Figure Notes Vos Max Magnitude of Vcc ov
46. 2 1 5 3 2 2 5 3 2 3 5 3 2 4 Table 30 Datasheet PECI Specifications PECI Device Address The socket 0 PECI register resides at address 30h and socket 1 resides at 31h Note that each address also supports two domains Domain 0 and Domain 1 For more information on PECI domains refer to the Platform Environment Control Interface Specification PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification Refer to this document for details on supported PECI command function and codes PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is known to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not ensured to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal c
47. 5 VSS Power Other J19 VCC Power Other L26 VSS Power Other J20 VCC Power Other L27 VSS Power Other J21 VCC Power Other L28 VSS Power Other J22 VCC Power Other L29 VSS Power Other J23 VCC Power Other L30 VSS Power Other J24 VCC Power Other M1 VSS Power Other J25 VCC Power Other M2 THERMTRIP Asynch CMOS Output J26 VCC Power Other M3 STPCLK Asynch CMOS Input J27 VCC Power Other M4 AO7 Source Synch Input Output J28 VCC Power Other M5 A05 Source Synch Input Output J29 VCC Power Other M6 REQ2 Source Synch Input Output J30 VCC Power Other M7 VSS Power Other K1 LI NTO Asynch CMOS Input M8 VCC Power Other K2 VSS Power Other M23 VCC Power Other K3 A20M Asynch CMOS Input M24 VCC Power Other K4 REQO Source Synch Input Output M25 VCC Power Other K5 vss Power Other M26 VCC Power Other K6 REQ3 Source Synch Input Output M27 VCC Power Other K7 VSS Power Other M28 VCC Power Other K8 VCC Power Other M29 VCC Power Other 55 56 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Land Land Name Signal Buffer Direction Type Type M30 VCC Power Other R7 VSS Power Other N1 PWRGOOD Power Other Input R8 VCC Power Other N2 IGNNE Asynch CMOS Input R23 VSS Power Other N3 VSS Power Other R24 VSS Power Oth
48. 800 August 2007 Datasheet Intel Core 2 Extreme Quad Core Processor QX6000 and Intel Core 2 Quad Processor Q6000 Sequence Features Available at 3 00 GHz Intel Core 2 Binary compatible with applications running Extreme Quad Core Processor QX6850 only on previous members of the Intel Available at 2 66 GHz Intel Core 2 microprocessor line Extreme Quad Core Processor QX6700 and Intel Core 2 Quad Processor Q6700 only Available at 2 40 GHz Intel Core 2 Quad Enhanced branch prediction od Q6600 only o Optimized for 32 bit applications running on Available at 2 93 GHz Intel Core 2 advanced 32 bit operating systems Extreme Quad Core Processor QX6800 only Advance Dynamic Execution Very deep out of order execution Four 32 KB Level 1 data caches amp Enhanced Intel Speedstep Technology Two 4 MB Level 2 caches Intel Advanced Digital Media Boost Supports Intel Virtualization Technology Enhanced floating point and multimedia unit Supports Execute Disable Bit capability for enhanced video audio encryption and s 3D performance e FSB frequency at 1066 MHz Intel Core 2 Extreme Quad Core Processor QX6700 Power Management capabilities QX6800 and Intel Core 2 Quad Processor System Management mode Supports Intel 64 architecture Q6700 and Q6600 only Multiple low power states e FSB frequency at 1333 MHz Intel Core 2 8 way cache associativity
49. Assignment Assignment E Land Name Direction E Land Name m Direction C20 DBI 3 Source Synch Input Output D29 VIT Power Other C21 D58 Source Synch Input Output D30 VIT Power Other C22 VSS Power Other E2 VSS Power Other C23 VCCIOPLL Power Other E3 TRDY Common Clock Input C24 VSS Power Other E4 HITM Common Clock Input Output C25 VIT Power Other E5 FC20 Power Other C26 VTT Power Other E6 RESERVED C27 VTT Power Other E7 RESERVED C28 VIT Power Other E8 VSS Power Other C29 VIT Power Other E9 D19 Source Synch Input Output C30 VIT Power Other E10 D21 Source Synch Input Output D1 RESERVED Ell vss Power Other D2 ADS Common Clock Input Output E12 DSTBP1 Source Synch Input Output D3 VSS Power Other E13 D26 Source Synch Input Output D4 HIT Common Clock Input Output E14 VSS Power Other D5 VSS Power Other E15 D33 Source Synch Input Output D6 VSS Power Other E16 D34 Source Synch Input Output D7 D20 Source Synch Input Output E17 VSS Power Other D8 D12 Source Synch Input Output E18 D39 Source Synch Input Output D9 VSS Power Other E19 D40 Source Synch Input Output D10 D22 Source Synch Input Output E20 VSS Power Other D11 D15 Source Synch Input Output E21 D42 Source Synch Input Output D12 VSS Power Other E22 D45 Source Synch Input Output D13 D25 Source Synch Input Output E23 RESERVED D14 RESERVED E24 FC10 Power Other D15 vss Power Other E25 vss Power Other D16 RESERVED E26 VSS Power Other D17 D49
50. Decouiplingi i eor ere ti eren reno e err TAE PANET RE PEE eM la ee aer 14 2 3 Voltage dentificatioli ciere ea emet e png nnd ek amp ERR Ra ep d na gum 14 2 4 Reserved Unused and TESTHI Signals rr mns 16 2 5 Voltage and Current Specification ccc enne memes 17 2 5 1 Absolute Maximum and Minimum Ratings r Hee 17 2 5 2 DC Voltage and Current Specification rr 18 2 5 3 VOC OVershODE esos ete etitm xke RRRE PA REPRE k kin d ab okn ka EVE ANE ene 21 2 5 4 Die Voltage Validation rr emen memes 21 2 6 Signaling Specifications eite bez nb vad ex bark t exu PARARE HU K akaw UAE FRE E KA Nur bi Ke 22 2 6 1 FSB Signal Groups uuu l u Kask o bobo a Raka n m RGNMPKTRRNEEPIrEM KDE d 22 2 6 2 CMOS and Open Drain Signals srra aaa n nn 24 2 6 3 Processor DC Specifications nrnna 24 2 6 3 1 GTL Front Side Bus Specifications 26 2 Clock Specifications certet reda nn br eer b tr bed rebns rer dis etii nagd 26 2 7 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking 26 2 7 2 FSB Frequency Select Signals BSEL 2 0 seem 27 2 7 3 Phase Lock Loop PLL and Filter r 27 2 7 4 BCLK 1 0 Specifications sssssssesseen nmm nnns 28 3 Package Mechanical Specifications sss 31 3 1 Package Mechanical Drawing
51. Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate Larger bulk storage Cgyj y such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4 Failure to do so can result in timing violations or reduced lifetime of the component 2 2 1 Vcc Decoupling Vcc regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load current In addition ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity Consult the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket 2 2 2 V11 Decoupling Decoupling must be provided on the motherboard Decoupling solutions must be sized
52. ED AB30 VSS Power Other AE7 vss C AC1 TMS TAP Input AE8 SKTOCC Power Other Output AC2 DBR Power Other Output AE9 VCC Power Other AC3 VSS Power Other AE10 VSS Power Other ACA RESERVED AE11 VCC Power Other AC5 A25 Source Synch Input Output AE12 WCC Power Other AC6 VSS Power Other AE13 VSS Power Other AC7 VSS Power Other AE14 VCC Power Other AC8 VCC Power Other AE15 VCC Power Other AC23 VCC Power Other AE16 VSS Power Other AC24 VCC Power Other AE17 VSS Power Other AC25 VCC Power Other AE18 VCC Power Other AC26 VCC Power Other AE19 VCC Power Other AC27 VCC Power Other AE20 VSS Power Other AC28 VCC Power Other AE21 VCC Power Other AC29 VCC Power Other AE22 VCC Power Other AC30 VCC Power Other AE23 VCC Power Other AD1 TDI TAP Input AE24 VSS Power Other AD2 BPM2 Common Clock Input Output AE25 vss Power Other AD3 FC36 Power Other AE26 VSS Power Other AD4 VSS Power Other AE27 VSS Power Other AD5 ADSTB1 Source Synch Input Output AE28 VSS Power Other AD6 A22 Source Synch Input Output AE29 VSS Power Other AD7 VSS Power Other AE30 VSS Power Other AD8 VCC Power Other AF1 TDO TAP Output AD23 VCC Power Other AF2 BPM4 Common Clock Input Output AD24 VCC Power Other AF3 VSS Power Other AD25 VCC Power Other AF4 A28 Source Synch Input Output AD26 VCC Power Other AF5 A27 Source Synch Input Output AD27 VCC Power Other AF6 VSS Power Other AD28 VCC Power Other AF7 VSS Power Other AD29 VCC Power O
53. Ex E k taki asc 77 5 2 3 On Demand Mode op aaa iska RPRRRA EIER REIR RU yayawa 78 5 2 4 PROCHOT Signal nnm nennen nenne nennen nn nn nnn nnn 79 Datasheet 3 ntel 52 5 THERMTITRIP3 Sigti l uu y u dite db t zad RI RR PUER MER MIS bee eee 79 5 3 Platform Environment Control Interface PECI rr 80 BS introductions sions epic er Dux ER EOM ERU UN SERERE uska swaqaqususpaququ 80 5 3 1 1 TcoNTnRoL and TCC Activation on PECI Based Systems 80 5 3 2 PEGI Speolficablons s ERI eene Pozo ces blade da eripe aaa vk rad d rete D Rd ee 81 5 3 2 1 PECI Device Address ssssssssssssssssssssssenemenee memes ense 81 5 3 2 2 PECI Command Support uu aasan enm dose cies erre Rt rd 81 5 3 2 3 PECI Fault Handling ReguireMents eee 81 5 3 2 4 PECI GetTemp0 and GetTemp1 Error Code Support 81 Features ccr 83 6 1 Power On Configuration Options r emen sese emen nnns 83 6 2 Clock Control and Low Power States r rr nemen emen nnn 83 62 1 Normal State smoren edu exte teenies E Kee iced cxepenpin bic uama akana ee ma 84 6 2 2 HALT and Extended HALT Powerdown States eee 84 6 2 2 1 HALT Powerdown State aaa aasasasnasawaaqunaqaqsqakayaniayasquqa 84 6 2 2 2 Extended HALT Powerdown State rr 85 6 2 3 Stop Grant State ws ccs eee eene one fare Dna e REX RR LER e REEL ERE FAR RERO Keg lac 85 6 2 4 Exte
54. G28 BCLK1 Clock Input F19 VSS Power Other G29 BSELO Power Other Output F20 D41 Source Synch Input Output G30 BSEL2 Power Other Output F21 D43 Source Synch Input Output H1 GTLREFO Power Other Input F22 VSS Power Other H2 GTLREF1 Power Other Input F23 RESERVED H3 vss Power Other F24 TESTHI 7 Power Other Input H4 FC35 Power Other F25 TESTHI2 Power Other Input H5 TESTHI10 Power Other Input F26 TESTHIO Power Other Input H6 VSS Power Other F27 VIT SEL Power Other Output H7 VSS Power Other F28 BCLKO Clock Input H8 VSS Power Other F29 RESERVED H9 vss Power Other G1 BPMb0 Common Clock Input Output H10 vss Power Other G2 COMP2 Power Other Input H11 vss Power Other G3 BPMb3 Common Clock Input Output H12 vss Power Other G4 BPMb2 Common Clock Input Output H13 vss Power Other G5 PECI Power Other Input Output H14 vss Power Other G6 RESERVED H15 FC32 Power Other G7 DEFER Common Clock Input H16 FC33 Power Other G8 BPRI Common Clock Input H17 vss Power Other G9 D16 Source Synch Input Output H18 vss Power Other G10 GTLREF2 Power Other Input H19 VSS Power Other G11 DBI1 Source Synch Input Output H20 VSS Power Other G12 DSTBN1 Source Synch Input Output H21 vss Power Other G13 D27 Source Synch Input Output H22 VSS Power Other G14 D29 Source Synch Input Output H23 VSS Power Other G15 D31 Source Synch Input Output H24 VSS Power Other G16 D32 Source Synch Input Output H25 VSS Power Other G17 D36 Source
55. Intel Core 2 Extreme Quad Core Processor QX6000 Sequence and Intel Core 2 Quad Processor Q6000 Sequence Datasheet on 65 nm Process in the 775 land LGA Package supporting 2 Intel 64 architecture and Intel virtualization Technology August 2007 Document Number 315592 005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLI ED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 quad processor Q6000 sequence
56. J25 Power Other VCC AM15 Power Other VCC J26 Power Other VCC AM18 Power Other VCC 127 Power Other Datasheet Land Listing and Signal Descriptions intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name s Beo ns Direction Land Name cw bittet ione Direction VCC J28 Power Other VCC T27 Power Other VCC J29 Power Other VCC T28 Power Other VCC J30 Power Other VCC T29 Power Other VCC J8 Power Other VCC T30 Power Other VCC J9 Power Other VCC T8 Power Other VCC K23 Power Other VCC U23 Power Other VCC K24 Power Other VCC U24 Power Other VCC K25 Power Other VCC U25 Power Other VCC K26 Power Other VCC U26 Power Other VCC K27 Power Other VCC U27 Power Other VCC K28 Power Other VCC U28 Power Other VCC K29 Power Other VCC U29 Power Other VCC K30 Power Other VCC U30 Power Other VCC K8 Power Other VCC U8 Power Other VCC L8 Power Other VCC V8 Power Other VCC M23 Power Other VCC W23 Power Other VCC M24 Power Other VCC W24 Power Other VCC M25 Power Other VCC W25 Power Other VCC M26 Power Other VCC W26 Power Other VCC M27 Power Other VCC W27 Power Other VCC M28 Power Other VCC W28 Power Other VCC M29 Power Other VCC W29 Power Other VCC M30 Power Other VCC W30 Power Other VCC M8 Power Other VCC w8 Power Oth
57. K 1 0 Frequency 331 635 333 364 MHz 2 T1 BCLK 1 0 Period 2 99972 3 01536 ns 3 3 T2 BCLK 1 0 Period Stability 150 ps 3 Apo T5 BCLK 1 0 Rise and Fall Slew Rate 2 5 8 V nS 5 T6 Slew Rate Matching N A N A 20 96 i NOTES 1 Unless otherwise noted all specifications in this table apply to all processor core frequencies based on a 333 MHz BCLK 1 0 2 Duty Cycle High time Period must be between 40 and 60 3 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 Min period specification is based on 300 PPM deviation from a 3 ns period Max period specification is based on the summation of 300 PPM deviation from a 3 ns period and a 40 596 maximum variance due to spread spectrum clocking 4 For the clock jitter specification refer to the CK505 Clock Synthesizer Driver Specification 5 Inthis context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 6 Measurement taken from differential waveform 7 Matching applies to rising edge rate for Clock and falling edge rate for Clocks It is measured using a 75 mV window centered on the average cross point where Clock rising meets Clock falling The median cross point is used to calculate the voltage thr
58. M11 VCC Power Other AN19 VCC Power Other AM2 vec Power other fanzo vss Power Other AM13 vss Power Other AN21 VCC Power Other AM14 VCC Power Other AN22 VCC Power Other AM15 VCC Power Other AN23 VSS Power Other AM16 vss Power Other AN24 vss Power Other AM17 VSS Power Other AN25 VCC Power Other AM18 vec Power Other AN26 VCC Power Other AM19 VCC Power Other AN27 VSS Power Other AM20 VSS Power Other AN28 vss Power Other AM21 VCC Power Other AN29 VCC Power Other AM22 VCC Power Other AN30 VCC Power Other AM23 VSS Power Other AM24 VSS Power Other AM25 VCC Power Other AM26 VCC Power Other Datasheet 61 intel Land Listing and Signal Descriptions 4 2 Alphabetical Signals Reference Table 25 Signal Description Sheet 1 of 9 Name Type Description A 35 3 Input Output A 35 3 Address define a 238 pyte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins lands of all agents on the processor FSB A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 signals to determine power on configuration See Section 6 1 for more details A20M Input If A20M Addr
59. M25 Power Other VCC AJ25 Power Other VCC AM26 Power Other VCC AJ26 Power Other VCC AM29 Power Other VCC AJ8 Power Other VCC AM30 Power Other VCC AJ9 Power Other VCC AM8 Power Other VCC AK11 Power Other VCC AM9 Power Other VCC AK12 Power Other VCC AN11 Power Other VCC AK14 Power Other VCC AN12 Power Other VCC AK15 Power Other VCC AN14 Power Other VCC AK18 Power Other VCC AN15 Power Other VCC AK19 Power Other VCC AN18 Power Other VCC AK21 Power Other VCC AN19 Power Other VCC AK22 Power Other VCC AN21 Power Other VCC AK25 Power Other VCC AN22 Power Other VCC AK26 Power Other VCC AN25 Power Other VCC AK8 Power Other VCC AN26 Power Other VCC AK9 Power Other VCC AN29 Power Other VCC AL11 Power Other VCC AN30 Power Other VCC AL12 Power Other VCC AN8 Power Other VCC AL14 Power Other VCC AN9 Power Other VCC AL15 Power Other VCC J10 Power Other VCC AL18 Power Other VCC J11 Power Other VCC AL19 Power Other VCC J12 Power Other VCC AL21 Power Other VCC J13 Power Other VCC AL22 Power Other VCC J14 Power Other VCC AL25 Power Other VCC J15 Power Other VCC AL26 Power Other VCC J18 Power Other VCC AL29 Power Other VCC J19 Power Other VCC AL30 Power Other VCC J20 Power Other VCC AL8 Power Other VCC J21 Power Other VCC AL9 Power Other VCC J22 Power Other VCC AM11 Power Other VCC J23 Power Other VCC AM12 Power Other VCC J24 Power Other VCC AM14 Power Other VCC
60. MB Vss It is connected internally in the processor package to the sense REGULATION Output point land V27 as described in the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket VTT Miscellaneous voltage supply VTT OUT LEFT The VTT OUT LEFT and VTT OUT RIGHT signals are included to Output provide a voltage supply for some signals that require termination VTT OUT RIGHT to Vy on the motherboard The VTT SEL signal is used to select the correct Vr voltage level for VTT SEL Output the processor This land is connected internally in the package to VTT 70 ss Datasheet m Thermal Specifications and Design Considerations n tel 5 5 1 Note 5 1 1 Datasheet Thermal Specifications and Design Considerations Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal so
61. Other R5 VSS Power Other U26 VCC Power Other R6 ADSTB0 Source Synch Input Output U27 VCC Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment bane Land Name Signal B ffer Direction Land Land Name Signal Buffer Direction Type Type U28 VCC Power Other Y5 VSS Power Other U29 VCC Power Other Y6 A193 Source Synch Input Output U30 MCC Power Other Y7 VSS Power Other V1 MSID1 Power Other Output Y8 VCC Power Other v2 RESERVED Y23 VCC Power Other v3 VSS Power Other Y24 VCC Power Other V4 A15 Source Synch Input Output Y25 VCC Power Other V5 Al4 Source Synch Input Output Y26 VCC Power Other V6 VSS Power Other Y27 VCC Power Other V7 VSS Power Other Y28 VCC Power Other V8 VCC Power Other Y29 VCC Power Other V23 VSS Power Other Y30 VCC Power Other V24 VSS Power Other AA1 MCN Power Other Output V25 VSS Power Other AA2 FC39 Power Other V26 VSS Power Other AA3 VSS Power Other V27 VSS Power Other AAA A21 Source Synch Input Output V28 VSS Power Other AA5 A234 Source Synch Input Output V29 VSS Power Other AA6 VSS Power Other V30 VSS Power Other AA7 VSS Power Other W1 MSIDO Power Other Output AA8 VCC Power
62. SS VSS v VSS VSS VSS VSS VSS VSS VSS VSS N VCC VCC VCC VCC VCC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC J vec vcc voc vec vec vec vcc vec vec vec vec vec vec Fc34 Foa1 vec H BSEL1 Fcis vss vss vss vss vss vss vss vss vss vss vss vss Fc33 FC32 G BSEL2 BSELO BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET D47 D44 DSTBN2 DSTBP2 D35 D36 D32 D31 F RSVD BCLK0 VTT SEL TESTHIO TESTHI2 TESTHI7 RSVD vss D43 D41i vss D38 D87 vss D304 E Foz vss vss vss vss Fcio Rsvp base D42 vss D40 D39 vss psa D33 p r vr Wr vr vr vt vss voceu pes vss pues pei vss paw Rsvp vss c wt wr vm vm vm VTT vss vapo VSS D58 DBI3 vss D54 DSTBP3 VSS D51 B VTT VTT VTT VTT VTT vr vss vssA D63 bos vss Deo D57 vss D55 D53 A vr vr wt wt vr vr FC23 voca D62 vss RsvD pei vss D56 DSTBN3 vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 40 Datasheet Land Listing and Signal Descriptions F
63. Source Synch Input Output E27 VSS Power Other D18 VSS Power Other E28 VSS Power Other D19 DBI2 Source Synch Input Output E29 FC26 Power Other D20 D48 Source Synch Input Output F2 GTLREF3 Power Other Input D21 VSS Power Other F3 BRO Common Clock Input Output D22 D46 Source Synch Input Output F4 VSS Power Other D23 VCCPLL Power Other F5 RS1 Common Clock Input D24 vss Power Other F6 FC21 Power Other D25 VTT Power Other F7 vss Power Other D26 VTT Power Other F8 D17 Source Synch Input Output D27 VTT Power Other F9 D18 Source Synch Input Output D28 VTT Power Other F10 VSS Power Other 53 54 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction tand Land Name Signal Butter Direction Type Type F11 D23 Source Synch Input Output G21 D44 Source Synch Input Output F12 D24 Source Synch Input Output G22 D47 Source Synch Input Output F13 VSS Power Other G23 RESET Common Clock Input F14 D28 Source Synch Input Output G24 TESTHI6 Power Other Input F15 D30 Source Synch Input Output G25 TESTHI3 Power Other Input F16 VSS Power Other G26 TESTHI5 Power Other Input F17 D37 Source Synch Input Output G27 TESTHI4 Power Other Input F18 D38 Source Synch Input Output
64. Synch Input Output H26 VSS Power Other G18 D35 Source Synch Input Output H27 VSS Power Other G19 DSTBP2 Source Synch Input Output H28 vss Power Other G20 DSTBN2 Source Synch Input Output H29 FC15 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment FADE Land Name Signal Butter Direction sna Land Name signat Buter Direction Type Type H30 BSEL1 Power Other Output K23 VCC Power Other J1 VIT OUT LEFT Power Other Output K24 VCC Power Other J2 FC3 Power Other K25 VCC Power Other J3 FC22 Power Other K26 VCC Power Other J4 VSS Power Other K27 VCC Power Other J5 REQ1 Source Synch Input Output K28 VCC Power Other J6 REQ4 Source Synch Input Output K29 VCC Power Other J7 VSS Power Other K30 VCC Power Other J8 VCC Power Other L1 LINT1 Asynch CMOS Input J9 VCC Power Other L2 TESTHI13 Power Other Input J10 VCC Power Other L3 VSS Power Other J11 VCC Power Other L4 A06 Source Synch Input Output J12 VCC Power Other L5 A03 Source Synch Input Output J13 VCC Power Other L6 VSS Power Other J14 VCC Power Other L7 VSS Power Other jas VCC Power Other L8 VCC Power Other J16 FC31 Power Other L23 VSS Power Other J17 FC34 Power Other L24 VSS Power Other J18 VCC Power Other L2
65. al Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 5096 Clocks often will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An Datasheet m Thermal Specifications and Design Considerations n tel 5 2 2 Datasheet under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a Tc that exceeds the specified maximum temperature and may affect the long te
66. al solution it is anticipated that PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi directional PROCHOT feature THERMTRI P Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 25 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 25 THERMTRIP activation is independent of processor activity and does not generate any bus cycles If THERMTRIP is asserted processor core voltage Vcc must be removed within the timeframe defined in Table 10 79 m n tel Thermal Specifications and Design Considerations 5 3 5 3 1 5 3 1 1 Figure 20 80 Platform Environment Control I nterface PECI I ntroduction PECI offers an interface for thermal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues PECI uses CRC che
67. ased Platforms rr nes 80 21 Processor Low Power State Machine r r nemen enn 84 22 Mechanical Representation of the Boxed Processor rr 87 23 Space Requirements for the Boxed Processor Side View 88 24 Space Requirements for the Boxed Processor Top View ssssssss nmm 89 25 Space Requirements for the Boxed Processor Overall View 89 26 Boxed Processor Fan Heatsink Power Cable Connector Description 91 27 Baseboard Power Header Placement Relative to Processor Socket 92 28 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 1 View 93 29 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 2 View 93 30 Boxed Processor Fan Heatsink Set POINtS cece eee memes 95 Datasheet Tables T References chromium Eure SEE noci cua etnies CLR EQ E LU URL LUE 11 2 Voltage Identification Definition nm mnm meme sese nemen nnne nnn 15 3 Absolute Maximum and Minimum RatingS rr emm meme enn 17 4 Voltage and Current Specifications cc emen ene emen enne 18 5 Vce Static and Transient Tolerance sese ener nnn 19 6 Vec Overshoot Specifications eeepc tene ipie sed tete Fo nek pan umes EES ae nen 21 3 FSB Signal
68. at spreader I HS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Retention mechanism RM Since the LGA775 socket does not include any mechanical features for heatsink attach a retention mechanism is required Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Storage conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Functional operation Refers to normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied
69. be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 6 of 9 Name LOCK Type Input Output Description LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock PECI Input Output PECI is a proprietary one wire bus interface See Section 5 3 for details PROCHOT Input Output As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will ac
70. cal Design Guide Processor Mass Specification The typical mass of the processor is 21 5 g 0 76 oz This mass weight includes all the components that are included in the package Processor Materials Table 22 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader Nickel Plated Copper IHS Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 10 shows the topside markings on the processor This diagram is to aid in the identification of the processor Processor Top Side Markings Example for 1066 MHz Processors INTEL 05 QX6700 INTEL CORE 2 EXTREME Sixx COO 2 66GHZ 8M 1066 05B FPO Datasheet Package Mechanical Specifications Figure 11 Datasheet Processor Top Side Markings Example for 1333 MHz Processors INTEL 05 OX 59 50 INTEL CORE 2 EXTREME SLxxx COO 3 00GHZ 8M 1333 05B PO 37 n te Package Mechanical Spec 3 9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 12 Processor Land Coordinates and Quadrants Top View Voc Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 y
71. ce Synch Input Output AK15 VCC Power Other AJ7 VSS Power Other AK16 VSS Power Other AJ8 VCC Power Other AK17 VSS Power Other AJ9 VCC Power Other AK18 WCC Power Other AJ10 VSS Power Other AK19 VCC Power Other AJ11 VCC Power Other AK20 VSS Power Other AJ12 VCC Power Other AK21 VCC Power Other AJ13 VSS Power Other AK22 VCC Power Other AJ14 VCC Power Other AK23 VSS Power Other AJ15 VCC Power Other AK24 VSS Power Other AJ16 VSS Power Other AK25 VCC Power Other AJ17 VSS Power Other AK26 VCC Power Other AJ 18 VCC Power Other AK27 VSS Power Other AJ 19 VCC Power Other AK28 VSS Power Other AJ20 VSS Power Other AK29 VSS Power Other AJ21 VCC Power Other AK30 VSS Power Other AJ 22 VCC Power Other AL1 FC25 Power Other AJ23 VSS Power Other AL2 PROCHOT Asynch CMOS Input Output AJ24 VSS Power Other AL3 VRDSEL Power Other AJ25 VCC Power Other AL4 VID5 Power Other Output AJ 26 VCC Power Other AL5 VID1 Power Other Output AJ27 VSS Power Other AL6 VID3 Power Other Output AJ28 VSS Power Other AL7 VSS Power Other AJ29 VSS Power Other AL8 VCC Power Other AJ30 VSS Power Other ALY VCC Power Other AK1 FC24 Power Other AL10 VSS Power Other AK2 VSS Power Other AL11 VCC Power Other AK3 ITP CLKO TAP Input AL12 VCC Power Other AK4 VID4 Power Other Output AL13 VSS Power Other AK5 VSS Power Other AL14 VCC Power Other AK6 FC8 Power Other AL15 VCC Power Other AK7 VSS Power Other AL16 VSS Power Other AK8 VCC Power Other AL17 VSS Power Other
72. cking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on the processor is disabled by default and must be enabled through BIOS TcourRor and TCC Activation on PECI Based Systems Fan speed control solutions based on PECI use a TcoxrRoL value stored in the processor 1A32 TEMPERATURE TARGET MSR The TcontroL MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the TcowrRo Value as negative Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the TconTRoL MSR value to control or optimize fan speeds Figure 20 shows a conceptual fan control diagram using PECI temperatures The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT assertions As the temperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero Conceptual Fan Control on PECI Based Platforms TcontRoL TCC Activation Setting Temperature Max PEG 0 Fan Speed RPM Temperature Note Not intended to depict actual implementation Datasheet Thermal Specifications and Design Considerations n tel 5 3 2 5 3
73. d a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality ntel virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Pentium Itanium Xeon Intel SpeedStep andand the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2006 2007 Intel Corporation 2 Datasheet Contents 1 dipped c n O E E E O 9 11 Terminology uc 9 LLI Processor Terminology retenir aeterni E E manana Kb er E RR I Rd 10 PEE Voces 11 2 Electrical Specifications oot erar A eie ne veens Ex Faq RR S EFE E PERI etnias 13 2 1 Power and Ground Lands oit e Ret a duu va RE ER PEARCE REY FRIEND eee 13 2 2 Decoupling Guidelin S i ioter errore does xh reme naka unen Ru RR Ke e ERU ES Vanda d 13 2 2 1 VGC Decoupling ro UA Matis ata MEER Renae I rt IE EDAM 13 2 22 VIT Decotuplifig ccrte ERE asaspuyayasnakasqaspaspapasasatysakanusquaswa pap hanakasaamassas 13 2 2 3 FSB
74. d on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Package Handling Guidelines Table 21 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 Ibf L2 Tensile 111 N 25 Ibf 2 3 Torque 3 95 N m 35 Ibf in 2 NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidelines are based on limited testing for design characterization 3 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 4 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 35 m n tel Package Mechanical Specifications 3 7 Table 22 3 8 Figure 10 36 Package I nsertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times The Socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechani
75. e It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 4 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 5 and Figure 1 as measured across the VCC SENSE and VSS SENSE lands The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 4 and Table 5 Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details Datasheet Electrical Specifications n tel Table 2 Voltage Identification Definition VI D6 VID5 VIDA VID3 VID2 VID1 Vcc MAX VI D6 VID5 VIDA VID3 VID2 VID1 Vec max 1 1 1 1 0 1 0 8500 0 1 1 1 1 0 1 2375 1 1 1 1 0 0 0 8625 0 1 1 1 0 1 1 2500 1 1 1 0 1 1 0 8750 0 1 1 1 0 0 1 2625 1 1 1 0 1 0 0 8875 0 1 1 0 1 1 1 2750 1 1 1 0 0 1 0 9000 0 1 1 0 1 0 1 2875 1 1 1 0 0 0 0 9125 0 1 1 0 0 1 1 3000 1 1 0 1 1 1 0 9250 0 1 1 0 0 0 1 3125 1 1 0 1 1 0 0 9375 0 1 0 1 1 1 1 3250 1 1 0 1 0 1 0 9500 0 1 0 1 1 0 1 3375 1 1 0 1 0 0 0 9625 0 1 0 1 0 1 1 3500 1 1 0 0 1 1 0 9750 0 1 0 1 0 0 1 3625 1 1 0 0 1 0 0 9875 0 1 0 0 1 1 1 3750
76. e Synch Input Output D41 F20 Source Synch Input Output FCO Y1 Power Other D42 E21 Source Synch Input Output FC3 J2 Power Other D43 F21 Source Synch Input Output FC10 E24 Power Other D44 G21 Source Synch Input Output FC15 H29 Power Other D45 E22 Source Synch Input Output FC17 Y3 Power Other D46 D22 Source Synch Input Output FC18 AE3 Power Other D47 G22 Source Synch Input Output FC20 E5 Power Other D48 D20 Source Synch Input Output FC21 F6 Power Other D49 D17 Source Synch Input Output FC22 J3 Power Other D50 A14 Source Synch Input Output FC23 A24 Power Other D51 C15 Source Synch Input Output FC24 AK1 Power Other D52 C14 Source Synch Input Output FC25 AL1 Power Other D53 B15 Source Synch Input Output FC26 E29 Power Other D54 C18 Source Synch Input Output FC29 U2 Power Other D55 B16 Source Synch Input Output FC30 U3 Power Other D56 A17 Source Synch Input Output FC31 J16 Power Other 43 44 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name E Bun tuos Direction Land Name d Buses ums Direction FC32 H15 Power Other RESERVED AH2 FC33 H16 Power Other RESERVED D1 FC34 J17 Power Other RESERVED D14 FC35 H4 Power Other RESERVED D16 FC36 AD3 Power Other
77. e upon software only solutions Because this virtualization hardware provides a new architecture upon which the operating system can run directly it removes the need for binary translation Thus it helps eliminate associated performance overhead and vastly simplifies the design of the VMM in turn allowing VMMs to be written to common standards and to be more robust See the Inte Architecture for more details References Virtualization Technology Specification for the 1A 32 Intel Material and concepts available in the following documents may be beneficial when reading this document References Document Location Intel Core 2 Extreme Quad Core Processor QX6000 Sequence and Intel Core 2 Quad Processor Q6000 Sequence Specification Update http www intel com design processor specupdt 315593 htm Intel Core 2 Extreme Quad Core Processor and Intel Core 2 Quad Processor Thermal and Mechanical Design Guidelines http www intel com design processor designex 315594 htm Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket http www intel com design processor applnots 313214 htm Balanced Technology Extended BTX System Design Guide www formfactors org Intel Virtualization Technology Specification for the IA 32 Intel Architecture http www intel com technology computing vptech index htm LGA775 Socket Mecha
78. ents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups DSTBN DSTBP PB Data Group D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 01 Input Output DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBI 3 D 63 48 DBI 2 D 47 32 DBI 1 D 31 16 DBI0 D 15 0 DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR
79. er N4 RESERVED R25 VSS Power Other N5 RESERVED R26 vss Power Other N6 VSS Power Other R27 VSS Power Other N7 VSS Power Other R28 VSS Power Other N8 VCC Power Other R29 VSS Power Other N23 VCC Power Other R30 VSS Power Other N24 VCC Power Other T1 COMP1 Power Other Input N25 VCC Power Other T2 FC4 Power Other N26 VCC Power Other T3 VSS Power Other N27 VCC Power Other T4 A11 Source Synch Input Output N28 VCC Power Other TS A094 Source Synch Input Output N29 VCC Power Other T6 VSS Power Other N30 vcc Power Other T7 VSS Power Other P1 TESTHI 11 Power Other Input T8 VCC Power Other P2 SMI Asynch CMOS Input T23 VCC Power Other P3 INIT Asynch CMOS Input T24 VCC Power Other P4 VSS Power Other T25 VCC Power Other P5 RESERVED T26 VCC Power Other P6 A04 Source Synch Input Output T27 VCC Power Other P7 VSS Power Other T28 VCC Power Other P8 VCC Power Other T29 VCC Power Other P23 VSS Power Other T30 VCC Power Other P24 VSS Power Other U1 TDO_M TAP Output P25 vss Power Other U2 FC29 Power Other P26 vss Power Other U3 FC30 Power Other P27 VSS Power Other U4 A13 Source Synch Input Output P28 VSS Power Other U5 A124 Source Synch Input Output P29 VSS Power Other U6 A10 Source Synch Input Output P30 vss Power Other U7 VSS Power Other R1 COMP3 Power Other Input U8 VCC Power Other R2 VSS Power Other U23 VCC Power Other R3 FERR PBE Asynch CMOS Output U24 VCC Power Other R4 A08 Source Synch Input Output U25 VCC Power
80. er VCC N23 Power Other VCC Y23 Power Other VCC N24 Power Other VCC Y24 Power Other VCC N25 Power Other VCC Y25 Power Other VCC N26 Power Other VCC Y26 Power Other VCC N27 Power Other VCC Y27 Power Other VCC N28 Power Other VCC Y28 Power Other VCC N29 Power Other VCC Y29 Power Other VCC N30 Power Other VCC Y30 Power Other VCC N8 Power Other VCC Y8 Power Other lt MERE R CUPATICN AN5 Power Other Output VEE Power Other VCC_SENSE AN3 Power Other Output 6 PowerfoOther VCCA A23 Power Other IE T25 Poker Other VCCIOPLL C23 Power Other wee T36 Power other VCCPLL D23 Power Other 47 48 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name R Butter duos Direction Land Name zu Bustos ons Direction VID SELECT AN7 Power Other Output VSS AC6 Power Other VIDO AM2 Power Other Output VSS AC7 Power Other VID1 AL5 Power Other Output VSS AD4 Power Other VID2 AM3 Power Other Output VSS AD7 Power Other VID3 AL6 Power Other Output VSS AE10 Power Other VID4 AK4 Power Other Output VSS AE13 Power Other VID5 AL4 Power Other Output VSS AE16 Power Other VID6 AM5 Power Other Output VSS AE17 Power Other VID7 AM7 Power Other Output VSS AE2 Power Other VRDSEL AL3 Pow
81. er Other VSS AE20 Power Other VSS A12 Power Other VSS AE24 Power Other VSS A15 Power Other VSS AE25 Power Other VSS A18 Power Other VSS AE26 Power Other VSS A2 Power Other VSS AE27 Power Other VSS A21 Power Other VSS AE28 Power Other VSS A6 Power Other VSS AE29 Power Other VSS A9 Power Other VSS AE30 Power Other VSS AA23 Power Other VSS AE5 Power Other VSS AA24 Power Other VSS AE7 Power Other VSS AA25 Power Other VSS AF10 Power Other VSS AA26 Power Other VSS AF13 Power Other VSS AA27 Power Other VSS AF16 Power Other VSS AA28 Power Other VSS AF17 Power Other VSS AA29 Power Other VSS AF20 Power Other VSS AA3 Power Other VSS AF23 Power Other VSS AA30 Power Other VSS AF24 Power Other VSS AA6 Power Other VSS AF25 Power Other VSS AA7 Power Other VSS AF26 Power Other VSS AB1 Power Other VSS AF27 Power Other VSS AB23 Power Other VSS AF28 Power Other VSS AB24 Power Other VSS AF29 Power Other VSS AB25 Power Other VSS AF3 Power Other VSS AB26 Power Other VSS AF30 Power Other VSS AB27 Power Other VSS AF6 Power Other VSS AB28 Power Other VSS AF7 Power Other VSS AB29 Power Other VSS AG10 Power Other vss AB30 Power Other vss AG13 Power Other vss AB7 Power Other vss AG16 Power Other vss AC3 Power Other vss AG17 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel
82. er s Guide for more information Datasheet Features 6 2 2 2 6 2 3 Datasheet intel The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT Power Down state the processor will process bus snoops Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS When one of the processor cores executes the HALT instruction that logical processor is halted however the other processor continues normal operation The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification Not all processors are capable of supporting Extended HALT State More details on which processor frequencies will support this feature will be provided in future releases of the Intel Core 2 Extreme Quad Core Processor QX6700 and Intel Core 2 Quad Processor Q6000 Sequence Specification Update when available The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus ratio and then t
83. erboard requirements for 4 wire based fan speed control refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 ss Datasheet m Debug Tools Specifications n tel 8 8 1 8 1 1 8 1 2 Datasheet Debug Tools Specifications Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a r system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstruc
84. ershoot above VID 50 mV 2 1 Time duration of Vcc overshoot above Tos MAX es 25 us 2 N VID NOTES T Adherence to these specifications is required to ensure reliable processor operation Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos o 8 S gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vos is measured overshoot voltage 2 Tos is measured time duration above VID Die Voltage Validation Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit 21 m n tel Electrical Specifications 2 6 2 6 1 Table 7 22 Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic GTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Platforms implement a termination voltage level for GTL signals defined as V m Because platforms implement separate power planes for each processor and chipset separate Vcc and Vyr supplies are necessary This configuration allows for improved noi
85. esholds the oscilloscope is to use for the edge rate calculations Slew rate matching is a single ended measurement Figure 3 Differential Clock Waveform CLK 0 Vcnoss d ES n Median 75 mV X 500 mV CROSS v q V median CROSS V CROSS ee VcRoss Min me Median 75 mV 300 mV CLK 1 Period Datasheet 29 n tel Electrical Specifications Figure 4 Differential Clock Crosspoint Specification 650 600 550 0 5 VHavg 700 300 0 5 VHavg 700 Crossing Point mV 250 LT 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Figure 5 Differential Measurements Slew rise Slew fall 150 mV eeecc s s s p Diff ss 30 Datasheet m Package Mechanical Specifications n tel 3 Figure 6 3 1 Datasheet Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array FC LGA6 package that interfaces with the motherboard via an LGA775 socket The package consists of a processor core mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 6 shows a sketch of the
86. ess 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe the ADS activation to begin protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Outpu
87. flow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 28 and Figure 29 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 39 C Again meeting the processor s temperature specification is the responsibility of the system integrator Datasheet Boxed Processor Specifications n tel Figure 28 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 1 View R55 2 2 17 Figure 29 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 2 View Datasheet 93 m n tel Boxed Processor Specifications 7 3 3 94 Fan Speed Control Operation Intel Core 2 Extreme processors only The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed The fan speed can be controlled by hardware and software from the motherboard This is accomplished by varying the duty cycle of the Control signal on the 4th pin see Table 32 The motherboard must have a 4 pin fan header and must be designed with a fan speed controller with PWM output and Digital Thermometer measurement capabilities For more information on specific
88. he temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 5 2 Systems that implement fan speed control must be designed to take these conditions in to account Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications To determine a processor s case temperature specification based on the thermal profile it is necessary to accurately measure processor power dissipation Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 71 e n tel Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 26 instead of the maximum processor power consumption The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time For more details on the usage of this feature refer to Section 5 2
89. hronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins lands of all processor FSB agents ITP CLK 1 0 Input ITP CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system ITP CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins lands of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must
90. igure 14 land out Diagram Top View Right Side 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VID SEL VSS MB VCC MB VSS VCC voc vss vec vec vss vec vec ECT REGULATION REGULATION SENSE SENSE VSS VSS VCC VSS VCC VCC VSS VCC VCC VID7 FC40 VID6 VSS VID2 VIDO VSS VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VRDSEL PROCHOT FC25 VCC VSS VCC VCC VSS VCC VCC VSS FC8 VSS VID4 ITP_CLKO VSS FC24 VCC VSS VCC VCC VSS VCC VCC VSS A35 A34 VSS ITP_CLK1 BPMO BPM1 vec vss vec vec vss vec VCC vss vss A33 A324 vss RSVD vss vec vss vec vcc vss vec VCC vss A29 A31 A308 BPM5 BPM3 TRST vec vss vec vec vss vec VCC VSS vss A27 A28 VSS BPM4 TDO vec vss vec vce vss voc skrocc vss RSVD vss RSVD FC18 vss TCK VCC VSS A224 ADSTB1 VSS FC36 BPM2 TDI VCC VSS VSS A25it RSVD vss DBR TMS VCC VSS A17 A24 A26 FC37 IERR VSS VTT OUT vec vss vss A23 A214 vss FC39 T VCC VSS A194 vss A20 FC17 vss FCO VCC VSS A18 A16 vss TESTHI1 TDI M MSIDO VCC VSS VSS A14 A15 vss RSVD MSID1 VCC vss A10 A12 A13 FC30 FC29 TDO M vcc vss vss A9 ATA vss FC4 COMP1 vec VSS ADSTBOR VSS ase core vss COMP3 VCC VSS A4 RSVD vss INIT SMI TESTHITI VCC VSS VSS RSVD RSVD VSS IGNNE PWRGOOD vcc VSS REQ2 A5 A7 stpcik MERMTRI VSS VCC VSS VSS A3 A6 VSS TESTHI13 LINT1 VCC VSS REQ3 VSS REQo A20M VSS LINTO vec vcc vec vec vec vec vec vss REQ4 REQ1 vss FC22 FC3 ME VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI
91. igure 22 Mechanical Representation of the Boxed Processor NOTE The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Datasheet 87 m n tel Boxed Processor Specifications 7 1 Z L 1 Figure 23 88 Mechanical Specifications Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor The boxed processor will be shipped with an unattached fan heatsink Figure 22 shows a mechanical representation of the boxed processor Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 23 Side View and Figure 24 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 28 and Figure 29 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning Space Requirements for the Boxed Processor Side View 95 0 8 747 A 81 3 3 2 10 0 25 0 0 39 0 98 v 4 Boxed Proc SideView Datasheet m Boxed Processor Specifications n tel Figure 24 Space Requirements for the Boxed Processor Top View
92. knowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI_M Input TDI and TDI M Test Data In transfer serial test data into the processor cores TDI and TDI M provide the serial input needed for JTAG specification support TDI connects to core 0 TDI M connects to core 1 TDO TDO M TESTHI 13 11 10 7 0 Output Input TDO and TDO M Test Data Out transfer serial test data out of the processor cores TDO and TDI M provide the serial output needed for JTAG specification support TDO connects to core 1 TDO M connects to core 0 TESTHI 13 11 10 7 0 must be connected to the pr
93. lutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 The boxed processor will ship with a component thermal solution Refer to Chapter 7 for details on the boxed processor Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature Tc specifications when operating at or below the Thermal Design Power TDP value listed per frequency in Table 26 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 5 3 1 1 T
94. may contain design defects or errors known as errata which may cause the product to deviate from published specifications Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order A ntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com technology intel64 index htm for more information including details on which processors support Intel 64 or consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability an
95. merical Land Assignment sssssessssssssssssenenese enemies ee esee K K K K eese 52 25 Signal DescriptlOli erret etr Eo eR RE rtech E anes tebou ak onak RR UM ERREE FE NU pu ka 62 26 Processor Thermal Specifications ccc nemen emen eene 72 27 Thermal Profile for 130 W Processors tenet need 73 28 Thermal Profile for 105 W Processors eter 74 29 Thermal Profile 95 W Processors sssssssssssssennememen mme messe K K P eese 75 30 GetTempO and GetTempl Error Codes eee enna 81 31 Power On Configuration Option Signals 2 2 4440 000000000 eh net k 83 32 Fan Heatsink Power and Signal SpecificationsS rr 91 33 Fan Heatsink Power and Signal Specifications sssssssssssssseene menn 95 6 Datasheet Revision History pe Description Date 001 Initial release November 2006 Added specifications for the Intel Core 2 Ouad Processor 06600 m eee retinas January 2007 Updated Table 29 Fan Heatsink Power and Signal Specifications 003 s specifications for the Intel Core 2 Ouad Processor 06700 and Intel Core 2 July 2007 xtreme quad core processor OX6850 003 Added Intel Core 2 Quad Processor 06600 for 775 VR CONFIG 05A July 2007 004 Added Intel Core 2 Extreme quad core processor QX6850 July 2007 005 Added Intel Core 2 Extreme quad core processor QX6
96. mmunity above 300 MHz 0 1 Vr Vp p NOTE 1 V supplies the PECI interface PECI behavior does not affect V r min max specifications Refer to Table 4 for Vrr specifications 2 The leakage specification applies to powered devices on the PECI bus 3 The input buffers use a Schmitt triggered input design for improved noise immunity Datasheet 25 intel 2 6 3 1 Table 14 2 7 2 7 1 Table 15 26 Electrical Specifications GTL Front Side Bus Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 8 for details on which GTL signals do not include on die termination Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF Table 14 lists the GTLREF specifications The GTL reference voltage GTLREF should be generated on the system board using high precision voltage divider circuits GTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF PU GTLREF pull up resistor 124 0 99 124 124 1 01 Q 2 GTLREF_PD GTLREF pull down resistor 210 0 99 210 210 1 01 Q 2 RTT Termination Resistance 45 50 55 Q 3 COMP 3 0 COMP Resistance 49 40 49 90 50 40 Q u COMP8 COMP Resistance 24 65 24 90 25 15 Q 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 GTLREF is
97. n 10 us of the assertion of PWRGOOD provided Vrr and Vcc are valid TMS Input TMS Test Mode Select is a J TAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins lands of all FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCC Input VCC are the power pins for the processor The voltage supplied to these pins is determined by the VID 7 0 pins VCCPLL Input VCCPLL provides isolated power for internal processor FSB PLLs VCC SENSE VCC MB REGULATION Output Output VCC SENSE is an isolated low impedance connection to processor core power Vcc It can be used to sense or measure voltage near the silicon with little noise This land is provided as a voltage regulator feedback sense point for Vcc It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket VID 7 0 Output VID 7 0 Voltage ID signals are used to support automatic selection of power supply voltages Vcc Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desk
98. n GTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the motherboard trace for front side bus signals For unused GTL input or I O signals use pull up resistors of the same value as the on die termination resistors RTT For details see Table 14 TAP and CMOS signals do not include on die termination Inputs and utilized outputs must be terminated on the motherboard Unused outputs may be terminated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing All TESTHI 13 11 10 7 0 lands should be individually connected to V via a pull up resistor which matches the nominal trace impedance The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group TESTHI 1 0 TESTHI 7 2 TESTHI10 cannot be grouped with other TESTHI signals TESTHI11 cannot be grouped with othe
99. n be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes Vec Core voltage with respect to Vss 0 3 1 55 V FSB termination voltage with VI respect to Vss ae 1 95 y I See See s Tc Processor case temperature Chapter 5 Chapter 5 C Tstorace Processor storage temperature 40 85 ec 3 4 5 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation Refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Fail
100. n measurements at a later date Adherence to the voltage specifications for the processor are required to ensure reliable processor operation Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Extended HALT State These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 for more information The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Refer to Table 5 and Figure 1 for the minimum typical and maximum Vec allowed for a given current The processor should not be subjected to any Vcc and Icc combination wherein Vcc exceeds Vcc max for a given current These processors have CPUID 06F7h Datasheet Electrical Specifications n tel
101. nded HALT Snoop or HALT Snoop State Stop Grant Snoop State mese see enne nnn 86 6 2 4 1 HALT Snoop State Stop Grant Snoop State 86 6 2 4 2 Extended HALT Snoop State rr 86 Boxed Processor Specifications ssssssssssssseesneememee meme eene 87 7 1 Mechanical Specifications 0 mmm senem seen memes sens 88 7 1 1 Boxed Processor Cooling Solution DIMENSIONS 88 7 1 2 Boxed Processor Fan Heatsink Weight 0000 n en 90 7 1 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 90 7 2 Electrical Requirements 2 2 2440 0000 memes eene eme sene K K K KK nns 90 7 2 1 Fan Heatsink Power Supply uuu eee ee ee memes 90 7 3 Thermal Specifications coercet RUE SIR TY IR auqa wawawa m SE K RUNI wasiq 92 7 3 1 Boxed Processor Cooling Requirements eee 92 7 3 2 Fan Speed Control Operation Intel Core 2 Extreme processors only 94 7 3 3 Fan Speed Control Operation Intel Core 2 Quad processor 94 Debug Tools Specifications sssssssssssssssse memes ene 97 8 1 Logic Analyzer Interface LAI a memes menn nnn 97 8 1 1 Mechanical Considerations c sss emen memes 97 8 1 2 Electrical Corisideratfions uuu u uuu eene ana T naa nemen memes 97 Datasheet Figures 1 Vee Static and Transient Tolerance
102. nical Design Guide http intel com design Pentium4 guides 302666 htm Intel 64 and IA 32 Architecture Software Developer s Manuals Volume 1 Basic Architecture Volume 24A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide http www intel com products processor manuals http www intel com products processor manuals http www intel com products processor manuals http www intel com products processor manuals http www intel com products processor manuals S S 11 12 Introduction Datasheet Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals DC electrical characteristics are provided 2 1 Power and Ground Lands The processor has VCC power VTT and VSS ground inputs for on chip power distribution All power lands must be connected to Vcc while all Vss lands must be connected to a system ground plane The processor VCC lands must be supplied the voltage determined by the Voltage I Dentification VID lands The signals are denoted as VTT which provide termination for the front side bus and ntel power to the I O buffers A separate supply must be implemented for these lands that meets the V4 specifications outlined in Table 4 2 2 Decoupling Guidelines
103. ntel Table 27 Thermal Profile for 130 W Processors Power Maximum Power Maximum Power Maximum Power Maximum W Tc C W Tc C W Tc C W Tc C 0 42 4 34 48 2 68 54 0 102 59 7 2 42 7 36 48 5 70 54 3 104 60 1 4 43 1 38 48 9 72 54 6 106 60 4 6 43 4 40 49 2 74 55 0 108 60 8 8 43 8 42 49 5 76 55 3 110 61 1 10 44 1 44 49 9 78 57 7 112 61 4 12 44 4 46 50 2 80 56 0 114 61 8 14 44 8 48 50 6 82 56 3 116 62 1 16 45 1 50 50 9 84 56 7 118 62 5 18 45 5 52 51 2 86 57 0 120 62 8 20 45 8 54 51 6 88 57 4 122 63 1 22 46 1 56 51 9 90 57 7 124 63 5 24 46 5 58 52 3 92 58 0 126 63 8 26 46 8 60 53 1 94 58 4 128 64 1 28 47 2 62 52 9 96 58 7 130 64 5 30 47 5 64 53 3 98 59 1 32 47 8 66 53 6 100 59 4 Figure 15 Thermal Profile for 130 W Processors Datasheet Tcase C 65 0 60 0 m e o a e o y 0 17x 42 4 45 0 20 30 40 50 60 70 Power W 80 90 100 110 120 130 73 intel Thermal Specifications and Design Considerations Table 28 Thermal Profile for 105 W Processors Power Maximum Power Maximum Power Maximum Power Maximum W Tc C W Tc C W Tc C W Tc C 0 43 3 28 48 3 56 53 4 84 58 4 2 43 7 30 48 7 58 53 8 86 58 8 4 44 0 32 49 1 60 54 1 88 59 1 6 44 4 34 49 4 62 54 5 90
104. ocessor s appropriate power source refer to VTT OUT LEFT and VTT OUT RIGHT signal description through a resistor for proper processor operation See Section 2 4 for more details Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 8 of 9 Name THERMTRIP Type Output Description In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum Tc Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 us of the assertion of PNRGOOD provided V and Vcc are valid and is disabled on de assertion of PWRGOOD if Vr or Vcc are not valid THERMTRIP may also be disabled Once activated THERMTRIP remains latched until PWRGOOD V or Vcc is de asserted While the de assertion of the PWRGOOD Vr or Vcc will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRI P will again be asserted withi
105. ondition on PECI the Host controller should take action to protect the system from possible damaging states It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive GetTempO s or GetTemp1 s or for a one second time interval The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO and GetTemp1 Error Code Support The error codes supported for the processor GetTempO and GetTemp1 commands are listed in Table 30 GetTempO and GetTemp1 Error Codes Error Code Description 8000h General sensor error 8002h Sensor is operational but has detected a temperature below its operational range underflow S S 81 82 Thermal Specifications and Design Considerations Datasheet Features 6 6 1 Table 31 6 2 Datasheet intel Features Power On Configuration Options Several configuration options can be configured by hardware The processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options refer to Table 31 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset pu
106. or is that contained in the CLOCK FLEX MAX MSR and the VID is that specified in Table 4 These parameters represent normal system operation The second operating point consists of both a lower operating frequency and voltage When the TCC is activated the processor automatically transitions to the new frequency This transition occurs very rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will likely be one VID table entry see Table 4 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature
107. ould be kept below 38 C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor Refer to Table 32 for the specific requirements Datasheet Boxed Processor Specifications n tel Figure 30 Table 33 Datasheet Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise Level Increasing Fan Speed amp Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point C Boxed Processor Fan Speed Notes When the internal chassis temperature is below or equal to this set point the fan operates at its lowest speed 1 Recommended maximum internal chassis temperature for nominal operating environment X lt 30 When the internal chassis temperature is at this point the fan operates between its lowest and highest speeds Recommended maximum internal chassis temperature for worst case operating environment Z gt 39 When the internal chassis temperature is above or equal to i B this set point the fan operates at its highest speed NOTES 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink
108. ource Synch Input Output A31 AG5 Source Synch Input Output D7 A7 Source Synch Input Output A324 AH4 Source Synch Input Output D8 A10 Source Synch Input Output A33 AH5 Source Synch Input Output D9 A11 Source Synch Input Output A34 AJ5 Source Synch Input Output D10 B10 Source Synch Input Output A35 AJ6 Source Synch Input Output D11 C11 Source Synch Input Output A20M K3 Asynch CMOS Input D12 D8 Source Synch Input Output ADS D2 Common Clock nput Output D13 B12 Source Synch Input Output ADSTBO R6 Source Synch Input Output D14 C12 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output D15 D11 Source Synch Input Output BCLK0 F28 Clock Input D16 G9 Source Synch Input Output BCLK1 G28 Clock Input D17 F8 Source Synch Input Output Datasheet Land Listing and Signal Descriptions Datasheet intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name ue BiU Pubs Direction Land Name E denne Direction D18 F9 Source Synch Input Output D573 B18 Source Synch Input Output D19 E9 Source Synch Input Output D58 C21 Source Synch Input Output D20 D7 Source Synch Input Output D59 B21 Source Synch Input Output D21 E10 Source Synch Input Output D60 B19
109. ove on software only solutions ss 8 Datasheet Introduction 1 Note Note 1 1 Datasheet intel Introduction The Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 quad processor Q6000 sequence are the first desktop quad core processors that combine the performance and power efficiencies of four low power microarchitecture cores to enable a new level of multi tasking multi media and gaming experiences They are 64 bit processors that maintain compatibility with IA 32 software The processors use Flip Chip Land Grid Array FC LGA6 package technology and plug into a 775 land surface mount Land Grid Array LGA socket referred to as the LGA775 socket The processors are based on 65 nm process technology In this document the Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 quad processor Q6000 sequence are referred to simply as processor In this document the Intel Core 2 quad core processor Q6000 sequence refers to the Intel Core 2 quad processor Q6600 and Q6700 The Intel Core 2 Extreme quad core processor QX6000 sequence refers to the Intel Core 2 Extreme quad core processors QX6700 QX6800 and QX6850 The processor supports all the existing Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3 The processor supports several advanced technologies including Execute Disable Bit Intel 64 architecture and Intel Virt
110. processor package components and how they are assembled together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 6 include the following e Integrated Heat Spreader IHS Thermal Interface Material TI M Processor core die Package substrate Capacitors Processor Package Assembly Sketch Core die MM IHS Substrate o S Capacitors LGA775 Socket t 4 NOT E 1 Socket and motherboard are included for reference and are not part of processor package Package Mechanical Drawing The package mechanical drawings are shown in Figure 7 and Figure 8 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include e Package reference with tolerances total height length width etc IHS parallelism and tilt Land dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm in Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines 31 intel Figure 7 Processor Package Drawing Sheet 1 of 3 L ua l o Package Mechanical Specifications WV C88285 7 Y E T 0000000000000000000000000
111. put B28 VTT Power Other A20 RESERVED B29 VTT Power Other A21 VSS Power Other B30 VIT Power Other A22 D62 Source Synch Input Output C1 DRDY Common Clock Input Output A23 VCCA Power Other C2 BNR Common Clock Input Output A24 FC23 Power Other C3 LOCK Common Clock Input Output A25 VIT Power Other C4 VSS Power Other A26 VIT Power Other C5 D01 Source Synch Input Output A27 VTT Power Other C6 D03 Source Synch Input Output A28 VTT Power Other C7 VSS Power Other A29 VIT Power Other C8 DSTBNO Source Synch Input Output A30 VIT Power Other C9 BPMb1 d Input Output Bl VSS Power Other C10 VSS Power Other B2 DBSY Common Clock Input Output C11 D11 Source Synch Input Output B3 RS0 Common Clock Input C12 D14 Source Synch Input Output B4 D00 Source Synch Input Output C13 VSS Power Other B5 VSS Power Other C14 D52 Source Synch Input Output B6 DO5 Source Synch Input Output C15 D51 Source Synch Input Output B7 D06 Source Synch Input Output C16 vss Power Other B8 VSS Power Other C17 DSTBP3 Source Synch Input Output B9 DSTBPO Source Synch Input Output C18 D54 Source Synch Input Output B10 D10 Source Synch Input Output C19 VSS Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land
112. r Input REQ3 K6 Source Synch Input Output TESTHI4 G27 Power Other Input REQ4 Je Source Synch Input Output TESTHI5 G26 Power Other Input RESERVED A20 TESTHI6 G24 Power Other Input RESERVED AC4 TESTHI7 F24 Power Other Input RESERVED AE4 THERMTRIP M2 Asynch CMOS Output RESERVED AE6 TMS AC1 TAP Input Datasheet Land Listing and Signal Descriptions intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name Bes n Direction Land Name Eo Bitte done Direction TRDY E3 Common Clock Input VCC AF22 Power Other TRST AG1 TAP Input VCC AF8 Power Other VCC AA8 Power Other VCC AF9 Power Other VCC AB8 Power Other VCC AG11 Power Other VCC AC23 Power Other VCC AG12 Power Other VCC AC24 Power Other VCC AG14 Power Other VCC AC25 Power Other VCC AG15 Power Other VCC AC26 Power Other VCC AG18 Power Other VCC AC27 Power Other VCC AG19 Power Other VCC AC28 Power Other VCC AG21 Power Other VCC AC29 Power Other VCC AG22 Power Other VCC AC30 Power Other VCC AG25 Power Other VCC AC8 Power Other VCC AG26 Power Other VCC AD23 Power Other VCC AG27 Power Other VCC AD24 Power Other VCC AG28 Power Other VCC AD25 Power Other VCC AG29 Power Other VCC AD26 Power Other VCC AG30 Power Other VCC AD27 Power Other VCC AG8 Power Other VCC AD28
113. r Other vss AK10 Power Other VSS AN17 Power Other VSS AK13 Power Other VSS AN2 Power Other VSS AK16 Power Other VSS AN20 Power Other VSS AK17 Power Other VSS AN23 Power Other VSS AK2 Power Other vss AN24 Power Other vss AK20 Power Other vss AN27 Power Other vss AK23 Power Other vss AN28 Power Other vss AK24 Power Other vss B1 Power Other vss AK27 Power Other vss B11 Power Other vss AK28 Power Other vss B14 Power Other vss AK29 Power Other vss B17 Power Other 49 50 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name E No AR Direction Land Name zd Butte oos Direction VSS B20 Power Other vss H11 Power Other vss B24 Power Other vss H12 Power Other vss B5 Power Other vss H13 Power Other vss B8 Power Other vss H14 Power Other vss C10 Power Other vss H17 Power Other vss C13 Power Other vss H18 Power Other vss C16 Power Other vss H19 Power Other vss C19 Power Other vss H20 Power Other vss C22 Power Other vss H21 Power Other vss C24 Power Other vss H22 Power Other vss C4 Power Other VSS H23 Power Other VSS C7 Power Other vss H24 Power Other vss D12 Power Other vss H25 Power Other vss D15 Power Other vss H26 Power Other vss D18 Power Other vss H27 Power Other vss D21 Power Other vss H28 Power Other
114. r TESTHI signals TESTHI13 cannot be grouped with other TESTHI signals However use of boundary scan test will not be functional if these lands are connected together For optimum noise margin all pull up resistor values used for TESTHI 13 11 10 7 0 lands should have a resistance value within 20 of the impedance of the board transmission line traces For example if the nominal trace impedance is 50 Q then a value between 40 and 60 Q should be used Datasheet Electrical Specifications n tel 2 5 2 5 1 Table 3 Datasheet Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability ca
115. ransition to the lower VID While in Extended HALT state the processor will process bus snoops The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus ratio back to the original value Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle The processor will issue two Stop Grant Acknowledge special bus cycles once for each die Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state All processor cores will enter the Stop Grant state once the STPCLK pin is asserted Additionally all processor cores must be in the Stop Grant state before the deassertion of STPCLK Since the GTL signals receive power from the FSB these signals should not be driven allowing the level to return to V for minimum power drawn by the termination resistors in this state In addition all other input signals on the FSB should be driven to the inactive state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur
116. re speed may have different default VID settings This is reflected by the VID Range values provided in Table 4 Refer to the Intel Core 2 Extreme Quad Core Processor QX6000 Sequence and Intel Core 2 Quad Processor Q6000 Sequence Specification Update for further details on specific valid core frequency and VID values of the processor Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Extended HALT State The processor uses six voltage identification signals VID 7 0 to support automatic selection of power supply voltages Table 2 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 7 0 11111111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself The Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID 7 0 VID7 and VIDO are not used on the processor VIDO and VID7 are strapped to Vss on the processor package VIDO and VID7 must be connected to the VR controller for compatibility with future processors The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load lin
117. rm reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple utilized by the process
118. rposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Signals Configuration Option Signal 3 Output tristate SMI Execute BIST A3 Disable dynamic bus parking A25 Symmetric agent arbitration ID BRO RESERVED A 8 5 A 24 11 A 35 26 NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core per die within the package Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 21 for a visual representation of the processor low power states 83 intel Features Figure 21 Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Extended HALT or HALT Normal State INIT BINIT INTR NMI SMI State Normal Execution RESET FSB interrupts BCLK running Snoops and interrupts allowed Snoop Snoop STPCLK STPCLK sni cea o iced
119. rred to as On Demand mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Clovertown processor s must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the 1A32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same 1A32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 596 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode Datasheet m Thermal Specifications and Design Considerations n tel 5 2 4 5 2 5 Datasheet PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification
120. s as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 7 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Sheet 1 of 2 Signal Group Type Signals GTL Common Synchronous to Clock Input BCLK 1 0 BPRI DEFER RESET RS 2 0 TRDY GTL Common Synchronous to ADS BNR BPM 5 0 BPMb 3 0 BRO DBSY Clock 1 0 BCLK 1 0 DRDY HIT HITM LOCKA Signals Associated Strobe REQ 4 0 A 16 3 4 amp ADSTB0 3 GTL Source Synchronous to A 35 17 ADSTB1 Synchronous I O assoc strobe D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Synchronous to GTL Strobes BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 Datasheet Electrical Specifications Table 7 Table 8 Table 9 Datasheet intel FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals A20M IGNNE INIT LINTO INTR LINT1 NMI SMI CMOS STPCLK PWRGOOD TCK TDI TMS TRST BSEL 2 VID 7 0 Open Drain FERR PBE IERR THERMTRIP TDO Output Open Drain 4 Input Output POCHI FSB Clock Clock BCLK 1 0 ITP CLK 1 0 VCC VTT VCCA VCCIOPLL VCCPLL VSS VSSA GTLREF 3 0 COMP 8 3 0 RESERVED power Other TESTHI 13 11 10 7 0 VCC SENSE
121. se tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families The GTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical O or a logical 1 GTLREF must be generated on the motherboard see Table 14 for GTLREF specifications Termination resistors R r for GTL signals are provided on the processor silicon and are terminated to V m Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the motherboard for most GTL signals FSB Signal Groups The front side bus signals have been combined into groups by buffer type GTL input signals have differential input buffers which use GTLREF 3 0 as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL I O group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and addres
122. specifications On observing active RESET all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RESERVED All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss Vmr or to any other signal including each other can result in component malfunction or incompatibility with future processors 67 Table 25 68 intel Land Listing and Signal Descriptions Signal Description Sheet 7 of 9 Name RS 2 0 Type Input Description RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins lands of all processor FSB agents SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this signal to determine if the processor is present SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Ac
123. stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BRO Input Output BRO drives the BREQO signal in the system and is used by the processor to request the bus During power on configuration this signal is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated BSEL 2 0 Output The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 16 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these signals including termination recommendations refer to Section 2 7 2 COMP8 COMP 3 0 Analog COMP 3 0 and COMP8 must be terminated to Vss on the system board using precision resistors Datasheet 63 Table 25 64 intel Land Listing and Signal Descriptions Signal Description Sheet 3 of 9 Name D 63 0 Type Input Output Description D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins lands on all such ag
124. t BNR Block Next Request is used to assert a bus stall by any bus agent unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions 62 Datasheet Land Listing and Signal Descriptions intel Table 25 Signal Description Sheet 2 of 9 Name BPM 5 0 BPMb 3 0 Type Input Output Description BPM 5 0 and BPMb 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 and BPMb 3 0 should connect the appropriate pins lands of all processor FSB agents BPM 3 0 are associated with core 0 BPMb 3 0 are associated with core 1 BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor These signals do not have on die termination Refer to Section 2 5 2 for termination requirements BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins lands of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to
125. t has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level l n tel Introduction 10 Front Side Bus refers to the interface between the processor and system core logic a k a the chipset components The FSB is a multiprocessing interface to processors memory and I O Processor Terminology Commonly used terms are explained here for clarification Intel Core 2 Extreme quad core processor QX6000 sequence Quad core processor in the FC LGA6 package with a 2x4 MB L2 cache Intel Core 2 quad processor Q6000 sequence Quad core processor in the FC LGA6 package with a 2x4 MB L2 cache Processor For this document the term processor is the generic form of the Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 quad processor Q6000 sequence The processor is a single package that contains one or more execution units Keep out zone The area on or near the processor that system design can not utilize Processor core Processor core die with integrated L2 cache LGA775 socket The processor mates with the system board through a surface mount 775 land LGA socket Integrated he
126. ted inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor s heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides S S 97 98 Debug Tools Specifications Datasheet
127. tel SANTA CLARA CA 95052 8119 EY l MEET or 3 C88285 DO NOT SCALE DRAWING DEPARTMENT ATD TIME DRAWING NUMBER SIZE A beue 5 1 02 23 05 DATE DATE 02 23 05 DATE DATE FINISH M MANUSHAROW DESIGNED BY DRAWN BY N WALSH CHECKED BY APPROVED BY MATERIAL UNLESS OTHERWISE SPECIFIED INTERPRET DIMENSIONS AND TOLERANCES THIRD ANGLE PROJECTION COMMENTS go 2e3 c p E MAX 31 55 31 55 2 3 2 3 4 242 2 593 MILLIMETERS MIN 31 45 31 45 33 9 33 9 2 2 2 2 3 806 33 93 BASIC 34 88 BASIC 16 965 BASIC 17 44 BASIC 1 17 BASIC 1 09 BASIC 0 82 0 14 SYMBOL 8 8 9 I P FRONT VIEW OM vera B SCALE 50 1 32 Datasheet Package Mechanical Specifications n te Figure 8 Processor Package Drawing Sheet 2 of 3 o uc ui l a o m lt PILA C88285 w C88285 DO NOT SCALE DRAWING fucer 2 oF 3 STZE DRAWING WONDER lt oL C SCALE 20 1 0 021 Heje 2200 MISSION COLLEGE BLVD P 0 BOX 58119 cote intel M F SCALE 60 1 DETAIL DEPARTMENT ATD
128. ther AF8 VCC Power Other AD30 VCC Power Other AF9 VCC Power Other AE1 TCK TAP Input AF10 VSS Power Other AE2 VSS Power Other AF11 VCC Power Other 58 Datasheet Land Listing and Signal Descriptions intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment n Land Name ue Direction pcs Land Name m Direction AF12 VCC Power Other AG21 VCC Power Other AF13 VSS Power Other AG22 VCC Power Other AF14 VCC Power Other AG23 VSS Power Other AF15 VCC Power Other AG24 VSS Power Other AF16 VSS Power Other AG25 VCC Power Other AF17 VSS Power Other AG26 VCC Power Other AF18 VCC Power Other AG27 VCC Power Other AF19 VCC Power Other AG28 VCC Power Other AF20 VSS Power Other AG29 VCC Power Other AF21 VCC Power Other AG30 VCC Power Other AF22 VCC Power Other AH1 VSS Power Other AF23 VSS Power Other AH2 RESERVED AF24 VSS Power Other AH3 VSS Power Other AF25 VSS Power Other AH4 A324 Source Synch Input Output AF26 vss Power Other AH5 A33 Source Synch Input Output AF27 VSS Power Other AH6 VSS Power Other AF28 VSS Power Other AH7 VSS Power Other AF29 VSS Power Other AH8 VCC Power Other AF30 VSS Power Other AH9 VCC Power Other AG1 TRST TAP Input AH10 VSS Power Other AG2 BPM3 Common Clock Input Output AH11 VCC Power Other AG3 BPM5 Common Clock Input Output AH12 VCC Power
129. tion frequencies Datasheet Electrical Specifications 2 7 2 Table 16 2 7 3 Datasheet FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 16 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The Intel Core 2 Extreme Quad Core processor QX6800 QX6700 and Intel Core 2 Quad processors Q6600 and Q6700 operate at a 1066 MHz FSB frequency selected by a 266 MHz BCLK 1 0 frequency The Intel Core 2 Extreme Quad Core processor QX6850 operates at 1333 MHz FSB frequency selected by a 333 MHz BCLK 1 0 frequency Individual processors will only operate at their specified FSB frequency BSEL 2 0 Frequency Table for BCLK 1 0 BSEL2 L BSEL1 L BSELO L FSB Frequency 266 MHz RESERVED RESERVED RESERVED RESERVED RESERVED m I I ri r I RESERVED I I IZ zr ri r i E E E e 333 MHz Phase Lock Loop PLL and Filter An on die PLL filter solution will be implemented on the processor The VCCPLL input is used for the PLL Refer to Table 4 for DC specifications 27 intel 2 7 4 Table 17 Table 18 Electrical Specifications BCLK 1 0 Specifications Front
130. tivate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT See Section 5 2 4 for more details PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins lands of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB0 RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper
131. top LGA775 Socket for more information The voltage supply for these signals must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid The VID signals are needed to support the processor voltage specification variations See Table 2 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VID SELECT Output This land is tied high on the processor package and is used by the VR to choose the proper VID table Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information 69 intel Table 25 Land Listing and Signal Descriptions Signal Description Sheet 9 of 9 Name Type Description This input should be left as a no connect in order for the processor VRDSEL Input to boot The processor will not boot on legacy platforms where this land is connected to Vss VSS are the ground pins for the processor and should be connected VSS Input to the system ground plane VSSA Input VSSA is the isolated ground for internal PLLs VSS SENSE is an isolated low impedance connection to processor VSS SENSE Output core Vss It can be used to sense or measure ground near the silicon with little noise This land is provided as a voltage regulator feedback sense point for VSS
132. ualization Technology VT The processor s front side bus FSB uses a split transaction deferred reply protocol like the Intel Pentium 4 processor The FSB uses Source Synchronous Transfer SST of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10 7 GB s The processor uses some of the infrastructure already enabled by the 775 VR CONFIG 05 platforms including heatsink heatsink retention mechanism and Socket Supported platforms may need to be refreshed to ensure the correct voltage regulation VRD11 and PECI support is enabled Manufacturability is a high priority hence mechanical assembly may be completed from the top of the baseboard and should not require any special tooling The processor includes an address bus power down capability that removes power from the address and data signals when the FSB is not in use This feature is always enabled on the processor Terminology A 3t symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrup
133. up resistor provides Vor to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL The boxed processor s fanheat sink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentation or on the system board itself Figure 27 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from the center of the processor socket Datasheet Boxed Processor Specifications intel Figure 26 Boxed Processor Fan Heatsink Power Cable Connector Description GND 12 V SENSE CONTROL G N Straight square pin 4 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pitch 0 025 square pin width Match with straight pin friction lock header on mainboard Table 32 Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12 V 12 volt fan power supply
134. ure to adhere to this specification can affect the long term reliability of the processor 17 m n tel Electrical Specifications 2 5 2 DC Voltage and Current Specification Table 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 2 VID Range VID 0 8500 1 5 V 3 Processor Number Vcc for 775 VR CONFIG 05 QX6850 3 00 GHz Vcc QX6800 2 93 GHz Refer ES Table 5 and V 4 5 6 QX6700 2 66 GHz oe Q6700 2 66 GHz Q6600 2 40 GHz Vcc BooT Default Vcc voltage for initial power up 1 10 V VccPLL PLL Vcc 5 1 50 5 Processor Number Ice for 775 VR CONFIG 05B QX6850 3 00 GHz 125 a 8 QX6800 2 93 GHz 125 QX6700 2 66 GHz 125 lcc Q66007 2 40 GHz 115 Processor Number Ice for 775_VR_CONFIG_05A 06700 2 66 GHz 115 06600 2 40 GHz 115 Itcc lec TCC active lec A 10 FSB termination voltage Mu DC AC specifications NES ee 2 Y ium VTT OUT LEFT and DC Current that may be drawn from 580 mA VTT OUT RIGHT VIT OUT LEFT and VIT OUT RIGHT per pin lec Ice for VT supply before Vcc stable E m 8 0 A 13 M Icc for Vr supply after Vcc stable 7 0 Ice vccPLL lec for PLL land m 130 mA Icc GTLREF lec for GTLREF EL 200 pA NOTES 1 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data 2 3 18 These specifications will be updated with characterized data from silico
135. ut signals GTLREF is used by the GTL receivers to determine if a signal is a logical 0 or logical 1 Datasheet 65 intel Table 25 66 Land Listing and Signal Descriptions Signal Description Sheet 5 of 9 Name HIT HITM Type Input Output Input Output Description HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR IGNNE Output Input IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 5 2 for termination reguirements IGNNE Ignore Numeric Error is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is de asserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an async
136. vss D24 Power Other vss H3 Power Other vss D3 Power Other vss H6 Power Other vss D5 Power Other vss H7 Power Other vss D6 Power Other vss H8 Power Other vss D9 Power Other vss H9 Power Other VSS E11 Power Other VSS J4 Power Other VSS E14 Power Other VSS J7 Power Other VSS E17 Power Other vss K2 Power Other vss E2 Power Other vss K5 Power Other vss E20 Power Other vss K7 Power Other vss E25 Power Other vss L23 Power Other vss E26 Power Other vss L24 Power Other vss E27 Power Other vss L25 Power Other vss E28 Power Other vss L26 Power Other vss E8 Power Other vss L27 Power Other vss F10 Power Other vss L28 Power Other vss F13 Power Other vss L29 Power Other vss F16 Power Other vss L3 Power Other vss F19 Power Other vss L30 Power Other vss F22 Power Other vss L6 Power Other vss F4 Power Other vss L7 Power Other vss F7 Power Other vss M1 Power Other VSS H10 Power Other vss M7 Power Other Datasheet Land Listing and Signal Descriptions intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Buffer Type Direction Land Name Buffer Type Direction VSS N3 Power Other VSS WA Power Other VSS N6 Power Other vss W7 Po
137. wer Other VSS N7 Power Other VSS Y2 Power Other VSS P23 Power Other VSS Y5 Power Other VSS P24 Power Other vss Y7 Power Other VSS P25 Power Other VSS_MB_ REGULATION AN6 Power Other Output vss P26 Power Other VSS_SENSE AN4 Power Other Output VSS P27 Power Other e VSSA B23 Power Other VSS P28 Power Other VIT A25 Power Other VSS P29 Power Other VIT A26 Power Other VSS P30 Power Other VIT A27 Power Other VSS P4 Power Other VIT A28 Power Other VSS P7 Power Other VIT A29 Power Other VSS R2 Power Other VIT A30 Power Other VSS R23 Power Other VIT B25 Power Other VSS R24 Power Other VIT B26 Power Other VSS R25 Power Other VIT B27 Power Other VSS R26 Power Other VIT B28 Power Other VSS R27 Power Other VIT B29 Power Other VSS R28 Power Other VIT B30 Power Other VSS R29 Power Other VIT C25 Power Other VSS R30 Power Other VIT C26 Power Other VSS R5 Power Other VIT C27 Power Other VSS R7 Power Other VIT C28 Power Other VSS T3 Power Other VIT C29 Power Other VSS T6 Power Other VIT C30 Power Other VSS T7 Power Other VIT D25 Power Other VSS U7 Power Other VIT D26 Power Other VSS V23 Power Other VTT D27 Power Other VSS V24 Power Other VTT D28 Power Other VSS V25 Power Other VIT D29 Power Other VSS V26 Power Other VIT D30 Power Other VSS V27 Power Other VTT_OUT vss V28 Power Other LEFT J1 Power Other Output VSS V29 Power Other UI AA1 Power Other Output VSS V3 Power Other VSS V30 Power Other VTT SEL F27 Power Other Output
138. when the processor detects a snoop on the FSB see Section 6 2 4 While in the Stop Grant State SMI INIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process a FSB snoop 85 intel 6 2 4 1 6 2 4 2 86 Extended HALT Snoop or HALT Snoop State Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state If Extended HALT state is not enabled in the BIOS the default Snoop State entered will be the HALT Snoop State Refer to the sections below for details on HALT Snoop State Grant Snoop State and Extended HALT Snoop State HALT Snoop State Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state During a snoop transaction the processor enters the HALT Snoop State Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT Power Down state as appropriate Extended HALT Snoop State The Extended HALT Snoop State is the default Snoop State when the Extended HALT state is enabled via the BIOS The processor will
139. ysical location of each signal on the package land array top view Table 23 is a listing of all processor lands ordered alphabetically by land signal name Table 24 is also a listing of all processor lands the ordering is by land number Datasheet 39 m n tel Land Listing and Signal Descriptions Figure 13 land out Diagram Top View Left Side 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC vss vss VCC AK vss vss vss vss VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC vss VCC VCC VSS VSS VCC AH VCC VCC VCC VCC VCC VCC VSS VSS VCC Vee VSS VCC VCC VSS VSS VCC AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VCC VCC VCC VCC VCC VCC AB VSS VSS VSS VSS VSS VSS VSS VSS AA VSS VSS VSS VSS VSS VSS VSS VSS Y VCC VCC VCC VCC VCC VCC VCC VCC w VCC VCC VCC VCC VCC VCC VCC VCC v VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS V

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