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Fujitsu Intel Xeon 5080

1. r S 9 L 8 39 15s EIERE EE EEN 90 DOEN q en EE 2011 N 804 NId33 1H9I3H 1N3NOdMOO XVN MH vG Z 001 00661 SHYOSLVTd 3AOBY ONY NZ N03 NI433y 1HDI3H N3NOdHOD XA WH 80 S 002 26196 SEL Q3NOTIV 1N3N3OV1d LN3NOdHOD CUVOYIHLON EW STEET ECH V 006711 Le seen put 803 NMOHS QHYOB 1831 WW Ion 21 1 88 66 100711 i zer g ost ERD 0062 mei 009 1 mei 929 1 90 K 698 lt 10001 9 AINO 1 p 100271 380dUNd NOILVHISITII 04 806 NHOHS 3NI1100 ONIYdS 3 10011 009 ie 1 SI 22 Bese ge 08 8 ix TI 2X 2 171 NOISYJA ISS NOILY21419348 AVG 91N0419313 NIHL 3H1 NO Q3SV8 34V SNOISNIN Q 3S3H1 omio41y Td ae ONY CU AN S34 2NOOROO AVA NN 89 eee SE 10423 3diSXova QHVOEHSHION NOLLYNOdIOD 13 181 4O AN3SNOD N3LLLUA 80184 JHL LOOHLIM 138019810 38 LON AYN S1N31N02 SLI QNY 3248014403 NY 038019910 EWEN 90 Azyl am 1Y91S5 on ena 9 L 8 Dual Core Intel Xeon Processor 5000 Series Datasheet 94 intel 3 30 Y INS TAVIS 10N 00 INON Ly NL MVNO X 3002 sevo lari ATNO 32N383338 04 NMOHS 3NI1100 CH AINO 310H 9NIINDnON YOSSIIOYd V3uV SIHL NI SJJOQNYIS SISSVHO YO S310H ONIINDnON QHVOB ON 328303438 04 NMOHS 310H O
2. ay m L DWG NO C88287 3 Y 2 lt 5 ile gu 9 5 ES Ss EOS 2 gt 2 Ei m E 33 88 E Tim ER SC 000000000 5 5 0000000000000000 aza 000000000000000000000 M f ea dees eu zm E san S ES di ke 2 du Q z ES e a a S gt x ma lt C 36 Dual Core Intel Xeon Processor 5000 Series Datasheet m Mechanical Specifications n tel 3 2 3 3 Table 3 1 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements A thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 3 4 for keepout zones Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly mechanical stress testing or standard drop and shipping conditions The heatsink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain the heatsink to processor thermal interface Also any mechanical system or component testing should not exceed these limits The processor package substrate sh
3. Description Min Frequency Nominal Frequency Max Frequency Unit PWM Control 21 000 25 000 28 000 Hz Frequency Range Fan Specifications for 4 pin Active CEK Thermal Solution S Typ Max Max Description Min Steady Steady Startup Unit 12 V 12 volt fan power supply 10 8 12 12 13 2 V IC Fan Current Draw N A 1 1 25 1 5 A SENSE SENSE frequency 2 2 2 2 Pulses per fan revolution Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution PIN 3 PIN4 PIN 2 j LE Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution Pin Number Signal Color 1 Ground Black 2 Power 12 V Yellow 3 Sense 2 pulses per revolution Green 4 Control 21 KHz 28 KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will be available in two product configurations Each configuration will require unique design considerations Meeting the processor s temperature specifications is also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specifications are found in Chapter 6 Thermal Specifications of this document Dual Core Intel Xeon Processor 5000 Series Datasheet Boxed Processor Specifications n tel 8 3 2 1 8 3 2 2 8 3 2 3 8 4 1U Passive 2U Active Combination Heat Sink Solution 1U Rack Passive In the 1U configuration it is assumed that a chassis
4. Land Name pos E x Direction Land Name ue m Direction DO2 A4 Source Sync Input Output D45 E22 Source Sync Input Output DO3 C6 Source Sync Input Output D46 D22 Source Sync Input Output DO4 A5 Source Sync Input Output D47 G22 Source Sync Input Output DO5 B6 Source Sync Input Output D48 D20 Source Sync Input Output DO6 B7 Source Sync Input Output D49 D17 Source Sync Input Output DO7 A7 Source Sync Input Output D50 A14 Source Sync Input Output DO8 A10 Source Sync Input Output D51 C15 Source Sync Input Output DO9 All Source Sync Input Output D52 C14 Source Sync Input Output D10 B10 Source Sync Input Output D53 B15 Source Sync Input Output D11 C11 Source Sync Input Output D543 C18 Source Sync Input Output D12 D8 Source Sync Input Output D55 B16 Source Sync Input Output D13 B12 Source Sync Input Output D56 A17 Source Sync Input Output D14 C12 Source Sync Input Output D573 B18 Source Sync Input Output D15 D11 Source Sync Input Output D58 C21 Source Sync Input Output D16 G9 Source Sync Input Output D59 B21 Source Sync Input Output D17 F8 Source Sync Input Output D60 B19 Source Sync Input Output D18 F9 Source Sync Input Output D61 A19 Source Sync Input Output D19 E9 Source Sync Input Output D62 A22 Source Sync Input Output D20 D7 Source Sync Input Output D63 B22 Source Sync Input Output D21 E10 Sour
5. GTLREF VTT 2 A20M IGNNE INIT PWRGOOD SMI STPCLK A 35 3 ADS ADSTB 1 0 AP 1 0 BINIT TCK TDI TMS1 TRST VITPWRGD BNR BPM 5 0 BPRI BR 1 0 D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPRZ HIT HITM IERR LINTO INTR LINT1 NMI LOCK MCERR RESET REQ 4 0 RS 2 0 RSP TRDY Notes 1 These signals also have hysteresis added to the reference voltage See Table 2 14 for more information 2 Use Table 2 15 for signal FORCEPR specifications GTL Asynchronous and AGTL Asynchronous Signals Input signals such as A20M FORCEPR IGNNEZ INIT LINTO INTR LINT1 NMI SMI and STPCLK utilize GTL input buffers Legacy output FERR PBE and other non AGTL signals IERRz THERMTRIP and PROCHOT utilize GTL output buffers All of these asynchronous GTL signals follow the same DC requirements as AGTL signals however the outputs are not driven high during the electrical O to 1 transition by the processor FERR PBE IERR and GNNE have now been defined as AGTL asynchronous signals as they include an active p MOS device Asynchronous GTL and asynchronous AGTL signals do not have setup or hold time specifications in relation to BCLK 1 0 however all of the asynchronous GTL and asynchronous AGTL signals are required to be asserted deasserted for at least six BCLKs in order for the processor to recognize them See Tab
6. 1 0 Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edge Strobes are associated with signals as shown below Signals Associated Strobes REQ 4 0 A 16 3 A 35 17 ADSTBO ADSTB1 AP 1 0 1 0 AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 signals A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all Dual Core Intel Xeon Processor 5000 series FSB agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 A 35 24 APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 APO BCLK 1 0 The differential bus clock pair BCLK 1 0 Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss Dual Core Intel Xeon Processor 5000 Series Datasheet 61 Bi intel E Table 5 1 Signal Definitions Sheet 2 of 8 Name Type Description Notes BINIT 1 0 BINIT Bus Initializ
7. Signals AGTL Common Clock Input Synchronous to BCLK 1 0 BPRI DEFER RESET RS 2 0 RSP TRDY AGTL Common Clock I O Synchronous to BCLK 1 0 ADS AP 1 0 BINIT 2 BNR 2 BPM 5 0 BR 1 0 DBSY DP 3 0 DRDY HIT 2 HITM 2 LOCK MCERR 2 AGTL Source Synchronous I O Synchronous to assoc strobe Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 DSTBP2 DSTBN2 D 47 32 DBI2 D 63 48 DBI3 DSTBP3 DSTBN3 AGTL Strobes I O Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 AGTL Asynchronous Output Asynchronous FERR PBE ERR PROCHOT GTL Asynchronous Input Asynchronous A20M FORCEPR IGNNEZ INIT LINTO INTR LINT1 NMI SMI STPCLK GTL Asynchronous Output Asynchronous THERMTRI P FSB Clock Clock BCLK1 BCLKO TAP Input Synchronous to TCK TCK TDI TMS TRST TAP Output Power Other Synchronous to TCK Power Other TDO BSEL 2 0 COMP 7 0 GTLREF ADD C 1 0 GTLREF DATA C 1 0 LL ID 1 0 MS ID 1 0 PWRGOOD Reserved SKTOCC TEST BUS TESTHI 11 0 THERMDA THEMRDA2 THERMDC THERMDC2 Vcc VccA VcciopLL VCC DIE SENSE VCC DIE SENSE2 VID 5 0 VID SELECT VSS DIE SENSE VSS DIE SENSE2 Vss Vssa Ver VITOUT VTTPWRGD Notes 1 Refer to Section 5 for signal descri
8. Tcontrol is a temperature specification based on a temperature reading from the thermal diode The value for Tcontrol will be calibrated in manufacturing and configured for each processor The Tcontrol value is set identically for both processor cores The Tcontrol temperature for a given processor can be obtained by reading the A32 TEMPERATURE TARGET MSR in the processor The Tcontrol value that is read from the 1A32 TEMPERATURE TARGET MSR must be converted from Hexadecimal to Decimal and added to a base value of 60 C The value of Tcontrol may vary from 0x00h to Ox1Eh When Tdiode is above Tcontrol then TcAse must be at or below Tcase max as defined by the thermal profile Refer to Figure 6 1 Figure 6 2 and Figure 6 3 Table 6 2 Table 6 3 Table 6 5 Table 6 6 and Table 6 8 Otherwise the processor temperature can be maintained at or below Tcontrol Thermal Diode The Dual Core Intel Xeon Processor 5000 series incorporates an on die PNP transistor whose base emitter junction is used as a thermal diode one per core with its collector shorted to Ground A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control Table 6 9 Table 6 11 and Table 6 12 provide the diode parameters and interface specifications Two different sets of diode parameters are listed in Table 6 9 and Table 6 11 The Diode Model parameters Table 6 9 apply to traditional thermal
9. 6310N5310N Nid i a 00 m DR r 8 2 0 xw G OR 03N19002 mp CORO D 62 1 WOl1VSOdHO 13181 JO 1835802 W311134 80184 JHI LNOHLIM 0314100N BO Q31v1d 10 3200034384 039012810 3 LON AVN 1N31N02 SLI NV 398301402 NI 035012610 SI LI NOLLVMHOINI 1Y11N301 JNO2 NOILVYOJYOJ 131NI SNIYINO 9NIMYAO SINL FUERTES Im p t ntel Figure 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink Dual Core Intel Xeon Processor 5000 Series Datasheet 98 C Boxed Processor Specifications n tel 8 2 2 8 2 2 1 8 2 3 8 3 8 3 1 Boxed Processor Heat Sink Weight Thermal Solution Weight The 1U passive 2U active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams Note that this is per processor so a dual processor system will have up to 2100 grams total mass in the heat sinks This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration See Section 3 for details on the processor weight Boxed Processor Retention Mechanism and Heat Sink Support CEK Baseboards and chassis designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor Refer to the Server System Infrastructure Specification SSI EEB 3 6 TEB 2 1 or CEB 1 1 These specification can be found at http www ssiforum org Fi
10. FSB is a quad pumped bus running off a 166 MHz system clock making 5 3 GBytes per second data transfer rates possible In addition enhanced thermal and power management capabilities are implemented including Thermal Monitor TM1 and Enhanced Intel SpeedStep technology These technologies are targeted for dual processor DP systems in enterprise environments TM1 provides efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep technology provides power management capabilities to servers and workstations The Dual Core Intel Xeon Processor 5000 series also include Hyper Threading Technology HT Technology resulting in four logical processors per package This feature allows multi threaded applications to execute more than one thread per physical processor core increasing the throughput of applications and enabling improved scaling for server and workstation workloads More information on Hyper Threading Technology can be found at http www intel com technology hyperthread Other features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution Advanced Transfer Cache enhanced floating point and multi media units and Streaming SIMD Extensions 3 SSE3 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The Advanced Transfer Cache in each core is a 2 MB level 2 L2 cache The floating point and multi media units include 128 bi
11. While in the Enhanced HALT state the processor will process bus snoops The processor exits the Enhanced HALT state when a break event occurs When the processor exits the Enhanced HALT state it will first transition the VID to the original value and then change the bus ratio back to the original value Dual Core Intel Xeon Processor 5000 Series Datasheet Features Figure 7 1 7 2 3 intel The Enhanced HALT state must be enabled by way of the BIOS for the processor to remain within its specifications The Enhanced HALT state requires support for dynamic VID transitions in the platform Stop Clock State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal Stat Enhanced HALT or HALT State N E e INIT BINIT INTR NMI SMI BCLK running SE RESET FSB interrupts Snoops and interrupts allowed A A Snoop Snoop STPCLK STPCLK Event Event Asserted De asserted Occurs Serviced Y Enhanced HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Stop Grant State Snoop Event Occur Stop Grant Snoop State BCLK running BCLK running Snoops and interrupts allowed Snoop Event Serviced Service snoops to caches Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus
12. 0 input with exceptions for spread spectrum clocking The Dual Core Intel Xeon Processor 5000 series utilize differential clocks Table 2 1 contains processor core frequency to FSB multipliers and their corresponding core frequencies Core Frequency to FSB Multiplier Configuration Core ren orsa Core DAD ProcessorNumber Notes 1 16 2 67 GHz 5030 1 2 3 4 1 18 3 GHz 5050 1 2 3 4 Core Frequency to FSB Core Frequency with Notes Multiplier 266 MHz FSB Clock 1 12 3 20 GHz 5063 1 2 3 4 1 12 3 20 GHz 5060 L 2 3 5 1 14 3 73 GHz 5080 1 2 3 Notes 1 Individual processors operate only at or below the frequency marked on the package 2 Listed frequencies are not necessarily committed production frequencies 3 For valid processor core frequencies refer to the Dual Core Intel Xeon Processor 5000 series Specification Update 4 Mid voltage MV processors only 5 The lowest bus ratio supported by the Dual Core Intel Xeon Processor 5000 series is 1 12 Front Side Bus Frequency Select Signals BSEL 2 0 Upon power up the FSB frequency is set to the maximum supported by the individual processor BSEL 2 0 are open drain outputs which must be pulled up to VTT and are used to select the FSB frequency Please refer to Table 2 12 for DC specifications Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the proces
13. 0 0 1 0 1 1 4000 0 0 0 1 0 0 1 0375 1 0 0 1 0 0 1 4125 0 0 0 0 1 1 1 0500 1 0 0 0 1 1 1 4250 0 0 0 0 1 0 1 0625 1 0 0 0 1 0 1 4375 0 0 0 0 0 1 1 0750 1 0 0 0 0 1 1 4500 0 0 0 0 0 0 1 0875 1 0 0 0 0 0 1 4625 1 1 1 1 1 1 OFF 0 1 1 1 1 1 1 4750 1 1 1 1 1 0 OFF 0 H 1 1 1 0 1 4875 1 1 1 1 0 1 1 1000 0 1 1 1 0 1 1 5000 1 1 1 1 0 0 1 1125 0 1 1 1 0 0 1 5125 1 1 T 0 1 1 1 1250 0 1 1 0 1 1 1 5250 1 1 1 0 1 0 1 1375 0 1 1 0 1 0 1 5375 1 1 1 0 0 1 1 1500 0 1 1 0 0 1 1 5500 1 1 1 0 0 0 1 1625 0 1 1 0 0 0 1 5625 1 1 0 1 1 1 1 1750 0 1 0 1 1 1 1 5750 1 1 0 1 1 0 1 1875 0 1 0 1 1 0 1 5875 1 1 0 1 0 1 1 2000 0 1 0 1 0 1 1 6000 Notes 1 When this VID pattern is observed the voltage regulator output should be disabled 2 Shading denotes the expected VID range of the Dual Core Intel Xeon Processor 5000 series 1 0750 V 1 3500 V Table 2 4 Loadline Selection Truth Table for LL 1D 1 0 LL ID1 LL IDO Description 0 0 Reserved 0 1 Dual Core Intel Xeon Processor 5000 Series 1 0 Reserved 1 1 Reserved Note 1 het ID 1 0 signals are used to select the correct loadline slope for the processor 2 These signals are not connected to the processor die 3 A logic 0 is achieved by pulling the signal to ground on the package 4 A logic 1 is achieved by leaving the signal as a no connect on the package Table 2 5 Market Segment Selection Truth Table for MS ID 1 0 MS ID1 MS IDO Description 0 0 Dual Core Inte
14. 12 11 10 9 8 7 6 5 4 3 2 1 SC Address Y x Socket 771 Common Clock Quadrants u Async Top View P P N N M M L L K K J J H H a 7 G F F E E D D C Cc B B ge aj 30 29 28 27 26 25 24 23 22 212019 18 17 16 15 14 13 1211109 8 7 6 5 4 3 2 1 Vo Clocks Data 40 Dual Core Intel Xeon Processor 5000 Series Datasheet Mechanical Specifications Figure 3 8 Processor Land Coordinates Bottom View intel 1234585 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vec Vss gt gt gt gt gt gt gt gt S amp xP zz Address Common Clock Async gt gt gt gt u O rm T amp amp X F Z Z J H CK EZE lt GZS Socket 771 Quadrants Bottom View 2 gt gt gt gt m m z 2 2 P z Z gt g o g m m9 zz c r EsnnaeeSsbEE 4 123 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data V Clocks Dual Core Intel Xeon Processor 5000 Series Datasheet 41 42 Mechanical Specifications Dual Core Intel Xeon Processor 5000 Series Datasheet Land Listing 4 4 1 Land Listing Dual Core I ntel Xeon Processor 5000 Series Land Assignments This section provides sorted land list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor lands ordered alphabetically by land name Table 4 2 is a listing of all proc
15. 2 Forthis pin on Dual Core Intel Xeon Processor 5000 series the maximum number of symmetric agents is two Maximum number of priority agents is zero 3 Forthis pin on Dual Core Intel Xeon Processor 5000 series the maximum number of symmetric agents is two Maximum number of priority agents is one 8 68 Dual Core Intel Xeon Processor 5000 Series Datasheet m Thermal Specifications n tel 6 6 1 Note 6 1 1 Thermal Specifications Package Thermal Specifications The Dual Core Intel Xeon Processor 5000 series require a thermal solution to maintain temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution
16. D35 Source Sync Input Output H3 VSS Power Other G19 DSTBP2 Source Sync Input Output H30 BSEL1 Power Other Output G2 COMP2 Power Other Input H4 RSP Common Clk Input G20 DSTBN2 Source Sync Input Output H5 BR1 Common Clk Input G21 D44 Source Sync Input Output H6 vss Power Other G22 D47 Source Sync Input Output H7 vss Power Other G23 RESET Common Clk Input H8 VSS Power Other G24 TESTHI06 Power Other Input H9 VSS Power Other G25 TESTHIO3 Power Other Input jl VTT OUT Power Other Output G26 TESTHIO5 Power Other Input J10 VCC Power Other G27 TESTHI04 Power Other Input J11 VCC Power Other G28 BCLK1 Clk Input J12 VCC Power Other G29 BSELO Power Other Output J13 VCC Power Other G3 TESTHI 08 Power Other Input J14 VCC Power Other G30 BSEL2 Power Other Output J15 VCC Power Other G4 TESTHI 09 Power Other Input J16 DPO Common Clk Input Output G5 RESERVED J17 DP3 Common Clk Input Output G6 RESERVED J18 VCC Power Other G7 DEFER Common Clk Input J19 VCC Power Other G8 BPRI Common Clk Input J2 COMP4 Power Other Input G9 D16 Source Sync Input Output 20 VCC Power Other H1 GTLREF_ADD_CO Power Other Input J21 VCC Power Other H10 VSS Power Other J22 VCC Power Other H11 vss Power Other 23 VCC Power Other H12 vss Power Other j24 VCC Power Other H13 vss Power Other j25 VCC Power Other H14 vss Power Other J26 VCC Power Other H15 DP1 Common Clk Input Output J27 VCC Power Other Dual Core Intel Xeon Processo
17. DC 1 Hz fpeak 1MHz 66 MHz fcore passband high frequency band CS00141 Notes 1 Diagram not to scale 2 No specifications for frequencies beyond fcore core frequency 3 peak if existent should be less than 0 05 MHz 4 re represents the maximum core frequency supported by the platform h o Dual Core Intel Xeon Processor 5000 Series Datasheet m Electrical Specifications n tel 2 5 Table 2 3 Dual Core Intel Xeon Processor 5000 Series Datasheet Voltage Identification VI D The Voltage Identification VID specification for the Dual Core Intel Xeon Processor 5000 series set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins VID signals are open drain outputs which must be pulled up to Var Please refer to Table 2 12 for the DC specifications for these signals A minimum voltage is provided in Table 2 10 and changes with frequency This allows processors running at a higher frequency to have a relaxed minimum voltage specification The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 3 The Dual Core Intel Xeon Processor 5000 series use six voltage identi
18. Datasheet 33 Mechanical Specifications intel Processor Package Drawing Sheet 1 of 3 Figure 3 2 jO L33Hs laun we 108 00 EENEN D 182992 2 Am uagwnn onimyya 3doo 3oyo azis SIN 4 ONIMVYC S1W3 aui i yniaiyw Aug BO AB Q3AONddY NOIl23fONd 319NV QHIHL Aug Ag 342382 6118 29096 v YAYI VINYS 260 61189 X08 0d i OMIA 3937709 NOISSIN 0022 PELTI aiya AB Nhyud Aug 4a Q3N61 3G REV HT C8828T DWG NO o 12001 110 09 o 1900 02 0 2601 620 28 0 vL O 507 2ISV8 601 9507 2ISV8 LI I 1897 HEED 899 2ISVB 96 91 ele 2ISVH 99 FE 9 11 2ISY8 6 9011 901 EIN e LII 0917 HEY ENZ 16071 180 2 ec 160 180 ec o 6 071 eren IMN He SES o 6 071 eren see 11 Hye BEE r Irir 11 sere AE ele tL sere DA S1N3NWNO2 XVN NIN CSSHONI SU313N TIN TORWAS IV WOLLOG V6 30128 V K EN ALVULSANS JOVI 1NV1V3S SHI o 180071 coz o Z 2001 070 Z aid SHI 2 800 ceoz o Z 007 80 0
19. Factor are listed in Table 6 12 For Dual Core Intel Xeon Processor 5000 series the range of Tdiode Correction Factor is 14 C Thermal Diode Parameters using Diode Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 200 HA 1 n Diode Ideality Factor 1 000 1 009 1 050 2 3 4 RT Series Resistance 2 79 4 52 6 24 Q 2 3 5 Notes 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized across a temperature range of 50 80 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation lpw Ig e9VD nKT _ 1 Where ls saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Ry is provided to allow for a more accurate measurement of the junction temperature Rr as defined includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and external remote diode thermal sensor Rz can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplif
20. Flip Chip Land Grid Array FC LGA6 package that interfaces to the baseboard via a LGA771 socket The package consists of a processor core mounted on a pinless substrate with 771 lands An integrated heat spreader IHS is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together The package components shown in Figure 3 1 include the following 1 Integrated Heat Spreader IHS Thermal Interface Material TI M Processor Core die Package Substrate Ui WN Landside capacitors 6 Package Lands Figure 3 1 Processor Package Assembly Sketch ims Core die TIM Substrate Package Lands io tm Capacitors LGA771 Socket System Board Note This drawing is not to scale and is for reference only 3 1 Package Mechanical Drawings The package mechanical drawings are shown in Figure 3 2 through Figure 3 4 The drawings include dimensions necessary to design a thermal solution for the processor including 1 Package reference and tolerance dimensions total height length width an so forth HS parallelism and tilt Land dimensions Top side and back side component keepout dimensions u WN Reference datums Note All drawing dimensions are in mm in Dual Core Intel Xeon Processor 5000 Series
21. Implementation of Thermal Profile B will result in increased probability of TCC activation and measurable performance loss Furthermore utilization of thermal solutions that do not meet Thermal Profile B do not meet the processor s thermal specifications and may result in permanent damage to the processor 5 Refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for system and environmental implementation details Dual Core I ntel Xeon Processor 5000 Series 667 MHz Thermal Profile A Table Power W Tcase Max C C Power W Tcase Max C C P profile min 4 40 9 50 0 80 57 9 45 50 8 85 59 0 50 51 9 90 60 0 55 52 9 95 61 0 60 53 9 65 54 9 70 55 9 75 56 9 Dual Core Intel Xeon Processor 5000 Series Datasheet 73 e n tel Thermal Specifications Table 6 6 Dual Core Intel Xeon 5000 Series 667 MHz Thermal Profile B Table Power W Tcase Max C C Power W Tcase Max C C P profijb min g 29 6 500 75 61 8 35 51 4 80 63 1 40 52 7 85 64 4 45 54 0 90 65 7 50 55 3 95 67 0 55 56 6 60 57 9 65 59 2 70 60 5 Table 6 7 Dual Core Intel Xeon Processor 5063 MV Thermal Specifications Thermal Minimum Core Frequency Design Power TCASE maximum TCASE Notes W C Launch to FMB 95 5 Refer to Figure 6 3 1 2 3 4 Tabl
22. Intel Xeon Processor 5000 Series 667 MHz Thermal Specifications 72 Dual Core Intel Xeon Processor 5000 Series 667 MHz Thermal Profile A Table 73 Dual Core Intel Xeon 5000 Series 667 MHz Thermal Profile B Table 74 Dual Core Intel Xeon Processor 5063 MV Thermal Specifications sss 74 Dual Core Intel Xeon Processor 5063 MV Thermal Profile Table ss 75 Thermal Diode Parameters using Diode Model 80 Thermal Diode Interface 81 Thermal Diode Parameters using Transistor Model 81 Parameters for Tdiode Correction Factor nemen nnn nn 81 Dual Core Intel Xeon Processor 5000 Series Datasheet 5 intel 7 1 Power On Configuration Option Landes 83 8 1 PWM Fan Frequency Specifications for 4 Pin Active CEK Thermal Solution 100 8 2 Fan Specifications for 4 pin Active CEK Thermal Solution 100 8 3 Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution 100 Dual Core Intel Xeon Processor 5000 Series Datasheet Revision History ntel Revision Description Date 001 Initial release May 2006 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Features Dual Core processor Available at 3 73 GHz processor speed Includes 16 KB Level 1 data cache per core 2 x 16 KB Includes 12 KB Level 1 trace cache per core 2 x 12 KB 2 MB Advanced T
23. Other AK28 VSS Power Other AM12 VCC Power Other AK29 VSS Power Other AM13 VSS Power Other AK3 RESERVED AM14 VCC Power Other AK30 VSS Power Other AM15 VCC Power Other AK4 VIDA Power Other Output AM16 VSS Power Other AK5 VSS Power Other AM17 VSS Power Other AK6 FORCEPR ASync GTL Input AM18 VCC Power Other AK7 VSS Power Other AM19 VCC Power Other AK8 VCC Power Other AM2 VIDO Power Other Output AK9 VCC Power Other AM20 VSS Power Other Dual Core Intel Xeon Processor 5000 Series Datasheet intel Land Listing Table 4 2 Land Listing by Land Number Sheet 4 of 9 pow Land Name c a Direction prd Land Name Noc wd Direction AL1 THERMDA Power Other Output AM21 VCC Power Other AL10 VSS Power Other AM22 VCC Power Other AL11 VCC Power Other AM23 VSS Power Other AL12 VCC Power Other AM24 VSS Power Other AL13 VSS Power Other AM25 VCC Power Other AL14 VCC Power Other AM26 VCC Power Other AL15 VCC Power Other AM27 VSS Power Other AL16 VSS Power Other AM28 VSS Power Other AL17 VSS Power Other AM29 VCC Power Other AL18 VCC Power Other AM3 VID2 Power Other Output AL19 VCC Power Other AM30 VCC Power Other AL2 PROCHOT ASync GTL Output AM4 VSS Power Other AL20 vss Power Other AM5 RESERVED AL21 VCC Power Other AM6 VTTPWRGD Power Other Input AL22 VCC Power Other AM7 VSS Power Other AL23 VSS Power Other
24. Other VCC U8 Power Other VSS AA27 Power Other VCC v8 Power Other VSS AA28 Power Other VCC W23 Power Other VSS AA29 Power Other VCC W24 Power Other VSS AA3 Power Other VCC W25 Power Other VSS AA30 Power Other VCC W26 Power Other VSS AA6 Power Other VCC W27 Power Other VSS AA7 Power Other VSS AB1 Power Other VSS AF30 Power Other VSS AB23 Power Other VSS AF6 Power Other VSS AB24 Power Other VSS AF7 Power Other VSS AB25 Power Other VSS AG10 Power Other VSS AB26 Power Other VSS AG13 Power Other VSS AB27 Power Other VSS AG16 Power Other VSS AB28 Power Other VSS AG17 Power Other VSS AB29 Power Other VSS AG20 Power Other VSS AB30 Power Other VSS AG23 Power Other VSS AB7 Power Other VSS AG24 Power Other VSS AC3 Power Other VSS AG7 Power Other VSS AC6 Power Other VSS AH1 Power Other VSS AC7 Power Other VSS AH10 Power Other VSS AD4 Power Other VSS AH13 Power Other VSS AD7 Power Other VSS AH16 Power Other VSS AE10 Power Other VSS AH17 Power Other VSS AE13 Power Other VSS AH20 Power Other VSS AE16 Power Other VSS AH23 Power Other VSS AE17 Power Other VSS AH24 Power Other VSS AE2 Power Other VSS AH3 Power Other VSS AE20 Power Other VSS AH6 Power Other VSS AE24 Power Other VSS AJ10 Power Other VSS AE25 Power Other VSS AJ13 Power Other VSS AE26 Power Other VSS AJ16 Power Other VSS AE27 Power Other VSS AJ17 Power Other VSS AE28 Power Other
25. Output F25 TESTHIO2 Power Other Input E14 VSS Power Other F26 TESTHI 00 Power Other Input 56 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Land Listing Table 4 2 Land Listing by Land Number Sheet 6 of 9 prd Land Name id WW Direction tg Land Name Ec Direction E15 D33 Source Sync Input Output F27 RESERVED E16 D34 Source Sync Input Output F28 BCLKO Clk Input E17 VSS Power Other F29 RESERVED E18 D39 Source Sync Input Output F3 BRO Common Clk Input Output E19 D40 Source Sync Input Output F30 VIT Power Other E2 VSS Power Other F4 VSS Power Other E20 VSS Power Other F5 RS1 Common Clk Input E21 D42 Source Sync Input Output F6 RESERVED E22 D45 Source Sync Input Output F7 VSS Power Other E23 RESERVED F8 D17 Source Sync Input Output E24 RESERVED F9 D18 Source Sync Input Output E25 VSS Power Other G1 VSS Power Other E26 VSS Power Other G10 GTLREF DATA CO Power Other Input E27 VSS Power Other G11 DBI1 Source Sync Input Output E28 vss Power Other G12 DSTBN1 Source Sync Input Output E29 VSS Power Other G13 D273 Source Sync Input Output E3 TRDY Common Clk Input G14 D29 Source Sync Input Output E30 VIT Power Other G15 D31 Source Sync Input Output G16 D32 Source Sync Input Output H28 VSS Power Other G17 D36 Source Sync Input Output H29 VSS Power Other G18
26. Power Other VCC AL21 Power Other VCC J22 Power Other VCC AL22 Power Other VCC J23 Power Other VCC AL25 Power Other VCC J24 Power Other VCC AL26 Power Other VCC j25 Power Other VCC AL29 Power Other VCC J26 Power Other VCC AL30 Power Other VCC J27 Power Other VCC AL9 Power Other VCC J28 Power Other VCC AM11 Power Other VCC J29 Power Other VCC AM12 Power Other VCC J30 Power Other VCC AM14 Power Other VCC J8 Power Other VCC AM15 Power Other VCC J9 Power Other VCC AM18 Power Other VCC K23 Power Other VCC AM19 Power Other VCC K24 Power Other VCC AM21 Power Other VCC K25 Power Other VCC AM22 Power Other VCC K26 Power Other VCC AM25 Power Other VCC K27 Power Other VCC AM26 Power Other VCC K28 Power Other VCC AM29 Power Other VCC K29 Power Other VCC AM30 Power Other VCC K30 Power Other VCC AM8 Power Other VCC K8 Power Other VCC AM9 Power Other VCC L8 Power Other VCC AN11 Power Other VCC M23 Power Other VCC M24 Power Other VCC W28 Power Other VCC M25 Power Other VCC W29 Power Other VCC M26 Power Other VCC W30 Power Other VCC M27 Power Other VCC W Power Other VCC M28 Power Other VCC Y23 Power Other VCC M29 Power Other VCC Y24 Power Other VCC M30 Power Other VCC Y25 Power Other VCC M8 Power Other VCC Y26 Power Other VCC N23 Power Other VCC Y27 Power Other VCC N24 Power Other VCC Y28 Power Other VCC N25 Power Other VCC Y29 Power Other VCC N26 Power Other VCC Y30 Powe
27. Processor Identification and the CPUID Instruction 241618 IA 32 Intel Architecture Software Developer s Manual Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide c Volume 3B System Programming Guide 64 bit Extension Technology Software Developer s Guide Volume 1 300834 Volume 2 300835 1A 32 Intel Architecture Optimization Reference Manual 248966 Dual Core Intel Xeon Processor 5000 Series Datasheet Introduction i n te l Document Intel Order Number Dual Core Intel Xeon Processor 5000 Series Specifications Update 313065 EPS12V Power Supply Design Guide A Server system Infrastructure SSI http Specification for Entry Chassis Power Supplies www ssiforum org Entry Level Electronics Bay Specifications A Server System Infrastructure SSI http Specification for Entry Pedestal Servers and Workstations www ssiforum org Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design 313062 Guidelines Dual Core Intel Xeon Processor 5000 Series Boundary Scan Descriptive 313064 Language BSDL Model Notes Contact your Intel representative for the latest revision of those documents 8 Dual Core Intel Xeon Processor 5000 Series Datasheet 14 Introduction Dual Core Intel Xeon Processor 5000 Series Datasheet m Electrical
28. QUIHI 200 XXX S20 F SOF mib EIFE 55328013101 118 25056 V vi T YLNVS dil 0313NL TII NI JAV SNOISNINIQ IRAK GIE LEKT 61195 X08 0 d AWTU GH 9013340 LANI woo WISS W hm m MU e 1S11 S1Uvd ol L ij WS DIA ISNY 83d 5812883101 NV SNINOISN3NIQ P O A GIN J0 ONILYY ALITIGVAAVTA Th HOHININ V 3AVH TIVHS LYVd QIHSINIA ALITIOYNWYTA AYOAT 780102 NOTAN Ing I D 310N V V N01123S 80 3 d gI 0T8 0l 80 S INO Nid 03N 18H02 2 0F29 L YS C XE SE I Xp SE I xv Lo H NOI1Y4OdS0 TILNI JO 1N35N02 NJLLINM HOI Hd IHA LDOMLIM Q314I0ON YO 031Y14810 OIONGONdIY 0350125 0 38 LON AYM 51831809 SLI ONY L all aam n t N3013N0 NI 035019510 SI LI NOLLYMJOJNI 1118301 JND2 N011Y804802 DIN SNIVINOD 9NIAYUO SIH j 97 Dual Core Intel Xeon Processor 5000 Series Datasheet Boxed Processor Specifications 430V3H Nid f NOI123fONd 319NY QNIHI 200 T xxx DARE dUOT raf eat 5322083101 118 25056 Y ND VINYS 4809 Par UA NI SHY tens T i Wir SASV HIA 39NVOHODOY NI 61185 xot O d OMG 1939300 NOISSIN 0022 TR Ee sii aS 1S11 S1uvd ASSY Wad 110 NO11d 182530 W38W N 1Y4 ON Will Op d01 HC A ISNY 834 ONIONVETTOL ONY SNINOISN3WIQ P et O AP amp Tn JO ONIIV ALII GVHNYT4 IN WININIM Y 3AVH IIHS L8 d Q3HSINISSALITIGYWNYTY E MOM 280109 2 NOTAN YIII I
29. RESERVED F27 VIT C30 Power Other VTTPWRGD AM6 Power Other Input VIT D25 Power Other 51 intel Land Listing 4 1 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 1 of 9 jc Land Name m Direction p Land Name Ao nd Direction A10 DO8 Source Sync Input Output AB1 VSS Power Other All D09 Source Sync Input Output AB2 IERR ASync GTL Output A12 vss Power Other AB23 vss Power Other A13 COMP0 Power Other Input AB24 VSS Power Other A14 D50 Source Sync Input Output AB25 VSS Power Other A15 VSS Power Other AB26 VSS Power Other A16 DSTBN3 Source Sync Input Output AB27 VSS Power Other A17 D56 Source Sync Input Output AB28 VSS Power Other A18 VSS Power Other AB29 VSS Power Other A19 D61 Source Sync Input Output AB3 MCERR Common Clk Input Output A2 VSS Power Other AB30 VSS Power Other A20 RESERVED ABA A263 Source Sync Input Output A21 VSS Power Other AB5 A24 Source Sync Input Output A22 D62 Source Sync Input Output AB6 Al7 Source Sync Input Output A23 VCCA Power Other Input AB7 VSS Power Other A24 VSS Power Other AB8 VCC Power Other A25 VTT Power Other AC1 TMS TAP Input A26 VTT Power Other AC2 DBR Power Other Output A3 RS2 Common Clk Input AC23 VCC Power Other A4 D02 Source Sync Input Output AC24 V
30. Specifications n tel 2 2 1 2 2 Electrical Specifications Front Side Bus and GTLREF Most Dual Core Intel Xeon Processor 5000 series FSB signals use Assisted Gunning Transceiver Logic AGTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active PMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Platforms implement a termination voltage level for AGTL signals defined as V m Because platforms implement separate power planes for each processor and chipset separate Vcc and Vy supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families The AGTL inputs require reference voltages GTLREF which are used by the receivers to determine if a signal is a logical O or a logical 1 GTLREF must be generated on the baseboard GTLREF is a generic name for GTLREF DATA C 1 0 the reference voltages for the 4X data bus and GTLREF ADD C 1 0 the reference voltages for the 2X address bus and
31. TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI l TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO O TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TEST_BUS Other Must be connected to all other processor TEST BUS signals in the system See the appropriate platform design guideline for termination details 66 Dual Core Intel Xeon Processor 5000 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 7 of 8 intel Name TESTHI 11 0 Type l Description TESTHI 11 0 must be connected to a Vr power source through a resistor for proper processor operation Refer to Section 2 6 for TESTHI grouping restrictions Notes THERMDA THERMDA2 Other Thermal Diode Anode THERMDA connects to processor core 0 THERMDA2 connects to processor core 1 Refer to the appropriate platform design guidelines for implementation details THERMDC THERMDC2 Other Thermal Diode Cathode THERMDC connects to processor core 0 THERMDC2 connects to processor core 1 Refer to the appropriate platform design guidelines for implementation details THERMTRIP Assertion of THERMTRIP Thermal Trip indicates the processor junction temperatur
32. Terror nf T measured X 1 Nactual trim where Terror nf is the offset in degrees C Treasured is in Kelvin Nactual is the measured ideality of the diode and ntrim is the diode ideality assumed by the temperature sensing device In order to improve the accuracy of diode based temperature measurements a new register Tdiode Offset has been added to Dual Core Intel Xeon Processor 5000 series which will contain thermal diode characterization data During manufacturing each processor s thermal diode will be evaluated for its behavior relative to a theoretical diode Using the equation above the temperature error created by the difference Dual Core Intel Xeon Processor 5000 Series Datasheet 79 Table 6 9 80 Thermal Specifications between Mirim and the actual ideality of the particular processor will be calculated This value Tdiode Offset will be programmed into the new diode correction MSR and then added to the Tdiode Base value can be used to correct temperatures read by diode based temperature sensing devices If the Nirim value used to calculating Tdiode Offset differs from the ntrim value used in a temperature sensing device the Terror nf may not be accurate If desired the Tdiode Offset can be adjusted by calculating nactua and then recalculating the offset using the actual Nirim as defined in the temperature sensor manufacturers datasheet The parameters used to calculate the Thermal Diode Tdiode Correction
33. The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe The processor must not be subjected to any static Vcc level that exceeds the Vcc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime lcc max is specified at Vcc max The processor is capable of drawing Icc max for up to 10 ms Refer to Figure 2 2 and Figure 2 3 for further details on the average processor current draw over various time durations FMB is the flexible motherboard guideline These guidelines are for estimation purposes only The current specified is also for HALT and Enhanced HALT State These specifications apply to the PLL power lands VCCA VCCIOPLL and VSSA See Section 2 4 2 for details These parameters are based on design characterization and are not tested This specification represents the total current for GTLREF DATA and GTLREF ADD per core Vr must be provided via a separate voltage source and must not be connected to Vcc This specification is measured at the land Dual Core Intel Xeon Processor 5000 Series Datasheet m Electrical Specifications n tel 11 12 13 14 15 16 17 Minimum VCC and maximum ICC are specified at the maximum processor case temperature TCASE shown in Table 6 1 This specification refers to the total reduction of the load line due to VID transitions below
34. VCC Power Other L1 LINT1 ASync GTL Input N4 RESERVED L2 TESTHI11 ASync GTL Input N5 RESERVED L23 VSS Power Other N6 VSS Power Other L24 VSS Power Other N7 VSS Power Other L25 VSS Power Other N8 VCC Power Other L26 VSS Power Other P1 TESTHI 10 Power Other Input L27 VSS Power Other P2 SMI ASync GTL Input L28 VSS Power Other P23 VSS Power Other L29 VSS Power Other P24 VSS Power Other L3 VSS Power Other P25 VSS Power Other L30 VSS Power Other P26 VSS Power Other L4 A06 Source Sync Input Output P27 VSS Power Other L5 A05 Source Sync Input Output P28 VSS Power Other L VSS Power Other P29 VSS Power Other L7 VSS Power Other P3 INIT ASync GTL Input L8 VCC Power Other P30 VSS Power Other M1 VSS Power Other P4 VSS Power Other M2 THERMTRIP ASync GTL Output P5 RESERVED M23 VCC Power Other P6 A04 Source Sync Input Output M24 VCC Power Other P7 VSS Power Other M25 VCC Power Other P8 VCC Power Other M26 VCC Power Other R1 COMP3 Power Other Input 58 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Land Listing Table 4 2 Land Listing by Land Number Sheet 8 of 9 prd Land Name c a Direction rg Land Name a Direction M27 VCC Power Other R2 VSS Power Other M28 VCC Power Other R23 VSS Power Other M29 VCC Power Other R24 VSS Power Other M3 STPCLK ASync GTL Input R25 VSS Power Other M30 VCC Power Ot
35. VSS AJ20 Power Other VSS AE29 Power Other VSS AJ23 Power Other VSS AE30 Power Other VSS AJ24 Power Other VSS AE5 Power Other VSS AJ27 Power Other VSS AE7 Power Other VSS AJ28 Power Other 48 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Land Listing Table 4 1 Land Listing by Land Name Sheet 7 of 9 Land Name po d dal Direction Land Name yc n Direction VSS AF10 Power Other VSS AJ29 Power Other VSS AF13 Power Other VSS AJ30 Power Other VSS AF16 Power Other VSS AJ4 Power Other VSS AF17 Power Other VSS AK10 Power Other VSS AF20 Power Other vss AK13 Power Other VSS AF23 Power Other VSS AK16 Power Other VSS AF24 Power Other VSS AK17 Power Other VSS AF25 Power Other VSS AK2 Power Other VSS AF26 Power Other VSS AK20 Power Other VSS AF27 Power Other VSS AK23 Power Other VSS AF28 Power Other VSS AK24 Power Other VSS AF29 Power Other VSS AK27 Power Other VSS AF3 Power Other VSS AK28 Power Other VSS AK29 Power Other VSS C10 Power Other VSS AK30 Power Other VSS C13 Power Other VSS AK5 Power Other VSS C16 Power Other VSS AK7 Power Other VSS C19 Power Other VSS AL10 Power Other VSS C22 Power Other VSS AL13 Power Other VSS C24 Power Other VSS AL16 Power Other VSS CA Power Other VSS AL17 Power Other vss C7 Power Other
36. VSS AL20 Power Other VSS D12 Power Other VSS AL23 Power Other VSS D15 Power Other VSS AL24 Power Other VSS D18 Power Other VSS AL27 Power Other VSS D21 Power Other VSS AL28 Power Other VSS D24 Power Other VSS AL3 Power Other VSS D3 Power Other VSS AM1 Power Other VSS D5 Power Other VSS AM10 Power Other VSS D6 Power Other VSS AM13 Power Other VSS D9 Power Other VSS AM16 Power Other VSS E11 Power Other VSS AM17 Power Other VSS E14 Power Other VSS AM20 Power Other VSS E17 Power Other VSS AM23 Power Other VSS E2 Power Other VSS AM24 Power Other VSS E20 Power Other VSS AM27 Power Other VSS E25 Power Other VSS AM28 Power Other vss E26 Power Other VSS AMA Power Other VSS E27 Power Other VSS AM7 Power Other VSS E28 Power Other VSS AN1 Power Other VSS E29 Power Other VSS AN10 Power Other VSS E8 Power Other VSS AN13 Power Other VSS F1 Power Other VSS AN16 Power Other VSS F10 Power Other VSS AN17 Power Other VSS F13 Power Other VSS AN2 Power Other VSS F16 Power Other VSS AN20 Power Other VSS F19 Power Other VSS AN23 Power Other VSS F22 Power Other VSS AN24 Power Other VSS F4 Power Other Dual Core Intel Xeon Processor 5000 Series Datasheet 49 intel Land Listing Table 4 1 Land Listing by Land Name Sheet 8 of 9 Land Name pons MG cod Direction Land Nam
37. assure a low interconnect resistance from the regulator EVRD or VRM pins to the LGA771 socket Bulk decoupling must be provided on the baseboard to handle large current swings The power delivery solution must insure the voltage and current specifications are met as defined in Table 2 10 For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Vr Decoupling Bulk decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To insure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Front Side Bus AGTL Decoupling The Dual Core Intel Xeon Processor 5000 series integrate signal termination on the die as well as a portion of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Decoupling guidel
38. at unparalleled value and flexibility for powerful servers internet infrastructure and departmental server applications The Intel NetBurst micro architecture Intel Virtualization Technology and Hyper Threading Technology deliver outstanding performance and headroom for peak internet server workloads resulting in faster response times support for more users and improved scalability 8 8 Dual Core Intel Xeon Processor 5000 Series Datasheet I ntroduction 1 intel Introduction The Dual Core Intel Xeon Processor 5000 series are Intel dual core products for dual processor DP servers and workstations The Dual Core Intel Xeon Processor 5000 series are 64 bit server workstation processors utilizing two physical Intel NetBurst microarchitecture cores in one package The Dual Core Intel Xeon Processor 5000 series include enhancements to the Intel NetBurst microarchitecture while maintaining the tradition of compatibility with A 32 software Some key features include Hyper Pipelined Technology and an Execution Trace Cache Hyper Pipelined Technology includes a multi stage pipeline depth allowing the processor to reach higher core frequencies The Dual Core Intel Xeon Processor 5000 series contain a total of 4 MB of L2 Advanced Transfer Cache 2 MB per core The 1066 MHz Front Side Bus FSB is a quad pumped bus running off a 266 MHz system clock making 8 5 GBytes per second data transfer rates possible The 667 MHz Front Side Bus
39. cece ee eee kk kk sensns 104 Figures 2 1 Phase Lock Loop PLL Filter Reouirements eee kk kk kk kk nnm nnn 18 2 2 Dual Core Intel Xeon Processor 5000 Series 1066 MHz Load Current versus Time 27 2 3 Dual Core Intel Xeon Processor 5000 Series 667 MHz and Dual Core Intel Xeon Processor 5063 MV Load Current versus Time 28 2 4 VCC Static and Transient Tolerance Load Lines 29 2 5 VCC Overshoot Example Waveform Lhkklkk kk kk kk nemen eee nennen 32 3 1 Processor Package Assembly Sketch 33 3 2 Processor Package Drawing Sheet 1 of i 34 3 3 Processor Package Drawing Sheet 2 of 3 35 3 4 Processor Package Drawing Sheet 3 of 3 36 3 5 Dual Core Intel Xeon Processor 5000 Series Top side Markinges ees 39 3 6 Dual Core Intel Xeon Processor 5063 MV Top side Markings sess 39 3 7 Processor Land Coordinates Top View 40 3 8 Processor Land Coordinates Bottom View 41 6 1 Dual Core Intel Xeon Processor 5000 Series 1066 MHz Thermal Profiles A and BR 71 6 2 Dual Core Intel Xeon Processor 5000 Series 667 MHz Thermal Profiles 73 6 3 Dual Core Intel Xeon Processor 5063 MV Thermal Profile 75 6 4 Case Temperature TCASE Measurement Location 76 Z51 Stop Clock State Machine u rere etr emn ke xi Kalek alan b na lea v E kela aa indies 85 4 Dual Core Intel Xeon Processor 5000 Series Datashe
40. error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal for example NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination 64 Dual Core Intel Xeon Processor 5000 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 5 of 8 Name IGNNE Z Type l Description IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If I GNNEZ is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNEZ has no effect when the NE bit in control register 0 CRO is set GNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction Notes INIT LINT 1 0 INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests d
41. feele SE b na kul reb Cab dln ka deed bayan ale a ETE veau 61 6 Thermal SpeciflCatilOFis cce dee ee dee DR Ed YY KE eile tua cal Ee Hunt ME Ma du RUE uate peas 69 6 1 Package Thermal Gpecfications ennemi eee 69 6 1 1 Thermal Specifications I memes eee 69 6 1 2 Thermal Metrology ed ore ere eed eres ed pera Peedi vie dn d pd b nin 75 6 2 Processor Thermal Features 77 6 2 1 Thermal MORnitOF exe er emen aki e idc e EEN EEN Waa 4a e avaa sa d e nad 77 6 2 2 On Demand Mode 77 6 2 3 PROCHOT eege ine teat avers Zika n na nakan ege arse ke dam ddr e Rn 78 6 2 4 FORCEPR Signal iste kulla biqedanda a Wi a ra kad a alek k h ka RENE d ts 78 6 2 5 THERMTRIP Signal s ciran nt cere pana n bn cik n n haka h n R N man hura k w ha aA a ra 78 Dual Core Intel Xeon Processor 5000 Series Datasheet 3 6 2 6 Tcontrol and Fan Speed Reduction r rr 79 6 2 7 Thermal Diode re e Rx a kk k ra KSE ENER E RAG CAZXRRGRRRIXXTERZTERREXRRRA 79 7 F a tU Sh e e Sua E uM Pr Sdn m ed M MM IN ME DU NER REN EU d 83 7 1 Power On Configuration Options eee aka ka aa kalan aa a 83 7 2 Clock Control and Low Power States 83 7 2 1 Normal State ecc k n Ane kann h k man xan n an Wa AEE EES Abe hara Zala na W ran 84 7 2 2 HALT or Enhanced Powerdown States 84 7 2 3 Stop Grant EE 85 7 2 4 Enhanced HALT Snoop or H
42. frequency Note that the top frequency for the processor can not be exceeded f the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals 8 Dual Core Intel Xeon Processor 5000 Series Datasheet 87 88 Features Dual Core Intel Xeon Processor 5000 Series Datasheet Boxed Processor Specifications n tel 8 8 1 Figure 8 1 Boxed Processor Specifications I ntroduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The Dual Core Intel Xeon Processor 5000 series will be offered as an Intel boxed processor Intel will offer the Dual Core Intel Xeon Processor 5000 series boxed processor with two heat sink configurations available for each processor frequency 1U passive 2U active combination solution and a 2U passive only solution The 1U passive 2U active combination solution is based on a 1U passive heat sink with a removable fan that will be pre attached at shipping This heat sink solution is intended to be used as either a 1U passive heat sink or a 2U active heat sink Although the active combination solution with removable fan mechanically fits into a 2U keepout additional design considerations may need to be addressed to provide sufficient airflow to the fan inlet The 1U
43. of all processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC O SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SMI l SMI System Management Interrupt is asserted asynchronously by system logic 2 On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tri state its outputs STPCLK 4 l STPCLK Stop Clock when asserted causes processors to enter a low power Stop 2 Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and API C units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK l
44. path between the processor FSB agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI DSTBN DSTBP DBU Data Group D 15 0 0 D 31 16 1 D 47 32 2 D 63 48 3 w NT oO Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high Notes DBI 3 0 DBR 1 0 DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment to Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3 D 63 48 DBR is us
45. refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines The boxed processor will ship with a component thermal solution Refer to Chapter 8 Boxed Processor Specifications for details on the boxed processor Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TcAsg specifications as defined by the applicable thermal profile refer to Table 6 1 Table 6 4 and Table 6 7 Figure 6 1 Figure 6 2 and Figure 6 3 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the processor thermal mechanical design guidelines The Dual Core Intel Xeon Processor 5000 series implement a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to ensure processor reliability Selection of the appropriate fan speed is based on the temperature reported by the processor s Thermal Diode If the diode temperature is greater than or equal to Tcontrol refer to Section 6 2 6 then the processor case temperature must remain at or below the temperature specified by the thermal profile refer to Figure 6 1 Figure 6 2 and Figure 6 3 If the diode temperature is less than Tcon
46. the latest specifications and before placing your product order Intel Pentium Intel Xeon Intel SpeedStep Intel NetBurst Intel Architecture Intel Virtualization Technology and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2004 2006 Intel Corporation 2 Dual Core Intel Xeon Processor 5000 Series Datasheet Contents 1 Jak gele lte Tel eee Eh 9 1 1 ler ge lte e Le KEE 11 1 2 State of Dal suu m ege dg Seene adl la i ib CR FOR RD Pa RE RR ER TA Rar Rl x n 12 A E i us DIE EP 12 2 Electrical Specificatl ris 52 eec etre tree vec io od ang E Er ha Ee aad poema Ra tb na nalan 15 2 1 Front Side Bus and GTLREF 10 ceceec cece eee ee nemen meses 15 2 2 Power and Ground Landes 15 2 3 Decoupling Guidelines enemies niens 16 2 3 1 VCC Deco pling cere iret eese Kend canan hin nne eles 16 2 3 2 VIE D COUD e Le DEE 16 2 3 3 Front Side Bus AGTL Decoupling r mme 16 2 4 Front Side Bus Clock BCLK 1 0 and Processor Clocking sene 16 2 4 1 Front Side Bus Frequency Select Signals BSEL 2 0 17 2 4 2 Phase Lock Loop PLL and Filter 18 2 5 Voltage Identification ID 19 2 6 Reserved or Unused Gionals eee eee ee nnne esent 21 2 7 Front Side Bus Signal Groups 21 2 8 GTL Asynchronous and AGTL Asynchro
47. 038 VID 0 053 VID 0 068 35 VID 0 044 VID 0 059 VID 0 074 40 VID 0 050 VID 0 065 VID 0 080 45 VID 0 056 VID 0 071 VID 0 086 50 VID 0 063 VID 0 078 VID 0 093 55 VID 0 069 VID 0 084 VID 0 099 60 VID 0 075 VID 0 090 VID 0 105 65 VID 0 081 VID 0 096 VID 0 111 70 VID 0 087 VID 0 103 VID 0 118 75 VID 0 094 VID 0 109 VID 0 124 28 Dual Core Intel Xeon Processor 5000 Series Datasheet Electrical Specifications n tel Table 2 11 Vcc Static and Transient Tolerance Sheet 2 of 2 Icc A Vcc Max V Vcc Typ V Vcc Min V Notes 80 VID 0 100 VID 0 115 VID 0 130 85 VID 0 106 VID 0 121 VID 0 136 90 VID 0 113 VID 0 128 VID 0 143 95 VID 0 119 VID 0 134 VID 0 149 100 VID 0 125 VID 0 140 VID 0 155 105 VID 0 131 VID 0 146 VID 0 161 110 VID 0 138 VID 0 153 VID 0 168 115 VID 0 144 VID 0 159 VID 0 174 120 VID 0 150 VID 0 165 VID 0 180 125 VID 0 156 VID 0 171 VID 0 186 130 VID 0 163 VID 0 178 VID 0 193 135 VID 0 169 VID 0 184 VID 0 199 140 VID 0 175 VID 0 190 VID 0 205 145 VID 0 181 VID 0 196 VID 0 211 150 VID 0 188 VID 0 203 VID 0 218 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 12 1 for Vcc overshoot specifications 2 This table is intended to aid in reading disc
48. 5 VSS Power Other B4 DOO Source Sync Input Output D16 RESERVED B5 VSS Power Other D17 D49 Source Sync Input Output B6 DO5 Source Sync Input Output D18 VSS Power Other B7 D06 Source Sync Input Output D19 DBI2 Source Sync Input Output D2 ADS Common Clk Input Output E4 HITM Common Clk Input Output D20 D48 Source Sync Input Output E5 RESERVED D21 VSS Power Other E6 RESERVED D22 D46 Source Sync Input Output E7 RESERVED D23 RESERVED E8 VSS Power Other D24 VSS Power Other E9 D19 Source Sync Input Output D25 VIT Power Other F1 VSS Power Other D26 VIT Power Other F10 VSS Power Other D27 VIT Power Other F11 D23 Source Sync Input Output D28 VIT Power Other F12 D24 Source Sync Input Output D29 VIT Power Other F13 VSS Power Other D3 VSS Power Other F14 D28 Source Sync Input Output D30 VIT Power Other F15 D30 Source Sync Input Output D4 HIT Common Clk Input Output F16 VSS Power Other D5 VSS Power Other F17 D37 Source Sync Input Output D6 VSS Power Other F18 D38 Source Sync Input Output D7 D20 Source Sync Input Output F19 VSS Power Other D8 D12 Source Sync Input Output F2 GTLREF DATA CL Power Other Input D9 VSS Power Other F20 D41 Source Sync Input Output El RESERVED F21 D43 Source Sync Input Output E10 D21 Source Sync Input Output F22 VSS Power Other E11 VSS Power Other F23 RESERVED E12 DSTBP1 Source Sync Input Output F24 TESTHIO7 Power Other Input E13 D26 Source Sync Input
49. 77 107 3198 g 11130 NAIA 1NONI V n 3 3 w01123S HI dOL Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Design Guidelines Note Dual Core Intel Xeon Processor 5000 Series Datasheet 34 Mechanical Specifications n Figure 3 3 Processor Package Drawing Sheet 2 of 3 os Pn ces rm at o 2 SS em PESE ES i di i oz E ES zs Es ik jm SC of 9 m Ti d E O00000000000000000000000000000000 e 000000 00000000 fe 900000000 5 000000000 E 2 000000000 000000000 E 000000000 8 900000000 000000000000 0000000 000000000000000060 00000000000000 2 eg 9 o P e S EL 85 28 ss ss ss ss ze se se ss ss sz SE sss ZI EI J lt 3 e e co lt Dual Core Intel Xeon Processor 5000 Series Datasheet e n tel Mechanical Specifications Figure 3 4 Processor Package Drawing Sheet 3 of 3
50. ALT Snoop State Stop Grant SNOOP State all eee eee enn Een enne 86 7 3 Enhanced Intel SpeedStep Technology 86 8 Boxed Processor Specifications ss sssssserrrtssrir rrtt kk nne 89 8 1 lintrOdUCtlON uuu inay ua gak RR wayan kalk n cud a S na bad raa na du a n k Ra Q ka Kak ia n UD ERRARE ad ka k n 89 8 2 Mechanical Specifications kk kk kk kk kk kaka kaka kaka ka k kake 90 8 2 1 Boxed Processor Heat Sink Dimensions CEK ssesesseen eene 91 8 2 2 Boxed Processor Heat Sink Weight sss 99 8 2 3 Boxed Processor Retention Mechanism and Heat Sink Support CEK sssssssssssesen kanala ka a d ba na nnn 99 8 3 Electrical Requirements stet zeg Ge terrere rex REES w nak hona geg EE 99 8 3 1 Fan Power Supply Active CEK I IHmHeemememene eene 99 8 3 2 Boxed Processor Cooling Requirements me 100 8 4 Boxed Processor Contents ics oe ERR YN RR LEER EAR an n k RR RATER H n k wa WA day n a 101 9 Debug Tools Specifications open ea een era ge eur ed E RR ER ER RE i wl e a Ra a deca 103 9 1 Debug Port System Requirements sss nenne eene een 103 9 2 Target System Implementation sss ee ee eee ener 103 9 2 1 System Implementation laya bille kaleki nmm 103 9 3 Logic Analyzer Interface LA 103 9 3 1 Mechanical Considerations kk kk kk rne 104 9 3 2 Electrical Considerations ccc cece cece
51. AM8 VCC Power Other AL24 VSS Power Other AM9 VCC Power Other AL25 VCC Power Other AN1 VSS Power Other AL26 VCC Power Other AN10 VSS Power Other AL27 VSS Power Other AN11 VCC Power Other AL28 VSS Power Other AN12 VCC Power Other AL29 VCC Power Other AN13 VSS Power Other AL3 VSS Power Other AN14 VCC Power Other AL30 VCC Power Other AN15 VCC Power Other AL4 VID5 Power Other Output AN16 VSS Power Other AL5 VID1 Power Other Output AN17 VSS Power Other AL6 VID3 Power Other Output AN18 VCC Power Other AL7 VSS DIE SENSE2 Power Other Output AN19 VCC Power Other AN2 VSS Power Other B8 VSS Power Other AN20 VSS Power Other B9 DSTBPO Source Sync Input Output AN21 VCC Power Other C1 DRDY Common Clk Input Output AN22 VCC Power Other C10 VSS Power Other AN23 VSS Power Other C11 D11 Source Sync Input Output AN24 VSS Power Other C12 D14 Source Sync Input Output AN25 VCC Power Other C13 VSS Power Other AN26 VCC Power Other C14 D52 Source Sync Input Output AN3 VCC DIE SENSE Power Other Output C15 D51 Source Sync Input Output AN4 VSS_DIE_SENSE Power Other Output C16 VSS Power Other AN5 RESERVED C17 DSTBP3 Source Sync Input Output AN6 RESERVED C18 D54 Source Sync Input Output AN7 VID_SELECT Power Other Output C19 VSS Power Other AN8 VCC Power Other C2 BNR Common Clk Input Output ANY VCC Power Other C20 D I 3 Source Sync Input Output B1 VSS Power Other C21 D58 Source Sync Input Output B10 D10 Source Sync In
52. CC Power Other A5 DO4 Source Sync Input Output AC25 VCC Power Other A6 VSS Power Other AC26 VCC Power Other A7 DO7 Source Sync Input Output AC27 VCC Power Other A8 DBIO Source Sync Input Output AC28 VCC Power Other A9 VSS Power Other AC29 VCC Power Other AA VIT OUT Power Other Output AC3 VSS Power Other AA2 LL ID1 Power Other Output AC30 VCC Power Other AA23 vss Power Other AC4 RESERVED AA24 VSS Power Other AC5 A25 Source Sync Input Output AA25 VSS Power Other AC6 VSS Power Other AA26 VSS Power Other AC7 VSS Power Other AA27 VSS Power Other AC8 VCC Power Other AA28 VSS Power Other AD1 TDI TAP Input AA29 VSS Power Other AD2 BPM2 Common Clk Input Output AA3 VSS Power Other AD23 VCC Power Other AA30 VSS Power Other AD24 VCC Power Other AAA A21 Source Sync Input Output AD25 VCC Power Other AA5 A23 Source Sync Input Output AD26 VCC Power Other AA6 VSS Power Other AD27 VCC Power Other AA7 VSS Power Other AD28 VCC Power Other AA8 VCC Power Other AD29 VCC Power Other AD3 BINIT Common Clk Input Output AF15 VCC Power Other AD30 VCC Power Other AF16 VSS Power Other AD4 VSS Power Other AF17 VSS Power Other AD5 ADSTB1 Source Sync Input Output AF18 VCC Power Other AD6 A22 Source Sync Input Output AF19 VCC Power Other 52 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Land Listing
53. Core Intel Xeon Processor 5000 series support Intel virtualization Technology virtualization within the processor Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple independent software environments inside a single platform More information on Intel Virtualization Technology can be found at http www intel com technology computing vptech index htm The Dual Core Intel Xeon Processor 5000 series are intended for high performance workstation and server systems The Dual Core Intel Xeon Processor 5063 is a lower power version of the Dual Core Intel Xeon Processor 5000 series The Dual Core Intel Xeon Processor 5000 series support a new Dual Independent Bus DIB architecture with one processor socket on each bus up to two processor sockets in a system The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth The Dual Core Intel Xeon Processor 5000 series will be packaged in an FC LGA6 Land Grid Array package with 771 lands for improved power delivery It utilizes a surface mount LGA771 socket that supports Direct Socket Loading DSL Dual Core I ntel Xeon Processor 5000 Series Features Cores Per L2 Advanced Hyper Threading Front Side Bus Package Package Transfer Cache Technology Frequency 9 2 2 MB pe
54. Dual Core Intel Xeon Processor 5000 Series Datasheet May 2006 Document Number 313079 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITI ONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLI ED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRI GHT OR OTHER INTELLECTUAL PROPERTY RI GHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Dual Core Intel Xeon Processor 5000 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain
55. G26 Power Other VCC AC28 Power Other VCC AG27 Power Other VCC AC29 Power Other VCC AG28 Power Other VCC AC30 Power Other VCC AG29 Power Other 45 intel Land Listing Table 4 1 LandListing by Land Name Sheet 4 of 9 Land Name pos ARE cod Direction Land Name dee Eu Direction VCC AC8 Power Other VCC AG30 Power Other VCC AD23 Power Other VCC AG8 Power Other VCC AD24 Power Other VCC AG9 Power Other VCC AD25 Power Other VCC AH11 Power Other VCC AD26 Power Other VCC AH12 Power Other VCC AD27 Power Other VCC AH14 Power Other VCC AD28 Power Other VCC AH15 Power Other VCC AD29 Power Other VCC AH18 Power Other VCC AD30 Power Other VCC AH19 Power Other VCC AD8 Power Other VCC AH21 Power Other VCC AE11 Power Other VCC AH22 Power Other VCC AE12 Power Other VCC AH25 Power Other VCC AE14 Power Other VCC AH26 Power Other VCC AE15 Power Other VCC AH27 Power Other VCC AE18 Power Other VCC AH28 Power Other VCC AE19 Power Other VCC AH29 Power Other VCC AE21 Power Other VCC AH30 Power Other VCC AE22 Power Other VCC AH8 Power Other VCC AE23 Power Other VCC AH9 Power Other VCC AE9 Power Other VCC AJ11 Power Other VCC AF11 Power Other VCC AJ12 Power Other VCC AF12 Power Other VCC AJ14 Power Other VCC AF14 Power Other VCC AJ15 Power Other VCC AF15 Pow
56. I VSS Power Other U26 VCC Power Other wa VCC Power Other U27 VCC Power Other Y1 RESERVED U28 VCC Power Other Y2 VSS Power Other U29 VCC Power Other Y23 VCC Power Other U3 AP1 Common Clk Input Output Y24 VCC Power Other U30 VCC Power Other Y25 VCC Power Other U4 A13 Source Sync Input Output Y26 VCC Power Other U5 A125 Source Sync Input Output Y27 VCC Power Other U6 A10 Source Sync Input Output Y28 VCC Power Other U7 VSS Power Other Y29 VCC Power Other U8 VCC Power Other Y3 COMP6 Power Other Input V1 MS ID1 Power Other Output Y30 VCC Power Other Dual Core Intel Xeon Processor 5000 Series Datasheet 59 intel Land Listing Table 4 2 Land Listing by Land Number Sheet 9 of 9 Land Signal Buffer Land Signal Buffer No Land Name Type Direction No Land Name Type Direction V2 LL IDO Power Other Output Y4 A20 Source Sync Input Output V23 VSS Power Other Y5 VSS Power Other Y6 A193 Source Sync Input Output Y7 VSS Power Other Y8 VCC Power Other 60 Dual Core Intel Xeon Processor 5000 Series Datasheet Signal Definitions 5 5 1 Table 5 1 Signal Definitions Signal Definitions Signal Definitions Sheet 1 of 8 Name Type Description Notes A 35 3 1 0 A 35 3 Address define a 239 byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a tra
57. Installation Manual Intel Branding Logo Dual Core Intel Xeon Processor 5000 Series Datasheet 101 e n tel Boxed Processor Specifications The other items listed in Figure 8 3 that are required to compete this solution will be shipped with either the chassis or boards They are as follows CEK Spring supplied by baseboard vendors Heat sink standoffs supplied by chassis vendors 8 102 Dual Core Intel Xeon Processor 5000 Series Datasheet Debug Tools Specifications n tel 9 9 1 Note 9 2 9 2 1 9 3 Debug Tools Specifications Please refer to the eXtended Debug Port Debug Port Design Guide for UP and DP Platforms and the appropriate platform design guidelines for information regarding debug tool specifications Section 1 3 provides collateral details Debug Port System Requirements The Dual Core Intel Xeon Processor 5000 series debug port is the command and control interface for the In Target Probe ITP debugger The ITP enables run time control of the processors for system debug The debug port which is connected to the FSB is a combination of the system J TAG and execution signals There are several mechanical electrical and functional constraints on the debug port that must be followed The mechanical constraint requires the debug port connector to be installed in the system with adequate physical clearance Electrical constraints exist due to the mixed high and low speed signals of th
58. LK signals are bussed together thus all processors are affected in unison The Hyper Threading Technology feature adds the conditions that all logical processors share the same STPCLK signal internally When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each processor or logical processor The chipset Dual Core Intel Xeon Processor 5000 Series Datasheet 83 intel 7 2 2 7 2 2 1 7 2 2 2 84 needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states Refer to the applicable chipset specification for more information Normal State This is the normal operating state for the processor HALT or Enhanced Powerdown States The Enhanced HALT power down state is enabled by default in the Dual Core Intel Xeon Processor 5000 series The Enhanced HALT power down state must remain enabled via the BIOS The Enhanced HALT state requires support for dynamic VID transitions in the platform HALT Powerdown State HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instruction When one of the logical processors executes the HALT or MWAIT instruction that logical processor is halted however the other processor continues normal operation The processor will transition to the Normal state upon
59. NILNNOW 305532084 Q 3 AINO SISOdYNd JM LYYISNITI 304 NMOHS INIILNO 3113N010A 13208 Nu31lVd 310H 40D 009 11 EN 95 NYJLLYA 310H 9NIINDON 40 NYaLL d 3108 40 1NIO 831832 NOWI I I 00e 721 Seas NOILVYOdYOD 131NI 40 1N3SNOO NILLIYM 20194 JHL LNOHLIM 0313100 YO O3AVIdSIO 0330008438 035070 1Q 38 LON AVN SINBINOD Sl ONY 328301309 NI 135010810 SI LI NOILVHNOJNI TVILN3014NOD NOILYYOJYOD 131NI SNIVINOD ONIMVHO SIHL 0 ar mme e m 9 T 9 Board Mounting Hole Keep Out Zones Boxed Processor Specifications Figure 8 7 Dual Core Intel Xeon Processor 5000 Series Datasheet e n tel Boxed Processor Specifications Figure 8 8 Volumetric Height Keep Ins m5 REV og 3001 askani TL TY 3 2X M T F Qaa 1 82 m 2 2 900 13 66 ee 6 99 215 88 9 3 501 96 52 3 800 VOLUMETRIC HEIGHT KEEPINS 96 Dual Core Intel Xeon Processor 5000 Series Datasheet ntel Boxed Processor Specifications 4 Pin Fan Cable Connector For Active CEK Heat Sink Figure 8 9 Y dO 1 133HS 9NIMVI 176 LON 00 Lr 325 HSINI 4 NOl123CO08d 319NY
60. Processor 5000 Series 1066 MHz Thermal Profile B Table Power W Tcase Max C Power W Tcase Max C C P profile min g 22 3 50 0 80 65 0 30 52 0 85 66 3 35 53 3 90 67 6 40 54 6 95 68 9 45 55 9 100 70 2 50 57 2 105 71 5 55 58 5 110 72 8 60 59 8 115 74 1 65 61 1 120 75 4 70 62 4 125 76 7 75 63 7 130 78 0 Table 6 4 Dual Core Intel Xeon Processor 5000 Series 667 MHz Thermal Specifications Thermal Minimum Core Frequency Design Power TcASE O TEASE Notes w C Launch to FMB 95 5 Refer to Figure 6 2 1 2 3 4 Table 6 5 Table 6 6 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and Icc combination wherein Vcc exceeds Vcc max at specified lI cc Please refer to the loadline specifications in Chapter 2 Electrical Specifications 2 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on final silicon validation characterization 4 Power specifications are defined at all VIDs found in Table 2 10 The Dual Core Intel Xeon Processor 5000 series may be shipped under multiple VI Ds for each frequency 5 FMB or Flexibl
61. S 14 75mm Measure Tcase geometric center of the top surface of the IHS 37 5 mm x 37 5mm Substrate Note Figure is not to scale and is for reference only 76 Dual Core Intel Xeon Processor 5000 Series Datasheet m Thermal Specifications n tel 6 2 6 2 1 6 2 2 Processor Thermal Features Thermal Monitor The Thermal Monitor TM1 feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Thermal Monitor TM1 must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor is enabled and a high temperature situation exists that is TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 5096 Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid acti
62. Table 4 2 Land Listing by Land Number Sheet 2 of 9 Find Land Name id Ea Direction pr Land Name M cw Direction AD7 VSS Power Other AF2 BPM4 Common Clk Input Output AD8 VCC Power Other AF20 VSS Power Other AE1 TCK TAP Input AF21 VCC Power Other AE10 VSS Power Other AF22 VCC Power Other AE11 VCC Power Other AF23 VSS Power Other AE12 VCC Power Other AF24 VSS Power Other AE13 VSS Power Other AF25 VSS Power Other AE14 VCC Power Other AF26 VSS Power Other AE15 VCC Power Other AF27 VSS Power Other AE16 VSS Power Other AF28 VSS Power Other AE17 VSS Power Other AF29 VSS Power Other AE18 VCC Power Other AF3 VSS Power Other AE19 VCC Power Other AF30 VSS Power Other AE2 VSS Power Other AF4 A28 Source Sync Input Output AE20 VSS Power Other AF5 A27 Source Sync Input Output AE21 VCC Power Other AF6 VSS Power Other AE22 VCC Power Other AF7 VSS Power Other AE23 VCC Power Other AF8 VCC Power Other AE24 VSS Power Other AF9 VCC Power Other AE25 VSS Power Other AG1 TRST TAP Input AE26 VSS Power Other AG10 VSS Power Other AE27 VSS Power Other AG11 VCC Power Other AE28 VSS Power Other AG12 VCC Power Other AE29 VSS Power Other AG13 VSS Power Other AE3 COMP7 Power Other Input AG14 VCC Power Other AE30 VSS Power Other AG15 VCC Power Other AE4 RESERVED AG16 vss Power Other AE5 VSS Power Other AG17 VSS Power Other AE6 RESERVED AG18 VCC Power Other AE7 VSS Power Other AG19 VCC Power Other AE8 SKTOCC Power Other Output AG2 BPM3 Comm
63. V and full power 64 bit Intel Xeon processors should not be mixed within a system Not all operating systems can support dual processors with mixed frequencies Intel does not support or validate operation of processors with different cache sizes Mixing processors of different steppings but the same model as per CPUID instruction is supported Details regarding the CPUID instruction are provided in the AP 485 Intel Processor Identification and the CPUID Instruction application note Absolute Maximum and Minimum Ratings Table 2 9 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condi
64. ackaging material Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessing SMP systems Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Enhanced I ntel SpeedStep Technology The next generation implementation of Intel SpeedStep technology which extends power management capabilities of servers and workstations Dual Core Intel Xeon Processor 5000 Series Datasheet 11 1 2 1 3 12 Introduction Thermal Design Power Processor thermal solutions should be designed to meet this target It is the highest expected sustainable power while running known power intensive real applications TDP is not the maximum power that the processor can dissipate LGA771 socket The Dual Core Intel Xeon Processor 5000 series interfaces to the baseboard through this surface mount 771 Land socket See the LGA771 Socket Design Guidelines for details regarding this socket Processor A single package that contains one or more complete execution cores Processor core Processor core die with
65. ame Notes Output tri state SMI 1 2 Execute BIST Built In Self Test A34 1 2 1 Order Queue de pipelining set IOQ depth to ATH 1 2 Disable MCERR observation A9 1 2 Disable BINIT observation A103 1 2 Disable bus parking A15 1 2 Symmetric agent arbitration ID BR 1 0 1 2 Force single logical processor A31 1 2 3 Notes 1 Asserting this signal during RESET will select the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET 3 This mode is not tested Clock Control and Low Power States The Dual Core Intel Xeon Processor 5000 series support the Enhanced HALT Powerdown state in addition to the HALT Powerdown state and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Enhanced HALT state is enabled by default in the Dual Core Intel Xeon Processor 5000 series The Enhanced HALT state must remain enabled via the BIOS for the processor to remain within its specifications For processors that are already running at the lowest core to bus ratio for its nominal operating point the processor will transition to the HALT Powerdown state instead of the Enhanced HALT state The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPC
66. appropriate pins of all processor 3 FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals RESET l Asserting the RESET signal resets all processors to known states and invalidates 3 their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after VCC and BCLK have reached their proper specifications On observing active RESET all FSB agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 l RS 2 0 Response Status are driven by the response agent the agent responsible 3 for completion of the current transaction and must connect the appropriate pins of all processor FSB agents RSP l RSP Response Parity is driven by the response agent the agent responsible for 3 completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins
67. ation may be observed and driven by all processor FSB agents 3 and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration see Figure 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their 1 O Queue 10Q and transaction tracking state machines upon observation of BI NIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a priority agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR 1 0 BNR Block Next Request is used to assert a bus stall by any bus agent who is 3 unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor FSB agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edg
68. ber reinforced resin Substrate Lands Gold over nickel Dual Core Intel Xeon Processor 5000 Series Datasheet m Mechanical Specifications n tel 3 8 Processor Markings Figure 3 5 and Figure 3 6 shows the topside markings on the processor This diagram aids in the identification of the Dual Core Intel Xeon Processor 5000 series Figure 3 5 Dual Core Intel Xeon Processor 5000 Series Top side Markings Legend Mark Text Production Mark GROUP1LINE1 GROUP1LINE1 3733DP 4M 1066 GROUP1LINE2 GROUP1LINE2 Intel amp Xeon GROUP1LINE3 GROUP1LINE3 5080 SXXX COO GROUP1LINE4 GROUP1LINE4 i M 05 GROUP LINES GROUPILINE5 FPO ATPO S N Figure 3 6 Dual Core Intel Xeon Processor 5063 MV Top side Markings Legend Mark Text Production Mark GROUPHLINE1 GROUP1LINE1 3200DP 4M 1066 MV GROUP1LINE2 GROUP1LINE2 Intel amp Xeon GROUP1LINE3 GROUP1LINE3 5063 SXXX COO GROUP1LINE4 GROUP1LINE4 i M 05 GROUP1LINES GROUP1LINE5 FPO Dual Core Intel Xeon Processor 5000 Series Datasheet 39 e n tel Mechanical Specifications 3 9 Processor Land Coordinates Figure 3 7 and Figure 3 8 show the top and bottom view of the processor land coordinates respectively The coordinates are referred to throughout the document to identify processor lands Figure 3 7 Processor Land Coordinates Top View Voc Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
69. cannot be grouped with other TESTHI signals TESTHI 11 cannot be grouped with other TESTHI signals Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active PMOS pull up transistor to assist the during the first clock of a low to high voltage transition Dual Core Intel Xeon Processor 5000 Series Datasheet 21 Table 2 6 22 Electrical Specifications With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITM and so forth and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE Z and so forth and can become active at any time during the clock cycle Table 2 6 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Signal Group Type
70. ce Sync Input Output DBIO A8 Source Sync Input Output D22 D10 Source Sync Input Output DBI1 G11 Source Sync Input Output D23 F11 Source Sync Input Output DBI 2 D19 Source Sync Input Output D243 F12 Source Sync Input Output DBI 3 C20 Source Sync Input Output D25 D13 Source Sync Input Output DBR AC2 Power Other Output D26 E13 Source Sync Input Output DBSY B2 Common Clk Input Output D27 G13 Source Sync Input Output DEFER G7 Common Clk Input D28 F14 Source Sync Input Output DPO J16 Common Clk Input Output D29 G14 Source Sync Input Output DP1 H15 Common Clk Input Output D30 F15 Source Sync Input Output DP2 H16 Common Clk Input Output D31 G15 Source Sync Input Output DP3 J17 Common Clk Input Output D32 G16 Source Sync Input Output DRDY C1 Common Clk Input Output D33 E15 Source Sync Input Output DSTBNO C8 Source Sync Input Output D34 E16 Source Sync Input Output DSTBN1 G12 Source Sync Input Output D35 G18 Source Sync Input Output DSTBN2 G20 Source Sync Input Output D36 G17 Source Sync Input Output DSTBN3 A16 Source Sync Input Output D37 F17 Source Sync Input Output DSTBPO B9 Source Sync Input Output D38 F18 Source Sync Input Output DSTBP1 E12 Source Sync Input Output D39 E18 Source Sync Input Output DSTBP2 G19 Source Sync Input Output DSTBP3 C17 Source Sync Input Output RESERVED E23 FERR PBE R3 ASync GTL Outp
71. common clock signals Refer to the applicable platform design guidelines for details Termination resistors Rrr for AGTL signals are provided on the processor silicon and are terminated to Ver The on die termination resistors are always enabled on the Dual Core Intel Xeon Processor 5000 series to control reflections on the transmission line Intel chipsets also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Some FSB signals do not include on die termination Rrr and must be terminated on the baseboard See Table 2 7 for details regarding these signals The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Contact your Intel Field Representative to obtain the processor signal integrity models which includes buffer and package models Power and Ground Lands For clean on chip processor core power distribution the processor has 223 Vec power and 271 Vss ground inputs All Vcc lands must be connected to the processor power plane while all Vss lands must be connected to the system ground plane The processor Vcc lands must be supplied with the voltage determined by the processor Voltage I Dentification VID signals See Table 2 3 for VID definitions Twenty two
72. cycle Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state For the Dual Core Intel Xeon Processor 5000 series all logical processor cores will enter the Stop Grant state once the STPCLK pin is asserted Additionally all logical cores must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vrr for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state Dual Core Intel Xeon Processor 5000 Series Datasheet 85 intel 7 2 4 7 2 4 1 7 2 4 2 7 3 86 RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 1 While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occ
73. diode T diode Fan RPM is modulated through the use of an ASIC located on the baseboard that sends out a PWM control signal to the 4th pin of the connector labeled as Control This thermal solution requires a constant 12 V supplied to pin 2 of the active thermal solution and does not support variable voltage control or 3 pin PWM control See Table 8 2 for details on the 4 pin active heat sink solution connectors If the 4 pin active fan heat sink solution is connected to an older 3 pin baseboard CPU fan header it will default back to a thermistor controlled mode allowing compatibility with legacy 3 wire designs When operating in thermistor controlled mode fan RPM is automatically varied based on the Tiner temperature measured by a thermistor located at the fan inlet of the heat sink solution Dual Core Intel Xeon Processor 5000 Series Datasheet 99 intel Table 8 1 Table 8 2 Figure 8 11 Table 8 3 8 3 2 100 Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it The fan power header identification and location must be documented in the suppliers platform documentation or on the baseboard itself The baseboard fan power header should be positioned within 177 8 mm 7 in from the center of the processor socket PWM Fan Frequency Specifications for 4 Pin Active CEK Thermal Solution
74. duct will be implemented to provide sufficient airflow to pass through the heat sink fins Currently the actual airflow target is within the range of 15 27 CFM The duct should be designed as precisely as possible and should not allow any air to bypass the heat sink 0 bypass and a back pressure of 0 38 in H20 It is assumed that a 40 C Ti is met This requires a superior chassis design to limit the Thise at or below 5 C with an external ambient temperature of 35 C Following these guidelines will allow the designer to meet Thermal Profile B and conform to the thermal requirements of the processor 1U Passive 2U Active Combination Heat Sink Solution Pedestal Active The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting It may be still be necessary to implement some form of chassis air guide or air duct to meet the T 4 temperature of 40 C depending on the pedestal chassis layout Also while the active thermal solution is designed to mechanically fit into a 2U volumetric it may require additional space at the top of the thermal solution to allow sufficient airflow into the heat sink fan Therefore additional design criteria may need to be considered if this thermal solution is used in a 2U rack mount chassis or in a chassis that has drive bay obstructions above the inlet to the fan heat sink Use of the active configurati
75. e 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet Thermal Profile will not meet the processor s thermal specifications and may result in permanent damage to the processor 3 Refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for system and environment implementation details Table 6 8 Dual Core Intel Xeon Processor 5063 MV Thermal Profile Table Power W Tcase Max C C Power W Tcase Max C C P profile min 3 29 6 50 0 75 61 8 35 51 4 80 63 1 40 52 7 85 64 4 45 54 0 90 65 7 50 55 3 95 67 0 55 56 6 60 57 9 65 59 2 70 60 5 6 1 2 Thermal Metrology The minimum and maximum case temperatures Tcase specified in Table 6 2 Table 6 3 Table 6 5 and Table 6 6 are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 4 illustrates the location where Dual Core Intel Xeon Processor 5000 Series Datasheet 75 e n tel Thermal Specifications Tcase temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines Figure 6 4 Case Temperature Tcase Measurement Location Measure from the edge of the top surface of processor IH
76. e calculated from the thermal profile is equal to 50 C The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 6 1 Table 6 4 and Table 6 7 instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with lower power dissipation is currently planned The Thermal Monitor feature must be enabled for the processor to remain within its specifications Dual Core Intel Xeon Processor 5000 Series 1066 MHz Thermal Specifications Thermal Minimum Core Frequency Design Power TCASE a Ee Notes W C Launch to FMB 130 5 Refer to Figure 6 1 Table 6 2 Table 6 3 1 2 3 4 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and Icc combination wherein Vcc exceeds Vcc
77. e 6 8 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified I cc Please refer to the loadline specifications in Chapter 2 Electrical Specifications i 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on final silicon validation characterization 4 Power specifications are defined at all VIDs found in Table 2 10 The Dual Core Intel Xeon Processor 5000 series may be shipped under multiple VI Ds for each frequency 5 FMB or Flexible Motherboard guideline provide a design target for meeting all planned processor frequency requirements 74 Dual Core Intel Xeon Processor 5000 Series Datasheet Thermal Specifications Figure 6 3 Dual Core Intel Xeon Processor 5063 MV Thermal Profile 70 65 60 55 Tcase C 45 40 T 50 TCASE_MAX TDP Thermal Profile Y 0 260 x 42 3 20 30 40 50 Power W 60 70 80 90 100 Notes 1 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 8 for discrete points that constitute the thermal profil
78. e A should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss Refer to Section 6 2 for details on TCC activation 3 Thermal Profile B is representative of a volumetrically constrained platform Please refer to Table 6 3 for discrete points that constitute the thermal profile 4 Implementation of Thermal Profile B will result in increased probability of TCC activation and measurable performance loss Furthermore utilization of thermal solutions that do not meet Thermal Profile B do not meet the processor s thermal specifications and may result in permanent damage to the processor 5 Refer to the Dual Core Intel Xeon processor 5000 Series Thermal Mechanical Design Guidelines for system and environmental implementation details Table 6 2 Dual Core Intel Xeon Processor 5000 Series 1066 MHz Thermal Profile A Table Power W Toast Max C Power W Tcase_max C C P profile min 436 5 50 0 85 59 9 40 50 7 90 60 9 45 51 7 95 61 9 50 52 8 100 62 9 55 53 8 105 63 9 60 54 8 110 64 9 65 55 8 115 65 9 70 56 8 120 67 0 75 57 8 125 68 0 80 58 8 130 69 0 Dual Core Intel Xeon Processor 5000 Series Datasheet 71 e n tel Thermal Specifications Table 6 3 Dual Core Intel Xeon
79. e Motherboard guidelines provide a design target for meeting all planned processor frequency requirements 72 Dual Core Intel Xeon Processor 5000 Series Datasheet C Thermal Specifications n tel Figure 6 2 Table 6 5 Dual Core I ntel Xeon Processor 5000 Series 667 MHz Thermal Profiles TCASE MAX is a thermal solution design point In actuality units will not significantly exceed TCASE MAX A due to TCC activation 70 TCASE MAX BQGTDP ERES SERE DR 65 4 TCASE MAX AQTDP gora 0 227789 ESTRUM ere S Thermal Profile B n ee Y 0 260 x 42 3 Thermal Profile A Y 0 203 x 41 7 50 7 lt I I I 1 LI I 1 45 4 I i I 1 I I LI 40 r j 4 4 r r r d 0 10 20 30 40 50 60 70 80 90 100 Power W Notes 1 Thermal Profile A is representative of a volumetrically unconstrained platform Please refer to Table 6 5 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile A should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss Refer to Section 6 2 for details on TCC activation 3 Thermal Profile B is representative of a volumetrically constrained platform Please refer to Table 6 6 for discrete points that constitute the thermal profile 4
80. e d TET Direction VSS Bl Power Other VSS F7 Power Other VSS B11 Power Other VSS G1 Power Other VSS B14 Power Other VSS H10 Power Other VSS B17 Power Other VSS H11 Power Other VSS B20 Power Other VSS H12 Power Other VSS B24 Power Other VSS H13 Power Other VSS B5 Power Other VSS H14 Power Other VSS B8 Power Other VSS H17 Power Other VSS H18 Power Other VSS P28 Power Other VSS H19 Power Other VSS P29 Power Other VSS H20 Power Other VSS P30 Power Other VSS H21 Power Other VSS P4 Power Other VSS H22 Power Other VSS P7 Power Other VSS H23 Power Other VSS R2 Power Other VSS H24 Power Other VSS R23 Power Other VSS H25 Power Other VSS R24 Power Other VSS H26 Power Other VSS R25 Power Other VSS H27 Power Other VSS R26 Power Other VSS H28 Power Other VSS R27 Power Other VSS H29 Power Other VSS R28 Power Other VSS H3 Power Other VSS R29 Power Other VSS H6 Power Other VSS R30 Power Other VSS H7 Power Other VSS R5 Power Other VSS H8 Power Other VSS R7 Power Other VSS H9 Power Other VSS T3 Power Other VSS J4 Power Other VSS T6 Power Other VSS J7 Power Other VSS T7 Power Other VSS K2 Power Other VSS U1 Power Other VSS K5 Power Other VSS U7 Power Other VSS K7 Power Other VSS V23 Power Other VSS L23 Power Other VSS V24 Power Other VSS L24 Power Other VSS V25 Power Other VSS L25 Power Other VSS V26 Power Other VSS L26 Power Other VSS V27 Power Other VSS L27 Power Other VSS V28 Po
81. e debug port for the processor While the JTAG signals operate at a maximum of 75 MHz the execution signals operate at the common clock FSB frequency The functional constraint requires the debug port to use the JTAG system via a handshake and multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Dual Core Intel Xeon Processor 5000 series based system designs including tools from vendors other than Intel The debug port and J TAG signal chain must be designed into the processor board to utilize the XDP for debug purposes except for interposer solutions Target System I mplementation System Implementation Specific connectivity and layout guidelines for the Debug Port are provided in the eXtended Debug Port Debug Port Design Guide for UP and DP Platforms and the appropriate platform design guidelines Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Dual Core Intel Xeon Processor 5000 series systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Dual Core Intel Xeon Processor 5000 series based multiprocessor systems the LAI is critical in providing the ability to
82. e guaranteed to be stable whenever the supply to the voltage regulator is stable Voltage Identification Definition Sheet 1 of 2 VI D4 VI D3 VID2 VID1 VI DO VI DS Vcc wax VI D4 VID3 VI D2 VID1 VIDO VIDS Vcc wax o o o 0 8375 o o 1 2125 0 8500 1 2250 0 8625 1 2375 0 8750 1 2500 0 8875 1 2625 0 9000 1 2750 0 9125 1 2875 0 9250 1 3000 0 9375 1 3125 0 9500 1 3250 ol ol oi ol ol oi oi ol oi ce o O ol oi ol Of el al al tal al B tal al ai bal al ol ol ol o O ol ai al al tal ol o ol ol ta al al oi ol al ai ol o ai ta O tal el ai el al ol kal oi B B B e el ele el J O Cf CO co cS Of BP bai bal Sl ta B e j e lJ al al al oll of ol o ei of FP e e blei ei of of B H B co ol Bl bS o lJ ol l ta O co al o co al co tal o 0 9625 1 3375 19 e n tel Electrical Specifications Table 2 3 Voltage Identification Definition Sheet 2 of 2 VI D4 VI D3 VID2 VID1 VIDO VIDS Vcc max VI D4 VID3 VID2 VID1 VIDO VIDS Nee max fo o 1 o o 2 0 9750 1 o 13 o T o 1 r350 0 0 1 0 0 0 0 9875 1 0 1 0 0 0 1 3625 0 0 0 1 1 1 1 0000 1 0 0 1 1 1 1 3750 0 0 0 1 1 0 1 0125 1 0 0 1 1 0 1 3875 0 0 0 1 0 1 1 0250 1
83. e has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Intel is currently evaluating whether V must also be removed Driving of the THERMTRIP signals is enabled within 10 ms of the assertion of PWRGOOD and is disabled on de assertion of PNRGOOD Once activated THERMTRI P remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRI P if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 ms of the assertion of PWRGOOD TMS TMS Test Mode Select is a J TAG specification support signal used by debug tools See the eXtended Debug Port Debug Port Design Guide for UP and DP Platforms for further information TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VccA Vcca prov
84. ed its maximum safe operating temperature This indicates that the Thermal Control Circuit TCC has been activated if enabled The TCC will remain active until shortly after the processor deasserts PROCHOT See Section 6 2 3 for more details PROCHOT from each processor socket should be kept separated and not tied together on platform designs Dual Core Intel Xeon Processor 5000 Series Datasheet 65 Bi intel Se Table 5 1 Signal Definitions Sheet 6 of 8 Name Type Description Notes PWRGOOD l PWRGOOD Power Good is an input The processor requires this signal to be a clean 2 indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 2 15 and be followed by a 1 10 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 1 0 REQ 4 0 Request Command must connect the
85. ed only in systems where no debug port connector is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port connector is implemented in the system DBR is treated as a no connect for the processor socket DBR is not a processor signal DBSY 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor FSB agents DP 3 0 1 0 DP 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor FSB agents DRDY 1 0 DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor FSB agents Dual Core Intel Xeon Processor 5000 Serie
86. eon Processor 5000 Series Datasheet m Electrical Specifications n tel Table 2 14 Table 2 15 Table 2 16 2 12 1 PWRGOOD Input and TAP Signal Group DC Specifications Sheet 2 of 2 1 Symbol Parameter Min Max Unit ne lu Input Leakage Current N A x 200 HA lio Output Leakage Current N A x 200 HA RoN Buffer On Resistance 7 11 Q 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All outputs are open drain 3 Vuys represents the amount of hysteresis nominally centered about 0 5 Ver for all PWRGOOD and TAP inputs 4 PWRGOOD input and the TAP signal group must meet system signal quality specification in Section 3 5 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load GTL Asynchronous and AGTL Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Mu Input Low Voltage 0 0 0 5 Vr 0 10 Vr V 3 11 Vin Input High Voltage 0 5 Vy 0 10 Vr Vir ys rents Vou Output High Voltage 0 90 V Vit V 2 5 7 V l Output Low C t H A 8 OL utput Low Curren 0 50 Rrr win Ron_ well lu Input Leakage Current N A x 200 HA 9 Output Leakage lio Current N A 200 HA 10 RoN Buffer On Resistance 7 11 Q 6 Notes 1 Unless otherwise noted all specifications in this table apply
87. er Other VCC AJ18 Power Other VCC AF18 Power Other VCC AJ19 Power Other VCC AF19 Power Other VCC AJ21 Power Other VCC AF21 Power Other VCC AJ22 Power Other VCC AF22 Power Other VCC AJ25 Power Other VCC AJ26 Power Other VCC AN12 Power Other VCC AJ8 Power Other VCC AN14 Power Other VCC AJ9 Power Other VCC AN15 Power Other VCC AK11 Power Other VCC AN18 Power Other VCC AK12 Power Other VCC AN19 Power Other VCC AK14 Power Other VCC AN21 Power Other VCC AK15 Power Other VCC AN22 Power Other VCC AK18 Power Other VCC AN25 Power Other VCC AK19 Power Other VCC AN26 Power Other VCC AK21 Power Other VCC AN8 Power Other VCC AK22 Power Other VCC AN9 Power Other VCC AK25 Power Other VCC J10 Power Other VCC AK26 Power Other VCC J11 Power Other VCC AK8 Power Other VCC J12 Power Other VCC AK9 Power Other VCC J13 Power Other VCC AL11 Power Other VCC J14 Power Other VCC AL12 Power Other VCC J15 Power Other VCC AL14 Power Other VCC J18 Power Other VCC AL15 Power Other VCC J19 Power Other VCC AL18 Power Other VCC J20 Power Other 46 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Land Listing Table 4 1 Land Listing by Land Name Sheet 5 of 9 Land Name po d da Direction Land Name yc Er cu Direction VCC AL19 Power Other VCC J21
88. erization and is not tested Figure 2 2 Dual Core Intel Xeon Processor 5000 Series 1066 MHz Load Current versus Time 155 150 145 140 135 Sustained Current A 130 125 T T T 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 2 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc Not 100 tested Specified by design characterization Dual Core Intel Xeon Processor 5000 Series Datasheet 27 e n tel Electrical Specifications Figure 2 3 Dual Core Intel Xeon Processor 5000 Series 667 MHz and Dual Core I ntel Xeon Processor 5063 MV Load Current versus Time 120 115 110 105 Sustained Current A 100 95 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc TDC m 2 Not 10096 tested Specified by design characterization Table 2 11 Vcc Static and Transient Tolerance Sheet 1 of 2 Icc A Vcc Max V Vcc ryp V Vcc Min V Notes 0 VID 0 000 VID 0 015 VID 0 030 1 2 3 4 5 VID 0 006 VID 0 021 VID 0 036 10 VID 0 013 VID 0 028 VID 0 043 15 VID 0 019 VID 0 034 VID 0 049 20 VID 0 025 VID 0 040 VID 0 055 25 VID 0 031 VID 0 046 VID 0 061 30 VID 0
89. es and sampled on specific clock edges BPM 5 0 I O BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals 2 They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guidelines for more detailed information BPRI l BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB 3 It must connect the appropriate pins of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BR 1 0 1 0 The BR 1 0 signals are sampled on the active to inactive transition of RESET 3 The signal which the agent samples asserted determines its agent ID BRO drives the BREQO signal in the system and is u
90. essor 5063 MV refers to the Mid Power Dual Core Intel Xeon Processor 5000 series Unless otherwise noted the terms Dual Core Intel Xeon 5000 series and processor also refer to the Dual Core Intel Xeon Processor 5063 FC LGA6 Flip Chip Land Grid Array Package The Dual Core Intel Xeon Processor 5000 series package is a Land Grid Array consisting of a processor core mounted on a pinless substrate with 771 lands and includes an integrated heat spreader IHS FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor front side bus or the front side bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC FSB signal quality mechanical and thermal are satisfied Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the p
91. essor lands ordered by land number 4 1 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 1 of 9 Land Name b al Direction Land Name ub us d Direction A03 M5 Source Sync Input Output A334 AH5 Source Sync Input Output A04 P6 Source Sync Input Output A34 AIS Source Sync Input Output A05 L5 Source Sync Input Output A35 AJ6 Source Sync Input Output A06 L4 Source Sync Input Output A20M K3 ASync GTL Input A07 M4 Source Sync Input Output ADS D2 Common Clk Input Output A08 R4 Source Sync Input Output ADSTB0 R6 Source Sync Input Output A09 T5 Source Sync Input Output ADSTB1 AD5 Source Sync Input Output A10 U6 Source Sync Input Output AP0 U2 Common CIk Input Output A11 T4 Source Sync Input Output AP1 U3 Common Clk Input Output A12 U5 Source Sync Input Output BCLK0 F28 CIk Input A13 U4 Source Sync Input Output BCLK1 G28 Clk Input Al4 V5 Source Sync Input Output BINIT AD3 Common Clk Input Output A15 v4 Source Sync Input Output BNR C2 Common Clk Input Output Al6 W5 Source Sync Input Output BPMO AJ2 Common Clk Input Output A174 AB6 Source Sync Input Output BPM1 AJ1 Common Clk Input Output A18 W Source Sync Input Output BPM2 AD2 Common Clk Input Output A19 Y6 Source Sync Input Output BPM3 AG2 Com
92. et T 1 1 Qo o UJ N CO CO CO CO CO CO OO CO k O 0 N O U e O Tables E t Ul ON PF O NNNNNNNNNNNNNNN HH H H H H IO 0 N Ui Q N H 1 1 N Oo E Q Q WH H HU N H H H 4 2 Boxed Dual Core Intel Xeon Processor 5000 Series 1U Passive 2U Active Combination Heat Sink With Removable Fan 89 Boxed Dual Core Intel Xeon Processor 5000 Series 2U Passive Heat Sink 90 2U Passive Dual Core Intel Xeon Processor 5000 Series Thermal Solution Exploded View r rr 90 Top Side Board Keep Out Zones Part IA 92 Top Side Board Keep Out Zones Part 2 93 Bottom Side Board Keep Out Zones 94 Board Mounting Hole Keep Out Zones 95 Volumetric Height Keep Ins sss mmm eene nene mese nnn 96 4 Pin Fan Cable Connector For Active CEK Heat Sink 97 4 Pin Base Board Fan Header For Active CEK Heat Gink essen 98 Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution 100 Dual Core Intel Xeon Processor 5000 Series Features 10 Core Frequency to FSB Multiplier Configuration rr 17 BSEL 2 0 Frequency Table 17 Voltage Identification Detinttion meme mmm eene 19 Loadline Selection Truth Table for LL_I D 1 OI 20 Market Segment Selection Truth Table for MS ID 1 0 seen mI 20 FSB Signal Groups ET 22 Signal Descr
93. fication signals VI D 5 0 to support automatic selection of power supply voltages The processor uses the VTTPWRGD input to determine that the supply voltage for VID 5 0 is stable and within specification Table 2 3 specifies the voltage level corresponding to the state of VID 5 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level The definition provided in Table 2 3 is not related in any way to previous Intel Xeon processors or voltage regulator designs If the processor socket is empty VID 5 0 2 x11111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself The Dual Core Intel Xeon Processor 5000 series provide the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 10 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 11 and Figure 2 4 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 10 and Table 2 11 Power source characteristics must b
94. gure 8 3 illustrates the Common Enabling Kit CEK retention solution The CEK is designed to extend air cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass CEK retention mechanisms can allow the use of much heavier heat sink masses compared to legacy limits by using a load path directly attached to the chassis pan The CEK spring on the secondary side of the baseboard provides the necessary compressive load for the thermal interface material The baseboard is intended to be isolated such that the dynamic loads from the heat sink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures All components of the CEK heat sink solution will be captive to the heat sink and will only require a Phillips screwdriver to attach to the chassis pan When installing the CEK the CEK screws should be tightened until they will no longer turn easily This should represent approximately 8 inch pounds of torque Avoid applying more than 10 inch pounds of torque otherwise damage may occur to retention mechanism components Electrical Requirements Fan Power Supply Active CEK The 4 pin PWM T diode controlled active thermal solution is being offered to help provide better control over pedestal chassis acoustics This is achieved though more accurate measurement of processor die temperature through the processor s temperature
95. h Voltage 0 90 V V V lot Output Low Current N A Var mA 4 0 50 Err wn Ron_min lu Input Leakage Current N A 200 HA 5 6 lio Output Leakage Current N A x 200 HA 5 6 RoN Buffer On Resistance 7 11 Q 7 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Mu is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value 3 Vip is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value 4 Vin and Voy may experience excursions above V However input signal drivers must comply with the signal quality specifications in Section 3 Leakage to Vss with land held at Vr Leakage to V with land held at 300 mV This parameter is based on design characterization and is not tested Dieu Table 2 14 PWRGOOD Input and TAP Signal Group DC Specifications Sheet 1 of 2 1 Symbol Parameter Min Max Unit Notas Vuys Input Hysteresis 120 396 mV 3 PWRGOOD Input Low to 0 5 Vr Vuys MIN 0 5 Vr Vuys MAX V Ve High Threshold Voltage 0 24 0 24 TAP Input Low to High 0 5 Vx Vuys MIN 0 5 Vx Vuys MAX V Threshold Voltage i u PWRGOOD Input High to 0 4 Vr 0 6 Vi V Ve Low Threshold Voltage TAP Input High to Low 0 5 Vrr Vuys MAX 0 5 Ver Vuys min V Threshold Voltage B u Vou Output High Voltage N A Vir V 4 30 Dual Core Intel X
96. he processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Units Notes Shear Ere he 14 5 Tensile pm z 2 4 5 a d sas Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization and incidental applications one time only 5 Handling guidelines are for the package only and do not include the limits of the processor socket Package I nsertion Specifications The Dual Core Intel Xeon Processor 5000 Series can be inserted and removed 15 times from an LGA771 socket Processor Mass Specifications The typical mass of the Dual Core Intel Xeon Processor 5000 series is 21 5 grams 0 76 oz This includes all components which make up the entire processor product Processor Materials The Dual Core Intel Xeon Processor 5000 series are assembled from several components The basic material properties are described in Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel over copper Substrate Fi
97. her R26 VSS Power Other M4 AO7 Source Sync Input Output R27 VSS Power Other M5 A03 Source Sync Input Output R28 VSS Power Other M6 REQ2 Source Sync Input Output R29 vss Power Other R3 FERR PBE ASync GTL Output V24 VSS Power Other R30 VSS Power Other V25 VSS Power Other R4 A08 Source Sync Input Output V26 VSS Power Other R5 VSS Power Other V27 VSS Power Other R6 ADSTBO Source Sync Input Output V28 VSS Power Other R7 VSS Power Other V29 VSS Power Other R8 VCC Power Other v3 VSS Power Other T1 COMP1 Power Other Input v30 VSS Power Other T2 COMP5 Power Other Input v4 A15 Source Sync Input Output T23 VCC Power Other V5 A143 Source Sync Input Output T24 VCC Power Other V VSS Power Other T25 VCC Power Other V7 VSS Power Other T26 VCC Power Other V8 VCC Power Other T27 VCC Power Other WI MS IDO Power Other Output T28 VCC Power Other w2 RESERVED T29 VCC Power Other W23 VCC Power Other T3 VSS Power Other W24 VCC Power Other T30 VCC Power Other W25 VCC Power Other T4 All Source Sync Input Output W26 VCC Power Other T5 A09 Source Sync Input Output W27 VCC Power Other T6 VSS Power Other W28 VCC Power Other T7 VSS Power Other W29 VCC Power Other T8 VCC Power Other W3 TESTHIO1 Power Other Input U1 VSS Power Other W30 VCC Power Other U2 APO Common Clk Input Output WA VSS Power Other U23 VCC Power Other w5 A163 Source Sync Input Output U24 VCC Power Other W6 A18 Source Sync Input Output U25 VCC Power Other W
98. ides isolated power for the analog portion of the internal processor core PLL s Refer to the appropriate platform design guidelines for complete implementation details VccioPLL VeciopLt provides isolated power for digital portion of the internal processor core PLL s Follow the guidelines for VccA and refer to the appropriate platform design guidelines for complete implementation details VCC DIE SENSE VCC DIE SENSE2 VCC DIE SENSE and VCC DIE SENSE2 provide an isolated low impedance connection to each processor core power and ground These signals should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details VID 5 0 VID 5 0 Voltage I D pins are used to support automatic selection of power supply voltages Vcc These are CMOS signals that are driven by the processor and must be pulled up through a resistor Conversely the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 2 3 for definitions of these pins The VR must supply the voltage that is requested by these pins or disable itself VID SELECT VID SELECT is an output from the processor which selects the appropriate VID table for the Voltage Regulator Dual Co
99. ied by the equation Terror Ry N 1 Igymin nk q In N Where Terror sensor temperature error N sensor current ratio k Boltzmann Constant q electronic charge Dual Core Intel Xeon Processor 5000 Series Datasheet Thermal Specifications Table 6 10 Thermal Diode I nterface intel Land Name Land Number Description THERMDA AL1 diode anode THERMDC AK1 diode cathode THERMDA2 AJ7 diode anode THERMDC2 AH7 diode cathode Table 6 11 Thermal Diode Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 200 HA 1 2 lg Emitter Current 5 200 HA no Transistor deality 0 997 1 001 1 005 3 4 5 Beta 0 391 0 760 3 4 Ry Series Resistance 2 79 4 52 6 24 Q Notes Intel does not support or recommend operation of the thermal diode under reverse bias 2 Same as lpw in the diode model in Table 6 9 3 Characterized across a temperature range of 50 80 C 4 Not 100 tested Specified by design characterization 5 The ideality factor no represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current Ic Ig eaVBE nokT 1 Where ls saturation current q electronic charge Vgg voltage across the transistor based emitter junction same nodes as Vp k Boltzmann Constant and T absolute temperature Kelvin 6 The series resista
100. ification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this dynamic load 7 Transient bend is defined as the transient board deflection during manufacturing such as board assembly and system integration It is a relatively slow bending event compared to shock and vibration tests 8 For more information on the transient bend limits please refer to the MAS document entitled Manufacturing with Intel Components using 771 land LGA Package that Interfaces with the Motherboard via a LGA771 Socket 9 Refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for information on heatsink clip load metrology Urdu Dual Core Intel Xeon Processor 5000 Series Datasheet 37 Table 3 2 3 5 3 6 3 7 Table 3 3 38 Mechanical Specifications 10 Ris defined as the radial distance from the center of the LGA771 socket ball array to the center of heatsink load reaction point closest to the socket 11 Applies to populated sockets in fully populated and partially populated socket configurations 12 Through life or product Condition must be satisfied at the beginning of life and at the end of life 13 Rigid back is not allowed The board should flex in the enabled configuration Package Handling Guidelines Table 3 2 includes a list of guidelines on a package handling in terms of recommended maximum loading on t
101. ines are described in the appropriate platform design guidelines Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous processor generations the Dual Core Intel Xeon Processor 5000 series core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier is set during manufacturing The default setting is for the maximum speed of the processor It is possible to override this setting using software see the A 32 Intel Architecture Software Developer s Manual Volume 3A amp 3B This permits operation at lower frequencies than the processor s tested frequency Dual Core Intel Xeon Processor 5000 Series Datasheet m Electrical Specifications n tel Table 2 1 2 4 1 Table 2 2 The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured via the IA32 FLEX BRVID SEL MSR For details of operation at core frequencies lower than the maximum rated processor speed refer to the IA 32 Intel Architecture Software Developer s Manual Volume 3A amp 3B Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1
102. integrated L2 cache All AC timing and signal integrity specifications are at the pads of the processor core I ntel Virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform VRM Voltage Regulator Module DC DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits EVRD Enterprise Voltage Regulator Down DC DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits Vcc The processor core power supply Vss The processor ground Ver FSB termination voltage State of Data The data contained within this document is subject to change It is the most accurate information available by the publication date of this document and is based on final silicon characterization All specifications in this version of the Dual Core Intel Xeon Processor 5000 Series Datasheet can be used for platform design purposes layout studies characterizing thermal capabilities and so forth References Material and concepts available in the following documents may be beneficial when reading this document Document Intel Order Number AP 485 Intel amp
103. iption Table 2 reru get En dE EEN ne binlya r m h an ne Ne ee e E gege 23 Signal Reference Voltages ssssssssssssssssesee enemies se eee nenne eese enn 23 Processor Absolute Maximum Ratings meme menn 24 Voltage and Current Specifications emen nemen 25 VCC Static and Transient Tolerance eet eat r teat nnne nnn 28 BSEL 2 0 VID 5 0 Signal Group DC Specifications sese 30 AGTL Signal Group DC Specifications kk kk kk k kk 30 PWRGOOD Input and TAP Signal Group DC Specifications 30 GTL Asynchronous and AGTL Asynchronous Signal Group Hee e ue EE 31 VITPWRGD DC Specifications s cii 3 u ce ier HENSE Ed Cent en kenl ebe be nina i dan blke nin a earan 31 VCC Overshoot Sp ecificatiO Ss a x xisl nanna ete tenet 32 Package Loading Specifications ccc cece kk kk ememememe nemen 37 Package Handling Guideltnes emm memes 38 Processor Materials an pela banll anam ek ee kila din en n karane D a kdo rore padres 38 Land Listing by Land Nam esses e eme ie e enne nns 43 Land Listing by Land Number 52 Me ERT let el 61 Dual Core Intel Xeon Processor 5000 Series 1066 MHz Thermal Specifications 70 Dual Core Intel Xeon Processor 5000 Series 1066 MHz Thermal Profile A Table 71 Dual Core Intel Xeon Processor 5000 Series 1066 MHz Thermal Profile B Table 72 Dual Core
104. l Xeon Processor 5000 Series 0 1 Reserved 1 0 Reserved D 1 Reserved 20 Dual Core Intel Xeon Processor 5000 Series Datasheet m Electrical Specifications n tel 2 6 2 7 Note 1 The MS_ID 1 0 signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying System management software may utilize these signals to identify the processor installed These signals are not connected to the processor die A logic 0 is achieved by pulling the signal to ground on the package A logic 1 is achieved by leaving the signal as a no connect on the package rad h Reserved or Unused Signals All Reserved signals must remain unconnected Connection of these signals to Vcc Vr Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 Land Listing for a land listing of the processor and the location of all Reserved signals For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signa
105. l to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace for FSB signals For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors R77 TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guidelines The TESTHI signals must be tied to the processor V using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 50 Q then a value between 40 O and 60 Qis required The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group e TESTHI 1 0 can be grouped together with a single pull up to Vy e TESTHI 7 2 can be grouped together with a single pull up to V TESTHI8 cannot be grouped with other TESTHI signals TESTHI9 cannot be grouped with other TESTHI signals TESTHI 10
106. lands are specified as V r which provide termination for the FSB and power to the I O buffers The platform must implement a separate supply for these lands which meets the V specifications outlined in Table 2 10 Dual Core Intel Xeon Processor 5000 Series Datasheet 15 e n tel Electrical Specifications 2 3 1 2 3 2 2 3 3 2 4 16 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the Dual Core Intel Xeon Processor 5000 series are capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cauik such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 10 Failure to do so can result in timing violations or reduced lifetime of the component For further information and guidelines refer to the appropriate platform design guidelines Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must
107. le 2 15 for the DC specifications for the asynchronous GTL signal groups Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain and followed by any other components within the system A translation buffer should be used to Dual Core Intel Xeon Processor 5000 Series Datasheet 23 intel 2 11 Table 2 9 24 Electrical Specifications connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS and TRST Two copies of each signal may be required with each driving a different voltage level Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency core frequency and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Note Processors within a system must operate at the same frequency per bits 15 8 of the IA32 FLEX BRVID SEL MSR however this does not apply to frequency transitions initiated due to thermal events Enhanced HALT Enhanced Intel SpeedStep Technology transitions or assertion of the FORCEPR signal See Chapter 6 Thermal Specifications Low voltage LV mid voltage M
108. lude any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Section 4 1 for the Dual Core Intel Xeon Processor 5000 series land listings and Section 5 1 for signal definitions Voltage and current specifications are detailed in Table 2 10 For platform planning refer to Table 2 11 which provides Voltage Current projections This same information is presented graphically in Figure 2 4 BSEL 2 0 and VID 5 0 signals are specified in Table 2 12 The DC specifications for the AGTL signals are listed in Table 2 13 Legacy signals and Test Access Port TAP signals follow DC specifications similar to GTL The DC specifications for the PWRGOOD input and TAP signal group are listed in Table 2 14 and the Asynchronous GTL signal group is listed in Table 2 15 The VITPWRGD signal is detailed in Table 2 16 Table 2 10 through Table 2 16 list the DC specifications for the processor and are valid only while meeting specifications for case temperature Tcase as specified in Table 6 1 clock frequency and input voltages Care should be taken to read all notes associated with each parameter Table 2 10 Voltage and Current Specifications Sheet 1 of 2 Dual Core Intel Xeon Processor 5000 Series Datasheet Symbol Pa
109. max at specified I cc Please refer to the loadline specifications in Chapter 2 Electrical Specifications i 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on final silicon validation characterization 4 Power specifications are defined at all VIDs found in Table 2 10 The Dual Core Intel Xeon Processor 5000 series may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Dual Core Intel Xeon Processor 5000 Series Datasheet C Thermal Specifications n tel Figure 6 1 Dual Core I ntel Xeon Processor 5000 Series 1066 MHz Thermal Profiles A and B TCASE MAX is a thermal solution design point In actuality units will not significantly exceed TCASE MAX A due to TCC activation 85 80 4 TCASE MAX B QTDP 75 4 35 TCASE MAX AQTDP D 65 Thermal Profile B a Y 2 0 260 x 44 2 2 90 hermal Profile A Y 0 203 x 42 6 55 4 504 45 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power W Notes 1 Thermal Profile A is representative of a volumetrically unconstrained platform Please refer to Table 6 2 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profil
110. mon Clk Input Output A20 Y4 Source Sync Input Output BPM4 AF2 Common Clk Input Output A21 AA4 Source Sync Input Output BPM5 AG3 Common Clk Input Output A22 AD6 Source Sync Input Output BPRI G8 Common Clk Input A23 AA5 Source Sync Input Output BRO F3 Common Clk Input Output A24 AB5 Source Sync Input Output BR1 H5 Common Clk Input A25 AC5 Source Sync Input Output BSELO G29 Power Other Output A26 AB4 Source Sync Input Output BSEL1 H30 Power Other Output A27 AF5 Source Sync Input Output BSEL2 G30 Power Other Output A28 AF4 Source Sync Input Output COMPO A13 Power Other Input A29 AG6 Source Sync Input Output COMP1 T1 Power Other Input A30 AG4 Source Sync Input Output COMP2 G2 Power Other Input A31 AG5 Source Sync Input Output COMP3 R1 Power Other Input A32 AH4 Source Sync Input Output COMP4 J2 Power Other Input COMP5 T2 Power Other Input D40 E19 Source Sync Input Output COMP6 Y3 Power Other Input D41 F20 Source Sync Input Output COMP7 AE3 Power Other Input D42 E21 Source Sync Input Output DOO B4 Source Sync Input Output D43 F21 Source Sync Input Output DO1 C5 Source Sync Input Output D44 G21 Source Sync Input Output Dual Core Intel Xeon Processor 5000 Series Datasheet 43 Table 4 1 intel Land Listing by Land Name Sheet 2 of 9 Land Listing
111. nce Rz provided in Table 6 9 can be used for more accurate readings as needed Table 6 12 Parameters for Tdiode Correction Factor Symbol Parameter Typ Unit Notes Dtrim Diode Ideality used to calculate 1 008 1 Tdiode Offset Tdiode Base 0 k 1 Notes 1 See the Dual Core Inte Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for more information on how to use the Tdiode Offset Tdiode Base and Nirim parameters for fan speed control 8 Dual Core Intel Xeon Processor 5000 Series Datasheet 81 82 Thermal Specifications Dual Core Intel Xeon Processor 5000 Series Datasheet Features 7 7 1 Table 7 1 7 2 intel Features Power On Configuration Options Several configuration options can be configured by hardware The Dual Core Intel Xeon Processor 5000 series samples its hardware configuration at reset on the active to inactive transition of RESET For specifics on these options please refer to Table 7 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset configuration purposes the processor does not distinguish between a warm reset PWRGOOD signal remains asserted during reset and a power on reset Power On Configuration Option Lands Configuration Option Land N
112. nous SGionals eee ee eee kk 23 2 9 Test Access Port TAP Connection 23 2 10 Mixing PrOCOSSOFS ctor catene a bab n een iir neka a wa nerd ina rca EE ee Rae 24 2 11 Absolute Maximum and Minimum Rating 24 2 12 Processor DC SpecifiCatiohs ss rere aeter bore Feri Eia erg eee en be Urea de Ka h b dad 25 2 12 1 VCC Overshoot Specification 0 cece eee eee kk nates 31 2 12 2 Die Voltage Validatton teeter tere ee eee en ene EE emen nnn 32 3 Mechanical Gpechfications 0 xalka na ee eee nenne eser 33 3 1 Package Mechanical Drawings mee mememese emen nnns 33 3 2 Processor Component Keepout Zones 37 3 3 Package Loading Specifications cece eee eee ee ee kak nens 37 3 4 Package Handling Guideltnes sss meme emnes 38 3 5 Package Insertion Gpechficattons sss ennemis 38 3 6 Processor Mass Specifications r emen kaka ka 38 3 7 Processor Materials nme nnne 38 3 8 Processor Markings ii K b WE Se w b r Dad w AR Waran ROME a D T ed kn an Dani D 39 3 9 Processor Land Coordinates eorr poa gz 40 4 PANG li SEQ sao ind m n I UTI conan Mas headend 43 4 1 Dual Core Intel Xeon Processor 5000 Series Land Assignments ees 43 4 1 1 Land Listing by LandName I kk kk kk kaka kk aka 43 4 1 2 Land Listing by Land Number 52 5 Signal Definitions eint te erprobt rhet tse tenti quati der mommmx w W mmmm 61 5al Signal Definitions egen oet iret
113. nsaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins of all agents on the FSB A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 35 3 lands to determine their power on configuration See Section 7 1 A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A202 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction ADS 1 0 ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 lands All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all Dual Core Intel Xeon Processor 5000 series FSB agents ADSTB 1 0
114. ntel Xeon Processor 5000 Series Thermal Solution Exploded View T uem x1 Heat sink i l eer SE screws p Heat sink V 1 Thermal Interface a Material lt NU HH Heat sink standoffs J Motherboard and Lee processor mn Protective Tape s i met CEK spring Chassis pan Notes 1 The heat sinks represented in these images are for reference only and may not represent the final boxed processor heat sinks 2 The screws springs and standoffs will be captive to the heat sink This image shows all of the components in an exploded view 3 Itis intended that the CEK spring will ship with the base board and be pre attached prior to shipping 8 2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor 90 Dual Core Intel Xeon Processor 5000 Series Datasheet C Boxed Processor Specifications n tel 8 2 1 Boxed Processor Heat Sink Dimensions CEK The boxed processor will be shipped with an unattached thermal solution Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8 4 through Figure 8 8 Figure 8 9 through Figure 8 10 are the mechanical drawings for the 4 pin board fan header and 4 pin connector used for the active CEK fan heat sink solution Dual C
115. o Vol 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note FORCEPR The FORCEPR force power reduction input can be used by the platform to cause the Dual Core Intel Xeon Processor 5000 series to activate the Thermal Control Circuit TCC GTLREF ADD CO GTLREF ADD CL GTLREF ADD CO and GTLREF ADD CL determine the signal reference level for AGTL address and common clock input lands on processor core 0 and processor core 1 respectively GTLREF ADD is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Please refer to the appropriate platform design guidelines for additional details GTLREF DATA CO GTLREF DATA CL GTLREF DATA CO AND GTLREF DATA CL determine the signal reference level for AGTL data input lands on processor core 0 and processor core 1 respectively GTLREF DATA is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Please refer to the appropriate platform design guidelines for additional details HIT HITM ERR 1 0 1 0 HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Internal Error is asserted by a processor as the result of an internal
116. of the processor FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MCERR 1 0 MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the 1A 32 Software Developer s Manual Volume 3 System Programming Guide MS ID 1 0 These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying The Dual Core Intel Xeon Processor 5000 series pull these signals to ground on the package for a logic 0 as these signals are not connected to the processor die A logic 1 is a no connect on the Dual Core Intel Xeon Processor 5000 series package PROCHOT PROCHOT Processor Hot will go active when the processor s temperature monitoring sensor detects that the processor has reach
117. on Clk Input Output AE9 VCC Power Other AG20 VSS Power Other AF1 TDO TAP Output AG21 VCC Power Other AF10 VSS Power Other AG22 VCC Power Other AF11 VCC Power Other AG23 VSS Power Other AF12 VCC Power Other AG24 VSS Power Other AF13 VSS Power Other AG25 VCC Power Other AF14 VCC Power Other AG26 VCC Power Other AG27 VCC Power Other AJ11 VCC Power Other AG28 VCC Power Other AJ12 VCC Power Other AG29 VCC Power Other AJ13 VSS Power Other AG3 BPM5 Common Clk Input Output AJ14 VCC Power Other AG30 VCC Power Other AJ15 VCC Power Other AG4 A30 Source Sync Input Output AJ16 vss Power Other AG5 A31 Source Sync Input Output AJ17 VSS Power Other AG6 A29 Source Sync Input Output AJ18 VCC Power Other AG7 VSS Power Other AJ19 VCC Power Other AG8 VCC Power Other AJ2 BPMO Common Clk Input Output Dual Core Intel Xeon Processor 5000 Series Datasheet 53 intel 54 Land Listing Table 4 2 Land Listing by Land Number Sheet 3 of 9 po Land Name Es sa Direction pe Land Name La Direction AG9 VCC Power Other AJ20 VSS Power Other AH1 VSS Power Other AJ21 VCC Power Other AH10 VSS Power Other AJ22 VCC Power Other AH11 VCC Power Other AJ 23 VSS Power Other AH12 VCC Power Other AJ 24 VSS Power Other AH13 VSS Power Other AJ25 VCC Power Other AH14 VCC Power Other AJ 26 VCC P
118. on in rackmount chassis is not recommended It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor thermal solution should not be preheated by other system components Meeting the processor s temperature specification is the responsibility of the system integrator 2U Passive Heat Sink Solution 2U Rack or Pedestal A chassis duct is required for the 2U passive heat sink In this configuration the thermal profile see Section 6 should be followed by supplying 27 CFM of airflow through the fins of the heat sink with a 0 or no duct bypass and a back pressure of 0 182 in H20 The T 4 temperature of 40 C should be met This may require the use of superior design techniques to keep Trise at or below 5 C based on an ambient external temperature of 35 C Boxed Processor Contents A direct chassis attach method must be used to avoid problems related to shock and vibration due to the weight of the thermal solution required to cool the processor The board must not bend beyond specification in order to avoid damage The boxed processor contains the components necessary to solve both issues The boxed processor will include the following items Dual Core Intel Xeon Processor 5000 series Unattached Heat Sink Solution 4 screws 4 springs and 4 heat sink standoffs all captive to the heat sink Thermal Interface Material pre applied on heat sink
119. ore Intel Xeon Processor 5000 Series Datasheet 91 Boxed Processor Specifications r S 9 8 Q3NO11V SIN3NOdMO3 GUVOBYIHLON ON 1004334 839N J QuYOB ONIYdS J39 e NOISH3A f 1320S Nid32 N03 ONNAVNA X33 7NOI1218138 1H513H LNINOdNOD QUYOBUJHLOM XVN WWII Eer e EP Q3W011V LN3H3OYTd IN3NOdHOD QNYOGU3HLON ON 97 zz ze E 3B NOILOIYLSIY LH9I3H LN3NOdNOD XVW MN 0 L SL2 O V3WV A18N3SSYSIQ JNISLV3H S 9 AINO SISOd Nd 3Al1VulSn11I tele NOI12INIS3U 1H913H IN3NOdOO XVM NN 0 L SLZ O V3uY XNISIV3H O NOI12181S38 1H913H 1N3NOdMO3 XVW M 0 E 8110 M EIER SNIQ 303 2 LHS 335 2 ANS aas 3N 11100 MNIS1V3H 3131834 1 1Y8 330108 134208 SNIQ 803 2 LHS 33 3NI1100 XNISLV3H 32N38343U 04 NMOHS 08v08 1931 NO1481 S310N ET EI a uL D er 3dis AuvWiHd NOI1VHOdNO2 131N JO IN3SNOO N3LIINA YOIYd JHL LNOHLIN 0314 GON NO 134V14S Q 032n008d3N 038019810 38 LON AYN S1N31NO2 SLI ANY 32N3014N09 NI 035010910 SI 11 NOIIVWSOJNI 1VILN3Q 4NOO NOILVYOdYOD 131NI SNIVINOO 9NINYHO SIHL Dual Core Intel Xeon Processor 5000 Series Datasheet ome Y S 9 L 9 Top Side Board Keep Out Zones Part 1 intel Figure 8 4 92 intel Boxed Processor Specifications Top Side Board Keep Out Zones Par
120. ould not be used as a mechanical reference or load bearing surface for thermal or mechanical solutions Please refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for further details Package Loading Specifications Parameter Board R Min Max Unit Notes Thickness Static Apply for all 25mm 80 133 N 1 2 3 9 Compressive Load board thickness lt R lt 18 30 bf 10 11 from 1 57 mm 45mm 12 13 0 062 to 2 54 mm R gt 45mm 80 311 N 0 100 18 70 bf Dynamic NA NA NA 311 N max static N 1 3 4 5 Compressive Load compressive load 6 222 N dynamic loading bf 70 Ibf max static compressive load 50 Ibf dynamic loading Transient Bend 1 57 mm NA NA 750 He 1 3 7 8 Limits 0 062 2 16 mm 700 0 085 2 54 mm 650 0 100 Notes 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface Loading limits are for the LGA771 socket Dynamic compressive load applies to all board thickness Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 6 Test condition used a heatsink mass of 1 Ibm with 50 g acceleration measured at heatsink mass The dynamic portion of this spec
121. ower Other AH15 VCC Power Other AJ27 VSS Power Other AH16 VSS Power Other AJ28 VSS Power Other AH17 VSS Power Other AJ29 VSS Power Other AH18 VCC Power Other AJ3 RESERVED AH19 VCC Power Other AJ 30 VSS Power Other AH2 TEST_BUS Power Other AJ4 VSS Power Other AH20 VSS Power Other AJ5 A34 Source Sync Input Output AH21 VCC Power Other AJ6 A35 Source Sync Input Output AH22 VCC Power Other AJ7 THERMDA2 Power Other Output AH23 VSS Power Other AJ8 VCC Power Other AH24 VSS Power Other AJ9 VCC Power Other AH25 VCC Power Other AK1 THERMDC Power Other Output AH26 VCC Power Other AK10 VSS Power Other AH27 VCC Power Other AK11 VCC Power Other AH28 VCC Power Other AK12 VCC Power Other AH29 VCC Power Other AK13 VSS Power Other AH3 VSS Power Other AK14 VCC Power Other AH30 VCC Power Other AK15 VCC Power Other AH4 A32 Source Sync Input Output AK16 VSS Power Other AH5 A33 Source Sync Input Output AK17 VSS Power Other AH6 VSS Power Other AK18 VCC Power Other AH7 THERMDC2 Power Other Output AK19 VCC Power Other AH8 VCC Power Other AK2 VSS Power Other AH9 VCC Power Other AK20 VSS Power Other AJ1 BPM1 Common Clk Input Output AK21 VCC Power Other AJ10 VSS Power Other AK22 VCC Power Other AK23 VSS Power Other AL8 VCC DIE SENSE2 Power Other Output AK24 VSS Power Other AL9 VCC Power Other AK25 VCC Power Other AM1 VSS Power Other AK26 VCC Power Other AM10 VSS Power Other AK27 VSS Power Other AM11 VCC Power
122. passive 2U active combination solution in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and strong side directional airflow is not an issue The 1U passive active combination solution with the fan removed and the 2U passive thermal solution require the use of chassis ducting and are targeted for use in rack mount servers The retention solution used for these products is called the Common Enabling Kit or CEK The CEK base is compatible with both thermal solutions and uses the same hole locations as the Intel Xeon processor with 800 MHz FSB The 1U passive active combination solution will utilize a removable fan with a 4 pin pulse width modulated PWM T diode control Use of a 4 pin PWM T diode controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the motherboards s ability to directly control the RPM of the processor heat sink fan Please see Section 8 3 for more details Figure 8 1 through Figure 8 3 are representations of the two heat sink solutions Boxed Dual Core Intel Xeon Processor 5000 Series 1U Passive 2U Active Combination Heat Sink With Removable Fan Dual Core Intel Xeon Processor 5000 Series Datasheet 89 e n tel Boxed Processor Specifications Figure 8 2 Boxed Dual Core I ntel Xeon Processor 5000 Series 2U Passive Heat Sink Figure 8 3 2U Passive Dual Core I
123. probe and capture FSB signals There are two sets of considerations to keep in mind when designing a Dual Core Intel Xeon Processor 5000 series based system that can make use of an LAI mechanical and electrical Dual Core Intel Xeon Processor 5000 Series Datasheet 103 e n tel Debug Tools Specifications 9 3 1 9 3 2 104 Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI plugs into the socket while the processor plugs into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may include differerent requirements from the space normally occupied by the heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyze
124. ptions 2 These signals may be driven simultaneously by multiple agents Wired OR Dual Core Intel Xeon Processor 5000 Series Datasheet Electrical Specifications Table 2 7 Table 2 8 2 8 2 9 intel Table 2 7 outlines the signals which include on die termination Rrr Open drain signals are also included Table 2 8 provides signal reference voltages Signal Description Table Signals with R rr Signals with no Rer A 35 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BPRI COMP 7 4 D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK A20M BCLK 1 0 BPM 5 0 BR 1 0 BSEL 2 0 COMP 3 0 FERR PBE GTLREF ADD C 1 0 GTLREF DATA C 1 0 IERR IGNNE INIT LINTO INTR LINTI NMI LL ID 1 0 MS ID 1 0 PWRGOOD RESET SKTOCC SMI STPCLK TDO TESTHI 11 0 THERMDA THERMDA2 THERMDC THERMDC2 THERMTRIP VCC_DIE_SENSE VCC DIE SENSE2 VID 5 0 VID SELECT VSS DIE SENSE VSS DIE SENSE2 VITPWRGD MCERR PROCHOT REQ 4 0 RS 2 0 RSP TCK2 TDI TEST BUS TMS TRDY TRST Open Drain Signals BPM 5 0 BRO FERR PBE IERRZ PROCHOT TDO THERMTRIP Notes 1 Signals that do not have Rrr nor are actively driven to their high voltage level 2 The on die termination for these signals is not Ry TCK TDI and TMS have an approximately 150 KQ pullup to Ver Signal Reference Voltages
125. put Output C22 vss Power Other B11 VSS Power Other C23 VCCI OPLL Power Other Input B12 D13 Source Sync Input Output C24 VSS Power Other B13 RESERVED C25 VIT Power Other Dual Core Intel Xeon Processor 5000 Series Datasheet 55 intel Land Listing Table 4 2 Land Listing by Land Number Sheet 5 of 9 po Land Name s d Direction pong Land Name dud cdd Direction B14 VSS Power Other C26 VIT Power Other B15 D53 Source Sync Input Output C27 VIT Power Other B16 D55 Source Sync Input Output C28 VIT Power Other B17 VSS Power Other C29 VIT Power Other B18 D57 Source Sync Input Output C3 LOCK Common Clk Input Output B19 D60 Source Sync Input Output C30 VIT Power Other B2 DBSY Common Clk Input Output CA VSS Power Other B20 VSS Power Other C5 DO1 Source Sync Input Output B21 D59 Source Sync Input Output C6 D03 Source Sync Input Output B22 D63 Source Sync Input Output C7 VSS Power Other B23 VSSA Power Other Input C8 DSTBNO Source Sync Input Output B24 vss Power Other C9 RESERVED B25 VIT Power Other D1 RESERVED B26 VIT Power Other D10 D22 Source Sync Input Output B27 VIT Power Other D11 D15 Source Sync Input Output B28 VIT Power Other D12 VSS Power Other B29 VIT Power Other D13 D25 Source Sync Input Output B3 RSO Common Clk Input D14 RESERVED B30 VIT Power Other D1
126. r 5000 Series Datasheet 57 intel Land Listing Table 4 2 Land Listing by Land Number Sheet 7 of 9 po Land Name Es x Direction N Land Name NIN Direction H16 DP2 Common Clk Input Output J28 VCC Power Other H17 VSS Power Other J29 VCC Power Other H18 VSS Power Other J3 RESERVED H19 VSS Power Other J30 VCC Power Other H2 GTLREF_ADD_C1 Power Other Input J4 VSS Power Other H20 VSS Power Other J5 REQ1 Source Sync Input Output H21 VSS Power Other J6 REQ4 Source Sync Input Output H22 VSS Power Other J7 VSS Power Other H23 VSS Power Other J8 VCC Power Other H24 VSS Power Other J9 VCC Power Other H25 VSS Power Other K1 LINTO ASync GTL Input H26 VSS Power Other K2 VSS Power Other H27 VSS Power Other K23 VCC Power Other K24 VCC Power Other M7 VSS Power Other K25 VCC Power Other M8 VCC Power Other K26 VCC Power Other N1 PWRGOOD Power Other Input K27 VCC Power Other N2 IGNNE ASync GTL Input K28 VCC Power Other N23 VCC Power Other K29 VCC Power Other N24 VCC Power Other K3 A20M ASync GTL Input N25 VCC Power Other K30 VCC Power Other N26 VCC Power Other K4 REQO Source Sync Input Output N27 VCC Power Other K5 VSS Power Other N28 VCC Power Other K6 REQ3 Source Sync Input Output N29 VCC Power Other K7 VSS Power Other N3 VSS Power Other K8 VCC Power Other N30
127. r Other VCC N27 Power Other VCC Y8 Power Other VCC N28 Power Other VCC DIE SENSE AN3 Power Other Output VCC N29 Power Other VCC_DIE_SENSE2 AL8 Power Other Output VCC N30 Power Other VCCA A23 Power Other Input VCC N8 Power Other VCCIOPLL G23 Power Other Input VCC P8 Power Other VIDO AM2 Power Other Output VCC R8 Power Other VID1 AL5 Power Other Output VCC T23 Power Other VID2 AM3 Power Other Output VCC T24 Power Other VID3 AL6 Power Other Output VCC T25 Power Other VIDA AK4 Power Other Output VCC T26 Power Other VID5 ALA Power Other Output VCC T27 Power Other VID_SELECT AN7 Power Other Output VCC T28 Power Other VSS A12 Power Other Dual Core Intel Xeon Processor 5000 Series Datasheet 47 intel Land Listing Table 4 1 Land Listing by Land Name Sheet 6 of 9 Land Name pons AE od Direction Land Name ur TEMA Direction VCC T29 Power Other VSS A15 Power Other VCC T30 Power Other VSS A18 Power Other VCC T8 Power Other VSS A2 Power Other VCC U23 Power Other VSS A21 Power Other VCC U24 Power Other VSS A24 Power Other VCC U25 Power Other VSS A6 Power Other VCC U26 Power Other VSS A9 Power Other VCC U27 Power Other VSS AA23 Power Other VCC U28 Power Other VSS AA24 Power Other VCC U29 Power Other VSS AA25 Power Other VCC U30 Power Other VSS AA26 Power
128. r core Yes 667 MHz FC LGA6 4 MB total 1066 MHz 771 Lands Notes 1 Total accessible size of L2 caches may vary by one cache line pair 128 bytes per core depending on usage and operating environment The Dual Core Intel Xeon Processor 5000 series based platforms implement independent core voltage Vcc power planes for each processor FSB termination voltage Vor is shared and must connect to all FSB agents The processor core voltage utilizes power delivery guidelines specified by VRM EVRD 11 0 and its associated load line Refer to the appropriate platform design guidelines for implementation details The Dual Core Intel Xeon Processor 5000 series support a 1066 667 MHz Front Side Bus frequency The FSB utilizes a split transaction deferred reply protocol and Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or a 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8 5 GBytes second 5 3 GBytes second for Dual Core Intel Xeon Processor 5000 series 667 Finally the FSB is also used to deliver interrupts Signals on the FSB use Assisted Gunning Transceiver Logic AGTL level
129. r vendor for electrical specifications and load models for the LAI solution they provide Dual Core Intel Xeon Processor 5000 Series Datasheet
130. rameter Min Typ Max Unit Bores VID VID range 1 0750 1 3500 Vec Vcc for Dual Core Intel Xeon See Table 2 11 and Figure 2 4 2 3 4 6 Processor 5000 series core FMB 11 processor VVID_STEP VID step size during a transition 12 5 mV VVID_SHIFT Total allowable DC load line shift 425 mV 12 from VID steps Vit FSB termination voltage DC AC 1 140 1 20 1 260 V 10 14 specification lec Icc for Dual Core Intel Xeon 115 A 4 5 6 11 Processor 5000 series with multiple VID 667 MHz lec Icc for Dual Core Intel Xeon 150 A 4 5 6 11 Processor 5000 series with multiple VID 1066 MHz lec Icc for Dual Core Intel Xeon 115 A 4 5 6 11 Processor 5063 MV with multiple VID Icc REsET lec RESET for Dual Core Intel Xeon 115 A 18 Processor 5000 series with multiple VID 667 MHz 25 intel Electrical Specifications Table 2 10 Voltage and Current Specifications Sheet 2 of 2 26 Symbol Parameter Min Typ Max Unit i lcc RESET lec reset for Dual Core Intel Xeon 150 A 18 i Processor 5000 series with multiple VID 1066 MHz lec RESET lec RESET for Dual Core Intel Xeon 115 A 18 E Processor 5063 MV with multiple VID l Steady state FSB Termination 6 1 A 16 Current Ir POWER UP Power up FSB Termination Current 8 0 A 19 lec Toc Thermal Design Current TDC for 100 A 6 15 i Dual Core Intel Xeon Processor 5000 series 667 MHz lec toc Thermal Design Cur
131. ransfer Cache per core 2 x 2 MB On die full speed Level 2 L2 Cache with 8 way associativity and Error Correcting Code ECC 667 1066 MHz front side bus 65 nm process technology Dual processing DP server support Intel NetBurst microarchitecture Hyper Threading Technology allowing up to 8 threads per platform Hardware support for multi threaded applications Intel virtualization Technology Intel Extended Memory 64 Technology Intel EM64T Execute Disable Bit XD Bit Enables system support of up to 64 GB of physical memory Enhanced branch prediction Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance Advanced Dynamic Execution Very deep out of order execution System Management mode Machine Check Architecture MCA Interfaces to Memory Controller Hub The Dual Core Intel Xeon Processor 5000 series are designed for high performance dual processor server and workstation applications Based on the Intel NetBurst microarchitecture and Hyper Threading Technology HT Technology it is binary compatible with previous Intel Architecture 1A 32 processors The Dual Core Intel Xeon Processor 5000 series are scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP Windows Server 2003 Linux and UNI X The Dual Core Intel Xeon Processor 5000 series deliver compute power
132. re Intel Xeon Processor 5000 series pull this signal to ground on the package as this signal is not connected to the processor die VSS DIE SENSE VSS DIE SENSE2 VSS DIE SENSE and VSS DIE SENSE2 provide an isolated low impedance connection to each processor core power and ground These signals should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details Vssa Vssa provides an isolated internal ground for internal PLL s Do not connect directly to ground This pin is to be connected to Vcca and Vcciopi through a discrete filter circuit Dual Core Intel Xeon Processor 5000 Series Datasheet 67 Bi intel RN Table 5 1 Signal Definitions Sheet 8 of 8 Name Type Description Notes Vir P The FSB termination voltage input pins Refer to Table 2 10 for further details VTT OUT O The VTT_OUT signals are included in order to provide a local V for some signals that require termination to V4 on the motherboard VITPWRGD l The processor requires this input to determine that the supply voltage for BSEL 2 0 and VID 5 0 is stable and within specification Notes 1 For this pin on Dual Core Intel Xeon Processor 5000 series the maximum number of symmetric agents is one Maximum number of priority agents is zero
133. rent TDC for 130 A 6 15 P Dual Core Intel Xeon Processor 5000 series 1066 MHz lcc TDC Thermal Design Current TDC for 100 A 6 15 i Dual Core Intel Xeon Processor 5063 MV lec vrTOUT DC current that may be drawn 580 mA 17 i from VrTrour per land lec vccA lec for PLL power lands 120 mA 8 Icc vccioPLL Icc for PLL power lands 100 mA 8 Icc GTLREF lec for GTLREF 200 HA 9 l cc I cc during active thermal control 150 A circuit TCC for Dual Core Intel Xeon Processor 5000 series Itcc I cc during active thermal control 115 A circuit TCC for Dual Core Intel Xeon Processor 5063 MV IsGNT I cc Stop Grant for Dual Core Intel 50 A 7 Xeon Processor 5000 series 667 MHz lsGNT lcc Stop Grant for Dual Core Intel 60 A 7 Xeon Processor 5000 series 1066 MHz IsGNT lcc Stop Grant for Dual Core Intel 40 A 7 Xeon Processor 5063 MV Notes 1 2 3 eoo md Unless otherwise noted all specifications in this table apply to all processors and are based on final silicon validation characterization These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 5 for more information The voltage specification requirements are measured across the VCC DIE SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance
134. rete points on Figure 2 4 3 Theloadlines specify voltage limits at the die measured at the VCC DIE SENSE and VSS DIE SENSE lands and at the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Please refer to the appropriate platform design guide for details on VR implementation 4 Non shading denotes the expected lcc range applies to both Dual Core Intel Xeon Processor 5000 series 1066 MHz amp 667 MHz and Dual Core Intel Xeon Processor 5063 MV Shading denotes the expected lcc range applies to Dual Core Intel Xeon Processor 5000 series 1066 MHz only 120 A 150 A Figure 2 4 Vcc Static and Transient Tolerance Load Lines Icc A 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 VID 0 000 1 d VID 0 020 4 Vcc Maximum VID 0 040 4 VID 0 060 4 VID 0 080 4 VID 0 100 4 SC VID 0 120 4 Minimurn Vcc V VID 0 140 4 VID 0 160 4 Voc Typical VID 0 180 4 VID 0 200 VID 0 220 VID 0 240 4 VID 0 260 Notes 1 2 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 12 1 for VCC overshoot specifications Refer to Table 2 10 for processor VID information Dual Core Intel Xeon P
135. rical Specifications Table 2 17 Figure 2 5 2 12 2 32 maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC DIE SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vcc overshoot above VID 50 mV 2 5 Tos MAX Time duration of Vcc overshoot above VID 25 us 2 5 Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos co o 8 o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID Notes 1 Vos is the measured overshoot voltage above VID 2 Tos is the measured time duration above VID Die Voltage Validation Core voltage VCC overshoot events at the processor must meet the specifications in Table 2 17 when measured across the VCC DIE SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands Overshoot events that are 10 ns in duration may be ignored These measurement of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope 8 Dual Core Intel Xeon Processor 5000 Series Datasheet Mechanical Specifications n te 3 Mechanical Specifications The Dual Core Intel Xeon Processor 5000 series are packaged in a
136. rmal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel Architecture Software Developer s Manual for specific register and programming details PROCHOT is designed to assert at or a few degrees higher than maximum Tease as specified by Thermal Profile A when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum Tcase when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature the case temperature or the thermal diode temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of TcAsg PROCHOT or Tdiode on random processor samples FORCEPR Signal The FORCEPR force power reduction input can be used by the platform to cause the Dual Core Intel Xeon Processor 5000 series to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal Assertion of the FORCEPR signal will activate TCC for both processor cores The TCC will remain active until the sy
137. rocessor 5000 Series Datasheet 29 e n tel Electrical Specifications Refer to Table 2 11 for processor VCC information The load lines specify voltage limits at the die measured at the VCC DIE SENSE and VSS DIE SENSE lands and at the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Please refer to the appropriate platform design guide for details on VR implementation gt t Table 2 12 BSEL 2 0 VI D 5 0 Signal Group DC Specifications Symbol Parameter Min Max Units Notes RoN BSEL 2 0 VID 5 0 N A 120 Q 2 Buffer On Resistance loL Output Low Current N A 2 4 mA 2 3 lou Output High Current N A 460 HA 2 3 VTOL Voltage Tolerance 0 95 Vit 1 05 Vr V 4 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 These parameters are based on design characterization and are not tested 3 lo is measured at 0 10 V lopis measured at 0 90 V7 4 Please refer to the appropriate platform design guide for implementation details Table 2 13 AGTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vu Input Low Voltage 0 0 GTLREF 0 10 Ver V 2 Vin Input High Voltage GTLREF 0 10 Mr V V 3 4 Vou Output Hig
138. rupt is latched the processor will return to the Stop Grant state or HALT Power Down state as appropriate Enhanced HALT Snoop State The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT state is enabled via the BIOS The processor will remain in the lower bus ratio and VID operating point of the Enhanced HALT state While in the Enhanced HALT Snoop state snoops and interrupt transactions are handled the same way as in the HALT Snoop state After the snoop is serviced or the interrupt is latched the processor will return to the Enhanced HALT state Enhanced I ntel SpeedStep Technology The Dual Core Intel Xeon Processor 5000 series support Enhanced Intel SpeedStep Technology This technology enables the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled Dual Core Intel Xeon Processor 5000 Series Datasheet Features Note intel Not all Dual Core Intel Xeon Processor 5000 series are capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature will be provided in future releases of the Dual Core Intel Xeon Processor 5000 Series Specification Update when available Enhanced Intel SpeedStep Technology creates proces
139. s Datasheet 63 intel Table 5 1 Signal Definitions Signal Definitions Sheet 4 of 8 Name DSTBN 3 0 Type 1 0 Description Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO D 31 16 DBI1 D 47 32 DBI2 D 63 48 DBI3 DSTBNO DSTBN1 DSTBN2 DSTBN3 Notes DSTBP 3 0 FERR PBE 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO D 31 16 DBI1 D 47 32 DBI2 D 63 48 DBI3 DSTBPO DSTBP1 DSTBP2 DSTBP3 FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer t
140. sed by the processor to request the bus These signals do not have on die termination and must be terminated BSEL 2 0 O The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer All FSB agents must operate at the same frequency The Dual Core Intel Xeon Processor 5000 series currently operate at either 667 or 1066 MHz FSB frequency For more information about these signals including termination recommendations refer to the appropriate platform design guideline COMP 3 0 l COMP 3 0 must be terminated to Vss on the baseboard using precision resistors These inputs configure the AGTL drivers of the processor Refer to the appropriate platform design guidelines for implementation details COMP 7 4 l COMP 7 4 must be terminated to V on the baseboard using precision resistors These inputs configure the AGTL drivers of the processor Refer to the appropriate platform design guidelines for implementation details 62 Dual Core Intel Xeon Processor 5000 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 3 of 8 intel Name D 63 0 Type 1 0 Description D 63 0 Data are the data signals These signals provide a 64 bit data
141. sensors that use the Diode Equation to determine the processor temperature Transistor Model parameters Table 6 11 have been added to support thermal sensors that use the transistor equation method The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor When calculating a temperature based on thermal diode measurements a number of parameters must be either measured or assumed Most devices measure the diode ideality and assume a series resistance and ideality trim value although some are capable of also measuring the series resistance Calculating the temperature is then accomplished by using the equations listed under Table 6 9 In most temperature sensing devices an expected value for the diode ideality is designed in to the temperature calculation equation If the designer of the temperature sensing device assumes a perfect diode the ideality value also called Nirim will be 1 000 Given that most diodes are not perfect the designers usually select an Nirim value that more closely matches the behavior of the diodes in the processor If the processors diode ideality deviates from that of Nirim each calculated temperature will be offset by a fixed amount The temperature offset can be calculated with the equation
142. sor performance states P states or voltage frequency operating points P states are lower power capability states within the Normal state as shown in Figure 7 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The Dual Core Intel Xeon Processor 5000 series have hardware logic that coordinates the requested processor voltage between the processor cores The highest voltage that is requested for either of the processor cores is selected for that processor Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new
143. sor s chipset and clock synthesizer All FSB agents must operate at the same core and FSB frequency See the appropriate platform design guidelines for further details BSEL 2 0 Frequency Table BSEL2 BSEL1 BSELO Bus Clock Frequency 0 0 0 266 67 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 166 67 MHz 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 I Reserved Dual Core Intel Xeon Processor 5000 Series Datasheet 17 e n tel Electrical Specifications 2 4 2 Figure 2 1 Phase Lock Loop PLL and Filter Vcca and Vcciopi are power sources required by the PLL clock generators on the Dual Core Intel Xeon Processor 5000 series Since these PLLs are analog in nature they require low noise power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings that is maximum frequency To prevent this degradation these supplies must be low pass filtered from Va The AC low pass requirements are as follows 0 2 dB gain in pass band 0 5 dB attenuation in pass band 1 Hz gt 34 dB attenuation from 1 MHz to 66 MHz gt 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2 1 For recommendations on implementing the filter refer to the appropriate platform design guidelines Phase Lock Loop PLL Filter Requirements e iU forbidc On PER W
144. stem deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when FORCEPR is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR signal may cause noticeable platform performance degradation Refer to the appropriate platform design guidelines for details on implementing the FORCEPR signal feature THERMTRI P Signal Regardless of whether or not Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 5 1 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Intel also recommends the removal of V Dual Core Intel Xeon Processor 5000 Series Datasheet m Thermal Specifications n tel 6 2 6 6 2 7 Tcontrol and Fan Speed Reduction
145. t 2 Figure 8 5 10001 0 9 9 NOI12181S3H 1H913H IN3NOdNOO XVN WW O L GI2 0 V3uV WNISIV3H NOI12181S38 1H913H 1N3NOdNOD XVW WW 0 z r l S 9 a 8 ege rm d Rm i P MEER Be Q3NOTIV SIN3NOdWO2 QNYOGNHIOH ON 100433 YIONI4 GYVOG 9NIMdS J39 o NOILOIYLS3Y 1HOI3H LN3NOdHOD QNVOGUIHLON XYM HHII EH A G3OT1Y ISO 1NNOdMOO GYVOBYIHLON ON Q PE 25 GE SAR US se 2 BR Sa gz XB s237 zz Sa NOLLOIBIS3U 1H913H 1N3NOMOO XYM MN O L SL2 0 V3UV ATONISSVSIO MNISIV3H 00r 2 96 09 00 2 HR s21 2 86 t6 S310H HONOYHL 9NIINQON NOILNTOS 1VWH3Hl 100 4 oor 2070 1 Sona 018 0001 ISIE 8 006 D 008 2 02 006 98122 180 21 98 26 IMN 9 6p AWO S3s0dund 3AI1VUISTTII HOJ AYYONNOG f 134208 97071 19 92 Let C ISZ 0 0 9 910 10001 0 EEN 66 6 Ier 66 8 32N34343U 403 NMOHS QUVOG 1931 mene oS EM gt Dis SS SS zs SF S8523 53 mua xu ue du SS Se EE AnOd33M 20 AuviWiHd QuvOSH3H LON gt NOILYYOdYOD 131N 40 IN3SNOO NILLIYM YOIYd FHL LNOHLIM 039012910 3G LON AVN SINJINOO SLI ONY EE Eege D I a d Y S 9 L 9 93 Dual Core Intel Xeon Processor 5000 Series Datasheet Boxed Processor Specifications intel Bottom Side Board Keep Out Zones Figure 8 6
146. t damage to the processor Intel has developed these thermal profiles to allow OEMs to choose the thermal solution and environmental parameters that best suit their platform implementation Refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for details on system thermal solution design thermal profiles and environmental considerations The Dual Core Intel Xeon Processor 5063 MV supports a single Thermal Profile targeted at volumetrically constrained thermal environments for example blades 1U form factors With this Thermal Profile it s expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for further details The upper point of the thermal profile consists of the Thermal Design Power TDP defined in Table 6 1 Table 6 4 Table 6 7 and the associated TcAsg value It should be noted that the upper point associated with Thermal Profile B x TDP and y Tcase MAX B TDP represents a thermal solution design point In actuality the processor case temperature will not reach this value due to TCC activation refer to Figure 6 1 and Figure 6 2 The lower point of the thermal profile consists of x P profile min and y Tcase max P profile min P profile min is defined as the processor power at which Tcas
147. t wide registers and a separate register for data movement Streaming SIMD3 SSE3 instructions provide highly efficient double precision floating point SIMD integer and memory management operations Other processor enhancements include core frequency improvements and microarchitectural improvements The Dual Core Intel Xeon Processor 5000 series support Intel Extended Memory 64 Technology Intel EM64T as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel Extended Memory 64 Technology and its programming model can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel com technology 64bitextensions In addition the Dual Core Intel Xeon Processor 5000 series support the Execute Disable Bit functionality When used in conjunction with a supporting operating system Execute Disable allows memory to be marked as executable or non executable This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities Dual Core Intel Xeon Processor 5000 Series Datasheet 9 intel Table 1 1 10 Introduction and can thus help improve the overall security of the system For further information on Execute Disable Bit functionality see http www intel com cd ids developer asmo na eng 149308 htm The Dual
148. the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state Refer to the IA 32 Intel Architecture Software Developer s Manual Volume IIl System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK the processor will return execution to the HALT state While in HALT Power Down state the processor will process front side bus snoops and interrupts Enhanced HALT Powerdown State Enhanced HALT state is a low power state entered when all logical processors have executed the HALT or MWAIT instructions When one of the logical processors executes the HALT instruction that logical processor is halted however the other processor continues normal operation The Enhanced HALT state is generally a lower power state than the Stop Grant state The processor will automatically transition to a lower core frequency and voltage operating point before entering the Enhanced HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID
149. the specified VID Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings Baseboard bandwidth is limited to 20 MHz Icc toc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc tpc indefinitely Refer to Figure 2 2 and Figure 2 3 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested This specification is per processor This is a steady state I r current specification which is applicable when both Vor and Vcc are high This parameter is based on design characterization and is not tested Please refer to the ler Analysis of System Bus Components Bensley Platform Whitepaper for platform implementation guidance Jo vrrour S Specified at 1 2 V 18 lcc Reset is specified while PWRGOOD and RESET are asserted 19 This specification is per processor This is a power up peak current specification which is applicable when V41 is powered up and Vcc is not This parameter is based on design charact
150. tion limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 2 Vcc Core voltage with respect to Vss 0 30 1 55 V Vr FSB termination voltage with respect to 0 30 1 55 V Vss TcASE Processor case temperature See See C Section 6 Section 6 TsTORAGE Storage temperature 40 85 G 3 4 5 Dual Core Intel Xeon Processor 5000 Series Datasheet Electrical Specifications 2 12 intel Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output and I O signals are outlined in Section 3 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not inc
151. to all processor frequencies 2 All outputs are open drain 3 V is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 4 Viy is defined as the voltage range at a receiving agent that will be interpreted as a logical high value D Mu and Voy may experience excursions above Ver However input signal drivers must comply with the signal quality specifications in Section 3 6 Refer to the processor HSPICE I O Buffer Models for I V characteristics 7 The V4 referred to in these specifications refers to instantaneous V 8 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load 9 Leakage to Vss with land held at Vr 10 Leakage to Vy with land held at 300 mV 11 LI NTO INTR and LINT1 NMI use GTLREF ADD as a reference voltage For these two signals Viu GTLREF ADD 0 10 V r and Muss GTLREF ADD 0 10 Vm VTTPWRGD DC Specifications Symbol Parameter Min Max Unit Vu Input Low Voltage 0 0 0 30 V Vin Input High Voltage 0 90 Ver V Vcc Overshoot Specification The Dual Core Intel Xeon Processor 5000 series can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos Max Vos wax is the Dual Core Intel Xeon Processor 5000 Series Datasheet 31 e n tel Elect
152. trol then the case temperature is permitted to exceed the thermal profile but the diode temperature must remain at or below Tcontrol Systems that implement fan speed control must be designed to take these conditions into account Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications Intel has developed two thermal profiles either of which can be implemented with the Dual Core Intel Xeon Processor 5000 series Both ensure adherence to Intel reliability requirements Thermal Profile A refer to Figure 6 1 Figure 6 2 Table 6 2 and Table 6 5 is representative of a volumetrically unconstrained thermal solution that is industry enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Thermal Profile B refer to Figure 6 1 and Dual Core Intel Xeon Processor 5000 Series Datasheet 69 Table 6 1 70 Thermal Specifications Figure 6 2 Table 6 3 and Table 6 6 is indicative of a constrained thermal environment that is 1U form factor Because of the reduced cooling capability represented by this thermal solution the probability of TCC activation and performance loss is increased Additionally utilization of a thermal solution that does not meet Thermal Profile B will violate the thermal specifications and may result in permanen
153. uring INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all FSB agents When the APIC functionality is disabled the LINTO INTR signal becomes INTR a maskable interrupt request signal and LINT1 NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LL ID 1 0 The LL 1D 1 0 signals are used to select the correct loadline slope for the processor The Dual Core Intel Xeon Processor 5000 series pull these signals to ground on the package for a logic 0 as these signals are not connected to the processor die A logic 1 is a no connect on the Dual Core Intel Xeon Processor 5000 series package LOCK 1 0 LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked series of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership
154. urrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signal can be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state Enhanced HALT Snoop or HALT Snoop State Stop Grant Snoop State The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state If the Enhanced HALT state is not enabled in the BIOS the default Snoop state entered will be the HALT Snoop state Refer to the sections below for details on HALT Snoop state Stop Grant Snoop state and Enhanced HALT Snoop state HALT Snoop State Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT Power Down state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the inter
155. ut RESERVED E24 FORCEPR AK6 ASync GTL Input RESERVED E5 GTLREF_ADD_CO H1 Power Other Input RESERVED E6 GTLREF ADD C1 H2 Power Other Input RESERVED E7 GTLREF DATA CO G10 Power Other Input RESERVED F23 GTLREF DATA C1 F2 Power Other Input RESERVED F29 HIT D4 Common Clk Input Output RESERVED F6 HITM E4 Common Clk Input Output RESERVED G5 IERR AB2 ASync GTL Output RESERVED G6 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Dual Core Intel Xeon Processor 5000 Series Datasheet Land Listing Table 4 1 Land Listing by Land Name Sheet 3 of 9 Land Name po d dd Direction Land Name yc xr d Direction GNNE N2 ASync GTL Input RESERVED J3 INIT P3 ASync GTL Input RESERVED N4 LINTO K1 ASync GTL Input RESERVED N5 LINT1 L1 ASync GTL Input RESERVED P5 LL IDO V2 Power Other Output RESERVED w2 LL ID1 AA2 Power Other Output I RESERVED Y1 LOCK C3 Common Clk Input Output RESET G23 Common Clk Input MCERR AB3 Common Clk Input Output RS0 B3 Common Clk Input MS IDO W1 Power Other Output RS1 F5 Common Clk Input MS ID1 V1 Power Other Output RS2 A3 Common Clk Input PROCHOT AL2 ASync GTL Output RSP H4 Common Clk Input PWRGOOD N1 Power Other Input SKTOCC AE8 Power Other Output REQO K4 Source Sync Input Output SMI P2 ASync GTL Input REQ1 J5 Source S
156. ve inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a thermal solution designed to meet Thermal Profile A it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable A thermal solution that is designed to Thermal Profile B may cause a noticeable performance loss due to increased TCC activation Thermal Solutions that exceed Thermal Profile B will exceed the maximum temperature specification and affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Dual Core Intel Xeon Processor 5000 Series Thermal Mechanical Design Guidelines for information on designing a thermal solution The duty cycle for the TCC when activated by the TM1 is factory configured and cannot be modified The TM1 does not require any additional hardware software drivers or interrupt handling routines On Demand Mode The processor provides an auxiliary mechanism that allows system soft
157. voltages Section 2 1 contains the electrical specifications of the FSB while implementation details are fully described in the appropriate platform design guidelines refer to Section 1 3 Dual Core Intel Xeon Processor 5000 Series Datasheet intel 1 1 Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Commonly used terms are explained here for clarification Dual Core Intel Xeon Processor 5000 Series Processor in the FC LGA6 package with two physical processor cores Dual Core Intel Xeon processor 5000 series refers to the Full Power Dual Core Intel Xeon Processor 5000 series with 1066 MHz Front Side Bus For this document processor is used as the generic term for the Dual Core Intel Xeon Processor 5000 series Dual Core I ntel Xeon Processor 5063 MV This is a lower power version of the Dual Core Intel Xeon Processor 5000 series Dual Core Intel Xeon Proc
158. ware to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Dual Core Intel Xeon Processor 5000 series must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the IA32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same IA32 CLOCK MODULATI ON MSR In On Demand mode the duty cycle can be programmed from 12 596 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor however if Dual Core Intel Xeon Processor 5000 Series Datasheet 77 e n tel Thermal Specifications 6 2 4 6 2 5 78 the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its factory configured trip point If Thermal Monitor is enabled note that The
159. wer Other VSS L28 Power Other VSS V29 Power Other VSS L29 Power Other VSS V3 Power Other VSS L3 Power Other VSS V30 Power Other VSS L30 Power Other VSS V6 Power Other VSS L6 Power Other VSS V7 Power Other VSS L7 Power Other VSS WA Power Other VSS M1 Power Other VSS WI Power Other VSS M7 Power Other VSS Y2 Power Other VSS N3 Power Other VSS Y5 Power Other VSS N6 Power Other VSS Y7 Power Other VSS N7 Power Other VSS_DIE_SENSE AN4 Power Other Output VSS P23 Power Other VSS_DIE_SENSE2 AL7 Power Other Output VSS P24 Power Other VSSA B23 Power Other Input 50 Dual Core Intel Xeon Processor 5000 Series Datasheet intel Dual Core Intel Xeon Processor 5000 Series Datasheet Land Listing Table 4 1 Land Listing by Land Name Sheet 9 of 9 Land Name po d da Direction Land Name yo x cu Direction VSS P25 Power Other VIT A25 Power Other VSS P26 Power Other VIT A26 Power Other VSS P27 Power Other VIT B25 Power Other VIT B26 Power Other VIT D26 Power Other VIT B27 Power Other VIT D27 Power Other VIT B28 Power Other VIT D28 Power Other VIT B29 Power Other VIT D29 Power Other VIT B30 Power Other VIT D30 Power Other VIT C25 Power Other VIT E30 Power Other VIT C26 Power Other VIT F30 Power Other VIT C27 Power Other VIT OUT AAT Power Other Output VIT C28 Power Other VTT OUT jl Power Other Output VIT C29 Power Other
160. ync Input Output STPCLK M3 ASync GTL Input REQ2 M6 Source Sync Input Output TCK AE1 TAP Input REQ3 K6 Source Sync Input Output TDI AD1 TAP Input REQ4 J6 Source Sync Input Output TDO AF1 TAP Output RESERVED A20 TEST_BUS AH2 Power Other RESERVED AC4 TESTHI00 F26 Power Other Input RESERVED AE4 TESTHI01 w3 Power Other Input RESERVED AE6 TESTHIO2 F25 Power Other Input RESERVED AK3 TESTHIO3 G25 Power Other Input RESERVED AJ3 TESTHIOA G27 Power Other Input RESERVED AM5 TESTHIO5 G26 Power Other Input RESERVED AN5 TESTHI06 G24 Power Other Input RESERVED AN6 TESTHIO7 F24 Power Other Input RESERVED B13 TESTHIO8 G3 Power Other Input RESERVED C9 TESTHIO9 G4 Power Other Input RESERVED D1 TESTHI 10 P1 Power Other Input RESERVED D14 TESTHI11 L2 Power Other Input RESERVED D16 THERMDA AL1 Power Other Output RESERVED D23 THERMDA2 AJ7 Power Other Output RESERVED El THERMDC AK1 Power Other Output THERMDC2 AH7 Power Other Output VCC AF8 Power Other THERMTRI P M2 ASync GTL Output VCC AF9 Power Other TMS AC1 TAP Input VCC AG11 Power Other TRDY E3 Common Clk Input VCC AG12 Power Other TRST AG1 TAP Input VCC AG14 Power Other VCC AA8 Power Other VCC AG15 Power Other VCC AB8 Power Other VCC AG18 Power Other VCC AC23 Power Other VCC AG19 Power Other VCC AC24 Power Other VCC AG21 Power Other VCC AC25 Power Other VCC AG22 Power Other VCC AC26 Power Other VCC AG25 Power Other VCC AC27 Power Other VCC A

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