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Silicon Laboratories C8051F344 Two

1. As muchas is possible do not route clock input and output signals underneath the BGA package The clock output signals should go directly outwards from the BGA footprint Figure 97 Output Clock Routing Rev 0 5 171 SILICON LABS Si53xx RM Avoid placing the OCS P and OSC N signals on the same layer as the clock outputs Add grounded guard traces surrounding the OSC P and OSC N signals N Routing Figure 98 OSC P OSC Rev 0 5 172 SILICON LABS Si53xx RM APP
2. Setting FRQSEL 3 0 fin MHz Mult Factor four MHz 0 LLLL 0 008 3125 25 1 LLLM 6480 51 84 2 LLLH 53125 8 53 125 3 LLML 15625 2 62 5 4 LLMM 53125 4 106 25 5 LLMH 15625 125 6 LLHL 78125 4 156 25 7 LLHM 159375 8 159 375 8 LLHH 53125 2 212 5 9 LMLL 53125 425 10 LMLM 19 440 625 486 25 11 LMLH 10625 3888 53 125 12 LMML 3125 972 62 5 13 LMMM 10625 1944 106 25 14 LMMH 3125 486 125 15 LMHL 15625 1944 156 25 16 LMHM 31875 3888 159 375 17 LMHH 15625 1944 x 66 64 161 13 18 LHLL 31875 3888 x 66 64 164 36 19 LHLM 15625 1944 x 66 172 64 64 x 255 238 20 LHLH 31875 3888 x 66 176 1 64 x 255 238 21 LHML 10625 972 212 5 22 LHMM 10625 486 425 23 LHMH 15625 486 x 66 64 644 53 24 LHHL 31875 972 x 66 64 657 42 25 LHHM 15625 486 x 66 690 57 64 x 255 238 26 LHHH 31875 972 x 66 704 38 64 x 255 238 27 MLLL 27 000 1 27 28 MLLM 250 91 74 17582 29 MLLH 11 4 74 25 lt Rev 0 5 61 SILICON LABS Si53xx RM Table 18 SONET to Datacom Clock Multiplication Settings Continued Setting FRQSEL 3 0 fiN MHz Mult Factor four MHz 30 MLML 62 500 2 125 31 MLMM 4 250 32 MLMH 74 176 91 250 27 33 MLHL 1 74 17582 34 MLHM 91 x 11 250 x 4 74 25
3. 1 All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated 2 See Sections 6 7 1 and 8 2 1 for restrictions on output formats for TQFP devices at 3 3 V SIGNAL Single Ended Differential VOS Voc Vise Vose 5 SIGNAL Peak to Peak Voltage SIGNAL SIGNAL Differential Peak to Peak Voltage Voom SIGNAL Vip SIGNAL SIGNAL SIGNAL Figure 16 Differential Voltage Characteristics 80 CKIN CKOUT 20 t ta Figure 17 Rise Fall Time Characteristics 32 Rev 0 5 e SILICON LABS Si53xx RM Table 4 DC Characteristics Parameter Test Condition Supply Current Independent of Supply Voltage LVPECL Format 622 08 MHz Out All CKOUT s Enabled LVPECL Format 622 08 MHz Out Only 1 CKOUT Enabled CMOS Format 19 44 MHz Out All CKOUTs Enabled CMOS Format 19 44 MHz Out Only 1 CKOUT Enabled Disable Mode CKIN_n Input Pins 1 8V 10 2 5 V 1096 3 3 V 10 Single ended foKIN lt 212 5 MHz See Figure 16 ckIN 212 5 MHz See Figure 16 foKIN lt 212 5 MHz See Figure 16 foKIN gt 212 5 MHz See Figure 16
4. XO t i N32 fs DSPLL N1 HS NC1 gt CKOUT CKIN pm N31 gt 4 Loss of Signal lt or VDD Signal Detect ontro Loss of Lock lt lt _ GND PC SPI Port lt Xtal Clock Select Device Interrupt lt Rate Select Figure 2 Si5319 Any Frequency Jitter Attenuating Clock Multiplier Block Diagram 18 Rev 0 5 SILICON LABS Si53xx RM 3 3 515322 515322 is low jitter precision clock multiplier for applications requiring clock multiplication without jitter attenuation The Si5322 accepts dual clock inputs ranging from 19 44 to 707 MHz and generates two frequency multiplied clock outputs ranging from 19 44 to 1050 MHz The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET Ethernet Fibre Channel and broadcast video HD SDI 501 rates The DSPLL loop bandwidth is digitally selectable from 150 kHz to 1 3 MHz Operating from a single 1 8 2 5 3 3 V supply the Si5322 is ideal for providing low jitter clock multiplication in high performance timing applications See 6 Pin Control Parts 515316 515322 515323 515365 515366 on page 50 for a complete description CKIN 1 1 2 2 C2B BWSEL 1 0 FROTBL FROSEL 3 0 RST Control Bandwidth Control Frequency Contr
5. Refer to Section 6 7 1 and 8 2 1 for restrictions on output formats for TQFP devices at 3 3 V 2 This is the amount of leakage that the 3L inputs can tolerate from an external driver See Figure 55 on page 115 3 No under or overshoot is allowed SILICON LABS 5153 Table 4 DC Characteristics Continued Symbol Test Condition Typ JN 9 o 0 S 971402 0 0 W CKOUTn See 8 2 Output Clock Drivers for Configuring Output Drivers for LVPECL CML LVDS CMOS Common Mode Vocm LVPECL 1000 e V load line to line 1 42 1 25 Differential Output Vop LVPECL 100 Q 1 1 1 9 Vpp i load line to line Vse LVPECL 100 Q 0 5 0 93 Vpp load line to line CKOyp CML 100 load 500 mVpp line to line CML 100 load V line to line CKOyp LVDS 100 Q load line to line Low swing LVDS 100 load line to line LVDS 100 load line to line CKOrp CML LVPECL LVDS Disabled Sleep CKO CMOS VOLLH CKO Vpp 1 71V 0 8 x VOHLH CMOS Vpp Refer to Section 6 7 1 and 8 2 1 for restrictions on output formats for TQFP devices at 3 3 V 2 This is the amount of leakage th
6. 85 7 5 3 Free Run Reference Frequency 86 7 5 4 Free Run Reference Frequency 86 or ER 87 7 6 1 Narrowband Digital Hold 515316 515324 515326 515368 515369 515374 87 7 6 2 History Settings for Low Bandwidth Devices 515324 515327 515369 515374 89 7 6 3 Recovery from Digital Hold 515319 515324 515326 515327 515368 515369 515374 89 7 6 4 VCO Freeze 515319 515325 515367 375 89 7 6 5 Digital Hold versus VCO Freeze 89 7 7 Output Phase Adjust 515326 515368 90 7 7 1 Coarse Skew Control 515326 6 5368 90 7 7 2 Fine Skew Control 515326 5368 90 7 7 3 Independent Skew 515324 515326 515368 515369 515374 91 7 7 4 Output to output Skew 515324 515326 515327 515368 515369 515374 91 7 7 5 Input to Output Skew All 91 7 8 Frame Synchronization Realignment 515368 and CK CONFIG REG 1 91 7 8 1 FSYNC Realignment 5368 1 93 7 8 2 FSYNC
7. AS At ipee ChOUTIPLA CKOUTIN CKOUT2P CEOUTZN A gt gt ChOUTIP_B ChOUTIN_G CVOVTZP y LOLE PSTL_E Oom R32 it im CK IP C tt kk as Crime gt CKWIN D CKWZP D CKMZN D AD lt lt RET L c D 0 CHOUTIP_C CKOUT2P CKOUT2P D CKOUTZK D gt gt LLE CFOUTIP C C VOUTIN SroUT2P CKOUTZM gt gt gt gt LOLE IRO D These four resistors force the common RESET connection away from the BGA footprint Figure 96 Ground Plane and Reset CKOUTIP D CkOUTIN D CHOUTZP D CHOUTZN D 170 SILICON LABS Si53xx RM The following is a set of recommendations and guidelines for printed circuit board layout with the Si5374 and Si5374 devices Because the four DSPLLs are in close physical and electrical proximity to one another PCB layout is critical to achieving the highest levels of jitter performance The following images were taken from the Si537x EVB evaluation board layout For more details about this board please refer to the Si537x EVB Evaluation Board User s Guide
8. Write Command Byte Address gt Dl 79 5 Slave Address 0 A 5 Slave Address Data A Data Read Command address auto incremented after each data read or write this can be two separate transactions From master to slave A Acknowledge SDA LOW 5 START condition STOP condition From slave to master Figure 34 IZC Command Format In Figure 35 the value 68 is seven bits The sequence of the example is Write register 00 with the value OxAA then read register 00 Note that 0 Write W and 1 Read R Read Command Figure 35 2 Example 102 Rev 0 5 e SILICON LABS Si53xx RM 7 14 Serial Microprocessor Interface SPI When configured in SPI control mode CMODE H the control interface to the device is a 4 wire interface modeled after commonly available microcontroller and serial peripheral devices The interface consists of a clock input SCLK slave select input SSb serial data input SDI and serial data output SDO In addition an output interrupt INT is provided with selectable active polarity determined by INT_ POL bit Data is transferred a byte at a time with each register access consisting of a pair of byte transfers Figure 36 and Figure 37 illustrate read and write set address operations on the SPI bus and AC SPEC gives the timing requirements for th
9. Pin 5374 75 Pull D4 RSTL_A U D6 RSTL_B U F6 RSTL_C U F4 RSTL_D U D1 CS_CA_A U D A6 CS_CA_B U D 9 U D J4 U D G5 SCL D lt Rev 0 5 153 SILICON LABS Si53xx RM APPENDIX F TYPICAL PERFORMANCE CROSSTALK OUTPUT FORMAT JITTER BYPASS This appendix is divided into the following four sections m Bypass Mode Performance Power Supply Noise Rejection m Crosstalk m Output Format Jitter Bypass 622 08 MHz In 622 08 MHz Out 622 08 MHz in 622 08 MHz out I o m 5 EL E e Pil 2 MIN MA 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency Hz Dark blue normal locked Pink bypass Light blue digital hold Green Marconi RF generator Normal In Digital Hold In Bypass Marconi RF Locked Source Jitter Bandwidth Jitter RMS Jitter RMS Jitter RMS Jitter RMS Broadband 1000 Hz to 10 MHz 296 fs 294 fs 2 426 fs 249 fs OC 48 12 kHz to 20 MHz 303 fs 304 fs 2 281 fs 236 fs OC 192 20 kHz to 80 MHz 321 fs 319 fs 3 079fs 352 fs OC 192 4 MHz to 80 MHz 169 fs 165 fs 2 621 fs 305 fs OC 192 50 kHz to 80 MHz 304 fs 303 fs 3 078 fs 340 fs Broadband 800 Hz to 80 MHz 329 fs 325 fs 3 076 fs 370 fs 154 Rev 0 5 lt SILICON LABS Si53xx RM Power Supply
10. 68 6 3 3 Hitless Switching with Phase Build Out 515323 5366 69 6 4 Digital Hold VCO Freeze os ure scr ee oie o erect te ar Re 70 6 4 1 Narrowband Digital Hold 515316 515323 5 5366 70 6 4 2 Recovery from Digital Hold Si5316 515323 5 5366 70 6 4 3 Wideband VCO Freeze 515322 365 70 6 5 Frame Synchronization 515366 70 6 6 Output Phase Adjust 515323 515366 71 6 6 1 FSYNC Realignment 5366 71 6 6 2 Including FSYNC Inputs in Clock Selection 515366 71 6 6 3 FS OUT Polarity and Pulse Width Control 515366 71 6 6 4 Using OUT as a Fifth Output Clock 515366 71 6 6 5 Disabling FS OUT Si5366 72 6 7 OUIDUESGIBOKJDEF NOS sus o DeL ib si de Ad atc a 72 6 7 1 LVPECL and CMOS TQFP Output Signal Format Restrictions at 3 3 V 515365 515366 72 6 8 PLL Bypass Mode Wig horas tese d 73 5 9 ATA Fee hw EE ER ER a 73 6 9 1 Loss of Signal Alarms 515316 515322 515323
11. 85 Figure 30 Parameters in History Value of M 87 Figure 31 Digital Hold vs VCO Freeze 89 Figure 32 Frame Syne 92 Figure 33 FOS Compare A Le 98 Figure 34 Command Format 102 Figure 35 IPC Example ee ove ME ees tedio LM 102 Figure 36 SPI Write Set Address Command 104 Figure 37 SPI Read Command 104 Figure 38 Differential LVPECL 105 Figure 39 Single Ended LVPECL 105 Figure 40 CML LVDS Termination 1 8 2 5 3 3 106 Figure 41 CMOS Termination 1 8 2 5 3 3 106 Figure 42 Typical Output Circuit Differential 107 Rev 0 5 7 SILICON LABS Si53xx RM Figure 43 Differential Output Example Requiring 108 Figure 44 Typical CMOS Output Circuit Tie CKOUTn and CKOUTn Together 108 Figure 45 CKOUT Structure simo me y 109 Fig re 46 SIOUE 2 CMS aratri we We ia
12. 1 80E 02 1 00E 01 1 00 02 1 00E 03 1 00E 04 1 00 05 1 00 06 1 00E 07 1 00E 08 Offset Frequency Hz Blue RF Generator Figure 89 RF Generator Si5326 Si5324 50 Hz Jitter e Rev 0 5 165 SILICON LABS Si53xx RM 622 08 MHz in 622 08 MHz out 0 00E 00 fC 2 00E 01 4 00E 01 6 00E 01 8 00E 01 1 00E 02 Phase Noise dBc Hz 1 20E 02 1 40E 02 1 60E 02 1 80E 02 1 00E 01 1 00E 02 1 00 03 1 00 04 1 00 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Blue RF Generator Red Si5324 Figure 90 RF Generator Si5326 Si5324 100 Hz Jitter 622 08 MHz in 622 08 MHz out 0 00E 00 2 00E 01 4 00E 01 6 00E 01 8 00E 01 Phase Noise dBc Hz 1 00E 02 1 20E 02 1 40E 02 1 60E 02 1 80E 02 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Blue RF Generator Red Si5324 Figure 91 RF Generator Si5326 Si5324 500 Hz Jitter 166 Rev 0 5 lt SILICON LABS Si53xx RM 0 00E 00 622 08 MHz in 622 08 MHz out 2 00E 01 4 00E 01 6 00E 01 8 00E 01 1 00 02 a 1 20 02 x Phase Noise dBc Hz 1 1 40E 02 1 60E 02 1 80E 02 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 Offset Frequency
13. 170 Figure 97 Output Clock Routing 171 Figure 98 OSC B OSC N Routing 172 Figure 99 515374 515375 DSPLL A 174 Figute 100 5 5974 515375 DSPLE B 3 ui ete o A EUR e De apu o o a ee AS 175 Figure 101 515374 515375 DOP LE C 176 Figure 102 515374 515375 DSPLL D 177 Rev 0 5 9 SILICON LABS Si53xx RM LisT OF TABLES Table 1 Product Selection Guides 522259 R3 14 Table 2 Product Selection Guide 515322 25 65 67 15 Table 3 Recommended Operating Conditions 32 Table 4 DC Characteristics dw ee RIED e D DR T DE 33 Table 5 DC Characteristics Microprocessor Devices 515324 Si5325 5SIB957 9D JOB Xe a sepe a cuadro Sus 37 Table 6 SPI Specifications 515324 515325 515367 515368 37 Table 7 DC Characteristics Narrowband Devices Si5316 Si5319 915929 515266 9 5968 uq Susana Sh coute ce IR QUY Da sa q 38 Table 8 AC Characteristics All 40 Table 9 Jitter Generation 515316 515324 515366 515368 44 Table 10 Jitter Genera
14. 2 C3B ALRMOUT Si5368 CK CONFIG 1 100 7 11 7 LOS Algorithm for Reference Clock Input 515319 515324 515326 515327 515368 515369 515374 5 5375 100 7 11 8 LOL 515319 515324 515326 515327 515368 515369 515374 515375 100 Z 11 9 Device Intetrupts enm ERE CR a Ro eee ee 101 7 12 DEVICA Reset a rer du qo 101 7 13 Serial Microprocessor Interface 102 7 14 Serial Microprocessor Interface SPI 103 7 14 1 Default Device 104 Z I5chedlster Descriptions beo pex deh Rede m teu 104 7 16 DSPLLsim Configuration Software 104 8 High Speed VO u coe ered vee x bt mamme a ede eco del nmm 2 e ene n n 105 8 1 Input Clock Buffers d uut s atate gerne Ao Qe QUU Su PRR aq AW 105 9 2 Quiplit DIIVBES o nep d d ede Resim Dh eas TN 107 e Rev 0 5 5 SILICON LABS Si53xx RM 8 2 1 LVPECL TQFP Output Signal Format Restrictions at 3 3 V 515367 515368 Si5369 107 8 2 2 Typical Output 1 107 8 2 3 Typical Clock Output Sco
15. Phase Noise dBc Hz 1 40E 02 1 20E 02 x 1 60E 02 1 80E 02 1 00 07 1 00E 08 1 00E 02 1 00 03 1 00 04 693 493 2 1 00 05 Offset Frequency Hz Blue 173 371 MHz Figure 77 86 685 MHz In 173 371 MHz and 693 493 MHz Out Table 66 Jitter Values for Figure 77 Jitter Bandwidth 173 371 MHz 693 493 MHz Jitter RMS Jitter RMS Broadband 1 kHz to 10 MHz 262 fs 243 fs OC 48 12 kHz to 20 MHz 297 fs 265 fs OC 192 20 kHz to 80 MHz 309 fs 264 fs OC 192 4 MHz to 80 MHz 196 fs 124 fs OC 192 50 kHz to 80 MHz 301 fs 255 fs Broadband 800 Hz to 80 MHz 313 fs 269 fs 138 Rev 0 5 e SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 173 370000 MHz 5 1955 dB Xf Start 100 Stop 100 0009 MHz 10 00 Center 50 0005 MHZ Span 100 0008 MHz Noise 20 00 Analysis Range x Band Marker Analysis Range Y Band Marker Intg Noise 47 7569 dBc 40 MHz 30 00 RMS Noise 5 78991 mrad 331 737 mdeg RMS Jitter 5 31518 psec 40 00 Residual 4 20257 kHz 50 00 60 00 70 00 80 00 90 00 11 140 0 160 0 100 1k 10k 100 1M 10M Figure 78 86 685 MHz In 173 371 MHz Out s Rev 0 5 139 SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 693 479996 MHz 0 5181 dBi Start 100 Hz Stop 100 0009 MHz 10 00 Cente
16. 4 VDD LOL ree Pave do sedo 94508589926 wo O53 tr lt T lt o a o N Figure 12 515368 Clock Multiplier and Jitter Attenuator Block Diagram 28 Rev 0 5 lt SILICON LABS Si53xx RM 3 13 Si5369 The Si5369 is a jitter attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance The Si5369 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The device provides virtually any frequency translation combination across this operating range The Si5369 input clock frequency and clock multiplication ratio are programmable through an 12 or SPI interface The DSPLL loop bandwidth is digitally programmable providing loop bandwidth values as low as 4 Hz Operating from a single 1 8 2 5 or 3 3 V supply the Si5369 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 on page 76 for a complete description Xtal or Refclock RATE
17. 76 Rev 0 5 SILICON LABS Si53xx RM Because there is only one DCO and all of the outputs must be frequencies that are integer divisions of the DCO frequency there are restrictions on the ratio of one output frequency to another output frequency That is there is considerable freedom in the ratio between the input frequency and the first output frequency but once the first output frequency is chosen there are restrictions on subsequent output frequencies These restrictions are made tighter by the fact that the N1_HS divider is shared among all of the outputs DSPLLsim should be used to determine if two different simultaneous outputs are compatible with one another The same issue exists for inputs of different frequencies both inputs after having been divided by their respective N3 dividers must result in the same f3 frequency because the phase frequency detector can operate at only one frequency at one time 7 1 2 1 Loop Bandwidth Si5325 Si5367 The loop bandwidth BW is digitally programmable using the BWSEL_REG 3 0 register bits The device operating frequency should be determined prior to loop bandwidth configuration because the loop bandwidth is a function of the phase detector input frequency and the PLL feedback divider See DSPLLsim for BWSEL_REG settings and associated bandwidth 7 1 2 2 Lock Detect Si5325 Si5367 A PLL loss of lock indicator is not available in these devices 7 1 2 3 Input to Output Skew Si53
18. AUTOSEL Clock Selection Mode Manual See Previous Section M Automatic Non revertive H Automatic Revertive Table 25 Clock Active Indicators AUTOSEL M or H Si5322 and Si5323 CS_CA Active Clock CKIN1 CKIN2 Table 26 Clock Active Indicators AUTOSEL M or H Si5365 and Si5367 CA1 CA2 CS0 CS1 Active Clock 1 0 0 0 CKIN1 0 1 0 0 CKIN2 0 0 1 0 CKIN3 0 0 0 1 CKIN4 The prioritization of clock inputs for automatic switching is shown in Table 27 and Table 28 This priority is hardwired in the devices Table 27 Input Clock Priority for Auto Switching Si5322 Si5323 Priority Input Clocks 1 CKIN1 2 CKIN2 3 Digital Hold 68 Rev 0 5 SILICON LABS Si53xx RM Table 28 Input Clock Priority for Auto Switching Si5365 Si5366 Priority Input Clock Configuration 515365 515366 4 Input Clocks FSYNC Switching CK_CONF 0 CK_CONF 1 1 CKIN1 CKIN1 CKIN3 2 CKIN2 CKIN2 CKIN4 3 CKIN3 N A 4 CKIN4 N A 5 Digital Hold Digital Hold At power on or reset the valid CKINn with the highest priority 1 being the highest priority is automatically selected If no valid CKINn is available the device suppresses the output clocks and waits for a valid CKINn signal If the currently selected CKINn goes into an alarm state the next v
19. 1 gt FRQTBL Control FRQSEL 3 0 gt INC 3 Frequency l DEC gt Contro VDD RST gt GND Figure 4 Si5323 Jitter Attenuating Clock Multiplier Block Diagram 20 Rev 0 5 e SILICON LABS Si53xx RM 3 5 515324 The 515324 is jitter attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance The Si5324 accepts dual clock inputs ranging from 2kHz to 710MHz and generates two independent synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The device provides virtually any frequency translation combination across this operating range The Si5324 input clock frequency and clock multiplication ratios are programmable through an 2 or SPI interface The DSPLL loop bandwidth is digitally programmable providing jitter performance optimization at the application level The Si5324 features loop bandwidth values as low as 4 Hz Operating from a single 1 8 2 5 or 3 3 V supply the Si5324 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 on page 76 for a complete description Xtal or Refclock RATE 1 0 XB DSPLL BYPASS 0 2 CKIN 1 gt N31 CKIN 1 gt 2
20. 5 2 1 Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock Generated jitter arises from sources within the VCO and other PLL components Jitter generation is a function of the PLL bandwidth setting Higher loop bandwidth settings may result in lower jitter generation but may result in less attenuation of jitter that might be present on the input clock signal 5 2 2 Jitter Transfer Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency The jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs The DSPLL technology used in the Any Frequency Precision Clock devices provides tightly controlled jitter transfer curves because the PLL gain parameters are determined largely by digital circuits which do not vary over supply voltage process and temperature In a system application a well controlled transfer curve minimizes the output clock jitter variation from board to board and provides more consistent system level jitter performance The jitter transfer characteristic is a function of the loop bandwidth setting Lower bandwidth settings result in more jitter attenuation of the incoming clock but may result in higher jitter generation Section 1 Any Frequency Precision Clock Product Family Overview also includes specifications related to jitter bandwidth a
21. 5153 Table 8 5 Devices Continued Parameter Symbol Test Condition S 5 10 8 S Min Typ Max Units 0 19 19 10 10 0 0 W 0 Device Skew Output Clock tsxew of CKOUT nto T of ele 100 ps Skew CKOUT m see Section 7 7 4 CKOUT n and CKOUT m at same frequency and signal format PHASE OFFSET 0 SQICAL 1 CKOUT ALWAYS O N21 Coarse Skew tpHRES Using CLAT 7 0 e 1 Fyco ps Adjust Resolution register using INC DEC pins e 1 Fyco ps Coarse Skew Using CLAT 7 0 e 00 Adjust Range register using INC DEC pins 00 00 5 Fine Skew Adjust tepysres using FLATT 14 0 e 9 ps Resolution register Fine Skew Adjust using FLAT 14 0 e e 110 110 ps Range register Phase Offset using PHASEOFF e NI HS Resolution SETn 7 0 registers fyco Phase Offset torsTRNG using PHASEOFF 128 127 x Range SETn 7 0 registers tor tor STRES STRES PLL Performance Lock Time tlockHw T RST with valid 1 2 sec CKIN to LOL BW 100 Hz Pin Reset or tREADY ee ele 10 ms Register Reset to Microprocessor Access Ready Reset to first on Vali
22. 515375 Layout Recommendations 169 Appendix J Si5374 and 515375 Crosstalk 173 Document Change 178 Contact Information Sa ane Qna aw VO CO Y eas 180 6 Rev 0 5 SILICON LABS Si53xx RM LIST OF FIGURES Figure 1 515316 Any Frequency Jitter Attenuator Block Diagram 17 Figure 2 515319 Any Frequency Jitter Attenuating Clock Multiplier Block Diagram 18 Figure 515322 Low Jitter Clock Multiplier Block Diagram 19 Figure 4 Si5323 Jitter Attenuating Clock Multiplier Block Diagram 20 Figure 5 515324 Clock Multiplier and Jitter Attenuator Block Diagram 21 Figure 6 515325 Low Jitter Clock Multiplier Block Diagram 22 Figure 7 515326 Clock Multiplier and Jitter Attenuator Block Diagram 23 Figure 8 515327 Clock Multiplier and Jitter Attenuator Block Diagram 24 Figure 9 515365 Low Jitter Clock Multiplier Block Diagram 25 Figure 10 Si5366 Jitter Attenuating Clock Multiplier Block Diagram 26 Figure 11 515367 Clock Multiplier Block Diagram 27 Figure 12 515368 Clock Multiplier and Jitter Attenuator Block Diagram 28 Figure 13 Si5369 Cloc
23. SILICON LABS ANY FREQUENCY PRECISION CLOCKS 515316 515319 515322 515323 515324 515325 515326 515327 515365 515366 515367 515368 515369 515374 515375 FAMILY REFERENCE MANUAL Rev 0 5 6 11 Copyright 2011 by Silicon Laboratories Si53xx RM Si53xx RM 2 0 5 SILICON LABS Si53xx RM TABLE OF CONTENTS Section Page 1 Any Frequency Precision Clock Product Family Overview 12 2 Narrowband vs Wideband Overview 16 3 i Bs Clock Family Members 17 ory Fob dit e dE ey re bob als DE e ean To Cute S ha ets 17 U te ERE h D Say tame Aa peer ae eon 18 Se u uu 19 dud OIDU S OE uod at gcc shh Ph a apu kuu 20 od bot hie Sel fate late te p ps hieu a a tt a 21 30 5515 JOB ab o der Nata tal Cabo fO c 22 BS DID IE au aru aac eir ires Gr OO nd 23 s 2 rrr 24 di AID dB cis Bic ch aca The vau a cap SN eC at ie TI Ane Md pie e pa P aod 25 5 Fig 10 aro 9 D 26 Z Z Bi dite crs ts Sa
24. Selected Clock CK PRIORn 1 0 CK CONFIG REG 0 CK CONFIG REG 1 00 CKIN1 CKIN1 CKIN3 01 CKIN2 CKIN2 CKIN4 10 CKIN3 Not Used 11 CKIN4 Not Used If CK_CONFIG_REG 1 and the desired clock priority is CKIN1 CKIN3 and then CKIN2 CKIN4 the user should set CK_PRIOR1 1 0 00 and CK PRIORZ 1 0 01 CK_PRIOR3 1 0 and CK_PRIOR4 1 0 are ignored in this case The following discussion describes the clock selection algorithm for the case of four possible input clocks CK CONFIG REG 0 in the default priority arrangement priority order CKIN1 CKIN2 CKIN3 Automatic switching mode selects CKIN1 at powerup reset or when in revertive mode with no alarms present on CKIN1 If an alarm condition occurs on CKIN1 and there are no active alarms on CKIN2 the device switches to CKIN2 If both CKIN1 and CKIN2 are alarmed and there is no alarm on CKINS the device switches to CKING If CKIN1 and CKIN3 are alarmed and there is no alarm on CKIN4 the device switches to CKIN4 If alarms exist on CKIN1 CKIN2 CKIN3 and CKIN4 the device enters digital hold mode If automatic mode is selected and the frequency offset alarms FOS1_INT FOS2_INT FOS3_INT FOS4_INT are disabled automatic switching is not initiated in response to FOS alarms The loss of signal alarms LOS1_INT LOS2_INT LOS3_INT LOS4_INT are always used in making automatic clock selection choices In non revertive mode once CKIN2 is selecte
25. With crosstalk in digital hold Rev 0 5 SILICON LABS 157 Si53xx RM Clock Input Crosstalk Detail View Phase Noise dBc Hz 130 155 521 MHz in 622 084 MHz out 100 1000 10000 Offset Frequency Hz 100000 Dark blue No crosstalk Light blue With crosstalk low bandwidth Yellow With crosstalk high bandwidth Red With crosstalk in digital hold 158 Rev 0 5 SILICON LABS Si53xx RM Clock Input Crosstalk Wideband Comparison 20 40 60 80 100 120 Phase Noise 4 140 160 180 155 521 MHz in 622 084 MHz out 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency Hz Dark blue Bandwidth 6 72 kHz no Xtalk Light blue Bandwidth 6 72 kHz with Xtalk Jitter Band Jitter w Xtlk Jitter no Xtlk OC 48 12 kHz to 20 MHz 303 fs RMS 422 fs RMS OC 192 20 kHz to 80 MHz 316 fs RMS 366 fs RMS Broadband 800 Hz to 80 MHz 340 fs RMS 1 010 fs RMS e Rev 0 5 SILICON LABS 159 Si53xx RM Clock Input Crosstalk Output of Rohde and Schwartz RF Rohde and Schwarz 155 521 MHz lt o m m o z o G 100 1000 Offset Frequency Hz 160 Rev 0 5 SILICON LABS Si53xx RM Jitter vs Output Format 19 44 MHz In 622 08 MHz Out 19 44 MHz in 622
26. simplified block diagram of the device and Table 35 and Table 36 for frequency and divider limits The PLL dividers and their associated ranges are listed in the diagram Each PLL divider setting is programmed by writing to device registers There are additional restrictions on the range of the input frequency the DSPLL phase detector clock rate and the DSPLL output clock fogc The selected input clock passes through the N3 input divider and is provided to the DSPLL In addition the external crystal or reference clock provides a reference frequency to the DSPLL The DSPLL output frequency fosc is divided down by each output divider to generate the clock output frequencies The input to output clock multiplication ratio is defined as follows four fin X N2 N1 X N3 where N1 output divider N2 feedback divider N3 input divider lt Rev 0 5 77 SILICON LABS Si53xx RM Xtal or Refclock 515319 515324 515326 515327 515368 515369 Refclock only for the 515374 515375 BYPASS 2 2 _ CKOUT_1 5 f Heo CKOUT 1 EN D gt N32 fs Digital 4 ee ce le gt Prase fosc 41 2
27. 0 5 93 SILICON LABS Si53xx RM For cases where phase skew is required see Section 7 7 Output Phase Adjust Si5326 Si5368 for more details on controlling the sync input to sync output phase skew via the FSYNC SKEW 16 0 bits See Section 8 2 Output Clock Drivers for information on the FS_OUT signal format pulse width and active logic level control 7 8 2 FSYNC Skew Control Si5368 When CKIN3 and CKIN4 are configured as frame sync inputs CK_CONFIG_REG 1 phase skew of the sync input active edge to FS OUT active edge is controllable via the FSYNC SKEW 16 0 register bits Skew control has a resolution of 1 fckour2 and a range of 181 0717 The entered skew value must be less than the period of CKIN3 CKIN4 and FS OUT The skew should be changed more than once per FS OUT period If a FSYNC realignment is being made the skew should not be changed until the realignment is complete The skew value and the FS OUT pulse width should not be changed within the same 5 OUT period Before writing the three bytes needed to specify a new SKEW 16 0 value the user should set the register bit FSKEW VALID 0 This causes the alignment state machine to keep using the previous SKEW 16 0 value ignoring the new register values as they are being written Once the new FSYNC SKEW 16 0 value has been completely written the user should set FSKEW VALID 1 at which time the alignment state mac
28. 1 166 63 166 63 54 4 238 255 622 08 622 08 55 MHML 4 666 51 666 51 54 Rev 0 5 e SILICON LABS Si53xx RM Table 16 SONET Clock Multiplication Settings FRQTBL L Continued No FRQSEL fin MHz Mult Factor Nominal All Devices 515366 Only four F kours MHz FS OUT MHz CK CONF 0 CK CONF 1 56 HLLL 167 33 237 255 155 52 155 52 NA 57 MMHM 1 167 33 167 33 NA 58 HLLM 4 x 237 255 622 08 622 08 NA 59 MHML 4 669 33 669 33 NA 60 HLLH 168 04 236 255 155 52 155 52 NA 61 MMHM 1 168 04 168 04 NA 62 HLML 4 x 236 255 622 08 622 08 NA 63 MHML 4 672 16 672 16 NA 64 HLMM 311 04 1 311 04 311 04 0 008 65 HLMH 2 622 08 622 08 0 008 66 HLHL 2 x 255 238 666 51 666 51 NA 67 HLHM 2 x 255 237 669 33 669 33 NA 68 HLHH 2 x 255 236 672 16 672 16 NA 69 HMLL 622 08 1 32 19 44 19 44 0 008 70 HMLM 1 16 38 88 38 88 0 008 71 HMLH 1 8 77 76 77 76 0 008 72 HMML 1 4 155 52 155 52 0 008 73 HMMM 1 2 311 04 311 04 0 008 74 HMMH 1 622 08 622 08 0 008 75 HMHL 255 238 666 51 666 51 NA 76 255 237 669 33 669 33 77 HMHH e 255 236 672 16 672 16 NA 78 HHLL e 666 51 1 4 x 238 255 155 52 155 52 NA 79 HMML e 1 4 166 63 166 63 NA 80 HHLM e
29. 35 MLHH 74 250 4 11 27 36 MMLL 4 x 250 11 x 91 74 17582 37 MMLM 1 74 25 38 MMLH 77 760 10625 7776 106 25 39 MMML 3125 1944 125 40 MMMM 15625 7776 156 25 41 MMMH 31875 15552 159 375 42 MMHL 15625 7776 x 66 64 161 13 43 MMHM 31875 15552 x 66 64 164 36 44 MMHH 15625 7776 x 66 172 64 64 x 255 238 45 MHLL 31875 15552 x 66 176 1 64 x 255 238 46 MHLM 10625 3888 212 5 47 MHLH 10625 1944 425 48 MHML 15625 1944 x 66 64 644 53 49 MHMM 31875 3888 x 66 64 657 42 50 MHMH 15625 1944 x 66 690 57 64 x 255 238 51 MHHL 31875 3888 x 66 704 38 64 x 255 238 62 0 5 e SILICON LABS Si53xx RM Table 18 SONET to Datacom Clock Multiplication Settings Continued Setting FRQSEL 3 0 fiN MHz Mult Factor four MHz 52 MHHM 155 520 15625 15552 156 25 53 MHHH 31875 31104 159 375 54 HLLL 15625 15552 x 66 64 161 13 55 HLLM 31875 31104 x 66 64 164 36 56 HLLH 15625 15552 x 66 172 64 64 x 255 238 57 HLML 31875 31104 x 66 176 1 64 x 255 238 58 HLMM 10625 7776 212 5 59 HLMH 10625 3888 425 60 HLHL 15625 3888 x 66 64 644 53 61 HLHM 31875 7776 x 66 64 657 42 62 HLHH 15625 3888 x 66 690 57 64 x 255 238 63 HMLL 31875 7776 x 66 704 38 64 x 255 238 64 HMLM 622 080 15625 15552 x 66 64 644 53 65 HMLH 31875 31104 x 66 64 657 42 66 HMML 15625 15552 x 66 690 57 64 x 255 238 67 H
30. 515316 Pin 1PLL 2 1 19 710 19 710 0 3 ps i o sa 515317 Pin 1PLL 112 1 710 1 710 0 3 ps 51 2 515319 12 5 1 1PLL 1 0 002 710 0 002 1417 0 3 ps ps 515323 Pin 1PLL 2 2 0 008 707 0 008 1050 0 3 ps P 112 515324 PC SPI 1PLL 2 2 0 002 710 0 002 1417 0 3 ps r 515326 I2C SPI 1PLL 2 2 0 002 710 0 002 1417 0 3 ps e TA amp 2 515327 1PLL 2 2 0 002 710 0 002 808 0 5 ps p gt 515366 Pin 1PLL 4 5 0 008 707 0 008 1050 0 3 ps 5 515368 12 5 1 1PLL 4 5 0 002 710 0 002 1417 0 3 ps ps ur s a n 515369 IC SPI 1PLL 4 5 0 002710 0 002 1417 0 3 ps POP n EUNT Sib374 4PLL 8 8 0 002710 0 002 808 0 4 ps Y js 515375 4PLL 4 4 0 002710 0 002 808 0 4 ps ae Note Maximum input and output rates may be limited by speed rating of device See each device s data sheet for ordering information Rev 0 5 SILICON LABS Si53xx RM Table 2 Product Selection Guide Si5322 25 65 67 T o LL rx c o iE E 5 2 lt 2 iL og x o 5 5 Ele S E o 5 5 2 zr 9 lt 9 gt 5 5 amp o ON o o c
31. 60 00 70 00 100 0 110 0 140 0 150 0 160 046 1 10 1001 IM 10M Figure 71 622 08 MHz In 672 16 MHz Out Loop BW 6 9 kHz 132 Rev 0 5 s SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz Smo 0 000 Carrier 672 162614 MHz 0 0925 dBm 10 00 110 0 140 0 150 0 100 2 51 6332 dBc Hz Start 12 kHz Stop 20 MHZ Center 10 006 MHz Span 19 988 MHZ NOdise Analysis Range x Band Marker Analysis Range Y Band Marker Intg Noise 61 1356 dBc 19 60 MHz RMS Noise 1 2409 mrad 71 0984 mdeg RMS Jitter 293 821 fsec Residual 3 00371 kHz 60 0 1001 1 Figure 72 622 08 MHz In 672 16 MHz Out Loop BW 100 Hz 10M SILICON LABS Rev 0 5 133 Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 155 519988 MHz 4 2154 dBm 1 100 Hz 64 6054 dBc Hz 2 1 103 3014 dBc Hz 10 00 3 10 kHz 127 0755 dBc Hz Bao 4 100 kHz 134 3491 dBc Hz 5 1 MHZ 144 5667 dBc Hz 20 00 gt 6 10 MHz 155 6637 dBc Hz Start 10 KHz stop 10 MHz 30 00 Center 5 005 MHz Span 9 99 MHZ Noise 40 00 Analysis Range x Band Marker Analysis Range Y Band Marker ae Intg Noise 76 2854 dBc 9 99 MHz 50 00 RMS Noise 216 893 prad 12 4271 mdeg q us RMS Jitter 221 963 fsec 00 09 Residual 474 866 Hz 70 00 80 00 100 0 110 0 20 0 30 0 140 0
32. Si5326 515327 515367 515368 and 515369 For the Si5374 and 515375 there is a different configuration utility Si537xDSPLLsim Both are available to download from www silabs com timing 8 104 Rev 0 5 e SILICON LABS Si53xx RM 8 High Speed I O 8 1 Input Clock Buffers Any Frequency Precision Clock devices provide differential inputs for the CKINn clock inputs These inputs are internally biased to a common mode voltage and can be driven by either a single ended or differential source Figure 38 through Figure 41 show typical interface circuits for CML LVDS or CMOS input clocks Note that the jitter generation improves for higher levels on CKINn within the limits in Table 8 AC Characteristics Alll Devices AC coupling the input clocks is recommended because it removes any issue with common mode input voltages However either ac or dc coupling is acceptable Figures 38 and 39 show various examples of different input termination arrangements Unused inputs should have an AC ground connection For microprocessor controlled devices the PD CkKn bits may be set to shut off unused input buffers to reduce power Si53xx gt 40 300 Q 40 k Vicm gt Figure 38 Differential LVPECL Termination 3 9 V Si53xx 1800 Driver 3000 820 Figure 39 Single Ended LVPECL Termination lt Rev 0 5 105 SI
33. jitter performance optimization at the application level The Si5327 features loop bandwidth values as low as 4 Hz Operating from a single 1 8 2 5 or 3 3 V supply the Si5327 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts Si5319 Si5324 515325 515326 515327 515367 515368 515369 515374 515375 on page 76 for a complete description Xtal Refclock RATE 1 0 x DSPLL BYPASS 0 2 CKIN 1 gt 1 CKIN 1 gt 2 2 ZH DSPLL fse Tel 2 CKOUT 1 CKIN 2 REST CKOUT 1 gt INT_C1B lt Signal Detect T 2 CKOUT 2 ENS EIN CKOUT 2 LOL CS CA lt CMODE SDA 500 4 SCL SDI Control 2 55 A 1 0 DEC RST GND VDD Figure 8 Si5327 Clock Multiplier and Jitter Attenuator Block Diagram 24 Rev 0 5 e SILICON LABS Si53xx RM 3 9 Si5365 The Si5365 is a low jitter precision clock multiplier for applications requiring clock multiplication without jitter attenuation The Si5365 accepts four clock inputs ranging from 19 44 MHz to 707 MHz and generates five frequency multipli
34. 08 MHz out 20 40 60 80 100 Phase Noise dBc Hz 120 140 Mili 100 1000 10000 100000 1000000 10000000 Offset Frequency Hz 100000000 Spectrum Analyzer Agilent Model E4440A Table 81 Output Format vs Jitter Bandwidth LVPECL Jitter LVDS Jitter CML Jitter RMS Low Swing LVDS RMS RMS Jitter RMS Broadband 1 kHz to 10 MHz 282 fs 269 fs 257 fs 261 fs OC 48 12 kHz to 20 MHz 297 fs 289 fs 290 fs 291 fs OC 192 20 kHz to 80 MHz 315 fs 327 fs 358 fs 362 fs OC 192 4 MHz to 80 MHz 180 fs 222 fs 277 fs 281 fs OC 192 50 kHz to 80 MHz 299 fs 313 fs 348 fs 351 fs Broadband 800 Hz to 80 MHz 325 fs 332 fs 357 fs 360 fs lt Rev 0 5 161 SILICON LABS Si53xx RM APPENDIX G NEAR INTEGER RATIOS To provide more details and to provide boundaries with respect to the Reference vs Output Frequency issue described in Appendix B on page 121 the following study was performed and is presented below Test Conditions m XA XB External Reference held constant at 38 88 MHz m Input frequency centered at 155 52 MHz then scanned Scan Ranges and Resolutions e 50 ppm with 2 ppm steps e 200 ppm with 10 ppm steps e 2000 ppm with 50 ppm steps m Output frequency always exactly four times the input frequency e Centered at 622 08 MHz m Jitter values are RMS integrated from 800 Hz to 80 MHz 38 88 MHz External XA X
35. 1 0 Clock Validation Time 00 2ms hitless switching not available 01 100 ms 10 200 ms 11 13s 7 11 1 Loss of Signal Alarms Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 515375 The device has loss of signal circuitry that continuously monitors CKINn for missing pulses The LOS circuitry generates an internal LOSn NT output signal that is processed with other alarms to generate CnB and ALARMOUT An LOS condition on CKIN1 causes the internal LOS1 alarm become active Similarly an LOS condition on CKINn causes the LOSn INT alarm become active Once a LOSn INT alarm is asserted on one of the input clocks it remains asserted until that input clock is validated over a designated time period If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over 7 11 1 1 Narrowband LOS Algorithms 515319 515324 515326 515327 515368 515369 515374 515375 There are three options for LOS LOS LOS no LOS which are selected using the LOSn_EN registers The values for the LOSn_EN registers are given in Table 49 Table 49 Loss of Signal Registers LOSn EN 1 0 LOS Selection 00 Disable all LOS monitoring 01 Reserved 10 LOS A enabled 11 LOS enabled 96 Rev 0 5 lt SILICON LABS Si53xx RM 7 11 1 2 Standard LOS Si5319 515324 515326 515327
36. 1 0 il xa BYPASS DSBL2 CKIN_1 2 N3 1 i CKIN 1 E CKOUT_1 prive rm CKOUT 1 CKIN 2 2 CKIN 2 DSPLL _ CKOUT_2 3 BIS ERG N1_HS Ncd a udi CKOUT 2 _ DSBL2 BYPASS CKIN_4 21 N3 4 GKOUT S tenca CKOUT 3 N2 DSBL34 CKOUT 2 FSYNC 1 2 CKOUT 4 CKIN 3 LOGIC TERENCA E CKOUT 4 4 31 oon NGB CKOUT 5 FSYNC ENS CKOUT 5 C3B lt DSBL5 INT_ALM lt Control lt 2 lt CS0 lt gt CS1 gt lt VDD LOL lt L al cae T Rd d 8 9 8 Zuo lt lt lt lt e Figure 13 Si5369 Clock Multiplier and Jitter Attenuator Block Diagram 3 14 Si5374 75 Compared to Si5324 19 In general the Sib374 can be viewed as a quad version of the Si5324 and the Si5375 can be viewed as a quad version of the Si5319 However there are not exactly the same This is an overview of the differences 1 The Si5374 75 cannot use a crystal as its OSC reference It requires the use of a single external single ended or differential crystal oscillator 2 Si5374 75 only supports 2 as its serial port protocol and does not have SPI No 2 address pins are available on the Si5374 75 3 The Si5374 75 does not provide separate INT CK1B and CK2B pins to indicate when CKIN1 and CKIN2 do not have valid clock inputs Instead th
37. 30 SFOUT 1 U D 33 SFOUTO U D Table 71 Si5319 Si5324 Pullup Down Pin Si5326 Pull 1 RST U 11 RATEO U D 15 RATE1 U D 21 CS CA U D 22 SCL 24 AO D 25 A1 D 26 A2 SS D 27 SDI D 36 CMODE U D 148 0 5 e SILICON LABS Si53xx RM Table 72 Si5325 Pullup Down Pin 515325 Pull 1 RST U 21 CS CA U D 22 SCL D 24 AO D 25 A1 D 26 A2 SS D 27 SDI D 36 CMODE U D Table 73 Si5326 Pullup Down Pin Si5326 Pull 1 RST U 11 RATEO U D 15 RATE1 U D 19 DEC D 20 INC D 21 CS CA U D 22 SCL D 24 AO D 25 A1 D 26 A2 SS D 27 SDI D 36 CMODE U D lt Rev 0 5 149 SILICON LABS 5153 Table 74 515327 Pullup Down Pin Si5327 Pull 1 RST U 11 RATEO U D 15 RATE1 U D 21 CS U D 22 SCL 24 AO D 25 A1 D 26 A2 SS D 27 SDI D 36 CMODE U D Table 75 Si5365 Pullup Down Pin 515365 Pull 3 RST U 4 FRQTBL U D 13 50 D 22 AUTOSEL U D 37 DBL2 BY U D 50 DSBL5 U D 57 CS1 U D 60 BWSELO U D 61 BWSEL1 U D 66 DIV34 0 U D 67 DIV34 1 U D 68 FRQSELO U D 69 FRQSEL1 U D 70 FRQSEL2 U D 71 FRQSEL3 U D 80 SFOUT1 U D 85 DBL34 U 95 SFOUTO U D 150 Rev 0 5 lt SILICON
38. 53 15 LMHL 51 2 x 66 64 657 42 16 LMHM 25 x 66 64 x 255 238 690 57 17 LMHH 25 x 66 64 x 255 237 693 48 18 LHLL 51 2 x 66 64 x 255 238 704 38 19 LHLM 51 2 x 66 64 x 255 237 707 35 20 LHLH 31 25 2 62 5 21 LHML 4 125 22 LHMM 8 250 23 LHMH 53 125 2 106 25 24 LHHL 4 212 5 25 LHHM 8 425 26 LHHH 106 25 3 2 x 66 64 164 36 27 MLLL 3 2 x 66 64 x 255 238 176 1 28 MLLM 3 2 x 66 64 x 255 237 176 84 29 MLLH 2 212 5 30 MLML 4 425 31 MLMM 6 x 66 64 657 42 32 MLMH 6 x 66 64 x 255 238 704 38 33 MLHL 6 x 66 64 x 255 237 707 35 e Rev 0 5 57 SILICON LABS 5153 Table 17 Datacom Clock Multiplication Settings FRQTBL 0 Continued Setting FRQSEL 3 0 fin MHz Mult Factor four MHz 34 MLHM 125 10 8 x 66 64 161 13 35 MLHH 10 8 x 66 64 x 255 238 172 64 36 MMLL 10 8 x 66 64 x 255 237 173 37 37 MMLM 5 66 64 644 53 38 MMLH 5 x 66 64 x 255 238 690 57 39 MMML 5 x 66 64 x 255 237 693 48 40 MMMM 156 25 66 64 161 13 41 MMMH 66 64 x 255 238 172 64 42 MMHL 66 64 x 255 237 173 37 43 MMHM 4 x 66 64 644 53 44 MMHH 4 x 66 64 x 255 238 690 57 45 MHLL 4 x 66 64 x 255 237 693 48 46 159 375 66 64 164 36 47 66 64 255 238 176 1 48 MMHL 66 64 x 255 237 176 84 49 MMHM 4
39. 61 ns 6 6 4 Using FS OUT as a Fifth Output Clock 515366 In applications where the frame synchronization functionality is not needed 5 OUT can be used as a fifth clock output In this case no realignment requests should be made to the NC5 divider This is done by holding FS ALIGN to 0 and CK CONF 0 lt Rev 0 5 71 SILICON LABS Si53xx RM 6 6 5 Disabling FS_OUT Si5366 The FS_OUT maybe disabled via the DBLFS pin see Table 29 The additional state M provided allows for FS_OUT to drive a CMOS load while the other clock outputs use a different signal format as specified by the SFOUTTI 0 pins Table 29 F8 OUT Disable Control DBLFS DBLFS FS OUT State H Tri State Powerdown M Active CMOS Format L Active SFOUT 1 0 Format 6 7 Output Clock Drivers The devices include a flexible output driver structure that can drive a variety of loads including LVPECL LVDS CML and CMOS formats The signal format is selected jointly for all outputs using the SFOUT 1 0 pins which modify the output common mode and differential signal swing See Table 4 DC Characteristics for output driver specifications The SFOUT 1 0 pins are three level input pins with the states designated as L ground M Vpp 2 and H Vpp Table 30 shows the signal formats based on the supply voltage and the type of load being driven For the CMOS setting SFOUT LH both output pins drive single ended in phase sig
40. 78 Rev 0 5 lt SILICON LABS Si53xx RM The output divider NC1 is the product of a high speed divider N1_HS and a low speed divider N1_LS Similarly the feedback divider N2 is the product of a high speed divider N2_HS and a low speed divider N2_LS When multiple combinations of high speed and low speed divider values are available to produce the desired overall result selecting the largest possible high speed divider value will produce lower power consumption With the fosc and N1 ranges given above any output frequency can be achieved from 2 kHz to 945 MHz where NC1 ranges from 4 x 220 to 6 For NC1 5 the output frequency range 970 MHz to 1 134 GHz can be obtained For NC1 4 the output frequency range from 1 2125 to 1 4175 GHz is available Because there is only one DCO and all of the outputs must be frequencies that are integer divisions of the DCO frequency there are restrictions on the ratio of one output frequency to another output frequency That is there is considerable freedom in the ratio between the input frequency and the first output frequency but once the first output frequency is chosen there are restrictions on subsequent output frequencies These restrictions are caused by the fact that the N1 HS divider is shared among all of the outputs DSPLLsim should be used to determine if two different simultaneous outputs are compatible with one another The same issue exists for inputs of different frequency both in
41. CKIN 3 2 og NCHS FNC 4 ag CKOUT 2 t DBL2 BY 4 4 gt Lula rl 2 CKOUT 3 CKIN 4 i CKOUT 3 N2 DBL34 CKOUT_2 gt rsync DIV34 1 0 CKIN 3 LOGIC t CONF gt gt ALIGN 21 CKOUT 4 CKiN 4 TN ed CKOUT 4 C2B lt FSYNC 5 Y C3B lt 2 CKOUT 5 ALRMOUT lt caa eg CKOUT 5 4 DBL5 C2A lt CS0 CS1 lt VDD LOL 4 us MERE NU 11 9 eels Tere e obe se Er2u5 Sle BBuguszeob5 va gt 2 o m tc o Figure 10 515366 Jitter Attenuating Clock Multiplier Block Diagram 26 Rev 0 5 e SILICON LABS Si53xx RM 3 11 Si5367 The Si5367 is a low jitter precision clock multiplier for applications requiring clock multiplication without jitter attenuation The 515367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency multiplied clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The Si5367 input clock frequency and clock multiplication ratio are programmable through an 2 or SPI interface The DSPLL loop bandwidth is digitally programmable from 150 kHz to 1 3 MHz Operating from a single 1 8 2 5 or 3 3 V supply the 515367 is ideal for providing clock multiplication in high performance timing applications See 7 Microprocessor C
42. CKOUT 2 515368 1 Detector DCO gt NC2 gt CKOUT 2 515369 erin wu oit L 2 3 271 515368 2 3 1 3 515369 CKOUT 3 2 4 N34 159 2 4 2 CKOUT 4 p c acti ru elt CKOUT 4 NCS Li 2 CKOUT 5 v CKOUT 5 Bandwidth FSYNC Note 5 ion 6 7 lt gt Control 515368 Si 310 515326 EE RE RR RS a mem Mu 515368 Note There are multiple outputs at different frequencies because of limitations caused by the DCO N1 HS Figure 26 Narrowband PLL Divider Settings 515319 515324 515326 515327 515368 515369 515374 515375 Table 35 Narrowband Frequency Limits Signal Frequency Limits CKINn 2 kHz 710 MHz fa 2 kHz 2 MHz fosc 4 85 5 67 GHz four 2 kHz 1 475 GHz Note Fmax 808 MHz for the Si5327 Si5374 and Si5375 Table 36 Dividers and Limits Divider Equation Si5325 515367 515319 515324 515326 515327 615368 515369 515374 515375 1 HS x 15 N1 HS 4 5 11 N1 HS 4 5 11 NCn_LS 1 2 4 6 2420 NCn_LS 1 2 4 6 27201 N2 N2 2 HSx LS N2 HS 1 N2 HS 4 5 11 N2 LS 32 34 36 2 9 N2 LS 2 4 6 2 20 N3 N3 N3n N3n 1 2 3 2 19 N3n 1 2 3 2 19
43. CKOUTn Together Unused output drivers should be powered down per Table 57 or left floating The pin controlled parts have a DBL2_BY pin that can be used to disable CKOUT2 Table 57 Disabling Unused Output Driver Output Driver Si5365 Si5366 515325 515326 515367 515368 CKOUT 1 CKOUT2 N A CKOUT3 and CKOUT4 DBL34 CKOUT5 FS_OUT DBL5 DBL_FS Use SFOUT_REG to disable individ ual CKOUTn 108 Rev 0 5 SILICON LABS Si53xx RM Output Disable 1000 1000 gt CKOUT CKOUT p exe Figure 45 CKOUT Structure 8 2 3 Typical Clock Output Scope Shots Table 58 Output Format Measurements Name SFOUT Pin SFOUT Code Single Diff Vocm Vpk pk Vpk pk Reserved HH LVDS HM 7 35 7 1 2 HLK 6 25 5 3 05 LVPECL MH 5 75 1 5 2 10 Reserved MM 4 Low Swing LVDS ML 3 25 5 1 2 CMOS LH 2 3 3 1 65 Disable LM 1 Reserved LL 0 Notes 1 Typical measurements with an Si5326 at 3 3 V 2 measurements Vpk pk on a single output double the values for differential Vdd 3 3 V 50 ac load to ground e Rev 0 5 109 SILICON LABS Si53xx RM 8 3 Typical Scope Shots for SFOUT Options a a ERIT Ch1 500m M 20 0ns 5 0GS s 80 Ops pt Ch
44. FOSn_FLG drive the output interrupt and can be individually masked Since CKIN3 and CKIN4 are configured as frame sync inputs CK_CONFIG_REG 1 ALRMOUT functions as the alignment alarm output ALIGN INT as described in Section 7 8 Frame Synchronization Realignment Si5368 and CK_CONFIG_REG 1 The equations below assume that the output alarm is active high however the active polarity is selectable via the CK BAD POL bit Operation of the C1B C2B C3B and ALRMOUT pins is enabled based on setting the C1B PIN C2B PIN and ALRMOUT PIN register bits Otherwise the will tri state Also if NT PIN 1 the interrupt functionality will override the appearance of ALRMOUT at the output even if ALRMOUT PIN 1 Once an LOS or FOS alarm is asserted for one of the input clocks it is held high until the input clock is validated over a designated time period The validation time is programmable via the VALTIMET1 0 register bits as shown in Table 8 AC Characteristics All Devices If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over Note that hitless switching between input clocks applies only when the input clock validation time VALTIMET1 0 01 or higher Table 53 Alarm Output Logic Equations 515368 and CKCONFIG REG 1 FOS EN Alarm Output Equations 0 LOS1 INT or 1053 INT and FSYNC SWTCH REG Dis
45. Figure 46 sfout 2 CMOS BE Chi 500mY M20 0ns 5 0055 IT 80 0ps pt A Ch4 ODV Figure 47 sfout_3 lowSwingLVDS 110 Rev 0 5 SILICON LABS Si53xx RM Chi 500mY M 20 0ns 5 0GS s 80 Ops pt Ch4 0 0V Figure 48 sfout 5 LVPECL EE Chi 500m M 20 0ns 5 0GS s 80 Dpshpt Ch 0 0Y Figure 49 sfout 6 CML Rev 0 5 111 SILICON LABS Si53xx RM Chi 500m M 20 0ns 5 0GS s 80 0ps pt Ch 00 Figure 50 sfout 7 LVDS 112 Rev 0 5 SILICON LABS Si53xx RM 8 4 Crystal Reference Clock Interfaces Si5316 Si5319 Si5323 Si5324 515326 515327 515366 515368 515369 515374 515375 All devices other than the 515374 515375 can use an external crystal or external clock as reference The 515374 and 515375 are limited to an external reference oscillator and cannot use a crystal If an external clock is used it must be ac coupled With appropriate buffers the same external reference clock can be applied to CKINn Although the reference clock input can be driven single ended See Figure 51 best performance is with a crystal or differential LVPECL source See Figure 55 If the crystal is located close to a fan it is recommended that the crystal be covered with some type of thermal cap For various crystal vendors and part numbers see Appendix A Narrowband References on page 119 1 For SONET applications the best j
46. Hz Blue RF Generator Green Si5326 Red 515324 0 00E 00 Figure 92 RF Generator Si5326 Si5324 1 kHz Jitter 622 08 MHz in 622 08 MHz out 1 00E 08 2 00E 01 4 00E 01 6 00E 01 8 00E 01 1 00E 02 1 20E 02 1 40E 02 Phase Noise dBc Hz 1 60E 02 1 80E 02 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 Offset Frequency Hz Blue RF Generator Green Si5326 Red 515324 Figure 93 RF Generator Si5326 Si5324 5 kHz Jitter 1 00E 08 SILICON LABS Rev 0 5 167 Si53xx RM 622 08 MHz in 622 08 MHz out 0 00E 00 2 00E 01 4 00E 01 6 00E 01 8 00E 01 1 00E 02 Phase Noise dBc Hz 1 20E 02 1 40E 02 1 60E 02 1 80E 02 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00 08 Offset Frequency Hz Blue RF Generator Green Si5326 Red Si5324 Figure 94 RF Generator Si5326 Si5324 10 kHz Jitter 168 Rev 0 5 SILICON LABS Si53xx RM APPENDIX I Si5374 AND Si5375 PCB LAYOUT RECOMMENDATIONS The following is a set of recommendations and guidelines for printed circuit board layout with the Si5374 and Si5374 devices Because the four DSPLLs are in close physical and electrical proximity to one another PCB layout is critical to achieving the highest levels of jitter performance The following images were taken from the Si537x EVB evaluation board layout For more details about
47. LABS Rev 0 5 17 Si53xx RM 3 2 515319 515319 is a jitter attenuating precision M N clock multiplier for applications requiring sub 1 ps jitter performance The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis The device provides virtually any frequency translation combination across this operating range The Si5319 input clock frequency and clock multiplication ratio are programmable through an 2 SPI interface The Si5319 is based on Silicon Laboratories 3rd generation DSPLL technology which provides any frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components The DSPLL loop bandwidth is digitally programmable providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 76 for a complete description j Xtal or Refclock
48. LABS Si53xx RM Table 76 Si5366 Pullup Down Pin Si5366 Pull 8 RST U 4 FRQTBL U D 13 50 D 20 FS SW 21 FS ALIGN 22 AUTOSEL U D 32 RATEO U D 37 DBL2 BY U D 42 RATE1 U D 50 DBL_FS U D 51 CK_CONF D 54 DEC D 55 INC D 56 FOS U D 57 CS1_C4A U D 60 BWSELO U D 61 BWSEL1 U D 66 DIV34_0 U D 67 DIV34_1 U D 68 FRQSELO U D 69 FRQSEL1 U D 70 FRQSEL2 U D 71 FRQSEL3 U D 80 SFOUT1 U D 85 DSBL34 U 95 SFOUTO U D lt Rev 0 5 151 SILICON LABS 5153 Table 77 515367 Pullup Down Pin Si5367 Pull 3 RST U 13 CS0_C3A D 57 CS1_C4A U D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U D Table 78 Si5368 Pullup Down Pin Si5368 Pull 3 RST U 13 CS0_C3A D 21 FS_ALIGN D 32 RATEO U D 42 RATE1 U D 54 DEC D 55 INC D 57 CS1_C4A U D 60 SCL D 68 AO D 69 A1 D 70 A2 SSB D 71 SDI D 90 CMODE U D 152 Rev 0 5 e SILICON LABS Si53xx RM Table 79 Si5369 Pullup Down Pin Si5368 Pull 3 RST U 13 CS0_C3A D 21 FS_ALIGN D 32 U D 42 RATE1 U D 57 CS1_C4A U D 60 SCL 68 AO D 69 A1 D 70 A2 SSB D 71 SDI D 90 CMODE U D Table 80 Si5374 75 Pullup Down
49. PLL lock detection algorithm that indicates the lock status on the LOL output pin and the LOL INT read only register bit See Section 7 11 8 LOL 515319 515324 515326 515327 515368 515369 515374 515375 for a detailed description of the LOL algorithm 7 2 PLL Self Calibration The device performs an internal self calibration before operation to optimize loop parameters and jitter performance While the self calibration is being performed the DCO is being internally controlled by the self calibration state machine and the LOL alarm will be active The output clocks can either be active or disabled depending on the SQ CAL bit setting The self calibration time t is given Table 8 AC Characteristics All Devices The procedure for initiating the internal self calibration is described below 7 2 1 Initiating Internal Self Calibration Any of the following events will trigger an automatic self calibration m Internal DCO registers out of range indicating the need to relock the DCO m Setting the CAL register bit to 1 In any of the above cases an internal self calibration will be initiated if a valid input clock exists no input alarm and is selected as the active clock at that time The external crystal or reference clock must also be present for the self calibration to begin LOSX INT 0 narrowband only When self calibration is initiated the device generates an output clock if the SQ CAL bit is set to 0
50. Range Band Marker Analysis Range Y Band marker 30 00 Intg Noise 59 5456 dBc 19 69 MHz RMS Noise 1 49018 mrad 85 3808 40 00 RMS gitter 237 169 fsec Residual FM 7 89282 kHz 50 00 80 00 110 0 140 0 50 0 160 0 18 E SE 1 10k 1001 1 10 Figure 81 10 MHz In 1 GHz Out 142 Rev 0 5 s SILICON LABS Si53xx RM Digital Video HD SDI 27 MHz in 148 5 MHz out 100 Phase Noise dBc Hz 120 140 160 10 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency Hz Jitter Band Jitter Brick Wall 10 Hz to 20 MHz 2 42 ps RMS Peak to peak 14 0 ps Phase noise equipment Agilent model JS500 Rev 0 5 SILICON LABS 143 Si53xx RM APPENDIX D ALARM STRUCTURE LOS INT LOSX FLG Sticky LOSX MSK Write 0 SS 22 to clear Ls LOS1_INT EE LOS1 FLG sticky 1051 to clear 1082 LOS2 FLG MN Sticky msk Write 0 eG to clear oT ps FOS1 INT l FOS1 FLG 7 Sticky FOS1 MSK p Write 0 _ to clear A FOS2 INT FOS2 FLG ps Sticky FOS2 MSK
51. The 5 OUT pulse should not be changed more than once per 5 OUT period If a FSYNC realignment is being made the pulse width should not be changed until the realignment is complete The FS OUT pulse width and the skew value should not be changed within the same 5 OUT period Before writing a new value into FSYNC_PW 9 0 the user should set the register bit FPW VALID 0 This causes the FS OUT pulse width state machine to keep using the previous FSYNC PW 9 0 value ignoring the new register values as they are being written Once the new FSYNC_PW 9 0 value has been completely written the user should set FPW VALID 1 at which time the FS OUT pulse width state machine will read the new pulse width value Writes to NC5 LS should be treated the same as writes to FSYNC PW Thus all writes to NC5 LS should occur only when FPW VALID 0 Any such writes will not take effect until FPW VALID 1 Note that must be less than or equal to 710 MHz when CK CONFIG REG 1 otherwise the 5 OUT buffer and NC5 divider must be disabled 7 8 5 Using FS OUT as a Fifth Output Clock 515368 In applications where the frame synchronization functionality is not needed CONFIG REG 0 FS OUT can be used as a fifth clock output In this case no realignment requests should be made to the NC5 divider hold FS ALIGN 0 and FSYNC ALIGN REG 0 Output pulse width and polarity controls for FS OUT are still available as described above The 509
52. The output clock will appear when the device begins self calibration The frequency of the output clocks may be as high as 5 above or as low as 20 below the final locked value If SQ CAL 1 the output clocks are disabled during self e Rev 0 5 79 SILICON LABS Si53xx RM calibration and will appear after the self calibration routine is completed The SQ_ICAL bit is self clearing after a successful ICAL After a successful self calibration has been performed with a valid input clock it is not necessary to reinitiate a self calibration for subsequent losses of input clock If the input clock is lost following self calibration the device enters digital hold mode When the input clock returns the device relocks to the input clock without performing a self calibration After power up and writing of dividers or PLL registers the user must set CAL 1 to initiate a self calibration LOL will go low when self calibration is complete Depending on the selected value of the loop bandwidth it may take a few seconds more for the output frequency and phase to completely settle It is recommended that a software reset precede all ICALs and their associated register writes by setting RST REG Register 136 7 7 2 1 1 PLL Self Calibration 515324 515327 515369 515374 Due the low loop bandwidth of the 515324 515327 515369 515374 the lock time of the Si5324 27 69 75 is significantly longer than the lock time of the Si5
53. Truth Table Cases CKOUT ALWAYS ON SQ ICAL Results 1 0 0 CKOUT OFF until after the first ICAL 22 0 1 CKOUT OFF until after the first successful ICAL i e when LOL is low 33 1 0 CKOUT always ON including during an ICAL CKOUT always ON including during an ICAL 44 1 1 Use these settings to preserve output to output skew Notes 1 Case 1 should be selected when an output clock is not desired until the part has been initialized after power up but is desired all of the time after initialization 2 Case 2 should be selected when an output clock is never desired during an any ICAL Case 2 will only generate outputs when the outputs are at the correct output frequency 3 Case 3 should be selected whenever a clock output is always desired 4 Case 4 is the same as Case 3 80 Rev 0 5 e SILICON LABS Si53xx RM 7 3 Input Clock Configurations Si5367 and Si5368 The device supports two input clock configurations based on CK_CONFIG_REG See 6 5 Frame Synchronization Si5366 on page 70 for additional details 7 4 Input Clock Control This section describes the clock selection capabilities manual input selection automatic input selection hitless switching and revertive switching The 515319 515327 and 515375 support only pin controlled manual clock selection Figure 27 and Figure 28 provide top level overviews of the clock selection logic though they do not cover wideban
54. Write 0 oF J to clear gt i LOL INT Sica LOL FLG e Wes clik 22 7 to clear p 32 2 WIDEBAND MODE LOS1 EN LOS HLOSI INT Detector _ POL PD 1 INT E DN FOS e gt o Detector m 7 51 EN INT_PIN _ FOS CK1 BAD PIN LOS2 EN LOS ES N LOS2 INT Detector d CK BAD POL PD CK2 gt 5 ES FOS2 INT Detector 52 CK2 BAD PIN FOS EN Figure 82 Si5324 and Si5326 Alarm Diagram 144 Rev 0 5 lt SILICON LABS Si53xx RM LOS INT LOSX FLG no LOSX MSK to clear INT POL LOS1 INT SENE LOS1 FLG a icky LOS1 MSK TE Wii 21 pace Q 4 LOS2 INT LOS2 FLG g Sticky kosem bVve Write 0 6 p to clear 1053 INT m LOS3 FLG Sticky Write 0 083 MSK q PF to clear gt 1084 INT LOSEELG Sticky 1054 MSK Write 0 E to clear FOS1 INT i 51 FLG m e Sticky Write 0 OO m to clear Men FOS2 INT E FOS2
55. a frequency offset alarm FOS if the threshold is exceeded This FOS feature is available for SONET SDH applications Both Stratum 3 3E and SONET Minimum Clock SMC FOS thresholds are supported The 515319 515323 515324 515326 515366 515368 and 515369 provide a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost During digital hold the DSPLL generates an output frequency based on historical average that existed a fixed amount of time before the error event occurred eliminating the effects of phase and frequency transients that may occur immediately preceding entry into digital hold The Si5322 Si5325 515365 Si5367 are frequency flexible low jitter clock multipliers that provide jitter generation of 0 6 ps RMS without jitter attenuation These devices provide low jitter integer clock multiplication or fractional clock synthesis but they are not as frequency flexible as the Si5319 23 24 26 66 68 69 The devices vary according to the number of clock inputs number of clock outputs and control method The 515322 Si5365 are pin controlled clock multipliers The frequency plan for these devices is selectable from frequency lookup tables 12 Rev 0 5 e SILICON LABS Si53xx RM A wide range of settings are available but they are a subset of the frequency plans supported by the Si5323 and 515366 jitter attenuating clock multi
56. any event causing digital hold do not affect the digital hold frequency Also noise related to input clock jitter or internal PLL jitter is minimized If a highly stable reference such as an oven controlled crystal oscillator is supplied at XA XB an extremely stable digital hold can be achieved If a crystal is supplied at the XA XB port the digital hold stability will be limited by the stability of the crystal 6 4 2 Recovery from Digital Hold 515316 515323 515366 When the input clock signal returns the device transitions from digital hold to the selected input clock The device performs hitless recovery from digital hold The clock transition from digital hold to the returned input clock includes phase buildout to absorb the phase difference between the digital hold clock phase and the input clock phase 6 4 3 Wideband VCO Freeze Si5322 Si5365 If an LOS condition exists on the selected input clock the device freezes the VCO In this mode the device provides a stable output frequency until the input clock returns and is validated When the device enters VCO freeze the internal oscillator is initially held to its last frequency value 6 5 Frame Synchronization Si5366 FSYNC is used in applications that require a synchronizing pulse that has an exact number of periods of a high rate clock Frame Synchronization is selected by setting CK CONF 1 and FRQTBL L In a typical frame synchronization application CKIN1 and CKIN
57. are shown in Table 23 The Si5366 has two modes of operation See Section 6 5 Frame Synchronization Si5366 With CK CONF 0 any of the four input clocks may be selected manually however when CK_CONF 1 the inputs are paired CKIN1 is paired with and likewise for CKIN2 and CKIN4 Therefore only two settings are available to select one of the two pairs Table 23 Manual Input Clock Selection Si5365 Si5366 AUTOSEL L CS1 CSO 515365 515366 CK CONF 0 CK_CONF 1 5 Output Clocks FS OUT Configuration 00 CKIN1 CKIN1 CKIN1 CKIN3 01 CKIN2 CKIN2 CKIN2 CKIN4 10 CKIN3 CKIN3 Reserved 11 CKIN4 CKIN4 Reserved Notes 1 To avoid clock switching based on intermediate states during a CS state change the CS input pins are internally deglitched 2 If the selected clock enters an alarm condition the PLL enters digital hold mode lt Rev 0 5 67 SILICON LABS 5153 6 3 2 Automatic Clock Selection 515322 515323 515365 515366 The AUTOSEL input pin sets the input clock selection mode as shown in Table 24 Automatic switching is either revertive or non revertive Setting AUTOSEL to M or H changes the CSn_CAm pins to output pins that indicate the state of the automatic clock selection See Table 25 and Table 26 Digital hold is indicated by all CnB signals going high after a valid ICAL Table 24 Automatic Manual Clock Selection
58. b N31 gt CKIN 1 2 2 1 2 N32 INT_C1B lt gt Signal C2B lt Detect CMODE SDA SDO SCL 4 SDI 255 Control DSPLL fosc N2 BYPASS 2 CKOUT_1 CKOUT 1 N1 HS Uh 21 CKOUT 2 me 1 CKOUT 2 VDD anD Figure 6 Si5325 Low Jitter Clock Multiplier Block Diagram 22 Rev 0 5 SILICON LABS Si53xx RM 3 7 Si5326 The Si5326 is a jitter attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance The Si5326 accepts dual clock inputs ranging from 2kHz to 710MHz and generates two independent synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The device provides virtually any frequency translation combination across this operating range The Si5326 input clock frequency and clock multiplication ratios are programmable through an 2 or SPI interface The DSPLL loop bandwidth is digitally programmable from 60 Hz to 8 kHz providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Control
59. be used The FOS reference clock is set via the FOSHEFSEL 2 0 bits as shown in Table 50 More than one input can be monitored against the FOS reference i e there can be more than one monitored clock but only one FOS reference When the XA XB input is used as the FOS reference there is only one reference frequency band that is allowed from 37 MHz to 41 MHz e Rev 0 5 97 SILICON LABS Si53xx RM Table 50 FOS Reference Clock Selection FOS Reference FOSREFSEL 2 0 Si5326 Si5368 000 XA XB XA XB 001 CKIN1 CKIN1 010 CKIN2 default CKIN2 default 011 Reserved CKIN3 100 Reserved CKIN4 all others Reserved Reserved Both the FOS reference and the FOS monitored clock must be divided down to the same clock rate and this clock rate must be between 10 MHz and 27 MHz As can be seen in Figure 33 the values for P and Q must be selected so that the FOS comparison occurs at the same frequency The registers that contain the values for P and Q are the 2 0 registers CKIN gt Compare FOS REF M 10 MHz min 27 MHz max Figure 33 FOS Compare The frequency band of each input clock must be specified to use the FOS feature The CLKNAATE registers specify the frequency of the device input clocks as shown in Table 51 When the FOS reference is the XA XB oscillator either internal or external the value of Q in Figure 33 is always 2 for an effec
60. may incorrectly cause the Any Frequency device to be forced into Digital Hold For example it is recommended that while in Free Run Mode LOSA be used instead of LOS because the two clock inputs will not be the same exact frequency This will avoid false LOS assertions when the XA XB frequency differs from the other clock inputs by more than 100 ppm See Section 7 11 1 3 for more information on LOSA 7 11 1 4 LOS disabled 515319 515324 515326 515327 515368 515369 515374 515375 For situations where form of LOS is desired LOS can be disabled by writing 00 to LOSn_EN This mode is provided to support applications which implement custom LOS algorithms off chip If this approach is taken the only remaining methods of entering Digital Hold will be FOS or by setting DHOLD register 3 bit 5 7 11 1 5 Wideband LOS Algorithm Si5322 Si5365 Each input clock is divided down to produce 78 kHz to 1 2 MHz signal before entering the LOS monitoring circuitry The same LOS algorithm as described in the above section is then used FOS is not available in wideband devices 7 11 1 6 LOS Alarm Outputs 515319 515324 Si5325 Si5326 515327 515367 515369 515374 Si5375 When LOS is enabled an LOS condition on CKIN1 causes LOS1 INT to become active Similarly when LOS is enabled LOS condition CKIN2 causes LOS2 NT to become active Once LOSn INT alarm is asserted on one of the input clocks it remains asserted until the input c
61. or 53 INT ALRMOUT LOS4 INT or FOS4 INT 1 L LOS1 INT or LOS3 INT and FSYNC SWTCH FSYNC switching Disables FOS C2B LOS2 INT or LOS4 INT and SWTCH mode C3B tri state ALRMOUT ALIGN INT M or H C1B LOS1 INT or 1053 INT and SWTCH or FOS1 INT 1052 INT or 1054 INT and FSYNC SWTCH or FOS2 INT C3B tri state ALRMOUT ALIGN INT 74 Rev 0 5 e SILICON LABS Si53xx RM 6 9 5 1 PLL Lock Detect 515316 Si5323 Si5366 The PLL lock detection algorithm indicates the lock status on the LOL output pin The algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock If the time between two consecutive phase cycle slips is greater than the Retrigger Time the PLL is in lock The LOL output has a guaranteed minimum pulse width as shown in Table 8 AC Characteristics All Devices The LOL pin is also held in the active state during an internal PLL calibration The retrigger time is automatically set based on the PLL closed loop bandwidth See Table 34 Table 34 Lock Detect Retrigger Time PLL Bandwidth Setting BW Retrigger Time ms 60 120 Hz 53 120 240 Hz 26 5 240 480 Hz 13 3 480 960 Hz 6 6 960 1920 Hz 3 3 1920 3840 Hz 1 66 3840 7680 Hz 833 6 9 5 2 Lock Detect 515322 515365 PLL loss of lock indicator is not available for thes
62. output phase and frequency For example it is recommended that the crystal not be placed close to a fan that is being turned off and on If a situation such as this is unavoidable the crystal should be thermally isolated with an insulating cover SILICON LABS Rev 0 5 119 Si53xx RM Fundamental Mode Crystals For cost sensitive applications that do not have the most demanding jitter requirements all of the narrow band devices can use fundamental mode crystals that are in the lowest frequency band ranging from 37 to 41 MHz corresponding to RATE LL Unlike the other narrowband members of the family the 515327 is only capable of using fundamental mode crystals that are in this range For a more detailed discussion of the trade offs associated with this approach and a list of approved low frequency crystals please see the application note AN591 which can be downloaded from www silabs com timing Reference Drift During Digital Hold long term and temperature related drift of the reference input result in a one to one drift of the output frequency That is the stability of the any frequency output is identical to the drift of the reference frequency This means that for the most demanding applications where the drift of a crystal is not acceptable an external temperature compensated or ovenized oscillator will be required Drift is not an issue unless the device is in Digital Hold Also the initial accuracy of the reference os
63. page 96 If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over 515326 Note that hitless switching between input clocks applies only when the input clock validation time VALTIMET1 0 01 or higher 7 11 4 LOS 515319 Si5375 A LOS condition causes the LOS INT read only register bit to be set This LOS condition will also be reflected onto the INT CB pin 7 11 5 C1B C2B C3B ALRMOUT 515367 515368 515369 CONFIG REG 0 The generation of alarms on the C1B C2B C3B and ALRMOUT outputs is a function of the input clock configuration and the frequency offset alarm enable as shown in Table 52 The LOSn INT and FOSn INT signals are the raw outputs of the alarm monitors These appear directly in the device status registers Sticky versions of these bits LOSn FLG FOSn drive the output interrupt and can be individually masked When the device inputs are configured as four input clocks CK CONFIG 0 the ALRMOUT pin reflects the status of the CKIN4 input The equations below assume that the output alarm is active high however the active polarity is selectable via the CK BAD POL bit Operation of the C1B C2B C3B and ALRMOUT pins is enabled based on setting the C1B PIN C2B PIN PIN and ALRMOUT PIN register bits Otherwise the pin will tri state Also if NT PIN 1 the interrupt functionality will override t
64. range of dividers and multipliers nearly any output frequency can be created from a fixed input frequency For typical telecommunications and data communications applications the hardware control parts Si5316 Si5322 Si5323 515365 and 515366 provide simple pin control The microprocessor controlled parts 515319 515324 515325 515326 515327 515367 515368 and Si5369 provide a programmable range of clock multiplications To assist users in finding valid divider settings for a particular input frequency and clock multiplication ratio Silicon Laboratories offers PC based software DSPLLsim that calculates these settings automatically When multiple divider combinations produce the same output frequency the software recommends the divider settings yielding the recommended settings for phase noise performance and power consumption DSPLL i m f Fin Divide By 3 Phase Digital Loo T E P gt Divide By NC1 Fout Divide By N2 four Fin N3 x 2 1 fuco Fin N3 x N2 Figure 21 Clock Multiplication Circuit e Rev 0 5 47 SILICON LABS Si53xx RM 5 2 PLL Performance All members of the Any Frequency Precision Clock family of devices provide extremely low jitter generation a well controlled jitter transfer function and high jitter tolerance For more information the loop bandwidth and its effect on jitter attenuation see Appendix H Jitter Attenuation and Loop BW on page 164
65. resolution of 1 fosc approximately 200 ps and a range from 25 6 to 25 4 ns Following powerup or reset RST pin or RST REG register bit the skew will revert to the reset value Any further changes made in the skew register will be read and compared to the previously held value The difference will be calculated and applied to the clock outputs All skew changes are made in a glitch free fashion When a phase adjustment is in progress any new CLATT 7 0 values are ignored until the update is complete The CLATPROG register bit is set to 1 during a coarse skew adjustment The time for an adjustment to complete is dependent on bandwidth and the delta value in CLAT To verify a written value into CLAT the CLAT register should be read after the register is written The time that it takes for the effects of a CLAT change to complete is proportional to the size of the change at 83 msec for every unit change assuming the lowest available loop bandwidth was selected For example if CLAT is zero and has the value 100 written to it the changes will complete in 100 x 83 msec 8 3 sec If it is necessary to set the high speed output clock divider N1 HS to divide by 4 in order to achieve the desired overall multiplication ratio and output frequency only phase increments are allowed and negative settings in the CLAT register or attempts to decrement the phase via writes to the CLAT register will be ignored Because of this restriction when there is a cho
66. set by the FRQSEL 1 0 pins as shown in Table 13 Table 13 Frequency Settings FRQSEL 1 0 Output Frequency MHz LL 19 38 22 28 LM 38 75 44 56 LH 77 50 89 13 ML 155 00 178 25 310 00 356 50 620 00 710 00 8 50 0 5 lt SILICON LABS Si53xx RM The 515316 can accept a CKIN1 input at a different frequency than the CKIN2 input The frequency of one input clock can be 1x 4x or 32x the frequency of the other input clock The output frequency is always equal to the lower of the two clock inputs and is set via the FRQSEL 1 0 pins The frequency applied at each clock input is divided down by a pre divider as shown in the Figure 1 on page 17 These pre dividers must be set such that the two resulting clock frequencies 1 and 2 must be equal and are set by the FRQSEL 1 0 pins Input divider settings are controlled by the CK1DIV and CK2DIV pins as shown in Table 14 Table 14 Input Divider Settings CKnDIV N3n Input Divider L 1 M 4 H 32 Table 15 Si5316 Bandwidth Values FRQSEL 1 0 Nominal Frequency Values MHz LL LM LH ML MM MH BW 1 0 19 44 MHz 38 88 MHz 77 76 MHz 155 52 MHz 311 04 MHz 622 08 MHz HM 100 Hz 100 Hz 100 Hz 100 Hz 100 Hz 100 Hz HL 210 Hz 210 Hz 200 Hz 200 Hz 200 Hz 200 Hz MH 410 Hz 410 Hz 400 Hz 400 Hz 400 Hz 400 Hz MM 1 7 kHz 1 7 kHz 1 6 kHz 1 6 kHz 1 6 kHz 1 6 k
67. te eed ats BA ode that TEUER 27 3 12 SD SOO tt A Pep a Rea 28 CEP 29 3 14 515374 75 Compared to 515324 19 29 d 15 9 Ad Ac o ALIE oe oa AC Adi Roa oda A abi OR 30 ZO 222 a abre Eo Lt a PME SAT cuf 31 4 Device Specifications i 5 cea cock hh prr aru 32 5 DSPEE All DEVICES Se we nim eem On ere d e a Ree 46 5 1 Clock 7 TP EMT 47 5 2 PEE Performante sce asta EA tert e rob X xt ar tette px drin os ee 48 5 2 Te Jitter Generation oso Dee Du eie nO Cie ud e RI datis m dd rie 48 52 2 Jitter Transtetec apy u umpu De nw Vg pde EG ep me 48 5 2 3 Jitter Tolerance xo d ERE Um NUR Pare ey She 49 6 Pin Control Parts 515316 515322 515323 515365 515366 50 6 1 Clock Multiplication 515316 515322 515323 515365 515366 50 6 1 1 Clock Multiplication 5 5316 50 6 1 2 Clock Multiplication 515322 515323 515365 515366 52 6 1 3 CKOUT3 CKOUT4 51
68. this board refer to the Si537x EVB Evaluation Board User s Guide Isolated Vdd s Main Vdd Isolated Vdd s The four Vdd supplies should be isolated from one another with four ferrite beads They should be separately bypassed with capacitors that are located very close to the Si537x device Figure 95 Vdd Plane m Use a solid and undisturbed ground plane for the Si537x and all of the clock input and output return paths m For applications that wish to logically connect the four RSTL_x signals do not tie them together underneath the BGA package Instead connect them outside of the BGA footprint m Where possible place the CKOUT and signals on separate PCB layers with a ground layer between them The use of ground guard traces between all clock inputs and outputs is recommended Rev 0 5 169 SILICON LABS Si53xx RM CKNIP A CKININ_A 2 _ CKWIP E CHI gt CKINZP_E CVM E CS CA B Lo IS eT eon T ez e C KINIMA CKINZN CVM IP d Jy OKINZP_E CkoUT2P CKOUTZN P ChOUTIP_E CKOUTIM E CKOVTZP E CKOUTZN E vbo_c ae 1 7 iour soon icon
69. this operating range The Si5368 input clock frequency and clock multiplication ratio are programmable through an I C or SPI interface The DSPLL loop bandwidth is digitally programmable from 60 Hz to 8 kHz providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5368 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 on page 76 for a complete description RATE 1 0 xB xa BYPASS DSBL2 3 CKIN D E N3 1 i 1 21 CKOUT_1 2 2 s RES CKOUT 1 CKIN 2 N3_2 fs 4 DSPLL fosc e CKOUT 2 KIN 3 2 AUN NL HS eNC2 77 E DSBL2 BYPASS CKIN 4 2 N3 4 gt 2 CKOUT 3 ENES 1 Lg s N2 DSBL34 CKOUT_2 gt FSYNC gt 21 CKOUT_4 CKIN 3 gt LOGIC CKOUT 4 p ALIGN Y eee CKIN 4 t ses 5 2 CKOUT 5 C2B FSYNC CKOUT 5 C3B 4 lL DSBL5 INT ALM lt Control C2A lt CS0 C3A lt gt 51
70. uw LO x 9 a lt lt q Z 8 9 co B amp B 3 S a S S S 5 Low Jitter Precision Clock Multipliers Wideband 515322 2 2 707 1050 0 6 ps rms typ e Si5325 2 2 710 1400 0 6 ps rms typ Si5365 4 5 707 1050 0 6 ps rms typ Si5367 4 5 710 1400 0 6 ps rms typ Notes 1 Maximum input and output rates may be limited by speed rating of device See each device s data sheet for ordering information 2 Requires external low cost fixed frequency 3rd overtone 114 285 MHz crystal or reference clock See Table 60 XA XB Reference Sources and Frequencies on page 119 SILICON LABS Rev 0 5 15 Si53xx RM 2 Narrowband vs Wideband Overview The narrowband NB devices offer a number of features and capabilities that are not available with the wideband WB devices as outlined in the below list Broader set of frequency plans due to more divisor options Hitless switching between input clocks Lower minimum input clock frequency Lower loop bandwidth Digital Hold reference based holdover instead of VCO freeze FRAMESYNC realignment CLAT and FLAT input to output skew adjust INC and DEC pins PLL Loss of Lock status indicator FOS is not supported 16 Rev 0 5 e SILICON LABS Si53xx RM 3 Any Frequency Clock Family Members 3 1 515316 The Si5316 is low jitte
71. x Band Marker Analysis Range Band Marker Intg Noise 74 5960 dBc 19 69 MHz 40 00 RMS Noise 263 46 urad 15 0952 RMS Jitter 268 358 fsec 50 00 Residual 1 51447 KHz 110 0 140 0 150 0 160 0 10 100 1k 10 100 1M 10M Figure 67 19 44 MHz In 156 25 MHz Out Loop BW 80 Hz 128 0 5 s SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz Carrier 156 250012 MHz 5 4246 dBm 0 000 gt 10 00 20 00 30 00 40 00 50 00 70 00 110 0 120 0 130 0 140 0 150 0 gt 1 12 2 20 MHZ x 12 Stop 20 center 10 Span 19 Noise Analysis Rang Analysis Rang Intg Noise 74 4433 dBc 19 69 MHz RMS Noise 2 d RMS Jitter 2 Residual Fih 131 4236 dBc Hz 154 7145 dBc Hz 972 kHz MHZ 005986 MHZ 988028 MHZ e x Band Marker e Y Band Marker 68 131 prad 5 3628 mdeg 73 116 fsec 1 51627 KHZ 160 0 45 100 1k 10 Figure 68 19 44 MHz In 156 25 MHz Out Loop BW 5 Hz Si5324 100 1 10M SILICON LABS Rev 0 5 129 Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 148 350000 MHz 5 0041 dBm 51 12 kHz 131 1295 dBc Hz 2 5 MHZ 154 6948 dBc Hz 10 00 Startle Stop 20 MHz A Center 10 006 MHz eU UU Span 19 988 MHz Noise Analysis Range Band Marker Analysis Range Band Marker Intg Noi
72. 0 128 256 64 111 256 512 128 CKOUT2 FS_OUT _CLKIN3RATE CKIN4 _CLKIN4RATE Y 1 Y I vI Typically the same frequency Clock select Figure 32 Frame Sync Frequencies 92 0 5 e SILICON LABS Si53xx RM The NC5 LS divider uses CKOUT2 as its clock input to derive FS_ OUT The limits for the NC5 LS divider are NC5 LS 1 2 4 6 219 ckoure 710 MHz Note that when in frame synchronization realignment mode writes to NC5 LS are controlled by FPW VALID See section 7 8 4 FS OUT Polarity and Pulse Width Control 515368 Common NC5 15 divider settings on F8 OUT are shown in Table 45 Table 45 Common 5 Divider Settings CKOUT2 Frequency MHz NC5 Divider Setting 2 kHz FS OUT 8 kHz FS OUT 19 44 9720 2430 77 76 38880 9720 155 52 77760 19440 622 08 311040 77760 7 8 1 FSYNC Realignment Si5368 The FSYNC ALIGN PIN bit determines if the realignment will be pin controlled via the FS ALIGN pin or register controlled via the FSYNC ALIGN REG register bit The active CKIN3 or CKIN4 edge to be used is controlled via the FSYNC POL register bit In either FSYNC alignment control mode the resolution of the phase realignment is 1 clock cycle of CKOUT2 If the realignment control is not active the NC5 divider will continuously divide down its fckour2 input This guarantees a fixed number of high frequency clock C
73. 150 0 160 0 a 1885 E 1 Figure 73 156 25 MHz In 155 52 MHz Out 134 0 5 lt SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz Carrier 644 531250 MHz 1 8744 dB 0 000 M 10 00 20 00 30 00 40 00 50 00 60 00 70 00 80 00 90 00 100 0 110 0 120 0 130 0 140 0 150 0 Start 100 Hz Stop 100 0009 MHz Center 50 0005 MHZ Span 100 0008 MHz Noise Analysis Range x Band Marker Analysis Range Y Band Marker Intg Noise 33 6883 dBc 40 MHz RMS Noise 29 2484 mrad 1 67581 deg RMS Jitter 7 22235 psec Residual FM 9 82748 kHz 160 0 100 1k 10k Figure 74 78 125 MHz In 644 531 MHz Out 1001 1 10 Table 63 Jitter Values for Figure 74 Jitter Bandwidth 644 531 MHz Jitter RMS Broadband 1 kHz to 10 MHz 223 fs OC 48 12 kHz to 20 MHz 246 fs OC 192 20 kHz to 80 MHz 244 fs OC 192 4 MHz to 80 MHz 120 fs OC 192 50 kHz to 80 MHz 234 fs Broadband 800 Hz to 80 MHz 248 fs 8 Rev 0 5 135 SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 pF Carrier 690 569197 MHz _ 0 5823 7 Start 100 Hz Stop 100 0009 MHz 10 00 Center 50 0005 MHz Span 100 0008 MHz Noise 0 00 Analysis Range X Band Marker Analysis Range Y Band Marker Intg Noise 36 4011 dBc 40 MHz 30 00 RMS Noise 21 4023 mrad 1 226826 deg RMS Jitter 4 93257 psec 40 00 Residu
74. 16 672 16 NA lt Rev 0 5 SILICON LABS Si53xx RM Table 16 SONET Clock Multiplication Settings FRQTBL L Continued No FRQSEL fin MHz Mult Factor Nominal All Devices 515366 Only ME four MHz F ours MHz FS OUT MHz CK CONF 0 CK CONF 1 28 MLLM 77 76 1 4 19 44 19 44 0 008 29 MLLH 1 2 38 88 38 88 0 008 30 MLML 1 77 76 77 76 0 008 31 MLMM 2 155 52 155 52 0 008 32 MLMH 2 255 238 166 63 166 63 33 MLHL 2 x 255 237 167 33 167 33 NA 34 MLHM 2 255 236 168 04 168 04 35 MLHH 4 311 04 311 04 0 008 36 MMLL 8 622 08 622 08 0 008 37 MMLM 8 x 255 238 666 51 666 51 NA 38 MMLH 8 x 255 237 669 33 669 33 NA 39 MMML 8 x 255 236 672 16 672 16 NA 40 155 52 1 8 19 44 19 44 0 008 41 MMMH 1 4 38 88 38 88 0 008 42 MMHL 1 2 77 76 77 76 0 008 43 1 155 52 155 52 0 008 44 MMHH e 255 238 166 63 166 63 NA 45 MHLL 255 237 167 33 167 33 NA 46 MHLM 255 236 168 04 168 04 NA 47 MHLH 2 311 04 311 04 0 008 48 MHML 4 622 08 622 08 0 008 49 MHMM 4 x 255 238 666 51 666 51 NA 50 MHMH 4 255 237 669 33 669 33 51 MHHL 4 x 255 236 672 16 672 16 NA 52 MHHM 166 63 238 255 155 52 155 52 NA 53 MMHM
75. 2 124 Figure 64 Jitter vs Reference Frequency 2 2 125 Figure 65 155 52 MHz In 622 08 MHz 126 Figure 66 155 52 MHz In 622 08 MHz Out Loop BW 7 Hz 515324 127 Figure 67 19 44 MHz In 156 25 MHz Out Loop BW 80 HZ 128 Figure 68 19 44 MHz In 156 25 MHz Out Loop BW 5 Hz 515324 129 Figure 69 27 MHz In 148 35 MHz Out Light Trace BW 6 Hz Dark Trace BW 110 Hz 515324 130 Figure 70 61 44 MHz In 491 52 MHz Out Loop BW 7 Hz 515324 131 Figure 71 622 08 MHz In 672 16 MHz Out Loop BW 6 9 KHz 132 Figure 72 622 08 MHz In 672 16 MHz Out Loop BW 100 HZ 133 Figure 73 156 25 MHz In 155 52 MHz 134 Figure 74 78 125 MHz In 644 531 MHz 135 Figure 75 78 125 MHz In 690 569 MHz 136 Figure 76 78 125 MHz Iri 693 493 MHz 137 Figure 77 86 685 MHz In 173 371 MHz and 693 493 MHz 138 Figure 78 86 685 MHz In 173 371 MHz 139 Figure 79 86 685 MHz In 693 493 MHz 140 Figure 80 155 52 MHz
76. 2 Jitter Values Fmod Fdev Jitter Start RF Gen 515326 515324 0 0 500 Hz 1 18 ps 283 fs 281 fs 50 Hz 50 Hz 10 Hz 181 ps 169 ps 10 6 ps 100 Hz 100 Hz 50 Hz 177 ps 136 ps 2 04 ps 500 Hz 500 Hz 100 Hz 175 ps 18 6 ps 295 fs 1 kHz 1 kHz 500 Hz 184 ps 4 28 ps 292 fs 5 kHz 5 kHz 500 Hz 138 ps 297 fs 302 fs 10 kHz 10 kHz 500 Hz 139 ps 302 fs 304 fs Notes 1 All phase noise plots are with 622 08 MHz input and 622 08 MHz output 515326 bandwidth 120 Hz 515324 bandwidth 7 Hz FM modulation at F Fmod with modulation amplitude Fdev Jit start is the start of the brick wall integration band All integration bands end at 50 MHz Phase noise measured by Agilent model E5052B RF Generator was Rohde and Schwarz model SMLO3 m RON 164 Rev 0 5 lt SILICON LABS Si53xx RM 622 08 MHz in 622 08 MHz out 0 00E 00 2 00E 01 4 00E 01 6 00E 01 8 00E 01 1 00E 02 Phase Noise dBc Hz 1 20E 02 1 40E 02 1 60E 02 1 80E 02 1 00E 01 1 00E 02 1 00E 03 1 00 04 1 00 05 1 00 06 1 00E 07 1 00E 08 Offset Frequency Hz Blue RF Generator Green Si5326 Red Si5324 Figure 88 RF Generator Si5326 Si5324 No Jitter For Reference 622 08 MHz in 622 08 MHz out 0 00E 00 2 00E 01 4 00E 01 6 00E 01 8 00E 01 1 00E 02 Phase Noise dBc Hz 1 20E 02 1 40E 02 1 60E 02
77. 2 Table 62 Jitter Values for Figure 62 123 Table 63 Jitter Values for Figure 74 135 Table 64 Jitter Values for Figure 75 136 Table 65 Jitter Values for Figure 76 137 Table 66 Jitter Values for Figure 77 138 Table 67 Jitter Values for Figure 80 141 Table 68 515316 147 Table 69 515322 Pullup DowWn 147 70 553293 P llup DOWN sacres reniei pena eni 148 Table 71 515319 515324 Pullup Down 148 Table 72 95925 PUlluUp DOWA ni uec Sl a usai cee teh RR ERI etus 149 Table 73 Si5326 Pullup Down RE EE Oe 149 Table 74 515327 Pullup DoWn 150 Table 75 SIS965 Pullip DONWEP turco tra Pia U era widens eaten ay wie tne ere 150 Table 76 515366 Pullup Down 151 Table 77 5193907 xi disni sss tae be Qa IRR 152 Table 78 515368 Pullup DOwn RR E ttr oo o EE eer ER EPA 152 Table 79 515369 Pullup Down 15
78. 2 are high speed input clocks from primary and secondary clock generation cards and CKIN3 and CKIN4 are their associated primary and secondary frame synchronization signals The device generates four output clocks and a frame sync output FS OUT and CKIN4 control the phase of FS OUT The frame sync inputs supplied to CKIN3 and CKIN4 must be 8 kHz Since the frequency of FS OUT is derived from CKOUT2 CKOUT2 must be a standard SONET frequency e g 19 44 MHz 77 76 MHz Table 16 lists the input frequency clock multiplication ratio combinations supporting an 8 kHz output on FS OUT 70 Rev 0 5 e SILICON LABS Si53xx RM 6 6 Output Phase Adjust Si5323 Si5366 Overall device skew CKINn to CKOUT_n phase delay is controllable via the INC and DEC input pins A positive pulse applied at the INC pin increases the device skew by 1 fogc one period of the DCO output clock A pulse on the DEC pin decreases the skew by the same amount Since fosc is close to 5 GHz the resolution of the skew control is approximately 200 ps Using the INC and DEC pins there is no limit to the range of skew adjustment that can be made Following a power up or reset the skew will revert to the reset value The INC pin function is not available for all frequency table selections DSPLLsim reports this whenever it is used to implement a frequency plan 6 6 1 FSYNC Realignment 515366 The FS ALIGN pin controls the realignment of FS OU
79. 20 80 at ured for CMOS See 622 08 MHz Figure 17 Output Rise Fall CMOS Output 1 8 ns 20 80 at Vpp 1 62 212 5 MHz Cload 5 pF CMOS Output 2 ns Vpp 2 97 Cload 5 pF Output Duty Cycle CKOpc 100 O Load 40 ps Differential Line to Line Uncertainty Measured at 50 Point not for CMOS 40 Rev 0 5 e SILICON LABS Si53xx RM Table 8 Characteristics All Devices Continued Parameter Symbol Test Condition amp 5 10 8 Ia Min Typ Max Units 0 0 0 0 0 W 0 LVCMOS Pins Input Capacitance Cin ele 3 pF Minimum Reset tRSTMN eje 1 us Pulse Width Reset to Micropro tReapy e e ee m 10 ms cessor Access Ready LVCMOS Output Pins LOSn Trigger From last CKIN n 7 ele 100 x 570x TcKIN Window to internal detection N3 N3 of LOSn From last CKIN_n T 0 8x 4 5 N3 Toxin to internal detection N3 LOSTRIG of LOSn N3 z 1 From last CKIN n T e e 250ns 45 Toxin to internal detection of LOSn N3 1 Time to Clear LOL timo YLOSto LOL e e 10 ms after LOS Cleared Assume Fold Fnew Stable XA XB reference e Rev 0 5 41 SILICON LABS
80. 238 255 622 08 622 08 NA 81 HMMH 1 666 51 666 51 NA e Rev 0 5 SILICON LABS 5153 Table 16 SONET Clock Multiplication Settings FRQTBL L Continued FRQSEL fin MHz Mult Factor Nominal All Devices 515366 Only four ours MHz FS OUT MHz CK CONF 0 CK CONF 1 82 HHLH 669 33 1 4x 237 255 155 52 155 52 NA 83 HMML 1 4 167 33 167 33 84 HHML 237 255 622 08 622 08 NA 85 HMMH e 1 669 33 669 33 NA 86 HHMM 672 16 1 4 x 236 255 155 52 155 52 NA 87 HMML 1 4 168 04 168 04 88 HHMH 236 255 622 08 622 08 NA 89 HMMH e 1 672 16 672 16 NA 56 0 5 e SILICON LABS Si53xx RM Table 17 Datacom Clock Multiplication Settings FRQTBL M CK_CONF 0 Setting FRQSEL 3 0 fin MHz Mult Factor four MHz 0 LLLL 15 625 2 31 25 1 LLLM 4 62 5 2 LLLH 8 125 3 LLML 16 250 4 LLMM 25 17 4 106 25 5 LLMH 5 125 6 LLHL 25 4 x 66 64 161 13 7 LLHM 51 8 x 66 64 164 36 8 LLHH 25 4 x 66 64 x 255 238 172 64 9 LMLL 25 4 x 66 64 x 255 237 173 37 10 LMLM 51 8 x 66 64 x 255 238 176 1 11 LMLH 51 8 x 66 64 x 255 237 176 84 12 LMML 17 2 212 5 13 LMMM 17 425 14 LMMH 25 x 66 64 644
81. 25 Si5367 The input to output skew for wideband devices is not controlled 7 1 3 Narrowband Parts 515319 515324 515326 515327 515368 515369 515374 515375 The DCO uses the reference clock on the XA XB pins 5 P and OSC_N for the 515374 515375 as its reference for jitter attenuation The XA XB pins support either a crystal oscillator or an input buffer single ended or differential so that an external oscillator can become the reference source In both cases there are wide margins in the absolute frequency of the reference input because it is a fixed frequency and is used only as a jitter reference and holdover reference see 7 6 Digital Hold on page 87 See Appendix A Narrowband References on page 119 for more details The Si5374 and Si5375 must be used with an external crystal oscillator and cannot use crystals Care must be exercised in certain areas for optimum performance For details on this subject refer to Appendix B Frequency Plans and Jitter Performance Si5316 515319 515323 515324 5 5326 Si5327 515366 Si5368 515369 515374 515375 on page 121 For examples of connections to the XA XB for the 515374 and Si5375 OSC_P OSC_N pins refer to 8 4 Crystal Reference Clock Interfaces 515316 515319 515323 515324 515326 515327 515366 515368 515369 515374 515375 on page 113 Refer Figure 26 Narrowband PLL Divider Settings 515319 515324 515326 515327 515368 515374 515375
82. 3 68 Table 28 Input Clock Priority for Auto Switching 515365 515366 69 Table 29 FS OUT Disable Control DBLFS 72 Table 30 Output Signal Format Selection 72 Table 31 DSBL2 BYPASS Pin Settings 73 Table 32 Frequency Offset Control 74 Table 33 Alarm Output Logic 74 Table 34 Lock Detect Retrigger 75 Table 35 Narrowband Frequency Limits 78 Table 36 Dividers and Limits 78 Table 37 ALWAYS SQ ICAL Truth Table 80 Table 38 Manual Input Clock Selection 515367 515368 515369 82 Table 39 Manual Input Clock Selection 515324 515325 515326 515374 83 Table 40 Automatic Manual Clock Selection 83 Table 41 Input Clock Priority for Auto Switching 84 10 Rev 0 5 SILICON LABS Si53xx RM Table 42 Digital Hold History 88 Table 43 Digital Hold History Averaging 88 Table 44 CKIN3 CKIN4 Freq
83. 3 515326 515327 515366 515368 515369 support a digitally programmable loop bandwidth that can range from 60 Hz to 8 4 kHz An external 37 41 MHz 55 61 MHz 109 125 5 MHz or 163 180 MHz reference clock or a low cost 114 285 MHz 3rd overtone crystal is required for these devices to enable ultra low jitter generation and jitter attenuation See Appendix A Narrowband References on page 119 The 515324 and Si5369 are much lower bandwidth devices providing a user programmable loop bandwidth from 4 to 525 Hz The 515323 515324 515326 515327 515366 515368 and 515369 support hitless switching between input clocks in compliance with GR 253 CORE and GR 1244 CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition 200 ps typ Manual automatic revertive and automatic non revertive input clock switching options are available The devices monitor the input clocks for loss of signal and provide a LOS alarm when missing pulses on any of the input clocks are detected The devices monitor the lock status of the PLL and provide a LOL alarm when the PLL is unlocked The lock detect algorithm works by continuously monitoring the phase of the selected input clock in relation to the phase of the feedback clock The 515326 515366 515368 and 515369 monitor the frequency of the input clocks with respect to a reference frequency applied to an input clock or the XA XB input and generates
84. 3 Table 80 Si5374 75 153 Table 81 Output Format vs 161 Table 82 ditter ValueS u E 164 Table 83 515374 75 Crosstalk Jitter Values 173 0 5 11 SILICON LABS Si53xx RM 1 Any Frequency Precision Clock Product Family Overview Silicon Laboratories Any Frequency Precision Clock products provide jitter attenuation and clock multiplication clock division for applications requiring sub 1 ps rms jitter performance The device product family is based on Silicon Laboratories 3rd generation DSPLL technology which provides any frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for discrete VCXO VCSOs and loop filter components These devices are ideally suited for applications which require low jitter reference clocks including OTN OTU 1 OTU 2 OTU 3 OTU 4 OC 48 STM 16 OC 192 STM 64 OC 768 STM 256 GbE 10GbE Fibre Channel 10GFC synchronous Ethernet wireless backhaul wireless point point infrastructure broadcast video HDTV HD SDI 3G SDI test and measurement data acquisition systems and FPGA ASIC reference clocking Table 1 provides a product selector guide for the Silicon Laboratories Any Frequency Precision Clocks Three product families are available The 515316 515319 515323 Si5324 51532
85. 326 As a method of reducing the lock time the FAST_LOCK register bit can be set to improve lock times As the Si5324 27 69 74 data sheets indicate FAST LOCK is the LSB of register 137 When FAST LOCK is high the lock time decreases Because the Si5324 27 74 is initialized with FAST_LOCK low it must be written before ICAL is set Typical Si5324 27 69 74 lock times as defined from the start of ICAL until LOL going low with FAST_LOCK set are one to two seconds To further reduce lock times it is also recommended that a value of 001 be written to LOCKT the three LSBs of register 19 7 2 2 Input Clock Stability during Internal Self Calibration An ICAL must occur when the selected active CKINn clock is stable in frequency and with a frequency value that is within the operating range that is reported by DSPLLsim The other CKINs must be stable in frequency lt 100 ppm from nominal or squelched during an ICAL 7 2 3 Self Calibration Caused by Changes in Input Frequency If the selected CKINn varies by 500 ppm or more in frequency since the last calibration the device may initiate a self calibration 7 2 4 Narrowband Input to Output Skew Si5319 515324 515326 515327 515368 515369 515374 515375 The input to output skew is not controlled External circuitry is required to control the input to output skew Contact Silicon Labs for further information 7 2 5 Clock Output Behavior Before and During ICAL Table 37 CKOUT ALWAYS ON and SQ ICAL
86. 5 DSPLL C 176 Rev 0 5 s SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 698 826126 MHz 2 5956 dBm 51 100 68 6425 dBc Hz Start 12 KHz 10 00 Stop 20 MHZ Center 10 006 MHz Span 19 988 MHz 20 00 Noise Analysis Range X Band Marker Analysis Range Y Band Marker 30 00 Intg Noise 59 7547 dBc 19 60 MHZ RMS Noise 1 45473 mrad 83 3499 mdeg 40 00 RMS Jitters 331 309 fsec Residual FM 3 85427 kHz 50 00 90 00 100 0 110 0 140 0 150 0 160 0 2 e 1k 10 100k 1M 10M Figure 102 515374 515375 DSPLL D s Rev 0 5 177 SILICON LABS Si53xx RM DOCUMENT CHANGE LIST Revision 0 3 to Revision 0 4 Updated AC Specifications in Table 8 AC Characteristics All Devices Added Si5365 Si5366 515367 and Si5368 operation at 3 3 V Updated Section 7 8 Frame Synchronization Realignment Si5368 and CK_CONFIG_REG 1 Added input clock control diagrams in Section 7 4 Input Clock Control Added new crystals into Table 59 Approved Crystals Updated Appendix D Alarm Structure on page 144 Added Appendix F Typical Performance Bypass Mode PSRR Crosstalk Output Format Jitter on page 154 Revision 0 4 to Revision 0 41 Added Si5324 Revision 0 41 to Revision 0 42 Moved Si5326 specifications to the Si5326 data sheet Corrected Figure 23 Jitter Tolerance Mask T
87. 515365 515366 73 6 9 2 FOS Alarms 515365 515366 73 6 9 3 FSYNC Align Alarm 515366 CONF 1 FRQTBL 0 74 6 9 4 C1B C2B Alarm Outputs 515316 515322 515323 74 6 9 5 C2B C3B ALRMOUT Outputs 515365 515366 74 6 10 Device Reset nsss tarda ie eI EO ey eee ee Ex 75 6 11 DSPLLsim Configuration Software 75 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 515367 Si5368 515369 515374 515375 76 7 1 Clock Multiplication esos 76 7 1 1 Jitter Tolerance 515319 515324 515325 515326 515327 515368 515369 515374 5 5375 76 7 1 2 Wideband Parts 515325 5 5367 7 76 7 1 3 Narrowband Parts 515319 515324 515326 515327 515368 515369 515374 5 375 77 7 1 4 Loop Bandwidth 515319 515326 515368 515375 79 7 1 5 Lock Detect 515319 515326 515327 515368 515369 515374 515375 79 7 2 PLL Self Calibration 79 7 2 1 Initia
88. 515368 515369 515374 515375 To facilitate automatic hitless switching the LOS trigger time can be significantly reduced by using the default LOS option LOSn_EN 11 The LOS circuitry divides down each input clock to produce a 2 kHz to 2 MHz signal The LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input clock transitions If the LOS monitor detects twice the normal number of samples without a clock edge an LOS alarm is declared The LOSn trigger window is based on the value of the input divider N3 The value of N3 is reported by DSPLLsim The range over which LOS is guaranteed to not produce false positive assertions is 100 ppm For example if a device is locked to an input clock on CKIN1 the frequency of CKIN2 should differ by no more than 100 ppm to avoid false LOS2 assertions The frequency range over which FOS monitoring may occur is from 10 to 710 MHz 7 11 1 3 LOSA 515319 515324 515326 515327 515368 515369 515374 515375 A slower response version of LOS called LOSA is available and should used under certain conditions Because LOSA is slower and less sensitive than LOS its use should be considered for applications with quasi periodic clocks e g gapped clocks with one or more consecutive clock edges removed when switching between input clocks with a large difference in frequency and any other application where false positive assertions of LOS
89. 5365 515366 64 6 1 4 Loop bandwidth 515316 515322 515323 515365 515366 64 6 1 5 Jitter Tolerance 515316 515323 515366 64 6 1 6 Narrowband Performance 515316 515323 515366 64 6 1 7 Input to Output Skew 515316 515323 515366 64 6 1 8 Wideband Performance 515322 515365 64 6 1 9 Lock Detect 515322 515365 64 6 1 10 Input to Output Skew 515322 and 5365 64 G2 PELSelt CalbraliGI Uh aration ar a CERCA 65 6 2 1 Input Clock Stability during Internal Self Calibration Si5316 515322 515323 515365 5366 65 6 2 2 Self Calibration caused by Changes Input Frequency Si5316 515322 515323 515365 5366 65 6 2 3 Recommended Reset Guidelines 515316 515322 515323 515365 515366 65 6 3 Pin Control Input Clock Control 67 Rev 0 5 3 SILICON LABS Si53xx RM 6 3 1 Manual Clock Selection i Pe wate gee belek eee adie nek RE 67 6 3 2 Automatic Clock Selection 515322 515323 515365 5366
90. 6 515366 and 515368 are jitter attenuating clock multipliers that provide ultra low jitter generation as low as 0 30 ps RMS The devices vary according to the number of clock inputs number of clock outputs and control method The Si5316 is a fixed frequency pin controlled jitter attenuator that can be used in clock smoothing applications The Si5323 and Si5366 are pin controlled jitter attenuating clock multipliers The frequency plan for these pin controlled devices is selectable from frequency lookup tables and includes common frequency translations for SONET SDH ITU G 709 Forward Error Correction FEC applications 255 238 255 237 255 236 238 255 237 255 236 255 Gigabit Ethernet 10G Ethernet 1G 2G 4G 8G 10G Fibre Channel ATM and broadcast video Genlock The 515319 515324 515326 515327 515368 and 515369 are microprocessor controlled devices that can be controlled via an 2 or SPI interface These microprocessor controlled devices accept clock inputs ranging from 2 kHz to 710 MHz and generate multiple independent synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz Virtually any frequency translation combination across this operating range is supported Independent dividers are available for every input clock and output clock so the 515324 515326 Si5327 515368 can accept input clocks at different frequencies and generate output clocks at different frequencies The 515316 515319 51532
91. 6 duty cycle setting would be used to generate a typical balanced output clock 94 Rev 0 5 lt SILICON LABS Si53xx RM 7 9 Output Clock Drivers 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 The device includes flexible output driver structure that can drive variety of loads including LVPECL LVDS CML and CMOS formats The signal format of each output is individually configurable through the SFOUTn_REG 2 0 register bits which modify the output common mode and differential signal swing Table 47 shows the signal formats based on the supply voltage and the type of load being driven For the CMOS setting both output pins drive single ended in phase signals and should be externally shorted together to obtain the maximum drive strength Table 47 Output Signal Format Selection SFOUTn 2 0 Signal Format 111 LVDS 110 CML 101 LVPECL 011 Low swing LVDS 010 CMOS 000 Disabled All Others Reserved The SFOUTn_REG 2 0 register bits can also be used to disable the outputs Disabling the outputs puts the CKOUT and CKOUT pins in a high impedance state relative to Vpp common mode tri state while the two outputs remain connected to each other through a 200 on chip resistance differential impedance of 200 The clock output buffers and DSPLL output dividers NCn are powered down in disable mode The additional functions of Hold Logic 1
92. B Reference 1200 1000 800 600 e 400 200 0 155 51 155 515 155 52 155 525 155 53 Input Frequency MHz Input Frequency Variation 50 ppm Figure 85 50 ppm 2 ppm Steps 162 Rev 0 5 SILICON LABS 5153 38 88 MHz External XA XB Reference 1200 1000 800 600 RMS jitter fs 400 200 155 49 155 5 155 51 155 52 155 53 155 54 155 55 Input Frequency MHz Input Frequency Figure 86 200 ppm 10 ppm Steps 38 88 MHz External XA XB Reference 1200 4 1000 800 600 RMS jitter fs 400 200 0 155 2 155 3 155 3 155 4 155 4 155 5 155 5 155 6 155 6 155 7 155 7 155 8 155 8 155 9 155 9 Input Frequency MHz Input Frequency Variation 2000 ppm Figure 87 2000 ppm 50 ppm Steps e Rev 0 5 163 SILICON LABS Si53xx RM APPENDIX H JITTER ATTENUATION AND Loop BW The following illustrates the effects of different loop BW values on the jitter attenuation of the Any Frequency devices The jitter consists of sine wave modulation at varying frequencies The RMS jitter values of the modulated sine wave input is compared to the output jitter of an 515326 and 515324 For reference the top entry in the table lists the jitter without any modulation For each entry in the table the corresponding phase noise plots are presented Table 8
93. Current liti See note LVCMOS Output Pins Output Voltage Low VoL lo 2 mA Vpp 1 62 V lo 2 mA Vpp 2 97 V Output Voltage High lp 2 2 mA Vpp 1 62 V lo 2 MA Vpp 2 97 V Tri State Leakage loz RST 0 Refer to Section 6 7 1 and 8 2 1 for restrictions on output formats for TQFP devices at 3 3 V 2 This is the amount of leakage that the 3L inputs can tolerate from an external driver See Figure 55 on page 115 3 No under or overshoot is allowed 36 Rev 0 5 e SILICON LABS Si53xx RM Table 5 DC Characteristics Microprocessor Devices Si5324 Si5325 Si5367 Si5368 Parameter Symbol Test Condition 2 Bus Lines SDA SCL Input Voltage Low Input Voltage High Input Current VIN 0 1 x Vpp to 0 9 x Hysteresis of Schmitt trig Vuysiec Vpp 1 8 V Vpp 2 5 or 9 3 V VoHI2C Vpp 1 8 V 3 mA Vpp 2 5or 3 3 V IO 2 3 mA Table 6 SPI Specifications 515324 Si5325 515367 and Si5368 Parameter Symbol Test Conditions Min Typ Max Unit Duty Cycle SCLK tpc SCLK 10 MHz 40 60 Cycle Time SCLK te 100 ns Rise Time SCLK t 20 80 25 ns Fall Time SCLK t 20 80 25 ns Low Time SCLK tisc 20 20 30 ns High Time SCLK thsc 80 80 30 ns Delay Time SCLK Fall to SDO A
94. ENDIX J Si5374 AND 515375 CROSSTALK While the four DSPLLs of the Si5374 and Si5375 are in close physical and electrical proximity to one another crosstalk interference between the DSPLLs is minimal The following measurements show typical performance levels that can be expected for the Si5374 and Si5375 when all four of their DSPLLs are operating at frequencies that are close in value to one another but not exactly the same 515374 515375 Crosstalk Test Bed All four DSPLLs share the same frequency plan m 38 88 MHz input m 38 88 MHz x 4080 227 698 81 MHz output rounded There are four slightly different input frequencies m DSPLLA 38 88 MHz 0 ppm gt 38 88000000 MHz m DSPLLB 38 88 MHz 1 ppm gt 38 88003888 MHz m DSPLLC 38 88 MHz 10 ppm gt 38 88038880 MHz m DSPLLD 38 88 MHz 20 ppm gt 38 88077760 MHz Table 83 Si5374 75 Crosstalk Jitter Values DSPLL Jitter fsec RMS A 334 B 327 358 D 331 OSC P OSC N Reference m 51530 at 121 109 MHz Test equipment m Agilent E5052B lt Rev 0 5 173 SILICON LABS Si53xx RM 16 0 000 10 00 40 00 50 00 90 00 110 0 140 0 150 0 bPhase Noise 10 00dB Ref 0 000dBc Hz Carrier 698 812232 MHzT 1 9312 dBm 51 100 Hz 60 9964 dBC Hz Start 12 kHz Stop 20 MHz Center 10 006 MHz Span 19 988 MHZ 158 Analysis Range Band Marker Analysis Range Y Band Marker
95. FLG Sticky I Waco FOS2 20 to clear FOSS INT FOSS Foss 2 to clear A FOS4 INT FOS4 FLG S 1 Sticky FOS4 MSK Write 0 u s to clear ALIGN_INT Stick ALIGN FLG Sticky 1 ee ER ALIGN xL to clear LOL INT Se LOL FLG Sticky Write 0 LOL MSK g to clear WIDEBAND MODE gt To Next Page LOS4 EN CK BAD POL CKIN4 LOS k w LOS4 INT CK CONFIG REG Detector de ES INT_ALM ALIGN INT E 4 ALIGN INT t a 9 PEL LL FOS Ad UN Detector 2 1 J 7 FOS4 EN INT_PIN FOS ALRMOUT PIN J Figure 83 Si5368 Alarm Diagram 1 of 2 Rev 0 5 145 SILICON LABS Si53xx RM 1053 EN CKIN3 105 N 1053 INT Detector Jede PD gt Fos A Detector l 2 53 5 LOSI LOS LOS1 INT Detector E PD p _ DE gt E E FOS Detector l 2 A x FOSI EN FOS EN CK CONFIG REG FSYNC SWTCH REG LOS2 EN xj 1054 INT CKIN2 LOS ES S LOS2 INT Detector jeu PD CK2 gt FOS Detector FOS2 EN FOS E
96. FRQSEL1 Yes 26 N A FRQSEL2 FRQSEL2 Yes 27 N A FRQSEL3 FRQSEL3 Yes 30 SFOUT1 N A SFOUT1 No but skew not guaranteed without Reset 33 SFOUTO N A SFOUTO No but skew not guaranteed without Reset Table 21 Si5365 and Si5366 Pins and Reset Pin Si5365 Pin Name Si5366 Pin Name Must Reset after Changing 4 FRQTBL FRQTBL Yes 32 N A RATE 0 Yes 42 N A RATE 1 Yes 51 N A CK CONF Yes 54 DEC No 55 N A INC No 60 BWSELO BSWELO Yes 61 BWSEL1 BWSEL1 Yes 66 DIV34_0 DIV34_0 Yes 67 DIV34_1 DIV34 1 Yes 68 FRQSELO FRQSELO Yes 69 FRQSEL1 FRQSEL1 Yes 70 FRQSEL2 FRQSEL2 Yes 71 FRQSEL3 FRQSEL3 Yes 80 N A SFOUT1 No but skew not guaranteed without Reset 95 N A SFOUTO No but skew not guaranteed without Reset 66 0 5 lt SILICON LABS Si53xx RM 6 3 Pin Control Input Clock Control This section describes the clock selection capabilities manual input selection automatic input selection hitless switching and revertive switching When switching between two clocks LOL may temporarily go high if the two clocks differ in frequency by more than 100 ppm 6 3 1 Manual Clock Selection Manual control of input clock selection is chosen via the CS 1 0 pins according to Table 22 and Table 23 Table 22 Manual Input Clock Selection Si5316 Si5322 Si5323 AUTOSEL L CS Si5316 515316 515322 515323 5 515322 515323 0 CKIN1 1 CKIN2 The manual input clock selection settings for the Si5365 and the Si5366
97. G The resolution of the phase adjustment is equal to NI HS Fycol Since Fyco is approximately 5 GHz and N1_HS 4 5 6 11 the resolution varies from approximately 800 ps to 2 2 ns depending on the PLL divider settings Silicon Laboratories PC based configuration software DSPLLsim provides PLL divider settings for each frequency translation if applicable If more than one set of PLL divider settings is available selecting the combination with the lowest N1 HS value provides the finest resolution for output clock phase offset control The INDEPENDENT SKEWn 7 0 n 1 to 5 register bits control the phase of the device output clocks By programming a different phase offset for each output clock output to output delays can easily be set 7 7 4 Output to output Skew 515324 515326 515327 515368 515369 515374 The output to output skew is guaranteed to be preserved only if the following two register bits are both high Register Bit Location CKOUT_ALWAYS_ON addr 0 bit 5 SQICAL addr 3 bit 4 In addition if SFOUT is changed the output to output skew may be disturbed until after a successful ICAL Note CKOUT5 phase is random unless it is used for Frame Sync See section 7 8 7 7 5 Input to Output Skew All Devices The input to output skew for these devices is not controlled 7 8 Frame Synchronization Realignment Si5368 and CK_CONFIG_REG 1 Frame Synchronization Realignment is selected by setting CK_CONFIG_LREG 1
98. Hz ML 7 0 kHz 7 0 kHz 6 8 kHz 6 7 kHz 6 7 kHz 6 7 kHz Figure 24 Si5316 Divisor Ratios One to one frequency ratio SILICON LABS Rev 0 5 51 Si53xx RM 6 1 2 Clock Multiplication Si5322 Si5323 Si5365 Si5366 These parts provide flexible frequency plans for SONET DATACOM and interworking between the two Table 16 Table 17 and Table 18 respectively The CKINn inputs must be the same frequency as specified in the tables The outputs are the same frequency however in the 515365 and 515366 CKOUT3 and CKOUT4 can be further divided down by using the DIV34 1 0 pins The following notes apply to Tables 16 17 and 18 All entries are available for the 515323 and 515366 Only those marked entries under the WB column are 1 available for the Si5322 and Si5365 2 The listed output frequencies appear on CKOUTn For the Si5365 and Si5366 sub multiples are available on CKOUT3 CKOUTA using the DIV34 1 0 control pins 3 All ratios are exact but the frequency values are rounded 4 For bandwidth settings f8 values and frequency operating ranges consult DSPLLsim 5 For the 515366 with CK CONF 1 CKIN3 and CKIN4 are the same frequency as FS OUT Table 16 SONET Clock Multiplication Settings FRQTBL L FRQSEL MHz Mult Factor Nominal All Devices Si5366 Only a four ours MHz F
99. INT OR FOS1 INT AND LOS2 INT OR FOS2 INT AND LOS3 INT OR FOS3 INT AND LOS4 INT OR 54 INT enter digital hold 7 6 1 1 Digital Hold Detailed Description 515324 515326 515327 515368 515369 515374 In this mode the device provides a stable output frequency until the input clock returns and is validated Upon entering digital hold the internal DCO is initially held to its last frequency value M See Figure 30 Next the DCO slowly transitions to a historical average frequency value supplied to the DSPLL Myjs7 as shown in Figure 30 Values of M starting from time t HI ST DEL HIST and ending at t H ST DEL are averaged to compute Mp st This historical average frequency value is taken from an internal memory location that keeps a record of previous M values supplied to the DCO By using a historical average frequency input clock phase and frequency transients that may occur immediately preceding digital hold do not affect the digital hold frequency Also noise related to input clock jitter or internal PLL jitter is minimized Digital Hold HIST DEL t 0 HIST AVG Time Figure 30 Parameters History Value of The history delay can be set via the HIST DEL 4 0 register bits as shown in Table 42 and the history averaging time be set via the H ST AVG 4 0 register bits as shown in Table 43 The DIGHOLDVALID register be used to determine if the information in HIST is valid a
100. In a typical frame synchronization application CKIN1 and CKIN2 are high speed input clocks from primary and secondary clock generation cards and CKIN3 and CKIN4 are their associated primary and secondary frame synchronization signals The device generates four output clocks and a frame sync output FS_OUT CKIN3 and CKIN4 control the phase of FS OUT When CK_CONFIG_REG 1 the Si5368 can lock onto only CKIN1 CKIN2 CKIN3 and CKIN4 are used only for purposes of frame synchronization The inputs supplied to CKIN3 and CKIN4 can range from 2 to 512 kHz So that two different frame sync input frequencies can be accommodated CKIN3 and CKIN4 each have their own input dividers as shown in Figure 32 CKIN3 and CKIN4 frequencies are set by the CKINSRATE 2 0 and CKINA4RATE 2 0 register bits as shown in Table 44 The frequency of FS OUT can range from 2 kHz to 710 MHz and is set using the NC5 LS divider setting OUT must divide evenly into CKOUT2 For example if CKOUT2 is 156 25 MHz then 8 kHz would not be an acceptable frame rate because 156 25 MHz 8 kHz 19 531 25 which is not an integer However 2 kHz would be an acceptable frame rate because 156 25 MHz 2 kHz 78 125 lt Rev 0 5 91 SILICON LABS 5153 Table 44 CKIN3 CKIN4 Frequency Selection 1 CKLNnRATE 2 0 CKINn Frequency kHz Divisor 000 2 4 1 001 4 8 2 010 8 16 4 011 16 32 8 100 32 64 16 101 64 128 32 11
101. Intg Noise 59 6726 dBc 19 69 MHz RMS Noise 1 46855 mrad 84 1415 mdeg RMS Jitter 334 462 fsec Residual FM 7 87761 kHz 1k 101 100k 1M 10M Figure 99 515374 515375 DSPLL 174 Rev 0 5 s SILICON LABS Si53xx RM 0 000 Py bPhase Noise 10 00dB Ref 0 000 Carrier 698 812944 MHz 2 7405 dBm 10 00 40 00 50 00 90 00 110 0 140 0 150 0 gt 1 100 Hz 52 5444 dBC Hz Start 12 kHz Stop 20 MHz Center 10 006 MHz Span 19 988 MHz Noise Analysis Range x Band Marker Analysis Range Y Band Marker Intg Noise 59 8581 dBc 19 69 MHz RMS Noise 1 4375 mrad 82 3628 RMS Jitters 327 392 fsec Residual 3 86292 kHz 160 0 PS 1k 10k 100 1 Figure 100 515374 515375 DSPLL 10 SILICON LABS Rev 0 5 175 Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 698 819214 MHz 2 8823 dBm 100 2 55 7982 dBC Hz Start 12 KHz 10 00 Stop 20 MHZ Center 10 006 MHz Span 19 988 MHZ 20 00 Noise Analysis Range Band Marker Analysis Range Y Band Marker 30 00 Intg Noise 59 0730 dBc 19 60 MHz RMS Noise 1 5735 mrad 90 155 mdeg 40 00 RMS 3itter 358 362 fsec Residual FMi 7 73943 kHz 50 00 90 00 100 0 110 0 20 0 30 0 140 0 150 0 160 0 4 1 10 100 1M 10M Figure 101 515374 Si537
102. KOUT2 cycles between each FS OUT cycle At power up the device automatically performs a realignment of OUT using the currently active sync input After this as long as the PLL remains in lock and a realignment is not requested FS OUT will include a fixed number of high speed clock cycles even if input clock switches are performed If many clock switches are performed in phase build out mode it is possible that the input sync to output sync phase relationship will shift due to the accumulated residual phase transients of the phase build out circuitry The ALIGN ERR 8 0 status register reports the deviation of the input to output sync phase skew from the desired FSYNC_SKEW 16 0 value in units of fckoure periods A programmable threshold to trigger the ALIGN INT alarm can be set via the ALIGN THHR 2 0 bits whose settings are given in Table 46 If the sync alignment error exceeds the threshold in either the positive or negative direction the alarm becomes active If it is then desired to reestablish the desired input to output sync phase relationship a realignment can be performed A realignment request may cause FS OUT to instantaneously shift its output edge location in order to align with the active input sync phase Table 46 Alignment Alarm Trigger Threshold ALIGN 2 0 Alarm Trigger Threshold Units of Tckour2 000 4 001 8 010 16 011 32 100 48 101 64 110 96 111 128 e Rev
103. LICON LABS Si53xx RM Si53xx CKIN CML TO 3000 LVDS 100 0 2 Driver 40 Vicm gt CMOS Driver Voo Voo R3 150 ohms Vicm C1 R5 40 kohm 33 ohms See Table 150 ohms Vpop R2 Notes 3 3V 100 ohm Locate R1 near CMOS driver 2 5V 49 9 ohm Locate other components near Si5317 1 8V 14 7 ohm Recalculate resistor values for other drive strengths Additional Notes 1 Attenuation circuit limits overshoot and undershoot 2 Not to be used with non square wave input clocks Figure 41 CMOS Termination 1 8 2 5 3 3 V 106 Rev 0 5 e SILICON LABS Si53xx RM 8 2 Output Clock Drivers The output clocks can be configured to be compatible with LVPECL CML LVDS or CMOS as shown in Table 56 Unused outputs can be left unconnected For microprocessor controlled devices it is recommended to write disable to SFOUTn to disable the output buffer and reduce power When the output mode is CMOS bypass mode is not supported Table 56 Output Driver Configuration Output Mode SFOUTn Pin Settings SFOUTn HEG 2 0 Settings 515316 Si5322 515323 515365 515319 515325 515326 515327 515367 515368 515369 515374 515375 LVDS HM 111 CML HL 110 LVPECL MH 101 Low swing ML 011 LVDS CMOS LH 010 Disabled LM 000 Reserved All Others All Others Note The LVPECL outputs are LVPECL compatible
104. MMM 31875 31104 x 66 704 38 64 x 255 238 lt Rev 0 5 63 SILICON LABS Si53xx RM 6 1 3 CKOUT3 and CKOUT4 Si5365 and Si5366 Submultiples of the output frequency on CKOUT1 and CKOUT2 can be produced on the CKOUT3 and CKOUT4 outputs using the DIV34 1 0 control pins as shown in Table 19 Table 19 Clock Output Divider Control DIV34 DIV34 1 0 Output Divider Value HH 32 HM 16 HL 10 MH 8 MM 6 ML 5 LH 4 LM 2 LL 1 6 1 4 Loop bandwidth Si5316 Si5322 Si5323 Si5365 515366 The loop bandwidth BW is digitally programmable using the BWSEL 1 0 input pins The device operating frequency should be determined prior to loop bandwidth configuration because the loop bandwidth is a function of the phase detector input frequency and the PLL feedback divider setting Use DSPLLsim to calculate these values automatically This utility is available for download from www silabs com timing 6 1 5 Jitter Tolerance 515316 Si5323 515366 Refer to 5 2 3 Jitter Tolerance on page 49 6 1 6 Narrowband Performance 515316 515323 515366 The DCO uses the reference clock on the XA XB pins as its reference for jitter attenuation The XA XB pins support either a crystal oscillator or an input buffer single ended or differential so that an external oscillator can be used as the reference source The reference source is chosen with the RATE 1 0 pins In both cases there are wide margins
105. N ws Figure 84 Si5368 Alarm Diagram 2 of 2 CK BAD POL C3B E gl 5 E 4 ss 2 gt amp 3 5 C2B amp 3 5 146 Rev 0 5 ay SILICON LABS Si53xx RM APPENDIX E INTERNAL PULLUP PULLDOWN BY PIN Tables 68 79 show which 2 Level CMOS pins have pullups or pulldowns Note the value of the pullup pulldown resistor is typically 75 kQ Table 68 Si5316 Pullup Down Pin Si5316 Pull 1 RST U 11 RATEO U D 14 DBL2 BY U D 15 RATE1 U D 21 5 U D 22 BWSELO U D 23 BWSEL1 U D 24 FRQSELO U D 25 FRQSEL1 U D 26 CK1DIV U D 27 CK2DIV U D 30 SFOUT1 U D 33 SFOUTO U D Table 69 Si5322 Pullup Down Pin i5322 Pull 1 RST U 2 FRQTBL U D AUTOSEL U D 14 DBL2_BY U D 21 5_ U D 22 BWSELO U D 23 BWSEL1 U D 24 FRQSELO U D 25 FRQSEL1 U D 26 FRQSEL2 U D 27 FRQSEL3 U D 30 SFOUT1 U D 33 SFOUTO U D e Rev 0 5 147 SILICON LABS 5153 Table 70 515323 Pullup Down Pin 515323 Pull 1 RST U 2 FRQTBL U D 9 AUTOSEL U D 11 RATEO U D 14 DBL2 BY U D 15 RATE1 U D 19 DEC D 20 INC D 21 CS CA U D 22 BWSELO U D 23 BWSEL1 U D 24 FRQSELO U D 25 FRQSEL1 U D 26 FRQSEL2 U D 27 FRQSEL3 U D
106. N LABS Si53xx RM Reference vs Output Frequency Because of internal coupling output frequencies that are an integer multiple or close to an integer multiple of the XA XB reference frequency either internal or external should be avoided Figure 62 illustrates this by showing a 38 88 MHz reference being used to generate both a 622 08 MHz output which is an integer multiple of 38 88 MHz and 696 399 MHz which is not an integer multiple of 38 88 MHz Notice the mid band spurs on the 622 08 MHz output which contribute to the RMS phase noise for the SONET jitter masks Their effect is more pronounced for the broadband case For more information on this effect see Appendix G Near Integer Ratios on page 162 155 52 MHz in 622 08 MHz out 696 399 MHz out 20 40 60 80 100 Phase Noise dBc Hz 120 140 160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency Hz Yellow 696 399 MHz output Blue 622 08 MHz output Figure 62 Reference vs Output Frequency Table 62 Jitter Values for Figure 62 696 399 MHz Out 622 08 MHz Out Jitter Bandwidth Yellow fs RMS Blue fs RMS SONET_OC48 12 kHz to 20 MHz 379 679 SONET_OC192_A 20 kHz to 80 MHz 393 520 SONET OC192 B 4 MHz to 80 MHz 210 191 SONET OC192 C 50 kHz to 80 MHz 373 392 Broadband 800 Hz to 80 MHz 484 1 196 The crystal frequency of 114 285 MHz was picked for its lack
107. No DC biasing circuitry is required to drive a standard LVPECL load 8 2 1 LVPECL TQFP Output Signal Format Restrictions at 3 3 V Si5367 Si5368 Si5369 The LVPECL and CMOS output formats draw more current than either LVDS or CML however there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3 3 V When Vdd 3 3 V and there are four enabled LVPECL or CMOS outputs the fifth output must be disabled When Vdd 3 3 V and there are five enabled outputs there can be no more than three outputs that are either or CMOS All other configurations are valid including those with Vdd 2 5 V 8 2 2 Typical Output Circuits It is recommended that the outputs be ac coupled to avoid common mode issues This suggestion does not apply to the 515366 Sib368 when CKOUTS is configured as FS OUT frame sync because it can a have a duty cycle significantly different from 50 Si53xx ZO 50 9 100 Q 70 500 Revr Figure 42 Typical Output Circuit Differential lt Rev 0 5 107 SILICON LABS Si53xx RM Si53xx 100 800 All resistors located next to RCVR 100 Revr Figure 43 Differential Output Example Requiring Attenuation Optionally Tie CKOUTn Outputs Together for Greater Strength Figure 44 Typical CMOS Output Circuit Tie CKOUTn and
108. Noise Rejection Power Supply Noise to Output Transfer Function 1 10 100 1000 2 38 88 MHz in 155 52 MHz out Bandwidth 110 Hz Rev 0 5 SILICON LABS 155 5153 Clock Input Crosstalk Results Test Conditions Jitter Band 155 52 MHz 155 521 MHz in 155 521 MHz in 155 521 MHz 155 521 MHz in 622 MHz out 622 084 MHz 622 084 MHz 622 084MHz 622 084 MHz For reference out out out out No crosstalk No crosstalk 155 52 MHz 155 52 MHz 155 52 MHz Xtalk Xtalk Xtalk 99 Hz loop 6 72 kHz loop In digital hold Bandwidth Bandwidth OC 48 262 fs 262 fs 269 fs 422 fs 255 fs 12 kHz to 20 MHz OC 192 287 fs 290 fs 296 fs 366 fs 280 fs 20 kHz to 80 MHz Broadband 285 fs 289 fs 298 fs 1 010 fs 27T fs 800 Hz to 80 MHz Measurement conditions 1 Using Si5365 66 EVB 2 Clock input on CKIN1 OdBm sine wave from Rohde and Schwarz RF Generator model SMLOS 3 Crosstalk interfering signal applied to CKIN3 a PECL output at 155 52 MHz 4 All differential AC coupled signals 156 Rev 0 5 SILICON LABS Si53xx RM Clock Input Crosstalk Phase Noise Plots 155 521 MHz in 622 084 MHz out Phase Noise dBc Hz 100 1000 10000 100000 1000000 10000000 Offset Frequency Hz 100000000 Dark blue No crosstalk Light blue With crosstalk low bandwidth Yellow With crosstalk high bandwidth Red
109. O circuitry uses the external supply voltage directly Figure 57 shows a typical power supply bypass network for the TQFP packages Figure 58 shows a typical power supply bypass network for QFN In both cases the center ground pad under the device must be electrically and thermally connected to the ground plane System Power Queso Supply 1 8 2 5 or Ferrite 1 0 uF 3 3 V Bead Ferrite bead is Venkel BC1206 471H or equivalent Vop GND TQFP PKG Figure 57 Typical Power Supply Bypass Network TQFP Package System um C Powerz 4 Supply Ferrite 1 0 UF 1 8 2 5 or Bead C 3 3 V Ferrite bead is Venkel BC1206 471H or equivalent Figure 58 Typical Power Supply Bypass Network QFN Package e Rev 0 5 117 SILICON LABS Si53xx RM 10 Packages and Ordering Guide Refer to the respective data sheet for your device packaging and ordering information 118 Rev 0 5 e SILICON LABS Si53xx RM APPENDIX A NARROWBAND REFERENCES Resonator External Clock Selection Table 59 shows the 114 285 MHz third overtone crystals that have been approved for use with the Si53xx jitter attenuating clocks Table 59 Approved Crystals Manufacturer Part Number Web Site Stability Initial Accuracy TXC 7MA1400014
110. Pin Control Parts 515316 515322 515323 515365 515366 These parts provide high performance clock multiplication with simple pin control Many of the control inputs are three levels High Low and Medium High and Low are standard voltage levels determined by the supply voltage Vpp and Ground If the input pin is left floating it is driven to nominally half of Vpp Effectively this creates three logic levels for these controls These parts span a range of applications and I O capacity as shown in Table 12 Table 12 Si5316 515322 Si5323 515365 and 515366 Key Features Si5316 Si5322 Si5323 515365 515366 SONET Frequencies e DATACOM Frequencies DATACOM SONET internetworking e E e Fixed Ratio between input clocks Flexible Frequency Plan Number of Inputs 2 2 2 4 4 Number of Outputs 1 2 2 5 5 Jitter Attenuation e 6 1 Clock Multiplication 515316 515322 515323 515365 515366 By setting the tri level FRQSEL 3 0 pins these devices provide a wide range of standard SONET and data communications frequency scaling including simple integer frequency multiplication to fractional settings required for coding and decoding 6 1 1 Clock Multiplication Si5316 The device accepts dual input clocks in the 19 39 78 155 311 or 622 MHz frequency range and generates a de jittered output clock at the same frequency The frequency range is
111. Ri DSPLL fsc 2 CKOUT_1 2 CKOUT_1 INT Signal C2B Detect LIN 2 y gt CKOUT 24 CKOUT 2 N2 2 LOL CS CA lt CMODE SDA 500 4 SCL SDI Control 2 55 1 0 VDD DEC RST GND Figure 5 Si5324 Clock Multiplier and Jitter Attenuator Block Diagram e Rev 0 5 21 SILICON LABS Si53xx RM 3 6 Si5325 The Si5325 is a low jitter precision clock multiplier for applications requiring clock multiplication without jitter attenuation The 515325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The Si5325 input clock frequency and clock multiplication ratios are programmable through an 2 or SPI interface The DSPLL loop bandwidth is digitally programmable from 150 kHz to 1 3 MHz Operating from a single 1 8 2 5 or 3 3 V supply the 515325 is ideal for providing clock multiplication in high performance timing applications See 7 Microprocessor Controlled Parts 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 on page 76 for a complete description 0 CKIN 1 2
112. S OUT MHz CK CONF 0 CK CONF 1 0 LLLL 0 008 1 0 008 0 008 0 008 1 LLLM 2430 19 44 19 44 0 008 2 LLLH 4860 38 88 38 88 0 008 3 LLML 9720 77 76 77 76 0 008 4 LLMM 19440 155 52 155 52 0 008 5 LLMH 38880 311 04 311 04 0 008 6 LLHL 77760 622 08 622 08 0 008 52 0 5 e SILICON LABS Si53xx RM Table 16 SONET Clock Multiplication Settings FRQTBL L Continued FRQSEL fin MHz Mult Factor Nominal All Devices 515366 Only four ours MHz FS OUT MHz CK CONF 0 CK CONF 1 7 LLHM 19 44 1 19 44 19 44 0 008 8 LLHH 2 38 88 38 88 0 008 9 LMLL 4 77 76 77 76 0 008 10 LMLM e 8 155 52 155 52 0 008 11 LMLH 8 x 255 238 166 63 166 63 NA 12 LMML 8 x 255 237 167 33 167 33 NA 13 LMMM 8 x 255 236 168 04 168 04 NA 14 LMMH 16 311 04 311 04 0 008 15 LMHL 32 622 08 622 08 0 008 16 LMHM 32 x 255 238 666 51 666 51 NA 17 LMHH 32 x 255 237 669 33 669 33 NA 18 LHLL 32 x 255 236 672 16 672 16 NA 19 LHLM 48 933 12 933 12 0 008 20 LHLH 54 1049 76 1049 76 0 008 21 LHML 38 88 1 38 88 38 88 0 008 22 LHMM 2 77 76 77 76 0 008 23 LHMH 4 155 52 155 52 0 008 24 LHHL 16 622 08 622 08 0 008 25 LHHM 16 255 238 666 51 666 51 26 LHHH 16 x 255 237 669 33 669 33 NA 27 MLLL 16 x 255 236 672
113. Skew Control 5 5368 1 94 7 8 3 Including FSYNC Inputs in Clock Selection 515368 94 7 8 4 FS OUT Polarity and Pulse Width Control 815368 94 7 8 5 Using FS OUT as a Fifth Output Clock 515368 94 7 9 Output Clock Drivers 515319 515324 Si5325 515326 515327 515367 515368 515369 515374 515375 95 7 9 1 Disabling CKOLTn kz dade PER dg We PER EE 95 7 9 2 LVPECL TQFP Output Signal Format Restrictions at 3 3 V 515367 515368 Si5369 95 7 10 PLL Bypass Mode Si5319 Si5324 Si5325 515326 Si5327 515367 515368 515369 515374 515375 96 7 11 Alarms 515319 515324 515325 515326 515327 515367 Si5368 Si5369 Si5374 515375 96 7 11 1 Loss of Signal Alarms Si5319 Si5324 Si5325 Si5326 Si5327 515367 515368 515369 515374 515375 96 7 11 2 FOS Algorithm 515324 515325 515326 515368 515369 515374 97 7 11 3 2 515319 515324 515325 515326 515327 515374 515375 99 7 11 4 LOS SiB319 SiB375 ea per ox Sua 99 7 11 5 C1B C2B ALRMOUT 515367 515368 515369 CK CONFIG REG 0 99 7 11 6
114. T to the active CKIN3 or CKIN4 input The currently active frame sync input is determined by which input clock is currently being used by the PLL For example if CKIN1 is being selected as the PLL input CKIN3 is the currently active frame sync input If neither CKIN3 or CKIN4 are currently active digital hold the realignment request is ignored The active edge used for realignment is the or CKIN4 rising edge FS ALIGN operates in Level Sensitive mode See Figure 19 Frame Synchronization Timing While 5 ALIGN is active each active edge of the currently active frame sync input CKIN3 or CKIN4 is used to control the NC5 output divider and therefore the FS OUT phase Note that while the realignment control is active it cannot be guaranteed that a fixed number of high frequency clock CKOUT2 cycles exists between each FS OUT cycle The resolution of the phase realignment is 1 clock cycle of CKOUT2 If the realignment control is not active the NC5 divider will continuously divide down its fc oure input This guarantees a fixed number of high frequency clock CKOUT2 cycles between each FS OUT cycle At power up or any time after the PLL has lost lock and relocked the device automatically performs a realignment of FS OUT using the currently active sync input After this as long as the PLL remains in lock and a realignment is not requested FS OUT will include a fixed number of high speed clock cycles even if input clock switches
115. a br RR ons we 110 Figure 47 sfout 3 5 110 Fig re 48 sfout 5 LVPEGL iu usa hak ee eee 111 OM ce te dy nra Crap rap ad 111 Figure ENERO toned oL pats AD 112 Figure 51 CMOS External Reference Circuit 113 Figure 52 Sinewave External Clock 113 Figure 53 Differential External Reference Input Example Not for 515374 or 515375 114 Figure 54 Differential OSC Reference Input Example for 515374 and 515375 114 Figure 55 Three Level Input 115 Figure 56 Three Level Input PinSs 116 Figure 57 Typical Power Supply Bypass Network TQFP Package 117 Figure 58 Typical Power Supply Bypass Network QFN Package 117 Figure 59 Typical Reference Jitter Transfer Function 120 Fig re OO SING VS Lecce ess wee tnt dei sd un box rd a ace te 121 Figure 61 Jitter vs f3 with FPGA d ra mee E PE ure oe 122 Figure 62 Reference vs Output 123 Figure 63 Jitter vs Reference Frequency 1
116. ables FOS C2B LOS2 INT or LOS4 INT and FSYNC SWTCH REG C3B tri state ALRMOUT ALIGN INT 1 1051 INT or LOSS INT FSYNC SWTCH or FOS1 INT C2B LOS2 INT or LOS4 INT and FSYNC_SWTCH_REG or FOS2 INT C3B tri state ALRMOUT ALIGN INT 7 11 7 LOS Algorithm for Reference Clock Input Si5319 515324 515326 515327 515368 515369 515374 Si5375 The reference clock input on the XA XB port is monitored for LOS The LOS circuitry divides the signal at XA XB by 128 producing a 78 kHz to 1 2 MHz signal and monitors the signal for LOS using the same algorithm as described in Section 7 11 1 Loss of Signal Alarms 515319 515324 Si5325 515326 515327 Si5367 515368 515369 515374 515375 The LOSX INT read only bit reflects the state of a loss of signal monitor on the XA XB port For the 515374 and Si5375 the XA XB port refers to the 5 P and OSC N pins 7 11 8 LOL 515319 515324 515326 515327 515368 515369 515374 515375 The device has PLL lock detection algorithm that indicates the lock status the LOL output and the LOL_INT read only register bit The algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock A retriggerable one shot is set each time a potential phase cycle slip condition is detected If no potential phase cycle slip occurs for the retrigger time the LOL output is set low indicating th
117. al 10 0153 kHz 110 0 140 0 150 0 100 1 10i 1001 1M 10M Figure 75 78 125 MHz In 690 569 MHz Ou 160 0 Table 64 Jitter Values for Figure 75 Jitter Bandwidth 690 569 MHz Jitter RMS Broadband 1 kHz to 10 MHz 244 fs OC 48 12 kHz to 20 MHz 260 fs OC 192 20 kHz to 80 MHz 261 fs OC 192 4 MHz to 80 MHz 120 fs OC 192 50 kHz to 80 MHz 253 fs Broadband 800 Hz to 80 MHz 266 fs 136 Rev 0 5 SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 110 0 5 _ Carrier 693 482994 MHz 0 5140 dB Start 100 Hz Stop 100 0009 MHz Center 50 0005 MHZ Span 100 0008 MHz Noise Analysis Range x Band Marker Analysis Range Y Band Marker Intg Noise 34 7608 dBc 40 MHz RMS Noise 25 8507 mrad 1 48114 deg RMS Jitter 5 93276 psec Residual 10 4274 kHz 1 10 Figure 76 78 125 MHz In 693 493 MHz Out 100 1 10 Table 65 Jitter Values for Figure 76 Jitter Bandwidth 693 493 MHz Jitter RMS Broadband 1 kHz to 10 MHz 243 fs OC 48 12 kHz to 20 MHz 265 fs OC 192 20 kHz to 80 MHz 264 fs OC 192 4 MHz to 80 MHz 124 fs OC 192 50 kHz to 80 MHz 255 fs Broadband 800 Hz to 80 MHz 269 fs 0 5 137 SILICON LABS Si53xx RM 86 685 MHz in 173 371 MHz and 693 493 MHz out 0 00E 00 2 00E 01 4 00E 01 6 01 8 00E 01 1 00E 02
118. alid CKINn in priority order is selected If no valid CKINn is available the device enters Digital Hold Operation in revertive and non revertive is different when a signal becomes valid Revertive AUTOSEL The device constantly monitors all CKINn If a CKINn with a higher priority than the current active CKINn becomes valid the active CKINn is changed to the CKINn with the highest priority Non revertive AUTOSEL M The active clock does not change until there is an alarm on the active clock The device will then select the highest priority CKINn that is valid Once in digital hold the device will switch to the first CKINn that becomes valid 6 3 3 Hitless Switching with Phase Build Out Si5323 Si5366 Silicon Laboratories switching technology performs phase build out to minimize the propagation of phase transients to the clock outputs during input clock switching All switching between input clocks occurs within the input multiplexor and phase detector circuitry The phase detector circuitry continually monitors the phase difference between each input clock and the DSPLL output clock fosc The phase detector circuitry can lock to a clock signal at a specified phase offset relative to fosc so that the phase offset is maintained by the PLL circuitry At the time a clock switch occurs the phase detector circuitry knows both the input to output phase relationship for the original input clock and for the new input clock The phase
119. and Hold Logic 0 which create static logic levels at the outputs are available For differential output buffer formats the Hold Logic 1 state causes the positive output of the differential signal to remain at its high logic level while the negative output remains at the low logic level For CMOS output buffer format both outputs remain high during the Hold Logic 1 state These functions are controlled by the HLOG n bits When entering or exiting the Hold Logic 1 or Hold Logic 0 states no glitches or runt pulses are generated on the outputs Changes to SFOUT or HLOG will change the output phase An ICAL is required to re establish the output phase When SFOUT 010 for CMOS bypass mode is not supported 7 9 1 Disabling CKOUTn Disabling CKOUTn output powers down the output buffer and output divider Individual disable controls are available for each output using the DS5BLn REG 7 9 2 LVPECL TQFP Output Signal Format Restrictions at 3 3 V Si5367 Si5368 Si5369 The LVPECL and CMOS output formats draw more current than either LVDS or CML therefore there are restrictions in the allowed output format pin settings that limit the maximum power dissipation for the TQFP devices when they are operated at 3 3 V When Vdd 3 3 V and there are four enabled LVPECL or CMOS outputs the fifth output must be disabled When Vdd 3 3 V and there are five enabled outputs there can be no more than three outputs that are either LVPECL CMOS All other
120. and 156 25 MHz In 622 08 MHz Out 141 Figure 81 10 MHz In 1 GHz Out 142 Figure 82 515324 and 515326 Alarm Diagram 144 Figure 83 515368 Alarm Diagram 1 0 12 145 Figure 84 515368 Alarm Diagram 2012 146 Figife 85 50 ppm 2 PPM Steps duos tree bue S Cg E RR Cd 162 Figure 86 200 ppm 10 ppm Steps 163 Figure 87 2000 ppm 50 ppm 163 8 Rev 0 5 SILICON LABS Si53xx RM Figure 88 RF Generator Si5326 Si5324 No Jitter For Reference 165 Figure 89 RF Generator 515326 515324 50 Hz 165 Figure 90 RF Generator 515326 515324 100 Hz 166 Figure 91 RF Generator 515326 515324 500 Hz 166 Figure 92 RF Generator 515326 515324 1 kHz 167 Figure 93 RF Generator 515326 515324 5 kHz 167 Figure 94 RF Generator 515326 515324 10 kHz 168 Figure 95 Wad PIANC cos costa ses T Dies ers aus avit ea dunes dtr eaqui qu sra cd 169 Figure 96 Ground Plane and
121. are performed If many clock switches are performed in phase build out mode it is possible that the input sync to output sync phase relationship will shift due to the accumulated residual phase transients of the phase build out circuitry If the sync alignment error exceeds the threshold in either the positive or negative direction an alignment alarm becomes active If it is then desired to reestablish the desired input to output sync phase relationship a realignment can be performed A realignment request may cause FS OUT to instantaneously shift its output edge location in order to align with the active input sync phase 6 6 2 Including FSYNC Inputs in Clock Selection Si5366 The frame sync inputs CKIN3 and CKIN4 are both monitored for loss of signal LOS3 INT 1054 INT conditions To include these LOS alarms in the input clock selection algorithm set FS SW 1 The LOS3 INT is logically ORed with LOS1 INT and 054 INT is ORed with LOS2 INT as inputs to the clock selection state machine If it is desired not to include these alarms in the clock selection algorithm set F8 SW 0 The FOS alarms for CKIN3 and CKIN4 are ignored See Table 33 on page 74 6 6 3 FS OUT Polarity and Pulse Width Control 515366 Additional output controls are available for 5 OUT FS OUT is active high and the pulse width is equal to one period of the CKOUT2 output clock For example if CKOUT2 is 622 08 MHz the FS OUT pulse width will be 1 622 0866 1
122. at the 3L inputs can tolerate from an external driver See Figure 55 on page 115 3 Nounder or overshoot is allowed 34 Rev 0 5 lt SILICON LABS Si53xx RM Table 4 DC Characteristics Continued Test Condition CMOS Driving into CKO vor for output low or for out put high CKOUT and CKOUT shorted shorted externally externally Vpp 1 8 V ICMOS 1 0 11 ICMOS 1 0 10 ICMOS 1 0 01 ICMOS 1 0 00 3 3 V ICMOS 1 0 11 1 0 10 ICMOS 1 0 01 ICMOS 1 0 00 2 Level LVCMOS Input Pins Input Voltage Low Vi Vpp 1 71 V Vpp 2 25 V Vpp 2 97 V Input Voltage High Vpp 1 89 V Vpp 2 25 V 3 63 V 3 Level Input Pins Input Voltage Low VILL Input Voltage Mid 0 45 x Vpp Input Voltage High 0 85 x Vpp Input Low Current See note 20 Notes 1 Refer to Section 6 7 1 and 8 2 1 for restrictions on output formats for TQFP devices at 3 3 V 2 This is the amount of leakage that the 3L inputs can tolerate from an external driver See Figure 55 on page 115 3 No under or overshoot is allowed lt Rev 0 5 35 SILICON LABS 5153 Table 4 DC Characteristics Continued Symbol Test Condition See note Input High
123. cillator or crystal is not relevant as long as it is within one of the frequency bands described in Table 60 Reference Jitter Jitter on the reference input has a roughly one to one transfer function to the output jitter over the band from 100 Hz up to about 30 kHz If the XA XB pins implement a crystal oscillator the reference will have suitably low jitter if a suitable crystal is used If the XA XB pins are connected to an external reference oscillator the jitter of the external reference oscillator may also contribute significantly to the output jitter A typical reference input to output jitter transfer function is shown in Figure 59 38 88MHz XO 38 88MHz CKIN 38 88MHz CKOUT 10 0 2 5 10 Jitter Xfer 20 30 1 10 100 1000 10000 100000 1000000 Frequency Hz Figure 59 Typical Reference Jitter Transfer Function 120 Rev 0 5 e SILICON LABS Si53xx RM APPENDIX B FREQUENCY PLANS AND JITTER PERFORMANCE Si5316 Si5319 515323 515324 515326 515327 515366 515368 515369 515374 515375 Introduction To achieve the best jitter performance from Narrowband Any Frequency Clock devices a few general guidelines should be observed High f3 Value is defined as the comparison frequency at the Phase Detector It is equal to the input frequency divided by DSPLLsim automatically picks the frequency plan that has the highest possible f3 value and it report
124. ck not the Any Frequency Precision Clock lt Rev 0 5 121 SILICON LABS Si53xx RM Figure 61 shows similar results and ties them to RMS jitter values It also helps to illustrate one potential remedy for solutions with low f3 Note that 38 88 MHz x 5 194 4 MHz In this case an FPGA was used to multiply 38 88 MHz input clock up by a factor of five to 194 4 MHz using a feature such as the Xilinx DCM Digital Clock Manager Even though FPGAs are notorious for having jittered outputs the jitter attenuating feature of the Narrowband Any Frequency Clocks allow an FPGA output to be used to produce a very clean clock as can be seen from the jitter numbers below 38 88 MHz in 194 4 MHz in 690 57 MHz out 20 40 60 80 100 Phase Noise dBc Hz 120 140 160 10 100 1000 10000 100000 Offset Frequency Hz Dark blue 38 88 MHz in f3 3 214 kHz Light blue 194 4 MHz in f3 16 1 kHz 1000000 Figure 61 Jitter vs f3 with FPGA Table 61 Jitter Values for Figure 61 10000000 100000000 f3 3 214 kHz 16 1 kHz CKIN 38 88 MHz 194 4 MHz Jitter Bandwidth Jitter RMS Jitter RMS OC 48 12 kHz to 20 MHz 1 034 fs 285 fs OC 192 20 kHz to 80 MHz 668 fs 300 fs OC 192 4 MHz to 80 MHz 169 fs 168 fs OC 192 50 kHz to 80 MHz 374 fs 287 fs 800 Hz to 80 MHz 3 598 fs 378 fs 122 Rev 0 5 lt SILICO
125. configurations are valid including all with Vdd 2 5 V lt Rev 0 5 95 SILICON LABS Si53xx RM 7 10 PLL Bypass Mode 515319 515324 Si5325 Si5326 Si5327 515367 515368 515369 515374 515375 The device supports a PLL bypass mode in which the selected input clock is fed directly to the output buffers bypassing the DSPLL In PLL bypass mode the input and output clocks will be at the same frequency PLL bypass mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation provided by the DSPLL The BYPASS_REG bit controls enabling disabling PLL bypass mode Before going into bypass mode it is recommended that the part enter Digital Hold by setting DHOLD Internally the bypass path is implemented with high speed differential signaling for low jitter Note that the CMOS output format does not support bypass mode 7 11 Alarms 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 Summary alarms are available to indicate the overall status of the input signals frame alignment 515368 only Alarm outputs stay high until all the alarm conditions for that alarm output are cleared The Register VALTIME controls how long a valid signal is re applied before an alarm clears Table 48 shows the available settings Note that only for VALT ME 1 0 00 hitless switching is not possible Table 48 Loss of Signal Validation Times VALTIME
126. ctive lat 25 ns Delay Time SCLK Fall to SDO Transition 25 ns Delay Time SS Rise to SDO Tri state ta3 25 ns Setup Time SS to SCLK Fall tout 25 ns Hold Time SS to SCLK Rise 20 ns Setup Time SDI to SCLK Rise tsu2 25 r2 ns Hold Time SDI to SCLK Rise tno 20 ns Delay Time between Slave Selects 25 ns Note All timing is referenced to the 50 level of the waveform unless otherwise noted Input test levels are Vpp 4 V VIL 0 4 V lt Rev 0 5 37 SILICON LABS 5153 SCLK SDI SDO Figure 18 SPI Timing Diagram Table 7 DC Characteristics Narrowband Devices Si5316 Si5319 Si5323 Si5366 Si5368 Parameter Symbol Test Condition Single Ended Reference Clock Input Pin XA XB with cap to gnd Input Resistance XARIN RATE 1 0 LM ML MH or HM Input Voltage Level Limits XAVIN Input Voltage Swing XAvpp Differential Reference Clock Input Pins XA XB Differential Input Voltage XA XByin LM ML MH or HM Level Limits Input Voltage Swing XAypp XBypp 38 Rev 0 5 e SILICON LABS Si53xx RM FLL ULL an FSYNC 2 CLKIN_4 f L tessu 6 tesh FSYNC_ALIGN 06 tate j 2722 Fixed number of CLKOUT 2 clock cycles CLKIN 2 and CLKIN 4 are the active input clock and frame sy
127. d CKIN2 selection remains as long as it is valid even if alarms are cleared on CKIN1 7 4 3 Hitless Switching with Phase Build Out Si5324 Si5326 Si5327 Si5368 Si5369 Si5374 Silicon Laboratories switching technology performs phase build out which maintains the phase of the output when the input clock is switched This minimizes the propagation of phase transients to the clock outputs during input clock switching All switching between input clocks occurs within the input multiplexer and phase detector circuitry The phase detector circuitry continually monitors the phase difference between each input clock and the DSPLL output clock fosc The phase detector circuitry can lock to a clock signal at a specified phase offset relative to fosc so that the phase offset is maintained by the PLL circuitry At the time a clock switch occurs the phase detector circuitry knows both the input to output phase relationship for the original input clock and for the new input clock The phase detector circuitry locks to the new input clock at the new clock s phase offset so that the phase of the output clock is not disturbed The phase difference between the two input clocks is absorbed in the phase detector s offset value rather than being propagated to the clock output The switching technology virtually eliminates the output clock phase transients traditionally associated with clock rearrangement input clock switching Note that hitless switching betwe
128. d stable clock on e e ele E 1 2 sec CKOUT CKIN Minimum Reset tRSTMIN 1 Us Pulse Width Lock Time Start of ICAL to 4 of e 35 1000 ms LOL lowest BW setting Closed Loop Jitter J 0 05 0 1 dB Peaking 42 Rev 0 5 lt SILICON LABS Si53xx RM Table 8 Characteristics All Devices Continued Test Condition Temperature Vari ation Max phase changes from 40 to 85 C Jitter Tolerance See 5 2 3 Jitte page 49 r Tolerance on Phase Noise fout 622 08 MHz 1 kHz Offset 106 10 kHz Offset 121 100 kHz Offset 132 1 MHz Offset 132 Subharmonic Noise Phase Noise 100 kHz Offset Spurious Noise SILICON LABS Rev 0 5 43 5153 Table 9 Jitter Generation 515316 515324 515366 515368 Parameter Symbol Test Condition 2 3 4 5 Min Typ Max GR 253 Spec Unit Measurement DSPLL Filter MHz Bandwidth 0 02 80 120 Hz 4 2 6 2 30 ps 0 3 pspp 27 42 4 80 120 Hz 3 7 6 4 10 ps pp 0 1 Ulpp pspp Jitter Gen OC 192 JGEN 14 31 N A DSrms 0 05 80 120 Hz 4 4 6 9 10 ps 0 1 Ulpp 26 41 1 0 PSims 0 01 Ulims 0 012 20 120 2 3 5 5 4 40 2 ps pp PS
129. d or frame sync applications Register values are indicated by underscored italics Note that when switching between two clocks LOL may temporarily go high if the clocks differ in frequency by more than 100 ppm CKIN1 Selected CKIN2 Clock LOS FO LOS FOS detect detect 4 CK PRIOHn d Clock priority logic CS CApin CKSEL REG 2 Auto AUTOSEL decode Manual I ACTV PIN CKSEL PIN Figure 27 515324 515325 515326 515327 and 515374 Input Clock Selection lt Rev 0 5 81 SILICON LABS Si53xx RM CKIN1 CKIN2 Selected CKIN Clock LOS FO LOS FO detect detect LOS FO LOS FO detect detect CK PRIOR 50 C3A CS1 pins CKSEL REG Z 2 AUTOSEL am decode Manual KSEL PIN Figure 28 Si5367 Si5368 and Si5369 Input Clock Selection 7 4 1 Manual Clock Selection 515324 515325 515326 515367 515368 515369 515374 Manual control of input clock selection is available by setting the AUTOSEL_REG 1 0 register bits to 00 In manual mode the active input clock is chosen via the CKSEL_REG 1 0 register setting according to Table 38 and Table 39 Table 38 Manual Input Clock Selection Si5367 Si5368 Si5369 CKSEL REG 1 0 Active Input Clock neg eer BUS CK CONFIG REG 0 CK CONFIG REG 1 CKIN1 2 3 4 input
130. detector circuitry locks to the new input clock at the new clock s phase offset so that the phase of the output clock is not disturbed The phase difference between the two input clocks is absorbed in the phase detector s offset value rather than being propagated to the clock output The switching technology virtually eliminates the output clock phase transients traditionally associated with clock rearrangement input clock switching lt Rev 0 5 69 SILICON LABS Si53xx RM 6 4 Digital Hold VCO Freeze All Any Frequency Precision Clock devices feature a hold over or VCO freeze mode whereby the DSPLL is locked to a digital value 6 4 1 Narrowband Digital Hold Si5316 Si5323 Si5366 If an LOS or FOS condition exists on the selected input clock the device enters digital hold In this mode the device provides a stable output frequency until the input clock returns and is validated When the device enters digital hold the internal oscillator is initially held to its last frequency value Next the internal oscillator slowly transitions to a historical average frequency value that was taken over a time window of 6 711 ms in size that ended 26 ms before the device entered digital hold This frequency value is taken from an internal memory location that keeps a record of previous DSPLL frequency values By using a historical average frequency input clock phase and frequency transients that may occur immediately preceding loss of clock or
131. e IRQ pin can be programmed to function as one pin the other pin or both 4 Selection of the OSC frequency is done by a register RATE REG not by using the RATE pins 5 The Si5374 75 uses a different version of DSPLLsim Sib37xDSPLLsim 6 The Si5374 75 does not support 3 3 V operation e Rev 0 5 29 SILICON LABS Si53xx RM 3 15 515374 The Si5374 is a highly integrated 4 PLL jitter attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance Each of the DSPLL clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent synchronous output clocks ranging from 2 kHz to 808 MHz Each DSPLL provides virtually any frequency translation across this operating range For asynchronous free running clock generation applications the Si5374 s reference oscillator can be used as a clock source for the four DSPLLs The Si5374 input clock frequency and clock multiplication ratio are programmable through 2 interface The 515374 is based on Silicon Laboratories 3rd generation DSPLL technology which provides any frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components Each DSPLL loop bandwidth is digitally programmable from 4 to 525 Hz providing jitter performance optimization at the application level The device operates from a single 1 8 or 2 5 V supply with
132. e PLL is in lock The LOL pin is held in the active state during an internal PLL calibration The active polarity of the LOL output pin is set using the LOL_POL register bit default active high The lock detect retrigger time is user selectable independent of the loop bandwidth The LOCKTT 2 0 register bits must be set by the user to the desired setting Table 54 shows the lock detect retrigger time for both modes of operation LOCKT is the minimum amount of time that LOL will be active 100 Rev 0 5 e SILICON LABS Si53xx RM Table 54 Lock Detect Retrigger Time LOCKT 2 01 Retrigger Time ms 000 106 001 53 010 26 5 011 13 3 100 6 6 value after reset 101 3 3 110 1 66 111 833 7 11 9 Device Interrupts Alarms on internal real time status bits such as LOS1_INT FOS1 INT etc cause their associated interrupt flags LOS1 FLG FOS1_FLG etc to be set and held The interrupt flag bits can be individually masked or unmasked with respect to the output interrupt pin Once an interrupt flag bit is set it will remain high until the register location is written with a O to clear the flag 7 12 Device Reset Upon powerup or asserting Reset via the RST pin or software the device internally executes a power on reset POR which resets the internal device logic and tristates the device outputs The device waits for configuration commands and the receipt of the CAL 1 c
133. e devices 6 10 Device Reset Upon powerup the device internally executes a power on reset POR which resets the internal device logic The pin RST can also be used to initiate a reset The device stays in this state until a valid CKINn is present when it then performs a PLL Self Calibration See 6 2 PLL Self Calibration 6 11 DSPLLsim Configuration Software To simplify frequency planning loop bandwidth selection and general device configuration of the Any Frequency Precision Clocks Silicon Laboratories offers the DSPLLsim configuration utility for this purpose This software is available to download from www silabs com timing e Rev 0 5 75 SILICON LABS Si53xx RM 7 Microprocessor Controlled Parts 5319 515324 515325 515326 515327 515367 515368 515369 515374 515375 The devices this family provide rich set of clock multiplication clock division options loop bandwidth selections output clock phase adjustment and device control options 7 1 Clock Multiplication The input frequency clock multiplication ratio and output frequency are set via register settings Because the DSPLL dividers settings are directly programmable a wide range of frequency translations is available In addition a wider range of frequency translations is available in narrowband parts than wideband parts due to the lower phase detector frequency range in narrowband parts To assist users in finding valid divider settin
134. e interface Table 55 shows the SPI command format Table 55 SPI Command Format Instruction BYTEO Address Data 7 0 BYTE1 00000000 Set Address AAAAAAAA 01000000 Write DDDDDDDD 01100000 Write Address Increment DDDDDDDD 10000000 Read DDDDDDDD 10100000 Read Address Increment DDDDDDDD The first byte of the pair is the instruction byte The Set Address command writes the 8 bit address value that will be used for the subsequent read or write The Write command writes data into the device based on the address previously established and the Write Address Increment command writes data into the device and then automatically increments the register address for use on the subsequent command The Read command reads one byte of data from the device and the Read Address Increment reads one byte and increments the register address automatically The second byte of the pair is the address or data byte As shown in Figure 36 and Figure 37 SSb should be held low during the entire two byte transfer Raising SSb resets the internal state machine so SSb can optionally be raised between each two byte transfers to guarantee the state machine will be reinitialized During a read operation the SDO becomes active on the falling edge of SCLK and the 8 bit contents of the register are driven out MSB first The SDO is high impedance on the rising edge of SS SDI is a don t care during the data po
135. ecessary CKOUT Jitter e XA XB to CKOUT jitter transfer function is roughly one to one e For very low jitter either use a high quality crystal or external oscillator e 3rd overtone crystals have lower close in phase noise e general higher XA XB frequency gt lower jitter frequency accuracy e For hitless switching to meet all published specifications the XA XB frequency divided by N32 should match the CLKIN frequency divided by N31 If they do not match the clock switch will still be well behaved Other than the above the absolute accuracy of the XA XB frequency is not important 86 Rev 0 5 lt SILICON LABS Si53xx RM 7 6 Digital Hold All Any Frequency Precision Clock devices feature a holdover mode whereby the DSPLL is locked to a digital value 7 6 1 Narrowband Digital Hold Si5316 Si5324 Si5326 Si5368 Si5369 Si5374 After the part s initial self calibration ICAL when no valid input clock is available the device enters digital hold Referring to the logical diagram in Appendix D Alarm Structure on page 144 lack of clock availability is defined by following the boolean equation for the Si5324 515326 and Si5374 LOS1_INT OR FOS1_INT AND LOS2_INT OR FOS2_INT enter digital hold The equivalent Boolean equation for the Si5327 is as follows LOS1 and LOS2 enter digital hold The equivalent boolean equation for the 515367 515368 and 515369 is as follows LOS1
136. ected each differential output buffer generates two in phase CMOS clocks at the same frequency For system level debugging a PLL bypass mode drives the clock output directly from the selected input clock bypassing the internal PLL Silicon Laboratories offers a PC based software utility DSPLLsim that can be used to determine valid frequency plans and loop bandwidth settings for the Any Frequency Precision Clock product family For the microprocessor controlled devices DSPLLsim provides the optimum PLL divider settings for a given input frequency clock multiplication ratio combination that minimizes phase noise and power consumption Two DSPLLsim configuration software applications are available for the 1 PLL and 4 PLL devices respectively DSPLLsim can also be used to simplify device selection and configuration This utility can be downloaded from http Awww silabs com timing Other useful documentation including device data sheets and programming files for the microprocessor controlled devices are available from this website e Rev 0 5 13 SILICON LABS Si53xx RM Table 1 Product Selection Guide Part Control Number of Input Output RMS Phase Jitter PLL Hitless Free Package Number Inputs and Frequency Frequency 12 kHz 20 MHz Bandwidth Switching Run Outputs MHz MHz Mode 515315 Pin 1PLL 2 2 0 008644 0 008 644 0 45 ps gt ut
137. ed clock outputs ranging from 19 44 MHz to 1050 MHz The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET Ethernet Fibre Channel and broadcast video rates The DSPLL loop bandwidth is digitally selectable Operating from a single 1 8 2 5 V or 3 3 V supply the Si5365 is ideal for providing clock multiplication in high performance timing applications See 6 Pin Control Parts 515316 515322 515323 515365 515366 on page 50 for a complete description BYPASS DSBL2 GAIN ts 2 N3 1 gt 2 CKOUT_1 ckour 1 CKIN_2 2 N3 2 gt 2 fs y 2 i CKOUT_2 CKIN 3 2 yg al 2 00 DSPLL NES Ne cy Le CKOUT 2 CKIN 3 DBL2 BY 4 He N3 nes roll CKOUT_3 CKIN 4 ol CKOUT 3 N2 DBL34 1 DIV34 1 0 gt 2 CKOUT 4 cod TENCA eo CKOUT 4 4 C3B 4 Lt 2 CKOUT 5 ALRMOUT lt Control p 4 5 4 L DBL5 C2A lt CS0 C3A 4 CS1 4 lt VDD Num 5 a e 88 e zu g u 5 2 4 gt m E o Fig
138. eds two cycles of CKOUT2 6 9 4 C1B and C2B Alarm Outputs Si5316 Si5322 Si5323 The alarm outputs C1B and C2B are determined directly by the LOS1_INT and LOS2_INT internal indicators directly That is C1B 1051 and C2B LOS2 6 9 5 C1B 2 C3B and ALRMOUT Outputs 515365 Si5366 The alarm outputs C1B C2B C3B ALRMOUT provide a summary of various alarm conditions on the input clocks depending on the setting of the FOS_CNTL and pins The following internal alarm indicators are used in determining the output alarms m LOSn INT See section 6 9 1 Loss of Signal Alarms 515316 Si5322 515323 515365 Si5366 for a description of how LOSn INT is determined m FOSn INT See section 6 9 2 FOS Alarms Si5365 and Si5366 for a description of how FOSn INT is determined m ALIGN INT See section 6 9 3 FSYNC Align Alarm 515366 and CONF 1 and FRQTBL L fora description of how ALIGN INT is determined Based on the above internal signals and the settings of the CONF and 5 pins the outputs C2B C3B ALRMOUT are determined See Table 33 For details see Appendix D Alarm Structure on page 144 Table 33 Alarm Output Logic Equations CK CONF FOS CTL Alarm Output Equations 0 L C1B LOS1 INT Four independent input Disables FOS C2B LOS2 INT clocks C3B LOSS INT ALRMOUT LOS4 INT M or H C1B LOS1 INT or FOS1 INT C2B LOS2 INT or FOS2 INT C3B LOSS INT
139. emplate Simplified Section 4 Device Specifications Updated Figure 41 CMOS Termination 1 8 2 5 3 3 V Revision 0 42 to Revision 0 5 Added Si5327 Si5369 Si5374 and Si5375 Removed Si5319 and Si5323 from the spec tables Updated the typical phase noise plots Added new appendixes G H and J Updated spec table values Added examples and diagrams throughout 178 Rev 0 5 SILICON LABS Si53xx RM NOTES SILICON LABS Rev 0 5 179 Si53xx RM CONTACT INFORMATION Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 Tel 1 512 416 8500 Fax 1 512 416 9669 Toll Free 1 877 444 3032 Please visit the Silicon Labs Technical Support web page https www silabs com support pages contacttechnicalsupport aspx and register to submit a technical support request Silicon Laboratories Silicon Labs and DSPLL are trademarks of Silicon Laboratories Inc Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice Silicon Laboratories assumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functionin
140. en input clocks applies only when the input clock validation time is VALTIMET1 0 01 or higher 84 Rev 0 5 e SILICON LABS Si53xx RM 7 5 515319 515324 515326 515327 515368 515369 515374 and 515375 Free Run Mode 515319 515324 Crystal or an external oscillator 515326 external oscillator only for the 515374 75 515327 515368 515369 515374 515375 CKIN1 CKOUT1 CKOUT2 CKIN2 Control I C SPI Figure 29 Free Run Mode Block Diagram CKIN2 has an extra mux with a path to the crystal oscillator output When in Free Run mode CKIN2 is sacrificed 515326 515368 515369 515374 Switching between the crystal oscillator and CLKIN1 is hitless Either a crystal or an external oscillator can be used External oscillator connection can be either single ended or differential All other features and specifications remain the same 5 1 Free Run Mode Programming Procedure Using DSPLLsim determine the frequency plan e Write to the internal dividers including N31 and N32 Enable Free Run Mode the mux select line FREE RUN Select CKIN1 as the higher priority clock Establish revertive and autoselect modes Once properly programmed the part will e Initially lock to either the XA XB 5 P and OSC N for the Si5374 75 or to CKIN1 e Automatically select CKIN1 if it is available e Automatically and hitlessly switch to XA XB if CKIN1 fails e Automatically and hitlessly s
141. er 10 006 MHz 20 00 Span 19 988 MHz 0156 Analysis Range Band Marker 30 00 Analysis Range Y Band Marker Intg Noise 63 8173 dBc 19 69 MHz RMS Noise 911 281 prad 40 00 52 2125 mdeg RMS Jitter 233 145 fsec Residual FM 4 03209 kHz 60 00 80 00 90 00 100 0 110 0 20 0 30 0 140 0 100 m 10 100i 2 1M m 10M 100M Figure 65 155 52 2 In 622 08 MHz Out 126 Rev 0 5 SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 622 079995 MHz 38 03 dBm gt i 1 003 kHz 114 5382 dBc Hz Start 500 Stop 50 MHz Center 25 00025 MHz Span 49 9995 MHZ L NOT S Analysis Range X Band Marker Analysis Range Y Band Marker Intg Noise 62 2020 dBc 49 85 MHz RMS Noise 1 09753 mrad 62 8839 mdeg RMS Jitter 280 796 fsec Residual 11 9358 kHz 10 00 40 00 50 00 110 0 140 0 150 0 160 0 10 100 101 100k 1M 10M Figure 66 155 52 MHz In 622 08 MHz Out Loop BW 7 Hz 515324 100M s Rev 0 5 SILICON LABS 127 Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 156 250015 MHz 5 3392 dBm i 51 12 kHz 131 5026 dBc Hz 2 20 MHz 154 8207 dBc Hz 10 00 start 11 972 kHz Stop 20 MHz _ Center 10 005986 MHZ 20 00 Span 19 988028 MHZ Noise 30 00 Analysis Range
142. g of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation conse quential or incidental damages Silicon Laboratories products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the Silicon Laboratories product could create a situation where per sonal injury or death may occur Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap plication Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages 180 Rev 0 5 SILICON LABS
143. ghly stable reference such as an oven controlled crystal oscillator OCXO is supplied at XA XB an extremely stable digital hold can be achieved If a crystal is supplied at the XA XB port the digital hold stability will be limited by the stability of the crystal 88 Rev 0 5 e SILICON LABS Si53xx RM 7 6 2 History Settings for Low Bandwidth Devices Si5324 Si5327 Si5369 Si5374 Because of the extraordinarily low loop bandwidth of the 515324 515369 and Si5374 it is recommended that the values for both history registers be increased for longer histories 7 6 3 Recovery from Digital Hold Si5319 Si5324 Si5326 Si5327 Si5368 Si5369 Si5374 When the input clock signal returns the device transitions from digital hold to the selected input clock The device performs hitless recovery from digital hold The clock transition from digital hold to the returned input clock includes phase buildout to absorb the phase difference between the digital hold clock phase and the input clock phase 7 6 4 VCO Freeze 515319 515325 515367 515375 If an LOS or FOS condition exists on the selected input clock the device enters VCO freeze In this mode the device provides a stable output frequency until the input clock returns and is validated When the device enters digital hold the internal oscillator is initially held to the frequency value at roughly one second prior to the leading edge of the alarm condition VCO freeze is no
144. gs for a particular input frequency and clock multiplication ratio Silicon Laboratories offers the DSPLLsim utility to calculate these settings automatically When multiple divider combinations produce the same output frequency the software recommends the divider settings that yield the best combination of phase noise performance and power consumption 7 1 1 Jitter Tolerance 515319 515324 515325 Si5326 515327 515368 515369 515374 and 515375 See Section 5 2 3 7 1 2 Wideband Parts 515325 Si5367 These devices operate as wideband clock multipliers without an external resonator or reference clock This mode may be desirable if the input clock is already low jitter and only simple clock multiplication is required A limited selection of clock multiplication factors is available in this mode The input to output skew for wideband parts is not controlled Refer to Figure 25 The selected input clock passes through the input divider and is provided to the DSPLL The input to output clock multiplication ratio is defined as follows four fin x N2 N1 x where N1 output divider N2 feedback divider N3 input divider fin 10 MHz 710 MHz four 2 kHz 1 4 GHz N1 CKIN1 CKOUT 1 GRINE CKOUT 2 N2 N2 LS LS 32 34 36 512 CKIN4 CKOUT_5 N3 1 N1_HS x NI LS 1 2 3 2 9 N1_HS 4 5 6 11 N1 LS 1 2 4 6 27 Figure 25 Wideband PLL Divider Settings Si5325 Si5367
145. h 85 x Input Low Current lill 6 Input Mid Current limm 2 2 Input High Current lihh E 6 uA Note The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver SILICON LABS Rev 0 5 115 Si53xx RM 8 6 Three Level 3L Input Pins With External Resistors Vpp Vpp 1 18 75 imm External Driver 18 75 One of eight resistors from a Panasonic EXB D10C183J or similar resistor pack Figure 56 Three Level Input Pins Parameter Symbol Min Max Input Low Current lill 30 uA Input Mid Current limm 11 11 pA Input High Current linh 30 uA Note The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver m Anyresistor pack may be used e The Panasonic EXB D10C183J is an example e PCB layout is not critical m Resistor packs are only needed if the leakage current of the external driver exceeds the listed currents m lfapinistied to ground or Vdd resistors are needed m If apinis left open no connect no resistors are needed 116 Rev 0 5 e SILICON LABS Si53xx RM 9 Power Supply These devices incorporate an on chip voltage regulator to power the device from supply voltages of 1 8 2 5 or 3 3 V Internal core circuitry is driven from the output of this regulator while I
146. he appearance of ALRMOUT at the output even if ALRMOUT PIN 1 Once an LOS or FOS alarm is asserted for one of the input clocks it is held high until the input clock is validated over a designated time period The validation time is programmable via the VALTIMET1 0 register bits as shown in Table 48 on page 96 If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over Note that hitless switching between input clocks applies only when the input clock validation time VALTIMET1 0 01 or higher For details see Appendix D Alarm Structure on page 144 Table 52 Alarm Output Logic Equations 515367 515368 and Si5369 CONFIG REG 01 FOS EN Alarm Output Equations 0 C1B LOS1 INT Disables FOS C2B LOS2 INT C3B LOSS INT ALRMOUT LOS4 INT 1 LOS1 INT or FOS1 INT C2B LOS2 INT or FOS2 INT C3B 1053 INT or 53 INT ALRMOUT LOS4 INT or FOS4 INT lt Rev 0 5 99 SILICON LABS Si53xx RM 7 11 6 C1B C2B C3B ALRMOUT Si5368 CK_CONFIG_REG 1 The generation of alarms on the C1B C2B C3B and ALRMOUT outputs is a function of the input clock configuration and the frequency offset alarm enable as shown in Table 53 The LOSn_INT and FOSn_INT signals are the raw outputs of the alarm monitors These appear directly in the device status registers Sticky versions of these bits LOSn_FLG
147. hine will read the new skew alignment value Note that when the new FSYNC SKEW 16 0 value is used a phase step will occur in 5 OUT 7 8 3 Including FSYNC Inputs in Clock Selection Si5368 The frame sync inputs CKIN3 and CKIN4 are both monitored for loss of signal LOSS INT and 1054 INT conditions To include these LOS alarms in the input clock selection algorithm set SWTCH REG 1 The LOSS INT is logically ORed with LOS1_INT and 1054 INT is ORed with LOS2 INT as inputs to the clock selection state machine If it is desired not to include these alarms in the clock selection algorithm set FSYNC SWTCH REG 0 The frequency offset FOS alarms for CKIN1 and can also be included in the state machine decision making as described in Section 7 11 Alarms 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 however in frame sync mode CK CONFIG REG 1 the FOS alarms for CKIN3 and CKIN4 are ignored 7 8 4 5 OUT Polarity and Pulse Width Control Si5368 Additional output controls are available for 5 OUT The active polarity of 5 OUT is set via the FS OUT POL register bit and the active duty cycle is set via the FSYNC PW 9 0 register Pulse width settings have a resolution of 1 and 50 duty cycle setting is provided Pulse width settings can range from 1 to NC5 1 CKOUT2 periods providing the full range of pulse width possibilities for a given NC5 divider setting
148. http www txc com tw 100 ppm 100 ppm Connor Winfield CS 018 http www conwin com 100 ppm 100 ppm Connor Winfield CS 023 http www conwin com 20 ppm 20 ppm NDK EXS00A CS00871 http www ndk com en 100 ppm 100 ppm NDK EXS00A CS00997 http Awww ndk com en 20 ppm 20 ppm Siward XTL573200NLG http www siward com 20 ppm 20 ppm 114 285 MHz OR Saronix eCera FLB420001 http www pericom com saronix 100 ppm 100 ppm http www ecera tw Mtron 12535071 http Awww mtronpti com 100 ppm 100 ppm Table 60 XA XB Reference Sources and Frequencies RATE 1 0 NB WB Type Recommended Lower limit Upper limit HH WB No crystal or external clock HM NB Reserved m HL NB Reserved External clock 114 285 MHz 109 MHz 125 5 MHz MM NB 3rd overtone crystal 114 285 MHz ML NB Reserved LH NB Reserved LM NB External clock 38 88 MHz 37 MHz 41 MHz LL NB Fundamental mode crystal 40 MHz 37 MHz 41 MHz In some applications a crystal with frequencies other than 114 285 MHz may be used Contact Silicon Labs for details and a current list of crystal vendors and approved part numbers External reference and crystal frequency values should be avoided that result in an output frequency that is an integer or near integer multiple of the reference frequency See Appendix B for details Because the crystal is used as a jitter reference rapid changes of the crystal temperature can temporarily disturb the
149. ice between using N1 HS 4 and another N1 HS value that can produce the desired multiplication ratio the other N1 HS value should be selected This restriction also applies when using the INC pin With the INCDEC PIN register bit set to 1 pin control on the INC and DEC pins function the same as they do for pin controlled parts See 6 6 Output Phase Adjust 515323 515366 on page 71 7 7 1 1 Unlimited Coarse Skew Adjustment Si5326 Si5368 Using the following procedure the CLAT register can be used to adjust the device clock output phase to an arbitrarily large value that is not limited by the size of the CLAT register 1 Write a phase adjustment value to the CLAT register Register 16 The DSPLLsim configuration software provides the size of a single step 2 Wait until CLATPROGRESS 0 register 130 bit 7 which indicates that the adjustment is complete Maximum time for adjustment 20 seconds for the Si5326 or Si5368 Set INCDEC PIN 1 Register 21 bit 7 Write CLAT register Register 16 Wait until CLATPROGRESS 0 Set INCDEC PIN 0 Repeat the above process as many times as desired Sleps 3 6 will clear the CLAT register without changing the output phase This allows for unlimited output clock phase adjustment using the CLAT register and repeating steps 1 3 as many times as needed Note The INC and DEC pins must stay low during this process 7 7 2 Fine Skew Control 515326 515368 An additiona
150. ilicon Laboratories third generation DSPLL technology to eliminate jitter noise and the need for external VCXO and loop filter components found in discrete PLL implementations This is achieved by using a digital signal processing DSP algorithm to replace the loop filter commonly found in discrete PLL designs Because external PLL components are not required sensitivity to board level noise sources is minimized This digital technology provides highly stable and consistent operation over process temperature and voltage variations A simplified block diagram of the DSPLL is shown in Figure 20 This algorithm processes the phase detector error term and generates a digital frequency control word M to adjust the frequency of the digitally controlled oscillator The narrowband configuration devices 515316 515319 515323 515324 515326 515327 515366 515368 515369 provide ultra low jitter generation by using an external jitter reference clock and jitter attenuation For applications where basic frequency multiplication of low jitter clocks is all that is required the wideband parts 515322 515325 515365 and 515367 are available fin Digital Loop Filter fout Figure 20 Any Frequency Precision Clock DSPLL Block Diagram 46 Rev 0 5 lt SILICON LABS Si53xx RM 5 1 Clock Multiplication Fundamental to these parts is a clock multiplication circuit that is simplified in Figure 21 By having a large
151. in the absolute frequency of the reference input because it is a fixed frequency reference and is only used as a jitter reference and holdover reference see 6 4 Digital Hold VCO Freeze on page 70 However care must be taken in certain areas for optimum performance For details on this subject refer to Appendix B Frequency Plans and Jitter Performance 515316 515319 515323 515324 515326 515327 515366 515368 515369 515374 515375 on page 121 For examples of connections to the XA XB pins refer to 8 4 Crystal Reference Clock Interfaces 515316 515319 515323 515324 515326 515327 515366 515368 515369 515374 515375 113 6 1 7 Input to Output Skew 515316 515323 515366 The input to output skew for these devices is controlled 6 1 8 Wideband Performance Si5322 and Si5365 These devices operate as wideband clock multipliers without an external resonator or reference clock They are ideal for applications where the input clock is already low jitter and only simple clock multiplication is required A limited selection of clock multiplication factors is available See Table 16 Table 17 and Table 18 6 1 9 Lock Detect Si5322 and Si5365 A PLL loss of lock indicator is not available in these parts 6 1 10 Input to Output Skew Si5322 and Si5365 The input to output skew for these devices is not controlled 64 Rev 0 5 e SILICON LABS Si53xx RM 6 2 PLL Self Calibrati
152. itter performance is with a 114 285 MHz third overtone crystal The 515327 crystal is fundamental mode and is limited to values between 37 MHz and 41 MHz 2 The jitter transfer for the external reference to CKOUT is nearly 1 1 see Appendix A Narrowband References on page 119 3 In digital hold or VCO freeze mode the VCO tracks any changes in the external reference clock 3 3V 1500 Si53xx 0 1 10k XA 6 V XB 1500 Er For 1 8 V operation change 130 to 47 5 For 2 5 V operation change 130 O to 82 Figure 51 CMOS External Reference Circuit CMOS buffer 8mA output current 0 dBm into 50 O Si53xx External Clock Source 500 0 1 UF Figure 52 Sinewave External Clock Circuit lt Rev 0 5 113 SILICON LABS Si53xx RM Si53xx LVDS LVPECL CML etc 0 01 Figure 53 Differential External Reference Input Example Not for Si5374 or Si5375 i5374 75 1000 1 2V 0 01 LVDS LVPECL CML etc 0 01 Figure 54 Differential OSC Reference Input Example for Si5374 and Si5375 8 114 Rev 0 5 e SILICON LABS Si53xx RM External Driver 8 5 Three Level 3L Input Pins No External Resistors Si53xx 75 Vpp Figure 55 Three Level Input Pins Parameter Symbol Min Max Input Voltage Low Vill 15 x Vpp Input Voltage Mid Vimm 45 x Vdd 55 x Input Voltage High Vih
153. k Multiplier and Jitter Attenuator Block Diagram 29 Figure 14 515374 Functional Block Diagram 30 Figure 15 515375 Functional Block Diagram 31 Figure 16 Differential Voltage Characteristics 32 Figure 17 Rise Fall Time 32 Figure 18 SPI Timing 38 Figure 19 Frame Synchronization Timing 39 Figure 20 Any Frequency Precision Clock DSPLL Block Diagram 46 Figure 21 Clock Multiplication Circuit aaa 47 Figure 22 PLL Jitter Transfer Mask Template 48 Figure 23 Jitter Tolerance 49 Figure 24 515316 Divisor Ratios or xn Facete ea QURE A DONE ahah ER RN RUD d 51 Figure 25 Wideband PLL Divider Settings 515325 55367 76 Figure 26 Narrowband PLL Divider Settings 515319 515324 515326 515327 515368 515369 515374 15375 78 Figure 27 515324 515325 515326 515327 515374 Input Clock Selection 81 Figure 28 515367 515368 515369 Input Clock Selection 82 Figure 29 Free Run Mode Block Diagram
154. l fine adjustment of the overall device skew can be used in conjunction with the INC and DEC pins or the CLAT 7 0 register bits to provide finer resolution output phase adjustments Fine phase adjustment is available using the FLAT 14 0 bits The nominal range and resolution of the FLAT 14 0 skew adjustment word are Range FLAT 110 ps Resolution FLAT 9 ps 90 Rev 0 5 e SILICON LABS NO OQ W Si53xx RM Before writing a new FLAT 14 0 value the FLAT_VALID bit must be set to 0 to hold the existing FLAT 14 0 value while the new value is being written Once the new value is written set FLAT VALID 1 to enable its use To verify a written value into FLAT the FLAT register should be read after the register is written Because the FLAT resolution varies with the frequency plan and selected bandwidth DSPLLsim reports the FLAT resolution each time it creates a new frequency plan 7 7 2 1 Output Phase Adjust 515324 Si5327 Si5369 Si5374 Because of its very low loop bandwidth the output phase of the 515324 515327 515369 Si5374 are not adjustable This means that the 515324 515327 515369 and 515374 do not have INC or DEC pins and that they do not have CLAT or FLAT registers 7 7 3 Independent Skew 515324 515326 Si5368 515369 Si5374 The phase of each clock output may be adjusted in relation to the phase of the other clock outputs respectively This feature is available when CK CONFIG RE
155. led Parts Si5319 Si5324 Si5325 Si5326 515327 515367 515368 515369 515374 515375 on page 76 for a complete description Xtal or Refclock RATE 1 0 10 DSPLL BYPASS 0 2 1 gt N31 CKIN 1 gt ao N32 i DSPLL na p CKOUT 1 CKOUT 1 N1 HS INT I Signal N C2B Detect y 1 2 N2 amp NC2 4 CKOUT 2 CKOUT 2 LOL CS lt CMODE SDA 500 4 SCL SDI Control 2 55 A 1 0 DEC 1 gt RST gt lt GND VDD Figure 7 Si5326 Clock Multiplier and Jitter Attenuator Block Diagram e Rev 0 5 23 SILICON LABS Si53xx RM 3 8 515327 515327 is jitter attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance The Si5327 accepts dual clock inputs ranging from 2kHz to 710MHz and generates two independent synchronous clock outputs ranging from 2 kHz to 808 MHz The device provides virtually any frequency translation combination across this operating range The Si5327 input clock frequency and clock multiplication ratios are programmable through an 2 or SPI interface The DSPLL loop bandwidth is digitally programmable providing
156. lock is validated over a designated time period If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over 7 11 2 FOS Algorithm 515324 515325 515326 515368 515369 515374 The frequency offset FOS alarms indicate if the input clocks are within specified frequency range relative to the frequency of a reference clock The reference clock can be provided by any of the four input clocks two for Si5324 515325 515326 or the XA XB input The default FOS reference is CKIN2 The frequency monitoring circuitry compares the frequency of the input clock s with the FOS reference clock If the frequency offset of an input clock exceeds a selected frequency offset threshold an FOS alarm FOS NT register bit is declared for that clock input Be aware that large amounts of wander can cause false FOS alarms Note For the 515368 If CK CONFIG REG 1 only CKIN1 and CKIN2 are monitored CKIN3 and CKIN4 are used for FSYNC and are not monitored The frequency offset threshold is selectable using the FOS_THA 1 0 bits Settings are available for compatibility with SONET Minimum Clock SCMD or Stratum 3 3E requirements See Table 8 on page 40 The device supports FOS hystereses per GR 1244 CORE making the device less susceptible to FOS alarm chattering A reference clock with suitable accuracy and drift specifications to support the intended application should
157. nals and should be externally shorted together to obtain the drive strength specified in Table 4 DC Characteristics see Section 8 2 Output Clock Drivers Table 30 Output Signal Format Selection SFOUT SFOUT 1 0 Signal Format HL CML HM LVDS LH CMOS LM Disabled MH LVPECL ML Low swing LVDS All Others Reserved The SFOUT 1 0 pins can also be used to disable the output Disabling the output puts the CKOUT and CKOUT pins in a high impedance state relative to Vpp common mode tri state while the two outputs remain connected to each other through a 200 on chip resistance differential impedance of 200 The maximum amount of internal circuitry is powered down minimizing power consumption and noise generation Changing SFOUT without a reset causes the output to output skew to become random When SFOUT LH for CMOS PLL bypass mode is not supported 6 7 1 LVPECL and CMOS TQFP Output Signal Format Restrictions at 3 3 V Si5365 Si5366 The LVPECL and CMOS output formats draw more current than either LVDS or CML However the allowed output format pin settings are restricted so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3 3 V When SFOUT 1 0 MH or LH for either LVPECL CMOS either DBL5 must be H or DBL34 must be high 72 Rev 0 5 e SILICON LABS Si53xx RM 6 8 PLL Bypass Mode The device supports a PLL bypass m
158. nc pair in this example Figure 19 Frame Synchronization Timing e Rev 0 5 39 SILICON LABS 5153 Table 8 AC Characteristics All Devices Parameter Symbol Test Condition lt lt amp 0 8 Min Typ Max Units 0 0 0 0 W W Input Frequency 19 38 710 MHz 19 43 707 35 MHz e 0 002 707 35 MHz 10 710 2 When used as frame 0 008 MHz synchronization input 2 512 kHz CKIN_n Input Pins Input Duty Cycle Whichever is smaller e e 40 60 96 Minimum Pulse i e the 40 60 ss re g S s 5 HE Width CKNpg limitation applies only to high frequency clocks Input Capacitance CKNcin 3 pF Input Rise Fall CKN1TnrF 20 80 11 ns Time See Figure 17 CKOUT n Output Pins See individual data sheets for speed grade limits Output Frequency 19 38 710 MHz Cuno 1943 1049 MHz configured for CMOS or tri state 0 008 1049 MHz 10 945 MHz e e 0 002 945 MHz ee 970 1134 MHz ele e 1 213 1 4 GHz Maximum Output CKOgyc 9 212 5 MHz Frequency in CMOS Format Output Rise Fall Output not config ele eje e e 230 350 ps
159. nd peaking Figure 22 shows the jitter transfer curve mask Jitter Transfer Jitter Out 20x LOG Jitter Inl 0 dB S EE 20 dB dec BW liter Figure 22 PLL Jitter Transfer Mask Template 48 Rev 0 5 e SILICON LABS Si53xx RM 5 2 3 Jitter Tolerance Jitter tolerance is defined as the maximum peak to peak sinusoidal jitter that can be present on the incoming clock before the DSPLL loses lock The tolerance is a function of the jitter frequency because tolerance improves for lower input jitter frequency The jitter tolerance of the DSPLL is a function of the loop bandwidth setting Figure 23 shows the general shape of the jitter tolerance curve versus input jitter frequency For jitter frequencies above the loop bandwidth the tolerance is a constant value Ajo Beginning at the PLL bandwidth the tolerance increases at a rate of 20 dB decade for lower input jitter frequencies Input 20 dB dec Jitter Amplitude Excessive Input Jitter Range BW 100 BW 10 BW Litter In Figure 23 Jitter Tolerance Mask Template The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth i e bandwidth 5000 Aio BW ns pk pk For example the jitter tolerance when fin 155 52 MHZ fout 622 08 MHz and the loop bandwidth BW is 100 Hz _ 5000 jo 99 50 ns pk pk lt Rev 0 5 49 SILICON LABS 5153 6
160. nd the device can enter SONET SDH compliant digital hold If DIGHOLDVALID is not active the part will enter VCO freeze instead of digital hold e Rev 0 5 87 SILICON LABS 5153 Table 42 Digital Hold History Delay HIST DEL 4 0 History Delay Time ms HIST DEL 4 0 History Delay Time ms 00000 0 0001 10000 6 55 00001 0 0002 10001 13 00010 0 0004 10010 default 26 00011 0 0008 10011 52 00100 0 0016 10100 105 00101 0 0032 10101 210 00110 0 0064 10110 419 00111 0 01 10111 839 01000 0 03 11000 1678 01001 0 05 11001 3355 01010 0 10 11010 6711 01011 0 20 11011 13422 01100 0 41 11100 26844 01101 0 82 11101 53687 01110 1 64 11110 107374 01111 3 28 11111 214748 Table 43 Digital Hold History Averaging Time HIST AVG 4 0 History Averaging Time ms HIST AVG 4 0 History Averaging Time ms 00000 0 0000 10000 26 00001 0 0004 10001 52 00010 0 001 10010 105 00011 0 003 10011 210 00100 0 006 10100 419 00101 0 012 10101 839 00110 0 03 10110 1678 00111 0 05 10111 3355 01000 0 10 11000 default 6711 01001 0 20 11001 13422 01010 0 41 11010 26844 01011 0 82 11011 53687 01100 1 64 11100 107374 01101 3 28 11101 214748 01110 6 55 11110 429497 01111 13 11111 858993 If a hi
161. ntil that input clock is validated over a designated time period The time to clear LOSn INT after valid input clock appears is listed in Table 8 AC Characteristics All Devices If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over 6 9 1 1 Narrowband LOS Algorithm Si5316 Si5323 Si5366 The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal For the Si5316 the output of divider N3 See Figure 1 is used The LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input clock transitions If the LOS monitor detects twice the normal number of samples without a clock edge LOSn INT alarm is declared Table 8 AC Characteristics All Devices gives the minimum and maximum amount of time for the LOS monitor to trigger 6 9 1 2 Wideband LOS Algorithm Si5322 Si5365 Each input clock is divided down to produce 78 kHz to 1 2 MHz signal before entering the LOS monitoring circuitry The same LOS algorithm as described in the above section is then used 6 9 2 FOS Alarms Si5365 and Si5366 If FOS alarms are enabled See Table 32 the internal frequency offset alarms FOSn INT indicate if the input clocks are within a specified frequency band relative to the frequency of CKIN2 The frequency offset monitoring circuitry compares
162. ode in which the selected input clock is fed directly to all enabled output buffers bypassing the DSPLL In PLL bypass mode the input and output clocks will be at the same frequency PLL bypass mode is useful in a laboratory environment to measure system performance with and without the effects of jitter attenuation provided by the DSPLL The DSBL2 BYPASS pin is used to select the PLL bypass mode according to Table 31 Table 31 DSBL2 BYPASS Pin Settings DSBL2 BYPASS Function L CKOUT2 Enabled M CKOUT2 Disabled H PLL Bypass Mode w CKOUT2 Enabled Internally the bypass path is implemented with high speed differential signaling for low jitter Bypass mode does not support CMOS clock output 6 9 Alarms Summary alarms are available to indicate the overall status of the input signals and frame alignment Si5366 only Alarm outputs stay high until all the alarm conditions for that alarm output are cleared 6 9 1 Loss of Signal Alarms Si5316 Si5322 Si5323 Si5365 Si5366 The device has loss of signal circuitry that continuously monitors CKINn for missing pulses The LOS circuitry generates an internal LOSn_INT output signal that is processed with other alarms to generate CnB An LOS condition on CKIN1 causes the internal LOS1_INT alarm to become active Similarly an LOS condition on CKINn causes the LOSn_INT alarm to become active Once a LOSn_INT alarm is asserted on one of the input clocks it remains asserted u
163. of integer relationship to most of the expected output frequencies If for instance an output frequency of 457 14 MHz 2 4 x 114 285 MHz were desired it would be preferable not to use the 114 285 MHz crystal as the reference For a more detailed study of this see Appendix G Near Integer Ratios on page 162 e Rev 0 5 123 SILICON LABS Si53xx RM High Reference Frequency When selecting a reference frequency with all other things being equal the higher the reference frequency the lower the output jitter Figures 63 and 64 illustrate this For a discussion of the available reference frequencies see section Resonator External Clock Selection on page 119 37 MHz thru 163 MHz Ext Ref 155 52 MHz in 622 08 MHz out 0 20 80 100 Phase Noise dBc Hz 120 140 160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency Hz Dark Blue 37 MHz Violet 55 MHz Light Blue 109 MHz Yellow Green 163 MHz Figure 63 Jitter vs Reference Frequency 1 of 2 8 124 Rev 0 5 e SILICON LABS Si53xx RM 41 MHz thru 180 MHz Ext Ref 155 52 MHz in 622 08 MHz out Phase Noise dBc Hz 1111 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency Hz Dark Blue 41 MHz Light Blue 61 MHz Red 125 5 MHz Green 180 MHz Figure 64 Jitter vs Reference Frequency 2 of 2 All phase noise number
164. ol DSPLL CKOUT_1 CKOUT_2 SFOUT 1 0 CKOUT 2 CKOUT 2 DBL2 BY VDD GND Figure 3 515322 Low Jitter Clock Multiplier Block Diagram SILICON LABS Rev 0 5 19 Si53xx RM 3 4 515323 The Si5323 is jitter attenuating precision clock multiplier for high speed communication systems including SONET OC 48 OC 192 Ethernet Fibre Channel and broadcast video HD SDI 3G SDI The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequency multiplied clock outputs ranging from 8 kHz to 1050 MHz The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET Ethernet Fibre Channel and broadcast video rates The DSPLL loop bandwidth is digitally selectable providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the 515323 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 6 Pin Control Parts 515316 515322 515323 515365 515366 on page 50 for a complete description Xtal or Refclock RATE 1 0 XB XA P 0 CKIN 1 2 CKOUT_1 CKIN 1 4 CKOUT 1 DSPLL9 2 2 2 SFOUT 1 0 2 ma CKOUT_2 CKOUT 2 CIB Signal AUTOSEL gt PD Bandwidth ndwi CSICA lt Control BWSEL 1 0
165. ommand to start its calibration Any changes to the CMODE pin require that RST be toggled to reset the part The power up default register values are given in the data sheets for these parts e Rev 0 5 101 SILICON LABS Si53xx RM 7 13 Serial Microprocessor Interface When configured in control mode CMODE L the control interface to the device is a 2 wire bus for bidirectional communication The bus consists of a bidirectional serial data line SDA and a serial clock input SCL Both lines must be connected to the positive supply via an external pull up In addition an output interrupt INT is provided with selectable active polarity determined by NT POL bit Fast mode operation is supported for transfer rates up to 400 kbps as specified in the I C Bus Specification standard To provide bus address flexibility three pins A 2 0 are available to customize the LSBs of the device address The complete bus address for the device is as follows 110 1 A 2 A 1 A 0 R W Figure 34 shows the command format for both read and write access Data is always sent MSB first The timing specifications and timing diagram for the 2 bus can be found in the 12 Specification standard fast mode operation See http www standardics nxp com literature books i2c pdf i2c bus specification pdf The maximum 2 clock speed is 400 kHz Byte Address A Data Data A P S Slave Address 0 A
166. on An internal self calibration ICAL is performed before operation to optimize loop parameters and jitter performance While the self calibration is being performed the DSPLL is being internally controlled by the self calibration state machine and the LOL alarm will be active for narrowband parts The self calibration time is given in Table 8 AC Characteristics All Devices Any of the following events will trigger a self calibration m Power on reset POR m Release of the external reset pin RST transition of RST from 0 to 1 m Change FRQSEL FRQTBL BWSEL or RATE pins m Internal DSPLL registers out of range indicating the need to relock the DSPLL In any of the above cases an internal self calibration will be initiated if a valid input clock exists no input alarm and is selected as the active clock at that time For the Si5316 Si5323 and Si5366 the external crystal or reference clock must also be present for the self calibration to begin If valid clocks are not present the self calibration state machine will wait until they appear at which time the calibration will start All outputs are on during the calibration process After a successful self calibration has been performed with a valid input clock no subsequent self calibrations are performed unless one of the above conditions are met If the input clock is lost following self calibration the device enters digital hold mode When the input clock retu
167. on chip voltage regulators with excellent PSRR The Si5374 is ideal for providing clock multiplication and jitter attenuation in high port count optical line cards requiring independent timing domains Input Stage Bypass Synthesis Stage Output Stage CKIN1P A CKIN1N A j not CKIN2P A CKIN2N j noo i Internal Osc PLL Bypass B CKIN3N B 14 EZ CKIN4N B Internal Osc CKIN5P_C owe gt CKIN6P_C CKIN6N_C gt Internal Osc CKIN7P_D CKIN7N_D NGI CKIN8P_D CKIN8N D N32 Nc2 Internal Osc PLL Bypass Status Control High PSRR 00 4 CS lt Voltage Regulator GND OSC P N Low Jitter SCL SDA LOL q IRQ q XO or Clock PLL Bypass gt gt NC2 1 PLL Bypass gt gt CKOUTIP A gt CKOUTIN A es HS gt CKOUT2P A gt CKOUT2N A PLL Bypass NC1 gt NC2 CKOUT4P_B I CKOUTAN B o PT gt CKOUTSP C gt lt gt CKOUT5N gt NC2 gt CKOUT6P_C PLL Bypass gt CKOUT6N p CKOUTS3P B gt CKOUT3N B YE es HS PLL Bypass fosc NC1 HS PLL Bypass gt fosc NC1 HS gt CKOUT8P D E
168. ontrolled Parts 515319 515324 515325 515326 515327 515367 515368 515369 515374 515375 on page 76 for a complete description BYPASS DSBL2 3 1 2 Y dium p 2 CKOUT_1 NC1 gt CKIN_2 2 L 0 CKOUT 1 CKIN 2 N3 2 DSPLL fosc _ gt CKOUT_2 2h Af Ns N1_HS gt NC2 e RT KOUT 2 7 DSBL2 BYPASS 4 2 FN gt CKOUT_3 d CKOUT 3 DSBL34 gt CKOUT_4 gt CKOUT 4 CKOUT_5 2 lt L NC5 D 2 gt CKOUT 5 C3B 4 INT DSBL5 ciae 2 lt 50 51 CAA 4 ee 122215 9 Y rae ae S258 ale Ble lt lt o Figure 11 515367 Clock Multiplier Block Diagram SILICON LABS Rev 0 5 27 Si53xx RM 3 12 515368 The Si5368 is a jitter attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The device provides virtually any frequency translation combination across
169. pe Shots 109 8 3 Typical Scope Shots for SFOUT Options 110 8 4 Crystal Reference Clock Interfaces 515316 Si5319 Si5323 515324 515326 515327 515366 515368 515369 515374 515375 113 8 5 Three Level 3L Input Pins No External Resistors 115 8 6 Three Level 3L Input Pins With External Resistors 116 S Power SUDDIV amer bb acea s OR een 117 10 Packages and Ordering Guide 118 Appendix A Narrowband References 119 Appendix B Frequency Plans and Jitter Performance Si5316 Si5319 515323 515324 515326 515327 515366 515368 515369 515374 915375 eii Iu or ee 121 Appendix C Typical Phase Noise Plots 126 Appendix D Alarm Structure ca ere RR 5 ew RR Rara 144 Appendix E Internal Pullup Pulldown by Pin 147 Appendix F Typical Performance Bypass Mode PSRR Crosstalk Output 2 2 2 154 Appendix G Near Integer 162 Appendix H Jitter Attenuation and Loop BW 164 Appendix I Si5374
170. peration is CKIN1 followed by CKIN2 and finally digital hold mode The inverse input clock priority arrangement is available through the CK PRIOR bits as shown in the Si5325 Si5326 and 515374 For the default priority arrangement automatic switching mode selects CKIN1 at powerup reset or when in revertive mode with no alarms present on CKIN1 If an alarm condition occurs on CKIN1 and there are no active alarms on CKIN2 then the device switches to CKIN2 If both CKIN1 and CKIN2 are alarmed then the device enters digital hold mode If automatic mode is selected and the frequency offset alarms FOS1 INT and FOS2 INT are disabled automatic switching is not initiated in response to FOS alarms The loss of signal alarms LOS1 INT and LOS2 INT are always used in making automatic clock selection choices In non revertive mode once CKIN2 is selected CKIN2 selection remains as long as it is valid even if alarms are cleared on CKIN1 lt Rev 0 5 83 SILICON LABS Si53xx RM 7 4 2 2 Detailed Automatic Clock Selection Description Si5367 Si5368 Si5369 The prioritization of clock inputs for automatic switching is shown in Table 41 For example if CK CONFIG REG 0 and the desired clock priority order is CKIN4 CKIN3 CKIN2 and then CKIN1 as the lowest priority clock the user should set CK PRIOH1 1 0 11 CK PRIOR2 1 0 10 CK PHRIOR3S 1 0 01 and CK PRIORd4 1 0 00 Table 41 Input Clock Priority for Auto Switching
171. pliers 515325 and 515367 are microprocessor controlled clock multipliers that can be controlled via an I C or SPI interface These devices accept clock inputs ranging from 10 MHz to 710 MHz and generate multiple independent synchronous clock outputs ranging from 10 MHz to 945 MHz and select frequencies to 1 4 GHz The Si5325 and 515367 support a subset of the frequency translations available in the 515319 515324 515326 515327 515368 and 515369 jitter attenuating clock multipliers The 515325 and 515367 can accept input clocks at different frequencies and generate output clocks at different frequencies The 515322 515325 515365 and 515367 support a digitally programmable loop bandwidth that ranges from 150 kHz to 1 3 MHz No external components are required for these devices LOS and FOS monitoring is available for these devices as described above 515374 and 515375 are quad DSPLL versions of the 515324 and 515319 respectively Each of the four DSPLLs can operate at completely independent frequencies The only resources that they share are a common 2 bus a common XA XB jitter reference oscillator The Si5375 consists of four one input and one output DSPLLs The Si5374 consists of four two input and two output DSPLLs with very low loop bandwidth The Any Frequency Precision Clocks have differential clock output s with programmable signal formats to support LVPECL LVDS CML and CMOS loads If the CMOS signal format is sel
172. pp 0 1 Ulpp Jitter Gen OC 48 27 41 4 02 PSims PSrms 0 01 Ulims Notes 1 Test condition fiy four 622 08 MHz LVPECL clock input 1 19 Vppd with 0 5 ns rise fall time 20 80 LVPECL clock output BWSEL 1 0 loop bandwidth settings provided in Pin Descriptions 114 285 MHz 3rd OT crystal used as XA XB input Vpp 2 2 5 V 85 Table 10 Jitter Generation 515322 515325 515365 515367 Test Condition Measurement DSPLL Filter MHz Bandwidth kHz JGEN 0 02 80 1096 49 DSrms 4 80 1096 23 DSrms 0 05 80 1096 47 DSrms JEEN 0 012 20 1096 48 DSrms Test condition fiy four 622 08 MHz LVPECL clock input 1 19 Vppd with 0 5 ns rise fall time 20 80 clock output 2 BWSEL 1 0 loop bandwidth settings provided in Pin Descriptions 44 Rev 0 5 e SILICON LABS Si53xx RM Table 11 Thermal Characteristics Parameter Test Condition Devices Thermal Resistance Junction to Ambient Still Air Si5316 5 5319 515322 Si5323 515324 515325 515365 15366 515367 515368 Thermal Resistance Junction to Case Still Air Si5316 515319 515322 Si5323 515324 515325 e Rev 0 5 45 SILICON LABS Si53xx RM 5 DSPLL All Devices All members of the Any Frequency Precision Clocks family incorporate a phase locked loop PLL that utilizes S
173. ppa t gt CKOUT7P D gt gt CKOUT7N D gt CKOUT8N_D Figure 14 Si5374 Functional Block Diagram 30 Rev 0 5 lt SILICON LABS Si53xx RM 3 16 515375 The Si5375 is a highly integrated 4 PLL jitter attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance Each of the DSPLL clock multiplier engines accepts an input clock ranging from 2 kHz to 710 MHz and generates an output clock ranging from 2 kHz to 808 MHz Each DSPLL provides virtually any frequency translation combination across this operating range For asynchronous free running clock generation applications the Si5375 s reference oscillator can be used as a clock source for any of the four DSPLLs The 515375 input clock frequency and clock multiplication ratio are programmable through an 12C interface The 515375 is based on Silicon Laboratories third generation DSPLL technology which provides any frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components Each DSPLL loop bandwidth is digitally programmable from 60 Hz to 8 kHz providing jitter performance optimization at the application level The device operates from a single 1 8 or 2 5 V supply with on chip voltage regulators with excellent PSRR The Si5375 is ideal for providing clock multiplication and jitter attenuation in high port coun
174. puts after having been divided by their respective N3 dividers must result in the same f3 frequency because the phase frequency detector can operate at only one frequency at one time 7 1 4 Loop Bandwidth 515319 515326 Si5368 515375 The device functions as a jitter attenuator with digitally programmable loop bandwidth BW The loop bandwidth settings range from 60 Hz to 8 4 kHz and are set using the BWSEL REG 3 0 register bits The device operating frequency should be determined prior to loop bandwidth configuration because the loop bandwidth is a function of the phase detector input frequency and the PLL feedback divider See DSPLLsim for a table of BWSEL REG and associated loop bandwidth settings For more information the loop BW and its effect on jitter attenuation see Appendix H Jitter Attenuation and Loop BW on page 164 7 1 4 1 Low Loop Bandwidth Si5324 Si5327 Si5369 Si5374 The loop BW of the 515324 515327 515369 515374 is significantly lower than the BW of the 515326 available Si5324 27 69 74 loop bandwidth settings and their register control values for a given frequency plan are listed by DSPLLsim Revision 4 0 1 or higher or in Sib37xDSPLLsim Compared to the 515326 the BW Si5324 27 69 74 settings are approximately 16 times lower which means that the Si5324 27 69 74 loop bandwidth ranges from about 4 to 525 Hz 7 1 5 Lock Detect 515319 515326 515327 515368 515369 515374 Si5375 The device has a
175. r precision jitter attenuator for high speed communication systems including OC 48 OC 192 10G Ethernet and 10G Fibre Channel The Si5316 accepts dual clock inputs in the 19 38 77 155 311 or 622 MHz frequency range and generates a jitter attenuated clock output at the same frequency Within each of these clock ranges the device can be tuned approximately 14 higher than nominal SONET SDH frequencies up to a maximum of 710 MHz in the 622 MHz range The DSPLL loop bandwidth is digitally selectable providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5316 is ideal for providing jitter attenuation in high performance timing applications See 6 Pin Control Parts Si5316 515322 515323 515365 515366 on page 50 for a complete description Xtal or Refclock RATE 1 0 CK1DIV Y SFOUT 1 0 1 2 E 1 fosc 2 DSPLL CKOUT CKIN 2 fs CKOUT CKIN 2 DBL BY CK2DIV 81 1 Signal Detect RST gt Bandwidth Control BWSEL 1 0 Control FRGSEL 1 0 T T Frequency iot Control lt VDD GND Figure 1 Si5316 Any Frequency Jitter Attenuator Block Diagram SILICON
176. r 50 0005 MHZ Span 100 0008 MHz Noise 20 00 Analysis Range X Band Marker Analysis Range Band Marker Intg Noise 35 6961 dBc 40 MHz 30 00 RMS Noise 23 2119 mrad 1 32995 deg RMS Jitter 5 32718 psec 40 00 Residual 10 2221 kHz 100 0 110 0 20 0 160 0305 1 101 100 1M 10M Figure 79 86 685 MHz In 693 493 MHz Out amp 140 Rev 0 5 s SILICON LABS Si53xx RM 155 52 MHz and 156 25MHz in 622 08 MHz out 0 00E 00 2 00E 01 4 00E 01 6 00E 01 8 00E 01 1 00E 02 Phase Noise dBc Hz 1 20E 02 1 40E 02 1 60E 02 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Blue 155 52 MHz Red 156 25 MHz Figure 80 155 52 MHz and 156 25 MHz In 622 08 MHz Out Table 67 Jitter Values for Figure 80 Jitter Bandwidth 155 52 MHz Input 156 25 MHz Input Jitter RMS Jitter RMS Broadband 100 Hz to 10 MHz 4432 fs 4507 fs OC 48 12 kHz to 20 MHz 249 fs 251 fs OC 192 20 kHz to 80 MHz 274 fs 271 fs OC 192 4 MHz to 80 MHz 166 fs 164 fs OC 192 50 kHz to 80 MHz 267 fs 262 fs Broadband 800 Hz to 80 MHz 274 15 363 fs e Rev 0 5 141 SILICON LABS Si53xx RM Phase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 999 999985 MHz r3 5840 dBm 51 90 Hz 67 5770 X Start 12 kHz 10 00 Stop 20 MHz Center 10 006 MHz Span 19 988 MHZ 20 00 NQisal Analysis
177. rns the device relocks to the input clock without performing a self calibration Narrow band devices only 6 2 1 Input Clock Stability during Internal Self Calibration 515316 515322 515323 515365 515366 An exit from reset must occur when the selected CKINn clock is stable in frequency with a frequency value that is within the operating range that is reported by DSPLLsim The other CKINs must also either be stable in frequency or squelched during a reset 6 2 2 Self Calibration caused by Changes in Input Frequency 515316 515322 515323 515365 515366 If the selected CKINn varies by 500 ppm or more in frequency since the last calibration the device may initiate a self calibration 6 2 3 Recommended Reset Guidelines 515316 515322 515323 515365 515366 Follow the recommended RESET guidelines Table 20 and Table 21 when reset should be applied a device e Rev 0 5 65 SILICON LABS 5153 Table 20 515316 515322 515323 Pins and Reset Pin 55316 Pin 515322 Pin 515323 Pin Must Reset after Changing Name Name Name 2 N A FRQTBL FRQTBL Yes 11 RATE 0 N A RATE 0 Yes 14 DBL_BY DBL2_BY DBL2_BY No 15 RATE1 N A RATE1 Yes 19 N A N A DEC No 20 N A N A INC No 22 BWSELO BWSELO BWSELO Yes 23 BWSEL1 BWSEL1 BWSEL1 Yes 24 FRQSELO FRQSELO FRQSELO Yes 25 FRQSEL1 FRQSEL1
178. rtion of read operations During write operations data is driven into the device via the SDI pin MSB first The SDO pin will remain high impedance during write operations Data always transitions with the falling edge of the clock and is latched on the rising edge The clock should return to a logic high when no transfer is in progress The SPI port supports continuous clocking operation where SSb is used to gate two or four byte transfers The maximum speed supported by SPI is 10 MHz lt Rev 0 5 103 SILICON LABS Si53xx RM SS SDI Instruction Byte Address or Write Data SDO High Impedance Figure 36 SPI Write Set Address Command Ss sek so XQ 5 KA AKA AKA Read Command SDO High Impedance 7 68 5 4 3 2 3 0 i Read Data Figure 37 SPI Read Command 7 14 1 Default Device Configuration For ease of manufacture and bench testing of the device the default register settings have been chosen to place the device in a fully functional mode with an easily observable output clock Refer to the data sheet for your device 7 15 Register Descriptions See the device data sheet for a full description of the registers 7 16 DSPLLsim Configuration Software To simplify frequency planning loop bandwidth selection and general device configuration of the Any Frequency Precision Clocks Silicon Laboratories has a configuration utility DSPLLsim for the 5319 Si5325
179. s CKIN1 3 amp CKIN2 4 clock FSYNC pairs 00 CKIN1 CKIN1 CKIN3 01 CKIN2 CKIN2 CKIN4 10 CKIN3 Not used 11 CKIN4 Not used Note Setting the CKSEL PIN register bit to one allows the CS 1 0 pins to continue to control input clock selection If CS PIN is set to zero the CKSEL REG 1 0 register bits perform the input clock selection function 82 Rev 0 5 lt SILICON LABS Si53xx RM Table 39 Manual Input Clock Selection Si5324 Si5325 Si5326 Si5374 CKSEL or CS pin Active Input Clock 0 CKIN1 1 CKIN2 If the selected clock enters an alarm condition the PLL enters digital hold mode The CKSEL_REG 1 0 controls are ignored if automatic clock selection is enabled 7 4 2 Automatic Clock Selection 515324 515325 515326 515367 515368 515369 515374 The AUTOSEL_REG 1 0 register bits sets the input clock selection mode as shown Table 40 Automatic switching is either revertive or non revertive Table 40 Automatic Manual Clock Selection AUTOSEL REG 1 0 Clock Selection Mode 00 Manual 01 Automatic Non revertive 10 Automatic Revertive 11 Reserved CKSEL PIN is of significance only when Manual is selected 7 4 2 1 Detailed Automatic Clock Selection Description 515324 515325 515326 515374 Automatic switching is either revertive or non revertive The default prioritization of clock inputs when the device is configured for automatic switching o
180. s are in fs RMS External Reference Frequency 37 41 55 61 109 125 5 163 180 Jitter Bandwidth MHz MHz MHz MHz MHz MHz MHz MHz SONET_OC48 12 kHz to 20 MHz 1092 858 633 715 330 321 292 298 SONET_OC192_A 20 kHz to 80 MHz 1086 855 639 698 356 335 325 331 SONET_OC192_B 4 MHz to 80 MHz 226 229 232 221 217 183 221 226 SONET OC192 C 50 kHz to 80 MHz 1028 797 597 651 340 316 314 320 BroadBand 800 Hz to 80 MHz 1165 956 728 773 423 375 393 393 e Rev 0 5 125 SILICON LABS Si53xx RM APPENDIX C TYPICAL PHASE NOISE PLOTS Introduction The following are some typical phase noise plots The clock input source is a Rohde and Schwarz model SMLO3 RF Generator Except as noted the phase noise analysis equipment is the Agilent E5052B Also except as noted the Any Frequency part was an Si5326 operating at 3 3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm Note that as with any PLL the output jitter that is below the loop bandwidth of the Any Frequency device is caused by the jitter of the input clock not the Any Frequency Precision Clock Except as noted the loop bandwidths were 60 Hz to 100 Hz bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 622 0808B0 M 2 6140 dBm j 1 12 ktiz 119 9510 dBc Hz 52 660 458 kHz 120 9693 dBc Hz 10 00 x Start 12 kHz Stop 20 MHz Cent
181. s f3 for every new frequency plan that it generates f3 has a range from 2 kHz minimum up to 2 MHz maximum The two main causes of a low are a low clock input frequency which establishes an upper bound on and PLL multiplier ratio that is comprised of large and mutually prime nominators and denominators Specifically for CKOUT x P Q if P and Q are mutually prime and large in size then f3 may have a low value Very low values of f3 usually result in extra jitter as can be seen in Figure 60 Phase Noise versus 155 52 MHz in 622 08 MHz out 1709 kHz _ 40 855 kHz N h 427 kHz m 60 214 kHz 80 107 kHz 54 kHz z 100 27 kHz o E AL 1274 13 kHz P me 120 neue 7 kHz p 8 kHz 140 160 10 100 1000 10000 100000 1000000 1E 07 1 08 Frequency Hz Figure 60 Jitter vs f3 For the f3 study the input output and DCO frequencies were held constant while the dividers were manipulated by hand to artificially reduce the value of f3 Two effects can be seen as f3 approaches the 2 kHz lower limit there are spur like spikes in the mid band and the noise floor is elevated at the near end It is also clear that once f3 is above roughly 50 kHz there is very little benefit from further increasing Note that the loop bandwidth for this study was 60 Hz and any noise below 60 Hz is a result of the input clo
182. se 74 7397 dBc 19 69 MHz 40 00 RMS Noise 259 136 urad 14 8474 mdeg RMS pitter 278 01 fsec 50 00 Residual FM 1 38416 KHz 90 00 110 0 140 0 150 0 160 0 10 7100 dk 108 1001 A jM Figure 69 27 MHz In 148 35 MHz Out Light Trace BW z 6 Hz Dark Trace BW z 110 Hz Si5324 130 0 5 s SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz Carrier 491 519998 MHz 4 3243 dB 0 0009 X Start 100 Hz Stop 40 MHz 10 00 Center 20 00005 MHz Span 39 9999 MHz Noise 20 00 Analysis Range x Band Marker Analysis Range Y Band Marker Intg Noise 64 3401 dBc 40 MHz 30 00 RMS Noise 858 048 prad 49 1626 mdeg RMS Jitter 277 837 fsec 40 00 Residual FM 7 5726 kHz 50 00 60 00 70 00 80 00 90 00 100 0 110 0 20 0 30 0 140 0 150 0 160 0 10 100 1 10k 100 1M 10M Figure 70 61 44 MHz In 491 52 MHz Out Loop BW 7 Hz 515324 s Rev 0 5 131 SILICON LABS Si53xx RM bPhase Noise 10 00dB Ref 0 000dBc Hz 0 000 Carrier 672 162617 0 0972 dBm 7 100 2 50 3913 dBc Hz Xt Start 12 kHz 10 00 Stop 20 2 Center 10 006 MHz Span 19 988 MHz 20 00 Nois Analysis Range x Band Marker Analysis Range Y Band Marker 30 00 Intg Noise 60 0979 dBc 19 69 MHz RMS Noise 1 39837 mrad 80 1205 mdeg 40 00 RMS Jitter 331 106 fsec Residual FM 3 36172 kHz 50 00
183. t compliant with SONET SDH MTIE requirements applications requiring SONET SDH MTIE requirements should use the 515324 515326 515368 515369 or 515374 Unlike the 515325 and 515367 the Si5319 s VCO freeze is controlled by the XA XB reference which is typically a crystal resulting in greater stability For the 515319 515327 and 515375 VCO freeze is similar to the Digital Hold function of the 515326 515368 and 515369 except that the HIST AVG and HIST DEL registers do not exist 7 6 5 Digital Hold versus VCO Freeze Figure 31 below is an illustration of the difference in behavior between Digital Hold and VCO Freeze freq x i VCO freeze Input clock drifts Digital Hold HIST_AVG c HIST DEL gt time Clock input LOS alarm occurs CADI iS Start Digital hold Figure 31 Digital Hold vs VCO Freeze Example e Rev 0 5 89 SILICON LABS Si53xx RM 7 7 Output Phase Adjust Si5326 Si5368 The device has a highly accurate digitally controlled device skew capability For more information on Output Phase Adjustments see both DSPLLsim and the respective data sheets Both can be downloaded by going to www silabs com timing and clicking on Documentation at the bottom of the page 7 7 1 Coarse Skew Control Si5326 Si5368 With the INCDEC_PIN register bit set to 0 pin control off overall device skew is controlled via the CLAT 7 0 register bits This skew control has a
184. t optical line cards requiring independent timing domains Input Stage Bypass Synthesis Stage Output Stage CKINIP A CKININ A N31 ou lonitor Sables gt CKOUTIP_A DSPLL A NC1 HS gt CKOUTIN A gt N32 PLL Bypass CKINIP B CKIN1N B m fees DLL Bypass gt CKOUTIP_B PLL s NC1_HS gt CKOUTIN B PLL Bypass gt CKINIP C CKININ C 4 2 fisse gt CKOUTIP_C PLL 5 C NC1 HS lt gt CKOUTIN C PLL Bypass CKINIP D CKININ D P Bypass gt CKOUTIP D e 6 gt CKOUTIN D Rma Status Control High PORR Men CSq lt Voltage Regulator GND OSC P N Low Jitter SCL SDA LOL q XO or Clock Figure 15 Si5375 Functional Block Diagram e Rev 0 5 31 SILICON LABS 5153 4 Device Specifications The following tables are intended to simplify device selection The specifications in the individual device data sheets take precedence over this document Refer to the respective device data sheet for devices not listed in the tables below Table 3 Recommended Operating Conditions Parameter Symbol Test Condition Ambient 25 Temperature Supply Voltage 3 3 V Nominal 3 3 During Normal Operation 2 5 V Nominal 2 25 2 5 1 8 V Nominal 1 71 1 8 1 89
185. the frequency of the input clock s with CKIN2 If the frequency offset of an input clock exceeds a preset frequency offset threshold an FOS alarm FOSn_INT is declared for that clock input Note that FOS monitoring is not available on CKIN3 and CKIN4 if CK_CONF 1 The device supports FOS hysteresis per GR 1244 CORE making the device less susceptible to FOS alarm chattering A TCXO or OCXO reference clock must be used in conjunction with either the SMC or Stratum 3 3E settings Note that wander can cause false FOS alarms e Rev 0 5 73 SILICON LABS Si53xx RM Table 32 Frequency Offset Control FOS CTL FOS_CNTL Meaning L FOS Disabled M Stratum 3 3E FOS Threshold 12 ppm H SONET Minimum Clock Threshold 48 ppm 6 9 3 FSYNC Align Alarm Si5366 and CONF 1 and FRQTBL L At power up or any time after the PLL has lost lock and relocked the device automatically performs a realignment of FS_OUT using the currently active sync input After this as long as the PLL remains in lock and a realignment is not requested FS_OUT will include a fixed number of high speed clock cycles even if input clock switches are performed If many clock switches are performed it is possible that the input sync to output sync phase relationship will shift due to the accumulated residual phase transients of the phase build out circuitry The internal ALIGN_INT signal is asserted when the accumulated phase errors exce
186. ting Internal 79 7 2 2 Input Clock Stability during Internal Self Calibration 80 7 2 3 Self Calibration Caused by Changes in Input Frequency 80 7 2 4 Narrowband Input to Output Skew Si5319 Si5324 Si5326 515327 515368 515369 9i5374 515375 2 4 Seale enu ep av Tube 80 7 2 5 Clock Output Behavior Before and During ICAL 80 7 3 Input Clock Configurations 515367 and 515368 81 Z4 np t Glock Control sssr oa d ened d ueser Rut on SN Sp ee ee ewes 81 7 4 1 Manual Clock Selection 515324 515325 515326 515367 515368 515369 5 5374 82 7 4 2 Automatic Clock Selection 515324 515325 515326 515367 515368 515369 515374 iue ete a om ee ee 83 7 4 3 Hitless Switching with Phase Build Out 515324 515326 515327 515368 515369 5 5374 84 7 5 515319 515324 515326 515327 515368 515369 515374 Rev 0 5 lt SILICON LABS Si53xx RM and 95375 Free unm Moder ine wis eR 85 7 5 1 Free Run Mode Programming Procedure 85 7 5 2 Clock Control Logic in Free Run
187. tion 515322 515325 515365 515367 44 Table 11 Thermal Characteristics _ 45 Table 12 515316 515322 515323 515365 and Si5366 Key Features 50 Table 13 Frequency 50 Table 14 Input Divider Settings 51 Table 15 515316 Bandwidth Values 51 Table 16 SONET Clock Multiplication Settings FRQTBL L 52 Table 17 Datacom Clock Multiplication Settings FRQTBL M CONF 20 57 Table 18 SONET to Datacom Clock Multiplication Settings 61 Table 19 Clock Output Divider Control 01 34 64 Table 20 515316 515322 515323 Pins and Reset 66 Table 21 515365 515366 Pins and 5 66 Table 22 Manual Input Clock Selection 515316 515322 515323 AUTOSEL L 67 Table 23 Manual Input Clock Selection 515365 515366 AUTOSEL L 67 Table 24 Automatic Manual Clock Selection 68 Table 25 Clock Active Indicators AUTOSEL M or H 515322 and Si5323 68 Table 26 Clock Active Indicators AUTOSEL M or H 515365 Si5367 68 Table 27 Input Clock Priority for Auto Switching 515322 5532
188. tive CLKINnRATE of 1 as shown in Table 51 Table 51 CLKnRATE Registers CLKnRATE Divisor P or Q Min Frequency MHz Max Frequency MHz 0 1 10 27 1 2 25 54 2 4 50 105 3 8 95 215 4 16 190 435 5 32 375 710 For example to monitor a 544 MHz clock at CKIN1 with a FOS reference of 34 MHz at CKIN2 CLK1RATE 5 CLK2RATE 1 FOSREFSEL 2 0 010 98 Rev 0 5 lt SILICON LABS Si53xx RM 7 11 3 2 515319 515324 515325 515326 515327 515374 515375 A LOS condition causes the associated LOS1_INT 1052 INT read only register bit be set A LOS condition on CKIN 1 will also be reflected onto C1B if CK1 BAD PIN 1 Likewise a LOS condition on CKIN 2 will also be reflected onto C2B if CK2 BAD PIN 1 A FOS condition causes the associated FOS1_INT FOS2 INT read only register bit to be set FOS monitoring is enabled or disabled using the FOS EN bit If FOS is enabled FOS EN 1 and BAD 1 a FOS condition will also be reflected onto its associated output pin C1B or C2B If FOS is disabled FOS EN 0 the FOS1 INT and FOS2 INT register bits do not affect the C1B C2B alarm outputs respectively Once an LOS or FOS alarm is asserted on one of the input clocks it is held high until the input clock is validated over a designated time period The validation time is programmable via the VALTIMET1 0 register bits as shown in Table 48 on
189. uency Selection CK CONF 1 92 Table 45 Common NC5 Divider 05 93 Table 46 Alignment Alarm Trigger Threshold 93 Table 47 Output Signal Format Selection 95 Table 48 Loss of Signal Validation 96 Table 49 Loss of Signal 96 Table 50 FOS Reference Clock Selection 98 Table 51 CLKnRATE Registers 98 Table 52 Alarm Output Logic Equations 515367 515368 and 515369 CONFIG REG 0 99 Table 53 Alarm Output Logic Equations 515368 CKCONFIG_REG 1 100 Table 54 Lock Detect Retrigger Time 101 Table 55 SPI Command Format lg 103 Table 56 Output Driver 107 Table 57 Disabling Unused Output 108 Table 58 Output Format Measurements 109 Table 59 Approved Grystalss uiv teh rb LEER ES cee 119 Table 60 XA XB Reference Sources and Frequencies 119 Table 61 Jitter Values for Figure 61 12
190. ure 9 515365 Low Jitter Clock Multiplier Block Diagram e Rev 0 5 25 SILICON LABS Si53xx RM 3 10 Si5366 The Si5366 is a jitter attenuating precision clock multiplier for high speed communication systems including SONET 48 192 Ethernet and Fibre Channel The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequency multiplied clock outputs ranging from 8 kHz to 1050 MHz The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET Ethernet Fibre Channel and broadcast video HD SDI 3G SDI rates The DSPLL loop bandwidth is digitally selectable from 60 Hz to 8 kHz providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5366 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 6 Pin Control Parts 515316 515322 515323 515365 515366 page 50 for a complete description RATE 1 0 Xtal ji Refclock BYPASS DSBL2 3 1 2 N3 1 1 B f m CKOUT 1 t H CKOUT 1 CKIN 2 2 N3 21 CKIN 2 f M DSPLL fosc s 1 CKOUT 2
191. witch back to CKIN1 when it subsequently returns m Forthe Si5319 e Clock selection is manual using an input pin e Clock switching is not hitless e 2 is not available 7 5 2 Clock Control Logic in Free Run Mode Noting that the mux that selects CKIN2 versus the XA XB oscillator is located before the clock selection and control logic when in Free Run mode operation all such logic will be driven by the XA XB oscillator not the pins For example when in Free Run mode the CK2B pin will reflect the status of the XA XB oscillator and not the status of the CKIN2 pins oN NH E e Rev 0 5 85 SILICON LABS Si53xx RM 7 5 3 Free Run Reference Frequency Constraints XA XB Frequency Min XA XB Frequency Max Xtal 109 MHz 125 5 MHz 3rd overtone 37 MHz 41 MHz Fundamental _ XA XB _ N31 N32 3 CKOUT XA XB All crystals and external oscillators must lie within these two bands e Not every crystal will work they should be tested e An external oscillator can be used at all four bands The frequency at the phase detector f3 must be the same for both CKIN1 and XA XB or else switching cannot be hitless To avoid spurs avoid outputs that are an integer or near integer of the XA XB frequency z Integer 7 5 4 Free Run Reference Frequency Constraints While in Free Run e CKOUT frequency tracks the reference frequency e For very low drift TCXO or OCXO reference is n
192. x 64 66 125 87 HMML 1 4 161 13 88 HMMM 1 644 53 89 255 238 690 57 90 HMHL 255 237 693 48 91 HMHM 657 42 1 6 64 66 106 25 92 HMML 1 4 164 36 93 HMMM 1 657 42 94 255 238 704 38 95 HMHL 255 237 707 35 96 HMHH 690 57 1 5 x 64 66 x 238 255 125 97 HHLL e 1 4 x 64 66 x 238 255 156 25 98 HHLM 1 4 x 238 255 161 13 99 HMML 1 4 172 64 100 HHLH 238 255 644 53 101 HMMM 1 690 57 lt Rev 0 5 59 SILICON LABS 5153 Table 17 Datacom Clock Multiplication Settings FRQTBL 0 Continued Setting FRQSEL 3 0 fin MHz Mult Factor four MHz 102 HHML 693 48 1 5 x 64 66 x 237 255 125 103 HHMM 1 4 x 64 66 x 237 255 156 25 104 HHMH 1 4 x 237 255 161 13 105 HMML 9 1 4 173 37 106 HHHL 237 255 644 53 107 HMMM 1 693 48 108 HHHM 704 38 1 6 x 64 66 x 238 255 106 25 109 HHLL 1 4 x 64 66 x 238 255 159 375 110 HHLM 1 4 x 238 255 164 36 111 HMML 1 4 176 1 112 HHLH 238 255 657 42 113 HMMM e 1 704 38 114 HHHH 707 35 1 6 x 64 66 x 237 255 106 25 115 HHMM 1 4 x 64 66 x 237 255 159 375 116 HHMH e 1 4 x 237 255 164 36 117 HMML 1 4 176 84 118 HHHL 237 255 657 42 119 HMMM 1 707 35 60 0 5 lt SILICON LABS Si53xx RM Table 18 SONET to Datacom Clock Multiplication Settings
193. x 66 64 657 4 50 MMHH 4 x 66 64 x 255 238 704 38 51 MHLL 4 x 66 64 x 255 237 707 35 52 MHLM 161 13 4 5 x 64 66 53 MHLH 255 238 172 64 54 MHML 255 237 173 37 55 MHMM 4 644 53 56 MHMH 4 x 255 238 690 57 57 MHHL 4 x 255 237 693 48 58 MHHM 164 36 2 3 x 64 66 106 25 59 MHLH 255 238 176 1 60 MHML 255 237 176 84 61 MHMM 4 657 42 62 MHMH 4 x 255 238 704 38 63 MHHL 4 x 255 237 707 35 64 MHHH 172 64 4 5 x 64 66 x 238 255 65 HLLL 64 66 x 238 255 156 25 66 HLLM 238 255 161 13 67 HLLH 4 x 238 255 644 53 68 MHMM 4 690 57 58 Rev 0 5 e SILICON LABS Si53xx RM Table 17 Datacom Clock Multiplication Settings FRQTBL M CK CONF 0 Continued Setting FRQSEL 3 0 fin MHz Mult Factor four MHz 69 HLML 173 37 4 5 x 64 66 x 237 255 125 70 HLMM 64 66 x 237 255 156 25 71 HLMH 237 255 161 13 72 HLHL 4 x 237 255 644 53 73 MHMM 4 693 48 74 HLHM 176 1 2 3 x 64 66 x 238 255 106 25 75 HLLL 64 66 x 238 255 159 375 76 HLLM 238 255 164 36 77 HLLH 4 x 238 255 657 42 78 MHMM 4 704 38 79 HLHH 176 84 2 3 x 64 66 x 237 255 106 25 80 HLMM 64 66 x 237 255 159 375 81 HLMH 237 255 164 36 82 HLHL 4 x 237 255 657 42 83 MHMM 9 4 707 35 84 HMLL 212 5 2 425 85 HMLM 425 1 425 86 HMLH 644 53 1 5

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