Home

Renesas 4513 Network Card User Manual

1. E 4513 4514 Group User s Manual FEATURES A TT APPLICATION 222220 aeae aa Aa aA EEEE AEEA BLOCK DIAGRAM MEE Table of contents CHAPTER 2 APPLICATION 2 2 RELIER 2 2 PR 2 4 e 2 7 ARUM ME M MEE 2 9 2 11 XE 2 11 2 2 2 elateditegisterS 5tut tu eto 2 13 2 16 E 2 25 Na eae Y 2 26 MM 2 26 2 27 TUNIS 2 30 EXTAT ME 2 39 mIRC TEN 2 40 2 44 __ ___ __ 2 40 D 2 41 2 42 EA 2 45 2 48 pn DTP 2 49 MM MO MM ME 2 50 T 2 51 a T 2 52 HE MON NEM
2. 1 58 Table 25 Product of built in PROM version nennen nenne 1 88 Fable 26 Programming adapters coii aeter sicat ec eaa de aee 1 89 CHAPTER 2 APPLICATION Table 2 1 1 control register PUO en trt tt ar Ee ceto 2 4 Table 2 1 2 Key on wakeup control register 2 5 Table 2 1 3 A D control eee ee Mee 2 5 Table 2 1 4 Direction register 0 2 6 Table 2 1 5 Timer control register WO eiit aite rt rece tta ade 2 6 Table 2 1 6 connections of unused pins sss 2 10 Table 2 2 1 Interrupt control register 1 2 14 Table 2 2 2 Interrupt control register 2 nnne 2 14 Table 2 2 3 Interrupt control register 1 00 entren nnn 2 15 Table 2 2 4 Interrupt control register 12 ssssssseeeeneeennn emen 2 15 Table 2 3 1 Interrupt control register eem eee 2 27 Table 2 3 2 Interrupt control register eene tee te iuc Le Ended 2 27 Table 2 3 3 Timer control register 1 2 28 Table 2 8 4 Timer control register W2 iacens eR edi cu ees 2 28 Table 2 3 5 Timer control register 3 2 29 Table 2 3 6 Timer control regist
3. AiN2 CMP1 O Ains CMP1 O P40 AIN4 P41 AIN5 P42 AIN6 P43 AIN7 Q A D control circuit A D interrupt Successive comparison register AD 10 operation signal 8 channel multi plexed analog switch Comparator register 8 Notes 1 This switch is turned ON only when A D converter is operating and generates the comparison voltage 2 Writing reading data to the comparator register is possible only in the comparator mode Q23 1 The value of the comparator register is retained even when the mode is switched to the A D conversion mode Q23 0 because it is separated from the successive comparison register AD Also the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits 3 The 4513 Group does not have ports P40 AIN4 P43 AIN7 and the IAP4 and instructions Fig 2 5 1 A D converter structure 4513 4514 Group User s Manual 2 49 APPLICATION 2 5 A D converter 2 5 1 Related registers 1 A D control register Q1 Analog input pin selection bits are assigned to register Q1 Set the contents of this register through register A with the TQ1A instruction The TAQ1 instruction can be used to transfer the contents of register Q1 to register A Table 2 5 1 shows the A D control register Q1 Table 2 5 1 A D control register Q1 A D control register Q1 at reset 00002 at power down state retained
4. Both edges detection circuit 3 1001 available 1 interrupt 1 available Timer 4 1 1ONot eave a interrupt 1 to available Data is set automatically from each reload register when timer 1 2 3 or 4 underflows Instruction clock auto reload function Notes 1 Timer 1 count start synchronous circuit is set D gt System reset by the valid edge of P30 INTO pin selected by bits 1 111 and 2 112 of register 11 WRST instruction 2 Timer 3 count start synchronous circuit is set Reset signal by the valid edge of P31 INT1 pin selected by bits 1 121 and 2 122 of register 12 3 Count source is stopped by clearing to 0 Fig 19 Timers structure 4513 4514 Group User s Manual 1 31 HARDWARE FUNCTION BLOCK OPERATIONS Table 10 Timer control registers Timer control register W1 at reset 00002 at RAM back up 00002 Stop state initialized Prescaler control bit Operating Instruction clock divided by 4 Prescaler dividing ratio selection bit Instruction clock divided by 16 Stop state retained Timer 1 control bit Operating Timer 1 count start synchronous circuit Count start synchronous circuit not selected control bit Timer control register W2 O O oO o Count start synchronous circuit selected reset 00002 at RAM back up
5. 42P2R A Plastic 42pin 450mil SSOP EIAJ Package Code JEDEC Code Weight g Lead Material SSOP42 P 450 0 80 0 63 Alloy 42 Cu Alloy ej Lan FARRAR AAA e Recommended Mount Pad Dimension in Millimeters a pMn pere E E 8 Fi UA A 2 4 qa A1 0 05 A2 2 0 2 gt 1 b 0 35 0 4 0 5 0 13 0 15 0 2 poe D 17 3 17 5 17 7 8 2 8 4 8 6 0 8 11 63 11 93 12 23 0 L 0 3 0 5 0 7 i L 1765 y 0 15 E 0 09 10 B bz 05 11 43 Detail F 12 1 27 3 40 4513 4514 Group User s Manual MITSUBISHI SEMICONDUCTORS USER S MANUAL 4513 4514 Group Dec First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1998 MITSUBISHI ELECTRIC CORPORATION REVISION DESCRIPTION LIST 4513 4514 GROUP USER S MANUAL No date 1 0 First Edition 981211
6. input Notes 1 R represents read enabled and W represents write enabled 2 When setting ports W63 W61 are not used 2 6 4513 4514 Group User s Manual APPLICATION 2 1 I O pins 2 1 3 Port application examples 1 Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an N channel open drain and port PO has the pull up resistor Outline The connecting required external part is just keys Specifications Port D is used to output L level and port PO is used to input 16 keys Multiple key inputs are not detected Figure 2 1 1 shows the key input and Figure 2 1 2 shows the key input timing M34513 M34514 Fig 2 1 1 Key input by key scan 4513 4514 Group User s Manual 2 7 APPLICATION 2 1 10 pins Switching key input selection port DoD 1 Stabilizing wait time for input Reading port key input Key input period IAPO IAPO IAPO IAPO IAPO BSH Input to Input to Input to Input to Input to SW1 SW4 SW5 SW8 SW9 SW12 SW13 SW16 SW1 SWA Note output of port D becomes high impedance state Fig 2 1 2 Key scan input timing 2 8 4513 4514 Group User s Manual APPLICATION 2 1 I O pins 2 1 4 Notes on use 1 2 3 4 5 6 7 Note when an I O port except port P5 is used as an input port Set the output latch to 1 and input the port value before input If t
7. 8 machine cycles M Comparison result store flag ADF DAC operation signal Fig 29 Comparator operation timing chart 4513 4514 Group User s Manual Comparator operation completed The value of ADF is determined 1 45 HARDWARE FUNCTION BLOCK OPERATIONS 15 Notes for the use of A D conversion 2 Do not change the operating mode both A D conversion mode and comparator mode of A D converter with bit 3 of register Q2 while A D converter is operating When the operating mode of A D converter is changed from the comparator mode to A D conversion mode with the bit 3 of register Q2 note the following Clear bit 2 of register V2 to 0 to change the operating mode of the A D converter from the comparator mode to A D conversion mode with the bit 3 of register Q2 The A D conversion completion flag ADF may be set when the operating mode of the A D converter is changed from the com parator mode to the A D conversion mode Accordingly set a value to register Q2 and execute the SNZAD instruction to clear the ADF flag Output data 1023 16 Definition of A D converter accuracy The A D conversion accuracy is defined below refer to Figure 30 Relative accuracy Zero transition voltage This means an analog input voltage when the actual A D con version output data changes from 0 to 1 Q Full scale transition voltage VFST This means an analog input voltage
8. E 2 gt 2 P30 INTO Outline 32P6B A 1 4 4513 4514 Group User s Manual HARDWARE PIN CONFIGURATION PIN CONFIGURATION TOP VIEW 4514 Group P43 AIN7 P42 AIN6 P41 AIN5 P40 AIN4 AIN3 CMP1 AIN2 CMP1 AIN1 CMP0 AINO CMPO P33 P32 P31 INT1 P30 INTO IN O1 DA TI TI 70 d3XXX XINY LSPEN Outline 42P2R A 4513 4514 Group User s Manual 1 5 HARDWARE BLOCK DIAGRAM BLOCK DIAGRAM 4513 Group SU SPIOM HBE 962 7821 X SpJOM 2618 19 960 8002 WOU 4 15 xoeijs 1dnueiu 5 8 xS 19481691 2816 sua 8 3 sia 2 1eisibeu v 1e1siDeu silq 7 7 NIV 9109 seues 004 Lx 9 leues uo x sud OL 1 514 91 doup 1nOX NIX 5 2 8 Jeu 516 9 8 8 eJeudued uod 4513 4514 Group User s Manual 1 6 HARDWARE BLOCK DIAGRAM BLOCK
9. DD 2 0 V to 5 5 V 0 8 2 40 to 60 One Time PROM version DD 4 0 V to 55 V 3 0 2 40 to 60 High speed mode Middle speed mode DD 2 5 5 5 3 0 MHz 40 to 60 DD 2 5 V to 5 5 V 1 0 MHz 40 to 60 ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM 1 Mask ROM Order Confirmation Form 1 2 Data to be written into mask ROM three sets containing the identical data 3 Mark Specification 4 1 1 58 4513 4514 Group User s Manual LIST OF PRECAUTIONS INoise and latch up prevention Connect a capacitor on the following condition to prevent noise and latch up connect a bypass capacitor approx 0 1 between pins VDD and Vss at the shortest distance equalize its wiring in width and length and use relatively thick wire In the One Time PROM version CNVss pin is also used as VPP pin Accordingly when using this pin connect this pin to 55 through a resistor about 5 kQ in series at the shortest distance Prescaler Stop the prescaler operation to change its frequency dividing ra tio G Timer count source Stop timer 1 2 3 or 4 counting to change its count source Reading the count value Stop timer 1 2 3 or 4 counting and then execute the TAB1 TAB
10. Interrupt disabled SNZT3 instruction is valid Timer 3 interrupt enable bit Interrupt control register 11 Interrupt enabled SNZTS instruction is invalid reset 00002 at RAM back up state retained Not used This bit has no function but read write is enabled Interrupt valid waveform for INTO pin Falling waveform L level of INTO pin is recognized with the SNZIO instruction L level return level selection bit Note 2 Rising waveform H level of INTO pin is recognized with the SNZIO instruction H level INTO pin edge detection circuit control bit One sided edge detected Both edges detected INTO pin Disabled timer 1 control enable bit Interrupt control register 12 Enabled reset 00002 at RAM back up state retained Not used This bit has no function but read write is enabled Interrupt valid waveform for INT1 pin Falling waveform L level of INT1 pin is recognized with the SNZI1 instruction L level return level selection bit Note 3 Rising waveform H level of INT1 pin is recognized with the SNZI1 instruction H level One sided edge detected INT1 pin edge detection circuit control bit Both edges detected INT1 pin Disabled timer 3 control enable bit Notes 1 R represents read enabled and W represents write enabled Enabled 2 When the contents of 112 is changed
11. L level input current Do D7 Vi 0V VDD 5V f XIN 4 0 MHz Middle speed mode f XIN 400 kHz VDD 3V f XIN 4 0 MHz Middle speed mode f XIN 400 kHz at active mode XIN 4 0 MHz H level output voltage P5 evel output voltage PO P1 P4 P5 evel output voltage P3 RESET VDD 5V evel output voltage De D7 VDD 3V L level output voltage Do D5 5 f Supply current High speed mode 400 kHz 3 2 0 2 High speed mode f XIN 400 kHz Ta 25 C at RAM back up mode 5 3 5 VDD 3V Hysteresis INTO INT1 CNTRO CNTR1 5V SIN SCK 3 5 3 Pull up resistor value Hysteresis RESET 4513 4514 Group User s Manual 3 5 APPENDIX 3 1 Electrical characteristics 3 1 4 A D converter recommended operating conditions Table 3 1 5 A D converter recommended operating conditions Comparator mode included Ta 20 C to 85 C unless otherwise noted Parameter Conditions Supply voltage Analog input voltage Middle speed mode VDD 2 2 7 V High speed mode VDD gt 2 7 V Oscillation frequency Table 3 1 6 A D converter characteristics 20 C to 85 C unless o
12. Notes 1 represents read enabled and W represents write enabled 2 Select AIN4 AIN7 with register Q1 after setting register Q2 3 In the 4513 Group these bits are not used 4 In the 4513 Group only read write of these bits is enabled 2 50 4513 4514 Group User s Manual APPLICATION 2 5 A D converter 2 5 2 A D converter application examples 1 A D conversion mode Outline Analog input signal from a sensor can be converted into digital values Specifications Analog voltage values from a sensor is converted into digital values by using a 10 bit successive comparison method Use the AINo pin for this analog input Figure 2 5 2 shows the A D conversion mode setting example Disable Interrupts A D interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI instruction b3 00 A D interrupt occurrence disabled Interrupt control register 2 X 2 ihsttuctiom Q Set A D Converter A D conversion mode is selected to A D operation mode Analog input Aino is selected b0 b3 A D control register Q2 0 A D conversion mode selected TQ2A instruction b0 b3 A D control register Q1 0 0 selected instruction Clear Interrupt Request A D interrupt activated condition is cleared conversion completion flag ADF A D conversion interrupt activated condition cleared SNZ
13. 0 Port P53 input FRO3 Port P53 input output control bit Ine 1 P53 output 0 Port P52 input FRO2 Port P52 input output control bit call abide 1 Port P52 output 0 Port P51 input FRO1 Port P51 input output control bit P 1 P51 output 0 Port P50 input FROo Port P50 input output control bit 1 5 output Notes 1 W represents write enabled 5 2 The 4513 Group does not have Timer control register W6 register FRO D6e CNTRO function selection bit is assigned to bit 0 D7 CNTR1 function selection bit is assigned to bit 2 Set the contents of this register through register A with the TW6A instruction The contents of register W6 is transferred to register A with the TAWS instruction Table 2 1 5 shows the timer control register W6 Table 2 1 5 Timer control register W6 Timer control register W6 at reset 00002 at RAM back up state retained R W Timer 3 underflow signal output divided by 2 0 W63 1 output control bit 1 CNTR1 output control by timer 4 underflow signal divided by 2 wee Dz CNTR1 function selection bit OC 0 input 1 1 l O D7 input 0 Ti 1 fl ignal ivi 2 Wet ENIRO ouput bit Timer 1 underflow divided 35 1 CNTRO output control by timer 2 underflow signal divided by 2 W60 D CNTRO function selection bit z CNTRO
14. 1 2 3 Note when the A D conversion starts again When the A D conversion starts again with the ADST instruction during A D conversion the previous input data is invalidated and the A D conversion starts again A D control register Q2 Select AIN4 AIN7 with register Q1 after setting register Q2 A D converter 1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage Accordingly when the analog voltage is input from the circuit with high impedance and charge discharge noise is generated and the sufficient A D accuracy may not be obtained Therefore reduce the impedance or connect a capacitor 0 01 uF to 1 uF to analog input pins Figure 2 5 3 shows the analog input external circuit example 1 When the overvoltage applied to the A D conversion circuit may occur connect an external circuit in order to keep the voltage within the rated range as shown the Figure 2 5 4 In addition test the application products sufficiently About 1 Note i 0 to 7 Note Apply the voltage within the specifications to an analog input pin i 0 to 7 Fig 2 5 4 Analog input external circuit example 2 Fig 2 5 3 Analog input external circuit example 1 4 Notes for the use of A D conversion 2 When the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode with bit 3 of register Q2 in a program be careful about the following notes
15. 2 Middle speed mode 3 0 MHz 2 0 V to 5 5 V Note f XIN High speed mode 1 5 MHz Note 2 5 V to 5 5 V for the One Timer PROM version 4513 4514 Note Externally connect a damping resistor Rd de pending on the oscilla tion frequency A feed back resistor is built in XOUT Use the resonator manufacturer s recom mended value because constants such as ca pacitance depend on the resonator Fig 2 10 1 Oscillation circuit example connecting ceramic resonator externally 4513 4514 Group User s Manual 2 63 APPLICATION 2 10 Oscillation circuit 2 10 2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation For the 4513 4514 Group the clock f XIN f XIN 2 which is supplied from the oscillation circuit is selected with the register MR Figure 2 10 2 shows the structure of the clock control circuit System clock eee oo p Kes Internal clock Xino Oscillation generation circuit Instruction clock XOUTO divided by 3 Wait time Note control circuit start signal O RESET Key on wake up control register 00 01 02 0 Ports POo P01 1 Ports P03 Falling detected F Ports P12 P13 P3o INTO H level 122 L level P31 INT1 L H level Note The wait time control circuit is used to generate the time required to stabilize
16. A2 0 lt X 2 lt 0 SP2 SPo X lt x x 0 to 15 Y lt y y 20to 15 2 7 2 0 03 Y lt Y 1 Y Y 1 XAMI j RAM to register transfer lt 2 M DP X lt X EXOR j20to 15 Y lt Y 1 M DP lt X lt X EXOR 01015 Bit operation SB RB j 578 Mj DP lt 1 j O0to3 Mj DP lt 0 0103 Mj DP 0 2 0103 RAM to register transfer lt M DP X lt X EXOR 01015 lt 2 M DP X X EXOR 01015 lt 2 M DP X lt X EXOR 01015 Y lt 1 1 Arithmetic operation n 01015 SP SP 1 SK SP PC PCH p PCL DR2 DRo 7 4 A ROM PO 3 0 PC SK SP SP SP 1 A lt A M DP A lt CY CY M DP lt Carry lt n 01015 A lt AND M DP lt OR M DP lt 1 0 IA3A2A1A0 4513 4514 Group User s Manual Comparison operation A M DP A 2n 010 15 Branch operation PCL lt ae ao PCH p PCL lt ae ao PCH p PCL lt DR2 DRo Subroutine operation lt SP 1 K SP PC PCH PCL lt 0 SP
17. L or L H Outline An external 1 interrupt be used by dealing with the change of edge H L or L H in both directions as a trigger Specifications An interrupt occurs by the change of an external signals edge H L or L H Figure 2 2 3 shows an operation example of an external 1 interrupt and Figure 2 2 4 shows a setting example of an external 1 interrupt Timer 1 interrupt Constant period interrupts by a setting value to timer 1 can be used Outline The constant period interrupts by the timer 1 underflow signal can be used Specifications Prescaler and timer 1 divide the system clock frequency f XIN 4 0 MHz and the timer 1 interrupt occurs every 1 ms Figure 2 2 5 shows a setting example of the timer 1 constant period interrupt Timer 2 interrupt Constant period interrupts by a setting value to timer 2 can be used Outline The constant period interrupts by the timer 2 underflow signal can be used Specifications Timer 2 divides the 16 bit fixed dividing frequency timer and the timer 2 interrupt occurs every about 2 sec Figure 2 2 6 shows a setting example of the timer 2 constant period interrupt Timer 3 interrupt Constant period interrupts by a setting value to timer 3 can be used Outline The constant period interrupts by the timer 3 underflow signal can be used Specifications Prescaler and timer 3 divide the system clock frequency f XIN 4 0 MHz and the timer 3 inte
18. Port D 8 bits Port PO 4 bits Port P1 4 bits Port P2 3 bits Port P3 4 bits Port P4 4 bits Port P5 4 bits Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A same for others Direction of data movement Data exchange between a register and memory Decision of state shown before Contents of registers and memories Negate Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address ae a5 a4 a2 a1 Label indicating address ae a5 a4 a2 a1 in page p5 p3 p2 pt po Hex C Hex number x also same for others Note The 4513 4514 Group just invalidates the next instruction when a skip is performed The contents of program counter is not increased by 2 Accord ingly the number of cycles does not change even if skip is not performed However the cycle count becomes 1 if the TABP p RT or RTS instruction is skipped 1 62 4513 4514 Group User s Manual LIST OF INSTRUCTION FUNCTION Mnemonic Function Mnemonic Function HARDWARE LIST OF INSTRUCTION FUNCTION Mnemonic Function Register to register transfer RAM addresses TAB TBA TAY TYA TEAB DR2 DRo lt 2 2 lt lt 0 DR2 DRo A1 lt Z1 20
19. This symbol represents a parasitic diode on the port Fig 17 External interrupt circuit structure 1 26 4513 4514 Group User s Manual 1 External 0 interrupt request flag EXFO External 0 interrupt request flag EXFO is set to 1 when a valid waveform is input to P30 INTO pin The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock Refer to Figure 16 The state of EXFO flag can be examined with the skip instruction SNZO Use the interrupt control register V1 to select the interrupt or the skip instruction The EXFO flag is cleared to 0 when an in terrupt occurs or when the next instruction is skipped with the skip instruction The 0 pin need not be selected the external interrupt input INTO function or the normal I O port function However the EXFO flag is set to 1 when a valid waveform is input even if it is used as an I O port P30 External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30 INTO pin The valid waveform can be selected from rising waveform falling waveform or both rising and falling waveforms An example of how to use the external 0 interrupt is as follows Select the valid waveform with the bits 1 and 2 of register I1 Q Clear the EXFO flag to 0 with the SNZO instruction G Set the NOP instruction for the case whe
20. 6 Timer 4 interrupt The interrupt request occurs by the timer 4 underflow E Timer 4 interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the interrupt enable flag INTE are set to 41 When the timer 4 interrupt occurs the interrupt processing is executed from address A in page 1 When the interrupt is not used The interrupt is disabled and the SNZTA instruction is valid when the bit 1 of register V2 is set to 0 2 12 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts 7 A D interrupt The interrupt request occurs by the end of the A D conversion B A D interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE set to 1 When the A D interrupt occurs the interrupt processing is executed from address C in page 1 When the interrupt is not used The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set to 0 8 Serial interrupt The interrupt request occurs by the end of the serial transmit receive Serial interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the interrupt enable flag INTE are set to 1 When the serial I O in
21. Clear bit 2 of register V2 to 0 to change the operating mode of the A D converter from the comparator mode to the A D conversion mode with bit 3 of register Q2 refer to Figure 2 5 50 The A D conversion completion flag ADF may be set when the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode Accordingly set a value to register Q2 and execute the SNZAD instruction to clear the ADF flag Do not change the operating mode both A D conversion mode and comparator mode of A D converter with bit 3 of register Q2 during operating the A D converter Clear bit 2 of register V2 to 0 Change of the operating mode of the A D converter from the comparator mode to the A D conversion mode Clear the ADF flag to 0 with the SNZAD instruction Execute the NOP instruction for the case when skip is performed with the SNZAD instruction Fig 2 5 5 A D converter operating mode program example 2 52 4513 4514 Group User s Manual APPLICATION 2 5 A D converter 5 A D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison the contents of ADF flag retains 0 not set to 1 In this case the A D interrupt does not occur even when the usage of the A D interrupt is enabled Accordingly consider the time until the comparator operation is completed and examine the state of ADF flag by software
22. J1 lt SIOF lt 0 Serial I O starting Serial I O control operation SIOF 1 After skipping SIOF 0 A AD5 AD2 lt AD9 AD6 However the comparator mode lt AD3 ADO lt AD7 AD4 AD1 ADo 0 0 lt AD7 AD4 lt lt Q1 Q1 lt ADF lt 0 A D conversion starting E o o 2 wn 2 gt lt ADF 1 After skipping ADF 0 lt 02 Q2 lt A PC lt PC 1 RAM back up POF instruction valid P 2 1 WDF1 0 WEF 1 A lt MR Other operation MR lt A lt Q33 Q32 A2 Q31 lt CMP1 comparison result Q30 comparison result 1 82 4513 4514 Group User s Manual HARDWARE MACHINE INSTRUCTIONS Skip condition Datailed description Transfers the contents of serial I O register SI to registers A B Transfers the contents of registers A and B to serial I O register SI Transfers the contents of serial mode register J1 to register A Transfers the contents of register A to serial I O mode register J1 Clears 0 to SIOF flag and starts serial 1 Skips the next instruction when the contents of SIOF flag is 1 After skipping clears 0 to SIOF flag Transfers the high order 8 bits of the contents of register AD t
23. Minimum instruction execution time 0 75 us at 4 0 MHz oscillation frequency in high speed mode VDD 4 0 V to 5 5 V e Supply voltage Middle speed mode 2 5 V to 5 5 V at 4 2 MHz oscillation frequency for Mask ROM version and One Time PROM version 2 0 V to 5 5 V at 3 0 MHz oscillation frequency for Mask ROM version Operation voltage of A D conversion 2 7 V to 5 5 V High speed mode 4 0 V to 5 5 V at 4 2 MHz oscillation frequency for Mask ROM version and One Time PROM version 2 5 V to 5 5 V at 2 0 MHz oscillation frequency for Mask ROM version and One Time PROM version cn 2 0 V to 5 5 V at 1 5 MHz oscillation frequency for Mask ROM version Operation voltage of A D conversion 2 7 V to 5 5 V ROM size X 10 bits Product HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION Timers e 8 bit timer with reload register 2 8 bit timer with reload register TIMEN mec 8 bit timer with reload register TIITIGI 4 iecur 8 bit timer with a reload register eirterr pt uoo mme Pr ie 8 sources e Serial iet tte ee n Ue b S UR 8 bit wide A D converter 10 bit successive comparison method Ge Voltage comparator 2 enne 2 circuits e Watchdog es 16 bits Voltage drop detection circuit Clo
24. SP 1 SK SP PCH lt p PCL lt DR2 DRo Return operation PC SK SP SP lt SP 1 PC SK SP SP lt SP 1 PC SK SP SP lt SP 1 1 63 HARDWARE LIST OF INSTRUCTION FUNCTION LIST OF INSTRUCTION FUNCTION continued roup ing Mnemonic Function Mnemonic Function Mnemonic Function Interrupt operation INTE 0 INTE 1 EXF0 21 After skipping 0 EXF1 21 After skipping EXF1 0 12 1 INTO 112 0 INTO 122 1 INT1 122 0 INT1 A lt V1 Timer operation The 4513 Group does not have these instructions 1 64 Timer operation TAW4 TW4A TAW6 TW6A TAB1 4513 4514 Group User s Manual lt W4 lt lt W6 6 lt T17 T14 lt 13 10 R17 R14 lt 717 714 lt R13 R10 lt 13 10 lt lt T27 T24 lt T23 T20 R27 R24 T27 T24 B R23 R20 lt A T23 T20 A B lt T37 T34 lt T33 T30 R37 R34 lt 737 734 lt R33 R30 lt 733 730 lt lt T47 T44 lt 43 40 R47 R44 lt T47 T44 lt R43 R40 lt T43 T40 lt R17 R14 lt R13 R10 lt R37
25. Table 2 9 7 shows the interrupt control register 12 Table 2 9 7 Interrupt control register 12 at reset 00002 at RAM back up state retained This bit has no function but read write is enabled Interrupt control register 12 R W 123 Not used Falling waveform L level of INT1 pin is recognized with the SNZI1 instruction L level Rising waveform H level of INT1 pin is recognized with the SNZI1 instruction H level Interrupt valid waveform for INT1 122 pin return level selection bit Note 2 l2 INT1 pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected INT1 pin 0 Disabled 120 timer 3 control enable bit Enabled Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 122 is changed the external interrupt request flag EXF1 may be set Accordingly clear EXF1 flag with the SNZ1 instruction 2 9 3 Notes on use 1 Key on wakeup function After setting ports P1 specified with register PUO and PO which key on wakeup function is valid to H execute the POF instruction L level is input to the falling edge detection circuit even if one of ports which key on wakeup function is valid is in the L level state and the edge is not detected 2 POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back up state Note
26. _ Software starts RESET address 0 in page 0 Note Keep the value of supply voltage to the minimum value or more of the recommended operating conditions Fig 33 RESET pin input waveform and reset operation 4513 4514 Group User s Manual 1 49 HARDWARE FUNCTION BLOCK OPERATIONS 1 Power on reset Reset can be performed automatically at power on power on re set by connecting resistors a diode and a capacitor to RESET pin Connect RESET pin and the external circuit at the shortest dis tance VDD RESET pin voltage f Reset state Internal reset signal Reset released Power on Note lt This symbol represents a parasitic diode Applied potential to RESET pin must be VDD or less Fig 34 Power on reset circuit example 2 Internal state at reset Table 19 shows port state at reset and Figure 35 shows internal state at reset they are the same after system is released from re set The contents of timers registers flags and RAM except shown in Figure 35 are undefined so set the initial value to them Table 19 Port state at reset Name Function Do D5 00 05 De CNTRO D7 CNTR1 De D7 P00 P03 P00 P03 P10 P13 P10 P13 20 5 P21 SOUT P22 SIN P20 P22 High impedance P30 INTO P31 INT1 P30 P31 P32 P33 Note 4 P32 P33 P40 AIN4 P43 AIN7 Note 4 P40 P43 High impedance Note 1 5 5 Note 4 P50 P53 High impedance Note 3 Notes 1 Outpu
27. p E De CNTRO RD Penei s 22 Timer 1 underflow signal divided by 2 or 7 1 signal of AND operation between timer 1 underflow signal divided by 2 and timer 2 underflow signal divided by 2 Skip decision SZD instruction lt Clock input for timer 4 event count lt CLD instruction SD instruction D7 ONTR1 RD Timer underflow signal divided by 2 1 signal of AND operation between timer 3 underflow signal divided by 2 and timer 4 underflow signal divided by 2 46 This symbol represents a parasitic diode on the port Applied potential to ports Do D7 must be 12 V i represents O 1 2 or 3 The 4513 Group does not have port P5 4513 4514 Group User s Manual HARDWARE PIN DESCRIPTION E One sided edge detection circuit P3o INTO External 0 Y interrupt Both edges detection circuit Wakeup 22 Falling P31 INT1 External 1 interrupt 4 This symbol represents a parasitic diode on the port External interrupt circuit structure 1 16 4513 4514 Group User s Manual FUNCTION BLOCK OPERATIONS CPU 1 Arithmetic logic unit ALU The arithmetic logic unit ALU performs 4 bit arithmetic such as 4 bit data addition comparison AND operation OR operation and bit manipulation 2 Register A and carry flag Register A is a 4 bit register used for arithmetic transf
28. 00 SEA 00 0111 nnnn SZD 00 0010 1011 1 68 4513 4514 Group User s Manual HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE continued for 4514 Group 1 00000 100001 1 0001011 0001 1 100100 100101 1001 10 1001 11 101000 101001 101010 10101 1 101 100 101 101 101110 101111 03 n 22 23 24 25 26 27 28 29 2A notation 0000 SNZT1 0001 SNZT2 0010 SNZT3 0011 SNZT4 0100 0101 0110 SNZAD TFROATSIAB SNZSI TALA The above table shows the relationship between machine language codes and machine language instructions D3 Do show the low order 4 bits of the machine language code and D9 D4 show the high order 6 bits of the machine language code The hexadecimal representation of the code is also provided There are one word instructions and two word instructions but only the first word of each instruction is shown Do not use code marked The codes for the second word of a two word instruction are described below The second word BL 10 paaa aaaa BML 10 paaa aaaa BLA 10 00 pppp BMLA 10 00 pppp SEA 00 0111 nnnn SZD 00 0010 1011 4513 4514 Group User s Manual 1 69 HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS Parameter Instruction
29. 1 1 User s Manual 4513 4514 Group Renesas Technology Corp Nippon Bldg 6 2 0temachi 2 chome Chiyoda ku Tokyo 100 0004 Japan New publication effective Dec 1998 1998 MITSUBISHI ELECTRIC CORPORATION Specifications subject to change without notice
30. 3 11 3 2 9 Characteristics PS tnt ut tre tr e e 3 13 3 13 E HQ 3 14 N 3 17 E 3 2 8 Detection voltage temperature characteristics of voltage drop A 3 24 3 4 1 Shortest wiring length 464 400000 eene 3 24 3 26 MINE ONG Am RAMS 3 27 xm PP 3 27 3 28 3 28 cen DTE 3 30 3 36 meme P S P 3 39 4513 4514 Group User s Manual iii List of figures List of figures CHAPTER 1 HARDWARE PIN CONFIGURATION TOP VIEW 4513 22 2 220004 1 4 PIN CONFIGURATION TOP VIEW 4514 1 5 BLOCK DIAGRAM 4513 1 6 BEOCK DIAGRAM 4514 GEOUD treten ttt deren candace ed 1 7 PORT BLOCK DIAGRAMS 1 12 External interrupt circuit nennen nnns 1 16 Fig 1 AMC instruction execution 1 17 Fig 2 RAR instruction execution example sse eene 1 17 Fig 3 RHegisters A B arid register E eR a RI ieee eds 1 17 Fig 4 p instruction execution example enne eene 1
31. CMP1 invalid control bit Voltage comparator CMP1 valid Q32 Voltage comparator Voltage comparator invalid control bit Voltage comparator valid CMP1 gt CMP1 CMP1 lt CMP1 gt lt Notes 1 R represents read enabled and W represents write enabled 2 Bits 0 and 1 of register can be only read Q31 1 comparison result store bit Q30 comparison reslut store bit 2 54 4513 4514 Group User s Manual APPLICATION 2 6 Voltage comparator 2 6 3 Notes on use Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3 it is operating even in the RAM back up mode Accordingly be careful about such state because it causes the increase of the operation current in the RAM back up mode In order to reduce the operation current in the RAM back up mode invalidate bits 2 and 3 of register Q3 0 the voltage comparator function by software before the POF instruction is executed Also while the voltage comparator function is valid current is always consumed by voltage comparator On the system required for the low power dissipation invalidate the voltage comparator when it is unused by software Register Q3 Bits 0 and 1 of register be only read Note that they cannot be written Reading the comparison res
32. ERROR 1LSB WIDTH mV 1 5 3 4 5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 STEP No 45 IRN NIAAA NANNY e ERROR 1LSB WIDTH mV o 1 5 3 L 4 5 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 STEP 4 5 3 NSE S PIN SAAN RAMA ANAT IIS A ISAAPATSSPNT V 1 5 rrr eSI PISIS APP PP re opi MV rt 80 a 1 5 o 3 4 5 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 STEP No 4 5 Z WAAAY yen AVA AA nner parr NNN 1 5 8 o a15 2 3 4 5 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024 4513 4514 Group User s Manual 3 15 APPENDIX 3 2 Typical characteristics 2 5 12 V 4 MHz high speed mode Ta 25 1LSB WIRTH a N a ERROR 1LSB WIDTH mV 2 5 5 7 5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 STEP No 7 5 ERROR 1LSB WIDTH mV 2 5 5 75 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 STEP No 75 ERROR 1LSB WIDTH mV 2 5 5 7 5 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 STEP 7 5 ERROR 1LSB WIDTH mV 7 5 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024 STEP 3 16 4513 4514 Group User
33. Set FF16 in the shaded area Set 1112 in the area 2 Mark Specification Low order BODIE 5 bit data 47 400016 57FFie of low order and high order 5 bit data Mark specification must be submitted using the correct form for the type of package being ordered Fill out the approximate Mark Specification Form 42P2R A for M34514M6 XXXFP and attach to the Mask ROM Order Confirmation Form 3 Comments 3 34 4513 4514 Group User s Manual GZZ SH52 4 lt 81A0 gt 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M34514M8 XXXFP MITSUBISHI ELECTRIC Please fill in all items marked Customer Company name APPENDIX 3 5 Mask ROM order confirmation form Mask ROM number Date Section head signature Date issued 1 Confirmation Specify the type of 5 submitted Three sets of EPROMs are required for each pattern check in the approximate box If at least two of the three sets of EPROMs submitted contain the identical data we will produce masks based on this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data Thus the customer must be especially careful in verifying the data contained in the EPROMs submitted Issuance signature Supervisor signature Responsible officer Supervisor Checksum
34. The comparator operation is completed after 8 machine cycles 6 Analog input pins Even when P40 AIN4 P43 AIN7 are set to pins for analog input they continue to function as P40 P43 I O Accordingly when any of them are used as 1 0 port P4 and others are used as analog input pins make sure to set the outputs of pins that are set for analog input to 1 Also the port input function of the pin functions as an analog input is undefined 7 TALA instruction When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A and simultaneously the low order 2 bits of register A is 0 8 Recommended operating conditions when using A D converter The recommended operating conditions of supply voltage and system clock frequency when using A D converter are different from those when not using A D converter Table 2 5 3 shows the recommended operating conditions when using A D converter Table 2 5 3 Recommended operating conditions when using A D converter Limits Parameter Condition Min Typ VDD 4 5 V to 5 5 V high speed mode VDD 4 0 V to 5 5 V high speed mode System clock frequency at ceramic resonance VDD 2 7 V to 5 5 V middle speed mode VDD 4 5 V 5 V high System clock frequency meee Duty VDD 4 0 V to 5 5 V high speed mode t ext clock t 40 to 60 96 clock 7 to 5
35. and L pulse width Mask ROM version Middle speed mode DD 4 0 V to 5 5 V DD 2 5 V to 5 5 V DD 2 0 V to 5 5 V One Time PROM version Middle speed mode DD 4 0 V to 5 5 V DD 2 5 V 5 5 V Mask ROM version High speed mode DD 4 0 V to 5 5 V DD 2 5 Vto 5 5 V V V V V V V V V V V VDD 2 0 V to 5 5 V V V V V V V V V V V DD 2 0 V to 5 5 V One Time PROM version High speed mode 4 0 V to 5 5 V 2 5 V to 5 5 V 4513 4514 Group User s Manual APPENDIX 3 1 Electrical characteristics 3 1 3 Electrical characteristics Table 3 1 4 Electrical characteristics Mask ROM version Ta 20 C to 85 C VDD 2 0 V to 5 5 V unless otherwise noted One Time PROM version Ta 20 C to 85 C VDD 2 5 V to 5 5 V unless otherwise noted Limits Typ Parameter Test conditions 5 loH 10 mA 3 loH 5 mA VDD 5V IOL 12 mA VDD 3V IOL 6 mA VDD 5V IOL 5 mA VDD 3V loL 2 mA IOL 30 mA loL 10 mA loL 15 mA loL 2 5 mA Vop 5V loL 15 mA VDD 3V IOL 3 mA H level input current VI VDD port P4 selected PO P1 P2 P3 P4 P5 RESET VDCE port P5 input state H level input current Do D7 Vi 12V L level input current 0 V No pull up of ports PO and PO P1 P2 P3 P4 P5 RESET VDCE port P4 selected port P5 input state
36. at RAM back up state retained R W J13 Not used This bit has no function but read write is enabled 0 1 Serial I O internal clock dividing 0 Instruction clock signal divided by 8 ratio selection bit 1 Instruction clock signal divided by 4 0 1 0 Input ports P20 P21 P22 selected Serial I O ports SCK Sour SiN input ports P20 P21 P22 selected Serial synchronous clock External clock selection bit 1 Internal clock instruction clock divided by 4 or 8 Note represents read enabled and W represents write enabled 411 Serial I O port selection bit 3 Serial transmission reception completion flag SIOF Serial I O transmission reception completion flag SIOF is set to 1 when serial data transmission or reception completes The state of SIOF flag can be examined with the skip instruction SNZSI 4513 4514 Group User s Manual 2 41 APPLICATION 2 4 Serial 2 4 3 Operation description Figure 2 4 2 shows the serial I O connection example Figure 2 4 3 shows the serial I O register state and Figure 2 4 4 shows the serial I O transfer timing Master internal clock selected 4513 4514 05 5 SOUT SIN Control signal Slave external clock selected 4513 4514 rd Ds 5 SIN SOUT Note The control signal is used to inform the master by the pin level that the slave is in a ready state to receive The 4
37. refer to Figure 466 The A D conversion completion flag ADF may be set when the Fi operating mode of the A D converter is changed from the com parator mode to the A D conversion mode Accordingly set a value to register Q2 and execute the SNZAD instruction to clear the ADF flag Do not change the operating mode both A D conversion mode and comparator mode of A D converter with the bit 3 of register Q2 during operating the A D converter X0XX2 The SNZAD instruction is valid 0XXX2 Change of the operating mode of the A D converter from the comparator mode to the A D conversion mode X this bit is not related to the change of the operating mode of the A D conversion g 46 A D converter operating mode program example OA D converter 2 1 60 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage Accordingly when the analog voltage is input from the circuit with high impedance and charge discharge noise is generated and the sufficient A D accuracy may not be obtained Therefore reduce the impedance or con nect a capacitor 0 01 uF to 1 uF to analog input pins Figure 47 When the overvoltage applied to the A D conversion circuit may occur connect an external circuit in order to keep the voltage within the rated range as shown the Figure 48 In addition test the application products sufficiently i Apply the voltage withiin the specifications to
38. the external interrupt request flag EXFO be set Accordingly clear EXFO flag with the SNZO instruction 3 When the contents of 122 is changed the external interrupt request flag EXF1 may be set Accordingly clear EXF1 flag with the SNZ1 instruction 1 84 4513 4514 Group User s Manual Timer control register W1 at reset 00002 HARDWARE CONTROL REGISTERS at RAM back up 00002 Prescaler control bit Stop state initialized Operating Instruction clock divided by 4 Prescaler dividing ratio selection bit Instruction clock divided by 16 Stop state retained Timer 1 control bit Operating Timer 1 count start synchronous circuit Count start synchronous circuit not selected control bit Timer control register W2 Count start synchronous circuit selected reset 00002 at RAM back up state retained Timer 2 control bit Stop state retained Operating Not used This bit has no function but read write is enabled Count source Timer 1 underflow signal Timer 2 count source selection bits Prescaler output Timer control register W3 CNTRO input 16 bit timer WDT underflow signal reset 00002 at RAM back up state retained W33 Timer 3 control bit Stop state retained Operating W32 Timer 3 count start synchronous circuit Count start synchronous circuit not selected control bit Count start
39. warm start or cold start can be identified by examining the state of the power down flag P with the SNZP instruction Table 2 9 3 Start condition identification Return condition P flag External wakeup signal input 1 Reset 0 Software start Cold start Warm start Fig 2 9 1 Start condition identified example 2 9 2 Related register 1 Key on wakeup control register KO Key on wakeup control register KO controls key on wakeup functions of ports POo P03 P10 P13 Set the contents of this register through register A with the TKOA instruction The TAKO instruction can be used to transfer the contents of register KO to register A Table 2 9 4 shows the key on wakeup control register KO Table 2 9 4 Key on wakeup control register KO at reset 00002 at RAM back up state retained Key on wakeup control register KO R W Pins P12 P13 wakeup 0 Key on wakeup not used control bit 1 Key on wakeup used Pins P10 and 11 wakeup 0 Key on wakeup not used control bit 1 Key on wakeup used Pins P02 and P03 key on wakeup 0 Key on wakeup not used did control bit 1 Key on wakeup used Koo Pins 00 and P01 key on wakeup 0 Key on wakeup not used control bit 1 Key on wakeup used Note R represents read enabled and W represents write enabled 2 60 4513 4514 Group User s Manual APPLICATION 2 9 RAM back up 2 Pull up control
40. 2 54 2 54 EE 2 54 p 2 55 cu 2 56 271 Reset o 2 56 2 7 2 rntetrnal state at ____ ___ _____ _ 2 57 2 8 Voltage drop detection 2 58 PANI NM MM NNNM 2 59 2 59 2 60 mE 2 62 2 10 Oscillation circuit annt san p ni a eu dna sra 2 63 2 10 1 Oscillation Circuit cette d ven dati n ed Fev cue 2 63 H Po 2 64 mc 2 64 ii 4513 4514 Group User s Manual Table of contents CHAPTER 3 APPENDIX 3 1 Electrical characteristics anan 3 2 3 1 1 Absolute maximum ratings a 3 2 NEN 3 3 PE 3 5 NE ES IUIS 3 6 3 6 3 7 M 3 7 Id 3 8 E 3 8 ee eer ee
41. 4 Serial 2 4 Serial I O The 4513 4514 Group has a clock synchronous serial I O which can be used to transmit and receive 8 bit data This section describes serial I O functions related registers application examples using serial I O and notes 2 4 1 Carrier functions Serial I O consists of the serial I O register SI serial mode register J1 serial I O transmit receive completion flag SIOF and serial I O counter clock synchronous serial I O uses the shift clock generated by the clock control circuit as a synchronous clock Accordingly the data transmit and receive operations are synchronized with this shift clock In transmit operation data is transmitted bit by bit from the SOUT pin synchronously with the falling edges of the shift clock In receive operation data is received bit by bit from the SIN pin synchronously with the rising edges of the shift clock Note 4513 4514 Group only supports LSB first transmission and reception B Shift clock When using the internal clock of 4513 4514 Group as a synchronous clock eight shift clock pulses are output from the SCK pin when a transfer operation is started Also when using some external clock as a synchronous clock the clock that is input from the SCK pin is used as the shift clock B Data transfer rate baudrate When using the internal clock the data transfer rate can be determined by selecting the instruction clock divided by 4 or 8 When using an external c
42. 4513 4514 Group has the programmable timers The fixed dividing frequency timer has the fixed frequency divid Programmable timer ing ratio n An interrupt request flag is set to 1 after every n The programmable timer has a reload register and enables the count of a count pulse frequency dividing ratio to be set It is decremented from a setting value n When it underflows count to n 1 a timer interrupt re quest flag is set to 1 new data is loaded from the reload register and count continues auto reload function n Counter initial value Count starts 1st underflow 2nd underflow x 5 o o 2 o n 1 count n 1 count Timer interrupt 4 4d _ iE request flag 0 An interrupt occurs or 4 a skip instruction is executed Fig 18 Auto reload function 4513 4514 Group User s Manual 1 29 HARDWARE FUNCTION BLOCK OPERATIONS The 4513 4514 Group timer consists of the following circuits Prescaler frequency divider Timer 1 8 bit programmable timer Timer 2 8 bit programmable timer Timer 3 8 bit programmable timer Timer 4 8 bit programmable timer Timers 1 to 4 have the interrupt function respectively 16 bit timer Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W6 The 16 bit timer is a free counter which is not controlled with the control regist
43. 4513 Group does not have AIN4 AIN7 CNTRO Timer input output CNTRO pin has the function to input the clock for the timer 2 event counter and to output the timer 1 underflow signal divided by 2 CNTRO pin is also used as port De CNTR1 Timer input output CNTR1 pin has the function to input the clock for the timer 4 event counter and to output the timer 3 underflow signal divided by 2 CNTR1 pin is also used as port D7 INTO INT1 Interrupt input INTO INT1 pins accept external interrupts They also accept the input signal to re turn the system from the RAM back up state INTO INT1 pins are also used as ports P30 and P31 respectively SIN Serial data input SIN is used to input serial data signals by software SIN pin is also used as port P22 SOUT Serial data output Sour is used to output serial data signals by software Sour is also used as port P21 SCK Serial 1 O clock input output 5 pin is used to input and output synchronous clock signals for serial data trans fer by software pin is also used as port P20 Voltage comparator input pins are used as the voltage comparator input pin when the volt age comparator function is selected by software pins are also used as Aino and AIN1 1 1 Voltage comparator input CMP1 CMP1 pins are used as the vo
44. 6144 words X 10 bits M34514M8 E8 8192 words X 10 bits M34513M2 128 words X 4 bits M34513M4 E4 256 words X 4 bits M34513M6 384 words X 4 bits M34513M8 E8 384 words X 4 bits M34514M6 384 words X 4 bits M34514M8 E8 384 words X 4 bits Input Output ports Eight independent I O ports ports De and D7 are also used as CNTRO and 1 respectively P00 P03 10 4 bit I O port each pin is equipped with a pull up function and a key on wakeup function Both functions can be switched by software 4 bit I O port each pin is equipped with a pull up function and a key on wakeup function Both functions can be switched by software P20 P22 3 bit input port ports P20 P21 and P22 are also used as SCK Sour and SIN respectively P30 P33 4 bit I O port 2 bit I O port for the 4513 Group ports P30 and P31 are also used as INTO and INT1 respectively The 4513 Group does not have ports P32 P33 P40 P43 4 bit I O port The 4513 Group does not have this port 5 5 4 bit I O port with direction register The 4513 Group does not have this port CNTRO 1 bit CNTRO pin is also used as port De CNTR1 1 bit CNTR1 is also used as port D7 INTO 1 bit input INTO pin is also used as port P30 and equipped with a key on wakeup function INT1 1 bit input INT1 pin is also used as port P31 and equippe
45. DIAGRAM 4514 Group y SPIOM HEE 54401 x SpJOM 2618 YY L9 WOH L das 19181691 xoeis dN113 U sje e 8 YS 19481691 8 3 13 8s 694 6 v g y v NIV 9100 seues 004 Lx s q 8 leues uo 8 x 81001 q Y sug 91 doup 1NOX NIX uiejs S 2 eDejoA suo Noun 8 8 2 39w11 8 z OUI 8 33w11 Od uod uod 4 1 7 4513 4514 Group User s Manual HARDWARE PERFORMANCE OVERVIEW PERFORMANCE OVERVIEW Parameter Function Number of basic instructions 4513 Group 123 4514 Group 128 Minimum instruction execution time 0 75 us at 4 0 MHz oscillation frequency in high speed mode Memory sizes ROM M34513M2 2048 words X 10 bits M34513M4 E4 4096 words X 10 bits M34513M6 6144 words X 10 bits M34513M8 E8 8192 words X 10 bits M34514M6
46. Group User s Manual 10 Operation at comparator mode The A D converter is set to comparator mode by setting bit 3 of the register Q2 to 1 Below the operation at comparator mode is described 11 Comparator register In comparator mode the built in DA comparator is connected to the comparator register as a register for setting comparison voltages The contents of register B is stored in the high order 4 bits of the comparator register and the contents of register A is stored in the low order 4 bits of the comparator register with the TADAB instruc tion When changing from A D conversion mode to comparator mode the result of A D conversion register AD is undefined However because the comparator register is separated from regis ter AD the value is retained even when changing from comparator mode to A D conversion mode Note that the comparator register can be written and read at only comparator mode If the value in the comparator register is n the logic value of com parison voltage Vret generated by the built in DA converter can be determined from the following formula Logic value of comparison voltage Vref n The value of register AD n 0 to 255 ADST instruction HARDWARE FUNCTION BLOCK OPERATIONS 12 Comparison result store flag ADF In comparator mode the ADF flag which shows completion of A D conversion stores the results of comparing the analog input volt age with the com
47. L Key on wakeup input External interrupt circuit IAP3 instruction Register 1 O P30 INTO P31 INT1 Ai OP3A instruction T Register A O P32 P33 4 Ai 4 This symbol represents a parasitic diode on the port Applied potential to ports P20 P22 must be i represents 0 1 2 or 3 The 4513 Group does not have ports P32 P33 4513 4514 Group User s Manual 1 13 HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS continued Analog input 1 O AINo CMPO oder Analog input AIN1 CMPO Analog input 1 z Analog input 1 O AINS CMP1 a 7 IAP4 instruction Register A i P40 AIN4 P43 AIN7 Ai D instruction 31 T Q Analog input lt 4 This symbol represents a parasitic diode on the port i represents 0 1 2 or 3 4513 Group does not have port P4 1 14 4513 4514 Group User s Manual HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS continued Direction register FROi Q 5 5 instruction T lt IAP5 instruction Skip decision I SZD instruction SD instruction RD instruction Skip decision SZD instruction lt 1 Clock input for timer 2 event count amp CLD instruction E SD instruction
48. LQFP MARK SPECIFICATION FORM Please choose one of the marking types below A B and enter the Mitsubishi catalog name and the special mark if needed eL r Mitsubishi lot number 4 digit or 5 digit 6 B Customer s Parts Number Mitsubishi catalog name 69 Mitsubishi IC catalog name Mitsubishi IC catalog name Customer s Parts Number Note The fonts and size of characters are standard Mitsubishi type Mitsubishi IC catalog name i Note1 The mark field should be written right aligned 2 The fonts and size of characters are standard Mitsubishi type 3 Customer s Parts Number can be up to 7 characters Only 0 9 A Z amp periods commas are usable 4513 4514 Group User s Manual 3 37 APPENDIX 3 6 Mark specification form 42P2R A 42 PIN SHRINK SOP MARK SPECIFICATION FORM Please choose one of the marking types below A B C and enter the Mitsubishi catalog name and the special mark if need
49. OPERATIONS Table 15 A D control registers A D control register Q1 at reset 00002 at RAM back up state retained Not used This bit has no function but read write is enabled Selected pins NO N1 N2 Analog input pin selection bits Note 2 N3 Not available for the 4513 Group N5 Not available for the 4513 Group N6 Not available for the 4513 Group a 2j loloi2i2 oi o a oi2j loi2lio 2 o A D control register Q2 N7 Not available for the 4513 Group reset 00002 at RAM back up state retained A D conversion mode A D operation mode selection bit Comparator mode P43 AIN7 and P42 AIN6 pin function selec P43 P42 read write enabled for the 4513 Group tion bit Not used for the 4513 Group AIN7 AIN6 P43 P42 read write enabled for the 4513 Group P41 AIN5 pin function selection bit Not used for the 4513 Group AIN5 P41 read write enabled for the 4513 Group P40 AIN4 pin function selection bit P40 read write enabled for the 4513 Group 9 9 9 Not used for the 4513 Group Notes 1 represents read enabled W represents write enabled 2 Select AIN4 AIN7 with register Q1 after setting register Q2 1 Operating at A D conversion mode The A D conversion mode is set by setting the bit 3 of register Q2 to 0 2 Successive comparison register AD R
50. PRECAUTIONS Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3 it is operating even in the RAM back up mode Accordingly be careful about such state because it causes the increase of the operation current in the RAM back up mode In order to reduce the operation current in the RAM back up mode invalidate bits 2 3 of register 0 the voltage comparator function by software before the POF instruction is ex ecuted Also while the voltage comparator function is valid current is al ways consumed by voltage comparator On the system required for the low power dissipation invalidate the voltage comparator when it is unused by software cfRegiser as Bits 0 and 1 of register can be only read Note that they can not be written Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time max 20 us is passed from the voltage comparator function become valid 4513 4514 Group User s Manual 1 61 HARDWARE SYMBOL SYMBOL The symbols shown below are used in the following instruction function table and instruction list Contents Contents Register A 4 bits Register B 4 bits Register D 3 bits Register E 8 bits A D control register Q1 4 bits A D control register Q2 4 bits Volta
51. Port P31 output latch Set to input OP3A instruction Set Valid Waveform Valid waveform of INT pin is selected Both edges detection selected x Interrupt control register 12 Both edges detection selected TI2A instruction Clear Interrupt Request External interrupt activated condition is cleared INT1 interrupt request flag EXF1 0 interrupt activated condition cleared SNZ1 instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag EXF1 insert the NOP instruction after the SNZ1 instruction Enable Interrupts The interrupt which is temporarily is enabled Interrupt control register V1 XT TV1 2 2 aes Interrupt enable flag INTE 4 M interrupts enabled El instruction interrupt execution started X it can be 0 or 1 Fig 2 2 4 INT1 interrupt setting example Note The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock 2 20 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts Disable Interrupts Timer 1 interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI instruction Timer 1 interrupt occurrence disabled Interrupt control register V1 Stop Timer Operation Timer 1 and prescaler are tempora
52. R W Q13 Not used This bit has no function but read write is enabled Qo Selected pin AINO AIN1 AIN2 AIN3 Not available for 4513 Group AIN5 Not available for 4513 Group Not available for 4513 Group 111 Not available 4513 Group Notes 1 R represents read enabled and W represents write enabled 2 Select AIN4 AIN7 with register Q1 after setting register Q2 Q12 Analog input pin selection bits Note 2 Q11 ojoilo o 1 2 0 control register 02 Analog input pin selection bits A D operation mode control bit assigned to register Q2 Set the contents of this register through register A with the TQ2A instruction The TAQ2 instruction can be used to transfer the contents of register Q2 to register A Table 2 5 2 shows the A D control register Q2 at reset 00002 Table 2 5 2 A D control register Q2 A D control register Q2 at power down state retained Q23 A D operation mode control bit 9 1 Comparator mode Q22 P43 AIN7 P42 AIN6 pin function 0 P43 P42 I O Note 4 selection bit Note 3 1 AIN7 AIN6 P43 P42 Output Note 4 Q2 P41 AIN5 pin function selection bit 0 P41 I O Note 4 Note 3 1 AIN5 P41 Output Note 4 Q20 P40 AIN4 pin function selection bit 0 P40 1 Note 4 Note 3 1 AIN4 P40 Output Note 4
53. Serial 4 4 211 nennen 1 36 Fig 23 Serial I O register state when transferring sss 1 37 Fig 24 Serial connection example esee nennen 1 38 Fig 25 Timing of serial I O data transfer 1 39 Fig 26 A D conversion circuit 1 41 Fig 27 A D conversion timing 1 44 ig 28 Setting registers 1 44 Fig 29 Comparator operation timing 1 45 Fig 30 Definition of A D conversion 1 46 Fig 31 Voltage comparator 1 47 F1g 32 Heset release TIMING tete terea ci cipes ee 1 49 Fig 33 RESET pin input waveform and reset operation 1 49 Fig 34 Power on reset circuit example estende dta nini eek Rida 1 50 Fig 35 Internal state at ci eene reri career d n ER Ede PL redes 1 51 Fig 36 Voltage drop detection reset circuit 1 52 Fig 37 Voltage drop detection circuit operation 1 52 Fig 88 State eee ata 1 55 Fig 39 Set source and clear source of the P 1 55 Fig 40 Start condition id
54. Timer 1 underflow signal output divided by 2 CNTRO output control bit CNTRO output control by timer 2 underflow signal divided by 2 De l O CNTRO input D6e CNTRO output control bit Note R represents read enabled and W represents write enabled oj joj 2j o 2 o CNTRO l O De input 1 32 4513 4514 Group User s Manual 1 Timer control registers Timer control register W1 Register W1 controls the count operation of timer 1 the selection of count start synchronous circuit and the frequency dividing ra tio and count operation of prescaler Set the contents of this register through register A with the TW1A instruction The TAW1 instruction can be used to transfer the contents of register W1 to register A Timer control register W2 Register W2 controls the count operation and count source of timer 2 Set the contents of this register through register A with the TW2A instruction TAW2 instruction can be used to trans fer the contents of register W2 to register A Timer control register W3 Register W3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit Set the contents of this register through register A with the TW3A in struction The TAW3 instruction can be used to transfer the contents of register W3 to register A Timer control register W4 Register W4 controls the count operation and count source of timer 4 Set th
55. User s Manual HARDWARE FUNCTION BLOCK OPERATIONS 7 Interrupt sequence Interrupts only occur when the respective INTE flag interrupt en able bits V1o V13 and V20 V23 and interrupt request flag are curs after 3 machine cycles only when the three interrupt condi tions are satisfied on execution of other than one cycle instructions Refer to Figure 16 1 The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied The interrupt oc When an interrupt request flag is set after its interrupt is enabled Note 1 f XiN middle speed mode FLTLFLFLELFLFLFLFLFLELFLILTLE 1 machine cycle Ti Ts Ti 1 r 1 El instruction execution cycle 1 ES WE S dinis disabled state Interrupt enable flag INTE Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary EXF1 Dou n Interrupt activated condition is satisfied INTO INT1 External interrupt 1 Timer 2 Timer 3 Timer 4 A D and Serial interrupts T2F T4F ADF SIOF Flag cleared z 2 to 3 machine cycles Notes 2 3 The program starts from the interrupt address Notes 1 The 4513 4514 Group operates in the middle speed mode after system is released fr
56. a product listed herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials if these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein Preface This user s manual describes the hardware and instructions of Mitsubishi s 4513 4514 Group CMOS 4 bit microcomputer After reading this manual the user should have a through knowledge of the functions and features of the 4513 4514 G
57. address DR2 DR1 DRo A2 A1 Ao 2 specified by registers D and A in page p Call the subroutine in page 2 Calls the subroutine at address a in page 2 Call the subroutine Calls the subroutine at address a in page p Call the subroutine Calls the subroutine at address DR2 DR1 DRo A2 A1 2 specified by registers D and A in page p Skip at uncondition Returns from interrupt service routine to main routine Returns each value of data pointer X Y Z carry flag skip status NOP mode status by the continuous de scription of the LA LXY instruction register A and register B to the states just before interrupt Returns from subroutine to the routine called the subroutine Returns from subroutine to the routine called the subroutine and skips the next instruction at uncondition Clears 0 to the interrupt enable flag INTE and disables the interrupt Sets 1 to the interrupt enable flag INTE and enables the interrupt Skips the next instruction when the contents of EXFO flag is 1 After skipping clears 0 to the EXFO flag Skips the next instruction when the contents of EXF1 flag is 1 After skipping clears 0 to the EXF1 flag 4513 4514 Group User s Manual 1 75 HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS continued Paramete Instruction code Mnemonic Function Hexadecimal Number of words Number of cycles D7 De Ds D4 D3 D2 Di inst
58. an analog input pin Fig 47 Analog input external circuit example 1 About 1kQ Fig 48 Analog input external circuit example 2 POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back up Note that system cannot enter the RAM back up state when ex ecuting only the POF instruction Be sure to disable interrupts by executing the DI instruction be fore executing the EPOF instruction Analog input pins Note the following when using the analog input pins also for 1 port P4 functions e Even when P40 AIN4 P43 AIN7 are set to pins for analog input they continue to function as 40 43 Accordingly when any of them are used as I O port and others are used as analog input pins make sure to set the outputs of pins that are set for analog input to 1 Also the port input function of the pin func tions as an analog input is undefined TALA instruction When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A si multaneously the low order 2 bits of register A is 0 Program counter Make sure that the PCH does not specify after the last page of the built in ROM G Port In the 4513 Group when the IAPS instruction is executed note that the high order 2 bits of register A is undefined 4513 4514 Group User s Manual HARDWARE LIST OF
59. and the reload register R2 with the T2AB instruction Timer 2 starts counting after the following process set data in timer 2 select the count source with the bits 0 and 1 of register W2 and set the bit 3 of register W2 to 1 When a value set in timer 2 is n timer 2 divides the count source signal by 1 n 0 to 255 Once count is started when timer 2 underflows the next count pulse is input after the contents of timer 2 becomes 0 the timer 2 interrupt request flag T2F is set to 1 new data is loaded from reload register R2 and count continues auto reload function Data can be read from timer 2 with the TAB2 instruction When reading the data stop the counter and then execute the TAB2 in struction The output from De CNTRO pin by timer 2 underflow signal divided by 2 can be controlled 1 33 HARDWARE FUNCTION BLOCK OPERATIONS 6 Timer 3 interrupt function Timer 3 is an 8 bit binary down counter with the timer 3 reload reg ister R3 Data can be set simultaneously in timer 3 and the reload register R3 with the T3AB instruction Data can be written to re load register R3 with the TR3AB instruction When writing data to reload register R3 with the TR3AB instruction the downcount after the underflow is started from the setting value of reload register R3 Timer 3 starts counting after the following process set data in timer 3 select the count source with the bits 0 a
60. code for entire EPROM area LI LL hexadecimal notation EPROM Type 276256 270512 Low order 5 bit data High order 5 bit data 000016 8 00K 1FFF e 4000 8 00 5FFF e 2 7FFFie Set FF16 in the shaded area Set 1112 in the area 2 Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered Fill out the approximate Mark Specification Form 42P2R A for M34514M8 XXXFP and attach to the Mask ROM Order Confirmation Form 3 Comments of low order and high order 5 bit data Low order 5 bit data 4513 4514 Group User s Manual 000016 1FFF e 400016 5FFF e 3 35 APPENDIX 3 6 Mark specification form 3 6 Mark specification form 32P4B 32 PIN SHRINK DIP MARK SPECIFICATION FORM Please choose one of the marking types below and enter the Mitsubishi catalog name and the special mark if needed A Standard Mitsubishi Mark Mitsubishi lot number 5 6 digit 7 digit 2 Mitsubishi catalog name VM MV VN MAR Customer s Parts Number Mitsubishi catalog name G2 POMPOM Customer s Parts Number Note The fonts and size of characters are standard Mitsubishi type T Mitsubi
61. connect to Vss Note 2 P10 P13 Open or connect to Vss Note 2 AIN4 P40 AIN5 P41 42 AIN7 P43 Notes 1 After system is released from reset port is in an input mode di rection register FRO 00002 2 When the POo P03 and P10 P13 are connected to Vss turn off their pull up transistors register 0 0 and also invalidate the key on wakeup functions register 0 0 by software When these pins are connected to Vss while the key on wakeup func tions are left valid the system fails to return from RAM back up state When these pins are open turn on their pull up transistors register 0 1 by software or set the output latch to 0 Be sure to select the key on wakeup functions and the pull up functions with every two pins If only one of the two pins for the key on wakeup function is used turn on their pull up transistors by software and also disconnect the other pin i 0 1 2 or 3 Note when the output latch is set to 0 and pins are open After system is released from reset port is in a high impedance state un til it is set the output latch to O by software Accordingly the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high impedance state To set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away cau
62. control signal transmission enabled state L level However SCK pin initial level 2 H level Start Serial I O Operation Serial transfer starts by clock of master side Check Serial I O Interrupt Request Serial I O Interrupt Occur SIOF flag is checked SNZSI instruction Receive Data Processing System enters to control signal transmission disabled state H level Data processing received by serial transfer is executed Register SI register A register B TABSI instruction When serial communication is executed 9 to 9 are repeated X it can be 0 or 1 Fig 2 4 6 Slave serial I O example 4513 4514 Group User s Manual 2 A7 APPLICATION 2 4 Serial 2 4 5 Notes on use 1 Note when an external clock is used as a synchronous clock An external clock is selected as the synchronous clock the clock is not controlled internally Serial transfer is continued as long as an external clock is input If an external clock is input 9 times or more and serial transfer is continued the receive data is transferred directly as transmit data so that be sure to control the clock externally Note also that the SIOF flag is set when a clock is counted 8 times Make sure that the initial input level on the external clock pin is always H level Table 2 4 2 shows the recommended operating conditions when using serial with an external clock Figure 2 4 7 shows an input waveform of
63. interrupt valid wave form of P31 INT1 pin is changed with the bit 2 of register I2 refer to Figure 45G Depending on the input state of the P31 INT1 pin the external 1 interrupt request flag EXF1 may be set when the interrupt valid waveform is changed Accordingly clear bit 2 of register 12 and execute the SNZ1 instruction to clear the EXF1 flag after execut ing at least one instruction refer to Figure 459 XX0X2 The SNZ1 instruction is valid Change of the interrupt valid waveform The SNZ1 instruction is executed X this bit is not related to the setting of INT1 Fig 45 External 1 interrupt program example One Time PROM version The operating power voltage of the One Time PROM version is 2 5V to 5 5 V Multifunction The input of De D7 P20 P22 I O of P30 and P31 input of CMPO 1 CMP1 and I O of P40 P43 can be used even when 0 CNTR1 Sck Sour SIN INTO INT1 AINO AIN3 AIN4 AIN7 are selected 1 59 ARDWARE LIST OF PRECAUTIONS A D converter 1 When the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode with the bit 3 of register Q2 in a program be careful about the following notes Clear the bit 2 of register V2 to 0 to change the operating mode of the A D converter from the comparator mode to the A D con version mode with the bit 3 of register Q2
64. is initialized to 7 at RAM back up 3 The state of the timer is undefined A Initialize the watchdog timer with the WRST instruction and then execute the POF instruction 5 The state is retained when the voltage comparator function is selected with the voltage comparator control register Q3 4513 4514 Group User s Manual 2 59 APPLICATION 2 9 RAM back up Table 2 9 2 Return source and return condition Return source Return condition Remarks Ports PO P1 Return by an external Set the port using the key on wakeup function selected edge input H L with register KO to H level before going into the RAM back up state because the port PO shares the falling edge detection circuit with port P1 Port P3o INTO Return by an external H level Select the return level L level or H level with the bit or L level input 2 of register 11 according to the external state before The EXFO flag is not set going into the RAM back up state Port P31 INT1 Return by an external H level Select the return level L level or H level with the bit or L level input 2 of register 12 according to the external state before The EXF1 flag is not set going into the RAM back up state External wakeup signal 2 Start condition identification When system returns from both RAM back up mode and reset software is started from address 0 in page O The start condition
65. is selected Timer 1 count time is set Timer control register W6 x x o 1 CNTRO output selected TW6A instruction Timer 1 reload register 1 2916 Timer count value 41 set T1AB instruction Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag 0 Timer 1 interrupt activated condition cleared SNZT1 instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction Start Timer 1 Operation Timer 1 and prescaler temporarily coe Timer control register wifi Timer 1 operation start TW1A instruction d Prescaler operation start Enable Interrupts The timer 1 interrupt which is temporarily disabled i is enabled Timer 1 interrupt occurrence enabled Interrupt control register V1 CERE instruction Interrupt enable flag INTE 1 interrupts enabled El instruction Stop CNTRO Output De CNTRO is set to CNTRO input pin and it is set to the high impedance state b3 bo Timer control register W6 x x o o CNTRO input pin set TW6A instruction Output latch of port De is set to 1 SD instruction X it can be 0 or 1 Fig 2 3 4 CNTRO output setting example 4513 4514 Group User s Manual 2 33 APPLICATION 2 3 Timers Disab
66. lt lt lt lt lt lt 0 15VDD loH peak H level peak output current P5 VDD 5 0V 3 gt 3 0 V loH avg H level average output current P5 Note VDD 5 0V 3 gt 3 0 L leve peak output current P3 RESET VDD 5 0 VDD 3 0 V L peak L leve peak output current De D7 5 0 V VDD 3 0 V L peak L leve peak output current 00 05 5 0 V VDD 3 0 V L peak L leve peak output current P1 P5 Sck SOUT D 5 0V 3 0 V L avg L leve average output current P3 RESET Note VDD 5 0V VDD 23 0V L avg L leve L leve average output current average output current average output current H level total average current De D7 Note Do Ds Note P1 P5 SCK Sour Note P5 VDD 5 0V VDD 23 0V L leve total average current P5 D RESET SCK SOUT PO P1 P3 P4 Note The average output current IOH IOL is the average value during 100 ms 4513 4514 Group User s Manual 3 3 APPENDIX 3 1 Electrical characteristics Table 3 1 3 Recommended operating conditions 2 Mask ROM version Ta 20 C to 85 C VDD 2 0 V to 5 5 V unless otherwise noted One
67. operating conditions 2 3 4 Table 3 1 4 Electrical characteristics nnne nennen 3 5 Table 3 1 5 A D converter recommended operating 3 6 Table 3 1 6 A D converter characteristics 2 3 6 Table 3 1 7 Voltage drop detection circuit 3 6 Table 3 1 8 Voltage comparator recommended operating 5 3 7 Table 3 1 9 Voltage comparator em 3 7 4513 4514 Group User s Manual CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS SYMBOL LIST OF INSTRUCTION FUNCTION INSTRUCTION CODE TABLE MACHINE INSTRUCTIONS CONTROL REGISTERS BUILT IN PROM VERSION HARDWARE 1 2 4513 4514 Group User s Manual DESCRIPTION The 4513 4514 Group is a 4 bit single chip microcomputer de signed with CMOS technology Its CPU is that of the 4500 series using a simple high speed instruction set The computer is equipped with serial I O four 8 bit timers each timer has a reload register and 10 bit A D converter The various microcomputers in the 4513 4514 Group include varia tions of the built in memory type and package as shown in the table below FEATURES
68. reset circuit VDD VRST detection voltage Voltage drop detection 1 circuit output The microcomputer starts operation after f XIN is counted gt 16892 to 16895 times RESET pin Notes 1 Pull up RESET pin externally 2 Refer to the voltage drop detection circuit in the electrical characteristics for the rating value of VRST detection voltage Fig 37 Voltage drop detection circuit operation waveform 1 52 4513 4514 Group Users Manual RAM BACK UP MODE The 4513 4514 Group has the RAM back up mode When the EPOF and POF instructions are executed continuously system enters the RAM back up state The POF instruction is equal to the NOP instruction when the EPOF instruction is not ex ecuted before the POF instruction As oscillation stops retaining RAM the function of reset circuit and states at RAM back up mode current dissipation can be reduced without losing the contents of RAM Table 20 shows the function and states retained at RAM back up Figure 38 shows the state transition 1 Identification of the start condition Warm start return from the RAM back up state or cold start re turn from the normal reset state can be identified by examining the state of the power down flag P with the SNZP instruction 2 Warm start condition When the external wakeup signal is input after the system enters the RAM back up state by executing the and POF instruc tions continuously the CPU starts executing t
69. s Manual APPENDIX 3 2 Typical characteristics 3 2 6 Analog input current characteristics pins AINO AIN7 1 3 0 V f XIN 2 MHz middle speed mode 25 Ta 25 C Analog input current IAIN nA 0 0 5 1 1 5 2 Analog input voltage VAIN V 2 VDD 3 0 V 4 MHz middle speed mode iod Ta 25 C Analog input current IAIN nA 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 Analog input voltage VAIN V 4513 4514 Group User s Manual 3 17 APPENDIX 3 2 Typical characteristics 3 VDD 3 0 V f XiN 2 MHz high speed mode Analog input current IAIN nA 1 5 2 Analog input voltage VAIN V 4 5 0 V f XiN 4 MHz high speed mode 200 2 5 Analog input current nA 0 0 5 1 1 5 3 5 Ta 25 Ta 25 C 2 2 5 3 Analog input voltage VAIN V 3 18 4513 4514 Group User s Manual APPENDIX 3 2 Typical characteristics 3 2 7 Vpp ViH VIL characteristics 1 RESET pin Ta 25 C 5 5 VIH rating value 4 5 VIH 4 3 5 3 VIL gt 25 ER gt L zn VIL m rating value 1 eee 0 2 2 5 3 3 5 4 4 5 5 5 5 6 Supply voltage VDD V 2 Ports PO P1 P2 P3 P4 P5 D XIN pin VDCE pin 25 C 5 __ rating value 4 5 Nd 4 T VIH VIL VIL rating value 2 2 5 3 3 5 4 4 5 5 5 5 6 Supply v
70. signal divided by 8 selection bit Instruction clock signal divided by 4 Input ports P20 P21 P22 selected J11 Serial port selection bit Serial I O ports SCK SOUT SiN input ports P20 P21 P22 selected External clock Internal clock instruction clock divided by 4 or 8 9 9 J10 Serial synchronous clock selection bit A D control register Q1 reset 00002 at RAM back up state retained Note used This bit has no function but read write is enabled Selected pins Analog input pin selection bits Note 2 N3 N4 Not available for the 4513 Group 5 Not available for the 4513 Group N6 Not available for the 4513 Group 7 Not available for the 4513 Group A D control register Q2 reset 00002 at RAM back up state retained A D conversion mode Comparator mode P43 P42 A D operation mode selection bit P43 AIN7 and P42 AIN6 pin function selec tion bit Not used for the 4513 Group P41 AIN5 pin function selection bit Not used for the 4513 Group P40 AIN4 pin function selection bit Not used for the 4513 Group read write enabled for the 4513 Group AIN6 P43 P42 read write enabled for the 4513 Group P41 read write enabled for the 4513 Group AIN5 P41 read write enabled for the 4513 Group P40 read write enabled for the 4513 Group AIN4 P40 read write enable
71. state of port P2 is transferred to register A when the IAP2 instruction is executed However port P2 is 3 bits and is fixed to 0 2 2 4513 4514 Group User s Manual APPLICATION 2 1 I O pins 4 Port P3 Port is a 4 bit I O port for the 4514 Group and 2 bit I O port for the 4513 Group B input output of port P3 Data input to port Set the output latch of specified port P3i i20 to 3 to 1 with the OP3A instruction If the output latch is set to 0 L level is input The state of port is transferred to register A when the IAP3 instruction is executed However A2 and are undefined in the 4513 Group Data output from port The contents of register is output to port P3 with the OP3A instruction The output structure is an N channel open drain 5 Port P4 The 4513 Group does not have this port Port is a 4 bit I O port B input output of port P4 Ports 40 4 are also used as AIN4 AIN7 Therefore when P40 AIN4 P43 AIN7 are used as port set corresponding bits of A D control register Q2 to 0 Data input to port P4 Set the output latch of specified port 1 0 to 3 to 1 with the instruction If the output latch is set to 0 L level is input The state of port P4 is transferred to register A when the IAP4 instruction is executed Data output from port P4 The contents of register A is output to port P4 with
72. state retained Stop state retained Timer 2 control bit Operating Not used This bit has no function but read write is enabled Count source Timer 1 underflow signal Timer 2 count source selection bits Prescaler output CNTRO input Timer control register W3 16 bit timer WDT underflow signal reset 00002 at RAM back up state retained Timer 3 control bit Stop state retained Operating Timer 3 count start synchronous circuit Count start synchronous circuit not selected control bit Count start synchronous circuit selected Count source Timer 2 underflow signal Timer 3 count source selection bits Prescaler output Not available Timer control register W4 Not available reset 00002 at RAM back up state retained Timer 4 control bit Stop state retained Operating Not used This bit has no function but read write is enabled Count source Timer 3 underflow signal Timer 4 count source selection bits Prescaler output CNTR1 input Timer control register W6 Not available reset 00002 at RAM back up state retained Timer 3 underflow signal output divided by 2 CNTR1 output control bit 1 output control by timer 4 underflow signal divided by 2 D7 CNTR1 function selection bit D7 l O CNTR1 input 1 1 0 07 input
73. the f XIN oscillation Fig 2 10 2 Structure of clock control circuit 2 10 3 Notes on use 1 Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board Accordingly consult the oscillator manufacturer for values of each part connected the oscillator 2 64 4513 4514 Group User s Manual CHAP 702 NDIX 3 1 Electrical characteristics 3 2 Typical characteristics 3 3 List of precautions 3 4 Notes on noise 3 5 Mask ROM confirmation form 3 6 Mark specification form 3 7 Package outline APPENDIX 3 1 Electrical characteristics 3 1 Electrical characteristics 3 1 1 Absolute maximum ratings Table 3 1 1 Absolute maximum ratings Parameter Conditions Ratings Supply voltage 0 3 to 7 0 P1 2 P5 RESET vee 0 3 to VDD 0 3 Input voltage Do D7 0 3 to 13 Input voltage AINO AIN7 0 3 to VDD 0 3 Output voltage PO P1 P3 P4 P5 RESET 0 3 to VDD 0 3 Output voltage Do D7 Output transistors in cut off state 2031013 Output voltage XOUT 0 3 to VDD 0 3 Package 42P2R 300 Power dissipation Package 32P6B 300 Package 32P4B 1100 Operating temperature range 20 to 85 Storage temperature range 40 to 125 3 2 4513 4514 Group User s Manual 3 1 2 Recom
74. to use A D conversion How to use A D conversion is explained using as example in which the analog input from P40 AIN4 pin is A D converted and the high order 4 bits of the converted data are stored in address M Z X Y 0 0 0 the middle order 4 bits in address M Z X Y 0 0 1 and the low order 2 bits in address M Z X Y 0 0 2 of RAM The A D interrupt is not used in this example After selecting the pin function with the bit 0 of the register Q2 select AiN4 pin and A D conversion mode with the register Q1 refer to Figure 28 Execute the ADST instruction and start A D conversion Examine the state of ADF flag with the SNZAD instruction to de termine the end of A D conversion Transfer the low order 2 bits of converted data to the high order 2 bits of register A TALA instruction Transfer the contents of register A to M Z X Y 0 0 2 Transfer the high order 8 bits of converted data to registers A and B TABAD instruction Transfer the contents of register A to M Z X Y 0 0 1 Transfer the contents of register B to register A and then store into M Z X Y 0 0 0 Bit 0 1 Bit 0 0 A D control register Q2 Am4 function selected A D conversion mode A D control register Q1 pin selected X Set an arbitrary value Fig 28 Setting registers 1 44 4513 4514
75. word of a two word instruction are described below The second word ang cannot be used in the M34513M2 XXXSP FP BL 10 paaa aaaa and cannot be used in the M34513M4 XXXSP FP BML 10 paaa aaaa and cannot be used in the M34513E4FP BLA 10 00 cannot be used the M34513M6 XXXFP BMLA 10 00 SEA 00 0111 nnnn SZD 00 0010 1011 1 66 4513 4514 Group User s Manual HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE continued for 4513 Group 100000 100001 100010100011 00100100101 100110 100111 101000 101001 1010104101011101100101101 101110 101111 110000 111111 03 22 23 25 28 30 3 notation IAPO 1 SNZT1 IAP1 TAB2 SNZT2 IAP2 TAB3 SNZT3 IAP3 TAB4 SNZTA4 SNZAD TSIAB SNZSI TRSAB The above table shows the relationship between machine language codes and machine language instructions D3 Do show the low order 4 bits of the machine language code and 09 04 show the high order 6 bits of the machine language code The hexadecimal representation of the code is also provided There are one word instructions and two word instructions but only the first word of each instruction is shown Do not use code marked The codes for the second word of a t
76. words X 4 bits M34513M6 384 words X 4 bits 1536 bits M34513M8 E8 M34514M6 384 words X 4 bits 1536 bits M34514M8 E8 RAM 384 words X 4 bits 1536 bits Register Z 384 words X 4 bits 1536 bits 384 words X 4 bits 1536 bits Register X 0 Register Y M34513M6 M34513M8 E8 1 384 words M34514M6 7 0 X 0 to 15 34514 8 8 7 7007 f 4 M34513M4 E4 2 0 0 15 4 1 Z 0 X 0107 M34513M2 Fig 12 RAM map 1128 words gt 256 words 4513 4514 Group User s Manual 1 21 HARDWARE FUNCTION BLOCK OPERATIONS INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address interrupt address according to each interrupt source An interrupt occurs when the following 3 conditions are satisfied An interrupt activated condition is satisfied request flag 1 Interrupt enable bit is enabled 1 Interrupt enable flag is enabled INTE 1 Table 3 shows interrupt sources Refer to each interrupt request flag for details of activated conditions 1 Interrupt enable flag INTE The interrupt enable flag INTE controls whether the every inter rupt enable disable Interrupts are enabled when INTE flag is set to 1 with the El instruction and disabled when INTE flag is cleared to 0 with the D
77. 1 Fig 2 2 5 Timer 1 constant period interrupt setting example 4513 4514 Group User s Manual 2 21 APPLICATION 2 2 Interrupts Disable Interrupts Timer 2 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI instruction b3 Interrupt control register V1 0 x x x T E disabled Stop Timer Operation Timer is temporarily stopped Timer 2 count source is selected Timer 2 stop TW2A instruction b3 bo EAE E Timer control register W2 c ed c underflow signal selected Set Timer Value Timer 2 count time is set The formula is shown below Timer 2 reload register R2 2716 Timer count value 39 set T2AB instruction Clear Interrupt Request Timer 2 interrupt activated condition is cleared Timer 2 interrupt request flag T2F 0 Timer 2 interrupt activated condition cleared SNZT2 instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T2F insert the NOP instruction after the SNZT2 instruction Start Timer 2 Operation Timer 2 temporarily stopped is restarted b3 bo Timer control register W2 Timer 2 operation start TW2A instruction Enable Interrupts The timer 2 interrupt which is temporarily disabled is enabled b3 bo H Interrupt control register V1 enabled Interrupt enable flag INTE 1 All i
78. 1 new data is loaded from reload register R4 and count continues auto reload function Data can be read from timer 4 with the 4 instruction When reading the data stop the counter and then execute the TABA in struction The output from D7 CNTR1 pin by timer 4 underflow signal divided by 2 can be controlled 8 Timer interrupt request flags T1F T2F and Each timer interrupt request flag is set to 1 when each timer underflows The state of these flags can be examined with the skip instructions SNZT1 SNZT2 SNZT3 and SNZT4 Use the interrupt control registers V1 V2 to select an interrupt or a skip instruction An interrupt request flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with a skip instruction 1 34 9 Timer De CNTRO D7 CNTR1 De CNTRO pin has functions to input the timer 2 count source and to output the timer 1 and timer 2 underflow signals divided by 2 D7 1 has functions to input the timer 4 count source and to output the timer 3 and timer 4 underflow signals divided by 2 The selection of De CNTRO pin function can be controlled with the bit 0 of register W6 The selection of D7 CNTR1 pin function can be controlled with the bit 2 of register W6 The following signals can be selected for the CNTRO output signal with the bit 1 of register W6 timer 1 underflow signal divided by 2 the signal of
79. 17 Fig 5 Stack registers SKS St UCtUTE enne 1 18 Fig 6 Example of operation at subroutine call 1 18 Fig 7 Program counter PC str ct te oett edi eer i e 1 19 Fig 8 Data pointer DP nennen 1 19 Fig 9 SD instruction execution example eese enne nne nennen 1 19 Fig map of M34514M9 EB8 1 20 Fig 11 Page 1 addresses 008016 to OOFF16 structure 1 20 Figs 12 RAM cR 1 21 Fig 13 Program example of interrupt 1 23 Fig 14 Internal state when interrupt 1 23 Fig 15 Interrupt system diaga M esseri tinnen nennen nnne nennen 1 23 Fig 16 INTE MUPL S COUCN CC 1 25 Fig 17 External interrupt circuit 1 26 Fig 18 Auto reload etos cornes ntt cedes enr i e pta RU ds 1 29 Fig 19 Timets StRUCUUNG eri ete bn et denen 1 31 19 20 Watchdog timer TUnctloh ieri eti uarie d eR To secure 1 35 Fig 21 Program example to enter the RAM back up mode when using the watchdog timer 1 35 Fig 22
80. 2 or TAB4 instruction to read its data Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating avoid a timing when timer 1 or timer 3 underflows e 0 pin When the interrupt valid waveform of the P30 INTO pin is changed with the bit 2 of register 1 in software be careful about the following notes Clear the bit 0 of register V1 to 0 before the interrupt valid wave form of P30 INTO pin is changed with the bit 2 of register 11 refer to Figure 440 Depending on the input state of the P30 INTO pin the external 0 interrupt request flag EXFO may be set when the interrupt valid waveform is changed Accordingly clear bit 2 of register 1 and execute the SNZO instruction to clear the EXFO flag after execut ing at least one instruction refer to Figure 442 LA 4 XXX02 TV1A The SNZO instruction is valid LA THA Interrupt valid waveform is changed NOP SNZO NOP The SNZO instruction is executed X this bit is not related to the setting of INTO pin Fig 44 External 0 interrupt program example 4513 4514 Group User s Manual HARDWARE LIST OF PRECAUTIONS IP31 INT1 pin When the interrupt valid waveform of P31 INT1 pin is changed with the bit 2 of register 12 in software be careful about the fol lowing notes Clear the bit 1 of register V1 to 0 before the
81. 3 4514 Group User s Manual 1 87 HARDWARE BUILT IN PROM VERSION BUILT IN PROM VERSION In addition to the mask ROM versions the 4513 4514 Group has programmable ROM version software compatible with mask ROM The built in PROM of One Time PROM version can be written to and not be erased The built in PROM versions have functions similar to those of the mask ROM versions but they have PROM mode that enables writ ing to built in PROM Table 25 shows the product of built in PROM version Figure 49 and 50 show the pin configurations of built in PROM versions Table 25 Product of built in PROM version Product PROM size X 10 bits RAM size X 4 bits Package ROM type M34513E4SP FP 4096 words 256 words SP 32P4B FP 32P6B A One Time PROM version M34513E8FP 8192 words 384 words 32P6B A M34514E8FP Do D1 D2 D3 D4 D5 De CNTRO D7 CNTR1 20 5 P21 SOUT P22 SIN RESET CNVss XOUT XIN Vss 8192 words dSrAelSoveW Outline 32P4B ale D4 D5 De CNTRo D7 CNTR1 P20 Sck P21 SouT P22 SIN M34513ExFP P3o INTO 16 Outline 32P6B A Fig 49 Pin configuration of built in PROM version of 4513 Group 384 words P13 P12 P11 P10 POs P01 0 Ains CMP 1 AIN2 CMP1 AIN1 CMPO P31 INT1 P3o INTO VDCE P02 P01 0 1 20
82. 5 V mede 4513 4514 Group User s Manual 2 53 APPLICATION 2 6 Voltage comparator 2 6 Voltage comparator The 4513 4514 Group has two voltage comparators 1 CMP1 This section describes the voltage comparator function related registers and notes 2 6 1 Voltage comparator function 1 CMPO E Voltage comparison The voltage of CMPO is compared with that of CMPO and the result is stored into bit of the voltage comparator control register Q3 2 1 Voltage comparison The voltage of CMP1 is compared with that of CMP1 and the result is stored into bit 1 of the voltage comparator control register Q3 2 6 2 Related registers 1 Voltage comparator control register Q3 The voltage comparator CMP1 control bit is assigned to bit 3 the voltage comparator control bit is assigned to bit 2 the CMP1 comparison result store bit is assigned to bit 1 and the comparison result store bit is assigned to bit 0 Set the contents of this register through register A with the instruction The TAQ3 instruction can be used to transfer the contents of register Q3 to register A Table 2 6 1 shows the voltage comparator control register Q3 Table 2 6 1 Voltage comparator control register Q3 Volt t trol ister Q3 EE ES at reset 00002 at RAM back up state retained R W Q33 Voltage comparator CMP1 Voltage comparator
83. 513 4514 Group does not have a control pin exclusively used for serial I O Accordingly if a control signal is required use the normal input output ports Fig 2 4 2 Serial I O connection example Master M7 Mo Transfer data Slave 57 50 Transfer data SIN pin SOUT pin Qa Serial register SI SOUT pin SIN pin Serial I O register 51 Mz Me Ms M Ms M VW So Mz Me 5 Ma Ms ie Transfer data setting Transfer starts Falling of clock Rising of clock Falling of clock Sa Transfer completes Fig 2 4 3 Serial register state when transmitting receiving 2 42 4513 4514 Group User s Manual APPLICATION 2 4 Serial I O Master SST instruction Control signal LU s _ AS XSXSXAS X SASASAS 7 the contents of master serial I O register 50 97 the contents of slave serial I O register Rising of SCK serial input Falling of SCK serial output Mo M7 previous MSB contents of master and slave Fig 2 4 4 Serial I O transfer timing 4513 4514 Group User s Manual 2 43 APPLICATION 2 4 Serial The full duplex communication of master and slave is described using the connection example shown in Figure 2 4 2 1 Transmit receive operation of master 2 44 The transmit data is written into the serial I O register SI with the TSIAB instruction When the TSIAB instruction is ex
84. 513M6 XXXFP and attach to 3 32 4513 4514 Group User s Manual GZZ SH52 9 9B lt 85A0 gt 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M34513M8 XXXFP MITSUBISHI ELECTRIC Please fill in all items marked Customer Company name APPENDIX 3 5 Mask ROM order confirmation form Mask ROM number Date issued 1 Confirmation Specify the type of EPROMs submitted Three sets of EPROMs are required for each pattern check in the approximate box If at least two of the three sets of EPROMs submitted contain the identical data we will produce masks based on this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data Thus the customer must be especially careful in verifying the data contained in the EPROMs submitted Issuance signature Date Section head signature Supervisor signature Responsible officer Supervisor Checksum code for entire EPROM area hexadecimal notation EPROM Type 270256 270512 Low order 5 bit data High order 5 bit data 000016 8 00K 1FFF e 4000 8 00K 5FFF e 1 7FFFie Set 16 in the shaded area Set 1112 in the area 2 Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered Fill out the approx
85. 7 Voltage comparator characteristics Parameter Characteristics Voltage comparator function 2 circuits CMP1 Input pin CMPO also used as AIN1 CMP1 CMP1 also used as AIN2 AIN3 Supply voltage 3 0 V to 5 5 V Input voltage 0 3 VDD to 0 7 VDD Comparison check error Typ 20 mV Max 100 mV Response time Max 20 us Voltage comparator control register Q3 4 TQ3A TAQ3 Register A 4 Note Bits 0 and 1 of register can be only read Fig 31 Voltage comparator structure 4513 4514 Group User s Manual 1 47 HARDWARE FUNCTION BLOCK OPERATIONS Table 18 Voltage comparator control register Q3 Voltage comparator control register Q3 Note 2 at reset 00002 at RAM back up state retained Voltage comparator CMP1 invalid Q33 Voltage comparator CMP1 control bit 1 1 Voltage comparator CMP1 valid Q32 Voltage comparator control bit Voltage comparator invalid Voltage comparator CMPO valid Q31 CMP1 comparison result store bit CMP1 gt CMP1 CMP1 CMP1 gt 0 0 0 comparison result store bit Notes 1 R represents read enabled and W represents write enabled 2 Bits 0 and 1 of register Q3 can be only read 1 Voltage comparator control register Q3 Register Q3 controls t
86. 7 to 0 are the ROM pattern in ad dress DR2 DR1 DRo A2 A1 Ao 2 specified by registers A and D in page When this instruction is executed 1 stage of stack register is used Adds the contents of M DP to register A Stores the result in register A The contents of carry flag CY re mains unchanged Adds the contents of M DP and carry flag CY to register A Stores the result in register A and carry flag CY Overflow 0 Adds the value n in the immediate field to register A The contents of carry flag CY remains unchanged Skips the next instruction when there is no overflow as the result of operation Takes the AND operation between the contents of register A and the contents of M DP and stores the re sult in register A Takes the OR operation between the contents of register A and the contents of M DP and stores the result in register A Sets 1 to carry flag CY Clears 0 to carry flag CY Skips the next instruction when the contents of carry flag CY is 0 Stores the one s complement for register A s contents in register A Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right Sets 1 the contents of bit j bit specified by the value j in the immediate field of M DP Clears 0 the contents of bit j bit specified by the value j in the immediate field of M DP Mj DP 0 Skips the next instruction when the contents of bit j bit specified by the value j in the
87. 717 714 lt R13 R10 lt 713 710 lt lt 727 724 lt 23 20 R27 R24 lt 27 24 lt R23 R20 lt T23 T20 lt A B T37 T34 lt T33 T30 R37 R34 737 734 lt R33 R30 T33 T30 lt A lt 47 44 lt T43 T40 847 844 lt T47 T44 lt R43 R40 lt T43 T40 lt 9 I o o lt E R17 R14 lt B 13 10 lt R37 R34 lt R33 R30 lt T1F 21 After skipping T1F 0 T2F 21 After skipping T2F 0 TSF 21 After skipping T3F 0 T4F 21 After skipping 0 1 78 4513 4514 Group User s Manual HARDWARE MACHINE INSTRUCTIONS Skip condition Datailed description Transfers the contents of timer 1 to registers A and B Transfers the contents of registers A and B to timer 1 and timer 1 reload register Transfers the contents of timer 2 to registers A and B Transfers the contents of registers A and B to timer 2 and timer 2 reload register Transfers the contents of timer 3 to registers A and B Transfers the contents of registers A and B to timer 3 and timer 3 reload register Transfers the contents of timer 4 to registers A and B Transfers the contents of registers A and B to timer 4 and timer 4 reload register Trans
88. 8 b 0 35 0 45 0 55 M E bi 0 9 1 0 1 3 b2 0 63 0 73 1 08 U U U u Uu u uU U d Uu c 022 027 0 34 D 278 28 0 28 2 b b be E 8 75 8 9 9 05 1778 SEATING PLANE el Z 10 16 Z L 0 32 6 EIAJ Package Code JEDEC Code Weight g Lead Material LQFP32 P 77 0 80 Alloy 42 HD D gt C Recommended Mount Pad ui gt Dimension in Millimeters Symbol Min Nom Max 17 1 0 0 1 0 2 KS A2 1 4 j b 0 3 0 35 0 45 0 105 0 125 0 175 A D 6 9 7 0 7 1 11 6 9 7 0 74 S e 0 8 HD 8 8 9 0 92 7 8 8 9 0 9 2 a L 0 3 0 5 0 7 V Li 1 0 E 0 1 y n o 0 10 b lt L b2 0 5 l2 1 0 Detail F MD 7 4 7 4 4513 4514 Group User s Manual 3 39 APPENDIX 3 7 Package outline
89. A at room temperature VDD 5 V output transistors in the cut off state 4513 4514 Group User s Manual DESCRIPTION Power supply Ground Voltage drop detec tion circuit enable Reset input System clock input Input Output Input HARDWARE PIN DESCRIPTION Function Connected to a plus power supply Connected to 0 V power supply VDCE pin is used to control the operation stop of the voltage drop detection circuit When level is input to this pin the circuit is operating When L level is inpu to this pin the circuit is stopped Connect CNVss to Vss and apply L OV to CNVSS certainly An N channel open drain pin for a system reset When the watchdog timer causes the system to be reset or system reset is performed by the voltage drop de tection circuit the RESET pin outputs L level I O pins of the system clock generating circuit XIN and XOUT can be connected to System clock output Output ceramic resonator A feedback resistor is built in between them port D Input is examined by skip decision 1 0 Each pin of port D has an independent 1 bit wide I O function Each pin has an out put latch For input use set the latch of the specified bit to 417 The output structure is N channel open drain Ports De 07 are also used as CNTRO and CNTR1 respectively 00 port PO Each of ports PO and P1 serves as a 4 bit I O p
90. AD instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the flag ADF insert the NOP instruction after the SNZAD instruction When interrupt is Y not used When interrupt is used Set Interrupt Set Interrupt Interrupts except A D conversion is A D conversion interrupt temporarily disabled is enabled enabled El instruction 50 A D interru pt occurrence enabled Interrupt control register V2 TV2A instruction Interrupt enable flag INTE 1 All interrupts enabled El instruction Start A D Conversion A D conversion operation is started ADST instruction When interrupt is not used When interrupt is used A D Interrupt Request A D Conversion Interrupt Occur D conversion completion flag is checked SNZAD instruciton po Execute A D Conversion High order 8 bits of register AD register A and register TABAD instruction Low order 2 bits of register AD high order 2 bits of register instruction 0 is set to low order 2 bits of register When A D conversion is executed by the same channel to is repeated When A D conversion is executed by the another channel to is repeated X it can be 0 or 1 Fig 2 5 2 A D conversion mode setting example 4513 4514 Group User s Manual 2 51 APPLICATION 2 5 A D converter 2 5 3 Notes on use
91. AM back up state retained 0 Stop state retained 1 Operating 0 Count start synchronous circuit not selected 1 Count start synchronous circuit selected Count source 0 Timer 2 underflow signal 1 Prescaler output Table 2 3 5 Timer control register W3 Timer control register W3 R W W33 control bit Timer 3 count start synchronous circuit control bit W32 W31 Timer 3 count source selection bits 0 Not available Not available W30 Note represents read enabled and W represents write enabled 6 Timer control register W4 The timer 4 count source selection bits are assigned to bits 0 and 1 and the timer 4 control bit is assigned to bit 3 Set the contents of this register through register A with the instruction The instruction can be used to transfer the contents of register W4 to register A Table 2 3 6 shows the timer control register W4 at reset 00002 at RAM back up state retained 0 Stop state retained Operating Table 2 3 6 Timer control register W4 Timer control register W4 R W W43 4 control bit W42 Not used This bit has no function but read write is enabled Count source Timer 3 underflow signal 1 Prescaler output 0 CNTR1 input Not available W41 Timer 4 count source selection bits W40 Note R represents read enabl
92. AND operation between timer 1 underflow signal di vided by 2 and timer 2 underflow signal divide by 2 The following signals can be selected for the CNTR1 output signal with the bit 3 of register W6 timer 3 underflow signal divided by 2 the signal of AND operation between timer 3 underflow signal di vided by 2 and timer 4 underflow signal divide by 2 Timer 2 counts the rising waveform of CNTRO input when the CNTRO input is selected as the count source Timer 4 counts the rising waveform of CNTR1 input when the 1 input is selected as the count source 10 Count start synchronous circuit timer 1 and 3 Each of timer 1 and timer 3 has the count start synchronous circuit which synchronizes P30 INTO pin and P31 INT1 pin respectively and can start the timer count operation Timer 1 count start synchronous circuit function is selected by set ting the bit 0 of register W1 to 1 The control by pin input can be performed by setting the bit 0 of register 11 to 1 The count start synchronous circuit is set by level change H L or L H of P30 INTO pin input This valid waveform is selected by bits 1 111 and 2 12 of register 11 as follows e 11 0 Synchronized with one sided edge falling or rising e 11 1 Synchronized with both edges both falling and rising When register 11 0 synchronized with the one sided edge the ris ing or falling waveform can be selec
93. AiN2 CMP1 AIN1 CMPO P31 INT1 42P2R A Do D1 D2 D3 D4 D5 D6 CNTRO D7 CNTR1 P50 P51 P52 P53 P20 SCK P21 SOUT P22 SIN RESET CNVss XOUT XIN Vss shipped in blank 12 P11 P10 P02 1 P00 P43 AIN7 P42 AIN6 P41 AIN5 P40 AIN4 AIN3 CMP1 AIN2 CMP1 AIN1 CMPO AINO CMPO P33 P32 P31 INT1 P30 INTO VDCE VDD dd83v Outline 42P2R A Fig 50 Pin configuration of built in PROM version of 4514 Group 1 88 4513 4514 Group User s Manual 1 PROM mode The built in PROM version has a PROM mode in addition to a nor mal operation mode The PROM mode is used to write to and read from the built in PROM In the PROM mode the programming adapter can be used witha general purpose PROM programmer to write to or read from the built in PROM as if it were M5M27C256K Programming adapters are listed in Table 26 Contact addresses at the end of this sheet for the appropriate PROM programmer Writing and reading of built in PROM Programming voltage is 12 5 V Write the program in the PROM of the built in PROM version as shown in Figure 51 2 Notes on handling high voltage is used for writing Take care that overvoltage is not applied Take care especially at turning on the power G For the One Time PROM version shipped in blank Mitsubishi Electric corp does not perform PROM writing test and screening in the assembly process and foll
94. D conversion characteristics data Figure 3 2 1 shows the A D accuracy measurement data 1 Non linearity error This means a deviation from the ideal characteristics between Vo to V1022 of actual A D conversion characteristics In Figure 3 2 1 it is 1LSB 2 Differencial non linearity error This means a deviation from the ideal characteristics between the input voltages Vo to 1022 necessary to change the output data to 1 In Figure 3 2 1 this is 1LSB 3 Zero transition error This means a deviation from the ideal characteristics between the input voltages 0 to VDD when the output data changes from 0 to 1 In Figure 3 2 1 this is the value of 4 Full scale transition error This means a deviation from the ideal characteristics between the input voltages 0 to VDD when the output data changes from 1022 to 1023 In Figure 3 2 1 this is the value of 5 Absolute accuracy This menas a deviation from the ideal characteristics between 0 to of actual A D conversion characteristics In Figure 3 2 1 this is the value of ERROR in each of and For the A D converter characteristics refer to the section 3 1 Electrical characteristics 3 14 4513 4514 Group User s Manual APPENDIX 3 2 Typical characteristics 1 3 072 V 2 MHz high speed mode 25
95. E 0 0 5 1 1 5 2 Output voltage VoL V 2 Port P3 RESET pin Ta 25 C 100 90 80 T 70 60 2 50 5 VDD 6V 5 6 30 4 10 Zs 2 0 0 0 5 1 1 5 2 Output voltage VOL V 4513 4514 Group User s Manual 3 11 APPENDIX 3 2 Typical characteristics 3 Pins Do D5 Output current mA 4 Output current mA 100 90 80 70 60 50 40 30 20 Pins 100 70 40 Ta 25 VDD 6 V VDD 5 V VDD 4V VDD 3V 22 2 V 0 0 5 1 1 5 2 Output voltage VOL V De CNTRO D7 CNTR1 Ta 2 25 C VDD 6V VDD 5V VDD 4V VDD 3V VDD 2V A 0 5 1 Output voltage VOL V 4513 4514 Group User s Manual 3 2 3 characteristics Port P5 Output current loH mA 3 2 4 Pull up resistor RPU VDD 2V VDD 3V VDD A4V APPENDIX 3 2 Typical characteristics VDD 5V 0 5 2 2 5 3 3 5 4 Output voltage VOH V VpD RPU characteristics Ports PO P1 350 4 5 6 25 55 6 Ta 25 N 2 5 4 5 5 3 5 4 Supply voltage VDD V 4513 4514 Group User s Manual 3 13 APPENDIX 3 2 Typical characteristics 3 2 5 A D converter typical characteristics 1LSB WIDTH HLGIM 857 gt E amp fra 1022 1023 Fig 3 2 1 A
96. I instruction When any interrupt occurs the INTE flag is automatically cleared to 0 so that other interrupts are disabled until the EI instruction is executed 2 Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction Table 4 shows the interrupt request flag interrupt enable bit and skip instruction Table 5 shows the interrupt enable bit function 3 Interrupt request flag When the activated condition for each interrupt is satisfied the cor responding interrupt request flag is set to 1 Each interrupt request flag is cleared to 0 when either an interrupt occurs or the next instruction is skipped with a skip instruction Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its in terrupt enable bit Once set the interrupt request flag retains set until a clear condition is satisfied Accordingly an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set If more than one interrupt request flag is set when the interrupt dis able state is released the interrupt priority level is as follows shown in Table 3 1 22 Table 3 Interrupt sources Priority level Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Addre
97. Mitsubishi logo is not required check the box below Mitsubishi logo is not required C Special Mark Required B gooo 52 Note1 If the Special Mark is to be Printed indicate the desired layout of the mark in the left figure The layout will be duplicated as close as possible Mitsubishi lot number 6 digit or 7 digit and Mask ROM number 3 digit are always marked 2 If the customer s trade mark logo must be used in the Special Mark check the box below Please submit a clean original of the logo For the new special character fonts a clean font original ideally logo drawing must be submitted Special logo required 3 38 4513 4514 Group User s Manual APPENDIX 3 7 Package outline 3 7 Package outline 32P4B Plastic 32pin 400mil SDIP EIAJ Package Code JEDEC Code Weight g Lead Material SDIP32 P 400 1 78 2 2 Alloy 42 Cu Alloy 93 0110 O UJUUUUUUUUUUIUUIUL gt Dimension Millimeters A 5 08 lt 0 51 1 1 A2 3
98. O Ports P02 P03 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUOO Ports 0 P01 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON Note R represents read enabled and W represents write enabled 2 4 4513 4514 Group User s Manual APPLICATION 2 1 I O pins 2 Key on wakeup control register KO Register KO controls the ON OFF of the key on wakeup function of ports POo P03 and P10 P13 Set the contents of this register through register A with the TKOA instruction The contents of register KO is transferred to register A with the TAKO instruction Table 2 1 2 shows the key on wakeup control register KO Table 2 1 2 Key on wakeup control register KO Key on wakeup control register KO at reset 00002 at RAM back up state retained R W Ports P12 P13 0 Key on wakeup not used key on wakeup control bit 1 Key on wakeup used Ports P10 P11 0 Key on wakeup not used nos key on wakeup control bit 1 Key on wakeup used Ports 02 P03 0 Key on wakeup not used i key on wakeup control bit 1 Key on wakeup used Ports POo P01 0 Key on wakeup not used key on wakeup control bit 1 Key on wakeup used Note R represents read enabled and W represents write enabled 3 A D control register Q2 Bits 0 to 2 of register Q2 controls the pin function selection bits Set the contents of this register through register A with the TQ2A instruc
99. P pin the shortest possible in series and also to the Vss pin When not connecting the resistor make the length of wiring between the VPP pin and the Vss pin the shortest possible refer to Figure 3 4 5 Note Even when a circuit which included an approximately 5 kQ resistor is used in the Mask ROM version the microcomputer operates correctly Reason The VPP pin of the One Time PROM ver sion is the power source input pin for the built in PROM When programming in the built in PROM the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM Because of this noise can enter easily If noise enters the VPP pin abnormal instruction codes or data are read from the built in PROM which may cause a program runaway When the Vr is also used as the CNVss Approximately CNVss VPP Vss In the shortest distance Fig 3 4 5 Wiring for the VPP pin of the One Time PROM version 3 26 3 4 2 Connection of bypass capacitor across Vss line and VDD line Connect an approximately 0 1 bypass capacitor across the Vss line and the VDD line as follows Connect a bypass capacitor across the 55 and the VDD pin at equal length Connect a bypass capacitor across the 55 pin and the VDD pin with the shortest possible wiring Use lines with a larger diameter than other signal lines for Vss line and VDD line Connect the power source wiring via a bypa
100. R34 B R33 R30 lt Timer operation SNZT1 T1F 1 After skipping T1F 0 T2F 21 After skipping T2F 0 21 After skipping T3F 0 1 After skipping 0 Input Output operation A lt PO PO lt A P1 lt A A2 A0 22 2 0 0 lt lt lt 4 P4 lt A lt 5 HARDWARE LIST OF INSTRUCTION FUNCTION LIST OF INSTRUCTION FUNCTION continued Mnemonic Mnemonic Function Function Input Output operation KO lt A lt PUO lt PUO FRO lt TABSI Serial I O control operation lt 813 510 517 5 513 510 lt 517 514 lt lt 01 J1 lt A SIOF 0 Serial I O starting SIOF 1 After skipping SIOF 0 A D conversion operation TABAD A AD5 AD2 lt AD9 AD6 However the com parator mode lt AD3 ADo AD7 AD4 lt AD1 ADo 0 0 lt A AD7 AD4 B A lt Q1 Q1 lt A ADF 0 A D conversion starting ADF 21 After skipping ADF 0 lt 02 02 lt A The 4513 Group does not have these instruction
101. RE FUNCTION BLOCK OPERATIONS Program counter hs N Peme eee V gt A PCH PCL Specifying page Specifying address Fig 7 Program counter PC structure Data pointer DP Xs Register Y 4 Specifying RAM digit Register X 4 Specifying RAM file Register Z 2 Specifying RAM file group Fig 8 Data pointer DP structure Specifying bit position Set Y D De Ds OO ALEL Register Y 4 Port D output latch Fig 9 SD instruction execution example HARDWARE FUNCTION BLOCK OPERATIONS PROGRAM MEMOY ROM The program memory is a mask ROM 1 word of ROM is composed of 10 bits ROM is separated every 128 words by the unit of page addresses 0 to 127 Table 1 shows the ROM size and pages Fig ure 10 shows the ROM map of M34514M8 E8 Table 1 ROM size and pages ROM size Product X 10 bits Pages M34513M2 2048 words 1 M34513M4 E4 4096 words 32 0 to 31 M34513M6 6144 words 48 0 to 47 6 0 to 15 2 01031 8 0 to 47 M34513M8 E8 8192 words 64 0 to 63 A part of page 1 addresses 008016 to 00 16 is reserved for terrupt addresses Figure 11 When an interrupt occurs the address interrupt address corresponding to each interrupt is set in the program counter and the instruction at the interrupt address is executed When using an interrupt service routine write the in struction generating the branch to that routine at an interrupt
102. Specify the type of EPROMs submitted Three sets of EPROMs are required for each pattern check in the approximate box If at least two of the three sets of EPROMs submitted contain the identical data we will produce masks based on this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data Thus the customer must be especially careful in verifying the data contained in the EPROMs submitted Microcomputer name _ M34513M4 XXXSP _IM34513M4 XXXFP Checksum code for entire EPROM area hexadecimal notation EPROM Type 270256 270512 Low order Low order 5 bit data ous 5 bit data OFFF e OFFF e 4000 e 4 00K UM 400016 High order 5 data i 4 1 7FFFie Set FF16 the shaded area Set 1112 in the area of low order and high order 5 bit data 2 Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered Fill out the approximate Mark Specification Form 32P4B for M34513M4 XXXSP 32P6B A for M34513M4 XXXFP and attach to the Mask ROM Order Confirmation Form 3 Comments 4513 4514 Group User s Manual 3 31 APPENDIX 3 5 Mask ROM order confirmation form GZZ SH53 01B lt 85A0 gt 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M34513M6 XXXFP Mask ROM nu
103. Table 2 9 6 shows the interrupt control register 11 Table 2 9 6 Interrupt control register 11 at reset 00002 at RAM back up state retained This bit has no function but read write is enabled Interrupt control register 11 R W 113 Not used Falling waveform L level of INTO pin is recognized with the SNZIO instruction L level Rising waveform H level of INTO pin is recognized with the SNZIO instruction H level Interrupt valid waveform for INTO 112 pin return level selection bit Note 2 114 INTO pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected 0 Disabled timer 1 control enable bit Enabled Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 112 is changed the external interrupt request flag EXFO may be set Accordingly clear EXFO flag with the SNZO instruction 4513 4514 Group User s Manual 2 61 APPLICATION 2 9 RAM back up 4 Interrupt control register 12 The interrupt valid waveform for INT1 pin return level selection bit is assigned to bit 2 the INT1 pin edge detection circuit control bit is assigned to bit 1 and the INT1 pin timer 1 control enable bit is assigned to bit 1 Set the contents of this register through register A with the TI2A instruction In addition the TAI2 instruction can be used to transfer the contents of register I2 to register A
104. Time PROM version Ta 20 C to 85 C VDD 2 5 V to 5 5 V unless otherwise noted Parameter Conditions Limits Typ Oscillation frequency with a ceramic resonator Mask ROM version Middle speed mode 2 5 V to 5 5 V DD 2 0 V to 5 5 V One Time PROM version Middle speed mode DD 2 5 V to 5 5 V Mask ROM version High speed mode DD 4 0 V to 5 5 V DD 2 0 V to 5 5 V One Time PROM version High speed mode DD 4 0 V to 5 5 V V V V VDD 22 5Vto5 5V V V V DD 2 5 V to 5 5 V Oscillation frequency with external clock input Serial external clock period H and L pulse width Mask ROM version Middle speed mode 2 0 V to 5 5 V One Time PROM version Middle speed mode Mask ROM version High speed mode One Time PROM version High speed mode Mask ROM version Middle speed mode 2 5 5 5 VDD 4 0 V to 5 5 V VDD 2 5 V to 5 5 V 2 0 V 5 5 V DD 4 0 V to 5 5 V DD 2 5 V to 5 5 V DD 4 0 V to 5 5 V DD 2 5 V to 5 5 V DD 2 0 V to 5 5 V One Time PROM version Middle speed mode DD 4 0 V to 5 5 V DD 2 5 5 5 V Mask ROM version High speed mode DD 4 0 V to 5 5 V DD 2 5 V to 5 5 V One Time PROM version High speed mode DD 4 0 V to 5 5 V DD 2 5 V to 5 5 V 3 4 Timer external input period H
105. To all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMSs etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 424 N SAS Renesas Technology Corp MITSUBISHI 4 BIT SINGLE CHIP MICROCOMPUTER 4500 SERIES 434 NC SAS Renesas Technology Corp keep safety first your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibili
106. UNCTION BLOCK OPERATIONS 4 Timer 1 interrupt function Timer 1 is an 8 bit binary down counter with the timer 1 reload reg ister R1 Data can be set simultaneously in timer 1 and the reload register R1 with the T1AB instruction Data can be written to re load register R1 with the TR1AB instruction When writing data to reload register R1 with the TR1AB instruction the downcount after the underflow is started from the setting value of reload register R1 Timer 1 starts counting after the following process set data in timer 1 and Q set the bit 1 of register W1 to 1 However P30 INTO pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to 1 When a value set in timer 1 is n timer 1 divides the count source signal by n 1 n 0 to 255 Once count is started when timer 1 underflows the next count pulse is input after the contents of timer 1 becomes 0 the timer 1 interrupt request flag T1F is set to 1 new data is loaded from reload register R1 and count continues auto reload function Data can be read from timer 1 with the TAB1 instruction When reading the data stop the counter and then execute the TAB1 in struction Timer 1 underflow signal divided by 2 can be output from De CNTRO pin 5 Timer 2 interrupt function Timer 2 is an 8 bit binary down counter with the timer 2 reload reg ister R2 Data can be set simultaneously in timer 2
107. Vss line and the VDD 3 26 Fig 3 4 7 Analog signal line and a resistor and 3 27 Fig 3 4 8 Wiring for a large current signal 3 27 Fig 3 4 9 Wiring to a signal line where potential levels change frequently 3 28 Fig 3 4 10 Vss pattern on the underside of an 3 28 Fig 3 4 11 Watchdog timer by software 00 3 29 vi 4513 4514 Group User s Manual List of tables List of tables CHAPTER 1 HARDWARE Table Selection of system 1 11 Table 1 ROM size and 1 20 Table 2 RA MSIZ ELM 1 21 Table 3 Int rr pt SOUCO nectare uuu ebd 1 22 Table 4 Interrupt request flag interrupt enable bit and skip instruction 1 22 Table 5 Interrupt enable bit function sssssseeeeeeneenn een nennen 1 22 Table 6 Interrupt control registers top cea ELI QUE Sie 1 24 Table 7 External interrupt activated 1 26 Table 8 External interrupt control 1 28 Tab
108. address Page 2 addresses 010016 to 017F 16 is the special page for sub routine calls Subroutines written in this page can be called from any page with the 1 word instruction BM Subroutines extending from page 2 to another page can also be called with the BM in struction when it starts on page 2 ROM pattern bits 7 to 0 of all addresses can be used as data ar eas with the TABP p instruction to 15 98 76543 210 000016 007F16 008016 OOFF16 Interrupt address page 010016 Subroutine special page 017F16 P iis 018016 OFFF16 1FFF16 Fig 10 ROM map of 34514 8 8 9876543210 008016 External 0 interrupt address 008216 External 1 interrupt address 008416 008616 008816 008A16 008 16 008 16 Fig 11 Page 1 addresses 008016 to 00 16 structure 1 20 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS DATA MEMORY RAM 1 word of RAM is composed of 4 bits but 1 bit manipulation with the SB j RB j and SZB j instructions is enabled for the entire memory area A RAM address is specified by a data pointer The data pointer consists of registers Z X and Y Set a value to the data pointer certainly when executing an instruction to access RAM Table 2 shows the RAM size Figure 12 shows the RAM map Table 2 RAM size Product RAM size M34513M2 128 words X 4 bits 512 bits M34513M4 E4 1024 bits 256
109. and the RAM back up mode ini tialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back up state refer to Figure 21 4513 4514 Group User s Manual System reset WRST instruction executed WRST EPOF POF Oscillation stop WDF1 flag reset POF instruction enabled RAM back up state Fig 21 Program example to enter the RAM back up mode when using the watchdog timer 1 35 HARDWARE FUNCTION BLOCK OPERATIONS SERIAL I O Table 11 Serial I O pins The 4513 4514 Group has a built in clock synchronous serial I O Pin Pin function when selecting serial I O which can serially transmit or receive 8 bit data 20 5 Clock I O Sck Serial I O consists of P21 SoUT Serial data output SOUT serial I O register SI P22 SIN Serial data input SIN serial mode register J1 serial transmission reception completion flag SIOF serial counter Registers A and B are used to perform data transfer with internal CPU and the serial I O pins are used for external data transfer pin functions of the serial I O pins can be set with the register J1 Note Input ports 20 22 be used regardless of register J1 Division circuit divided by 2 Internal clock generation circuit Instruction clock divided by 3 Serial I O mode register J1 ircui Serial I O interrupt P20 Sck Q SCK S
110. as the timer 1 count start trigger function from P30 INTO pin input Timer 2 B Timer operation Timer 3 B Timer operation Timer 3 has the timer 3 count start trigger function from P31 INT1 pin input Timer 4 B Timer operation 16 bit timer B Timer 2 count source 16 bit fixed dividing frequency Watchdog function Watchdog timer provides a method to reset the system when a program runs incorrectly When the count value of timer WDT reaches BFFF16 or 3FFF16 the WDF1 flag is set to 1 If the WRST instruction is never executed while timer WDT counts 32767 WDF2 flag is set to 1 to reset the microcomputer 4513 4514 Group User s Manual APPLICATION 2 3 Timers 2 3 2 Related registers 1 Interrupt control register V1 The timer 1 interrupt enable bit is assigned to bit 2 and the timer 2 interrupt enable bit is assigned to bit 3 Set the contents of this register through register A with the TV1A instruction The TAV1 instruction can be used to transfer the contents of register V1 to register A Table 2 3 1 shows the interrupt control register V1 Table 2 3 1 Interrupt control register V1 at reset 00002 at RAM back up 00002 0 Interrupt disabled SNZT2 instruction is valid Interrupt enabled SNZT2 instruction is invalid Interrupt disabled SNZT1 instruction is valid Interrupt enabled SNZT1 instruction is invalid Interrupt disabled SNZ1 instruction is valid Interrupt enabled SNZ1 instruc
111. ble bit V22 A D interrupt enable bit V21 4 interrupt enable bit V20 3 interrupt enable bit Note R represents read enabled and W represents write enabled 4 Interrupt request flag The activated condition for each interrupt is examined Each interrupt request flag is set to 1 when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit Each interrupt request flag is cleared to 0 when either ean interrupt occurs or the next instruction is skipped with a skip instruction 2 14 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts 5 Interrupt control register 11 The INTO pin timer 1 control enable bit is assigned to bit 0 INTO pin edge detection circuit control bit is assigned to bit 1 and interrupt valid waveform for INTO pin return level selection bit is assigned to bit 2 Set the contents of this register through register A with the TI1A instruction In addition the instruction can be used to transfer the contents of register 11 to register A Table 2 2 3 shows the interrupt control register 11 Table 2 2 3 Interrupt control register 11 Interrupt control register 11 at reset 00002 at RAM back up state retained R W 113 Not used 2 This bit has no function but read write is enabled Falling waveform L level of INTO pin is re
112. but read write is enabled Not used This bit has no function but read write is enabled 9 9 9 Note R represents read enabled and W represents write enabled 4513 4514 Group User s Manual 1 57 HARDWARE FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD Clock signal f XIN is obtained by externally connecting a ceramic resonator UD 4513 4514 Note Externally connect a Connect this external circuit to pins XIN and Xour at the shortest damping resistor Rd de distance A feedback resistor is built in between pins XIN and XOUT XOUT pending on the oscillation When an external clock signal is input connect the clock source to frequency A feedback resistor is XIN and leave Xour open When using an external clock the maxi built in mum value of external clock oscillating frequency is shown in Table Use the resonator manu 24 facturer s recommended value because constants such as capacitance de pend on the resonator Fig 42 Ceramic resonator external circuit 4513 4514 External oscillation circuit Fig 43 External clock input circuit Table 24 Maximum value of external clock oscillation frequency Supply voltage Oscillation frequency duty ratio Middle speed mode DD 2 0 V to 55 V 3 0 2 40 to 60 DD 4 0 V to 5 5 V 3 0 MHZ 40 to 60 Mask ROM versi as version High speed mode DD 2 5 V to 5 5 V 1 0 40 10 60
113. circuit RESET pino e gt Internal reset signal cs Voltage drop detection circuit Watchdog timer output WEF Note The output structure of RESET pin is N channel open drain Fig 2 8 1 Voltage drop detection reset circuit VDD VRST detection voltage Voltage drop detection 1 circuit output The microcomputer starts operation after f XIN is counted 16892 to 16895 times RESET pin Notes 1 Pull up RESET pin externally 2 Refer to the voltage drop detection circuit in the electrical characteristics for the rating value of VRST detection voltage Fig 2 8 2 Voltage drop detection circuit operation waveform Note Refer to section 3 1 Electrical characteristics for the reset voltage of the voltage drop detection circuit 2 58 4513 4514 Group User s Manual APPLICATION 2 9 RAM back up 2 9 RAM back up 2 9 1 RAM back up mode The system enters RAM back up mode when the POF instruction is executed after the EPOF instruction is executed Table 2 9 1 shows the function and state retained at RAM back up mode Also Table 2 9 2 shows the return source from this state 1 RAM back up mode As oscillation stops with RAM the state of reset circuit retained current dissipation can be reduced without losing the contents of RAM Table 2 9 1 Functions and states retained at RAM back up mode Function RAM back up Function RAM back up Program cou
114. ck generating circuit ceramic resonator LED drive directly enabled port D APPLICATION Electrical household appliance consumer electronic products of fice automation equipment etc RAM size X 4 bits Package ROM type M34513M2 XXXSP FP 2048 words 128 words SP 32P4B FP 32P6B A Mask ROM M34513M4 XXXSP FP 4096 words 256 words SP 32P4B FP 32P6B A Mask ROM M34513E4SP FP Note 4096 words 256 words SP 32P4B FP 32P6B A One Time PROM M34513M6 XXXFP 6144 words 384 words 32P6B A Mask ROM M34513M8 XXXFP 8192 words 384 words 32P6B A Mask ROM M34513E8FP Note 8192 words 384 words 32P6B A One Time PROM M34514M6 XXXFP 6144 words 384 words 42P2R A Mask ROM M34514M8 XXXFP 8192 words 384 words 42P2R A Mask ROM M34514E8FP Note 8192 words Note shipped in blank 4513 4514 Group User s Manual 384 words 42P2R A One Time PROM 1 3 HARDWARE PIN CONFIGURATION PIN CONFIGURATION TOP VIEW 4513 Group Do D1 D2 D3 D4 D5 De CNTRO D7 CNTR1 AIN3 CMP1 1 P20 SCK P21 SOUT dSrAelSrew dSXXX XNELSVEN Ain1 CMP0 P31 INT1 22 RESET CNVss XOUT P30 INTO XIN Vss Outline 32P4B P02 1 05 3 POo 3 M34513Mx XXXFP De CNTRo AIN3 CMP1 AIN2 CMP1 P21 SouT P31 INT1 16 eid e 2
115. code Mnemonic Function Hexadecimal Number of words Number of cycles Ds D7 De Ds D4 D3 Di instructions notation a E7 E4 lt lt A B E7 E4 lt DR2 DRo lt 2 2 lt DR2 DRo A3 0 Register to register transfer A1 Ao lt Z1 20 A2 0 A lt X 2 lt SP2 SPo 0 X x x 20to 15 Y lt y 20to 15 2 z z 0to3 o o o D o lt RAM to register transfer Xx RIRS lt u 1 70 4513 4514 Group User s Manual HARDWARE MACHINE INSTRUCTIONS Skip condition Datailed description Transfers the contents of register B to register A Transfers the contents of register A to register B Transfers the contents of register Y to register A Transfers the contents of register A to register Y Transfers the contents of registers A and B to register E Transfers the contents of register E to registers A and B Transfers the contents of register A to register D Transfers the contents of register D to register A Transfers the contents of register Z to register A Transfers the contents of register X to register A Transfers the contents of stack pointer SP to register A Continuous Loads the value x in the immediate field to register X and the value y in the immediate field to
116. cognized with the SNZIO instruction L level Rising waveform H level of INTO pin is recognized Interrupt valid waveform for INTO 0 112 pin return level selection bit DIO with the SNZIO instruction H level 114 INTO pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected 110 0 Disabled timer 1 control enable bit 1 Enabled Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 112 is changed the external interrupt request flag EXFO may be set Accordingly clear EXFO flag with the SNZO instruction 6 Interrupt control register 12 The INT1 pin timer 3 control enable bit is assigned to bit 0 the INT1 pin edge detection circuit control bit is assigned to bit 1 and the interrupt valid waveform for INT1 pin return level selection bit is assigned to bit 2 Set the contents of this register through register A with the TI2A instruction In addition the TAI2 instruction can be used to transfer the contents of register 2 to register A Table 2 2 4 shows the interrupt control register 12 Table 2 2 4 Interrupt control register 12 at reset 00002 at RAM back up state retained This bit has no function but read write is enabled R W Interrupt control register 12 123 Not used Falling waveform L level of INT1 pin is recognized with the SNZI1 instruction L level Rising wave
117. contents of the high order 2 bits of register A to the high order 2 bits of voltage comparator control register Q3 and the comparison result of the voltage comparator is transferred to the low order 2 bits of the register Q3 4513 4514 Group User s Manual 1 83 HARDWARE CONTROL REGISTERS CONTROL REGISTERS Interrupt control register V1 at reset 00002 at RAM back up 00002 Interrupt disabled SNZT2 instruction is valid Timer 2 interrupt enable bit Interrupt enabled SNZT2 instruction is invalid Interrupt disabled SNZT1 instruction is valid Timer 1 interrupt enable bit Interrupt enabled SNZT1 instruction is invalid Interrupt disabled SNZ1 instruction is valid External 1 interrupt enable bit Interrupt enabled SNZ1 instruction is invalid Interrupt disabled SNZO instruction is valid External 0 interrupt enable bit Interrupt control register V2 Interrupt enabled SNZO instruction is invalid reset 00002 at RAM back up 00002 Interrupt disabled SNZSI instruction is valid Serial I O interrupt enable bit Interrupt enabled SNZSI instruction is invalid Interrupt disabled SNZAD instruction is valid A D interrupt enable bit Interrupt enabled SNZAD instruction is invalid Interrupt disabled SNZTA instruction is valid Timer 4 interrupt enable bit Interrupt enabled SNZT4 instruction is invalid
118. ctions as analog input is undefined Notes on port P3 In the 4513 Group when the IAP3 instruction is executed the contents of high order 2 bits of register A are undefined 4513 4514 Group User s Manual 2 9 APPLICATION 2 1 I O pins Table 2 1 6 connections of unused pins Pin Connection XOUT Open when using an external clock VDCE Connect to Vss 00 05 Connect to 55 set the output latch to 0 and open De CNTRO D7 CNTR1 P20 SCK Connect to Vss P21 SOUT 22 5 P30 INTO Connect to 55 or set the output latch to 0 and open P31 INT1 P32 P33 P40 AIN4 P43 AIN7 P50 P53 Note 1 Connect to 55 or set the output latch to 0 and open When the input mode is selected by software pull up to VDD through a resistor or pull down to 55 When selecting the output mode open Connect to 55 AIN1 CMP0 AIN2 CMP1 AIN3 CMP1 P0o P03 Open or connect to Vss Note 2 10 13 Open or connect to 55 Note 2 Notes 1 After system is released from reset port P5 is in an input mode direction register FRO 00002 2 When the 00 P10 P13 are connected to Vss turn off their pull up transistors register 0 0 and also invalidate the key on wakeup functions register 0 0 by software When these pins are connected to Vss while the key on wakeup functions are left valid the system
119. current IDD mA 4 5 3 5 4 Supply voltage VDD V 2 CPU operating high speed mode 2 5 Supply current IDD mA 2 2 5 3 4 5 3 5 4 Supply voltage VDD V 3 8 4513 4514 Group User s Manual Ta 25 4 MHz f XIN 1 MHz 5 5 25 f XIN 4 MHz 1 MHz 5 5 3 Supply current IDD mA 4 Supply current IDD mA APPENDIX 3 2 Typical characteristics A D operating middle speed mode 2s Ta 25 2 4 23 2 2 24 2 1 9 i8 XIN 4 MHz 17 1 6 1 5 1 4 13 XIN 1 MHz 1 2 14 1 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 3 5 4 45 5 Supply voltage VDD V A D operating high speed mode a e a Ta 25 C 25 f XIN 4 MHz 2 3 2 2 21 2 1 9 1 8 1 7 1 6 1 5 1 MHz 1 3 12 14 1 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Supply voltage VDD V a a ES gt a a 4513 4514 Group User s Manual 3 9 APPENDIX 3 2 Typical characteristics 5 RAM back up Supply current IDD nA Ta 25 Supply voltage VDD V 4513 4514 Group User s Manual APPENDIX 3 2 Typical characteristics 3 2 2 VoL loL characteristics 1 Ports PO P1 P5 Sck Ta 25 100 90 VDD 6V 80 VDD 5V 70 60 4 ded 50 3 40 VDD 3V 5 2 30 5 20 2 10 4
120. current in the RAM back up mode invalidate bits 2 and 3 of register Q3 0 the voltage comparator function by software before the POF instruction is executed Also while the voltage comparator function is valid current is al ways consumed by voltage comparator On the system required for the low power dissipation invalidate the voltage comparator by software when it is unused Register Q3 Bits 0 and 1 of register Q3 can be only read Note that they can not be written Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time max 20 us is passed from the voltage comparator function becomes valid 1 48 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS RESET FUNCTION System reset is performed by applying L level to RESET pin for 1 machine cycle or more when the following condition is satisfied the value of supply voltage is the minimum value or more of the recommended operating conditions Then when level is applied to RESET pin software starts from address 0 in page 0 is counted 16892 to gt Software starts TOROS umes address 0 page 0 Note It depends on the internal state of the microcomputer when reset is performed Fig 32 Reset release timing Reset input f XiN is counted 16892 to 1 machine cycle or more 16895 times 0 85VDD
121. d for the 4513 Group o j o j2 jo 2 o Comparator control register Q3 Note 3 reset 00002 at RAM back up state retained Voltage comparator CMP1 invalid Voltage comparator 1 valid Voltage comparator invalid Voltage comparator valid CMP1 gt CMP1 CMP1 lt CMP1 gt lt Q33 Voltage comparator 1 control bit 1 1 Q32 Voltage comparator control bit Q31 CMP1 comparison result store bit 9 9 9 Q30 comparison reslut store bit Clock control register MR reset 10002 at RAM back up 10002 f XIN high speed mode System clock selection bit f XIN 2 middle speed mode Not used This bit has no function but read write is enabled Not used This bit has no function but read write is enabled Not used This bit has no function but read write is enabled 9 9 9 Notes 1 represents read enabled W represents write enabled 2 Select AINA AIN7 with register Q1 after setting register Q2 3 Bits 0 and 1 of register Q3 can be only read 1 86 4513 4514 Group User s Manual Key on wakeup control register KO at reset 00002 HARDWARE CONTROL REGISTERS at RAM back up state retained Pins P12 and P13 key on wakeup control bit Key on wakeup not used Key on wakeup used Pin
122. d with a key on wakeup function Timer 1 8 bit programmable timer with a reload register Timer 2 8 bit programmable timer with a reload register is also used as an event counter Timer 3 8 bit programmable timer with a reload register Timer 4 8 bit programmable timer with a reload register is also used as an event counter A D converter 10 bit wide This is equipped with an 8 bit comparator function Voltage comparator 2 circuits CMP1 Serial 8 bit X 1 Interrupt Sources 8 two for external four for timer one for A D and one for serial I O Nesting 1 level Subroutine nesting 8 levels Device structu Package re 4513 Group 4514 Group Operating temperature range CMOS silicon gate 32 pin plastic molded SDIP 32P4B LQFP 32P6B A 42 pin plastic molded SSOP 42P2R A 20 to 85 C Supply voltage 2 0 V to 5 5 V for Mask ROM version 2 5 V to 5 5 V for One Time PROM version Refer to the electrical characteristics because the supply voltage depends on the oscillation frequency Power dissipation typical value 1 8 Active mode 1 8 mA at VDD 5 0 V 4 0 MHz oscillation frequency in middle speed mode output transis tors in the cut off state 3 0 mA at VDD 5 0 V 4 0 MHz oscillation frequency in high speed mode output transistors in the cut off state RAM back up mode 0 1 u
123. ddress PCH PCL p pr po DR amp DRIDRO Az Ao X d UN A Low order 4bits Register A 4 T 1 Immediate field value p register D Fig 4 TABP p instruction execution example 4513 4514 Group User s Manual d Middle order 4 bits Register B 4 The contents of The contents of register A HARDWARE FUNCTION BLOCK OPERATIONS 5 Stack registers SKs and stack pointer SP Stack registers SKs are used to temporarily store the contents of program counter PC just before branching until returning to the original routine when branching to an interrupt service routine referred to as inter rupt service routine performing a subroutine call or executing the table reference instruction TABP p Stack registers SKs are eight identical registers so that subrou tines can be nested up to 8 levels However one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction Accordingly be care ful not to over the stack when performing these operations together The contents of registers SKs are destroyed when 8 lev els are exceeded The register SK nesting level is pointed automatically by 3 bit stack pointer SP The contents of the stack pointer SP can be transferred to register A with the TASP instruction Figure 5 shows the stack registers SKs structure Figure 6 sh
124. e TSIAB instruction The contents of register A is transmit ted to the low order 4 bits of register SI and the contents of register B is transmitted to the high order 4 bits of register SI During transmission each bit data is transmitted LSB first from the lowermost bit bit 0 of register SI and during reception each bit data is received LSB first to register SI starting from the topmost bit bit 7 When register SI is used as a work register without using serial I O pull up the SCK pin or set the pin function to an input port P20 2 Serial transmission reception completion flag SIOF Serial I O transmission reception completion flag SIOF is set to 1 when serial data transmission or reception completes The state of SIOF flag can be examined with the skip instruction SNZSI Use the interrupt control register V2 to select the inter rupt or the skip instruction The SIOF flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction 4513 4514 Group User s Manual Do Transfer data to be set Transfer started Transfer completed 7 06 05 D4 Ds D2 D1 3 Serial I O start instruction SST When the SST instruction is executed the SIOF flag is cleared to 0 and then serial I O transmission reception is started 4 Serial mode register J1 Register J1 controls the synchronous clock 20 5 P21 SOUT and P22 SIN pin functio
125. e contents of this register through register A with the instruction The instruction can be used to trans fer the contents of register W4 to register A Timer control register W6 Register W6 controls the De CNTRO pin and D7 CNTR1 func tions the selection and operation of the CNTRO and 1 output Set the contents of this register through register A with the TW6A instruction The TAW6 instruction can be used to trans fer the contents of register W6 to register A 2 Precautions Note the following for the use of timers Prescaler Stop the prescaler operation to change its frequency dividing ra tio Count source Stop timer 1 2 3 or 4 counting to change its count source Reading the count value Stop timer 1 2 3 or 4 counting and then execute the 1 TAB2 or 4 instruction to read its data Writing to reload registers R1 and R3 When writing data to reload registers R1 or while timer 1 or timer 3 is operating avoid a timing when timer 1 or timer 3 underflows 3 Prescaler Prescaler is a frequency divider Its frequency dividing ratio can be selected The count source of prescaler is the instruction clock Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation Prescaler is initialized and the output signal ORCLK stops when the bit 3 of register W1 is cleared to 0 4513 4514 Group User s Manual HARDWARE F
126. e length of wiring which is connected to clock pins as short as possible Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the Vss pin of a microcomputer as short as possible Separate the Vss pattern only for oscillation from other 55 patterns Fig 3 4 3 Wiring for clock I O pins Reason If noise enters clock pins clock waveforms may be deformed This may cause a program failure or program runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the 55 level of oscillator the correct clock will not be input in the microcomputer 4 Wiring to CNVss pin Connect the CNVss pin to the Vss pin with the shortest possible wiring Reason The operation mode of a microcomputer is influenced by a potential at the CNVSs pin If a potential difference is caused by the noise between pins CNVss and Vss the operation mode may become unstable This may cause a microcomputer malfunction or a program runaway Fig 3 4 4 Wiring for CNVss pin 4513 4514 Group User s Manual 3 25 APPENDIX 3 4 Notes on noise 5 Wiring to pin of One Time PROM version In the built in PROM version of the 4513 4514 Group the CNVss is also used as the built in PROM power supply input pin VPP When the is also used as the CNVss pin Connect an approximately 5 kQ resistor to the VP
127. e ree ex reete ER rex esr tod e e 2 7 2 1 2 Key scan input timing enne enne nnne nnne nns 2 8 2 2 1 INTO interrupt operation example 2422 0 2 17 22 2 INTO interrupt setting examwple act ted kt once eeu t oett tuae ex tg 2 18 2 2 3 INT1 interrupt operation example 2 2 19 2 2 4 INT1 interrupt setting 2224 a nennen nnn 2 20 2 2 5 Timer 1 constant period interrupt setting 2 21 2 2 6 Timer 2 constant period interrupt setting 2 22 2 2 7 Timer constant period interrupt setting 2 23 2 2 8 Timer 4 constant period interrupt setting 2 24 2 39 1 Peripheral circuit example sich He RR LAND IE ER Lus REINO 2 30 2 9 2 Watchdog fUngcllODus ee rt eade duca utet neut Lue v vue du Eun 2 31 2 3 3 Constant period measurement setting 2 32 2 3 4 CNTRO output setting example 2 33 2 3 5 CNTR1 input setting example sisisi tendai anann nnne 2 34 2 3 6 CNTRO output control setting example 2 35 2 3 7 Timer start by external input setting example 1 2 36 2 3 8 Timer start by externa
128. ected b3 bo Prescaler stop TW1A instruction Timer control register W1 el x Prescaler dived by 16 selected b3 bo x Timer 3 stop TW3A instruction Timer control register W3 ofx o 1 prescaler selected for count source Timer 4 stop instruction Timer control register Wa Timer 3 underflow signal selected for count source Set Timer Value Timer 3 and timer 4 count times set The formula is shown below Timer reload register 5216 Timer count value 82 set T3AB instruction Timer 4 reload register R4 F916 Timer count value 249 set T4AB instruction Clear Interrupt Request Timer 4 interrupt activated condition is cleared Timer 4 interrupt request flag 0 Timer 4 interrupt activated condition cleared SNZTA instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag insert the instruction after the SNZTA instruction Start Timer 4 Operation Timer 4 timer 3 and prescaler temporarily stopped are restarted b3 b0 Timer control register W4 1 x 0 Timer 4 operation start TW4A instruction b3 bo Timer control register W3 1 x 0 1 Timer 3 operation start TW3A instruction b3 bo Timer control register W1 Prescaler operation start TW1A instruction Enable Interrupts The timer 4 interrupt which is tem
129. ecuted the contents of register A are transferred to the low order 4 bits of register SI and the contents of register B are transferred to the high order 4 bits of register 51 Whether the microcomputer on the receiving side is ready to receive or not is checked In the connection example in Figure 2 4 2 check that the input level of control signal is L level Serial transfer is started with the SST instruction When the SST instruction is executed the serial transmit receive completion flag SIOF is cleared to 0 The transmit data is output from the SOUT pin synchronously with the falling edges of the shift clock The transmit data is output bit by bit beginning with the LSB bit of register SI Each time one bit is output the contents of register SI is shifted one bit position toward the LSB Also the receive data is input from the SIN pin synchronously with the rising edges of the shift clock The receive data is input bit by bit to the MSB bit of register 51 A serial I O interrupt request occurs when the transfer of transmit data and receive data is completed and the SIOF flag is set to 1 The receive data is taken in within the serial I O interrupt service routine or the data is taken in after examining the completion of the transmit receive operation with the SNZSI instruction without using an interrupt Also the SIOF flag is cleared to 0 when an interrupt occurs or the SNZSI instruction i
130. ed Set Serial I O b3 J Internal clock selected TJ1A instruction Serial I O mode register J1 x 1 1 1 Serial port selected Dividing ratio 4 selected Clear Interrupt Request Serial I O interrupt activated condition is cleared Serial I O transmit receive 0 Serial I O interrupt activated condition cleared completion flag SIOF SNZSI instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the SIOF flag insert the NOP instruction after the SNZSI instruction When interrupt is not used amp Set Interrupt Set Interrupt Interrupts except serial I O is enabled Serial I O interrupt temporarily disabled is enabled El instruction Serial I O interrupt occurrence Interrupt control register V2 1 TV2A Interrupt enable flag INTE 1 All interrupts enabled El instruction y When interrupt is used Start Condition of Serial I O operation Slave side is enabled to receive is checked Pin level of control signal L Start Serial I O Operation Serial transfer is started SST instruction after checking slave side is enabled to receive Check Serial I O Interrupt Request Serial I O Interrupt Occur SIOF flag is checked SNZSI instruction Execute Receive Data Data received by serial transfer is executed Register SI register A register B TABSI instruction When seria
131. ed A Standard Mitsubishi Mark amp Mitsubishi catalog esee Mitsubishi IC catalog name Mitsubishi lot number 6 digit or 7 digit 0 Customer s Parts Number Mitsubishi catalog name Hoge 2 Customer s Parts Number Note The fonts and size of characters are standard Mitsubishi type EN 77 Mitsubishi IC catalog name Mitsubishi lot number Note1 The mark field should be written right aligned 6 digit or 7 digit 2 The fonts and size of characters are standard Mitsubishi type 3 Customer s Parts Number can be up to 11 characters Only 0 D 9 2 periods commas are usable 4 If the
132. ed and W represents write enabled 4513 4514 Group User s Manual 2 29 APPLICATION 2 3 Timers 2 3 3 Timer application examples 1 2 Timer operation measurement of constant period The constant period by the setting timer count value can be measured Outline The constant period by the timer 1 underflow signal can be measured Specifications Timer 1 and prescaler divides the system clock frequency f XIN 4 0 MHz and the timer 1 interrupt request occurs every 3 ms Figure 2 3 3 shows the setting example of the constant period measurement CNTRO output operation piezoelectric buzzer output Outline Square wave output from timer 1 can be used for piezoelectric buzzer output Specifications 4 kHz square wave is output from the CNTRO pin at system clock frequency f XIN 4 0 MHz Also timer 1 interrupt occurs simultaneously Figure 2 3 1 shows the peripheral circuit example and Figure 2 3 4 shows the setting example of CNTRO output In order to reduce the current dissipation output is high impedance state during buzzer licores stop TAM ULL CNTRO 125 us Set ratio for timer 1 underflow cycle to 125 us Fig 2 3 1 Peripheral circuit example 3 2 30 CNTRO input operation event count Outline Count operation can be performed by using the signal rising waveform input from CNTRO pin as the event Specifications The low frequency pulse from external as the timer 2 count so
133. egister 11 Pull up transistor OFF Pull up transistor ON reset 00002 at RAM back up state retained Not used This bit has no function but read write is enabled Interrupt valid waveform for INTO pin return level selection bit Note 2 Falling waveform L level of INTO pin is recognized with the SNZIO instruction L level Rising waveform H level of INTO pin is recognized with the SNZIO instruction H level INTO pin edge detection circuit control bit One sided edge detected Both edges detected INTO pin timer 1 control enable bit Interrupt control register 12 Not used Interrupt valid waveform for INT1 pin return level selection bit Note 3 reset 00002 Disabled at RAM back up state retained R W Enabled This bit has no function but read write is enabled Falling waveform 47 level of INT1 pin is recognized with the SNZI1 instruction L level Rising waveform H level of INT1 pin is recognized with the SNZI1 instruction H level INT1 pin edge detection circuit control bit One sided edge detected Both edges detected INT1 pin timer 3 control enable bit Disabled Enabled Notes 1 represents read enabled and W represents write enabled 2 When the contents of 112 is changed the external interrupt request flag EXFO may be set Accordingly clear EXFO flag with the SNZO instruction 3 Whe
134. egister AD stores the A D conversion result of an analog input in 10 bit digital data format The contents of the high order 8 bits of this register can be stored in register B and register A with the TABAD instruction The contents of the low order 2 bits of this reg ister can be stored into the high order 2 bits of register A with the TALA instruction However do not execute this instruction during A D conversion When the contents of register AD is n the logic value of the com parison voltage Vret generated from the built in DA converter can be obtained with the reference voltage VDD by the following for mula Logic value of comparison voltage Vref Vref xn 1024 n The value of register AD n 0 to 1023 3 A D conversion completion flag ADF A D conversion completion flag ADF is set to 1 when A D con version completes The state of ADF flag can be examined with the skip instruction SNZAD Use the interrupt control register V2 to select the interrupt or the skip instruction The ADF flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction 1 42 P41 read write enabled for the 4513 Group AIN4 P40 read write enabled for the 4513 Group 4 A D conversion start instruction ADST A D conversion starts when the ADST instruction is executed The conversion result is automatically stored in the register AD 5 A D control regis
135. en the bit 2 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the timer 1 interrupt occurs the interrupt processing is executed from address 4 in page 1 When the interrupt is not used The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set to 0 4513 4514 Group User s Manual 2 11 APPLICATION 2 2 Interrupts 4 Timer 2 interrupt The interrupt request occurs by the timer 2 underflow Timer 2 interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the timer 2 interrupt occurs the interrupt processing is executed from address 6 in page 1 When the interrupt is not used The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set to 0 5 Timer 3 interrupt The interrupt request occurs by the timer 3 underflow B Timer 3 interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the interrupt enable flag INTE are set to 41 When the timer 3 interrupt occurs the interrupt processing is executed from address 8 in page 1 When the interrupt is not used The interrupt is disabled and the SNZTS3 instruction is valid when the bit 0 of register V2 is set to 0
136. entified example using the SNZP 1 55 Fig 41 Clock control circ lt Str CtUre 1 57 4513 4514 Group User s Manual List of figures Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 42 Ceramic resonator external eene eene 1 58 43 External clock input 1 58 44 External 0 interrupt program sssini 1 59 45 External 1 interrupt program example 1 59 46 A D converter operating mode program 1 60 47 Analog input external circuit 1 1 60 48 Analog input external circuit 2 1 60 49 Pin configuration of built in PROM version of 4513 1 88 50 Pin configuration of built in PROM version of 4514 1 88 51 PROM memory map et hence itc tet itin eda su aaa 1 89 52 Flow of writing and test of the product shipped in 1 89 CHAPTER 2 APPLICATION Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 2 21 11 KEY input DY KOy SCAM eee n tete rea
137. er 4 2 29 Table 2 4 1 Serial mode register 444040000 0 0 2 41 Table 2 4 2 Recommended operating conditions serial 1 2 48 4513 4514 Group User s Manual vii List of tables viii Table 2 5 1 A D control register 0 00 0000 enne trennen nnne 2 50 Table 2 5 2 A D control register 2 22 4 entren nnne 2 50 Table 2 5 3 Recommended operating conditions when using A D converter 2 53 Table 2 6 1 Voltage comparator control register 2 54 Table 2 9 1 Functions and states retained at RAM back up mode 2 59 Table 2 9 2 Return source and return 2 60 Table 2 9 3 Start condition 2 60 Table 2 9 4 Key on wakeup control register 2 60 Table 2 9 5 Pull up control register PUO EE Let tir ee c erc ee dos 2 61 Table 2 9 6 Interrupt control register 1 2 1 2 61 Table 2 9 7 Interrupt control register I2 eene enne 2 62 Table 2 10 1 Maximum value of oscillation frequency and supply voltage 2 63 CHAPTER 3 APPENDIX Table 3 1 1 Absolute maximum 3 2 Table 3 1 2 Recommended operating conditions 1 3 3 Table 3 1 3 Recommended
138. er Each function is described below Table 9 Function related timers Circuit Structure Count source Frequency dividing ratio Use of output signal Control register Prescaler Frequency divider Instruction clock 4 16 Timer 1 2 3 and 4 count sources W1 Timer 1 8 bit programmable binary down counter 8 bit programmable binary down counter link to P30 INTO input Prescaler output ORCLK Timer 1 underflow Prescaler output ORCLK CNTRO input 16 bit timer underflow 1 to 256 1 to 256 Timer 2 count source CNTRO output Timer 1 interrupt Timer 3 count source Timer 2 interrupt CNTRO output W1 W6 8 bit programmable binary down counter 8 bit programmable binary down counter link to P31 INT1 input Timer 2 underflow Prescaler output ORCLK Timer 3 underflow Prescaler output ORCLK e CNTR1 input 1 to 256 1 to 256 Timer 4 count source Timer 3 interrupt e CNTR1 output Timer 4 interrupt CNTR1 output 16 bit timer 16 bit fixed dividing frequency 1 30 Instruction clock Watchdog timer The 15th bit is counted twice Timer 2 count source 16 bit timer underflow 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS Internal clock generating circuit Timer 1 interrupt 2 interrupt
139. er ex change and I O operation Carry flag CY is a 1 bit flag that is set to 1 when there is a carry with the AMC instruction Figure 1 It is unchanged with both instruction and AM instruction The value of Ao is stored in carry flag CY with the RAR instruction Fig ure 2 Carry flag CY can be set to 1 with the SC instruction and cleared to 0 with the RC instruction 3 Registers B and E Register B is a 4 bit register used for temporary storage of 4 bit data and for 8 bit data transfer together with register A Register E is an 8 bit register It can be used for 8 bit data transfer with register B used as the high order 4 bits and register A as the low order 4 bits Figure 3 4 Register D Register D is a 3 bit register It is used to store a 7 bit ROM address together with register A and is used as a pointer within the specified page when the TABP p BLA p or BMLA p instruction is executed Figure 4 TABP p instruction HARDWARE FUNCTION BLOCK OPERATIONS lt Carry gt lt Result gt Fig 1 instruction execution example lt Clear gt RC instruction lt Set gt SC instruction lt Rotation gt 4 RAR instruction Fig 2 RAR instruction execution example Register B TAB instruction Register TEAB instruction Register E TABE instruction 8s Be B Bo Register B instruction Register Fig 3 Registers A B and register E Specifying a
140. er V1 Transfers the contents of interrupt control register V2 to register A Transfers the contents of register A to interrupt control register V2 Transfers the contents of interrupt control register 11 to register A Transfers the contents of register A to interrupt control register 11 Transfers the contents of interrupt control register I2 to register A Transfers the contents of register A to interrupt control register 12 Transfers the contents of timer control register W1 to register A Transfers the contents of register A to timer control register W1 Transfers the contents of timer control register W2 to register A Transfers the contents of register A to timer control register W2 Transfers the contents of timer control register W3 to register A Transfers the contents of register A to timer control register W3 Transfers the contents of timer control register W4 to register A Transfers the contents of register to timer control register W4 Transfers the contents of timer control register W6 to register A Transfers the contents of register A to timer control register W6 4513 4514 Group User s Manual 1 77 HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS continued Parameter Instruction code Mnemonic Function Hexadecimal Number of words Number of cycles Ds D7 De Ds D4 D3 D2 Di instructions notation 270 lt T17 T14 lt T13 T10 R17 R14 lt
141. erial counter 3 P21 SoUTO Sour P22 SiIn 58 MSB Serial I O register SI 8 LSB Note The output structure of Sck and Sour pins is N channel open drain Fig 22 Serial I O structure Table 12 Serial I O mode register Serial I O mode register J1 at reset 00002 at RAM back up state retained Not used This bit has no function but read write is enabled Serial internal clock dividing ratio selection bit Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P20 P21 P22 selected Serial ports Sck Sour SiN input ports 20 P21 P22 selected External clock Internal clock instruction clock divided by 4 or 8 Serial port selection bit Serial I O synchronous clock selection bit o 2 jo 2 o o Note R represents read enabled and W represents write enabled 1 36 4513 4514 Group User s Manual When transmitting D7 Do transfer data SIN pin os SOUT pin Serial I O register 51 HARDWARE FUNCTION BLOCK OPERATIONS When receiving Serial register 51 07 De Ds D4 Ds 02 D1 Do Fig 23 Serial I O register state when transferring 1 Serial I O register SI Serial I O register SI is the 8 bit data transfer serial parallel conver sion register Data can be set to register SI through registers A and B with th
142. erived by dividing the system clock by 3 The one instruction clock cycle generates the one machine cycle Machine cycle The machine cycle is the standard cycle required to execute the instruction 4513 4514 Group User s Manual HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS Key on wakeup input IAPO instruction Pull up transistor Register 4 Ai D OPOA instruction T Key on wakeup input IAPO instruction 1 00 01 A Pull up transistor Pos i i D OPOA instruction T K02 Key on wakeup input lt IAP1 instruction 1 P02 P03 4 ER Pull up transistor O Register 41 OP1A instruction 4T Q Key on wakeup input lt IAP1 instruction Pull up ranei or 2 i Register A Ai D instruction T Q 1 O P12 P13 777 4 This symbol represents a parasitic diode on the port i represents 0 1 2 or 3 1 12 4513 4514 Group User s Manual HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS continued IAP2 instruction lt Synchronous clock input for serial transfer 4 6 T t P20 Sck Synchronous clock output for serial transfer Jio ae atk IAP2 instruction 4 P21 SOUT ES Serial data input lt Q IAP2 instruction 4 1 0 P22 SIN
143. external clock Table 2 4 2 Recommended operating conditions serial 1 0 Typ Parameter Condition 4 0 V to 5 5 V Middle speed mode 2 5 V to 5 5 V Serial I O external clock period 2 0 V to 5 5 V Note 2 Note 1 4 0 V to 5 5 V ns High speed mode 2 5 V to 5 5 V 2 0 V to 5 5 V Note 2 Notes 1 Limits shown in Table 2 4 2 represent the pulse widths of H and L 2 It is effective only for mask version us External clock input waveform E di 4 p lt L pulse width pulse width Note Set H and L pulse width for external waveform according to using supply voltage and recommended operating conditions Fig 2 4 7 Input waveform of external clock 2 48 4513 4514 Group User s Manual APPLICATION 2 5 A D converter 2 5 A D converter The 4513 4514 Group has an A D converter with the 10 bit successive comparison method 4 channels for the 4513 Group 8 channels for the 4514 Group This A D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values This section describes the related registers application examples using the A D converter and notes Figure 2 5 1 shows the A D converter block diagram Register B 4 Register A 4 TAQ2 TAQI 2 P40 P43 922 021 020 Q11 ar 2 3 Note 3 Aino CMP0 O
144. fails to return from RAM back up state When these pins are open turn on their pull up transistors register PUOi 1 by software set the output latch to 0 Be sure to select the key on wakeup functions and the pull up functions with every two pins If only one of the two pins for the key on wakeup function is used turn on their pull up transistors by software and also disconnect the other pin i 0 1 2 or 3 Note in order to set the output latch to 0 and make pins open After system is released from reset a port is a high impedance state until the output latch of the port is set to 0 by software Accordingly the voltage level of pins is undefined and the excess of the supply current may occur To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away caused by noise Note in order to connect unused pins to Vss or VDD To avoid noise connect the unused pins to VsS or VDD at the shortest distance using a thick wire 2 10 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts 2 2 Interrupts The 4513 4514 Group has eight interrupt sources external INTO INT1 timer 1 timer 2 timer 3 timer 4 A D serial 1 This section describes individual types of interrupts related registers application examples using interrupts and notes 2 2 1 Interrupt functions 1 External 0 interrupt INTO The interr
145. fers the contents of registers A and B to timer 1 reload register Transfers the contents of registers A and B to timer 3 reload register Skips the next instruction when the contents of T1F flag is 1 After skipping clears 0 to T1F flag Skips the next instruction when the contents of T2F flag is 1 After skipping clears 0 to T2F flag Skips the next instruction when the contents of T3F flag is 1 After skipping clears 0 to T3F flag Skips the next instruction when the contents of T4F flag is 1 After skipping clears 0 to T4F flag 4513 4514 Group User s Manual 1 79 HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS continued Parameter Mnemonic instructions Instruction code Ds D7 De 05 D4 D3 D2 Di Hexadecimal notation Number of words Number of cycles Function c am 2 2 5 TAKO TPUOA TAPUO TFROA The 4513 Group does not have these instructions 1 80 260 2 a 4513 4514 Group User s Manual A lt PO lt lt 1 1 lt 2 lt 22 20 0 lt lt lt 4 P4 lt A lt 5 Skip condition HARDWARE MACHINE INSTRUCTIONS Datailed description Transfers the input of po
146. form H level of INT1 pin is recognized with the SNZI1 instruction H level Interrupt valid waveform for INT1 122 pin return level selection bit Note 2 i pin edge detection circuit 0 One sided edge detected control bit 1 Both edges detected INT1 pin Disabled 120 timer 3 control enable bit Enabled Notes 1 R represents read enabled and W represents write enabled 2 When the contents of 122 is changed the external interrupt request flag EXF1 may be set Accordingly clear EXF1 flag with the SNZ1 instruction 4513 4514 Group User s Manual 2 15 APPLICATION 2 2 Interrupts 2 2 3 Interrupt application examples 1 2 3 4 5 External 0 interrupt The INTO is used for external 0 interrupt of which valid waveforms can be chosen which can recognize the change of both edges or L H Outline An external 0 interrupt be used by dealing with the change of edge H L or L H in both directions as a trigger Specifications An interrupt occurs by the change of an external signals edge H 5 L or L H Figure 2 2 1 shows an operation example of an external 0 interrupt and Figure 2 2 2 shows a setting example of an external 0 interrupt External 1 interrupt The INT1 pin is used for external 1 interrupt of which valid waveforms can be chosen which can recognize the change of both edges H gt
147. ge comparator control register Q3 4 bits Successive comparison register AD 10 bits Serial I O mode register J1 4 bits Serial I O register SI 8 bits Interrupt control register V1 4 bits Interrupt control register V2 4 bits Interrupt control register 1 4 bits Interrupt control register I2 4 bits Timer control register W1 4 bits Timer control register W2 4 bits Timer control register W3 4 bits Timer control register W4 4 bits Timer control register W6 4 bits Clock control register MR 4 bits Key on wakeup control register KO 4 bits Pull up control register PUO 4 bits Direction register FRO 4 bits Register X 4 bits Register Y 4 bits Register Z 2 bits Data pointer 10 bits It consists of registers X Y and Z j Program counter 14 bits A3A2A1A0 High order 7 bits of program counter Low order 7 bits of program counter Stack register 14 bits X 8 Stack pointer 3 bits Carry flag Timer 1 reload register Timer 2 reload register Timer 3 reload register Timer 4 reload register Timer 1 Timer 2 Timer 3 Timer 4 Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A D conversion completion flag Serial I O transmission reception completion flag
148. ge its count source Reading the count value Stop timer 1 2 3 or 4 counting and then execute the 1 TAB2 or TABA instruction to read its data G Writing to reload registers R1 and R3 When writing data to reload registers R1 or while timer 1 or timer 3 is operating avoid a timing when timer 1 or timer 3 underflows GP30 INTO When the interrupt valid waveform of the P30 INTO pin is changed with the bit 2 of register 11 in software be careful about the following notes Clear the bit 0 of register V1 to 0 before the interrupt valid wave form of P30 INTO pin is changed with the bit 2 of register 11 refer to Figure 440 Depending on the input state of the P30 INTO pin the external 0 interrupt request flag EXFO may be set when the interrupt valid waveform is changed Accordingly clear bit 2 of register 11 and execute the SNZO instruction to clear the EXFO flag after execut ing at least one instruction refer to Figure 442 LA 4 TV1A 02 The SNZO instruction is valid LA i Interrupt valid waveform is changed THA NOP SNZO NOP The SNZO instruction is executed X this bit is not related to the setting of INTO pin Fig 44 External 0 interrupt program example IP31 INT1 pin When the interrupt valid waveform of P31 INT1 pin is changed with the bit 2 of register 12 in software be careful about the fol lowing notes Clear t
149. he bit 1 of register V1 to 0 before the interrupt valid wave form of P31 INT1 pin is changed with the bit 2 of register I2 refer to Figure 45G Depending on the input state of the P31 INT1 pin the external 1 interrupt request flag EXF1 may be set when the interrupt valid waveform is changed Accordingly clear bit 2 of register 12 and execute the SNZ1 instruction to clear the EXF1 flag after execut ing at least one instruction refer to Figure 459 XX0X2 The SNZ1 instruction is valid Change of the interrupt valid waveform The SNZ1 instruction is executed X this bit is not related to the setting of INT1 Fig 45 External 1 interrupt program example One Time PROM version The operating power voltage of the One Time PROM version is 2 5V to 5 5 V Multifunction The input of De D7 P20 P22 I O of P30 and P31 input of CMPO CMP1 1 and I O of P40 P43 can be used even when CNTRO CNTR1 Sck Sour SIN INTO INT1 AINO AIN3 AIN4 AIN7 are selected 4513 4514 Group User s Manual 3 21 APPENDIX 3 3 List of precautions A D converter 1 When the operating mode of the A D converter is changed from the comparator mode to the A D conversion mode with the bit 3 of register Q2 in a program be careful about the following notes Clear the bit 2 of register V2 to 0 to change the operating mode of the A D converter from the co
150. he function of the voltage comparator The function of the voltage comparator CMPO becomes valid by setting bit 2 of register Q3 to 1 and becomes invalid by setting bit 2 of register Q3 to 0 The comparison result of the voltage com parator is stored into bit 0 of register The function of the voltage comparator CMP1 becomes valid by setting bit 3 of register Q3 to 1 and becomes invalid by setting bit 3 of register Q3 to 0 The comparison result of the voltage com parator CMP1 is stored into bit 1 of register 2 Operation description of voltage comparator The voltage comparator function becomes valid by setting each control bit of register to 1 and compares the voltage of the in put pin The comparison result is stored into each comparison result store bit of register Q3 The comparison result is as follows When CMPO gt Q30 0 When lt CMP0 Q30 1 When CMP1 gt 1 Q31 0 When 1 CMP1 Q31 1 3 Precautions When the voltage comparator is used note the following Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3 it is operating even in the RAM back up mode Accordingly be careful about such state because it causes the increase of the operation current in the RAM back up mode In order to reduce the operation
151. he output latch is set to 0 L level can be input Noise and latch up prevention Connect an approximate 0 1 uF bypass capacitor directly to the Vss line and the VDD line with the thickest possible wire at the shortest distance and equalize its wiring in width and length The CNVSs pin is also used as the VPP pin programming voltage 12 5 V at the built in PROM version Connect the CNVSsS VPP pin to Vss through an approximate 5 resistor which is connected to the CNVSs VPP pin at the shortest distance Note on multifunction The input of De D7 20 22 CMP0 1 CMP1 and the input output of P30 P31 40 43 can be used even when CNTRO CNTR1 SCK Sour SIN AINO AIN3 INTO INT1 and AIN4 AIN7 are selected Connection of unused pins Table 2 1 6 shows the connections of unused pins SD RD instructions When the SD and RD instructions are used do not set 10002 or more to register Y Analog input pins When both analog input AlN4 AIN7 and I O port P4 function are used note the following Notes when selecting analog input pins Even when register Q2 is used to set the pins for analog input P40 AIN4 P43 AIN7 continue to function as P40 P43 Accordingly when any of them are used as 1 0 port P4 and others used as analog input pins make sure to set the outputs of pins that are set for analog input to 1 Also for the port input the port input function of the pin fun
152. he program from address 0 in page 0 In this case the P flag is 1 3 Cold start condition The CPU starts executing the program from address 0 in page 0 when reset pulse is input to RESET pin or reset by watchdog timer is performed or voltage drop detection circuit detects the voltage drop In this case the P flag is 0 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS Table 20 Functions and states retained at RAM back up Function RAM back up Program counter PC registers A B carry flag CY stack pointer SP Note 2 Contents of RAM Port level Timer control register W1 Timer control registers W2 to W4 W6 Clock control register MR Interrupt control registers V1 V2 Interrupt control registers 11 12 Timer 1 function Timer 2 function Timer 3 function Timer 4 function A D conversion function A D control registers Q1 Q2 Voltage comparator function Voltage comparator control register Q3 Serial function Serial mode register J1 Pull up control register PUO Key on wakeup control register KO Direction register FRO External 0 interrupt request flag EXFO External 1 interrupt request flag EXF1 Timer 1 interrupt request flag T1F x Watchdog timer flags WDF1 WDF2 Watchdog timer enable flag WEF 16 bit timer WDT A D conversion complet
153. he result in register X Adds 1 to the contents of register Y As a result of addition when the contents of register Y is 0 the next instruction is skipped After transferring the contents of register A to M DP an exclusive OR operation is performed between reg ister X and the value j in the immediate field and stores the result in register X 4513 4514 Group User s Manual 1 71 HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS continued Parameter Instruction code Mnemonic Function Hexadecimal Number of words Number of Ds D7 De Ds D4 Di instructions notation 0 p DR2 DRo OM PO 7 4 OM PC 3 0 SK SP lt SP 1 Note A M DP M DP CY arry Arithmetic operation Bit operation Comparison operation Note p is 0 to 15 for M34513M2 p is 0 to 31 for M34513M4 E4 p is 0 to 47 for M34513M6 and M34514M6 and p is 0 to 63 for M34513M8 E8 and M34514M8 E8 1 72 4513 4514 Group User s Manual HARDWARE MACHINE INSTRUCTIONS Skip condition Datailed description Continuous Loads the value n in the immediate field to register A description When the LA instructions are continuously coded and executed only the first LA instruction is executed and other LA instructions coded continuously are skipped Transfers bits 7 to 4 to register B and bits 3 to 0 to register A These bits
154. imate Mark Specification Form 32P6B A for M34513M8 XXXFP and attach to the Mask ROM Order Confirmation Form 3 Comments Low order 5 bit data 4513 4514 Group User s Manual 000016 1FFF e 400016 5FFF e of low order and high order 5 bit data 3 33 APPENDIX 3 5 Mask ROM order confirmation form GZZ SH52 41B lt 81A0 gt 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M34514M6 XXXFP MITSUBISHI ELECTRIC Please fill in all items marked Company name Customer Mask ROM number Date issued 1 Confirmation Specify the type of 5 submitted Issuance signature Date Section head signature Supervisor signature Responsible officer Supervisor Three sets of EPROMs are required for each pattern check in the approximate box If at least two of the three sets of EPROMs submitted contain the identical data we will produce masks based on this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data Thus the customer must be especially careful in verifying the data contained in the EPROMs submitted Checksum code for entire EPROM area LI LL hexadecimal notation EPROM Type 270256 270512 Low order 5 bit data 17FFss 400016 High order 5 bit data 57FFie 1 7FFFie
155. immediate field of 0103 M DP is 0 Skips the next instruction when the contents of register A is equal to the contents of M DP Skips the next instruction when the contents of register A is equal to the value n in the immediate field 4513 4514 Group User s Manual 1 73 HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS continued Parameter Instruction code Mnemonic instructions Ds D4 D3 D2 Di Hexadecimal notation Number of words Number of Function Branch operation 9 D o o o c 2 o 9 2 a5 a4 a3 a2 a1 p2 18 PCL ae ao PCH p PCL ae ao Note PCH p PCL DR2 DRo Return operation SP SP 1 PC SK SP SP SP 1 Interrupt operation Note p is 0 to 15 for M34513M2 p is 0 to 31 for M34513M4 E4 p is 0 to 47 for M34513M6 and M34514M6 and p is 0 to 63 for M34513M8 E8 and M34514M8 E8 1 74 4513 4514 Group User s Manual INTE 0 INTE 1 EXFO 1 After skipping 0 EXF1 1 After skipping EXF1 0 Skip condition HARDWARE MACHINE INSTRUCTIONS Datailed description Branch within a page Branches to address a in the identical page Branch out of a page Branches to address a in page p Branch out of a page Branches to
156. ing example to reset a microcomputer to normal operation the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine This example assumes that interrupt processing is repeated multiple times in a single main routine processing 3 28 4513 4514 Group User s Manual APPENDIX 3 4 Notes on noise lt The main routine gt Assigns a single word of RAM to a software watchdog timer SWDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following condition Counts of interrupt processing executed in 1 gt each main routine As the main routine execution cycle may change because of an interrupt processing or others the initial value N should have a margin Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents do not change after interrupt processing The interrupt processing routine Decrements the SWDT contents by 1 at each interrupt processing Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at a
157. instruction can be used to transfer the contents of register V2 to register A Interrupt control register V1 at reset 00002 at RAM back up 00002 Interrupt disabled SNZT2 instruction is valid Timer 2 interrupt enable bit Interrupt enabled SNZT2 instruction is invalid Interrupt disabled SNZT1 instruction is valid Timer 1 interrupt enable bit Interrupt enabled SNZT1 instruction is invalid Interrupt disabled SNZ1 instruction is valid External 1 interrupt enable bit Interrupt enabled SNZ1 instruction is invalid Interrupt disabled SNZO instruction is valid External 0 interrupt enable bit 0 1 0 1 0 1 0 1 Interrupt control register V2 Interrupt enabled SNZO instruction is invalid reset 00002 at RAM back up 00002 Interrupt disabled SNZSI instruction is valid Serial I O interrupt enable bit Interrupt enabled SNZSI instruction is invalid Interrupt disabled SNZAD instruction is valid A D interrupt enable bit Interrupt enabled SNZAD instruction is invalid Interrupt disabled SNZTA instruction is valid Timer 4 interrupt enable bit Interrupt enabled SNZT4 instruction is invalid Interrupt disabled SNZT3 instruction is valid Timer 3 interrupt enable bit Note R represents read enabled and W represents write enabled Interrupt enabled SNZTS instruction is invalid 1 24 4513 4514 Group
158. ion 5 Software start Reset input or voltage drop detection R circuit output Set source POF instruction is executed Cold start Warm start Clear source Reset input Fig 39 Set source and clear source of the P flag Fig 40 Start condition identified example using the SNZP in struction 4513 4514 Group User s Manual 1 55 HARDWARE FUNCTION BLOCK OPERATIONS Table 22 Key on wakeup control register pull up control register and interrupt control register Key on wakeup control register KO at reset 00002 at RAM back up state retained Pins P12 and P13 key on wakeup control bit Key on wakeup not used Key on wakeup used Pins P10 and P11 key on wakeup control bit Key on wakeup not used Key on wakeup used Pins P02 and P03 key on wakeup control bit Key on wakeup not used Key on wakeup used Pins POo and P01 key on wakeup control bit Pull up control register PUO Pins P12 and P13 pull up transistor control bit Pins P10 and P11 pull up transistor control bit Pins P02 and P03 pull up transistor control bit Key on wakeup not used 9 00002 at RAM back up state retained Pull up transistor O Pull up transistor ON Pull up transistor O Pull up transistor ON Pull up transistor OFF Pull up transistor ON Pins POo and P01 pull up transistor control bit Interrupt control r
159. ion related registers application example using each port function and notes 2 1 1 I O ports 1 Port PO Port PO is a 4 bit I O port Port PO has the key on wakeup function which turns ON OFF with register KO and pull up transistor which turns ON OFF with register PUO B input output of port PO Data input to port PO Set the output latch of specified port i20 to 3 to 1 with the OPOA instruction If the output latch is set to 0 L level is input The state of port PO is transferred to register A when the IAPO instruction is executed Data output from port PO The contents of register A is output to port PO with the OPOA instruction The output structure is an N channel open drain 2 Port P1 Port P1 is a 4 bit I O port Port P1 has the key on wakeup function which turns ON OFF with register KO and pull up transistor which turns ON OFF with register PUO B input output of port P1 Data input to port P1 Set the output latch of specified port P1i i20 to 3 to 1 with the instruction If the output latch is set to 0 L level is input The state of port P1 is transferred to register A when the IAP1 instruction is executed Data output from port P1 The contents of register is output to port P1 with the instruction The output structure is an N channel open drain 3 Port P2 Port P2 is a 3 bit input port E Input of port P2 Data input to port P2 The
160. ion cleared SNZT1 instruction INTO interrupt activated condition cleared INTO interrupt request flag EXFO SNZO instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flags T1F and EXFO insert the NOP instruction after the SNZT1 and SNZO instructions Enable Interrupts The timer 1 interrupt which is temporarily disabled is enabled Interrupt control register V1 FIRE Ama erable Interrupt enable flag INTE 4 All interrupts enabled El instruction Timer start by external input X it be 0 or 1 Fig 2 3 7 Timer start by external input setting example 1 2 36 4513 4514 Group User s Manual APPLICATION 2 3 Timers Processing in interrupt service routine Stop Timer Timer 1 control disabled Interrupt control register 11 x 1 0 0 instruction 9 Reset Timer TI1A instruction Timer 1 reload register R1 5216 Timer count value 82 set T1AB instruction b3 bO 1 Timer 1 control enabled Interrupt control register 11 1 0 1 X it can be 0 or 1 Fig 2 3 8 Timer start by external input setting example 2 4513 4514 Group User s Manual 2 37 APPLICATION 2 3 Timers Activate Watchdog Timer Watchdog timer is activated Watchdog timer enable flag WEF 1 Watchdog timer enable flag WEF set WRST instruction Main
161. ion flag ADF Serial I O transmission reception completion flag SIOF Interrupt enable flag INTE Notes 1 O represents that the function can be retained and X repre sents that the function is initialized Registers and flags other than the above are undefined at RAM back up and set an initial value after returning 2 The stack pointer SP points the level of the stack register and is initialized to 7 at RAM back up 3 The state of the timer is undefined 4 Initialize the watchdog timer with the WRST instruction and then execute the POF instruction 5 The state is retained when the voltage comparator function is se lected with the voltage comparator control register Q3 1 53 HARDWARE FUNCTION BLOCK OPERATIONS 4 Return signal An external wakeup signal is used to return from the RAM back up mode because the oscillation is stopped Table 21 shows the return condition for each return source 5 Ports PO and P1 control registers Key on wakeup control register KO Register KO controls the ports PO and P1 key on wakeup func tion Set the contents of this register through register A with the TKOA instruction In addition the TAKO instruction can be used to transfer the contents of register KO to register A Pull up control register PUO Register PUO controls the ON OFF of the ports PO and P1 pull up transistor Set the contents of this register through register A with the TPUOA in
162. isabled SNZT3 instruction is valid 1 Interrupt enabled SNZTS instruction is invalid Notes 1 R represents read enabled and W represents write enabled 2 When timer is used V22 and V23 are not used V20 3 interrupt enable bit 4513 4514 Group User s Manual 2 27 APPLICATION 2 3 Timers 3 Timer control register W1 The timer 1 count start synchronous circuit control bit is assigned to bit 0 the timer 1 control bit is assigned to bit 1 the prescaler dividing ratio selection bit is assigned to bit 2 and the prescaler control bit is assigned to bit 3 Set the contents of this register through register A with the TW1A instruction The instruction can be used to transfer the contents of register W1 to register A Table 2 3 3 shows the timer control register W1 at reset 00002 at RAM back up 00002 0 Stop state initialized 1 Operating 0 Instruction clock divided by 4 1 Instruction clock divided by 16 0 Stop state retained 1 0 Table 2 3 3 Timer control register W1 Timer control register W1 R W W13 control bit Prescaler dividing ratio selection bit W12 W11 1 control bit Operating Count start synchronous circuit not selected Count start synchronous circuit selected Timer 1 count synchronous circuit control bit W1o Note represents read enabled and W represents write e
163. it is 1 the next instruction is executed Data output from port D Set the output level to the output latch with the SD and RD instructions The state of pin enters the high impedance state when the SD instruction is executed The states of all port D enter the high impedance state when the CLD instruction is executed The state of pin becomes L level when the RD instruction is executed The output structure is an N channel open drain Notes 1 When the SD and RD instructions are used do not set 10002 or more to register Y 2 Port De is also used as CNTRO and port D7 is also used as CNTR1 Accordingly when using ports De and D7 functions set bit 0 W60 and bit 2 W62 of timer control register W6 to 0 2 1 2 Related registers 1 Pull up control register PUO Register PUO controls the ON OFF of the ports POo P03 and P10 P13 pull up transistor Set the contents of this register through register A with the TPUOA instruction The contents of register PUO is transferred to register A with the TAPUO instruction Table 2 1 1 shows the pull up control register PUO Table 2 1 1 Pull up control register PUO Pull up control register PUO at reset 00002 at RAM back up state retained R W 12 1 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PUO Ports P10 P11 0 Pull up transistor OFF pull up transistor control bit 1 Pull up transistor ON PU
164. l transmission reception completion flag SIOF Serial I O mode register J1 Serial register SI A D conversion completion flag ADF A D control register Q1 A D control register Q2 Voltage comparator control register Q3 Successive comparison register AD Comparator register Key on wakeup control register KO Pull up control register PUO Direction register FRO Carry flag CY Register A Register B Register D Register E Register X Register Y Register Z Stack pointer SP External clock selected and serial port not selected lololo x O O O x x lololo xixi Port P5 input mode X represents undefined Fig 35 Internal state at reset 4513 4514 Group User s Manual 1 51 HARDWARE FUNCTION BLOCK OPERATIONS VOLTAGE DROP DETECTION CIRCUIT The built in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value RESET pino 5 B gt Internal reset signal KGE 7 Voltage drop detection circuit C Watchdog timer output WEF Note The output structure of RESET pin is N channel open drain Fig 36 Voltage drop detection
165. l communication is executed to are repeated X it can be 0 or 1 Fig 2 4 5 Master serial setting example 2 46 4513 4514 Group User s Manual APPLICATION 2 4 Serial I O Disable Interrupts Serial I O interrupt is temporarily disabled Interrupt enable flag INTE o All interrupts disabled DI instruction Interrupt control register V2 occurrence disabled Set Serial I O 5 Exernal clock selected TJ1A instruction Serial I O mode register J1 x x 1 0 selected Clear Interrupt Request Serial I O interrupt activated condition is cleared Serial I O transmit receive 0 Serial I O interrupt activated condition cleared completion flag SIOF SNZSI instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the SIOF flag insert the NOP instruction after the SNZSI instruction When interrupt is m When interrupt is used Set Interrupt Set Interrupt Interrupts except serial I O is enabled Serial I O interrupt tempera dieen is enabled EI instruction x Serial I O interrupt occurrence Interrupt control register V2 1 x Snabled TV2A Interrupt enable flag INTE 1 All interrupts enabled El instruction Set When Transmit Receive Operation Start Enabled Serial transfer start state SST instruction System enters to
166. l input setting example 2 2 37 2 3 9 Watchdog timer setting example 2 38 2 4 1 Serial core tire ri re a deed 2 40 2 4 2 Serial connection example ener 2 42 2 4 3 Serial I O register state when transmitting receiving 2 42 2 4 4 Serial transfer enne aa aa 2 43 2 4 5 Master serial I O setting 2 46 2 4 6 Slave serial 2 47 2 4 7 Input waveform of external 4 24 2 48 2 5 1 A D converter structure 4 4 2 49 2 5 2 A D conversion mode setting example 2 51 2 5 3 Analog input external circuit 1 2 52 2 5 4 Analog input external circuit 2 2 52 2 5 5 A D converter operating mode program 2 52 2 7 1 Power on reset circuit 2 56 2 7 2 Oscillation stabilizing time after system is released from 2 56 2 7 3 Internal state at 2 57 2 8 1 V
167. le 9 Function related timers sssssssssssssssssseseeee eene nennen nennen nnns nennt 1 30 Table 10 Timer control FOglsIerS oth LE ke top e ting ani 1 32 Tablett Serial Pins ES 1 36 Table 12 Serial MOS register etre tite terne reete aaae esu i laa 1 36 Table 13 Processing sequence of data transfer from master to slave 1 40 Table 14 converter 224 1 41 Table 15 A D control registers 1 42 Table 16 Change of successive comparison register AD during A D conversion 1 43 Table 17 Voltage comparator characteristics 4 000 0000 1 47 Table 18 Voltage comparator control register 1 48 Table 19 Port state at ian eorr rte odore tesa 1 50 Table 20 Functions and states retained at RAM back up 1 53 Table 21 Return source and return 1 54 Table 22 Key on wakeup control register pull up control register and interrupt control 1 56 Table 23 Clock control register 44 0 211 00 nnne nennen entren 1 57 Table 24 Maximum value of external clock oscillation
168. le Interrupts Timer 2 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI instruction b3 5 Interrupt control register vt oppi Timer 2 interrupt occurrence disabled 2 Stop Timer Operation Timer 1 operation is temporarily stopped Timer 2 count source is selected 5 Timer 2 stop TW2A instruction Timer control register Wa of 1 o CNTRO input selected for count source Set Timer Value Timer 2 count time is set Timer 2 reload register R2 6316 Timer count value 99 set T2AB instruction Clear Interrupt Request Timer 2 interrupt activated condition is cleared Timer 2 interrupt request flag T2F 0 Timer 2 interrupt activated condition cleared SNZT2 instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T2F insert the NOP instruction after the SNZT2 instruction i Start Timer 2 Operation Timer 2 temporarily stopped is restarted b3 bO Enable Interrupts The timer 2 interrupt which is M disabled i is enabled Interrupt control register vt QEZ interrupt occurrence enabled Interrupt enable flag INTE All interrupts enabled El instruction X it can be 0 or 1 Fig 2 3 5 CNTR1 input setting example However specify the pulse width input to CNTRO pin CNTR1 pin Refer to section 2 3 4 Notes on use for the ti
169. lmost fixed cycles at the fixed interrupt processing count Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less Interrupt processing routine SWDT lt SWDT 1 Interrupt processing Sx lt 0 Y Return Interrupt processing Main routine routine errors errors Fig 3 4 11 Watchdog timer by software 4513 4514 Group User s Manual 3 29 APPENDIX 3 5 Mask ROM order confirmation form 3 5 Mask ROM order confirmation GZZ SH52 45B lt 81A0 gt 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M34513M2 XXXSP FP MITSUBISHI ELECTRI Please fill in all items marked Company name Customer form Mask ROM number Date Section head signature Supervisor signature Responsible officer Supervisor Date issued 1 Confirmation Specify the type of EPROMs submitted Issuance signature Three sets of EPROMs are required for each pattern check in the approximate box If at least two of the three sets of EPROMs submitted contain the identical data we will produce masks based on this data We shall assume the responsibility for errors only if
170. lock the clock frequency input to the Sck pin determines the data transfer rate Figure 2 4 1 shows the serial block diagram Division circuit divided by 2 Internal clock generation circuit Instruction clock divided by 3 Serial I O mode register J1 0 i SIOF gt Serial I O interrupt 20 5 Serial I O counter 3 sioF p P21 SouTO P22 SIN MSB Serial I O register SI 8 LSB Register B 4 Register A 4 Note The output structure of Sck and Sour pins is N channel open drain Fig 2 4 1 Serial block diagram 2 40 4513 4514 Group User s Manual APPLICATION 2 4 Serial I O 2 4 2 Related registers 1 Serial I O register SI Serial I O register SI is the 8 bit data transfer serial parallel conversion register Data can be set to register SI through registers A and B with the TSIAB instruction 2 Serial mode register J1 Serial I O synchronous clock selection bit is assigned to bit 0 serial I O port selection bit is assigned to bit 1 and serial internal clock dividing ratio selection bit is assigned to bit 2 Set the contents of this register through register A with the TJ1A instruction The TAJ1 instruction can be used to transfer the contents of register J1 to register A Table 2 4 1 shows the serial mode register J1 Table 2 4 1 Serial mode register J1 Serial I O mode register J1 at reset 00002
171. ltage comparator input pin when the volt age comparator function is selected by software CMP1 CMP1 pins are also used as AIN2 and AIN3 4513 4514 Group User s Manual 1 9 HARDWARE PIN DESCRIPTION MULTIFUNCTION Multifunction i Multifunction i Multifunction i Multifunction CNTRO De AINO CNTR1 D7 AIN1 5 SOUT SIN 1 AIN2 CMP1 AIN3 INTO INT1 Notes 1 Pins except above have just single function 2 The input of De D7 P20 P22 CMP0 CMP1 1 and the input output of P30 P31 P40 P43 can be used even when CNTRO 1 Sck SOUT SIN INTO INT1 and AINO AIN7 are selected 3 The 4513 Group does not P40 AIN4 P43 AIN7 CONNECTIONS OF UNUSED PINS Connection XOUT Open when using an external clock VDCE Connect to Vss Do Ds De CNTRO D7 CNTR1 Connect to Vss or set the output latch to 0 and open P20 SCK P21 SoUT P22 SIN Connect to Vss P30 INTO P31 INT1 P32 P33 Connect to Vss or set the output latch to 0 and open P40 AIN4 P43 AIN7 Connect to Vss or set the output latch to 0 and open 5 5 Note 1 When the input mode is selected by soft ware pull up to VDD through a resistor or pull down to VDD When selecting the output mode open AIN1 CMP0 AIN2 CMP1 AIN3 CMP1 P0o P03 Connect to Vss Open or
172. mber Date Section head Supervisor MITSUBISHI ELECTRIC signature signature Please fill in all items marked Company name Customer Responsible officer Supervisor Date issued 1 Confirmation Specify the type of EPROMs submitted Issuance signature Three sets of EPROMs are required for each pattern check in the approximate box If at least two of the three sets of EPROMs submitted contain the identical data we will produce masks based on this data We shall assume on the products we produce differ from this the responsibility for errors only if the mask ROM data data Thus the customer must be especially careful in verifying the data contained in the EPROMs submitted Checksum code for entire EPROM area LI LJ hexadecimal notation EPROM Type 270256 270512 Low order 99278 5 bit data 1 400016 High order 5 bit data 57FFie 2 7FFFie Set 16 in the shaded area Set 1112 in the area 2 Mark Specification Low order 2096 5 bit data 17FFis High order 2 57FFie FFFFic of low order and high order 5 bit data 400016 Mark specification must be submitted using the correct form for the type of package being ordered Fill out the approximate Mark Specification the Mask ROM Order Confirmation Form 3 Comments Form 32P6B A for M34
173. mended operating conditions Table 3 1 2 Recommended operating conditions 1 APPENDIX 3 1 Electrical characteristics Mask ROM version Ta 20 to 85 C VDD 2 0 V to 5 5 V unless otherwise noted One Time PROM version Ta 20 C to 85 VDD 2 5 V to 5 5 V unless otherwise noted Parameter Conditions Limits Typ Supply voltage Mask ROM version Middle speed mode gt 2 2 2 5 0 2 2 0 Mask ROM version High speed mode 2 MHz 4 0 gt 0 2 2 5 IA IA JIA JIA TIA 4 3 4 2 1 Ba Bo z 515151512 5 MHz 2 0 One Time PROM version Middle speed mode f XIN lt 4 2 MHz 2 5 One Time PROM version High speed mode f XIN lt 4 2 MHz 4 0 f XIN lt 2 0 MHz 2 5 RAM back up voltage at RAM back up mode Mask ROM version 1 8 One Time PROM version 2 0 Supply voltage H level input voltage PO P1 P2 P5 XIN VDCE 0 8VDD VDD H level input voltage Do D7 0 8VDD 12 H level input voltage RESET 0 85VDD VDD H level input voltage CNTRO CNTR1 SIN Sck INTO INT1 0 85VDD VDD L level input voltage PO P1 P2 P5 Do D7 VDCE 0 2VDD L level input voltage RESET 0 3VDD L level input voltage CNTRO CNTR1 SIN Sck INTO INT1
174. mer external input period condition 2 34 4513 4514 Group User s Manual APPLICATION 2 3 Timers Disable Interrupts Timer 3 and timer 4 interrupt are temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI instruction b3 60 Ti 3 and ti 4 interrupt occurrence disabled Interrupt control register 2 x x 0 0 TV2A P 2 Stop Timer Operation Timer is temporarily stopped Dividing ratio of prescaler is selected Timer 3 count source is selected Timer 4 count source is selected Ti 3 stop TW3A instruction imer 3 stop instruction Timer control register W3 0 0 1 Prescaler selected for count source b3 b0 Timer 4 stop TW4A instruction Timer control register W4 0 x 0 0 Timer 3 underflow selected for count source 20 Instruction clock divided by 4 selected Timer control register W1 1 o x x instruction y Set Timer Value Select CNTR1 Output 1 output is selected Timer 3 and timer 4 count time are set 0 Timer control register W6 CNTR1 output selected TW6A instruction Timer 3 reload register R3 2916 Timer count value 41 set T3AB instruction Timer 3 reload register R4 FF16 Timer count value 255 set T4AB instruction Start Timer Operation Timer 3 and timer 4 temporarily stopped are restarted b3 bo Timer control register wa3 1 x 0 1 Timer operation start TW3A instruction b3 bO Timer control regi
175. mparator mode to the A D con version mode with the bit 3 of register Q2 refer to Figure 466 The A D conversion completion flag ADF may be set when the Fi operating mode of the A D converter is changed from the com parator mode to the A D conversion mode Accordingly set a value to register Q2 and execute the SNZAD instruction to clear the ADF flag Do not change the operating mode both A D conversion mode and comparator mode of A D converter with the bit 3 of register Q2 during operating the A D converter X0XX2 The SNZAD instruction is valid 0XXX2 Change of the operating mode of the A D converter from the comparator mode to the A D conversion mode X this bit is not related to the change of the operating mode of the A D conversion g 46 A D converter operating mode program example OA D converter 2 3 22 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage Accordingly when the analog voltage is input from the circuit with high impedance and charge discharge noise is generated and the sufficient A D accuracy may not be obtained Therefore reduce the impedance or con nect a capacitor 0 01 uF to 1 uF to analog input pins Figure 47 When the overvoltage applied to the A D conversion circuit may occur connect an external circuit in order to keep the voltage within the rated range as shown the Figure 48 In addition test the application produc
176. n SRDY signal st 5 X Se X S A S A S A S A 5 Mi OX Mo X Ms Ms X Me Mo M7 the contents of master serial lO 50 57 the contents of slave serial I O register Rising of SCK serialinput Falling of SCK serial output Fig 25 Timing of serial 1 data transfer 4513 4514 Group User s Manual 1 39 HARDWARE FUNCTION BLOCK OPERATIONS Table 13 Processing sequence of data transfer from master to slave Master transmission Slave reception Initial setting Setting the serial I O mode register J1 and inter rupt control register V2 shown in Figure 24 Initial setting Setting serial I O mode register J1 and interrupt control register V2 shown Figure 24 TJ1A and TV2A instructions instructions Setting the port received the reception enable signal SRDY to the input mode Port D5 is used in this example Setting the port transmitted the reception enable signal SRDY and outputting H level reception impossible Port D5 is used in this example SD instruction SD instruction Transmission enable state Storing transmission data to serial I O register SI Reception enable state SIOF flag is cleared to 0 TSIAB instruction SST instruction L level reception possible is output from port 05 RD instruction Transmission Check port Ds is L level SZD instr
177. n Set the contents of this register through register A with the TJ1A instruction The TAJ1 instruction can be used to transfer the contents of register J1 to register A 1 37 HARDWARE FUNCTION BLOCK OPERATIONS 5 How to use serial I O Figure 24 shows the serial I O connection example Serial I O inter rupt is not used in this example In the actual wiring pull up the Master clock control wiring between each pin with a resistor Figure 25 shows the data transfer timing and Table 13 shows the data transfer sequence Slave external clock SRDY signal 1 Serial I O mode register J1 L Internal clock selected as a synchronous clock Serial port SCK SOUT SIN Instruction clock divided by 8 or 4 selected as a transfer clock Bit 0 x Interrupt control register V2 Serial I O interrupt enable bit SNZSI instruction is valid Fig 24 Serial I O connection example 1 38 Bit 0 0 Serial I O mode register J1 External clock selected as a synchronous clock Serial I O port SCK SOUT SIN This bit is not valid when J10z 0 Bit 0 x Interrupt control register V2 Serial I O interrupt enable bit SNZSI instruction is valid X Set an arbitrary value 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS Master SOUT SIN SST instruction SST instructio
178. n a skip is performed with the SNZO instruction amp Set both the external 0 interrupt enable bit V10 and the INTE flag to 1 The external 0 interrupt is now enabled Now when a valid wave form is input to the P30 INTO pin the EXFO flag is set to 1 and the external 0 interrupt occurs 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS 2 External 1 interrupt request flag EXF1 External 1 interrupt request flag EXF1 is set to 1 when a valid waveform is input to P31 INT1 pin The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock Refer to Figure 16 The state of EXF1 flag can be examined with the skip instruction SNZ1 Use the interrupt control register V1 to select the interrupt or the skip instruction The EXF1 flag is cleared to 0 when an in terrupt occurs or when the next instruction is skipped with the skip instruction The P31 INT1 pin need not be selected the external interrupt input INT1 function or the normal I O port P31 function However the EXF1 flag is set to 1 when a valid waveform is input even if it is used as an 1 port P31 External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31 INT1 pin The valid waveform can be selected from rising waveform falling waveform or both rising and falling waveforms An example of h
179. n the contents of 122 is changed the external interrupt request flag EXF1 may be set Accordingly clear EXF1 flag with the SNZ1 instruction 1 56 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS CLOCK CONTROL The clock control circuit consists of the following circuits System clock generating circuit Control circuit to stop the clock oscillation Division circuit divided by 2 XinO Oscillation Xour o 4ircuit POF instruction Control circuit to switch the middle speed mode and high speed mode Control circuit to return from the RAM back up state System clock Internal clock generation circuit Instruction clock Wait time Note control circuit start signal o RESET Key on wake up control register K00 K01 K02 K03 1 Ports P01 Ports P02 P03 r Ports P10 P11 Ports P12 P13 112 L level P30 INTo level 22 L level P31 INT1 H level Note The wait time control circuit is used to generate the time required to stabilize the f XIN oscillation Fig 41 Clock control circuit structure Table 23 Clock control register MR Clock control register MR at reset 10002 at RAM back up 10002 System clock selection bit f XIN high speed mode f XIN 2 middle speed mode Not used This bit has no function but read write is enabled Not used This bit has no function
180. nabled 4 Timer control register W2 The timer 2 count source selection bits are assigned to bits 0 and 1 and the timer 2 control bit is assigned to bit 3 Set the contents of this register through register A with the TW2A instruction The TAW2 instruction can be used to transfer the contents of register W2 to register A Table 2 3 4 shows the timer control register W2 at reset 00002 at RAM back up state retained 0 Stop state retained Operating Table 2 3 4 Timer control register W2 Timer control register W2 R W W23 2 control bit W22 Not used This bit has no function but read write is enabled Count source W21 0 1 underflow signal 1 Prescaler output 0 input 16 bit timer WDT underflow signal Note R represents read enabled and W represents write enabled Timer 2 count source selection bits W20 2 28 4513 4514 Group User s Manual APPLICATION 2 3 Timers 5 Timer control register W3 The timer 3 count source selection bits are assigned to bits 0 and 1 the timer 3 count start synchronous circuit control bit is assigned to bit 2 and the timer 3 control bit is assigned to bit 3 Set the contents of this register through register A with the TW3A instruction The TAW3 instruction can be used to transfer the contents of register W3 to register A Table 2 3 5 shows the timer control register W3 at reset 00002 at R
181. nd 1 of register W3 and set the bit 3 of register W3 to 1 However P31 INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 2 of register W3 to 1 When a value set in timer 3 is n timer 3 divides the count source signal by 1 n 0 to 255 Once count is started when timer 3 underflows the next count pulse is input after the contents of timer 3 becomes 0 the timer 3 interrupt request flag T3F is set to 1 new data is loaded from reload register R3 and count continues auto reload function Data be read from timer 3 with the TAB3 instruction When reading the data stop the counter and then execute the TAB3 in struction Timer 3 underflow signal divided by 2 can be output from D7 CNTR1 pin 7 Timer 4 interrupt function Timer 4 is an 8 bit binary down counter with the timer 4 reload reg ister R4 Data can be set simultaneously in timer 4 and the reload register R4 with the T4AB instruction Timer 4 starts counting after the following process set data in timer 4 select the count source with the bits 0 and 1 of register W4 and set the bit 3 of register W4 to 1 When a value set in timer 4 is n timer 4 divides the count source signal by 1 n 0 to 255 Once count is started when timer 4 underflows the next count pulse is input after the contents of timer 4 becomes 0 the timer 4 interrupt request flag is set to
182. ndition is cleared INTO interrupt request flag EXFO 0 INTO interrupt activated condition cleared SNZO instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag EXFO insert the NOP instruction after the SNZO instruction Enable Interrupts The INTO interrupt which is is enabled INT Interrupt control register V1 i enabled Interrupt enable flag INTE 41 M interrupts enabled El instruction INTO interrupt execution started X it be 0 or 1 Fig 2 2 2 INTO interrupt setting example Note The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock 2 18 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts P31 INT1 H An interrupt occurs after the valid waveform falling is detected P31 INT1 interrupt occurs after the valid waveform rising is detected Fig 2 2 3 INT1 interrupt operation example 4513 4514 Group User s Manual 2 19 APPLICATION 2 2 Interrupts Disable Interrupts INT1 interrupt is temporarily disabled Interrupt enable flag INTE de All interrupts disabled DI instruction INT1 interrupt occurrence disabled Interrupt control register V1 Sy eas 2 Set Port Port used for INT1 interrupt is set to input port
183. nted 16892 to 1 machine cycle or more 46895 times 0 85 Software starts RESET TA address 0 in page 0 Note Keep the value of supply voltage to the minimum value or more of the recommended operating conditions Fig 2 7 2 Oscillation stabilizing time after system is released from reset 2 56 4513 4514 Group User s Manual APPLICATION 2 7 Reset 2 7 2 Internal state at reset Figure 2 7 3 shows the internal state at reset The contents of timers registers flags and RAM other than shown in Figure 2 7 3 are undefined so that set them to initial values Program counter PC Address 0 in page 0 is set to program counter Interrupt enable flag INTE Interrupt disabled Power down flag P External 0 interrupt request flag EXFO External 1 interrupt request flag EXF1 Interrupt control register V1 Interrupt disabled Interrupt control register V2 Interrupt disabled Interrupt control register 11 Interrupt control register 12 Timer 1 interrupt request flag T1F Timer 2 interrupt request flag T2F Timer 3 interrupt request flag T3F Timer 4 interrupt request flag T4F Watchdog timer flags WDF1 WDF2 Watchdog timer enable flag WEF Timer control register W1 Timer control register W2 Timer control register W3 Timer control register W4 Timer co
184. nter PC registers A B Pull up control register PUO carry flag CY stack pointer SP Note 2 Key on wakeup control register KO Contents of Direction register FRO Port level O External 0 interrupt request flag EXFO x Timer control register W1 x External 1 interrupt request flag EXF1 x Timer control registers W2 to W4 W6 Timer 1 interrupt request flag 1 x Clock control register MR x Timer 2 interrupt request flag T2F Note 3 Interrupt control registers V1 V2 x Timer 3 interrupt request flag T3F Note 3 Interrupt control registers 11 12 Timer 4 interrupt request flag Note 3 Timer 1 function x Watchdog timer flags WDF1 WDF2 Note 4 Timer 2 function Note 3 Watchdog timer enable flag WEF Note 4 Timer 3 function Note 3 16 bit timer WDT Note 4 Timer 4 function Note 3 A D conversion completion flag ADF x A D function x Serial I O transmit receive completion flag x A D control registers Q1 Q2 SIOF Voltage comparator function O Note 5 Interrupt enable flag INTE x Voltage comparator control register Q3 Serial I O function Serial I O mode register J1 O Notes 1 O represents that the function can be retained and X represents that the function is initialized Registers and flags other than the above are undefined at RAM back up and set an initial value after returning 2 The stack pointer SP points the level of the stack register and
185. nterrupts enabled El instruction Constant period interrupt execution start The timer 2 count value to make the interrupt occur every about 2 s is set as follows 2 s 4 0 MHz x 3 x 216 x 39 1 System clock Instruction 16 bit Timer 2 clock fixed count dividing value frequency X it can be 0 or 1 Fig 2 2 6 Timer 2 constant period interrupt setting example 2 22 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts Disable Interrupts Timer 3 interrupt is temporarily disabled Interrupt enable flag INTE ka All interrupts disabled DI instruction Foy et 3 interrupt occurrence disabled Interrupt control register V2 TV2A Q Stop Timer 3 Operation Timer 3 and prescaler are temporarily stopped Dividing ratio of prescaler is selected b3 bo S Prescaler stop TW1A instruction Timer control register W1 01157 pregcaler divided by 16 selected i Timer 3 stop instruction Timer control register W3 Prescaler selected for count source Set Timer Value Timer 3 count time is set The formula is shown below Timer reload register R3 5216 Timer count value 82 set T3AB instruction Clear Interrupt Request Timer 3 interrupt activated condition is cleared Timer 3 interrupt request flag T3F 0 Timer 3 interrupt activated condition cleared SNZT3 instruction Note when the interrupt request is cleared When is executed con
186. ntrol register W6 Clock control register MR Serial I O transmit receive completion flag Serial I O mode register J1 External clock selected serial I O port not selected Prescaler timer 1 stopped Timer 2 stopped Timer 3 stopped Timer 4 stopped e Serial I O register SI A D conversion completion flag ADF A D control register Q1 A D control register Q2 Voltage comparator control register Q3 Successive comparison register AD Comparator register Key on wakeup control register KO Pull up control register PUO Direction register FRO Carry flag CY Register A Register B Register D Register E Register X Register Y Register Z Stack pointer SP X represents undefined Fig 2 7 3 Internal state at reset 4513 4514 Group User s Manual 2 57 APPLICATION 2 8 Voltage drop detection circuit 2 8 Voltage drop detection circuit The built in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value Figure 2 8 1 shows the voltage drop detection reset circuit and Figure 2 8 2 shows the operation waveform example of the voltage drop detection
187. o evaluate before actual use 3 4 1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer The shorter the total wiring length by mm unit the less the possibility of noise insertion into a microcomputer 1 Package Select the smallest possible package to make the total wiring length short Reason The wiring length depends on a microcom puter package Use of a small package for example QFP and not DIP makes the total wiring length short to reduce influence of noise Fig 3 4 1 Selection of packages 2 Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible Especially connect a capacitor across the RESET input pin and the Vss pin with the shortest possible wiring Reason In order to reset a microcomputer correctly 1 machine cycle or more of the width of a pulse input into the RESET pin is required If noise having a shorter pulse width than this is input to the RESET input pin the reset is released before the internal state of the microcomputer is completely initialized This may cause a program runaway Reset circuit Vss Reset 7 circuit Fig 3 4 2 Wiring for the RESET input 3 24 4513 4514 Group User s Manual APPENDIX 3 4 Notes on noise 3 Wiring for clock input output pins Make th
188. o registers A and B Transfers the low order 2 bits of the contents of register AD to the high order 2 bits of the contents of regis ter A Simultaneously the low order 2 bits of the contents of the register A is 0 Transfers the contents of registers A and B to the comparator register at the comparator mode Transfers the contents of the A D control register Q1 to register A Transfers the contents of register A to the A D control register Q1 Clears the ADF flag and the A D conversion at the A D conversion mode or the comparator operation at the comparator mode is started Skips the next instruction when the contents of ADF flag is 1 After skipping clears 0 the contents of ADF flag Transfers the contents of the A D control register Q2 to register A Transfers the contents of register A to the A D control register Q2 No operation Puts the system in RAM back up state by executing the POF instruction after executing the EPOF instruction Makes the immediate POF instruction valid by executing the EPOF instruction Skips the next instruction when P flag is 1 After skipping P flag remains unchanged Operates the watchdog timer and initializes the watchdog timer flag WDF1 Transfers the contents of the clock control register MR to register A Transfers the contents of register A to the clock control register MR Transfers the contents of the voltage comparator control register Q3 to register A Transfers the
189. ocks as the count source The underflow signal is generated when the count value reaches 000016 This underflow signal can be used as the timer 2 count source When the WRST instruction is executed after system is released from reset the WEF flag is set to 1 At this time the watchdog timer starts operating The value of timer WDT HARDWARE FUNCTION BLOCK OPERATIONS When the count value of timer WDT reaches BFFFt16 or 3FFF 16 the WDF1 flag is set to 1 If the WRST instruction is never ex ecuted while timer WDT counts 32767 WDF2 flag is set to 1 and the RESET pin outputs L level to reset the microcomputer Ex ecute the WRST instruction at each period of 32766 machine cycle or less by software when using watchdog timer to keep the micro computer operating normally To prevent the WDT stopping in the event of misoperation WEF flag is designed not to initialize once the WRST instruction has been executed Note also that if the WRST instruction is never ex ecuted the watchdog timer does not start 7 7BFFFt16 WDF1 flag WDF flag RESET pin output M yf WRST instruction executed Fig 20 Watchdog timer function The contents of WEF WDF1 and WDF2 flags and timer WDT are initialized at the RAM back up mode If WDF2 flag is set to 1 at the same time that the microcomputer enters the RAM back up state system reset may be performed When using the watchdog timer
190. oltage VDD V 4513 4514 Group User s Manual 3 19 APPENDIX 3 2 Typical characteristics 3 Pins INTO INT1 CNTRO CNTR1 Sck SIN Ta 25 C a rating value 45 4 3 5 VIH VIL VIH VIL V rating value Supply voltage VDD V 3 2 8 Detection voltage temperature characteristics of voltage drop detection circuit 45 44 43 42 4 1 3 9 3 8 37 3 6 3 5 3 4 33 32 3 1 Detection voltage VRST V 2 9 2 8 2 7 2 6 2 5 20 15 10 5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Storage temperature range C 3 20 4513 4514 Group User s Manual APPENDIX 3 3 List of precautions 3 3 List of precautions Noise and latch up prevention Connect a capacitor on the following condition to prevent noise and latch up e connect a bypass capacitor approx 0 1 uF between pins VDD and Vss at the shortest distance equalize its wiring in width and length and use relatively thick wire In the One Time PROM version 55 pin is also used as VPP pin Accordingly when using this pin connect this pin to 55 through a resistor about 5 series at the shortest distance G Prescaler Stop the prescaler operation to change its frequency dividing ra tio G Timer count source Stop timer 1 2 3 or 4 counting to chan
191. oltage drop detection reset circuit 2 58 2 8 2 Voltage drop detection circuit operation waveform 2 58 2 9 1 Start condition identified entren 2 60 2 10 1 Oscillation circuit example connecting ceramic resonator externally 2 63 2 10 2 Structure of clock control circuit 2 64 4513 4514 Group User s Manual V List of figures CHAPTER 3 APPENDIX Fig 3 2 1 A D conversion characteristics 3 14 Fig 44 External 0 interrupt program 3 21 Fig 45 External 1 interrupt program 3 21 Fig 46 A D converter operating mode program 3 22 Fig 47 Analog input external circuit 1 3 22 Fig 48 Analog input external circuit 2 3 22 Fig 3 4 1 Selection of 3 24 Fig 3 4 2 Wiring for the RESET Input tici rit 3 24 Fig 324 3 Wiring for clock suec retener 3 25 19 9 4 4 Wiring 3 25 Fig 3 4 5 Wiring for the VPP pin of the One Time PROM 3 26 Fig 3 4 6 Bypass capacitor across the
192. om reset 2 The address is stacked to the last cycle 3 This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied Fig 16 Interrupt sequence 4513 4514 Group User s Manual 1 25 HARDWARE FUNCTION BLOCK OPERATIONS EXTERNAL INTERRUPTS The 4513 4514 Group has two external interrupts external 0 and external 1 An external interrupt request occurs when a valid waveform is input to an interrupt input pin edge detection The external interrupts can be controlled with the interrupt control registers 1 and 12 Table 7 External interrupt activated conditions Input pin Activated condition External 0 interrupt P30 INTO When the next waveform is input to P30 INTO pin Falling waveform Rising waveform L H Both rising and falling waveforms Valid waveform selection bit External 1 interrupt P31 INT1 When the next waveform is input to P31 INT1 pin Falling waveform H gt L Rising waveform L H Both rising and falling waveforms 112 Ed Falling One sided edge detection circuit P3o INTO o 4 External 0 Y interrupt Both edges m detection circuit Wakeup skip 22 One sided edge detection circuit Y interrupt Both edges detection circuit External 1 gt Wakeup l J skp SNZI1 4
193. on execution address with the RT instruction and the BM instruction becomes the NOP instruction Fig 6 Example of operation at subroutine call 4513 4514 Group User s Manual 8 Program counter PC Program counter PC is used to specify a ROM address page and address It determines a sequence in which instructions stored in ROM are read It is a binary counter that increments the number of instruction bytes each time an instruction is executed However the value changes to a specified address when branch instructions subroutine call instructions return instructions or the table refer ence instruction TABP p is executed Program counter consists of PCH most significant bit to bit 7 which specifies to a ROM page and PCL bits 6 to 0 which speci fies an address within a page After it reaches the last address address 127 of a page it specifies address 0 of the next page Figure 7 Make sure that the PCH does not specify after the last page of the built in ROM 9 Data pointer DP Data pointer DP is used to specify a RAM address and consists of registers Z X and Y Register Z specifies a RAM file group reg ister X specifies a file and register Y specifies a RAM digit Figure 8 Register Y is also used to specify the port D bit position When using port D set the port D bit position to register Y certainly and execute the SD RD or SZD instruction Figure 9 4513 4514 Group User s Manual HARDWA
194. on from being affected by other signals 1 Keeping oscillator away from large current signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a current larger than the tolerance of current value flows Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance J Microcomputer Mutual inductance uu M current Ma Large GND Fig 3 4 8 Wiring for a large current signal line 2 Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise Reason Signal lines where potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer failure or a program runaway 3 27 APPENDIX 3 4 Notes on noise N G Do not cross Fig 3 4 9 Wiring to a signal line where potential levels change frequently 3 Oscillator protection using Vss pattern As f
195. or a two sided printed circuit board print a VSS pattern on the underside soldering side of the position on the component side where an oscillator is mounted Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring Besides separate this 55 pattern from other Vss patterns An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the Vss line for oscillation from other Vss lines Fig 3 4 10 Vss pattern on the underside of an oscillator 3 4 5 Setup for I O ports Setup ports using hardware and software as follows Hardware e Connect a resistor of 100 Q or more to an I O port in series Software As for an input port read data several times by a program for checking whether input levels are equal or not As for an output port or an I O port since the output data may reverse because of noise rewrite data to its output latch at fixed periods Rewrite data to pull up control registers at fixed periods 3 4 6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation This is equal to or more effective than program runaway detection by a hardware watchdog timer The following shows an example of a watchdog timer provided by software In the follow
196. ort and it can be used as inputs when the output latch is set to 1 The output structure is N channel open drain P10 P13 port Every pin of the ports has key on wakeup function and pull up function Both functions can be switched by software 20 22 Input port P2 3 bit input port Ports P20 P21 and P22 are also used as 5 SOUT and SIN re spectively port 4 bit I O port 2 bit I O port for the 4513 Group For input use set the latch of the specified bit to 1 The output structure is N channel open drain Ports P30 and P31 are also used as INTO and INT1 respectively The 4513 Group does not have ports P32 P33 40 port P4 4 bit I O port For input use set the latch of the specified bit to 1 The output Structure is N channel open drain Ports P40 P43 are also used as analog input pins AIN4 AINT respectively The 4513 Group does not have port P4 5 5 port P5 4 bit I O port Each pin has a direction register and an independent 1 bit wide I O function For input use set the direction register to 0 For output use set the di rection regiser to 1 The output structure is CMOS The 4513 Group does not have port P5 AINO AIN7 Analog input Analog input pins for A D converter AINO AIN3 are also used as voltage compara tor input pins and AIN4 AIN7 are also used as port The
197. ot executed and system reset occurs Specifications System clock frequency f XIN 4 0 MHz is used and program run away is detected by executing the WRST instruction in 24 ms Figure 2 3 2 shows the watchdog timer function and Figure 2 3 9 shows the example of watchdog timer FFFF16 Value of timer WDT 0000 16 pee WEF flag WDF1 flag WDF2 flag RESET pin output instruction instruction System reset execution execution Fig 2 3 2 Watchdog timer function 4513 4514 Group User s Manual 2 31 APPLICATION 2 3 Timers Disable Interrupts Timer 1 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI instruction b3 H Timer 1 interrupt occurrence disabled Interrupt control register 1 x o x x Q Stop Timer Operation Timer 1 and prescaler are temporarily stopped Dividing ratio of prescaler is selected b0 b3 TW1A Timer control register W1 o 1 0 E A instruction Prescaler divided by 16 selected Set Timer Value Timer 1 count time is set The formula is shown below Timer 1 reload register R1 F916 Timer count value 249 set T1AB instruction Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 instruction Note when the interrupt request is cleared When is execu
198. ow to use the external 1 interrupt is as follows Select the valid waveform with the bits 1 and 2 of register 12 Q Clear the EXF1 flag to 0 with the SNZ1 instruction 9 Set the NOP instruction for the case when skip is performed with the SNZ1 instruction Set both the external 1 interrupt enable bit V11 and the INTE flag to 1 The external 1 interrupt is now enabled Now when a valid wave form is input to the P31 INT1 pin the EXF1 flag is set to 1 and the external 1 interrupt occurs 1 27 HARDWARE FUNCTION BLOCK OPERATIONS 3 External interrupt control registers Interrupt control register 11 Register 1 controls the valid waveform for the external 0 inter rupt Set the contents of this register through register A with the instruction The instruction can be used to transfer the contents of register 11 to register A Table 8 External interrupt control registers Interrupt control register 11 at reset 00002 Interrupt control register I2 Register 12 controls the valid waveform for the external 1 inter rupt Set the contents of this register through register A with the TI2A instruction The TAI2 instruction can be used to transfer the contents of register 12 to register A at RAM back up state retained Not used This bit has no function but read write is enabled Interrupt valid waveform for INTO pin Falling waveform 417 level of INTO pin is recogni
199. owing processes In order to im prove reliability after writing performing writing and test according to the flow shown in Figure 52 before using is recom mended Products shipped in blank PROM contents is not written in factory when shipped 4513 4514 Group User s Manual HARDWARE BUILT IN PROM VERSIONS Table 26 Programming adapters Microcomputer M34513E4SP M34513E4FP M34513E8FP M34514E8FP Programming adapter PCA7442SP PCA7442FP PCA7441 Ds De Di Do Low order 5 bits Ds De Di Do High order 5 bits Note Since the screening temperature is higher than storage temperature never expose the microcomputer to 150 C exceeding 100 hours Fig 52 Flow of writing and test of the product shipped in blank 1 89 HARDWARE BUILT IN PROM VERSION 1 90 4513 4514 Group User s Manual CHAPTER 2 APPLICATION 2 1 I O pins 2 2 Interrupts 2 3 Timers 2 4 Serial 2 5 A D converter 2 6 Voltage comparator 2 7 Reset 2 8 Voltage drop detection circuit 2 9 RAM back up 2 10 Oscillation circuit APPLICATION 2 1 I O pins 2 1 I O pins The 4513 4514 Group has the twenty eight I O pins eighteen I O pins for 4513 Group three input pins Ports 20 22 P30 P31 De and D7 are also used as serial I O pins SCK SOUT SIN and INTO INT1 CNTRO 1 pins respectively This section describes each port I O funct
200. ows the example of operation at subroutine call 6 Interrupt stack register SDP Interrupt stack register SDP is a 1 stage register When an inter rupt occurs this register SDP is used to temporarily store the contents of data pointer carry flag skip flag register A and regis ter B just before an interrupt until returning to the original routine Unlike the stack registers SKs this register SDP is not used when executing the subroutine call instruction and the table refer ence instruction 7 Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions When an interrupt oc curs the contents of skip flag is stored automatically in the interrupt stack register SDP and the skip condition is retained Program counter PC Executing BM instruction Executing RT instruction v ll oil ll 0 1 2 3 4 5 6 7 Stack pointer SP points 7 at reset or returning from RAM back up mode It points 0 by executing the first BM instruction and the contents of program counter is stored in SKo When the BM instruction is executed after eight stack registers are used SP 7 SP 0 and the contents of SKo is destroyed Fig 5 Stack registers SKs structure SP 0 SKo lt 000116 SUB1 Main program Subroutine Address 000016 000116 BM SUB1 000216 NOP Note Returning to the BM instructi
201. parison voltage When the analog input voltage is lower than the comparison voltage the ADF flag is set to 1 The state of ADF flag can be examined with the skip instruction SNZAD Use the interrupt control register V2 to select the inter rupt or the skip instruction The ADF flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction 13 Comparator operation start instruction ADST instruction In comparator mode executing ADST starts the comparator oper ating The comparator stops 8 machine cycles after it has started 6 us at 4 0 MHz in high speed mode When the analog input volt age is lower than the comparison voltage the ADF flag is set to 1 14 Notes for the use of A D conversion 1 Note the following when using the analog input pins also for I O port P4 functions Even when P40 AIN4 P43 AIN7 are set to pins for analog input they continue to function as P40 P43 I O Accordingly when any of them are used as I O port P4 and others used as analog input pins make sure to set the outputs of pins that are set for analog input to 1 Also the port input function of the pin func tions as an analog input is undefined TALA instruction When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A si multaneously the low order 2 bits of register A is 0 46 2
202. porarily disabled is enabled b3 b0 8 Interrupt control register V2 Wedron e enable Interrupt enable flag INTE 4 All interrupts enabled El instruction Constant period interrupt execution start prescaler dividing ratio time 3 count value and timer 4 count value to make the interrupt occur every 250 ms are set as follows 250 ms 4 0 MHz x 16 X 82 1 249 1 System clock Instruction Prescaler Timer3 Timer 4 clock dividing count count ratio value value X it can be 0 or 1 Fig 2 2 8 Timer 4 constant period interrupt setting example 2 24 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts 2 2 4 Notes on use 1 2 3 4 5 6 7 Setting of INTO interrupt valid waveform Depending on the input state of P30 INTO pin the external interrupt request flag EXFO may be set to 1 when the interrupt valid waveform is changed Accordingly set a value to the bit 2 of register 11 and execute the SNZO instruction to clear the EXFO flag to 0 after executing at least one instruction Setting of INT1 interrupt valid waveform Depending on the input state of P31 INT1 pin the external interrupt request flag EXF1 may be set to 1 when the interrupt valid waveform is changed Accordingly set a value to the bit 2 of register 12 and execute the SNZ1 instruction to clear the EXF1 flag to 0 after executing at least one instruction Mul
203. register PUO Pull up control register PUO controls the pull up functions of ports POo P03 10 13 Set the contents of this register through register A with the TPUOA instruction The TAPUO instruction can be used to transfer the contents of register PUO to register A Table 2 9 5 shows the pull up control register PUO Table 2 9 5 Pull up control register PUO at reset 00002 at RAM back up state retained 0 Pull up transistor OFF 1 Pull up transistor 0 Pull up transistor OFF 1 Pull up transistor ON 0 Pull up transistor OFF 1 0 R W Pull up control register PUO Pins P12 and P13 pull up transistor control bit Pins and P11 pull up transistor control bit Pins and pull up transistor control bit Pins 0 and 1 pull up transistor control bit PUOS PU02 Pull up transistor Pull up transistor OFF Pull up transistor ON Note R represents read enabled and W represents write enabled PUOo 3 Interrupt control register 11 The interrupt valid waveform for INTO pin return level selection bit is assigned to bit 2 INTO pin edge detection circuit control bit is assigned to bit 1 and INTO pin timer 1 control enable bit is assigned to bit 0 Set the contents of this register through register A with the TI1A instruction In addition the instruction can be used to transfer the contents of register 11 to register
204. register Y description When the LXY instructions are continuously coded and executed only the first LXY instruction is executed and other LXY instructions coded continuously are skipped Loads the value z in the immediate field to register Z Adds 1 to the contents of register Y As a result of addition when the contents of register Y is 0 the next struction is skipped Subtracts 1 from the contents of register Y As a result of subtraction when the contents of register Y is 15 the next instruction is skipped After transferring the contents of M DP to register A an exclusive OR operation is performed between reg ister X and the value j in the immediate field and stores the result in register X After exchanging the contents of M DP with the contents of register A an exclusive OR operation is per formed between register X and the value j in the immediate field and stores the result in register X After exchanging the contents of M DP with the contents of register A an exclusive OR operation is per formed between register X and the value j in the immediate field and stores the result in register X Subtracts 1 from the contents of register Y As a result of subtraction when the contents of register Y is 15 the next instruction is skipped After exchanging the contents of M DP with the contents of register A an exclusive OR operation is per formed between register X and the value j in the immediate field and stores t
205. rily stopped Dividing ratio of prescaler is selected o Fi Timer 1 stop TW1A instruction Timer control register W1 x Prescaler stop Prescaler divided by 16 selected Set Timer Value Timer 1 count time is set The formula is shown below Timer 1 reload register R1 5216 Timer count value 82 set T1AB instruction Clear Interrupt Request Timer 1 interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condition cleared SNZT1 instruction Note when the interrupt request is cleared When is executed considering the skip of the next instruction according to the interrupt request flag T1F insert the NOP instruction after the SNZT1 instruction Start Timer Operation Timer 1 and prescaler temporarily stopped are restarted b3 bo Timer 1 operation start TW1A instruction Timer control register W1 i Enable Interrupts The Timer 1 interrupt which is temporarily aisabled is enabled Interrupt control register V1 FEE Viki m enabled Interrupt enable flag INTE 1 All interrupts enabled El instruction Constant period interrupt execution start RA The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1 ms are set as follows 1 ms 4 0 MHzJ X 3 X 16 824 System clock Instruction Prescaler Timer 1 clock dividing count ratio value X it can be 0 or
206. roup and should be able to fully utilize the product The manual starts with specifications and ends with application examples In this manual the 4514 Group is mainly described The differences from the 4513 Group are described at the related points BEFORE USING THIS USER S MANUAL This user s manual consists of the following three chapters Refer to the chapter appropriate to your conditions such as hardware design or software development 1 Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions based mainly on setting examples of related registers CHAPTER 3 APPENDIX This chapter includes precautions for systems development using the microcomputer the mask ROM confirmation forms mask ROM version and mark specification forms which are to be submitted when ordering Be sure to refer to this chapter because this chapter also includes necessary information for systems development Note In this manual the 4514 Group is mainly described The differences from the 4513 Group are described at the related points Table of contents Table of contents CHAPTER 1 HARDWARE PIN CONFIGURATION c EHE EUN tele pO UR UMEN e pm PROGRAM MEMOY ROM HW m o
207. routine every 20 ms Reset Flag WDF Watchdog timer flag is reset Watchdog timer flag WDF1 cleared WRST instruction Main routine execution Do not clear watchdog timer WDF flag in interrupt service routine Interrupt may be executed even if program run away occurs When going to RAM back up mod WRST WDF flag cleared EPOF POF instruction enabled POF Oscillation stop RAM back up mode In the RAM back up mode WEF WDF1 and WDF2 flags are initialized However when WDF2 flag is set to 1 at the same time system enters RAM back up mode microcomputer may be reset When watchdog timer and RAM back up mode are used execute the WRST instruction before system enters the RAM back up mode to initialize WDF flag X it can be 0 or 1 Fig 2 3 9 Watchdog timer setting example 2 38 4513 4514 Group User s Manual APPLICATION 2 3 Timers 2 3 4 Notes on use 1 Prescaler Stop the prescaler operation to change its frequency dividing ratio 2 Count source Stop timer 1 2 3 or 4 counting to change its count source 3 Reading the count values Stop timer 1 2 3 or 4 counting and then execute the TAB1 2 or TAB4 instruction to read its data 4 Writing to reload registers R1 R3 When writing data to reload registers R1 R3 while timer 1 and 3 are operating avoid a timing when timers 1 and 3 underflow 4513 4514 Group User s Manual 2 39 APPLICATION 2
208. rror 2LSB analog voltages input from the analog input pin with preset val Non linearity error 0 9LSB ues Conversion speed 46 5 us High speed mode at 4 0 MHz oscillation frequency Analog input pin 4 for 4513 Group 8 for 4514 Group Register B 4 Register A 4 TAQ1 IAP4 P40 P43 Y Q11 ai Note 3 AiNo CMPO O Ain1 CMP0 O Ain2 CMP1 O Ain3 CMP1 O P40 AIN4 41 5 P42 AIN6 P43 AIN7 gt A D interrupt Successive comparison register AD 10 operation signal 8 channel multi plexed analog switch DA converter Comparator register 8 J Notes 1 This switch is turned ON only when A D converter is operating and generates the comparison voltage 2 Writing reading data to the comparator register is possible only in the comparator mode Q23 1 The value of the comparator register is retained even when the mode is switched to the A D conversion mode Q23 0 because it is separated from the successive comparison register AD Also the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits 3 The 4513 Group does not have ports P40 AIN4 P43 AIN7 and the IAP4 and instructions Fig 26 A D conversion circuit structure 4513 4514 Group User s Manual 1 41 HARDWARE FUNCTION BLOCK
209. rrupt enable flag INTE INTE flag is cleared to 0 so that interrupts are disabled Interrupt request flag Only the request flag for the current interrupt source is cleared to 0 Data pointer carry flag skip flag registers and The contents of these registers and flags are stored automati cally in the interrupt stack register SDP 5 Interrupt processing When an interrupt occurs a program at an interrupt address is ex ecuted after branching a data store sequence to stack register Write the branch instruction to an interrupt service routine at an in terrupt address Use the RTI instruction to return from an interrupt service routine Interrupt enabled by executing the EI instruction is performed after executing 1 instruction just after the next instruction is executed Accordingly when the EI instruction is executed just before the RTI instruction interrupts are enabled after returning the main routine Refer to Figure 13 Main routine Interrupt service routine Interrupt occurs Interrupt is enabled Interrupt enabled state Interrupt disabled state Fig 13 Program example of interrupt processing 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS Program counter Each interrupt address The address of main routine to be executed when returning Interrupt enable flag INTE 0 Interrupt disabled Inte
210. rrupt occurs every 1 ms Figure 2 2 7 shows a setting example of the timer 3 constant period interrupt 4513 4514 Group User s Manual APPLICATION 2 2 Interrupts 6 Timer 4 interrupt Constant period interrupts by a setting value to timer 4 can be used Outline The constant period interrupts by the timer 4 underflow signal can be used Specifications Prescaler timer 3 and timer 4 divide the system clock frequency f XIN 4 0 MHz and the timer 4 interrupt occurs every 250 ms Figure 2 2 8 shows a setting example of the timer 4 constant period interrupt H PSo INTO P3o INTO 1 An interrupt occurs after the valid waveform falling is detected 4 An interrupt occurs after the valid waveform rising is detected Fig 2 2 1 INTO interrupt operation example 4513 4514 Group User s Manual 2 17 APPLICATION 2 2 Interrupts D Disable Interrupts INTO interrupt is temporarily disabled Interrupt enable flag INTE bs All interrupts disabled DI instruction interrupt occurrence disabled Interrupt control register V1 E TV1A instruction Q Set Port Port used for INTO interrupt is set to input port Port P30 output latch Set to input OP3A instruction Set Valid Waveform Valid waveform of INT pin is selected Both edges detection selected Interrupt control register 11 X Beth edges detection selected TI1A instruction Clear Interrupt Request External interrupt activated co
211. rrupt request flag only the flag for the current interrupt source 0 Data pointer carry flag registers A and skip flag Stored in the interrupt stack register SDP automatically Fig 14 Internal state when interrupt occurs INTO pin Address 0 LOH or in page 1 HL input INT1 pin Address 2 in page 1 LH or HL input Address 4 in page 1 Timer 1 underflow Address 6 in page 1 Timer 2 underflow Address 8 in page 1 Timer 3 underflow Address A in page 1 Timer 4 underflow Address C in page 1 Completion of A D conversion Address E in page 1 Completion of serial I O transfer SIOF Activated condition Request flag Enable Enable state retained bit flag Fig 15 Interrupt system diagram 1 23 HARDWARE FUNCTION BLOCK OPERATIONS 6 Interrupt control registers Interrupt control register V1 Interrupt enable bits of external 0 external 1 timer 1 and timer 2 are assigned to register V1 Set the contents of this register through register A with the instruction The TAV1 instruction can be used to transfer the contents of register V1 to register A Table 6 Interrupt control registers Interrupt control register V2 Interrupt enable bits of timer 3 timer 4 A D and serial are as signed to register V2 Set the contents of this register through register A with the TV2A instruction The TAV2
212. rt PO to register A Outputs the contents of register A to port PO Transfers the input of port P1 to register A Outputs the contents of register A to port P1 Transfers the input of port P2 to register A Transfers the input of port P3 to register A Outputs the contents of register A to port P3 Transfers the input of port P4 to register A Outputs the contents of register A to port P4 Transfers the input of port P5 to register A Outputs the contents of register A to port P5 Sets 1 to port D Clears 0 to a bit of port D specified by register Y Sets 1 to a bit of port D specified by register Y Skips the next instruction when bit of port D specified by register Y is 0 Transfers the contents of register A to key on wakeup control register KO Transfers the contents of key on wakeup control register KO to register A Transfers the contents of register A to pull up control register PUO Transfers the contents of pull up control register PUO to register A Transfers the contents of register A to direction register FRO 4513 4514 Group User s Manual 1 81 HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS continued Parameter Instruction code Mnemonic Function Hexadecimal Number of Number of cycles Ds D7 De Ds D4 D3 Di instructions notation 278 lt 5 lt 517 514 513 510 lt 517 514 B lt J1
213. ructions notation 03A k 112 1 INTO H 2 112 0 INTO L 122 1 INT1 H 2 122 0 INT1 L lt V1 V1 lt Interrupt operation A V2 V2 lt A lt 11 11 lt lt 12 12 lt lt W1 W1 lt lt W2 W2 lt lt W3 W3 lt Timer operation lt W4 W4 lt lt W6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 oo O O OG O UO O o cc O W6 lt 1 76 4513 4514 Group User s Manual Skip condition HARDWARE MACHINE INSTRUCTIONS Datailed description INTO H However 112 1 INTO L However 112 0 INT1 H However 122 1 INT1 L However 122 0 When bit 2 112 of register 11 is 1 Skips the next instruction when the level of INTO pin is H When bit 2 112 of register 1 is 0 Skips the next instruction when the level of INTO pin is L When bit 2 122 of register 12 is 1 Skips the next instruction when the level of INT1 pin is H When bit 2 122 of register 12 is 0 Skips the next instruction when the level of INT1 pin is L Transfers the contents of interrupt control register V1 to register A Transfers the contents of register A to interrupt control regist
214. rupt enabled SNZT1 instruction is invalid 0 Interrupt disabled SNZ1 instruction is valid 1 0 Interrupt control register V1 V13 2 interrupt enable bit Vi2 1 interrupt enable bit 11 External 1 interrupt enable bit P Interrupt enabled SNZ1 instruction is invalid Interrupt disabled SNZO instruction is valid 1 Interrupt enabled SNZO instruction is invalid Note R represents read enabled and W represents write enabled Vio External 0 interrupt enable bit 3 Interrupt control register V2 Interrupt enable bits of timer timer 4 A D and serial I O are assigned to register V2 Set the contents of this register through register A with the TV2A instruction In addition the TAV2 instruction can be used to transfer the contents of register V2 to register A Table 2 2 2 Interrupt control register V2 Table 2 2 2 shows the interrupt control register V2 at reset 00002 at RAM back up 00002 Interrupt disabled SNZSI instruction is valid Interrupt enabled SNZSI instruction is invalid Interrupt disabled SNZAD instruction is valid Interrupt enabled SNZAD instruction is invalid Interrupt disabled SNZTA instruction is valid Interrupt enabled SNZTA instruction is invalid Interrupt disabled SNZT3 instruction is valid 1 Interrupt enabled SNZTS instruction is invalid Interrupt control register V2 V23 Serial I O interrupt ena
215. s Other operation 4513 4514 Group User s Manual PC PO 1 RAM back up POF instruction valid P 21 WDF1 lt 0 WEF lt 1 lt MR lt lt Q3 Q32 lt A2 Q31 CMP1 com parison result Q30 com parison result 1 65 HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE for 4513 Group 0100000011000 000000 000001000010000011 000100 000101 000110 000111 001000 001001 001010001011 001100 001101 001110 001111 notation 00 BML BML BML BML BML BML BML BML BML BML gt gt gt 1 gt gt gt gt gt gt gt gt BML gt BML gt BML gt BML 99 BML d SS BML The above table shows the relationship between machine language codes and machine language instructions D3 Do show the low order 4 bits of the machine language code and 09 04 show the high order 6 bits of the machine language code The hexadecimal representa tion of the code is also provided There are one word instructions and two word instructions but only the first word of each instruction is shown Do not use code marked The codes for the second
216. s P10 and P11 key on wakeup control bit Key on wakeup not used Key on wakeup used Pins P02 and P03 key on wakeup control bit Key on wakeup not used Key on wakeup used Pins POo and P01 key on wakeup control bit Pull up control register PUO Key on wakeup not used 9 gt 9 00002 at RAM back up state retained Pins P12 and P13 pull up transistor control bit Pull up transistor O FF Pull up transistor O N Pins P10 and P11 pull up transistor control bit Pull up transistor O FF Pull up transistor O N Pins P02 and pull up transistor control bit Pull up transistor O FF Pull up transistor O N Pins 0 and P01 pull up transistor control bit Direction register FRO Note 2 Pull up transistor O FF 9 gt 9 9 Pull up transistor at reset 00002 N at RAM back up state retained Port P53 input output control bit Port P53 input Port P53 output Port P52 input output control bit Port P52 input Port P52 output Port P51 input output control bit Port P50 input output control bit Port P51 input Port P51 output Port P50 input Port P50 output Notes 1 R represents read enabled and W represents write enabled 2 The 4513 Group does not have the direction register FRO 451
217. s executed Notes 1 Repeat steps through to transmit or receive multiple data in succession 2 For the program on the master side make sure that transmission is not started before the control signal is released back after a transmit operation is started first 4513 4514 Group User s Manual APPLICATION 2 4 Serial I O 2 Transmit receive operation of slave The transmit data is written into the serial I O register SI with the TSIAB instruction When the TSIAB instruction is executed the contents of register A are transferred to the low order bits of register SI and the contents of register are transferred to the high order bits of register SI At this time the SCK pin must be at the H level Q Serial transfer is started with the SST instruction However in Figure 2 4 2 where an external clock is selected transfer is not started until the clock is input When the SST instruction is executed the serial I O transmit receive completion flag SIOF is cleared to 0 The microcomputer on the transmitting side is informed that the receiving side is ready to receive In the connection example in Figure 2 4 2 this notification is done by pulling the control signal L level The transmit data is output from the SOUT pin synchronously with the falling edges of the shift clock The transmit data is output bit by bit beginning with the LSB bit of register SI Each time one bit is output
218. sed by noise Note when connecting to Vss and VDD Connect the unused pins to Vss and VDD using the thickest wire at the shortest distance against noise 4513 4514 Group User s Manual HARDWARE PIN DESCRIPTION PORT FUNCTION Port Pin Control instructions Output structure Control registers Port D 05 De CNTRO D7 CNTR1 SD RD SZD CLD N channel open drain W6 Port PO P00 P03 IAPO N channel open drain Built in programmable pull up functions Key on wakeup functions programmable PortP1 10 1 OP1A IAP 1 N channel open drain Built in programmable pull up functions Key on wakeup functions programmable P20 SCK P21 SoUT P22 SIN P30 INTO P31 INT1 P32 P33 N channel open drain Built in key on wakeup function P30 INTO P31 INT1 P40 AIN4 P43 AIN7 N channel open drain 5 5 CMOS Notes 1 The 4513 Group does not have P32 and P33 2 The 4513 Group does not have these ports DEFINITION OF CLOCK AND CYCLE System clock The system clock is the basic clock for controlling this product The system clock is selected by the bit 3 of the clock control reg ister MR Table Selection of system clock Register MR System clock f XIN Instruction clock f XIN 2 Note f XIN 2 is selected after system is released from reset The instruction clock is a signal d
219. shi IC catalog name Mitsubishi lot number 6 digit or 7 digit UUUUUUUUUUUUUUUI Note1 The mark field should be written right aligned 2 The fonts and size of characters are standard Mitsubishi type 3 Customers Parts Number be up to 16 characters Only 0 9 A 2 amp periods and commas are usable 4 If the Mitsubishi logo is not required check the box on the right Mitsubishi logo is not required C Special Mark Required G2 ACANA A AAAA UUUUUUUUUUUUUUUI Note1 If the Special Mark is to be Printed indicate the desired layout of the mark in the upper figure The layout will be duplicated as close as possible Mitsubishi lot number 6 digit or 7 digit and Mask ROM number 3 digit are always marked 2 If the customer s trade mark logo must be used in the Special Mark check the box on the right Please submit a clean original of the logo For the new special Special logo required character fonts a clean font original ideally logo drawing must be submitted 3 The standard Mitsubishi font is used for all characters except for a logo 3 36 4513 4514 Group User s Manual APPENDIX 3 6 Mark specification form A Standard Mitsubishi Mark 32P6B 32 PIN
220. sidering the skip of the next instruction according to the interrupt request flag T3F insert the NOP instruction after the SNZT3 instruction Start Timer 3 Operation Timer 3 and prescaler temporarily stopped are restarted b3 bo Timer control register W3 1 X 0 1 Timer operation start TW3A instruction b3 bo Timer control register W1 Prescaler operation start TW1A instruction Enable Interrupts The timer 3 interrupt which is temporarily disabled is enabled Tim nterr n nabl Interrupt control register V2 x ven in Interrupt enable flag INTE 1 M interrupts enabled El instruction Constant period interrupt execution start The prescaler dividing ratio and time count value to make the interrupt occur every 1 ms are set as follows imss 40MHzj X 3 16 82 1 System clock Instruction Prescaler Tim Timer 3 clock dividing count ratio value X it can be 0 or 1 Fig 2 2 7 Timer 3 constant period interrupt setting example 4513 4514 Group User s Manual 2 23 APPLICATION 2 2 Interrupts Disable Interrupts Timer 4 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI instruction B 50 Timer 4 interrupt occurrence disabled Interrupt control register V2 x x o X TV2A instruction Q Stop Timer Operation Timer 4 timer 3 and prescaler are temporarily stopped Dividing ratio of prescaler is sel
221. ss capacitor to the Vss pin and the VDD pin Fig 3 4 6 Bypass capacitor across the Vss line and the Vpp line 4513 4514 Group User s Manual 3 4 3 Wiring to analog input pins Connect an approximately 100 Q to 1 resistor to an analog signal line which is connected to an analog input pin in series Besides connect the resistor to the microcomputer as close as possible Connect an approximately 1000 pF capacitor across the Vss and the analog input pin Besides connect the capacitor to the Vss pin as close as possible Also connect the capacitor across the analog input and the Vss pin at equal length Reason Signals which is input in an analog input pin such as A D converter comparator input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog input pin is longer necessarily This long wiring functions as an antenna which feeds noise into the microcomputer which causes noise to an analog input pin Note Microcomputer Analog Thermistor input pin Note The resistor is used for dividing resistance with a thermistor Fig 3 4 7 Analog signal line and a resistor and a capacitor 4513 4514 Group User s Manual APPENDIX 3 4 Notes on noise 3 4 4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operati
222. ss A in page 1 Address C in page 1 Address E in page 1 Interrupt name Activated condition External 0 interrupt Level change of INTO pin Level change of INT1 pin Timer 1 underflow External 1 interrupt Timer 1 interrupt Timer 2 underflow Timer 2 interrupt Timer 3 interrupt Timer 3 underflow Timer 4 interrupt Timer 4 underflow A D interrupt Completion of A D conversion Completion of serial 1 transfer Serial I O interrupt Table 4 Interrupt request flag interrupt enable bit and skip in struction Interrupt name External 0 interrupt EXFO External 1 interrupt EXF1 Timer 1 interrupt Timer 2 interrupt T2F Timer 3 interrupt T3F Timer 4 interrupt T4F A D interrupt ADF Serial interrupt SIOF Request flag Skip instruction Enable bit SNZO V10 SNZ1 V11 SNZT1 V12 SNZT2 V13 SNZT3 V20 SNZT4 V21 SNZAD V22 SNZSI V23 Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Skip instruction 1 Enabled Invalid 0 Disabled Valid 4513 4514 Group User s Manual 4 Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows Figure 14 Program counter PC An interrupt address is set in program counter The address to be executed when returning to the main routine is automatically stored in the stack register SK Inte
223. ster 4 1 0 0 Timer 4 operation start instruction Enable Interrupts Interrupt enable flag INTE 1 All interrupts enabled El instruction X it can be 0 or 1 Fig 2 3 6 CNTRO output control setting example 4513 4514 Group User s Manual 2 35 APPLICATION 2 3 Timers Disable Interrupts Timer 1 interrupt is temporarily disabled Interrupt enable flag INTE 0 All interrupts disabled DI instruction b3 b0 Interrupt control register 1 0 Timer 1 interrupt occurrence disabled TV1A instruction INTO interrupt occurrence disabled Q Stop Timer Operation Timer 1 and prescaler are temporarily stopped Dividing ratio of prescaler is selected b3 bo gt Timer control register W1 0 0 0 instruction Prescaler divided by 4 selected Set Timer Value Timer 1 count time is set Timer 1 reload register R1 5216 Timer count value 82 set T1AB instruction Set Port P30 INTO pin is set to INTO input b3 Port P30 output latch INTO input set OP3A instruction Set Valid Waveform Valid waveform of INTO pin is selected Timer 1 control is enabled b3 50 Interrupt control register 11 x 1 o 1 Rising edge detected TI1A instruction Clear Interrupt Request Timer 1 interrupt activated condition is cleared INTO interrupt activated condition is cleared Timer 1 interrupt request flag T1F 0 Timer 1 interrupt activated condit
224. struction In addition the TAPUO instruction can be used to transfer the contents of register PUO to register A Table 21 Return source and return condition Return source Return condition Remarks Ports PO P1 Return by an external falling Set the port using the key on wakeup function selected with register KO to edge input H L level before going into the RAM back up state because the port shares the falling edge detection circuit with port P1 Port P30 INTO Return by an external H level or Select the return level L level or H level with the bit 2 of register 1 ac L level input cording to the external state before going into the RAM back up state The EXFO flag is not set Port P31 INT1 Return by an external H level or Select the return level L level or H level with the bit 2 of register I2 ac L level input cording to the external state before going into the RAM back up state The EXF1 flag is not set 3 5 o x 1 54 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS POF instruction B is executed Stabilizing time stop f XiN oscillation Return input RAM back up Stabilizing time mode Stabilizing time Time required to stabilize the oscillation is automatically generated by hardware Fig 38 State transition Power down flag P POF instruct
225. synchronous circuit selected Count source Timer 2 underflow signal Timer 3 count source selection bits Timer control register W4 Prescaler output Not available Not available reset 00002 at RAM back up state retained Timer 4 control bit 0 1 0 Stop state retained Operating W42 Not used 1 This bit has no function but read write is enabled Count source Timer 3 underflow signal Timer 4 count source selection bits Prescaler output Timer control register W6 1 output control bit 1 input Not available reset 00002 at RAM back up state retained R W Timer 3 underflow signal output divided by 2 1 output control by timer 4 underflow signal divided by 2 D7 CNTR1 function selection bit D7 I O CNTR1 input CNTR1 l O D7 input Timer 1 underflow signal output divided by 2 CNTRO output control bit output control by timer 2 underflow signal divided by 2 De CNTRO output control bit o joj 2jo j 2 o Note R represents read enabled and W represents write enabled 4513 4514 Group User s Manual De l OJ CNTRO input CNTRO l O De input 1 85 HARDWARE CONTROL REGISTERS Serial I O mode register J1 at reset 00002 at RAM back up state retained Not used This bit has no function but read write is enabled Serial internal clock dividing ratio Instruction clock
226. t is Vref gt VIN it is cleared to 0 HARDWARE FUNCTION BLOCK OPERATIONS The 4513 4514 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value A D conversion stops after 62 machine cycles 46 5 us when f XIN 4 0 MHz in high speed mode from the start and the conversion re sult is stored in the register AD An A D interrupt activated condition is satisfied and the ADF flag is set to 1 as soon as A D conversion completes Figure 27 Table 16 Change of successive comparison register AD during A D conversion At starting conversion C Comparison voltage Vref value hange of successive comparison register AD 1st comparison 0 0 2nd comparison 2 After 10th comparison A D conversion result completes 2 3 3 amp 1 1st comparison result 353 3rd comparison result 9 9th comparison result 2 2nd comparison result x8 8th comparison result xA 10th comparison result 4513 4514 Group User s Manual 1 43 HARDWARE FUNCTION BLOCK OPERATIONS 8 A D conversion timing chart Figure 27 shows the A D conversion timing chart ADST instruction 62 machine cycles A D conversion completion flag ADF DAC operation signal Fig 27 A D conversion timing chart 9 How
227. t latch is set to 1 2 Pull up transistor is turned OFF 3 After system is released from reset port is in the input mode Direction register FRO 00002 4 The 4513 Group does not have these ports High impedance Note High impedance Notes 1 2 High impedance Note 1 1 50 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS Program counter Address 0 in page 0 is set to program counter Interrupt enable flag INTE Interrupt disabled Power down flag P External 0 interrupt request flag EXFO External 1 interrupt request flag EXF1 Interrupt control register V1 0 Interrupt disabled Interrupt control register V2 0 0 Interrupt disabled Interrupt control register 11 Interrupt control register 12 Timer 1 interrupt request flag T1F Timer 2 interrupt request flag T2F Timer 3 interrupt request flag T3F Timer 4 interrupt request Watchdog timer flags WDF1 WDF2 Watchdog timer enable flag WEF Timer control register W1 jm Prescaler and timer 1 stopped Timer control register W2 Timer 2 stopped Timer control register W3 0 0 Timer 3 stopped Timer control register W4 Timer 4 stopped Timer control register W6 Clock control register MR Seria
228. ted considering the skip of the next instruction according to the interrupt request flag insert the NOP instruction after the SNZT1 instruction G Start Timer 1 Operation Timer 1 and prescaler temporarily stopped are restarted b3 bo _ Timer control register W1 E 7 instruction Enable Interrupts The timer 1 interrupt which is temporarily disabled is enabled b3 E Interrupt control register V1 via enabled Interrupt enable flag INTE 4 All interrupts enabled El instruction Constant period interrupt execution start The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 4 ms are set as follows 4ms 4 0MHz X 3 X 16 X 24941 System clock Instruction Prescaler Timer 1 clock dividing count ratio value X it can be 0 or 1 Fig 2 3 3 Constant period measurement setting example 2 32 4513 4514 Group User s Manual APPLICATION 2 3 Timers Disable Interrupts Timer 1 interrupt is temporarily disabled Interrupt enable flag INTE All interrupts disabled DI instruction Timer 1 interrupt occurrence disabled Interrupt control register V1 XI instruction Q Stop Timer Operation Timer 1 and prescaler are temporarily stopped Dividing ratio of prescaler is selected TW1A Timer control register W1 instruction Prescaler divided by 4 selected Set Timer Value Select CNTRO Output CNTRO output
229. ted by bit 2 of register 11 112 0 Falling waveform e 112 1 Rising waveform Timer 3 count start synchronous circuit function is selected by set ting the bit 2 of register W3 to 1 The control by P31 INT1 pin input can be performed by setting the bit 0 of register I2 to 1 The count start synchronous circuit is set by level change H L or L H of P31 INT1 pin input This valid waveform is selected by bits 1 121 and 2 122 of register I2 as follows 121 0 Synchronized with one sided edge falling or rising 121 1 Synchronized with both edges both falling and rising When register 121 0 synchronized with the one sided edge the ris ing or falling waveform can be selected by bit 2 of register I2 122 0 Falling waveform 122 1 Rising waveform When timer 1 and timer 3 count start synchronous circuits are used the count start synchronous circuits are set the count source is input to each timer by inputting valid waveform to P30 INTO pin and P31 INT1 pin Once set the count start synchronous circuit is cleared by clearing the bit 110 or 120 to 0 or reset 4513 4514 Group User s Manual WATCHDOG TIMER Watchdog timer provides a method to reset the system when a pro gram runs wild Watchdog timer consists of a 16 bit timer WDT watchdog timer enable flag WEF and watchdog timer flags WDF1 WDF2 The timer WDT downcounts the instruction cl
230. ter Q1 Register Q1 is used to select one of analog input pins The 4513 Group does not have AIN4 AIN7 Accordingly do not select these pins with register Q1 6 A D control register Q2 Register Q2 is used to select the pin function of P40 AlN4 P41 5 42 and P43 AIN7 A D conversion mode is se lected when the bit 3 of register Q2 is 0 and the comparator mode is selected when the bit 3 of register Q2 is 1 After set this register select the analog input with register Q1 Even when register Q2 is used to set the pins for analog input P40 AIN4 P43 AIN7 continue to function as P40 P43 I O Accord ingly when any of them are used as port P4 and others are used as analog input pins make sure to set the outputs of pins that are set for analog input to 1 Also for the port input the port input function of the pin functions as analog input is undefined 4513 4514 Group User s Manual 7 Operation description A D conversion is started with the A D conversion start instruction ADST The internal operation during A D conversion is as follows When A D conversion starts the register is cleared to 00016 Next the topmost bit of the register AD is set to 1 and the comparison voltage Vref is compared with the analog input volt age VIN When the comparison result is Vref lt VIN the topmost bit of the register AD remains set to 1 When the comparison resul
231. terrupt occurs the interrupt processing is executed from address E in page 1 When the interrupt is not used The interrupt is disabled and the SNZSI instruction is valid when the bit 3 of register V2 is set to 0 2 2 2 Related registers 1 Interrupt enable flag INTE The interrupt enable flag INTE controls whether the every interrupt enable disable Interrupts are enabled when INTE flag is set to 1 with the El instruction and disabled when INTE flag is cleared to 0 with the DI instruction When any interrupt occurs the INTE flag is automatically cleared to 0 so that other interrupts are disabled until the El instruction is executed Note The interrupt enabled with the El instruction is performed after the El instruction and one more instruction 4513 4514 Group User s Manual 2 13 APPLICATION 2 2 Interrupts 2 Interrupt control register V1 Interrupt enable bits of external 0 external 1 timer 1 and timer 2 are assigned to register V1 Set the contents of this register through register A with the TV1A instruction In addition the TAV1 instruction can be used to transfer the contents of register V1 to register A Table 2 2 1 Interrupt control register V1 Table 2 2 1 shows the interrupt control register V1 at reset 00002 at RAM back up 00002 0 Interrupt disabled SNZT2 instruction is valid 1 Interrupt enabled SNZT2 instruction is invalid 0 Interrupt disabled SNZT1 instruction is valid 1 Inter
232. that system cannot enter the RAM back up state when executing only the POF instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction 3 Return from RAM back up After system returns from RAM back up set the undefined registers and flags Especially be sure to set data pointer registers Z X Y 2 62 4513 4514 Group User s Manual APPLICATION 2 10 Oscillation circuit 2 10 Oscillation circuit The 4513 4514 Group has an internal oscillation circuit to produce the clock required for microcomputer operation The clock signal f XIN is obtained by connecting a ceramic resonator to XIN pin and XOUT pin 2 10 1 Oscillation circuit 1 f XiN clock generating circuit The clock signal f XIN is obtained by connecting a ceramic resonator externally Connect this external circuit to pins XIN and Xour at the shortest distance A feed back resistor is built in between XIN pin and XOUT pin Figure 2 10 1 shows an example of an oscillation circuit connecting a ceramic resonator externally Keep the maximum value of oscillation frequency within the range listed Table 2 10 1 Table 2 10 1 Maximum value of oscillation frequency and supply voltage Supply voltage System clock Oscillation frequency 2 5 V to 5 5 V f XiN 2 Middle speed mode 4 2 MHz 4 0 V to 5 5 V High speed mode 4 2 MHz 2 5 V to 5 5 V High speed mode 2 0 MHz 2 0 V to 5 5 V Note
233. the instruction The output structure is an N channel open drain 6 Port P5 The 4513 Group does not have this port Port P5 is a 4 bit I O port B input output of port P5 Port P5 has direction register FRO to input output by the bit Data input to port P5 Set the bit of register FROi iz0 to 3 corresponding to specified port P5i 0 to 3 to 0 When the register FRO is set to 1 the value of output latch is input The state of port P5 is transferred to register A when the instruction is executed Data output from port P5 Set the bit of register FROi iz0 to 3 corresponding to specified port P5i i0 to 3 to 1 When the register FRO is set to 0 specified port P5i is in the high impedance state The contents of register A is output to port P5 with the instruction The output structure is CMOS 4513 4514 Group User s Manual 2 3 APPLICATION 2 1 I O pins 7 Port D Do D7 are eight independent 1 ports B input output of port D Each pin of port D has an independent 1 bit wide I O function For I O of ports Do D7 select one of port D with the register Y of the data pointer first Data input to port D Set the output latch of specified port Di i O to 7 to 1 with the SD instruction When the output latch is set to 0 L level is input When the SZD instruction is executed if the port specified by register Y is 0 the next instruction is skipped If
234. the contents of register SI are shifted to one bit position toward the LSB Also the receive data is input from the SIN pin synchronously with the rising edges of the shift clock The receive data is input bit by bit to the MSB bit of register 51 A serial l O interrupt request occurs when the transmit receive of data is completed and the SIOF flag is set to 1 The receive data is taken in within the serial I O interrupt service routine or the data is taken in after examining the completion of the transmit receive operation with the SNZSI instruction without using an interrupt Also the SIOF flag is cleared to 0 when an interrupt occurs or the SNZSI instruction is executed Make sure that the control signal pin level is after the receive operation is completed Note Repeat steps through to transmit or receive multiple data in succession 2 4 4 Serial application example 1 Serial I O Outline The 4513 4514 Group can communicate with peripheral ICs Specifications Figure 2 4 2 Serial connection example Figure 2 4 5 shows the master serial I O setting example and Figure 2 4 6 shows the slave serial setting example 4513 4514 Group User s Manual 2 45 APPLICATION 2 4 Serial Disable Interrupts Serial I O interrupt is temporarily disabled Interrupt enable flag INTE 9 All interrupts disabled DI instruction Interrupt control register V2 EJ A occurrence disabl
235. the mask ROM data on the products we produce differ from this data Thus the customer must be especially careful in verifying the data contained in the EPROMs submitted Microcomputer name M34513M2 XXXSP M34513M2 XXXFP Checksum code for entire EPROM area LI LJ hexadecimal notation EPROM Type 27C256 27C512 Low order 5 bit data 7 4000 High order 5 bit data ATEFs TFFF e Set 16 in the shaded area Set 1112 in the area 2 Mark Specification Low order 1028 5 bit data 7 22 High order 2 00K 5 bit data 47FFis FFFFie of low order and high order 5 bit data Mark specification must be submitted using the correct form for the type of package being ordered Fill out the approximate Mark Specification Form 32P4B for M34513M2 XXXSP 32P6B A for M34513M2 XXXFP and attach to the Mask ROM Order Confirmation Form 3 Comments 3 30 4513 4514 Group User s Manual APPENDIX 3 5 Mask ROM order confirmation form GZZ SH52 44B lt 81A0 gt Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M34513M4 XXXSP FP ME MITSUBISHI ELECTRIC sse e Please fill in all items marked Company Responsible name officer Supervisor Customer Date Issuance signature issued 1 Confirmation
236. therwise noted Limits Typ Parameter Test conditions Resolution 25 C VDD 2 7 V to 5 5 V Ta 25 to 85 C VDD 3 0 V to 5 5 V 25 C VDD 2 7 V to 5 5 V Ta 25 to 85 C VDD 3 0 V to 5 5 V VDD 5 12 V VDD 3 072 V VDD 5 12 V VDD 3 072 V VDD 5 0 V f XIN 0 4 MHz to 4 0 MHz 3 0 V f XIN 0 4 MHz to 2 0 MHz f XIN 4 0 MHz Middle speed mode f XIN 4 0 MHz High speed mode Comparator resolution Comparator mode VDD 5 12 V VDD 3 072 V f XIN 4 0 MHz Middle speed mode f XIN 4 0 MHz High speed mode Note As for the error from the ideal value in the comparator mode when the contents of the comparator register is n the logic value of the comparison volt age Vref which is generated by the built in DA converter can be obtained by the following formula Linearity error Differential non linearity error Zero transition voltage Full scale transition voltage A D operating current A D conversion time Comparator error Note Comparator comparison time r Logic value of comparison voltage Vref VDD Vref ee 7T x n 256 n Value of register AD n 0 to 255 3 1 5 Voltage drop detection circuit characteristics Table 3 1 7 Voltage drop detection circuit characteristics 20 C to 85 C unless otherwise noted Parameter Test condi
237. tion The contents of register Q2 is transferred to register A with the TAQ2 instruction Table 2 1 3 shows the A D control register Q2 at reset 00002 at RAM back up state retained Table 2 1 3 A D control register Q2 A D control register Q2 R W 0 A D conversion mode Q23 A D operation mode control bit 1 Comparator mode Q22 P43 AIN7 P42 AIN6 pin function 0 P43 P42 I O Note 4 selection bit Note 3 1 AIN7 AIN6 P43 P42 Output Note 4 gt P41 AIN5 pin function selection bit 0 P41 I O Note 4 Note 3 1 AIN5 P41 Output Note 4 or P40 AIN4 pin function selection bit 0 P4o I O Note 4 Note 3 AlN4 P40 Output Note 4 Notes 1 R represents read enabled and W represents write enabled 2 Select AIN4 AIN7 with register Q1 after setting register Q2 3 For the 4513 Group these bits are not used 4 For the 4513 Group only read write of these bits is enabled 5 When setting ports Q23 is not used 4513 4514 Group User s Manual 2 5 APPLICATION 2 1 I O pins 4 Direction register FRO The 4513 Group does not have this register Register FRO is used to switch to input output of 50 53 Set the contents of this register through register A with the TFROA instruction Table 2 1 4 shows the direction register FRO Table 2 1 4 Direction register FRO Direction register FRO Note 2 at reset 00002 at RAM back up state retained W
238. tion is invalid Interrupt disabled SNZO instruction is valid Interrupt enabled SNZO instruction is invalid Notes 1 R represents read enabled and W represents write enabled 2 When timer is used V11 and V10 are not used Interrupt control register V1 V13 2 interrupt enable bit 12 Timer 1 interrupt enable bit 11 1 interrupt enable bit Vio External 0 interrupt enable bit 2 Interrupt control register V2 The timer 3 interrupt enable bit is assigned to bit 0 and the timer 4 interrupt enable bit is assigned to bit 1 Set the contents of this register through register A with the TV2A instruction The TAV2 instruction can be used to transfer the contents of register V2 to register A Table 2 3 2 shows the interrupt control register V2 Table 2 3 2 Interrupt control register V2 at reset 00002 at RAM back up 00002 0 Interrupt disabled SNZSI instruction is valid 1 Interrupt enabled SNZSI instruction is invalid 0 Interrupt disabled SNZAD instruction is valid 1 Interrupt enabled SNZAD instruction is invalid 0 Interrupt disabled SNZT4 instruction is valid 1 0 Interrupt control register V2 R W V23 Serial I O interrupt enable bit V22 A D interrupt enable bit V21 Timer 4 interrupt enable bit Interrupt enabled SNZT4 instruction is invalid Interrupt d
239. tions Detection voltage Operation current of voltage drop detection circuit 3 6 4513 4514 Group User s Manual APPENDIX 3 1 Electrical characteristics 3 1 6 Voltage comparator characteristics Table 3 1 8 Voltage comparator recommended operating conditions Ta 20 C to 85 C unless otherwise noted Limits Symbol Parameter Conditions Typ VDD Supply voltage VINCMP Voltage comparator input voltage 3 0 V to 5 5 V Voltage comparator response time 3 0 V to 5 5 V Table 3 1 9 Voltage comparator characteristics Ta 20 C to 85 C VDD 3 0 V to 5 5 V unless otherwise noted m Limits Symbol Parameter Test conditions Hatt Min gt CMP0 lt CMP0 1 gt CMP1 CMP1 lt CMP1 Voltage comparator operation current VDD 5 0 V Comparison decision voltage error 3 1 7 Basic timing diagram Parameter XIN System clock f XIN XIN System clock 2 Port D output Do D7 Port D input Do D7 Ports PO P1 5 P4 P5 output ses P4o P4s P5o P53 Ports PO P1 P2 P3 A MESA 13 P5 input 20 2 gt P3o P33 P4o P43 P5o P53 Interrupt input INTO INT1 4513 4514 Group User s Manual 3 7 APPENDIX 3 2 Typical characteristics 3 2 Typical characteristics 3 2 1 VDD IDD characteristics 1 CPU operating middle speed mode 2 5 Supply
240. tiple interrupts Multiple interrupts cannot be used in the 4513 4514 Group Notes on interrupt processing When the interrupt occurs at the same time the interrupt enable flag INTE is cleared to 0 interrupt disable state In order to enable the interrupt at the same time when system returns from the interrupt write El and RTI instructions continuously P30 INTO pin The 0 pin need not be selected the external interrupt input INT function or the normal output port P30 function However the EXFO flag is set to 1 when a valid waveform is input to INTO pin even if it is used as an I O port P30 P31 INT1 pin The P31 INT1 pin need not be selected the external interrupt input INT function or the normal output port P31 function However the EXF1 flag is set to 1 when a valid waveform is input to INT1 pin even if it is used as an I O port P31 EPOF instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction 4513 4514 Group User s Manual 2 25 APPLICATION 2 3 Timers 2 3 Timers The 4513 4514 Group has four 8 bit timers each has a reload register and a 16 bit fixed dividing frequency timer which has the watchdog timer function This section describes individual types of timers related registers application examples using timers and notes 2 3 1 Timer functions 1 2 3 4 5 2 26 Timer 1 B Timer operation Timer 1 h
241. ts sufficiently i Apply the voltage withiin the specifications to an analog input pin Fig 47 Analog input external circuit example 1 About 1kQ Fig 48 Analog input external circuit example 2 POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back up Note that system cannot enter the RAM back up state when ex ecuting only the POF instruction Be sure to disable interrupts by executing the DI instruction be fore executing the EPOF instruction Analog input pins Note the following when using the analog input pins also for 1 port P4 functions e Even when P40 AIN4 P43 AIN7 are set to pins for analog input they continue to function as 40 43 Accordingly when any of them are used as I O port and others are used as analog input pins make sure to set the outputs of pins that are set for analog input to 1 Also the port input function of the pin func tions as an analog input is undefined TALA instruction When the TALA instruction is executed the low order 2 bits of register AD is transferred to the high order 2 bits of register A si multaneously the low order 2 bits of register A is 0 Program counter Make sure that the PCH does not specify after the last page of the built in ROM G Port In the 4513 Group when the IAPS instruction is executed note that the high order 2 bits of register A is
242. ty that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials information contained in these materials including product data diagrams and charts represent information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing
243. uction Serial transfer starts SST instruction Check transmission completes Reception Check reception completes SNZSI instruction SNZSI instruction Wait timing when continuously transferring H level is output from port 05 SD instruction Data processing 1 byte data is serially transferred on this process Subsequently data can be transferred continuously by repeating the process from When an external clock is selected as a synchronous clock the clock is not controlled internally Control the clock externally be cause serial transfer is performed as long as clock is externally input Unlike an internal clock an external clock is not stopped when serial transfer is completed However the SIOF flag is set to 1 when the clock is counted 8 times after executing the SST in struction Be sure to set the initial level of the external clock to H 1 40 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS A D CONVERTER Table 14 A D converter characteristics The 4513 4514 Group has a built in A D conversion circuit that Parameter Characteristics performs conversion by 10 bit successive comparison method Conversion format Successive comparison method Table 14 shows the characteristics of this A D converter This A Resolution 10 bits D converter can also be used as an 8 bit comparator to compare Relative accuracy Linearity e
244. ult of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time max 20 us is passed from the voltage comparator function become valid 4513 4514 Group User s Manual 2 55 APPLICATION 2 Reset 2 Reset System reset is performed by applying L level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied the value of supply voltage is the minimum value or more of the recommended operating conditions oscillation is stabilized Then when level is applied to RESET pin the software starts from address 0 in page 0 after elapsing of the internal oscillation stabilizing time f XIN is counted for 16892 to 16895 machine cycles Figure 2 7 2 shows the oscillation stabilizing time 2 7 1 Reset circuit The 4513 4514 Group has the power on reset circuit and voltage drop detection circuit 1 Power on reset Reset can be performed automatically at power on power on reset by connecting resistors a diode and a capacitor to RESET pin Connect a capacitor between the RESET pin and Vss at the shortest distance VDD RESET pin voltage 2 Reset state Internal reset signal Reset released Power on Note lt This symbol represents a parasitic diode Applied potential to RESET pin must be VDD or less Fig 2 7 1 Power on reset circuit example Reset input f XiN is cou
245. undefined 4513 4514 Group User s Manual APPENDIX 3 3 List of precautions Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3 it is operating even in the RAM back up mode Accordingly be careful about such state because it causes the increase of the operation current in the RAM back up mode In order to reduce the operation current in the RAM back up mode invalidate bits 2 3 of register 0 the voltage comparator function by software before the POF instruction is ex ecuted Also while the voltage comparator function is valid current is al ways consumed by voltage comparator On the system required for the low power dissipation invalidate the voltage comparator when it is unused by software cfRegiser as Bits 0 and 1 of register can be only read Note that they can not be written Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time max 20 us is passed from the voltage comparator function become valid 4513 4514 Group User s Manual 3 23 APPENDIX 3 4 Notes on noise 3 4 Notes on noise Countermeasures against noise are described below The following countermeasures are effective against noise in theory however it is necessary not only to take measures as follows but t
246. upt request occurs by the change of input level of INTO pin The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register 11 E External 0 interrupt INTO processing When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the external 0 interrupt occurs the interrupt processing is executed from address 0 in page 1 When the interrupt is not used The interrupt is disabled and the SNZO instruction is valid when the bit 0 of register V1 is set to 0 2 External 1 interrupt INT1 The interrupt request occurs by the change of input level of INT1 pin The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register 12 B External 1 interrupt INT1 processing When the interrupt is used The interrupt occurrence is enabled when the bit 1 of the interrupt control register V1 and the interrupt enable flag INTE are set to 1 When the external 1 interrupt occurs the interrupt processing is executed from address 2 in page 1 When the interrupt 15 not used The interrupt is disabled and the SNZ1 instruction is valid when the bit 1 of register V1 is set to 0 3 Timer 1 interrupt The interrupt request occurs by the timer 1 underflow B Timer 1 interrupt processing When the interrupt is used The interrupt occurrence is enabled wh
247. urce is input to CNTRO pin and the timer 2 interrupt request occurs every 100 counts Figure 2 3 5 shows the setting example of CNTRO input 4513 4514 Group User s Manual APPLICATION 2 3 Timers 4 5 6 CNTR1 output control square wave output control Outline The output stop of square wave from timer 3 every timer 4 underflow can be controlled Specifications 4 kHz square wave is output from timer 3 at system clock frequency f XIN 4 0 MHz Also timer 4 controls ON OFF of square wave every constant period Figure 2 3 6 shows the setting example of CNTR1 output Timer operation timer start by external input Outline The constant period can be measured by external input Specifications Timer 1 operates by INTO input as a trigger and an interrupt occurs after 1 ms Figure 2 3 7 and Figure 2 3 8 show the setting example of timer start Watchdog timer Watchdog timer provides a method to reset the system when a program run away occurs In the 4513 4514 Group bit 15 of 16 bit timer is counted twice for the watchdog timer Accordingly when the watchdog timer function is set to be valid execute the WRST instruction at a certain period which consists of timer 16 bit timers 32767 counts or less execute WRST instruction at a cycle of 32766 machine cycles or less Outline Execute the WRST instruction in 16 bit timer s 32767 counts at the normal operation If a program runs incorrectly the WRST instruction is n
248. when the actual A D con version output data changes from 1023 to 1022 G Linearity error This means a deviation from the line between Vor and VFST of a converted value between Vor and VFST Differential non linearity error This means a deviation from the input potential difference re quired to change a converter value between Vor and VFST by 1 LSB at the relative accuracy Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A D conversion characteristics Full scale transition voltage 1022 Differential non linearity error LSB Linearity error zx LSB Actual A D conversion characteristics a 1LSB by relative accuracy b Vn 1 Vn c Difference between ideal Vn and actual Vn Zero transition voltage Fig 30 Definition of A D conversion accuracy Analog voltage Vn Analog input voltage when the output data changes from n to n 1 n 0 to 1022 1LSB at relative accuracy 1022 e 1LSB at absolute accuracy gt V 1024 1 46 4513 4514 Group User s Manual VOLTAGE COMPARATOR The 4513 4514 Group has 2 voltage comparator circuits that perform comparison of voltage between 2 pins Table 17 shows the characteristics of this voltage comparison CMP0 AIN1 CMP1 AIN2 CMP1 AIN3 HARDWARE FUNCTION BLOCK OPERATIONS Table 1
249. wo word instruction are described below The second word BL 10 paaa aaaa BML 10 paaa aaaa BLA 10 00 pppp BMLA 10 00 SEA 00 0111 nnnn 520 00 0010 1011 4513 4514 Group User s Manual 1 67 HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE for 4514 Group 010000011000 010111 07 09 0B 0C OD OE OF 10 17 00000000000 1 00001 000001 1 000100 000101 0001 10 0001 1 1 001000 001001 001010 00101 11001 100 001 101 001110 001111 03 05 notation 16 BL BL BM SNZO SNZ1 gt gt gt 1 gt gt gt gt gt gt gt gt SNZIO gt SNZI1 ae p gt o gt RD The above table shows the relationship between machine language codes and machine language instructions D3 Do show the low order 4 bits of the machine language code and 09 04 show the high order 6 bits of the machine language code The hexadecimal representa tion of the code is also provided There are one word instructions and two word instructions but only the first word of each instruction is shown Do not use code marked The codes for the second word of a two word instruction are described below The second word cannot be used in the M34514M6 XXXFP BL 10 paaa aaaa BML 10 paaa aaaa BLA 10 pp00 pppp BMLA 10
250. zed with the SNZIO instruction L level return level selection bit Note 2 Rising waveform H level of INTO pin is recognized with the SNZIO instruction H level INTO pin edge detection circuit control bit One sided edge detected Both edges detected INTO pin Disabled timer 1 control enable bit Interrupt control register I2 reset 00002 Enabled at RAM back up state retained Not used This bit has no function but read write is enabled Interrupt valid waveform for INT1 pin Falling waveform 47 level of INT1 pin is recognized with the SNZI1 instruction L level return level selection bit Note 3 Rising waveform H level of INT1 pin is recognized with the SNZI1 instruction H level INT1 pin edge detection circuit control bit One sided edge detected Both edges detected INT1 pin Disabled timer 3 control enable bit Notes 1 R represents read enabled and W represents write enabled Enabled 2 When the contents of 112 is changed the external interrupt request flag EXFO be set Accordingly clear EXFO flag with the SNZO instruction 3 When the contents of 122 is changed the external interrupt request flag EXF1 may be set Accordingly clear EXF1 flag with the SNZ1 instruction 1 28 4513 4514 Group User s Manual HARDWARE FUNCTION BLOCK OPERATIONS TIMERS Fixed dividing frequency timer The

Renesas 4513 Network Card User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents