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Intel IQ80960RM Computer Accessories User Manual

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11. 8 L 9 S r e L or 0 80 jeeus 86 vi p ewg 9 AdH Zz iSnglOd AHVQNOO3S Vd SONOS AS a ene gav a Vd 39N3I9S SZ 294 poa 8LAYS Ley Leg WHO9608 Ml SWILSASOYOIN 3NOTOAO SE QUT ravens SAS Fog see aol geye NO 610V pog TOYS L 09V E L ozdvs 62100 edy eu s Ast P Old weave 8212207 ZIONS zg AS odvs 990007 HOV gag Tavs AS Twp e 20V req 2075 z vs sv 00v 9 aN9 Fag 10 92 1390 18 0528 3638 08 agy UNS 00 ecg tavs vZGVS sey aav ENC 55 00v S00V Savs pzy IND pag 90 pay 0v pog 920 7 nd 207 peg Zzavs tg et 00 ggg 32075 224820 HONO Eg 3038 08 zoy Q8 800V ecg 80 Tew 8 60 eg zavS 08075 023089 av peg Teqvs 9 ely ANS 3 6 vs epy 00v SON Brg are N9 D3dgig IO3US j La pp a oravs FINDS ND bg oe LLAYS LvN uva eIavs 18 9 SEED erdvs Ez QV BONS rg 1595 SOND A deuroNH Ez hal vias viv pra 0 97 d HB Fg 139705 gi NS SON FTE Uvas LNE er zii LOND Fig FA ss zpy e N9 HUAS Fg 99365 ny 21559 anio 1085 9 ra Divi AS bra SS 3 F 60305 ofyaNoas FEES E Jg 3 20995 Sev e 910015 Bye S GN eg WINS 2 2 NNOO IOdS j z ipsus 40155 ONO peg FOINIS ui aipg FOINIS ze NS J3SA3Gygg TISSA3G 81NIS sv NI 5g 3 700305 Sey AHL sat beg 60 v0 20 10 Aged yt ist SA
12. eene enne nennen nnns 3 9 5 1 Initialization MOSS uu u u TE nre reipsa kusam dn 5 3 A 1 IQ80960HN Bill of tenete teer teret daan Poe Un nee A 1 A 2 IQ80960RM Bill of Materials nennen nennen internen sistens A 5 B 1 I Q809650RN Schematics LISIELLL ciui oen e eua te nean opu uoa ug B 1 B 2 IQ80960RM Schematics LE nnne nennen nennen B 2 IQ80960RM RN Evaluation Platform Board Manual V intel Introduction 1 Figure 1 1 This manual describes the IQ80960RM and IQ80960RN evaluation platforms for Intel s 19609 RM RN I O processor The 1960 RM RN I O processors combine an 80960JT core with two PCI bus interfaces as well as a memory controller DMA channels an interrupt controller interface and an serial bus The difference between the two processors is that the 80960RN utilizes 64 bit primary PCI and secondary PCI buses while the 80960RM utilizes both a 32 bit primary and secondary PCI bus The IQ80960RM and IQ80960RN platforms are full length PCI adapter boards and are 8 9 in height to accommodate four standard PCI connectors on the secondary PCI bus The boards can be installed in any PCI host system that complies with the PCI Local Bus Specification Revision 2 1 PCI devices can be connected to the secondary bus to build powerful intelligent I O subsystems IQ80960RM IQ8096
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15. asian 3 3 3 3 1 Flash ROM Programming E nennen nennen enne nnne 3 3 Gonsole Serial P ON uu uuu 3 4 Secondary PCI Bus Expansion Connectors UU 3 4 35 1 PCI Slots Power Availability torte et ie ated ERREA vea eiu 3 4 3 5 2 Interrupt and IDSEL Routing uuu l u eterne E nete da a 3 5 siste beads 3 5 Losso darle m 3 5 Logic Analyzer Fleaders iced ri etn terrier tot epa ed esa dun rui eda 3 6 UM AA GTA CAG ON erm 3 7 User LEDS 3 8 3 10 1 User LEDs During Initialization u u Uu u ul uu s nnn 3 8 IQ80960RM RN Evaluation Platform Board Manual ili 5 3 5 4 O gt i9609 RM RN I O Processor Overview eterne 4 1 utere ette Eu Sus a huay Mes Lee dene 4 2 Local Interrupts s Q ua a usoq ape de k 4 3 ce 4 5 Primary PCI Interface 2 l au odii tia EON A AREA AEAEE due vane da 4 5 Secondary PCI Interface eter tene TA S aa AA ATE AEEA 4 5 DMA Channels n u u a a a ua la usss 4 6 Application Accelerator renea ena Ga aypaq A as Ceri Aian nnns 4 6 Performance Monitor Unit e 4 7 960 Support fo
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17. Voltage Typical Current Maximum Current 3 3 V 0 V 0v 5 1 32 1 86 12 V 284 485 12 V 1 1 NOTE Does include the power required by PCI mounted the IQ80960RM platform 3 3V for 80960RM Processor created on board from 5V SDRAM The IQ80960RM RN platform is equipped with a 168 pin DIMM socket formatted to accept 3 3V synchronous DRAM with or without Error Correction Code ECC The socket will accept SDRAM from 8 Mbytes to 128 Mbytes 128 Mbyte SDRAMs are available in both x64 and x72 configurations Note that 8 Mbyte SDRAMs are only for x64 or non ECC memory The SDRAM is accessible from either of the PCI buses via the ATUs and the local bus on the IQ80960RM RN platform 3 1 L Hardware Reference I ntel 3 2 1 Table 3 3 SDRAM Performance The IQ80960RM RN platform uses 72 bit SDRAM with ECC or 64 bit SDRAM without ECC SDRAM allows zero data to data wait state operation at 66 MHz The memory controller unit MCU of the 1960 RM RN I O processor supports SDRAM burst lengths of four A burst length of four enables seamless read write bursting of long data streams as long as the MCU does not cross the page boundary Page boundaries are naturally aligned 2 Kbyte blocks 72 bit SDRAM with ECC allows a maximum throughput of 528 Mbytes per second Both 16 Mbit and 64 Mbit SDRAM devices are supported The MCU keeps two pages per bank open simultaneous
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21. IxWORKS allows secondary PCI devices to be configured as Public or Private Public devices are configured by the PCI host Private devices are configured by the IKWORKS kernel and the device specific HDM IQ80960RM RN Evaluation Board Manual 4 5 m i9606 RM RN I O Processor Overview I ntel 4 6 Figure 4 4 4 7 4 6 DMA Channels The 1960 RM RN I O processor features three independent DMA channels two of which operate on the primary PCI interface whereas the remaining one operates on the secondary PCI interface All three of the DMA channels connect to the 1960 RM RN I O processor s local bus and can be used to transfer data from PCI devices to memory on IQ80960RM RN platform Support for chaining and scatter gather is built into all three channels The DMA can address the entire 294 bytes of address space on the PCI bus and 222 bytes of address space on the internal bus i9609 RM RN I O Processor DMA Controller Primary PCI Bus DMA Channel 0 DMA Channel 1 80960 Local Bus PCI to PCI Bridge DMA Channel 2 Secondary PCI Bus Application Accelerator Unit The Application Accelerator provides low latency high throughput data transfer capability between the AA unit and 80960 local memory It executes data transfers to and from 80960 local memory and also provides the necessary programming interface The Application Accelerator performs the following functions Transfers data read fro
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25. R10 R11 Resistor Pk SM RNC4R8P 2 7 Kohm CTS 742083272JTR R12 R33 R36 R38 R44 R45 80 2 R40 R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR 81 2 R15 R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR 82 1 R13 Resistor Pk SM RNC4R8P 1 5 Kohm CTS 742083152JTR 83 2 R22 R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR Central 84 1 CR9 Diode CMPSH3 Surface Mount Semiconductor CMPSH3 85 2 CR6 CR7 Diode SM MBRS340T3 Motorola MBRS340T3 Central 86 1 CR8 Diode SM 1N4001 CMR1 02 Semiconductor CMR1 02 87 1 J5 SDRAM DIMM ECC 2Mx72 16 Unigen UG5287408GSG Texas 88 2 U20 U21 IC SM TL7702BCD In trument TL7702BCD A 4 IQ80960RM RN Evaluation Board Manual Table A 2 IQ80960RM Bill of Materials Sheet 1 of 5 Bill of Materials Item Qty Location Part Description Manufacturer Manufacturer Part National 1 1 U13 IC SM 74ALS32 SOIC 14 Semiconductor DM74ALS32M National 2 1 U6 IC SM 74ALS04 SOIC Semiconductor DM74ALS04BM 3 1 U3 IC SM 74ABT273 SOIC Tode SN74ABT273DW Instruments 4 2 U1 U2 IC SM 74ABT573 SOIC Texas SN74ABT573DW Instruments National 5 1 U16 IC SM 74ALS08 SOIC Semiconductor DM74ALS08M National 6 1 U5 IC SM 1488A SOIC Semi p duet r DS1488M National 7 1 U7 IC SM 1489A SOIC Semiconductor DS1489AM 8 1 Q1 IC SM Si9430DY SOIC 8 Siliconix Si9430DY 9 1 U9 IC SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 Natio
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27. 35 1 R17 R SM 1 10 W 5 470 ohm 0805 Dale CRCW 0805 471JT 36 2 R48 R49 R SM 1 10 W 1 4 7 Kohm 0805 Dale CRCWO08054701FRT 37 1 R53 R SM 1 10 W 5 47 Kohm 0805 Dale CRCWO0805473JT 38 1 R26 R SM 1 10 W 5 68 Kohm 0805 Dale CRCW0805683JT R30 R43 39 4 R54 R56 R SM 1 8 W 5 10 ohm chip 1206 Dale CRCW1206100FT 40 5 WE icc CONN SM TH Mictor 43 Recptcl AMP 767054 1 J1 J2 J3 41 4 JA CONN PCI 64BIT 5 V PCB ThruHole AMP 145166 4 42 1 J5 CONN DIMM 168P RAng Socket TH Molex 73790 0059 43 1 J7 CONN TJ6 PCB 6 6 LP thru hole KYCON GM N 66 44 1 J13 CONN FAN ASSY Socket ThruHole AMP 173981 03 45 1 J6 CONN Hdr 16 pin w shell pcb AMP 103308 3 46 4 2122 28 Jumper JUMP2X1 Molex 22 54 1402 47 1 L1 Inductor SM 47uH 20 Coilcraft D03340P 473 48 1 L2 Inductor SM 3 3 uH 20 Coilcraft D03316P 332 49 1 51 Switch SM DIP4 Mors DHS 4S Mors DHS 4S 50 1 U4 OSC 1 8432 MHz 1 2 Thru hole Kyocera KHOHC1CSE 1 843 51 1 U18 Clock Chip CY7B9910 7SC Cypress CY7B9910 7SC Hewlett 52 1 CR5 LED Green Packard HLMP 3507 010 Hewlett 53 1 CR3 LED Red Packard HLMP3301 010 Hewlett 54 1 CR4 LED Green LP HLMP4740 010 55 2 CR1 CR2 LED Red Small Group Dialight 555 4001 56 2 Q2 Q3 Transistor SM N Channel Harris RFD16NO5LSM 57 1 Q4 Transistor 2N6109 Thru Hole Motorola 2N6109 58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269 1 BT1 BT2 BT3 BT4 60 8 BT5 BTS Battery Clips PC Snap In AA Keystone 92 BT7 BT8 61 1 U19 PALLV 16V8Z 20JI AMD
28. Device Number and Function Number of the Nth Device Function whose Vendor ID and Device ID match the input parameters Calling software can find all devices having the same Vendor ID and Device ID by making successive calls to this function starting with the index set to 0 and incrementing the index until the function returns DEVICE NOT FOUND A return value of BAD_VENDOR_ID indicates that the Vendor ID value passed had a value of all 1 s Calling convention int sysFindPCIDevice int device id int vendor id int index Return values This function returns SUCCESSFUL if the indicated device is located DEVICE_NOT FOUND if the indicated device cannot be located or BAD_VENDOR_ID if the vendor_id value is illegal sysFindPCIClassCode This function returns the location of PCI devices that have a specific Class Code Given a Class Code and an Index the function returns the Bus Number Device Number and Function Number of the Nth Device Function whose Class Code matches the input parameters Calling software can find all devices having the same Class Code by making successive calls to this function starting with the index set to 0 and incrementing the index until the function returns DEVICE_NOT_FOUND Calling convention int sysFindPCIClassCode int class_code int index Return values This function returns SUCCESSFUL when the indicated device is located or DEVICE_NOT FOUND when the indicated device
29. If you have IxWorks installed in the flash ROM the user LEDs display the binary pattern 99H In the Ix Works development environment raw serial input output is not used Instead the Wind DeBug WDB protocol is run over the serial port to allow communication with Tornado development tools If the terminal emulation package is running at 115 200 baud the letters WDB_READY display prior to launching in the WDB serial protocol IQ80960RM RN Evaluation Board Manual intel 2 4 2 4 1 Getting Started 4 If you have MON960 installed in the flash ROM press ENTER on a terminal connected to the IQ80960RM RN platform to bring up the MON960 prompt MON960 automatically adjusts its baud rate to match that of the terminal at start up At baud rates other than 9600 it may be necessary to press ENTER several times Creating and Downloading Executable Files To download code to the IQ80960RM RN platform running IxWorks consult Wind River documentation on the supplied TORNADO for I 0 CD ROM To download code to the IQ80960RM RN platform your compiler produces an ELF format object file To download code to the IQ80960RM RN platform running CTOOLS consult the CTOOLS documentation for information regarding compiling linking and downloading applications During a download MON960 checks the link address stored in the ELF file and stores the file at that location on the IQ80960RM RN platform If the executable file is linked to an in
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31. To support a private secondary PCI bus the Secondary IDSEL Select Register SISR is initialized to prevent the secondary PCI address bits 20 16 from being asserted during conversion of PCI Type 1 configuration cycles on the primary PCI bus to PCI Type 0 configuration cycles on the secondary PCI bus Secondary PCI bus masters are prevented from initiating transactions that will be forwarded to the primary PCI interface The PCI host is responsible for assigning and initializing the PCI bus numbers allocating PCI address space Memory Memory Mapped I O and I O and assigning the IRQ numbers to valid interrupt routing values Secondary ATU Initialization Secondary ATU Bridge initialization consists mainly of establishing the operational parameters for access between the local IQ80960RM RN platform bus and the secondary PCI devices The Secondary Inbound ATU Base Address Register SIABAR is initialized to establish the PCI base address of IQ80960RM RN platform local memory from the secondary PCI bus By convention the secondary PCI base address for access to IQ80960RM RN platform local memory is 0 The Secondary Inbound ATU Limit Register SIALR is initialized to establish the block size of memory required by the secondary ATU The SIALR value is based on the installed SDRAM configuration The Secondary Inbound ATU Translate Value Register SIATVR is initialized to establish the translation value for Secondary PCI to Local accesses The S
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36. IQ80960RM RN Evaluation Board Manual 3 5 Hardware Reference I n 3 8 Logic Analyzer Headers There are five logic analyzer connectors on the IQ80960RM RN platform The connectors are Mictor type AMP part 767054 1 Hewlett Packard and Tektronix manufacture and sell interfaces to these connectors The logic analyzer connectors allow for interfacing to the SDRAM and ROM buses along with secondary PCI arbitration signals Table 3 7 shows the connectors and the pin assignments for each Table 3 7 Logic Analyzer Header Definitions PIN J9 J11 J12 J10 J8 3 SDRAMCLK 4 DQ15 SDQM7 DQ31 RAD15 5 DQ14 SDQM6 DQ30 RAD14 6 DQ13 SDQM5 DQ29 RAD13 7 DQ12 SDQM4 DQ28 RAD12 8 DQ11 SDQM3 DQ27 RAD11 9 DQ10 SDQM2 DQ26 RAD10 10 DQ9 SDQM1 DQ25 RAD9 11 DQ8 SDQM0 DQ24 RAD8 12 DQ7 SCB7 DQ23 RAD7 13 DQ6 SCB6 DQ22 RAD6 14 DQ5 SCB5 DQ21 RAD5 15 DQ4 SCB4 DQ20 RAD4 16 DQ3 SCB3 DQ19 SCE0 RAD3 17 DQ2 SCB2 DQ18 SCE1 RAD2 18 DQ1 SCB1 DQ17 SBA1 RAD1 19 DQO SCBO DQ16 SBA0 RAD0 20 DQ32 SA0 DQ48 SREQ0 RAD16 21 DQ33 SA1 DQ49 SREQ1 22 DQ34 SA2 DQ50 SREQ2 23 DQ35 SA3 DQ51 SREQ3 RALE 24 DQ36 SA4 DQ52 SREQ4 RCE0 25 DQ37 SA5 DQ53 SREQ5 RCE1 26 DQ38 SA6 DQ54 SGNTO ROE 27 DQ39 SA7 DQ55 SGNT1 RWE 28 DQ40 SA8 DQ56 SGNT2 29 DQ41 SA9 DQ57 SGNT3 RST 30 DQ42 SA10 DQ58 SGNT4 31 DQ43 SA11 DQ59 SGNT5S 32 DQ44 DQ60 33 DQ45 SWE DQ61 34 DQ46 SCAS DQ62 35 DQ47
37. Logic analyzer connector for Secondary PCI bus arbitration signals J9 J11 J12 Logic analyzer connector for access to SDRAM bus J13 Active heatsink connector for example fan monitor circuit CR1 CR2 Eight user LEDs CR3 Self test fail LED CR4 Battery backup SDRAM 3 3 V available CR5 Indicates host system providing 3 3 V to Secondary PCI bus connectors 1 DIP switch Table 3 9 IQ80960RM RN Evaluation Board Manual 3 9 intel i960 RM RN I O Processor Overview Figure 4 1 Local Memory This chapter describes the features and operation of the processor on the IQ80960RM RN platform For more detail refer to the i960 RM RN I O Processor Developer s Manual i9609 RM RN I O Processor Block Diagram SDRAM Flash 2 Serial Bus 80960 Core Processor Memory Bus m Controller Interface 2 Bus Application Internal Unit Interface Accelerator Arbitration 64 bit Internal Bus Messaging Two DMA Unit Channels Address Translation Unit 64 bit 32 bit Primary PCI Bus Performance Monitoring Unit One DMA Address Channel Translation Unit PCI to PCI Bridge 64 bit 32 bit Secondary PCI Bus Secondary PCI Arbitration IQ80960RM RN Evaluation Board Manual 4 1 i960 RM RN I O Processor Overview I n 4 1 Figure 4 2 4 2 CPU Memory Map The memory map for the IQ80960RM
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39. ONS pog avs 891000 100 Tavs 2316 207728 82075 vEGVS egy cav SEOV pog seavs Zzavs 9 aN9 10 gzy 3S0 e 3638 08 ggypeav 9 5 ggg ggy S ON9 00V sg cave TINS sayveav EAE sog Taye N9 eav gg 7895 sgy 00V S00V Eg avs vay ONO 820 peg Scavs 8EGvS peg 66Gvs 9075 pog 920 7 ed 220729 220 oravs sgy LOND gag cay Ae 200 Zavs 8zavs 223820 HONO zg veve s WOW Tavs 3038 08 25 028 0 800V Eq gavs Tay het 62072 6z vs zravs tavi av pag travs 0875 peg Teavs vrOVS zay 0v I ON9 psg siy LS Tay ONO svav Tag Sravs 60 epy 00v SONS ra SIE QNS doi 10395 ovavS beg Zvavs Spy N9 OV Eg oravs FINOS Try mg 8 rr 2494 67 LLAYS zov eO Sg eravs Ng eo azy QNO 60 PTY oye Qv SON rg 1SuS gry SH SOND Gig A osavs 223089 HV rg Tavs py het vivs viv pre 250 5 9792297 2 036 STavs dv Haora 138705 ejf NS NNOO 1948 727 DEM S0V jg save Vds epy vd LAE eg ziv QNS LOND eg UF vSdvs viv 30v ssav pr 55095 zy NO 5 v ZINSUd jig 2100 95 vs gz PSV FOND T 193095 SNe yg ony st pra VM zip NS ASV Ea Zsavs oy B NOOS EXTER Sy UE 85095 r 8sqv 68 7a 65095 egy e 400 Keg 10075 VINIS 99 090 ozv 90v VN org dO1SS gevdO1S 2939 beg 3GINIS ui HNS 55 INS 190v bog T9dvs Ty NS ASAI eg TIJSA3G IN
40. SM 1488A SOIC Semiconductor DS1488M National 7 1 U7 IC SM 1489A SOIC Semiconductor DS1489AM 8 1 Q1 IC SM Si9430DY SOIC 8 Siliconix Si9430DY 1 U9 IC SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 National 10 1 U10 IC SM LM339 SOIC 14 Semiconductor LM339M 11 1 U8 IC SM MAX1651CSA SOIC 8 Maxim MAX1651CSA 12 1 U14 IC SM MAX712CSE SOIC 16 Maxim MAX712CSE 13 1 U17 IC SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 PROCESSOR from Intel 80960RN Intel 15 1 U12 VLSI I O UART 16C550 PLCC Texas TL16C550AFN Instruments 16 1 C65 CAP SM 0 47 uF 1206 Philips Philips 12062F474Z9BB0 C2 C3 C10 C11 C18 C19 C26 C27 17 15 Gee CAP SM 0 01 uF 0805 Kemet C0805C103K5RAC C61 C68 C77 C83 C96 IQ80960RM RN Evaluation Board Manual A 1 Bill of Materials A 2 Table A 1 IQ80960RN Bill of Materials Sheet 2 of 4 Item Qty Location Part Description Manufacturer Manufacturer Part 18 81 C1 C4 C5 C6 C7 C8 C9 C12 C13 C14 C15 C16 C17 C20 C21 C22 C23 C24 C25 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C48 C49 C50 C51 C53 C59 C62 C66 C67 C69 C70 C71 C73 C79 C80 C81 C85 C86 C87 C94 C95 C97 C98 C99 C100 C101 C102 C108 C104 C105 C106 C107 C108 C109 C111 C112 C113 C115 C116 C114 C117 C120 C121 CAP SM 0 1 uF 0805 Philips 08052R104K8BB2 19 C110
41. SRAS DQ63 36 P_PCICLK RALE 3 6 IQ80960RM RN Evaluation Board Manual Table 3 8 Table 3 9 Hardware Reference JTAG Header The JTAG header allows debugging hardware to be quickly and easily connected to some of the IQ80960RM RN processor s logic signals The JTAG header is a 16 pin header A 3M connector part number 2516 6002UG is required to connect to this header The pinout for the JTAG header is shown in Table 3 8 The header and connector are keyed using a tab on the connector and a slot on the header to ensure proper installation Each signal in the JTAG header is paired with its own ground connection to avoid the noise problems associated with long ribbon cables Signal descriptions are found in the i960 RM RN I O Processor Developer s Manual 80960RM I O Processor Data Sheet and the SO960RN I O Processor Data Sheet JTAG Header Pinout Pin Signal Input Output to 80960RM RN Pin Signal 1 TRST IN 2 GND 3 TDI IN 4 GND 5 TDO OUT 6 GND 7 TMS IN 8 GND 9 TCK IN 10 GND 11 LCDINIT IN 12 GND 13 RST OUT 14 GND 15 PWRVLD OUT 16 GND Table 3 9 describes switch setting options and defaults These switch settings are sampled at Primary PCI Reset See Table 5 1 Initialization Modes on page 5 3 for processor initialization configurations Switch S1 Settings Position Name Description Default Determines if the processor is to be held in rese
42. are established immediately after processor core initialization Memory Bank 0 is associated with the ROM on the IQ80960RM RN platform Memory Bank 1 is associated with the UART and the LED Control Register Parameters such as Bank Base Address Read Wait States and Write Wait States must be established to ensure the proper operation of the IQ80960RM RN platform The Memory Controller is initialized so as to be consistent with the IQ80960RM RN platform memory map shown in Figure 4 2 SDRAM Initialization SDRAM initialization includes setting operational parameters for the SDRAM controller and sizing and clearing the installed SDRAM configuration To configure the system properly Presence Detect data is read from the EEPROM of the SDRAM module using the 80960RM RN Bus Interface Unit Presence Detect data includes the number and size of SDRAM banks present on the installed module On power up 64 bytes of Presence Detect data are read and validated The SDRAM controller is then configured by setting the base address of SDRAM the boundary limits for each SDRAM bank the refresh cycle interval and the output buffer drive strength Once the SDRAM controller is configured the SDRAM is cleared in preparation for the C language runtime environment The actual SDRAM size is stored for later use e g to establish the size of the IQ80960RM RN platform PCI Slave image The SDRAM controller is initialized to be consistent with the IQ80960RM RN platfor
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44. cannot be located IQ80960RM RN Evaluation Board Manual 5 7 MON960 Support for IQ80960RM RN I ntel 5 4 2 4 5 4 2 5 5 8 sysGenerateSpecialCycle This function allows for generation of PCI Special Cycles The generated special cycle is broadcast on a specific PCI Bus in the system PCI Special Cycles are not supported on the IQ80960RM RN platform secondary PCI bus Calling convention int sysGenerateSpecialCycle int bus number int special cycle data Return values Since PCI Special Cycles are not supported by the IQ80960RM RN platform this function always returns FUNC NOT SUPPORTED sysReadConfigByte This function allows the caller to read individual bytes from the configuration space of a specific device Calling convention int sysReadConfigByte int bus number int device number int function number int register number 0 1 2 255 UINT8 data Return values This function returns SUCCESSFUL when the indicated byte was read correctly or ERROR when there is a problem with the parameters IQ80960RM RN Evaluation Board Manual I n MONS960 Support for IQ80960RM RN 5 4 2 6 sysReadConfigWord This function allows the caller to read individual shorts 16 bits from the configuration space of a specific device The Register Number parameter must be a multiple of two 1 bit 0 must be set to 0 Calling convention int sysReadConfig Word int bus number int device n
45. the four secondary PCI expansion connectors The features of the IQ80960RM and IQ80960RN platforms are enumerated below and shown in Figure 1 1 and Figure 1 2 1960 RM RN I O processor Modified PCI long card form factor 64 bit or 32 bit primary PCI bus interface 80960RM 32 bit only e 64 bit or 32 bit secondary PCI bus connected to the primary PCI interface with a PCI to PCI bridge 80960RM 32 bit only DMA channels on both PCI buses Serial Bus 168 pin 3 3V DIMM socket supporting 16 to 128 Mbytes of Synchronous DRAM organized X72 to support Error Correction Code ECC and clocked at 66 MHz ships with 16 M ECC installed Serial console port based on 16C550 UART Eight user programmable LEDs 3 Indicator LEDs processor has passed self test 3 3 V is supplied to SDRAM and 3 3 V is supplied to secondary PCI slots Flash ROM 2 Mbytes Logic analyzer connectors for SDRAM bus ROM bus and secondary PCI arbitration signals Fan heatsink monitor circuit Battery backup for SDRAM JTAG header Software Development Tools A number of software development tools are available for the 19609 processor family This manual provides information on two software development toolsets Wind River System s Tornado for I 0 and Intel s CTOOLS If you are using other software development tools read through the information in this chapter and in Chapter 2 to gain a general understanding of how to use your tools w
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48. 0RN Platform Functional Block Diagram Secondary PCI Slot 4 Secondary PCI Slot 3 Secondary PCI Slot 2 Secondary PCI Slot 1 Console SDRAM x72 Port RS 232 LED Battery Serial Port Bacup Logic Analyzer Interface Logic Flash Analyzer UART LED ROM Interface Register Support i960 RMWRN Secondary PCI VO Processor Bus 32 64 bits ROM Bus Primary PCI Bus 32 64 bits IQ80960RM RN Evaluation Board Manual 1 1 Introduction i ntel Figure 1 2 IQ80960RN Platform Physical Diagram 64 Bit Secondary PCI Slots N je 168 Pin SDRAM DIMM Socket J3 J2 2 RS 232 Serial Port Ji e Flash Memory J9 J10 Jn J12 JE ERER 1 0 e e ETE e sesse e n e eee J6 erry BUM JTAG Port ma 015 4 E Logic Analyzer Connectors X PCI NiCd Batteries 1 2 IQ80960RM RN Evaluation Board Manual 1 2 Introduction i960 RM RN I O Processor and IQ80960RM RN Features The i960 RM RN I O processor serves as the main component of a high performance PCI based intelligent I O subsystem The IQ80960RM and IQ80960RN platforms allow the developer to connect PCI devices to the i960 RM RN I O processors using
49. 15 R16 Resistor Pk SMRNC4R8P 470ohm CTS 742083471JTR 1 Resistor Pk SM RNC4R8P 1 5 Kohm CTS 742083152JTR 2 R22 R23 Resistor Pk SMRNC4R8P 30 ohm CTS 742083300JTR 85 1 CR9 Diode CMPSH3 Surface Mount gental ductor CMPSH3 86 2 CR6 CR7 Diode SM MBRS340T3 Motorola MBRS340T3 87 1 CR8 Diode SM 1N4001 CMR1 02 gentral ductor CMR1 02 88 1 5 SDRAM DIMM ECC 2Mx72 16 MB Unigen UG52S7408GSG IQ80960RM RN Evaluation Board Manual intel Table A 2 IQ80960RM Bill of Materials Sheet 5 of 5 Bill of Materials Item Qty Location Part Description Manufacturer Manufacturer Part Texas 89 2 U20 U21 IC SM TL7702BCD inetruments TL7702BCD IQ80960RM RN Evaluation Board Manual A 9 Bill of Materials A 10 IQ80960RM RN Evaluation Board Manual intel Schematics B This appendix includes schematics for the IQ80960RN Table B 1 and IQ80960RM Table B 2 Table B 1 IQ80960RN Schematics List Page Schematic Title B 2 Decoupling and 3 3V Power B 3 Primary PCI Interface B 4 Memory Controller B 5 Flash ROM UART amp LEDs B 6 Logic Analyzer I F B 7 SDRAM 168 Pin DIMM B 8 Secondary PCI 960 Core B 9 Secondary PCI Bus 1 2 B 10 Secondary PCI Bus 3 4 B 11 SPCI Pull ups B 12 Battery Monitor IQ80960RM RN Evaluation Board Manual B 1
50. 155 E i SHUJSS GnAVEEBS S EINO Sgeyy 6IN S 0 0 195 Y I3SA3QS oeny 28430 S ZINS Syz Ny SzINOS 90 0 vas E 4dOlSS 02920185 Mis 5 155 1 E mais 5 OINO Sieny 01465 r FACES Tp AHS Faas ran S SIVN IS At INOO3S S Er oosus deHvONH sin Szy sous 9639705 venyan Sezqy__ e05US 238705 Srzyy 820395 aagos emis 3 z005 21 028 0 S T 3 e 8 I d8HVONH AS 60 80 S0 IOdS 8 L 9 S v
51. 5 68 Kohm 0805 Dale CRCWO0805683JT R30 R43 39 4 R54 R56 R SM 1 8 W 5 10 ohm chip 1206 Dale CRCW1206100FT 40 5 m A CONN SM TH Mictor 43P Recptcl AMP 767054 1 at 4 1517203 CONN PCI Slot 5W PCB ThruHole 145154 4 42 1 J5 CONN DIMM 168P RAng Socket TH Molex 73790 0059 43 1 J7 CONN TJ6 PCB 6 6 LP thru hole KYCON GM N 66 44 1 J13 CONN FAN ASSY Socket ThruHole AMP 173981 03 45 1 J6 CONN Hdr 16 pin w shell pcb AMP 103308 3 46 4 2122 28 Jumper JUMP2X1 Molex 22 54 1402 47 1 L1 Inductor SM 47 uH 2096 Coilcraft D03340P 473 48 1 L2 Inductor SM 3 3 uH 2096 Coilcraft D03316P 332 49 1 S1 Switch SM DIP4 Mors DHS 4S Mors DHS 4S 50 1 U4 OSC 1 8432 MHz 1 2 Thru hole Kyocera KHOHC1CSE 1 843 51 1 U18 Clock Chip CY7B9910 7SC Cypress CY7B9910 7SC Hewlett 52 1 CR5 LED Green Packard HLMP 3507 010 Hewlett 53 1 CR3 LED Red Packard HLMP3301 010 Hewlett 54 1 CR4 LED Green LP Packard HLMP4740 010 55 2 CR1 CR2 LED Red Small Group Dialight 555 4001 56 2 Q2 Q3 Transistor SM N Channel Harris RFD16NO5LSM 57 1 Q4 Transistor 2N6109 Thru Hole Motorola 2N6109 58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269 1 60 1 U11 SOCKET SM TSOP 40 pin Meritec 980020 40 02 IQ80960RM RN Evaluation Board Manual A 7 Bill of Materials A 8 Table A 2 IQ80960RM Bill of Materials Sheet 4 of 5 Intel Item Q
52. CAP SM 18 pF 0805 Kemet C0805C180J5GAC 20 R27 R28 R SM 1 10 W 5 1 ohm 0805 Dale CRCW0805100JT 21 R60 R SM 1 10 W 5 10 ohm 0805 Dale CRCW08051000JT 22 R25 R61 R62 R SM 1 10 W 5 1 Kohm 0805 Dale CRCW08051001FRT 23 R35 R39 R58 R59 R SM 1 10 W 5 10 Kohm 0805 Dale CRCW08051002FRT 24 R24 R32 R SM 1 10 W 5 100 Kohm 0805 Dale CRCW08051003FRT 25 R20 R SM 1 10 W 1 150 ohm 0805 Dale CRCW08051500FRT 26 R14 R41 R42 R SM 1 10 W 5 1 5 Kohm 0805 Dale CRCW0805152JT 27 R18 R SM 1 10 W 5 1 6 Kohm 0805 Dale CRCW0805162JT 28 R50 R51 R SM 1 10 W 5 22 ohm 0805 Dale CRCW0805220JT 29 R34 R SM 1 10 W 5 22 Kohm 0805 Dale CRCWO0805223JT 30 R37 R SM 1 10 W 5 24 ohm 0805 Dale CRCWO0805240JT IQ80960RM RN Evaluation Board Manual Table A 1 IQ80960RN Bill of Materials Sheet 3 of 4 Bill of Materials Item Qty Location Part Description Manufacturer Manufacturer Part 31 1 R47 R SM 1 10 W 5 2 4 Kohm 0805 Dale CRCWO0805242JT 32 2 R2 R57 R SM 1 10 W 5 2 7 Kohm 0805 Dale CRCWO0805272JT 33 1 R19 R SM 1 10 W 596 330 ohm 0805 Dale CRCWO0805331JT 34 1 R29 R SM 1 10 W 596 36 ohm 0805 Dale CRCWO0805360JT
53. CKE END OUTO SCKEO PIN amp PRSTn SCKE is the set term PRSTn is the reset term SCKEO PIN amp OUTO PIN ISCKEO PIN amp PRSTn SCKEO 0 SCKEO OE OUTO When OUT 0 SCKE is grounded When OUT 1 SCKE is high impedance OUTI SCKEI PIN amp PRSTn SCKEI PIN amp OUTI PIN ISCKEI PIN amp PRSTn SCKEI 0 SCKEI OE OUTI IQ80960RM RN Evaluation Board Manual C 1 intel Recycling the Battery D The IQ80960RM RN platform contains four AA NiCd batteries Each battery has the logo of the Rechargeable Battery Recycling Corporation RBRC stamped on it The recycling fees have been prepaid on these batteries Do not dispose of a rechargeable battery with regular trash in a landfill Rechargeable batteries contain toxic chemicals and metals that are harmful to the environment Improperly disposing of rechargeable batteries is also illegal The RBRC logo on a battery is a verification that recycling fees have been prepaid to the RBRC and such a battery can be recycled at no additional cost to the user The RBRC is a non profit corporation that promotes the recycling of rechargeable batteries including NiCd batteries Information on the RBRC program and the locations of participating recycling centers can be obtained by telephoning 1 800 8 BATTERY in the USA and following the recorded instructions The information obtained from this telephone number is updated frequently since the RBRC program is growing th
54. D Register Bitmap is E aasawa 3 8 4 1 i9609 RM RN I O Processor Block DIA QIAN ect 4 1 4 2 IQ80960RM RN Platform Memory Map u nnn nennen nnne 4 2 4 3 i9609 RM RN I O Processor Interrupt Controller Connections 4 4 4 4 i9609 RM RN I O Processor DMA 4 6 4 5 Application Accelerator Unit nennen 4 7 Tables 1 1 Document Informoatioti 1 9 1 2 GYCIONG uya unu u u ama ua z 1 9 3 1 IQ80960RN Platform Power Requiremenits 3 1 3 2 IQ80960RM Platform Power Requirements sese 3 1 3 3 SDRAM neuicm 3 2 3 4 SDRAM Gonfig ratioris cen oorr uu l ERRARE Da SERERE Uu ERRARE eS duh cR Rudd 3 3 3 5 UART Register Addresses ei de cet doeet Lxx aate o pe au de tete 3 4 3 6 Secondary PCI Bus Interrupt and IDSEL Routing eene 3 5 3 7 Logic Analyzer Header Definition Seassa anai seen 3 6 3 8 Header dM n o U epp c DES 3 7 3 9 Switch S1 Setllrgs ect aa FE ree dote uec Pda beu re ilasa Exe 3 7 3 10 Start up LEDs MONGGO Zulu l teretes Fe data 3 8 3 11 IQ80960RM RN Connectors and LEDS
55. IATVR value is set to reference the base of local SDRAM The Secondary Outbound Memory Window Value Register SOMWVR is initialized to establish the translation value for Local to Secondary PCI accesses The SOMWVR value is left at its default value of 0 to allow the IQ80960RM RN platform to access the start of the PCI Memory address map Likewise the Secondary Outbound I O Window Value Register SOIOWVR is left at its default value of 0 to allow the IQ80960RM RN platform to access the start of the PCI I O address map On the secondary PCI bus the IQ80960RM RN platform assumes the duties of PCI host and as such is required to configure the devices of the secondary PCI bus Secondary Outbound Configuration Cycle parameters are established during secondary PCI bus configuration Secondary PCI bus configuration is accomplished via MON960 Extension routines IQ80960RM RN Evaluation Board Manual 5 4 5 4 1 960 Support for IQ80960RM RN MON960 Kernel The MON060 Kernel monitor provides the IQ80960RM RN user with a software platform on which application software can be developed and run The monitor provides several features available to the IQ80960RM RN user to speed application development Among the available features are Communication with a terminal or terminal emulation package on a host computer through a serial cable with automatic baud rate detection Communication with a software debugger such as GDB960 ava
56. IQ80960RM RN processor reset In this mode the IQ80960RM RN platform sends PCI Retries when the PCI host attempts to access the platform s Configuration Space This mode allows the IQ80960RM RN processor time to initialize its internal registers The processor remains in this mode until the Configuration Cycle Disable bit in the Extended Bridge Control Register EBCR is cleared For this reason and to prevent PCI host problems Primary PCI initialization occurs at the earliest possible opportunity after Memory and SDRAM controller initialization Primary ATU Initialization Primary ATU Bridge initialization includes initialization by the 80960JT core and initialization by the PCI host processor Local initialization occurs first and consists mainly of establishing the operational parameters for access to the local IQ80960RM RN platform bus The Primary Inbound ATU Limit Register PIALR is initialized to establish the block size of memory required by the Primary ATU The PIALR value is based on the installed SDRAM configuration The Primary Inbound ATU Translate Value Register PIATVR is initialized to establish the translation value for PCI to Local accesses The PIATVR value is set to reference the base of local SDRAM The Primary Outbound Memory Window Value Register POMWVR is initialized to establish the translation value for Local to PCI accesses The POMWVR value remains at its default value of 0 to allow the IQ80960RM RN platform to ac
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63. PALLV16V8Z 20JI 62 1 U11 MEM Flash E28F016S5 090 TSOP Intel E28F016S5 090 IQ80960RM RN Evaluation Board Manual A 3 Bill of Materials Table A 1 IQ80960RN Bill of Materials Sheet 4 of 4 Intel Item Qty Location Part Description Manufacturer Manufacturer Part BT1 BT2 BT3 BT4 63 8 BT5 BT6 Battery AA NiCd 600 mA Hour SAFT NIC AA 600 SAFT BT7 BT8 64 1 U15 HeatSink Fan Assy 80960RM RN Panasonic UDQFNBEOIF 65 1 C84 CAP SM 0 22 uF 1206 Philips 12062E224M9BB2 C60 C75 66 3 C78 CAP TANT SM 220 uF 10 V 7343 AVX TPSE227K010R010 C89 C90 67 4 C91 C93 CAP TANT SM 47 uF 16 V 7343 AVX TPSD476K016R015 68 1 C63 CAP TANT SM 33 uF 10 V 7343 Sprague 293D336X9016D2T 69 4 05776 CAP TANT SM 4 7 pF 35 V 7343 Sprague 293D475X9035D2T 70 1 C47 CAP TANT SM 22 pF 20 V 7343 Sprague 293D226X9020D2T 71 1 C74 CAP TANT SM 1 pF 16 V 3216 Sprague 293D105X0016A2T 72 2 C52 C54 CAP TANT SM 10 uF 25 35 V Sprague 293D1060025D2T 73 1 C56 CAP TANT SM 100 pF 10 V 7343 AVX TPSD107K010R0100 74 1 C64 CAP TANT SM 330 uF 6 3 V 7343 AVX TPSE337K063R0100 75 3 Por ME CAP SM 0 047 uF 0805 Kemet C0805C473K5RAC 76 1 R46 Res SM 1 W 196 0 012 ohm 2512 Dale WSL 2512 R012 77 1 R21 Res SM 1 W 195 0 05 ohm 2512 Dale WSL 2512 R050 78 1 R52 Resistor SM 1 2 W 596 100 ohm Beckmen BCR 1 2 101 JT R1 R3 R4 R5 R6 R7 R8 R9 79 16
64. PCI devices onto the host PCI bus and supports transaction forwarding in both directions across the bridge PCI devices connected via the expansion slots can therefore act as masters or slaves on the host system s PCI bus Additional PCI to PCI bridge devices are supported by the 1960 RM RN I O processor on its secondary PCI interface and can be designed into add on PCI cards In addition the 1960 RM RN I O processor supports private PCI devices on its secondary bus Private devices are hidden from initialization code on the host system and are configured and accessed directly by the 1960 RM RN I O processor These devices are not part of the normal PCI address space but they can act as PCI bus masters and transfer data to and from other PCI devices in the system Unless designated as private devices PCI devices installed on the secondary PCI interface of the IQ80960RM RN platform are mapped into the system wide PCI address space by configuration software running on the host system No logical distinction is made at the system level between devices on the primary PCI bus and devices on secondary buses all transaction forwarding is handled transparently by the PCI to PCI bridge Configuration cycles and read and write accesses from the host are forwarded through the PCI to PCI bridge unit of the 1960 RM RN I O processor Master read and write cycles from devices on the secondary PCI bus are also forwarded to the host bus by the PCI to PCI bridge unit
65. R61 R62 R SM 1 10 W 5 1 Kohm 0805 Dale CRCW08051001FRT 23 12 R5 R6 R7 R8 R9 R10 R11 R12 R35 R39 R58 R59 R SM 1 10 W 5 10 Kohm 0805 Dale CRCW208051002FRT 24 R24 R32 R SM 1 10 W 5 100 Kohm 0805 Dale CRCW08051003FRT 25 R20 R SM 1 10 W 1 150 ohm 0805 Dale CRCW08051500FRT 26 R14 R41 R42 R SM 1 10 W 5 1 5 Kohm 0805 Dale CRCW20805152JT 27 R18 R SM 1 10 W 5 1 6 Kohm 0805 Dale CRCW0805162JT A 6 IQ80960RM RN Evaluation Board Manual Table A 2 IQ80960RM Bill of Materials Sheet 3 of 5 Bill of Materials Item Qty Location Part Description Manufacturer Manufacturer Part 28 2 R50 R51 R SM 1 10 W 5 22 ohm 0805 Dale CRCW0805220JT 29 1 R34 R SM 1 10 W 5 22 Kohm 0805 Dale CRCW0805223JT 30 1 R37 R SM 1 10 W 5 24 ohm 0805 Dale CRCW0805240JT 31 1 R47 R SM 1 10 W 5 2 4 Kohm 0805 Dale CRCW0805242JT 32 1 R57 R SM 1 10 W 5 2 7 Kohm 0805 Dale CRCW0805272JT 33 1 R19 R SM 1 10 W 5 330 ohm 0805 Dale CRCWO0805331JT 34 1 R29 R SM 1 10 W 596 36 ohm 0805 Dale CRCWO0805360JT 35 1 R17 R SM 1 10 W 596 470 ohm 0805 Dale CRCW 0805 471JT 36 2 R48 R49 R SM 1 10 W 1 4 7 Kohm 0805 Dale CRCWO08054701FRT 37 1 R53 R SM 1 10 W 5 47 Kohm 0805 Dale CRCW0805473JT 38 1 R26 R SM 1 10 W
66. RN I O processor receives its clock from the primary PCI interface clock generated by the motherboard Most motherboards generate a 33 MHz clock signal although the PCI specification requires a clock frequency between 0 and 33 MHz The timers can be programmed for single shot or continuous mode and can generate interrupts to the processor when the countdown expires Primary PCI Interface The primary PCI interface on the IQ80960RM RN platform provides the i960 RM RN I O processor with a connection to the PCI bus on the host system Only the PCI to PCI bridge unit on the 1960 RM RN I O processor is directly connected to the primary PCI interface Devices installed on the expansion slots are connected to the PCI bus via the bridge unit on the 1960 RM RN I O processor The PCI to PCI bridge accepts Type 1 configuration cycles destined for devices on the secondary bus and will forward them as Type 0 or Type configuration cycles or as special cycles The IQ80960RN platform interfaces to a 64 bit PCI bus and the IQ80960RM platform interfaces to a 32 bit PCI bus Secondary PCI Interface The secondary PCI interface provided by the 1960 RM RN I O processor is used to connect PCI cards via the expansion slots to the host system s PCI bus PCI cards are attached to the IQ80960RM RN platform with a standard PCI connector and may contain up to four separate PCI devices The 1960 RM RN I O processor provides PCI to PCI bridge functionality to map installed
67. RN platform is shown in Figure 4 2 All addresses below 9002 0000H on the IQ80960RM RN platform are reserved for various functions of the 1960 RM RN I O processor as shown on the memory map Documentation for these areas as well as the processor memory mapped registers at FF00 0000H and the IBR can be found in the i960 RM RN I O Processor Developer s Manual IQ80960RM RN Platform Memory Map Flash ROM Processor and Memory Mapped Processor Registers Registers FF00 0000H Flash ROM F000 0000H FEE0 0000H On board Devices Reserved DRAM Reserved E000 0000H F000 0000H k W LED Register write onl E004 0000H UART B000 0000H E000 0000H A000 0000H 2 H ATU Outbound Translation Windows 8000 0000H ATU Outbound Direct Addressing Window Memory Mapped Registers 0000 2000H 0000 1900H 0000 0800H 0000 0400H 0000 0000H IQ80960RM RN Evaluation Board Manual In 4 2 tel i960 RM RN I O Processor Overview Local Interrupts The i960 RM RN I O processor is built around an 80960JT core which has seven external interrupt lines designated XINTO through XINT5 and NMI In the i960 RM RN I O processor these interrupt lines are not directly connected to external interrupts but pass through a layer of internal interrupt routing logic Figure 4 3 shows the interrupt connections on the 1960 RM RN I O processor XINTO through XINT3 o
68. Register Unused E000 0017H Scratchpad Register Scratchpad Register 3 5 Secondary PCI Bus Expansion Connectors Four PCI Expansion Slots are available on the IQ80960RM RN platform The IQ80960RM supports 32 bit PCI expansion and the IQ80960RN supports 64 bit PCI expansion The slots are designed for 5V PCI signalling and accommodate PCI cards with 5V or universal signalling capabilities 3 5 1 PCI Slots Power Availability 3 4 Power from the Primary PCI bus 3 3V 5V 12V and 12V is routed to the Secondary PCI bus expansion slots 3 3V is only available at the secondary PCI slots if the host system makes 3 3V available on the Primary PCI slots LED CR5 indicates if this power is available IQ80960RM RN Evaluation Board Manual intel 3 5 2 Table 3 6 3 6 3 7 Note Hardware Reference Interrupt and IDSEL Routing Secondary PCI Bus Interrupt and IDSEL Routing Connector IDSEL INTA INTB INTC INTD J11 SAD16 SINTA SINTB SINTC SINTD J12 SAD17 SINTB SINTC SINTD SINTA J13 SAD18 SINTC SINTD SINTA SINTB J14 SAD19 SINTD SINTA SINTB SINTC Battery Backup Battery backup is provided to save any information in SDRAM during a power failure The IQ80960RM RN platform contains four AA NiCd batteries a charging circuit and a regulator circuit The batteries installed in the IQ80960RM RN platform are rated at 600 mA Hr SDRAM technology provides a simple way of enabling
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72. Stamp counter and Fourteen 14 Programmable Event counters The global time stamp counter is a dedicated free running 32 bit counter The programmable event counters are 32 bits wide Each counter can be programmed to observe an event from a defined set of events An event consists of a set of parameters which define a start condition and a stop condition The monitored events are selected by programming an event select register ESR IQ80960RM RN Evaluation Board Manual 4 7 intel MON960 Support for IQ80960RM RN 5 This chapter discusses a number of additions that have been made to MON960 to support the IQ80960RM RN in an optional non O capacity For complete documentation on the operation of MON 960 see the MON960 Debug Monitor User s Guide The IQ80960RM RN evaluation platform ships with IxWorks from Wind River Systems installed in flash firmware To use CTOOLS and MON960 instead of IxWorks you need to download MON960 into the onboard Flash See Chapter 2 for more information on updating the onboard Flash See Chapter 1 for descriptions of both IxWorks and CTOOLS 5 1 Secondary PCI Bus Expansion Connectors The IQ80960RM RN platform contains four secondary PCI bus expansion connectors to give users access to the secondary PCI bus of the 19609 RM RN I O processor Extensions to MON960 perform secondary PCI bus initialization including the establishment of a secondary PCI bus address map Routines compatible with the PCI Local Bus Speci
73. Systems Inc DOC 12381 8D 00 Tornado for 10 Compact Disk Rev 1 0 TDK 12380 ZC 00 SP610 Emulation System Reference Manual Spectrum Digital Inc 503715 Contact Cyclone Microsystems for additional information about their products and literature Table 1 2 Cyclone Contacts Phone 203 786 5536 Cyclone Microsystems FAX 203 786 5025 25 Science Park New Haven CT 06511 e mail info cyclone com WWW http www cyclone com IQ80960RM RN Evaluation Board Manual intel Getting Started 2 2 1 2 2 2 2 1 This chapter contains instructions for installing the IQ80960RM RN platform in a host system and how to download and execute an application program using Wind River System s IxWorks or Intel s CTOOLS software development toolsets Pre Installation Considerations This section provides a general overview of the components required to develop and execute a program on the IQ80960RM RN platform IQ80960RM RN evaluation boards support two software development toolsets Wind River System s IxWorks and Intel s CTOOLS IxWorks is a complete toolset featuring an integrated development environment including a compiler assembler linker and debugger It also features a real time operating system If you are using the Ix Works operating system with the TORNADO development environment refer to the Wind River Systems Inc documentation referenced in Section 1 8 3 CTOOLS is a co
74. Trays ze tav eg ory St era 20 vro azy oy i eravs OY SON 1595 5 SON Tg A L NNOO 1949 umasa a iri AND ae s oodvo 0sqvs ua LSAYS SIavs re 139 95 Erg 250 szv 90v 2 036 Wvds eyy vd iNet Epa zry QNS AON Eg Hy szveASt esaY bzg esavs gpy EON HH3SEyg 99355 ny ZINSHd ig Jnio o ysavs SSOVE7g SSavs 157085 t m PASt ora TENIS Ssavs HONS Ezer ojy NOQS HHddogg THH3dS v NSH UE SOV ETE 250 ev et en WIOOTS GINIS 869 85dvs ssavizg 65 vs 40155 559015 PNS 8INIS 090 aa VN Tae ON saare TISSA3d WINS 9 9 69 17 soyan 190 ggg 19155 sey Qut beg 60 0 20 10 Aged 290 soy 90v 90V ggg 90VS ggy ON AdHlceg AGNIS breor ais Col be v9HVdS 9uvd 9 aN9 Fag JSWVUS za m SONS for eo snis SON FG soy 5 bog WIGS 60 v0 20 10 Aged coy thet zasob EOS zi 39158 01 60 HOLS 3838 08 soya 928 058 3938 08 ze OV _ AVES 10 0 60 19415 ISL FAS 759 38 0 Egg v9 IodNNOO v9 IodNNOO tano TM p ast ast ast as Aev AS AS V 01 60 20 80 IOdS 8 L 9 r 4 L
75. _SUPPORTED IQ80960RM RN Evaluation Board Manual 5 11 MON960 Support for IQ80960RM RN I ntel 5 4 2 12 5 4 3 5 4 3 1 5 5 5 5 1 5 5 2 5 12 sysSetPClirq The PCI Interrupt routing fabric on the IQ80960RM RN platform is not reconfigurable fixed mapping relationships therefore this function is not supported Calling convention int sysSetPCIIrq int int_pin int irq_num int bus_dev Return values This function always returns FUNC_NOT_SUPPORTED Additional MON960 Commands The following commands have been added to the UI interface of MON960 to support the IQ80960RM RN platform print_pci Utility A print_pci command to MON960 is accessed through the MON960 command prompt This command displays the contents of the PCI configuration space on a selected adapter on the secondary PCI interface or on the 1960 RM RN I O processor itself For more information on the meaning of the fields in PCI configuration space refer to the PCI Local Bus Specification Revision 2 1 The syntax of this command is pp lt bus number gt lt device number gt lt function number gt Diagnostics Example Code 1Q80960RM RN platform diagnostic routines serve a twofold purpose to verify proper hardware operation and to provide example code for users who need similar functions in their applications Diagnostic routines fall into two categories board level diagnostics and PCI expansion module diagnostics Board Level Di
76. agnostics Board level diagnostics exercise all basic areas of the IQ80960RM RN platform Diagnostic routines include SDRAM tests UART tests LED tests internal timer tests PC bus tests and primary PCI bus tests Primary PCI bus tests exercise the primary ATU the PCI Doorbell unit and the PCI DMA controller Interrupts from both local and PCI sources are generated and handled The PCI bus tests require an external test suite running on a PC to verify complete functionality of the IQ809060RM RN platform Secondary PCI Diagnostics Secondary PCI diagnostics exercise the secondary PCI bus thereby confirming hardware functionality as well as illustrating the use of the PCI BIOS routines present in MON960 IQ80960RM RN Evaluation Board Manual intel Bill of Materials A This appendix identifies all components on the IQ80960RN Evaluation Platform Table A 1 and the IQ80960RM Evaluation Platform Table A 2 Table A 1 IQ80960RN Bill of Materials Sheet 1 of 4 Item Qty Location Part Description Manufacturer Manufacturer Part National 1 1 U13 IC SM 74ALS32 SOIC 14 Semiconductor DM74ALS32M National 2 1 U6 IC SM 74ALS04 SOIC Semiconductor DM74ALS04BM 3 1 U3 IC SM 74ABT273 SOIC Texas SN74ABT273DW Instruments 4 2 U1 U2 IC SM 74ABT573 SOIC exes SN74ABT573DW Instruments National 5 1 U16 IC SM 74ALS08 SOIC Semiconductor DM74ALS08M National 6 1 U5 IC
77. ation Run the Intel DOS based flash utility to program the Flash ROM boot sectors Set switch S1 s 1 and 2 to the off position N Reset board by cycling power on workstation 3 3 Hardware Reference 3 4 Console Serial Port intel The console serial port on the IQ80960RM RN platform based on a 16C550 UART is capable of operation from 300 to 115 200 bps The port is connected to a phone jack style plug on the IQ80960RM RN platform The DB25 to RJ 45 cable included with the IQ80960RM RN can be used to connect the console port to any standard RS 232 port on the host system The UART on the IQ80960RM RN platform is clocked with a 1 843 MHz clock and may be programmed to use this clock with its internal baud rate counters The UART register addresses are shown in Table 3 5 refer to the 16C550 device data book for a detailed description of the registers and device operation Note that some UART addresses refer to different registers depending on whether a read or a write is being performed Table 3 5 UART Register Addresses Address Read Register Write Register E000 0000H Receive Holding Register Transmit Holding Register E000 0001H Unused Interrupt Enable Register E000 0002H Interrupt Status Register FIFO Control Register E000 0003H Unused Line Control Register E000 0014H Unused Modem Control Register E000 0015H Line Status Register Unused E000 0016H Modem Status
78. ature Customer Support Number United States 800 548 4725 800 628 8686 Canada 800 468 8118 or 303 297 7763 800 628 8686 Europe Contact local distributor Contact local distributor Australia Contact local distributor Contact local distributor Israel Contact local distributor Contact local distributor Japan Contact local distributor Contact local distributor IQ80960RM RN Evaluation Board Manual intel 1 8 3 Related Information Introduction To order printed manuals from Intel contact your local sales representative or Intel Literature Sales 1 800 548 4725 Table 1 1 Document Information Product Document Name Company Order All Developers Insight CD ROM Intel 273000 80960RM RN i960 RM RN I O Processor Developer s Manual Intel 273158 80960RM I O Processor Data Sheet Intel 273156 80960RN I O Processor Data Sheet Intel 273157 960 RM RN I O Processor Design Guide Intel 273139 MON960 Debug Monitor User s Guide Intel 484290 PCI Local Bus Specification Revision 2 1 PCI Special Interest Group 1 800 433 5177 Writing 1 0 Device Drivers in IxWorks Wind River Systems Inc DOC 1173 8D 02 IxWorks Reference Manual Wind River Systems Inc DOC 1173 8D 03 VxWorks Programmer s Guide Wind River Systems Inc DOC 11045 ZD 01 Tornado User s Guide Wind River Systems Inc DOC 1116 8D 01 Tornado for I5O Wind River
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80. cess the start of the PCI Memory address map which is typically occupied by PCI host memory Likewise the Primary Outbound I O Window Value Register POIOW VR remains at its default value of 0 to allow the IQ80960RM RN platform to access the start of the PCI I O address map PCI Doorbell related parameters are also established to allow for communication between the IQ80960RM RN platform and a PCI bus master using the doorbell mechanism IQ80960RM RN Evaluation Board Manual 5 8 MON960 Support for IQ80960RM RN I ntel 5 2 7 5 2 8 5 4 By default Primary Outbound Configuration Cycle parameters are not established The ATU Configuration Register ATUCR is initialized to establish the operational parameters for the Doorbell Unit and ATU interrupts both primary and secondary and to enable the primary and secondary ATUs The PCI host is responsible for allocating PCI address space Memory Memory Mapped I O and I O and assigning the PCI Base addresses for the IQ80960RM RN platform PCI to PCI Bridge Initialization PCI to PCI Bridge initialization includes initialization by the 80960JT core and initialization by the PCI host processor Local initialization occurs first and consists mainly of establishing the operational parameters for the secondary PCI interface of the PCI to PCI bridge On the IQ80960RM RN platform the secondary PCI bus is configured to consist of private devices not visible to PCI host configuration cycles
81. cing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 1999 Third party brands and names are the property of their respective owners IQ80960RM RN Evaluation Platform Board Manual intel Contents 2 1 2 2 2 3 2 4 3 1 3 2 3 3 I I 6d elieivu y T 1 1 i960 RM RN I O Processor and IQ80960RM RN 1 3 Software Development ANNE 1 3 IxWorks Software Development Toolset u uu nnns 1 4 1 89 4 IxWorks Real Time Operating System 1 u uuu 1 4 1 3 2 TORNADO Build Tools siz u a edie ei aed pee 1 4 1 3 3 TORNADO Test and Debug Tools 1 4 CTOOLS Software Development Toolset U u u uuu nnns 1 5 1 4 1 CTOOLS and the MON960 Debug Monitor u 1 5 1 4 1 1 MON960 Host Communications essen enne 1 5 1 4 1 2 Terminal Emulation Method 1 5 1 4 1 3 Host Debugger Interface HDI Method 1 5 Abou
82. data preservation though the self refresh command When the processor receives an active Primary PCI reset it will issue the self refresh command and drive the SCKE signals low Upon seeing this condition a PAL on the 1Q80960RM RN platform will hold SCKE low before the processor loses power The batteries will maintain power to the SDRAM and the PAL to ensure self refresh mode When the PAL sees PRST returning to inactive state the PAL will release the hold on SCKE The battery circuit can be disabled by removing the batteries LED CR4 indicates when the SDRAMs have sufficient power If the batteries remain in the evaluation platform when it is depowered and or removed from the chassis the batteries will maintain the SDRAM for approximately 30 hours Once power is again applied the batteries will be fully charged in about four hours Loss of Fan Detect The 1960 RM RN I O processor can be cooled by an active heat sink mounted on top The fan provides a square wave output that is monitored by a comparator circuit on IQ809060RM RN platform The frequency of the fan output is approximately 9K RPM If the frequency falls below approximately 8K RPM the circuit will provide an interrupt to the processor This is an evaluation board feature intended as an example of system hardware monitoring since IQ80960RM RN platform does not ship with a heatsink When using a passive heat sink the processor never sees an interrupt from not having a fan
83. de the user IQ80960RM RN Evaluation Board Manual 5 1 MON960 Support for IQ80960RM RN I ntel 5 2 2 5 2 3 5 2 4 5 2 is given the ability to initialize the PCI configuration registers to values other than the default power up values Configuration Mode gives the user maximum flexibility to customize the way in which the 1960 RM RN I O processor and IQ80960RM RN platform appear to the PCI host configuration software 80960JT Core Initialization The 80960JT core begins the initialization process by reading its Initial Memory Image IMI from a fixed address in the boot ROM FEFF FF30H in the 1960 address space The IMI includes the Initialization Boot Record IBR the Process Control Block PRCB and several system data structures The IBR provides initial configuration information for the core and integrated peripherals pointers to the system data structures and the first instruction to be executed after processor initialization and checksum words that the processor uses in its self test routine In addition to the IBR and PRCB the required data structures are the System Procedure Table Control Table Interrupt Table Fault Table User Stack application dependent Supervisor Stack Interrupt Stack Memory Controller Initialization Since the 1960 RM RN I O processor Memory Controller is integral to the design and operation of the IQ80960RM RN platform the operational parameters for Bank 0 and Bank 1
84. e new recycling locations are being added regularly IQ80960RM RN Evaluation Board Manual D 1
85. en the indicated byte was written correctly or ERROR when there is a problem with the parameters This function allows the caller to write individual shorts 16 bits to the configuration space of a specific device The Register Number parameter must be a multiple of two i e bit 0 must be set to 0 0 244 254 This function returns SUCCESSFUL when the indicated word was written correctly or ERROR when there is a problem with the parameters IQ80960RM RN Evaluation Board Manual In 5 4 2 10 5 4 2 11 960 Support for IQ80960RM RN sysWriteConfigDword This function allows the caller to write individual longs 32 bits to the configuration space of a specific device The Register Number parameter must be a multiple of four i e bits 0 and 1 must be set to 0 Calling convention int sysWriteConfigDword int bus number int device number int function number int register number 0 4 8 252 UINT32 data Return values This function returns SUCCESSFUL when the indicated long was written correctly or ERROR when there is a problem with the parameters sysGetlrqRoutingOptions The PCI Interrupt routing fabric on the IQ80960RM RN platform is not reconfigurable fixed mapping relationships therefore this function is not supported Calling convention int sysGetIrqRoutingOptions PCI IRQ ROUTING TABLE table Return values This function always returns FUNC_NOT
86. erbar Bold Italics Courier font Asterisks UPPERCASE Designations for hexadecimal and binary numbers In code examples the pound symbol is appended to a signal name to indicate that the signal is active Normally inverted clock signals are indicated with an overbar above the signal name e g RAS Indicates user entry and or commands PLD signal names are in bold lowercase letters e g h_off h_on Indicates a reference to related documents also used to show emphasis Indicates code examples and file directories and names On non Intel company and product names a trailing asterisk indicates the item is a trademark or registered trademark Such brands and names are the property of their respective owners In text signal names are shown in uppercase When several signals share a common name each signal is represented by the signal name followed by a number the group is represented by the signal name followed by a variable n In code examples signal names are shown in the case required by the software development tool in use In text instead of using subscripted base designators e g or leading Ox e g OXFF hexadecimal numbers are represented by a string of hex digits followed by the letter H A zero prefix is added to numbers that begin with A through F e g FF is shown as OF FH In examples of actual code Ox is used Decimal and binary numbers are represented by their custo
87. errupt Controller Connections S_INTD Select bit S_INTA XINTO S_INTB XINT1 S_INTC XINT2 S_INTD XINT3 XINT4 Loss of Fan XINT5 UART put put put put P_INTC Out P_INTB Out P_INTA Out P_INTD Out S_INTC Select bit S_INTB Select N S_INTA Selett bit I DMA Channel 0 Interrupt Pending DMA Channel 1 Interrupt Pending gt DMA Channel 2 Interrupt Pending gt Performance Monitor Unit Interrupt Pending C Bus Interface Unit Interrupt Pending gt Messaging Unit Interrupt Pending Primary ATU Start BIST Interrupt Pending Bus Interface Unit Error Primary PCI Bridge Interface Error gt Secondary PCI Bridge Interface Error 3 i9609 RN RM I O Processor 80960 Outbound Doorbell 0 80960 Outbound Doorbell 1 80960 Outbound Doorbell 2 80960 Outbound Doorbell 3 i960 Core Processor pt 6 Interru Primary ATU Error Secondary ATU Error 3 Memory Controller Unit Error 3 DMA Channel 0 Error 3 DMA Channel 1 Error 3 DMA Channel 2 Error Messaging Unit Error 3 Application Accelerator Unit Error 3 NMI N C pt NMI Interru Latch IQ80960RM RN Evaluation Board Manual 4 4 4 5 i960 RM RN I O Processor Overview CPU Counter Timers The i960 RM RN I O processor is equipped with two on chip counter timers which are clocked with the i960 RM RN I O processor clock signal The i960 RM
88. fication Revision 2 1 allow the software on the IQ80960RM RN platform to search for devices on the secondary PCI bus and read and write the configuration space of those devices 5 2 MON960 Components The remaining sections of this chapter assume that MON960 is installed in the onboard Flash replacing IxWorks The IQ80960RM RN optional MON960 debug monitor consists of four main components Initialization firmware MONO60 extensions MON960 kernel Diagnostics example code These four components together are referred to as MON960 5 2 1 MON960 Initialization At initialization MON960 puts the IQ80960RM RN platform into a known functional state that allows the host processor to perform PCI initialization Once in this state the MON960 kernel and the MON960 extensions can load and execute correctly Initialization is performed after a RESET condition MON960 initialization encompasses all major portions of the 1960 RM RN I O processor and IQ80960RM RN platform including 80960JT core initialization Memory Controller initialization SDRAM initialization Primary PCI Address Translation Unit ATU initialization and PCI to PCI Bridge Unit initialization The IQ80960RM RN platform is designed to use the Configuration Mode of the 1960 RM RN I O processor Configuration Mode allows the 80960JT core to initialize and control the initialization process before the PCI host configures the i960 RM RN I O processor By utilizing Configuration Mo
89. ftware monitor that allows you to execute and debug programs written for 1960 processors in a non I O environment The monitor provides program download breakpoint single step memory display and other useful functions for running and debugging a program The IQ80960RM RN platform works with the source level debuggers provided with CTOOLS including GDB960 command line version and GDB960V GUI version MON960 Host Communications MON960 allows you to communicate and download programs developed for the IQ80960RM RN platform across a host system s serial port or PCI interface The IQ80960RM RN platform supports two methods of communication terminal emulation and Host Debugger Interface HDI Terminal Emulation Method Terminal emulation software on your host system can communicate to MON960 on the IQ80960RM RN platform via an RS 232 serial port The IQ80960RM RN platform supports port speeds from 300 to 115 200 bps Serial downloads to MON960 require that the terminal emulation software support the XMODEM protocol Configure the serial port on the host system for 300 115 200 baud 8 bits one stop bit no parity with XON XOFF flow control Host Debugger Interface HDI Method You may use a source level debugger such as Intel s GDB960 and GDB960V to establish serial or PCI communications with the IQ80960RM RN platform The MON960 Host Debugger Interface HDD provides a defined messaging layer between MON960 and the debugger For more i
90. g0 v0 20 Lo Aged SAS e aayrouvd sey n9 Aces GS ais gayi 5 1389599 1939705 V3UWUdS ye ANH SONS peg reor Sne guon SONS bg FOS 8 0 abog FASS g0 v0 zo 10 Aged coy Net US zu 01 80 HOLS 8705 vov 6 Fog zeye tov Zravs borsot 19415 2 j zy N9 Ext 9 OdNNOO Eon 9 IOdNNOO AEN v9 Dico zayeNs uS Tavs TA 910N9 pag iy e 6 SAS eg gey ON 610V peg ravs ge p IND eda oy 903 POV sg SROXOVS ozGVS 62 089 HV zg Tzdvs zv gea egy ASt YS 22095 sey aov 2109 Eg zeavs rev ee av SLONS reg avs 8591000 HOOV psg Tavs 2316 2075 os NS peg t6GVS z vs 1g 00v 9 aN9 sg 8iGVs gy 390 818 052 3638 08 vEGVS egy cav SEQV pog seavs ggy N9 00V avs Zg sgy aav enet Erg 96GVS aB EY 9 5 pag Vs sgy 00v S00V Egg Savs pzy QNS szav peg Szavs zey N9 1 0V req Save ysy 0Y 8AE pog 92075 D d V peg Zzovs ggypeav SOV ggg Ke sg 820 22 80 HONO egg OrQvs say Qv BLOND pea 4038 08 ge 38 9 800V ecg 8avs fao vo zo i0 Aged Tay 6 Bev leg 6zqvs y8vPASt pag TAVS 08075 023080 av peg Teqvs avs egy av Egg evavs ety ANS ETS vravs zay rov LOND ggg avs SOND Brg Datiprg zO3HS SvOV eg Sravs ayy N9 OV erg oravs zIN S Try OV peg Zravs Tavs Try tov eV ig 210 ory Ast erg 20 8ravs 6 SNS 678 eravs omy OY SON Bg 1595 5 A
91. grave gano 055091 on gvino VIN 88v gl aape E ZHNCEPETOSO 8 L S r 4 L 8 9 S 4 IL SO weus sevuv ewa 11690 10 NJAVH 8 AN H3ZAVNY 21007 Mud 3ON3IOS SZ NH09608 ML SWALSASOHOIN dii zr ep NO H rave N9 z Brod pr NS z 075 EH oND z Zod e 100308 tano AND tano gg aNo ra zi ra 600 E ra TVS 23 ra eed ER Ie TID3HS eano AND eano Tg No pz aNd Hi gz 0504 TH gz 215 Hi pz vod jii E fepdus zano AND zano THINS z 3H GND OH z isbd oH z evs OH z edd Ki z Zeps tano 8 0308 zaono Ez OSS 8 2500 8 p WS 6a p 900 fee Eee 5 1308 JSD3HS e500 595 2 z 86 H 7308 z ase z r500 z a 6 Fama FINOS 9500 WS a R 9500 z B2 ooa z FINDS EE dar Di zh D c IROS 3500 B OWS mo IF dines 6500 TYS In 391055 ents amp 01 60 80 20 IOdS EE EE EE prod be ke 1900 SVHS D Sroa pe pe 2504 pe 3SVOS e 9700 pe Le Bc t800 5c FMS Bc oa P L sive
92. ilable from Intel using the Host Debugger Interface HDI software interface Communication with the host computer via the primary PCI bus Downloads of ELF object files via the primary PCI bus or via the serial console port at rates up to 115 200 baud Downloads of ELF object files via the primary PCI bus On board erasure and programming of Intel 28F016S5 Flash ROM Memory display and modification capability Breakpoint and single step capability to support debugging of user code Disassembly of 1960 processor instructions 960 Extensions The monitor has been extended to include the secondary PCI bus initialization and also the BIOS routines which are contained in the PCI BIOS Specification Revision 2 1 Secondary PCI Initialization MONO60 extensions are responsible for initializing the devices on the secondary PCI bus of the IQ80960RM RN platform Secondary PCI initialization involves allocating address spaces Memory Memory Mapped I O and I O assigning PCI base addresses assigning IRQ values and enabling PCI mastership MON960 does not support devices containing PCI to PCI bridges and hierarchical buses IQ80960RM RN Evaluation Board Manual 5 5 MON960 Support for IQ80960RM RN I ntel 5 4 2 5 4 2 1 5 6 PCI BIOS Routines MON960 includes PCI BIOS routines to aid application software initialization of the secondary PCI bus The supported BIOS functions are described in the subsections that foll
93. ith this board 1 view the electronic tools catalog access http developer intel com design develop htm from the web IQ80960RM RN Evaluation Board Manual 1 3 Introduction 1 3 1 3 1 1 3 2 1 3 3 intel Tornado for 120 Software Development Toolset Tornado for I 0 is a complete toolset featuring an integrated development environment including a compiler assembler linker and debugger It also features a real time operating system IxWorks Real Time Operating System The IQ80960RM RN platforms are equipped with Wind River Systems Inc s Ix Works Ix Works provides for the elements of the L O standard an event driven driver framework host message protocols and executive modules for configuration and control Ix Works also allows for the writing of basic device drivers and provides NOS to driver independence TORNADO for LO provides a visual environment for building testing and debugging of I O drivers TORNADO Build Tools TORNADO for 1 0 includes a collection of supporting tools that provide a complete development tool chain These include the compiler assembler linker and binary utilities Also provided is an 1 0 module builder which creates L O loadable modules TORNADO Test and Debug Tools TORNADO for I50 test and debug tools include the dynamic loader the CrossWind debugger the WindSh interactive shell and a system browser The dynamic loader allows for interactive loading testing and re
94. ithout ECC rated at 10 ns should be used on the IQ80960RM RN platform The column labeled ECC determines if that particular memory configuration can be used with ECC SDRAM Configurations SDRAM SDRAM Total Memory Technology Arrangement Banks Row Column EGG Size 1 Yes 16 Mbytes 2M x8 11 9 2 Yes 32 Mbytes 16 Mbit 1 No 8 Mbytes 1M x 16 11 8 2 No 16 Mbytes 1 Yes 64 Mbytes 8Mx8 12 9 2 Yes 128 Mbytes 64 Mbit 1 No 32 Mbytes 4M x 16 12 8 2 No 64 Mbytes Flash ROM An E28F016S5 2 Mbytes Flash ROM is included on the IQ80960RM RN platform This Flash ROM contains IxWorks and may be used to store user applications Flash ROM Programming Two types of Flash ROM programming exist on the IQ80960RM RN platform The first is normal application development programming This occurs using IxWorks to download new software and the 80960JT core to write the new code to the Flash ROM During this time the boot sectors containing Ix Works are write protected The second type of Flash ROM programming is loading the boot sectors You will not be required to load the boot sectors except To load MON960 To load a new release of IxWorks To change between the check build and the free build of IxWorks The following steps are required to program the Flash ROM boot sectors 1 Set switch S1 s 1 and 2 to the on position Reset the board by cycling power on the workst
95. luation platform when it is depowered and or removed from the chassis the batteries will maintain the SDRAM for approximately 30 hours Once power is again applied the batteries will be fully charged in about 4 hours Installing the IQ80960RM RN Platforms in the Host System If you are installing the IQ80960RM RN platform for the first time visually inspect the board for any damage that may have occurred during shipment If there are visible defects return the board for replacement Follow the host system manufacturer s instructions for installing a PCI adapter The IQ80960RM RN platform is a full length PCI adapter and requires a PCI slot that is free from obstructions The IQ80960RM RN platform is taller than specified in the PCI Local Bus Specification Revision 2 1 The extended height of the board will require you to keep the cover off of your PC Refer to Chapter 3 for physical dimensions of the board Verify IQ80960RM RN Platform is Functional These instructions assume that you have already installed the IQ80960RM RN platform in the host system as described in Section 2 3 2 1 To connect the serial port for communicating with and downloading to the IQ80960RM RN platform connect the RS 232 cable provided with the IQ80960RM RN from a free serial port on the host system to the phone jack style connector on the IQ80960RM RN platform 2 Upon power up the red FAIL LED turns off indicating that the processor has passed its self test 3
96. ly for 16 Mbit devices and 4 pages per bank for 64 Mbit devices Simultaneously open pages allow for greater performance for sequential access distributed across multiple internal bus transactions Table 3 3 shows read and write examples of a single 8 byte access and for a multiple 40 byte access SDRAM Performance Cycle Type Table Clocks Performance Bandwidth Read Page Hit 8 bytes 7 76 Mbytes sec Read Page Miss 8 bytes 12 44 Mbytes sec Read Page Hit 40 bytes 11 240 Mbytes sec Read Page Miss 40 bytes 16 165 Mbytes sec Write Page Hit 8 bytes 4 132 Mbytes sec Write Page Miss 8 bytes 8 66 Mbytes sec Write Page Hit 40 bytes 8 330 Mbytes sec Write Page Miss 40 bytes 12 220 Mbytes sec Note that if ECC is enabled and you attempt a partial write less than 64 bits you will incur a penalty Because ECC is enabled the MCU will translate the write into a read modify write transaction Therefore for a single byte write the clock count will be 11 IQ80960RM RN Evaluation Board Manual In 3 2 2 Table 3 4 3 3 3 3 1 IQ80960RM RN Evaluation Board Manual Hardware Reference Upgrading SDRAM The IQ80960RM RN is equipped with 16 Mbytes of SDRAM with ECC inserted in the 168 pin DIMM socket The memory may be expanded by inserting up to a 128 Mbyte module into the DIMM socket The various memory combinations are shown in Table 3 4 Only 168 pin 3 3V SDRAM modules with or w
97. m memory controller Performs an optional boolean operation XOR on read data Transfers data write to memory controller The AA unit features 128 byte arranged as 8 byte x 16 deep store queue e Utilization of the 80960RN RM processor memory controller interface 232 addressing range on the 80960 local memory interface Hardware support for unaligned data transfers for the internal bus Full programmability from the 1960 core processor Support for automatic data chaining for gathering and scattering of data blocks IQ80960RM RN Evaluation Board Manual _ l ntel i9608 RM RN I O Processor Overview Figure 4 5 shows a simplified connection of the Application Accelerator to the 1960 RM RN I O Processor Internal Bus Figure 4 5 Application Accelerator Unit Application Accelerator Unit Packing Unpacking Data Queue Boolean Unit Unit 64 bit Internal Bus 4 8 Performance Monitor Unit The Performance Monitoring features aid in measuring and monitoring various system parameters that contribute to the overall performance of the processor The monitoring facility is generically referred to as PMON Performance Monitoring The facility is model specific not architectural its intended use is to gather performance measurements that can be used to retune refine code for better system level performance The PMON facility provided on the 1960 RM RN I O processor comprises One dedicated global Time
98. m memory map shown in Figure 4 2 IQ80960RM RN Evaluation Board Manual Intel 5 2 5 Table 5 1 5 2 6 MON960 Support for IQ80960RM RN Primary PCI Interface Initialization The IQ80960RM RN platform is a multi function PCI device On the primary PCI bus two functions from a PCI Configuration Space standpoint are supported Function 0 is the PCI to PCI Bridge of the 1960 RM RN I O processor which optionally provides access capability between the primary PCI bus and the secondary PCI bus Function 1 is the Primary ATU which provides access capability between the primary PCI bus and the local i960 bus The platform can be initialized into one of four modes Modes 0 and 3 are described below Initialization Modes swe SWE2 Mode Primary PCI Interface loe 0 ON 0 ON Mode 0 Accepts Transactions Held in Reset 0 ON 1 OFF Mode 1 Retries All Configuration Transactions Held in Reset 1 OFF 0 ON Mode 2 Accepts Transactions Initializes 1 OFF 1 OFF Mode 3 default Retries All Configuration Transactions Initializes When the IQ80960RM RN is operating in Mode 0 the processor core is held in reset allowing register defaults to be used on the Primary PCI interface This mode is used to program the onboard Flash with either KWORKS MON960 When the IQ80960RM RN platform is operating in Mode 3 the Configuration Cycle Disable bit in the Extended Bridge Control Register EBCR is set after
99. mary notations e g 255 is a decimal number and 1111 1111 is a binary number In some cases the letter B is added to binary numbers for clarity 1 8 Technical Support Up to date product and technical information is available electronically from Intel s World Wide Web WWW Location http www intel com Q80960RM and IQ80960RN Product Information http developer intel com design i960 For technical assistance electronic mail e mail provides the fastest route to reach engineers specializing in IQ80960RM and IQ80960RN issues Posting messages on the Embedded Microprocessor Forum at http support intle com newsgroups is also a direct route for IQ80960RM and IQ80960RN technical assistance See Section 1 8 2 Within the United States and Canada you may contact the Intel Technical Support Hotline See Section 1 8 1 for a list of customer support sources for the US and other geographical areas IQ80960RM RN Evaluation Board Manual 1 7 Introduction n 1 8 1 Intel Customer Electronic Mail Support For direct support from engineers specialing in 19609 Microprocessor issues send e mail in english to 960tools intel com 1 8 2 1 8 Questions and other messages may be posted to the Embedded Microprocessor Forum at http support intel com newsgroups Intel Customer Support Contacts Contact Intel Corporation for technical assistance for the IQ80960RM RN evaluation platform Country Liter
100. mplete C C language software development toolset for developing embedded applications to run on 1960 processors It contains a C C compiler the gcc960 and ic960 compiler driver programs an assembler runtime libraries a collection of software development tools and utilities and printed and on line documentation The MON960 Debug Monitor User s Guide fully describes the components of MON960 including MON960 commands the Host Debugger Interface Library HDIL and the MONDB EXE utility If you are using MON960 and the CTOOLS toolset refer to section Section 2 2 1 Installing Software Development Tools on page 2 1 See Chapter 1 for more information on the IxWorks and CTOOLS features The IQ80960RM RN evaluation boards are supplied with IxWorks intelligent real time operating system pre loaded into the on board Flash You also have the option of installing the MON960 debug monitor which is required if you are using the CTOOLS debugging tools GDB960 GDB960V or MONDB Section 3 3 1 describes the Flash ROM programming utility which allows you to load MON960 onto the platform or re load Ix Works Software Installation Installing Software Development Tools If you haven t done so already install your development software as described in its manuals All references in this manual to CTOOLS or CrossWind assume that the default directories were selected during installation If this is not the case substitute the appropriate path for the defa
101. n the 80960JT core can be used to receive PCI interrupts from the secondary PCI bus or these interrupts can be passed through to the primary PCI interface depending on the setting of the XINT Select bit of the PCI Interrupt Routing Select Register in the 1960 RM RN I O processor On IQ80960RM RN platform XINTO through XINT3 are configured to receive interrupts from the secondary PCI bus XINT4 and XINT5 on the 1960 RM RN I O processor may be connected to interrupt sources external to the processor On IQ80960RM RN platform XINT4 is connected to the loss of fan detect and XINT5 is connected to the 16C550 UART XINT6 XINT7 receive interrupts from internal sources NMI receives interrupts from internal sources and from an external source Since all of these interrupts accept signals from multiple sources a status register is provided for each of them to allow service routines to identify the source of the interrupt Each of the possible interrupt sources is assigned a bit position in the status register The interrupt sources for these lines are shown in Figure 4 3 On the IQ80960RM RN platform the NMI interrupt is not connected to any external interrupt source and receives interrupts only from the internal devices on the 1960 RM RN I O processor Note that all error conditions result in an NMI interrupt IQ80960RM RN Evaluation Board Manual 4 3 i960 RM RN I O Processor Overview Figure 4 3 i9609 RM RN I O Processor Int
102. nal 10 1 U10 IC SM LM339 SOIC 14 Semicond ctor LM339M 11 1 U8 IC SM MAX1651CSA SOIC 8 Maxim MAX1651CSA 12 1 U14 IC SM MAX712CSE SOIC 16 Maxim MAX712CSE 13 1 U17 IC SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 PROCESSOR frm Intel i960RM Intel 15 1 u12 VLSI I O UART 16C550 PLCC Texas TL16C550AFN Instruments 16 1 C65 CAP SM 0 47 uF 1206 Philips Philips 12062F474Z9BBO C2 C3 C10 C11 C18 C19 C26 C27 17 15 Geo CAP SM 0 01 uF 0805 Kemet C0805C103K5RAC C61 C68 C77 C83 C96 IQ80960RM RN Evaluation Board Manual A 5 Bill of Materials Table A 2 IQ80960RM Bill of Materials Sheet 2 of 5 Item Qty Location Part Description Manufacturer Manufacturer Part 18 81 C1 C4 C5 C6 C7 C8 C9 C12 C13 C14 C15 C16 C17 C20 C21 C22 C23 C24 C25 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C48 C49 C50 C51 C53 C59 C62 C66 C67 C69 C70 C71 C73 C79 C80 C81 C85 C86 C87 C94 C95 C97 C98 C99 C100 C101 C102 C108 C104 C105 C106 C107 C108 C109 C111 C112 C113 C114 C115 C116 C117 C120 C121 CAP SM 0 1 uF 0805 Philips 08052R104K8BB2 19 C110 CAP SM 18 pF 0805 Kemet C0805C180J5GAC 20 R27 R28 R SM 1 10 W 5 1 ohm 0805 Dale CRCW0805100JT 21 R60 R SM 1 10 W 5 10 ohm 0805 Dale CRCW208051000JT 22 R25
103. nformation on this interface see the MON960 Debug Monitor User s Manual 484290 HDI connection requests cannot be detected by MON960 if the user has already initiated a connection using a terminal emulator In this case the IQ80960RM RN platform must be reset before the debugger can connect to MON960 SPI610 JTAG Emulation System The SPI610 JTAG Emulation System from Spectrum Digital Inc is included in the IQ80960RM RN development kit It furnishes the default host development environment to evaluation board communication link based on the 1960 RM RN I O processor JTAG interface IQ80960RM RN Evaluation Board Manual 1 5 Introduction 1 6 Intel Refer to the SPI610 Reference Manual for JTAG emulation system installation and operation for both the Tornado and CTOOLS environment Optionally evaluation board serial port communications can be used for this communication link see Section 1 3 3 TORNADO Test and Debug Tools on page 1 4 About This Manual A brief description of the contents of this manual follows Chapter 1 Introduction Introduces the IQ80960RM and IQ80960RN Evaluation Board features This chapter also describes Intel s CTOOLS and WindRiver Systems IxWorks software development tools and defines notational conventions and related documentation Chapter 2 Getting Started Provides step by step instructions for installing the IQ80960RM or IQ80960RN platform in a host system and downl
104. nvas ioi S ZINS Syzww zINSS 90 0 vas 9 WSNOVS SIWVE9MOV S HNS Say 165 1 E Xegodus cv S OLN Sz Ny 0XINSS 8 38 0 8 S IIS S S038 gsosus 939705 8 Szy 0995 Wagos cuv EHE S 60305 maos S 577 zO3HS raos repy aS S IWNOIS 10 ANVONOOAS OS E Faas S rg 0039 Spziy 003HS lt t 8 13005 ery aS 7 z maas nme S e m e 10 ie 10 e e e e ge e d e e i e e e e e e ie it iD e e e e rd e 8 I P p p p p p p p p p p gt p p p p gt p p pP p gt p gt p gt p p gt gt p gt gt gt gt gt S5S8S85585885555555885S5859888988589888553 K 8 8 5 5 e 5 5 amp 5 2 2 8 O 8 9S S 9 8 2 2 39 93933333333993393339313393339333 m NS e lo lo lo lo o o o o o o o gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt 6 6 j 2 B 2 BBERESSREEEERSESSRESSPRECAR AEBS eee 01 60 80 S0 IOdS 8 L 9 S r
105. oading and executing an application program This chapter also describes Intel s software development tools the 960 Debug Monitor IXWORKS software installation and hardware configuration Chapter 3 Hardware Reference Describes the locations of connectors switches and LEDs on the IQ80960RM and IQ80960RN platforms Header pinouts and register descriptions are also provided in this chapter Chapter 4 i960 RM RN I O Processor Overview Presents an overview of the capabilities of the i960 RM RN I O processor and includes the CPU memory map Chapter 5 MON960 Support for IQ80960RM RN Describes a number of features added to MON960 to support application development on the i960 RM RN I O processor Appendix A Bill of Materials Shows complete parts list Q80960RM and IQ80960RN Evaluation Platforms Appendix B Schematics Complete set of schematics for the IQ80960RM and IQ80960RN Evaluation Platforms Appendix C PLD Code Example PLD code used on IQ80960RM and IQ80960RN evaluation boards for SDRAM battery backup Appendix D Recycling the Battery Information on the RBRC program and the locations of participating recycling centers IQ80960RM RN Evaluation Board Manual intel Introduction 1 7 Notational Conventions The following notation conventions are consistent with other i960 RM RN I O processor documentation and general industry standards or ov
106. ow SysPCIBIOSPresent sysFindPCIDevice SysFINDPCIClassCode sysGenerateSpecialCycle sysReadConfigByte sysReadConfigWord sysReadConfigD word sysWriteConfigByte sysWriteConfigWord sysWriteConfigDword sysGetIrqRoutingOptions sysSetPCIIrq These functions preserve as closely as possible the parameters and return values described in the PCI Local Bus Specification Revision 2 1 Functions that return multiple values do so by filling in the fields of a structure passed by the calling routine You can access these functions via a calls instruction The system call indices are defined in the MON960 source file PCI BIOS H The function prototypes are defined in the IORP_ASM H file sysPCIBIOSPresent This function allows the caller to determine whether the PCI BIOS interface function set is present and the current interface version level It also provides information about the hardware mechanism used for accessing configuration space and whether or not the hardware supports generation of PCI Special Cycles Calling convention int sysPCIBIOSPresent PCI BIOS INFO info Return values This function always returns SUCCESSFUL IQ80960RM RN Evaluation Board Manual In 5 4 2 2 5 4 2 3 960 Support for IQ80960RM RN sysFindPCIDevice This function returns the location of PCI devices that have a specific Device ID and Vendor ID Given a Vendor ID a Device ID and an Index the function returns the Bus Number
107. placement of individual object modules that comprise a driver CrossWind is an extended version of GDB960 Using it you can debug I O drivers by setting breakpoints on desired L O components A variety of windows display source code registers locals stack frame memory and so on WindSh allows you to communicate to the IQ80960RM RN platform via an RS 232 serial port The IQ80960RM RN platform supports port speeds from 300 to 115 200 bps The shell can be used to control and monitor L O drivers format send and receive driver messages examine hardware registers run automated 1 0 test suites The shell also provides essential debugging capabilities including breakpoints single stepping stack checking and disassembly IQ80960RM RN Evaluation Board Manual 1 4 1 1 4 1 1 1 4 1 2 1 4 1 3 1 5 Introduction CTOOLS Software Development Toolset Intel s 1960 processor software development toolset CTOOLS features advanced C C language compilers for the 1960 processor family CTOOLS development toolset is available for Windows 95 NT based systems and a variety of UNIX workstation hosts These products provide execution profiling and instruction scheduling optimizations and include an assembler a linker and utilities designed for embedded processor software development CTOOLS and the MON960 Debug Monitor In place of Ix Works the IQ80960RM RN platform can be equipped with Intel s MON960 an on board so
108. r IGQ80960RMWRN 5 1 Secondary PCI Bus Expansion Connectors sse nennen 5 1 MONYQ6O Components uu 12122 ce Hcet revue tet etie poe eI E ee Tae poe cas eed 5 1 5 2 1 MONSOO nitialiZatiOn indi ed eter Ee e e rx RE e ue AERE 5 1 5 2 2 80960JT Core Initialization u u 5 2 5 2 3 Memory Controller Initialization essen nnne 5 2 5 24 SDRAM Iritialization eret Perret tete Patet rte te e bert Ree biet ids 5 2 5 2 5 Primary PCI Interface Initialization u u 5 3 5 26 Primary ATU Initialization s u L tee ete dre e nee ate 5 3 5 2 7 Bridge InitialiZation uy u u S Sa Sus us 5 4 5 2 8 Secondary ATU Initlalization iecit deen edie 5 4 KEE 33 2 i ene E EPIO ec EXE D awa Pen dfe iE m s es 5 5 MONO60 EXIenSIONS oer oae ecce ea e Pri acct cote d e eee P ER EE 5 5 5 4 1 Secondary PCI Initialization sees 5 5 5 42 POL BIOS Boutines s u n n u ttt erret er eset Patet tete bet E 5 6 5 4 2 1 SysPGIBIOSPresent s u L a ae a ERR Ra EORR ukuka E 5 6 5 42 2 SySEIndP GIDOVIGG intente peace Pride peret cette cedant reete ek uad 5 7 5 4 2 3 sysFindPCIClassGode e nee Ine a tuat 5 7 5 4 2 4 sy
109. rave viv 319 Yavd SWOOST eq ss zz vo en save IOO VH _ ons gens ovo asos 3qoW isusave vig 300 1Susdvd LWOQS Ec Ws IV Lavy ces twee cave Ma ay 13 08 ec saved 513 een 5 MOL L vu 03x08 01 90 0340S en sie Ea ati sas Oldvy 513 Ben 1455 T SIVWOH tavy lt L tro vwou 213 0425 0555 ale IMS 259 222 gif ovu SVOS 3 ridva sig QV8 SVHSESN 3svus stave ers W8Sher twas zxidinr Siavg eive vu 08S i cr ovas SONO 125200 ovSi 05 en ave eig Vd Sez IVS 21100 10567 z0 90 108 Fog 5131309 INS pex us oe 92910 vasks z0 90 vas 30358 590809 eed oa MY 599100 T3MH OZV ws yy no 08 eared SvSoeq___s S 3 B evs 900 _ 2858 EOS mud ui io o5 0808 202 pH VS 90 190 sa ino Taos o5 999 9VSpcg svS ZHOS EA 808 VS Erg 6VS o g sino SaaS zEMesOS 0175 2 D s te egos ZEM zg 05 sg wS h d8HVONH Tano 905 i5 929 HI TIOHINOO AHOWSIA HYS ive fs yano saos 02319909 N4096 sg5s ssA989S CEU NDMOO FSS NIIOG 519110 7858 vei 808 hita H B grano Do0bD0o00o000000000000000000000002090 1no S G amp 58 o 5 6 6 5 5 amp 5 3 o6 o 9 95 M o Q 9S S o9 S 99 S MOL L 90 8 9 ERE amp
110. s suva 9v m ER g ale quo aye uc uva goHoisv4 8255 Ts za GIP 99 E 9 re xa T ng m 1 Nod El oevels D 3 g _ 918 good E o 3 veal uqi uvg Ey ase zinoa als Q B2 Wd 528 2 2 BR x 24 Lo e MZzg g NaHS 9 yow va Ine 85 29 bess amp ISSUXVA rit uH s REPO OER Ne v18 auk p g LWA 9 32 29 29 A Live IRFS Or01 8A91ATIVd e Ns 9050 10 Ace 7900 E 5 yia TT ene 20 19 8 yra ahg 5199 9 ysa s gt 90 80 i340 srr erie 255 ores are E 8 25 y rs o 90 0 0305 gri tz m9 zi e 3 o 0 8 2528 Ase mp IE owe T F685 ein 10 0S861 101 1H Vd 8 L 9 S v intel PLD Code MODULE BATT TITLE SDRAM Battery Backup Enable PATTERN 101 1809 01 REVISION AUTHOR J Neumann COMPANY Cyclone Microsystems Inc DATE CHIP 10 30 97 PALLV 16V8Z 20JI 1 20 98 Modify target device to PALLV16V8Z 20JI Initial release PRSTn PIN 9 Primary PCI reset SCKEO PIN 13 SDRAM bank 0 clock enable SCKEI PIN 16 SDRAM bank 1 clock enable OUTO PIN 14 SCKEO output enable OUTI PIN 17 SCKEI output enable EQUATIONS If SDRAM clock enable goes low SDRAM clock enable must be held low to ensure that the SDRAM is held in auto refresh mode Reset going high will release the hold on S
111. sGenerateSpecialCycle U nennen 5 8 5 4 2 5 sysReadConfigByte i 5 8 5 4 2 6 sysReadConfigWOrd u usu uns rE EE aait 5 9 5 4 2 7 sysReadConfigDword U nnne 5 9 5 4 2 8 sysWriteConfigByte 1 5 10 5 4 2 9 sysWriteConfigWord 11 u 5 10 5 4 2 10 sysWriteConfigDword sseeeeeesseeeneeneenn nennen 5 11 5 4 2 11 sysQGetlrqRoutingOptions a 5 11 5 4 2 12 SysSetPGlltq uuu yin eats pees Geter eee eed oe ae 5 12 5 4 3 Additional MON960 Commands U 5 12 5 4 9 1 pei UUNY serierna 5 12 Diagnostics Example CGo006e s u eene enne enne en 5 12 5 5 1 Board Level Diagnostics ceecee a 5 12 5 5 2 Secondary PCI Diagnostics sa ulio aa T a 5 12 Bill of Materials y ee e ed e tet A 1 SCHEMALICS si 2 Soie EEG Eun B 1 u S utu toit ied diuitiis C 1 Recycling the Battery sua ener D 1 IQ80960RM RN Evaluation Platform Board Manual intel Figures 1 1 IQ80960RM IQ80960RN Platform Functional Block 1 1 1 2 IQ80960RN Platform Physical Diagram sese nen enne nnns 1 2 3 1 LE
112. t S1 1 RST_MODE ON holdin rest OFF OFF allows processor initialization Determines if the Primary PCI interface will be disabled S1 2 RETRY ON allows Primary PCI configuration cycles to occur OFF OFF retries all Primary PCI configuration cycles Notifies Memory Controller of the SDRAM width S1 3 32BITMEM_EN ON Memory Controller utilizes 32 bit SDRAM access protocol OFF OFF Memory Contoller utilizes 64 bit SDRAM access protocol Determines whether Secondary PCI bus is a 32 or 64 bit bus 51 42 32BITPCI_EN ON indicates Secondary PCI bus is 32 bit bus OFF OFF indicates Secondary PCI bus is a 64 bit bus a This switch is active for IQ80960RN ONLY IQ80960RM RN Evaluation Board Manual 3 7 Hardware Reference I ntel 3 10 Figure 3 1 3 10 1 Table 3 10 User LEDs The IQ80960RM RN platform has a bank of eight user programmable LEDs located on the upper edge of the adapter board These LEDs are controlled by a write only register and used as a debugging aid during development Software can control the state of the user LEDs by writing to the LED Register located at E004 0000H Each of the eight bits of this register correspond to one of the user LEDs Clearing a bit in the LED Register by writing a 0 to it turns the corresponding LED on while setting a bit by writing a 1 to it turns the corresponding LED off Resetting the IQ80960RM RN platform resul
113. t This Malu ul m 1 6 Notational ConVventlons sez eee 1 7 TOCHMICAl SUP POM MEM 1 8 1 7 1 Intel Customer Electronic Mail Support 1 8 1 7 2 Intel Customer Support Comais LIU 1 8 1 7 9 Related Information uuu otro intent tane 1 9 Getting Started TT 2 1 Pre Installation Considerations ULU nn EEE nennen 2 1 So wale 2 1 2 2 1 Installing Software Development Tools 1 uu 2 1 Hardware Installatigris iced niter ed tse nr vetera a do v Shay tee 2 2 2 9 1 Patery Backup ul u unu E Saa sua 2 2 2 3 2 Installing the IQ80960RM RN Platforms in the Host System 2 2 2 3 3 Verify IQ80960RM RN Platform is Functional uu u 2 2 Creating and Downloading Executable Files 2 3 2 4 44 Sample Download and Execution Using 9 2 3 Hardware Reference ecciesie d ecc e cdd d t v ne t dee ev dee 3 1 Power Hegulrermernts He eR etre eu gus euet vov de Qasa 3 1 SDRAM sss ks 3 1 3 2 1 SBRAM PFerforimarce eite eene pup nubes vecta SENES SAAE ue cu 3 2 3 2 2 Upgrading SDRAM t x t sundae ces usen aux Exe ne ERR usaha 3 3 Flash
114. tel IQ80960RM RN Evaluation Platform Board Manual February 1999 Order Number 273160 004 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The IQ80960RM RN may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before pla
115. ts in clearing the register and turning all the LEDs on The LED Register bitmap is shown in Figure 3 1 The user LEDs are numbered in descending order from left to right with LED7 being on the left when looking at the component side of the adapter LED Register Bitmap User LED 7 User LED 6 User LED 5 User LED 4 User LED 3 User LED 2 User LED 1 User LED 0 User LEDs During Initialization MON960 indicates the progress of its hardware initialization on the user LEDs In the event that initialization should fail for some reason the number of lit LEDs can be used to determine the cause of the failure Table 3 10 lists the tests that correspond to each lit LED Start up LEDs MON960 LEDs Tests LED 0 SDRAM serial EEPROM checksum validated LED 1 UART walking ones test passed LED 2 DRAM walking ones test passed LED 3 DRAM multiword test passed LED 4 Hardware initialization started LED 5 Flash ROM initialized LED 6 PCI to PCI Bridge initialized LED 7 UART internal loopback test passed IQ80960RM RN Evaluation Board Manual Intel Hardware Reference Table 3 11 lists the connectors and LEDs Table 3 11 1Q80960RM RN Connectors and LEDs Item Description J1 J4 Secondary PCI bus expansion connector J5 168 pin SDRAM DIMM socket J6 JTAG connector J7 Serial port connector J8 Logic analyzer connector for flash ROM bus J10
116. ty Location Part Description Manufacturer Manufacturer Part BT1 BT2 61 8 EIS 2 Battery Clips PC Snap In AA Keystone 92 BT7 BT8 62 1 1019 PALLV16V8Z 20JI AMD PALLV16V8Z 20JI 1 lun MEM Flash E28F016S5 090 TSOP Intel E28F016S5 090 BT1 BT2 64 8 E Ere Battery AA NiCd 600 mA Hour SAFT NIC AA 600 SAFT BT7 BT8 65 1 U15 HeatSink Fan Assy 80960RN RM Panasonic UDQFNBEOIF 66 CAP SM 0 22 uF 1206 Philips 12062E224M9BB2 67 8 E C75 GAP TANT SM 220 pF 10 V 7343 AVX TPSE227K010R010 68 4 car eae CAP TANT SM 47 pF 16 V 7343 AVX TPSD476K016R015 69 1 CAP TANT SM 33 uF 10 V 7343 Sprague 293D336X9016D2T 70 4 m cH CAP TANT SM 4 7 uF 35 V 7343 Sprague 293D475X9035D2T 1 CAP TANT SM 22 uF 20 V 7343 Sprague 293D226X9020D2T 72 1 C74 CAP TANT SM 1 uF 16 V 3216 Sprague 293D105X0016A2T 73 2 C52 C54 CAP TANT SM 10uF 25 35 V Sprague 293D1060025D2T 74 1 C56 CAP TANT SM 100 pF 10 V 7343 AVX TPSD107K010R0100 75 1 C64 CAP TANT SM 330 pF 6 3 V 7343 AVX TPSE337K063R0100 76 3 eno e CAP SM 0 047 uF 0805 Kemet C0805C473K5RAC 77 1 R46 Res SM 1 W 1 0 012 ohm 2512 Dale WSL 2512 R012 78 1 Rei Res SM 1 W 196 0 05 ohm 2512 Dale WSL 2512 R050 79 1 R52 Resistor SM 1 2 W 596 100 ohm Beckmen BCR 1 2 101 JT R1 R31 80 7 Be By Resistor Pk SM RNC4R8P 2 7 Kohm CTS 742083272JTR R45 81 2 R40 R55 Resistor Pk SMRNC4R8P 22 ohm CTS 742083220JTR 82 2 R
117. ult path wherever file locations are referenced in this manual IQ80960RM RN Evaluation Board Manual 2 1 Getting Started ntel 2 3 Warning 2 3 1 2 3 2 2 3 3 2 2 Hardware Installation Follow these instructions to get your new IQ80960RM RN platform running Be sure all items on the checklist were provided with your IQ80960RM RN Static charges can severely damage the IQ80960RM RN platforms Be sure you are properly grounded before removing the IQ80960RM RN platform from the anti static bag Battery Backup Battery backup is provided to save any information in SDRAM during a power failure The 1Q80960RM RN platform contains four AA NiCd batteries a charging circuit and a regulator circuit The batteries installed in the IQ80960RM RN platform are rated at 600 mA Hr SDRAM technology provides a simple way of enabling data preservation through the self refresh command When the processor receives an active Primary PCI reset it issues the self refresh command and drives the SCKE signals low Upon seeing this condition a PAL on the IQ80960RM RN platform holds SCKE low before the processor loses power The batteries maintain power to the SDRAM and the PAL to ensure self refresh mode When the PAL detects PRST returning to inactive state the PAL releases the hold on SCKE The battery circuit can be disabled by removing the batteries LED CR4 indicates when the SDRAMs have sufficient power If the batteries remain in the eva
118. umber int function number int register number 0 2 4 254 UINT16 data Return values This function returns SUCCESSFUL when the indicated word was read correctly or ERROR when there is a problem with the parameters 5 4 2 7 sysReadConfigDword This function allows the caller to read individual longs 32 bits from the configuration space of a specific device The Register Number parameter must be a multiple of four i e bits 0 and 1 must be set to 0 Calling convention int sysReadConfigDword int bus number int device number int function number int register number 0 4 8 252 UINT32 data Return values This function returns SUCCESSFUL when the indicated long was read correctly or ERROR when there is a problem with the parameters IQ80960RM RN Evaluation Board Manual 5 9 MON960 Support for IQ80960RM RN 5 4 2 8 5 4 2 9 5 10 sysWriteConfigByte Calling convention int sysWriteConfieByte Int bus_number Int device_number Int function_number Int register_number UINT8 data Return values sysWriteConfigWord Calling convention int sysWriteConfig Word int bus_number int device_number int function_number int register_number UINT16 data Return values intel This function allows the caller to write individual bytes to the configuration space of a specific device 0 1 2 255 This function returns SUCCESSFUL wh
119. valid address on the IQ80960RM RN platform MON960 aborts the download Sample Download and Execution Using GDB960 This example shows you how to use GBD960 to download and execute a file named myapp via the serial port Invoke GDB960 From a Windows 95 NT command prompt issue the command gdb960 r com2 myapp This command establishes communication and downloads the file myapp To execute the program enter the command from the GDB960 command prompt gdb960 run More information on the GDB960 commands mentioned in this section can be found in the GDB960 User s Manual IQ80960RM RN Evaluation Board Manual 2 3 intel Hardware Reference 3 3 1 Table 3 1 Table 3 2 3 2 IQ80960RM RN Evaluation Board Manual Power Requirements The IQ80960RM RN platform draws power from the PCI bus The power requirements of the 1Q80960RM RN platforms are shown in Table 3 1 and Table 3 2 The numbers do not include the power required by a PCI card s mounted on one or more of the IQ80960RM RN platforms four expansion slots IQ80960RN Platform Power Requirements Voltage Typical Current Maximum Current 43 3 V 0 V 0v 5 V 1 45A 1 96 A 12 V 286 mA 485 mA 12 V 1 1 NOTE Does include the power required by PCI mounted the IQ80960RN platform 3 3V for 80960RN Processor created on board from 5V IQ80960RM Platform Power Requirements

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