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Analog Devices ADSP-2181 Network Card User Manual

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1. 128 97 PFO WR RD IOMS BMS DMS CMS GND Vpp PMS A0 A1 A2 A3 128L PQFP A4 28mm x 28mm AS TOP VIEW AG PINS DOWN A7 XTAL CLKIN GND CLKOUT GND Vpp A8 A9 A10 A11 A12 A13 IRQE MMAP 32 65 33 64 FLO FL1 FL2 DTO DRO SCLKO C BGH Vpp GND DT1 FO TFS1 IRQ1 GND DR1 FI SCLK1 ERESET EMS EE ELIN EINT RFSO RFS1 IRQO TFSO ECLK ELOUT IRQL1 IRQLO RESET 34 REV 0 ADSP 2181 ADSP 2183 PQFP Pin Configurations PQFP Pin PQFP Pin PQFP Pin PQFP Pin Number Name Number Name Number Name Number Name 1 PFO 33 PWD 65 EBR 97 D23 2 WR 34 IRQ2 66 BR 98 GND 3 RD 35 BMODE 67 EBG 99 IWR 4 IOMS 36 PWDACK 68 BG 100 IRD 5 BMS 37 IACK 69 VDD 101 IAD 15 6 DMS 38 BGH 70 DO 102 IAD 14 7 CMS 39 VDD 71 D1 103 IAD 13 8 GND 40 GND 72 D2
2. ADSP 2181 Parameter Min Max Unit Memorv Read Timing Requirements trop RD L ow to Data Valid 0 5tck 9 w ns taa A0 A13 xMS to D ata Valid 0 75tck 10 5 w ns trou Data Hold from RD High 0 ns Switching Characteristics tap RD Pulse Width OQ Stc 5 w ns terp CLKOUT HightoRDLow _ 0 25tc 5 0 25tck 7 ns tasR A0 A13 xMS Setup before RD Low 0 25tc 6 ns taDA A0 A13 xMS Hold after RD D easserted 0 25tc 3 ns tawR RD High to RD or WR Low 0 5tck 5 ns ADSP 2183 28 8 MHz Parameter Min Max Unit Memory Read Timing Requirements _ trop RD Low to Data Valid 0 5tck 9 w ns taa A0 A13 xMS to D ata Valid 0 75tc 12 5 w ns trou Data Hold from RD High 0 ns Switching Characteristics tap RD PulseWidth 0 5tck 5 w ns tcro CLKOUT HightoRDLow _ 0 25tck 5 0 25tck 7 ns tasr A0 A13 xMS Setup before RD Low 0 25tc 6 ns tnpA A0 A13 xMS H old after RD D easserted 0 25tc 3 ns tawR RD High to RD or WR Low 0 5tck 5 ns w wait states x tc xMS PMS DMS CMS IOMS BMS CLKOUT o Figure 25 Memory Read REV 0 23 ADSP 2181 ADSP 2183 ADSP 2181 ADSP 2183 Parameter Min Max Unit Memorv Write Switching C haracteristics tow Data Setup before WR High 0 5tcek 7 W ns toy Data H old after WR High 0 25tc 2 ns twp WR Pulse Width Q 5tck 5 w ns twoe WR Low to Data Enabled 0 ns tasw A0 A13 xMS Setup before WR Low 0 25tcx 6 ns topr D at
3. Example teku 0 5tc 7 ns 0 5 30 ns 7 ns 8 ns 13 ADSP 2181 ADSP 2183 ADSP 2181 ENVIRONMENTAL CONDITIONS Ambient T emperature Rating Tame 7 T case PD x60c4 T case Case T emperature in C PD Power Dissipation in W 0c4 T hermal Resistance C ase to A mbient 8 Thermal Resistance Junction to A mbient 8 c Thermal Resistance Junction to C ase Package Oya jc Oca TQFP 50 C W 2 C W 48 C W PQFP 41 C W 10 C W 31 C W 1000 Vpp 5 5V 4 Popes T 100 a E 10 e 3 0 5 25 55 85 TEMPERATURE C NOTES 1 REFLECTS ADSP 2181 OPERATION IN LOWEST POWER MODE SEE SYSTEM INTERFACE CHAPTER OF THE ADSP 2100 FAMILY USER S MANUAL FOR DETAILS 2 CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS Figure 8 Power Down Supply Current Typical POWER DISSIPATION To determine total power dissipation in a specific application the following equation should be applied for each output C xVpp x f C load capacitance f output switching frequency Example In an application where external data memory is used and no other outputs are active power dissipation is calculated as follows A ssumptions External data memory is accessed every cycle with 5096 of the address pins switching External data memory writes occur every other cycle with 5096 of the data pi
4. GND Vpp IAD6 IAD7 IAD8 IAD9 IAD10 IAD11 IAD12 IAD13 IAD14 IAD15 IRD IWR 128 103 1 102 IAL GND PF3 D23 PF2 D22 PF1 D21 PFO D20 WR D19 RD D18 IOMS D17 BMS D16 DMS D15 CMS GND GND Vpp Vpp GND PMS D14 A0 D13 A1 D12 A2 D11 A3 TOP VIEW D10 A4 PINS DOWN D9 A5 D8 A6 D7 A7 D6 XTAL D5 CLKIN GND GND D4 CLKOUT D3 GND D2 Vpp D1 A8 DO A9 Vpp A10 BG A11 EBG A12 BR A13 EBR IRQE EINT MMAP ELIN PWD ELOUT IRQ2 ECLK 38 65 39 64 a Si6 6 828 A IA g gza ogg Er orErOorgugu sz oz O9mim a LL lu ul l ie REV O 31 ADSP 2181 ADSP 2183 TQFP Pin Configurations TQFP Pin TQFP Pin TQFP Pin TQFP Pin Number Name Number Name Number Name Number Name 1 IAL 33 A12 65 ECLK 97 D19 2 PF3 34 A13 66 ELOUT 98 D 20 3 PF2 35 IRQE 67 ELIN 99 D21 4 PF1 36 MMAP 68 EINT 100 D22 5 PFO 37 PWD 69 EBR 101 D23 6 WR 38 IRQ2 70 BR 102 GND 7 RD
5. ADSP 2183 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit Vpp Supply Voltage 3 0 3 6 3 0 3 6 V Tams Ambient Operating T emperature 0 70 40 85 C ELECTRICAL CHARACTERISTICS K B Grades Parameter Test Conditions Min Max Unit Vin Hi Level Input Voltage 9 Vpp 2 max 2 0 V Vin Hi Level CLKIN Voltage 9 Vpp max 2 2 V Vu Lo L evel Input Voltage 3 9 Vpp min 0 4 V Vou Hi Level Output Voltage gt 8 Vpp 2 min lou 2 0 5 mA 2 4 V Vop min lon 100 pA Von 0 3 V VoL Lo L evel Output Voltage 5 Vpp min lo 2 MA 0 4 V liu H i L evel Input Current 9 Vpp max Vin 7 Vpp max 10 WA lu Lo L evel Input Current 9 Vpp max Vin 0V 10 uA lozu T hree State L eakage C urrent 9 Vpp max Vin Vpp max 10 uA loz T hree State L eakage C urrent 9 Vpp max Viy 0 V8 10 uA lop Supply Current Idle 1 9 Vpp max tck 34 7 ns 9 mA Ipp Supply Current Dynamic 11 9 Vpp max tek 34 7 ns 54 mA C Input Pin Capacitance 1 Vy 22 5 V fiy 1 0 M Hz Tame 25 C 8 pF Co Output Pin Capacitance 13 4 Vin 2 5V fin 1 0 M H Z Tams 25 C 8 pF NOTES IBidirectional pins D0 D23 RFSO RFS1 SCLKO SCLK1 TFSO TFS1 IADO IAD 15 PFO PF7 Input only pins RESET IRQ2 BR M MAP DRO DR1 PWD IRQLO IRQLI IRQE IS IRD IWR IAL 3Input only pins CLKIN RESET IRQ2 BR MM AP DRO DR1 IS IAL I
6. IRQLI 2 L evel Sensitive Interrupt Requests IRQE 1 Edge Sensitive Interrupt Request BR l Bus Request Input BG 1 0 Bus Grant Output BGH 1 o Bus Grant Hung Output PMS 1 o Program M emory Select Output DMS 1 0 D ata M emory Select Output BMS 1 O Byte M emory Select O utput IOMS 1 0 I O Space M emory Select Output CMS 1 0 Combined M emory Select Output RD 1 O M emory Read Enable Output WR 1 o M emory Write Enable Output MMAP 1 M emory M ap Select Input BMODE 1 l Boot Option Control Input CLKIN XTAL 2 Clock or Quartz C rystal Input Pin of Input Name s Pins Output Function CLKOUTJ1 O Processor Clock Output SPORTO 5 1 0 Serial Port I O Pins SPORT1 5 1 0 Serial Port 1 or Two External IRQs Flag In and Flag Out IRD IWR 2 IDMA Port Read Write Inputs IS 1 IDMA Port Select IAL 1 IDM A Port Address Latch Enable IAD 16 1 0 IDMA Port Address D ata Bus IACK 1 o IDMA Port Access Readv Acknowledge PWD 1 Powerdown Control PWDACK 1 o Powerdown Control FLO FL1 FL2 3 0 Output Flags PF7 0 8 1 0 Programmable I O Pins EE 1 ku Emulator Only EBR 1 Emulator Only EBG 1 Emulator Only ERESET 1 Emulator Only EMS 1 Emulator Only EINT 1 Emulator Only ECLK 1 Emulator Only ELIN 1 i Emulator Only ELOUT 1 Emulator Only GND 11 Ground Pins VDD 6 Power Supplv Pins T hese ADSP 2181 AD SP 2183 pins must be
7. and use either DMS or PMS as the additional address bit The CMS pin functions like the other memory select signals with the same timing and bus request logic A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal All enable bits default to 1 at reset except the BMS bit Byte Memory T he byte memory space is a bidirectional 8 bit wide external memory space used to store programs and data Byte memory is accessed using the BD M A feature T he byte memory space con sists of 256 pages each of which is 16K x 8 T he byte memory space on the AD SP 2181 AD SP 2183 sup ports read and write operations as well as four different data for mats T he byte memory uses data bits 15 8 for data T he byte memory uses data bits 23 16 and address bits 13 0 to create a 22 bit address T his allows up to a 4 meg x 8 32 megabit ROM or RAM to be used without glue logic All byte memory accesses are timed by the BM WAIT register Byte Memory DMA BDMA T he Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space TheBDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8 16 or 24 bit word transferred TheBDMA circuit supports four different data formats which are selected by the BT Y PE register field T he appropriate num ber of 8 bit accesses are
8. 104 IAD 12 9 VDD 41 IRQLO 73 D3 105 IAD11 10 PMS 42 IRQLI 74 D4 106 IAD 10 11 A0 43 FLO 75 GND 107 IAD9 12 A1 44 FL1 76 D5 108 IAD8 13 A2 45 FL2 71 D6 109 IAD7 14 A3 46 DTO 78 D7 110 IAD6 15 A4 47 TFSO 79 D8 111 VDD 16 A5 48 RFSO 80 D9 112 GND 17 A6 49 DRO 81 D10 113 IAD5 18 A7 50 SCLKO 82 Dil 114 IAD4 19 XTAL 5l DTI FO 83 D12 115 IAD3 20 CLKIN 52 TFSI IRO1 84 D 13 116 IAD2 21 GND 53 RFSI IRQO 85 D14 117 IAD1 22 CLKOUT 54 GND 86 GND 118 IADO 23 GND 55 DRI FI 87 VDD 119 PF7 24 VDD 56 SCLK1 88 GND 120 PF6 25 A8 57 ERESET 89 D15 121 PF5 26 A9 58 RESET 90 D16 122 PF4 27 A10 59 EMS 91 D17 123 GND 28 All 60 EE 92 D18 124 IS 29 A12 61 ECLK 93 D 19 125 IAL 30 A13 62 ELOUT 94 D 20 126 PF3 31 IRQE 63 ELIN 95 D21 127 PF2 32 MMAP 64 EINT 96 D22 128 PF1 REV 0 35 ADSP 2181 ADSP 2183 OUTLINE DIMENSIONS 128 Lead Metric Plastic Quad Flatpack PQFP e o gt TOP VIEW PINS DOWN jie gt fe B e exe mE 2790 28002810 1o 1102 1106 D E 2275 as 2usr 0974 0976 oss os os 36 REV 0 ADSP 2181 ADSP 2183 ORDERING GUIDE Part Number Ambient Temperature Range Instruction Rate MHz Package Description Package Option ADSP 2181K ST 115 ADSP 2181BST 115 ADSP 2181K S 115 ADSP 2181BS 115 ADSP 2181K ST 133 ADSP 2181BST 133 AD SP 2181K S 133 AD SP 2181BS 133 ADSP 2183K ST 115 ADSP 2183BS
9. 2183 s I O memory space are as follows Syntax IO addr dreg dreg 10 addr where addr is an address value between 0 and 2047 and dreg is any of the 16 data registers 10 23 ARO AR1 10 17 Description Thel O space read and write instructions move data between the data registers and the 1 O memory space Examples DESIGNING AN EZ ICE COMPATIBLE SYSTEM T he AD SP 2181 AD SP 2183 has on chip emulation support and an ICE Port a special set of pins that interface to the EZ ICE T hese features allow in circuit emulation without replacing the target system processor by using only a 14 pin connection from the target system to the EZ ICE T arget systems must have a 14 pin connector to accept the EZ IC E s in circuit probe a 14 pin plug See the AD SP 2100 F amily EZ T ools data sheet for com plete information on ICE products ThelCE Port interface consists of the following AD SP 2181 AD SP 2183 pins EBR EBG ERESET EMS EINT ECLK ELIN ELOUT EE 10 REV 0 ADSP 2181 ADSP 2183 T hese AD SP 2181 A D SP 2183 pins must be connected only to the EZ ICE connector in the target svstem T hese pins have no function except during emulation and do not require pull up or pull down resistors T he traces for these signals between the AD SP 2181 AD SP 2183 and the connector must be kept as short as possible no longer that 3 inches T he following pins are also used by the EZ ICE BR BG RESET GND TheEZ ICE us
10. 5 shows the memory map in this configuration PROGRAM MEMORY ADDRESS Ox3FFF INTERNAL 8K PMOVLAY 0 MMAP 1 0x2000 0x1 FFF 8K EXTERNAL 0x0000 Figure 5 Program Memory MMAP 1 Data Memory The ADSP 2181 AD SP 2183 has 16 352 16 bit words of inter nal data memory In addition the AD SP 2181 AD SP 2183 allows the use of 8K external memory overlays Figure 6 shows the organization of the data memory DATA MEMORY ADDRESS Ox3FDF 32 MEMORY MAPPED REGISTERS INTERNAL 8160 WORDS 0x2000 Ox1FFF 8K INTERNAL DMOVLAY 0 OR EXTERNAL 8K DMOVLAY 1 2 0x0000 Figure 6 Data Memory ADSP 2181 ADSP 2183 T here are 16 352 words of memory accessible internally when the DM OVLAY register is set to 0 When DM OVLAY is set to something other than 0 external accesses occur at addresses 0x0000 through Ox1FFF T he external address is generated as shown in T able III Tablelll DMOVLAY Memory A13 A12 0 0 Internal JNot Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x0000 and Ox1F FF 2 External 1 13 LSBs of Address Overlay 2 Between 0x0000 and Ox1F FF T his organization allows for two external 8K overlays using only the normal 14 address bits All internal accesses complete in one cycle Accesses to external memory are timed using the wait states specified by the DWAIT register I O Space T he AD SP 2181 AD SP 2183 supports a
11. ADSP 2183 ADSP 2181 Parameter Min Max Unit IDMA Read Long Read Cycle Timing R equirenents tika IACK Low before Start of Read 0 ns Unp Duration of Read 15 ns Switching Characteristics kun IACK H igh after Start of Read 15 ns tikos IAD 15 0 Data Setup before IACK Low 0 5tck 10 ns tikoH IAD 15 0 Data H old after End of Read 0 ns kpp IAD 15 0 Data Disabled after End of Read 10 ns tiane IAD 15 0 Previous Data Enabled after Start of Read 0 ns tirov IAD 15 0 Previous D ata Valid after Start of Read 15 ns tiRDHI IAD 15 0 Previous Data H old after Start of Read DM PM 1 2tck 5 ns tiRDH2 IAD 15 0 Previous Data H old after Start of Read PM 2 tck 5 ns ADSP 2183 28 8 MHz Parameter Min Max Unit IDMA Read Long Read Cycle Timing Requirements tice IACK Low before Start of Read 0 ns tire Duration of Read 15 ns Switching Characteristics tikHR IACK High after Start of Read 17 ns tikos IAD 15 0 Data Setup before IACK Low 0 5tck 10 ns tikwi IAD 15 0 Data Hold after End of Read 0 ns kpp IAD 15 0 Data Disabled after End of Read 10 ns tIRDE IAD 15 0 Previous D ata Enabled after Start of Read 0 ns tirDv IAD 15 0 Previous D ata Valid after Start of Read 15 ns tiRDHI IAD 15 0 Previous D ata H old after Start of Read DM PM 1 2tck 5 ns tiRDH2 IAD 15 0 Previous Data H old after Start of Read PM 2 tck 5 ns NOTES Istart of Read IS Low and IRD Low End of Read IS High or I
12. CLOCK FREQUENCY REDUCTION App MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY 50 OF THE INSTRUCTIONS ARE MULTIFUNCTION TYPES 1 4 5 12 13 14 30 ARE TYPE 2 AND TYPE 6 AND 20 ARE IDLE INSTRUCTIONS Figure 9 Power vs Frequency 14 IDLE 16 IDLE 128 REV O ADSP 2181 ADSP 2183 ADSP 2181 CAPACITIVE LOADING Figures 10 and 11 show the capacitive loading characteristics of the AD SP 2181 RISE TIME 0 4V 2 4V ns 0 50 100 150 200 250 300 C pF Figure 10 Typical Output Rise Time vs Load Capacitance C at Maximum Ambient Operating Temperature NOMINAL 2 4 6 VALID OUTPUT DELAY OR HOLD ns 0 50 100 150 200 250 CL pF Figure 11 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out put high or low voltage to a high impedance state T he output disable time tpis is the difference of tyeasurep and tpecav as shown in the Output Enable D isable diagram T he time is the interval from when a reference signal reaches a high or low volt age level to when the output voltages have changed by 0 5 V from the measured output high or low voltage T he decay time REV 0 tpecay is dependent o
13. Maximum Ambient Operating Temperature TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out put high or low voltage to a high impedance state T he output disable time tpis is the difference of tueasurep and tpecay as shown in the Output Enable D isable diagram T he time is the interval from when a reference signal reaches a high or low volt age level to when the output voltages have changed by 0 5 V from the measured output high or low voltage T he decay time tpecav is dependent on the capacitive load C and the current load i on the output pin It can be approximated by the fol lowing equation C 0 5V tbecay I REV 0 from which tois ty EASURED toecay is calculated If multiple pins such as the data bus are dis abled the measurement value is that of the last pin to stop driving 3 0V INPUT 1 5V 0 0V 2 0V OUTPUT 1 5V 0 3V Figure 19 Voltage Reference Levels for AC Measure ments Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when that have made atransition from a high impedance state to when they start driving T he output enable time tena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in the Output Enable D isable diagram If multi
14. SP 2183 has two mechanisms to allow au tomatic loading of the on chip program memory after reset T he method for booting after reset is controlled by the M M AP and BM ODE pins as shown in T able VI BDMA Booting When theBM ODE and MM AP pins specify BDM A booting MMAP 0 BMODE 0 the ADSP 2181 AD SP 2183 ini tiates a BDMA boot sequence when reset is released T he REV 0 Table VI Boot Summary Table MMAP BMODE Booting Method 0 0 BDM A feature is used in default mode to load the first 32 program memory words from the byte memory space Program execution is held off until all 32 words have been loaded IDMA feature is used to load any inter nal memory as desired Program execu tion is held off until internal program memory location 0 is written to Bootstrap features disabled Program execution immediately starts from location 0 BDMA interface is set up during reset to the following defaults when BDM A booting is specified the BDIR BM PAGE BIAD and BEAD registers are set to 0 the BT Y PE register is set to 0 to specify program memory 24 bit words and the BWCOUNT register is set to 32 T his causes 32 words of on chip program memory to be loaded from byte memory T hese 32 words are used to set up the BD M A to load in the remaining program code T he BCR bit is also set to 1 which causes program execu tion to be held off until all 32 words are loaded into on chip program memory Executi
15. connected only to the EZ ICE connector in the target svstem T hese pins have no function except during emulation and do not require pull up or pull down resistors Interrupts T he interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead The ADSP 2181 AD SP 2183 provides four dedicated external interrupt input pins IRQ2 IRQLO IRQLI and IRQE In addi tion SPORT 1 may be reconfigured for IRQO IRQ FLAG_IN and FLAG OUT for a total of six external interrupts T he AD SP 2181 AD SP 2183 also supports internal interrupts from the timer the byte DM A port the two serial ports software and the power down control circuit T he interrupt levels are internally prioritized and individually maskable except power down and reset The IRQ2 IRQO and IRQ input pins can be programmed to be either level or edge sensitive IRQLO and IRQLI are level sensitive and IRQE is edge sensitive T he priorities and vector addresses of all interrupts are shown in T able I and the inter rupt registers are shown in Figure 7 REV O ADSP 2181 ADSP 2183 Tablel Interrupt Priority amp Interrupt Vector Addresses Interrupt Vector Source of Interrupt Address H ex Reset or Power U p with PUCR 1 0000 Highest Priority Power Down N onmaskable 002C IRQ2 0004 IRQLI 0008 IRQLO 000C SPORTO Transmit 0010 SPORT 0 Receive 0014 IRQE 0018 BDMA Interrupt
16. digital signal processing DSP and other high speed numeric processing applications The ADSP 2181 AD SP 2183 combines the AD SP 2100 family base architecture three computational units data address gen erators and a program sequencer with two serial ports a 16 bit internal DMA port a byte DM A port a programmable timer Flag I O extensive interrupt capabilities and on chip program and data memory The ADSP 2181 AD SP 2183 integrates 80K bytes of on chip memory configured as 16K words 24 bit of program RAM and 16K words 16 bit of data RAM Power down circuitry is also provided to meet the low power needs of battery operated portable equipment T he AD SP 2181 is available in 128 pin TQFP and 128 pin PQFP packages the AD SP 2183 is avail able in the T QFP package only In addition the ADSP 2181 AD SP 2183 supports new instruc tions which include bit manipulations bit set bit clear bit toggle bit test new ALU constants new multiplication instruction x squared biased rounding result free AL U operations I O memory transfers and global interrupt masking for increased flexibility Fabricated in a high speed double metal low power 0 5 um CM OS process the AD SP 2181 operates with a 30 ns instruc tion cycle time 34 7 ns for the AD SP 2183 Every instruction can execute in a single processor cycle The AD SP 2181 AD SP 2183 s flexible architecture and com prehensive instruction set allow the processor to
17. done from the byte memory space to build the word size selected T able V shows the data formats supported by the BDMA circuit Table V Internal BTYPE Memory Space WordSize Alignment 00 Program M emory 24 Full Word 01 D ata M emory 16 Full Word 10 D ata M emory 8 MSBs Tl D ata M emory 8 LSBs Unused bits in the 8 bit data memory formats are filled with Os TheBIAD register field is used to specify the starting address for the on chip memory involved with the transfer T he 14 bit BEAD register specifies the starting address for the external byte memory space T he 8 bit BM PAGE register specifies the start ing page for the external byte memory space T he BDIR register field selects the direction of the transfer Finally the 14 bit BWCOUNT register specifies the number of D SP words to transfer and initiates the BDM A circuit transfers BDM A accesses can cross page boundaries during sequential addressing A BDM A interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register TheBWCOUNT register is updated after each transfer so it can be used to check the status of the transfers When it reaches zero the transfers have finished and a BDM A interrupt is gener ated The BM PAGE and BEAD registers must not be accessed by the DSP during BDM A operations T he source or destination of a BDMA transfer will always be on chip program or data memory regardless of the values of MMAP
18. same ratio T he default form of the in struction when no clock divisor is given is the standard IDLE instruction ADSP 2181 ADSP 2183 When the IDLE n instruction is used it effectively slows down the processor s internal clock and thus its response time to in coming interrupts T he one cycle response time of the standard idle state is increased by n the clock divisor When an enabled interrupt is received the AD SP 2181 A D SP 2183 will remain in the idle state for up to a maximum of n processor cycles n 16 32 64 or 128 before resuming normal operation When the IDLE n instruction is used in systems that have an externally generated serial clock SCLK the serial clock rate may be faster than the processor s reduced internal clock rate U nder these conditions interrupts must not be generated at a faster rate than can be serviced due to the additional time the processor takes to come out of the idle state a maximum of n processor cycles SYSTEM INTERFACE Figure 2 shows a typical basic system configuration with the AD SP 2181 AD SP 2183 two serial devices a byte wide EPROM and optional external program and data overlay memories P rogram mable wait state generation allows the pro cessor connects easily to slow peripheral devices T he AD SP 2181 AD SP 2183 also provides four external interrupts and two serial ports or six external interrupts and one serial port 1 2x CLOCK OR CRYSTAL ADSP 21
19. support allows an unlimited number of instruc tions to be executed before optionally powering down T he power down interrupt also can be used as a non maskable edge sensitive interrupt Context clear save control allows the processor to con tinue where it left off or start with a clean context when leaving the power down state The RESET pin also can be used to terminate power down Power down acknowledge pin indicates when the proces sor has entered power down Processor supply current during power down varies with temperature see Figures 8 and 15 Idle When the AD SP 2181 A D SP 2183 is in the Idle M ode the processor waits indefinitely in a low power state until an interrupt occurs When an unmasked interrupt occurs it is serviced execution then continues with the instruction fol lowing the IDLE instruction Slow Idle ThelDLE instruction is enhanced on the AD SP 2181 AD SP 2183 to let the processor s internal clock signal be slowed further reducing power consumption T he reduced clock frequency a programmable fraction of the normal clock rate is specified by a selectable divisor given in the IDLE instruction T he format of the instruction is IDLE n where n 16 32 64 or 128 T his instruction keeps the processor fully functional but operating at the slower clock rate While it is in this state the processor s other internal clock signals such as SCLK CLK OUT and timer clock are reduced by the
20. 001C SPORT 1 Transmit or IRQ1 0020 SPORT 1 Receive or IRQO 0024 Timer 0028 Lowest Priority Interrupt routines can either be nested with higher priority in terrupts taking precedence or processed sequentially Interrupts can be masked or unmasked with the IM ASK register Indi vidual interrupt requests are logically AN D ed with the bits in IM ASK the highest priority unmasked interrupt is then selected T he power down interrupt is nonmaskable The AD SP 2181 AD SP 2183 masks all interrupts for one in struction cycle following the execution of an instruction that modifies the IM ASK register T his does not affect serial port autobuffering or DMA transfers T heinterrupt control register ICNTL controls interrupt nest ing and defines the IRQO IRQI and IRQ2 external interrupts to be either edge or level sensitive T he IRQE pin is an external edge sensitive interrupt and can be forced and cleared T he IRQLO and IRQLI pins are external level sensitive interrupts T heIFC register is a write only register used to force and clear interrupts On chip stacks preserve the processor status and are automati cally maintained during interrupt handling T he stacks are twelve levels deep to allow interrupt loop and subroutine nesting T hefollowing instructions allow global enable or disable servic ing of the interrupts including power down regardless of the state of IM ASK Disabling the interrupts does not affect seria
21. 183 Parameter Min Max Unit IDMA Address Latch Timing R equirenents tate Duration of Address L atch 10 ns tiasu IAD 15 0 Address Setup before Address Latch End 5 ns tian IAD 15 0 Address H old after Address Latch End 2 ns tika IACK Low before Start of Address L atch 0 ns tats Start of Write or Read after Address Latch E nd 3 3 ns NOTES Istart of Address Latch IS Low and IAL High Start of Write or Read IS Low and IWR Low or IRD Low 3End of Address Latch IS High or IAL Low TACK i tika IAL tiar gt is IAD 15 0 IRD OR IWR Figure 28 IDMA Address Latch 26 REV 0 ADSP 2181 ADSP 2183 ADSP 2181 Parameter Min Max Unit IDMA Write Short Write Cvcle Timing Requirements tikw IACK Low before Start of Write 0 ns tiwp Duration of Write 15 ns tissu IAD 15 0 Data Setup before End of Write gt 4 5 ns toy IAD 15 0 D ata Hold after End of Write 2 ns Switching Characteristics tikkw Start of Write to IACK High 15 ns ADSP 2183 28 8MHz Parameter Min Max Unit IDMA Write Short Write Cvcle Timing Requirements tikw IACK Low before Start of Write 0 ns tiwp Duration of Write 15 ns tipsu IAD 15 0 D ata Setup before End of Write 5 ns tion IAD 15 0 D ata H old after End of Write 34 2 ns Switching Characteristics kuw Start of Write to IACK H igh 17 ns NOTES Istart of Write IS Low and IWR Low End of Write IS High or IWR High 31f Write Pulse ends befo
22. 2 23 24 25 26 27 28 29 30 31 1 tcx MHz POWER IDLE1 2 E 1 u a a e Lu o a IDLE g E I a a a tc z IDLE 9 16 IDLE 128 672 23 24 25 26 27 28 29 30 31 1 tck MHz VALID FOR ALL TEMPERATURE GRADES 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS IDLE REFERS TO ADSP 2183 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3TYPICAL POWER DISSIPATION AT 3 3V Vpp DURING EXECUTION OF IDLE n INSTRUCTION CLOCK FREQUENCY REDUCTION Ipp MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY 50 OF THE INSTRUCTIONS ARE MULTIFUNCTION TYPES 1 4 5 12 13 14 30 ARE TYPE 2 AND TYPE 6 AND 20 ARE IDLE INSTRUCTIONS Figure 16 Power vs Frequency REV 0 ADSP 2181 ADSP 2183 ADSP 2183 CAPACITIVE LOADING Figures 17 and 18 show the capacitive loading characteristics of the AD SP 2183 30 T 85 C Vpp 3 0V 25 20 RISE TIME 0 4V 2 4V ns 0 25 50 75 100 125 150 175 200 CL pF Figure 17 Typical Output Rise Time vs Load Capacitance C at Maximum Ambient Operating Temperature ORHOLD ns ALID OUTPUT DELAY 8 6 4 2 V NOMINAL 2 4 6 0 25 50 75 100 125 150 175 200 C pF Figure 18 Typical Output Valid Delay or Hold vs Load Capacitance C at
23. 39 BMODE 71 EBG 103 IWR 8 IOMS 40 PWDACK 72 BG 104 IRD 9 BMS 41 IACK 73 VDD 105 IAD 15 10 DMS 42 BGH 74 DO 106 IAD 14 11 CMS 43 VDD 75 D1 107 IAD 13 12 GND 44 GND 76 D2 108 IAD 12 13 VDD 45 IRQLO 71 D3 109 IAD11 14 PMS 46 IRQLI 78 D4 110 IAD10 15 A0 47 FLO 79 GND 111 IAD9 16 A1 48 FLI 80 D5 112 IAD8 17 A2 49 FL2 81 D6 113 IAD7 18 A3 50 DTO 82 D7 114 IAD6 19 A4 51 TFSO 83 D8 115 VDD 20 A5 52 RFSO 84 D9 116 GND 21 A6 53 DRO 85 D10 117 IAD5 22 A7 54 SCLKO 86 D11 118 IAD4 23 XTAL 55 DT 1 FO 87 D12 119 IAD3 24 CLKIN 56 TFSI IRQI 88 D13 120 IAD2 25 GND 57 RF SI IRQO 89 D14 121 IAD1 26 CLKOUT 58 GND 90 GND 122 IADO 27 GND 59 DRI FI 91 VDD 123 PF7 28 VDD 60 SCLK1 92 GND 124 PF6 29 A8 61 ERESET 93 D15 125 PF5 30 A9 62 RESET 94 D16 126 PF4 31 A10 63 EMS 95 D17 127 GND 32 All 64 EE 96 D18 128 IS 32 REV 0 ADSP 2181 ADSP 2183 OUTLINE DIMENSIONS 128 Lead Metric Thin Plastic Quad Flatpack TQFP i FILI D D D3 PRAHA HARE AAA LEE LILI TOP VIEW PINS DOWN 1258 0492 0 495 E 21 75 22002225 0856 0 866 0876 E 1990 2000 2010 0783 0 787 0 792 _ E 18501859 0 728 0731 045 aco 075 oo 0 024 0 030 e os 050 0058 joo 0 019 0 023 B a7 a22 027 0007 0009 oon e Jow 0 004 REV 0 33 ADSP 2181 ADSP 2183 128 Lead PQFP Package Pinout
24. 81 ADSP 2183 CLKIN XTAL Do3 16 gt A0 A21 BYTE DATA MEMORY ADDR VO SPACE PERIPHERALS CS 2048 LOCATIONS DATA ADDR OVERLAY DATA MEMORY SERIAL TWO 8K DEVICE PM SEGMENTS TWO 8K DM SEGMENTS SYSTEM INTERFACE OR HCONTROLLER Figure 2 ADSP 2181 ADSP 2183 Basic System Configuration Clock Signals T he ADSP 2181 AD SP 2183 can be clocked by either a crystal or by aT T L compatible clock signal TheCLKIN input cannot be halted changed during operation or operated below the specified frequency during normal opera tion T he only exception is while the processor is in the power down state For additional information refer to Chapter 9 ADSP 2100 Family U ser s M anual for detailed information on this power down feature If an external clock is used it should be a T T L compatible sig nal running at half the instruction rate T he signal is connected to the processor s CLKIN input When an external clock is used the XT AL input must be left unconnected TheADSP 2181 AD SP 2183 uses an input clock with a fre quency equal to half the instruction rate a 16 67 MHz input clock yields a 30 ns processor cycle which is equivalent to 33 MHz Normally instructions are executed in a single pro cessor cycle All device timing is relative to the internal instruc tion clock rate which is indicated by the CLK OUT signal when enabled Because t
25. ANALOG DEVICES DSP Microcomputers ADSP 2181 ADSP 2183 FEATURES PERFORMANCE 30 ns Instruction Cycle Time 5 0 Volts 33 MIPS Sustained Performance 34 7 ns Instruction Cycle Time 3 3 Volts Single Cycle Instruction Execution Single Cycle Context Switch 3 Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP 2100 Family Code Compatible with Instruction Set Extensions 80K Bytes of On Chip RAM Configured as 16K Words On Chip Program Memory RAM 16K Words On Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU Multiplier Accumulator amp Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16 Bit Interval Timer with Prescaler 128 Lead TQFP 128 Lead PQFP SYSTEM INTERFACE 16 Bit Internal DMA Port for High Speed Access to On Chip Memory 4 MByte Memory Interface for Storage of Data Tables amp Program Overlays 8 Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers I O Memory Interface with 2048 Locations Supports Parallel Peripherals Programmable Memory Strobe amp Separate I O Memory Space Permits Gluele
26. DEVICE OPERATING WITH NO OUTPUT LOADS Figure 15 Power Down Supply Current Typical POWER DISSIPATION T o determine total power dissipation in a specific application the following equation should be applied for each output C xVpp xf C load capacitance f output switching frequency Example In an application where external data memory is used and no other outputs are active power dissipation is calculated as follows A ssumptions External data memory is accessed every cycle with 5096 of the address pins switching External data memory writes occur every other cycle with 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin T he application operates at Vpp 3 3 V and tc 34 7 ns Total Power Dissipation Pint C xVpp x f Pint internal power dissipation from Power vs Frequency graph Figure 16 18 C x Vpp x f is calculated for each output of Pins x C x Vpop xf Address DMS 8 x10 pF x3 32V x 333MHz 29 0 mW Data Output WR 9 x10 pF x3 3 V x16 67MHz 16 3 mW RD 1 x10pF x3 2V x1667MHz 1 8 mW CLKOUT 1 x10pF x3 2V x333MHz 3 6 mW 50 7 mW T otal power dissipation for this example is Pint 50 7 mW POWER INTERNAL14 g E I T z a tc S a 00 2
27. F 8K INTERNAL 0x0000 Figure 4 Program Memory MMAP 0 T here are 16K words of memory accessible internally when the PM OVLAY register is set to 0 When PM OVLAY is set to something other than 0 external accesses occur at addresses 0x2000 through Ox3F FF T he external address is generated as shown in T able Il REV 0 Tablell PMOVLAY Memory A13 A12 0 0 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x2000 and Ox3F F F 2 External 1 13 LSBs of Address Overlay 2 Between 0x2000 and Ox3F F F T his organization provides for two external 8K overlay segments using only the normal 14 address bits T his allows for simple program overlays using one of the two external segments in place of the on chip memory Care must be taken in using this overlay space in that the processor core i e the sequencer does not take into account the PM OVLAY register value F or example if a loop operation was occurring on one of the exter nal overlays and the program changes to another external over lay or internal memory an incorrect loop operation could occur In addition care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack For ADSP 2100 Family compatibility MM AP 1 is allowed In this mode booting is disabled and overlay memory is dis abled PM OVLAY must be 0 Figure
28. PM OVLAY or DMOVLAY REV O ADSP 2181 ADSP 2183 When the BWCOUNT register is written with a nonzero value theBDMA circuit starts executing bvte memorv accesses with wait states set by BM WAIT T hese accesses continue until the count reaches zero When enough accesses have occurred to create a destination word it is transferred to or from on chip memory T he transfer takes one D SP cycle DSP accesses to ex ternal memory have priority over BDM A byte memory accesses TheBDMA Context Reset bit BCR controls whether the processor is held off while the BD M A accesses are occurring Setting the BCR bit to 0 allows the processor to continue opera tions Setting the BCR bit to 1 causes the processor to stop ex ecution while the BDM A accesses are occurring to clear the context of the processor and start execution at address 0 when the BDM A accesses have completed Internal Memory DMA Port IDMA Port ThelDMA Port provides an efficient means of communication between a host system and the AD SP 2181 AD SP 2183 T he port is used to access the on chip program memory and data memory of the D SP with only one DSP cycle per word over head TheIDMA port cannot be used however to write to the DSP s memory mapped control registers ThelDMA port has a 16 bit multiplexed address and data bus and supports 24 bit program memory The IDM A port is com pletely asynchronous and can be written to while the AD SP 2181 AD SP 2183 is operating at
29. RD IWR IRQLO IRQLI IRQE PWD Output pins BG PMS DMS BMS IOMS CMS RD WR IACK PWDACK A0 A13 DTO DT 1 CLKOUT FL2 0 Although specified for TTL outputs all AD SP 2183 outputs are CM OS compatible and will drive to V pp and GND assuming no dc loads 6G uaranteed but not tested T hree statable pins A0 A13 D0 D 23 PMS DMS BMS IOMS CMS RD WR DT 0 DT 1 SCLK0 SCLK1 TFSO TFS1 RFSO RSF1 IADO IAD 15 PFO PF7 80 V on BR CLKIN Active to force three state condition Idle refers to AD SP 2183 state of operation during execution of IDLE instruction D easserted pins are driven to either V pp or GND 10C urrent reflects device operating with no output loads H pp measurement taken with all instructions executing from internal memory 50 of the instructions are multifunction types 1 4 5 12 13 14 30 are type 2 and type 6 and 20 are idle instructions DVju 0 4 V and 24 V For typical figures for supply currents refer to Power Dissipation section BA pplies to T QFP and PQFP package types 40 utput pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice 16 REV O ADSP 2181 ADSP 2183 ADSP 2183 ABSOLUTE MAXIMUM RATINGS Supply Voltage 2 eee eee 0 3 V to 4 6V Input Voltage LL L 0 5 V to Vpp 0 5V Output Voltage Swing 0 5 V to Vppg 0 5V Operating T emperature Range Am
30. RD High 3DM read or first half of PM read 4Second half of PM read gt tikHR tkr 4 RI tinp tiroe gt gt IAD 15 0 Figure 31 IDMA Read Long Read Cycle REV 0 29 ADSP 2181 ADSP 2183 ADSP 2181 Parameter Min Max Unit IDMA Read Short Read Cvcle Timing R equirenents tik IACK Low before Start of Read 0 ns tire Duration of Read 15 ns Switching Characteristics tikHR IACK High after Start of Read 15 ns tikoH IAD 15 0 Data Hold after End of Read 0 ns tikon IAD 15 0 Data Disabled after End of Read 10 ns tiRDE IAD 15 0 Previous Data Enabled after Start of Read 0 ns tiapv IAD 15 0 Previous D ata Valid after Start of Read 15 ns ADSP 2183 28 8MHz Parameter Min Max Unit IDMA Read Short Read Cycle Timing Requirements tikR IACK Low before Start of Read 0 ns np Duration of Read 15 ns Switching Characteristics tixue IACK High after Start of Read 17 ns tikoH IAD 15 0 Data Hold after End of Read 0 ns tcp IAD 15 0 Data Disabled after End of Read 10 ns tIRDE IAD 15 0 Previous Data Enabled after Start of Read 0 ns tirpv IAD 15 0 Previous Data Valid after Start of Read 15 ns NOTES IStart of Read IS Low and IRD Low End of Read IS High or IRD High IACK tr J 1 tur tiroe IAD 15 0 Figure 32 IDMA Read Short Read Cycle 30 REV 0 ADSP 2181 ADSP 2183 128 Lead TQFP Package Pinout 1 1 1 l
31. SHIFTER OUTPUT REGS TRANSMIT REG RECEIVE REG SERIAL PORTO TRANSMIT REG RECEIVE REG SERIAL PORTO INPUT REGS OUTPUT REGS R BUS Figure 1 ADSP 2181 ADSP 2183 Block Diagram REV O 3 ADSP 2181 ADSP 2183 SPORT s support serial data word lengths from 3 to 16 bits and provide optional A law and u law companding according to CCITT recommendation G 711 SPORT receive and transmit sections can generate unique in terrupts on completing a data word transfer SPORT s can receive and transmit an entire circular buffer of data with only one overhead cycle per data word An interrupt is generated after a data buffer transfer SPORT 0 has a multichannel interface to selectively receive and transmit a 24 or 32 word time division multiplexed se rial bitstream SPORT 1 can be configured to have two external interrupts IRQO and IRQ1 and the Flag In and Flag Out signals T he internally generated serial clock may still be used in this configuration Pin Descriptions The ADSP 2181 AD SP 2183 is available in 128 lead T QFP and 128 lead PQFP packages PIN DESCRIPTIONS Pin of Input Name s Pins Output Function Address 14 0 Address Output Pins for Program Data Byte amp I O Spaces D ata 24 1 0 Data I O Pins for Program and D ata M emory Spaces 8 M SBs Are Also U sed as Byte Space Addresses RESET 1 l Processor Reset Input IRQ2 1 Edge or L evel Sensitive Interrupt Request IRQLO
32. T 115 0 C to 70 C 40 C to 85 C 0 C to 70 C 40 C to 85 C 0 C to 70 C 40 C to 85 C 0 C to 70 C 40 C to 85 C 0 C to 70 C 40 C to 85 C 28 8 28 8 28 8 28 8 33 3 33 3 33 3 33 3 28 8 28 8 128 L ead T QFP 128 L ead T QFP 128 L ead PQFP 128 L ead PQFP 128 L ead T QFP 128 L ead TQFP 128 L ead PQFP 128 L ead PQFP 128 L ead TQFP 128 L ead TQFP ST 128 ST 128 5 128 5 128 ST 128 ST 128 5 128 5 128 ST 128 ST 128 S Plastic Quad Flatpack PQFP ST Plastic Thin Quad Flatpack T QFP REV 0 37 38 39 96 9 9T kvIZI V S f1 NI GALNIdd 40
33. Vin Vpp max 10 uA lu Lo L evel Input Current 9 Vpp max Vin 0V 10 uA lozu T hree State L eakage C urrent 9 Vpp max Vin Vpp max 10 uA loz T hree State L eakage C urrent 9 Vpp max Vin O V8 10 uA lop Supply Current Idle 2 Vpp max 16 5 mA Ipp Supply Current D ynamic 9 11 9 Vpp max tek 30 ns 100 mA C Input Pin Capacitance 9 13 Vin 22 5 V fin 1 0M Hz Tams 25 C 8 pF Co Output Pin Capacitance 1 14 Q Vin 2 5V fin 2 1 0M Hz TAMB 25 C 8 pF NOTES IBidirectional pins D 0 D 23 RF S0 RFS1 SCLK0 SCLK 1 TFSO TFS1 IADO IAD 15 PFO PF7 Input only pins RESET IRQ2 BR M M AP DRO DR1 PWD IRQLO IRQLI IRQE IS IRD IWR IAL 3Input only pins CLKIN RESET IRQ2 BR MM AP DRO DR1 IS IAL IRD IWR IRQLO IRQLI IRQE PWD Output pins BG PMS DMS BMS IOMS CMS RD WR IACK PWDACK A0 A13 DT0 DT1 CLK OUT FL2 0 5Although specified for T T L outputs all AD SP 2181 outputs are CM OS compatible and will drive to V pp and GND assuming no dc loads Guaranteed but not tested 1T hree statable pins A0 A 13 D 0 D 23 PMS DMS BMS IOMS CMS RD WR DT 0 DT 1 SCLKO SCLK 1 TFSO TFS1 RFSO RSF1 IADO IAD 15 PFO PF 7 80 V on BR CLKIN Active to force three state condition Idle refers to AD SP 2181 state of operation during execution of IDLE instruction D easserted pins are driven to either V pp or GND 10C urrent reflects device operating with no outpu
34. a Disable before WR or RD Low 0 25tc 7 ns twa CLKOUT HightoWRLow 0 25tck 5 0 25 tck 7 ns taw A0 A 13 xMS Setup before WR D easserted 0 75tck 9 w ns twra A0 A13 xMS H old after WR D easserted 0 25tck 3 ns twwR WR High to RD or WR Low Q 5tck 5 ns w wait states x tc xMS PMS DMS CMS IOMS BMS CLKOUT EE I CENE IEEE NN A0 A13 DMS PMS BMS CMS IOMS Figure 26 Memorv Write 24 REV 0 ADSP 2181 ADSP 2183 ADSP 2181 ADSP 2183 Parameter Min Max Unit Serial Ports Timing R equirenents tsck SCLK Period 50 ns tscs DR TFS RFS Setup before SCLK Low 4 ns tscy DR TFS RFS Hold after SCLK Low 7 ns tscp SCLK y Width 20 ns Switching Characteristics tcc CLKOUT High to SCLKour 0 25tc 0 25tck 10 ns tscne SCLK High to DT Enable 0 ns tscpv SCLK High to DT Valid 15 ns tau TFS RF Sou Hold after SCLK High 0 ns tap TFS RF Sou Delay from SCLK High 15 ns tscoH DT Holdafter SCLK High 0 ns trpe TFS Alt to DT Enable 0 ns trov TFS Alt to DT Valid 14 ns tscpp SCLK High to DT Disable 15 ns tkov RFS M ultichannel F rame D elay Zero to DT Valid 15 ns CLKOUT SCLK tses tscH DR TFSiN RFSin He tro try RFSour TFSour tscpp k tscpv gt DT TFS ALTERNATE FRAME MODE trov gt RFS MULTICHANNEL MODE FRAME DELAY 0 MFD 0 Figure 27 Serial Ports REV 0 25 ADSP 2181 ADSP 2183 ADSP 2181 ADSP 2
35. an input is synchronized to the AD SP 2181 AD SP 2183 s clock Bits that are programmed as outputs will read the value being output The PF pins default to input during reset In addition to the programmable flags the AD SP 2181 AD SP 2183 has five fixed mode flags FLAG_IN FLAG_OUT FLO FL1 and FL2 FLO FL2 are dedicated output flags FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT 1 BIASED ROUNDING A mode is available on the AD SP 2181 AD SP 2183 to allow biased rounding in addition to the normal unbiased rounding When the BIASRND bit is set to 0 the normal unbiased round ing operations occur When the BIASRND bit is set to 1 biased rounding occurs instead of the normal unbiased rounding When operating in biased rounding mode all rounding opera tions with M RO set to 0x8000 will round up rather than only rounding odd M R1 values up For example MR valuebeforeRND biased RND result unbiased RN D result 00 0000 8000 00 0001 8000 00 0000 8001 00 0001 8001 00 0000 7FFF 00 0001 7FFF 00 0001 8000 00 0002 8000 00 0001 8001 00 0002 8001 00 0000 7FFF 00 0001 7FFF 00 0000 8000 00 0002 8000 00 0001 8001 00 0002 8001 00 0000 7FFF 00 0001 7FFF T his mode only has an effect when the M RO register contains 0x8000 all other rounding operation work normally T his mode allows more efficient implementation of bit specified algorithms that use biased rounding for example the GSM speech com p
36. anual 2183 to continue running from on chip memory N ormal execu for further details tion mode requires the processor to halt while buses are granted e SPORTS are bidirectional and have a separate double The ADSP 2181 AD SP 2183 can respond to eleven interrupts buffered transmit and receive section T here can be up to six external interrupts one edge sensitive e SPORT scan use an external serial clock or generate their two level sensitive and three configurable and seven internal own serial clock internally interrupts generated by the timer the serial ports SPORT s the Byte DM A port and the power down circuitry T here is also a master RESET signal SPORTS have independent framing for the receive and trans mit sections Sections run in a frameless mode or with frame synchronization signals internally or externally generated T he two serial ports provide a complete synchronous serial inter Frame sync signals are active high or inverted with either of face with optional companding in hardware and a wide variety of two pulse widths and timings framed or frameless data transmit and receive modes of operation 21xx CORE ADSP 2181 ADSP 2183 INTEGRATION POWER 2 contro 2 LOGIC 8 16k x 24 BYTE PROGRAMMABLE GENERATOR FLAGS 7 1 2 e a C E E Ed e 14 E A CP EXTERNAL ADDRESS BUS L PMD BUS EXTERNAL DATA BUS INPUT REGS OUTPUT REGS
37. arges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur to devices subjected to high energy electrostatic discharges TheADSP 2181 features proprietary ESD protection circuitry to dissipate high energy discharges Human Body M odel Per method 3015 of MIL ST D 883 the AD SP 2181 has been classified as a Class 2 device Proper ESD precautions are recommended to avoid performance degradation or loss of function WARNING som a ESD SENSITIVE DEVICE ality Unused devices must be stored in conductive foam or shunts and the foam should be discharged to the destination before devices are removed ADSP 2181 TIMING PARAMETERS GENERAL NOTES Use the exact timing information given D o not attempt to de rive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases Consequently you cannot meaningfully add up parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its signals Y ou have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteristics tell you what the processor will do in a given circumstance Y ou can also use switch ing characteristi
38. bient 40 C to 85 C Storage T emperatureRange 65 C to 150 C Lead Temperature 5 sec TQFP 000 280 C Stresses above those listed under Absolute M aximum Ratings may cause perma nent damage to the device T hese are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD SENSITIVITY T he AD SP 2183 is an ESD electrostatic discharge sensitive device Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur to devices subjected to high energy electrostatic discharges T he ADSP 2183 features proprietary ESD protection circuitry to dissipate high energy discharges Human Body M odel Per method 3015 of M IL ST D 883 the AD SP 2183 has been classified as a Class 2 device Proper ESD precautions arerecommended to avoid performancedegradation or loss of functionality WARNING SENT ESD SENSITIVE DEVICE U nused devices must be stored in conductive foam or shunts and the foam should be discharged to the destination before devices are removed ADSP 2183 TIMING PARAMETERS GENERAL NOTES Use the exact timing information given Do not attempt to de rive parameters from the add
39. cs to ensure that any timing requirement of a device connected to the processor such as memory is satisfied Timing requirements apply to signals that are controlled by cir cuitry external to the processor such as the data input for a read operation T iming requirements guarantee that the processor operates correctly with other devices REV 0 MEMORY TIMING SPECIFICATIONS T hetable below shows common memory device specifications and the corresponding AD SP 2181 timing parameters for your convenience Memory ADSP 2181 Timing Device Timing Parameter Specification Parameter Definition Address Setup to tasw A0 A13 xMS Setup before Write Start WR Low Address Setup to taw A0 A13 xMS Setup before Write End WR D easserted Address Hold Time twra A0 A13 xMS H old after WR D easserted DataSetupTime tow Data Setup before WR High Data H old Time tou Data H old after WR High OE to DataValid tgpp RD Low to Data Valid Address Access T ime taa A0 A13 xMS to D ata Valid xMS PMS DMS BMS CMS IOMS FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tcx is defined as 0 5tcx The AD SP 2181 uses an input clock with a frequency equal to half the instruction rate a 16 67 MHz input clock which is equivalent to 60 ns yields a 30 ns proces sor cycle equivalent to 33 M Hz tex values within the range of 0 5tcx period should be substituted for all relevant timing pa rameters to obtain the specification value
40. d DataSetupTime tpw Data Setup before WR High Data Hold Time tou Data H old after WR High OE to DataValid trpp RD Low to Data Valid Address Access T ime taa A0 A13 xMS to Data Valid xMS PMS DMS BMS CMS IOMS FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tcx is defined as 0 5tcx The AD SP 2183 uses an input clock with a frequency equal to half the instruction rate a 14 4 MHz input clock which is equivalent to 57 6 ns yields a 34 7 ns pro cessor cycle equivalent to 28 8 M Hz tc values within the range of 0 5tck period should be substituted for all relevant timing parameters to obtain the specification value Example teku 0 5tcx 7 ns 0 5 34 7 ns 7 ns 11 7 ns 17 ADSP 2181 ADSP 2183 ADSP 2183 ENVIRONMENTAL CONDITIONS Ambient T emperature Rating Tama 7 Tease PD x Oca T case Case T emperature in C PD Power Dissipation in W 0c4 T hermal Resistance C ase to A mbient 8 Thermal Resistance J unction to A mbient 6jc Thermal Resistance Junction to C ase Package OjA jc Oca TQFP 50 C W 2 C W 48 C W PQFP 41 C W 10 C W 31 C W 1000 a i Vpp 3 6V E Vpp 3 3V T 100 Vpp 3 0V a o a e o E z 10 tt 3 o 0 5 25 55 85 TEMPERATURE C NOTES 1 REFLECTS ADSP 2183 OPERATION IN LOWEST POWER MODE SEE SYSTEM INTERFACE CHAPTER OF THE ADSP 2100 FAMILY USER S MANUAL FOR DETAILS 2 CURRENT REFLECTS
41. e ADSP 2181 AD SP 2183 has 16K words on D ata M emory RAM on chip consisting of 16 352 user accessible locations and 32 memory mapped registers Support also exists for up to two 8K external memory overlay spaces through the external data bus Byte Memory provides access to an 8 bit wide memory space through the Byte DM A BDM A port T he Byte M emory inter face provides access to 4 M Bytes of memory by utilizing eight data lines as additional address lines T his gives the BDM A Port an effective 22 bit address range On power up the D SP can automatically load bootstrap code from byte memory I O Space allows access to 2048 locations of 16 bit wide data It is intended to be used to communicate with parallel periph eral devices such as data converters and external registers or latches Program Memory The ADSP 2181 AD SP 2183 contains a 16K x 24 on chip program RAM The on chip program memory is designed to al low up to two accesses each cycle so that all operations can complete in a single cycle In addition the AD SP 2181 AD SP 2183 allows the use of 8K external memory overlays T he program memory space organization is controlled by the MMAP pin and the PM OVLAY register Normally the ADSP 2181 AD SP 2183 is configured with M M AP 0 and program memory organized as shown in F igure 4 PROGRAM MEMORY ADDRESS Ox3FFF 8K INTERNAL PMOVLAY 0 MMAP 0 OR EXTERNAL 8K PMOVLAY 1 or 2 MMAP 0 0x2000 0x1 FF
42. ed 3IRQx IRQO IRQI IRQ2 IRQLO IRQLI IRQE 4PFx PFO PF1 PF2 PF3 PF4 PF5 PF6 PF7 5Flag outputs PF x FLO FL1 FL2 Flag out trop CLKOUT trou FLAG OUTPUTS t iru IRQx FI PFx trs e Figure 23 Interrupts and Flags REV 0 21 ADSP 2181 ADSP 2183 ADSP 2181 ADSP 2183 Parameter Min Max Unit Bus Request Grant Timing Requirements tex BR Hold after CLK OUT High 0 25tc 2 ns tgs BR Setup before CLKOUT Low 0 25tck 17 ns Switching Characteristics tsp CLKOUT High to xMS 0 25tcy 10 ns RD WR Disable tspg xMS RD WR Disableto BG Low 0 ns tse BG High to xMS RD WR Enable 0 ns tsec xMS RD WR Enable to CLK OUT High 0 25tck 7 ns tspBH xMS RD WR Disable to BGH L ow 0 ns tsEH BGH High to xMS RD WR Enable 0 ns NOTES xMS PMS DMS CMS IOMS BMS TBR is an asynchronous signal If BR meets the setup hold requirements it will be recognized during the current clock cycle otherwise the signal will be recognized on the following cycle Refer to the ADSP 2100 Family User s M anual for BR BG cycle relationships BGH is asserted when the bus is granted and the processor requires control of the bus to continue teH CLKOUT r NT tes CLKOUT PMS DMS BMS RD WR tsp gt tsec BG tsps A tse j4 Figure 24 Bus Request Bus Grant 22 REV 0 ADSP 2181 ADSP 2183
43. ent Figure 1 is an overall block diagram of the AD SP 2181 AD SP 2183 T he processor contains three independent computational units the ALU the multiplier accumulator M AC and the shifter T he computational units process 16 bit data directly and have provisions to support multiprecision computations T he ALU performs a standard set of arithmetic and logic operations division primitives are also supported T he M AC performs single cycle multiply multiply add and multiply subtract opera tions with 40 bits of accumulation T he shifter performs logical and arithmetic shifts normalization denormalization and de rive exponent operations T he shifter can be used to efficiently implement numeric format control including multiword and block floating point representations T he internal result R bus connects the computational units so that the output of any unit may bethe input of any unit on the next cycle A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu tational units T he sequencer supports conditional jumps sub routine calls and returns in a single cycle With internal loop counters and loop stacks the ADSP 2181 AD SP 2183 executes looped code with zero overhead no explicit jump instructions are required to maintain loops T wo data address generators D AG s provide addresses for simultaneous dual operand fetches from data memory and pro gram
44. es the EE emulator enable signal to take con trol of the AD SP 2181 AD SP 2183 in the target system T his causes the processor to use its ERESET EBR and EBG pins instead of the RESET BR and BG pins T he BG output is three stated T hese signals do not need to be jumper isolated in your system TheEZ ICE connects to your target system via a ribbon cable and a 14 pin female plug T he female plug is plugged onto the 14 pin connector a pin strip header on the target board Target Board Connector for EZ ICE Probe TheEZ ICE connector a standard pin strip header is shown in Figure 7 You must add this connector to your target board design if you intend to use the EZ ICE Be sure to allow enough room in your system to fit the EZ ICE probe onto the 14 pin connector H GND Ho EBG EBR KEY NO PIN 5 a 7 x 9 a ELOUT EE Bc RESET TOP VIEW Figure 7 Target Board Connector for EZ ICE T he 14 pin 2 row pin strip header is keyed at the Pin 7 loca tion you must remove Pin 7 from the header T he pins must be 0 025 inch square and at least 0 20 inch in length Pin spac ing should be 0 1 x 0 1 inches T he pin strip header must have at least 0 15 inch clearance on all sides to accept the EZ ICE probe plug Pin strip headers are available from vendors such as 3M McKenzie and Samtec REV 0 Target Memory Interface For your target system to be compatible with the EZ I CE emu lato
45. full speed The DSP memory address is latched and then is automatically incremented after each IDM A transaction An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block T his in creases throughput as the address does not have to be sent for each memory access IDMA Port access occurs in two phases T he first is the IDM A Address L atch cycle When the acknowledge is asserted a 14 bit address and 1 bit destination type can be driven onto the bus by an external device T he address specifies an on chip memory location the destination type specifies whether itis a DM or PM access T he falling edge of the address latch signal latches this value into the IDM AA register Once the address is stored data can then be either read from or written to the AD SP 2181 AD SP 2183 s on chip memory As serting the select line IS and the appropriate read or write line IRD and IWR respectively signals the AD SP 2181 AD SP 2183 that a particular transaction is required In either case there is a one processor cycle delay for synchronization T he memory access consumes one additional processor cycle Once an access has occurred the latched address is automati cally incremented and another access can occur Through the IDM AA register the DSP can also specify the starting address and data format for DM A operation Bootstrap Loading Booting The ADSP 2181 AD
46. he AD SP 2181 AD SP 2183 includes an on chip oscil lator circuit an external crystal may be used T he crystal should be connected across the CLKIN and XTAL pins with two capaci tors connected as shown in Figure 3 Capacitor values are de pendent on crystal type and should be specified by the crystal manufacturer A parallel resonant fundamental frequency mi croprocessor grade crystal should be used A clock output CLK OUT signal is generated by the processor at the processor s cycle rate T his can be enabled and disabled by the CLK ODIS bit in the SPORT 0 Autobuffer Control Register CLKIN XTAL ADSP 2181 ADSP 2183 CLKOUT Figure 3 External Crystal Connections Reset The RESET signal initiates a master reset of the AD SP 2181 AD SP 2183 T he RESET signal must be asserted during the power up sequence to assure proper initialization RESET dur ing initial power up must be held long enough to allow the in ternal clock to stabilize If RESET is activated any time after power up the clock continues to run and does not require stabilization time T he power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Vpp is ap plied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start up time D uri
47. ition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases Consequently you cannot meaningfully add up parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its sig nals You have no control over this timing circuitrv external to the processor must be designed for compatibility with these sig nal characteristics Switching characteristics tell you what the processor will do in a given circumstance Y ou can also use switch ing characteristics to ensure that any timing requirement of a de vice connected to the processor such as memory is satisfied Timing requirenents apply to signals that are controlled by cir cuitry external to the processor such as the data input for a read operation T iming requirements guarantee that the processor operates correctly with other devices REV 0 MEMORY TIMING SPECIFICATIONS T he table below shows common memory device specifications and the corresponding AD SP 2183 timing parameters for your convenience Memory ADSP 2183 Timing Device Timing Parameter Specification Parameter Definition Address Setup to tren A0 A13 xMS Setup before Write Start WR Low Address Setup to taw A0 A13 xMS Setup before Write End WR D easserted Address Hold Time twra A0 A13 xMS H old after WR D easserte
48. l port autobuffering or DM A ENA INTS DIS INTS W hen the processor is reset interrupt servicing is enabled LOW POWER OPERATION TheADSP 2181 AD SP 2183 has three low power modes that significantly reduce the power dissipation when the device oper ates under standby conditions T hese modes are Power Down Idle Slow Idle TheCLKOUT pin may also be disabled to reduce external power dissipation REV 0 Power Down TheADSP 2181 AD SP 2183 processor has a low power feature that lets the processor enter a very low power dor mant state through hardware or software control Hereisa brief list of power down features Refer to theADSP 2100 Family U ser s M anual Chapter 9 System Interface for de tailed information about the power down feature Quick recovery from power down T he processor begins executing instructions in as few as 100 CLKIN cycles Support for an externally generated T T L or CM OS pro cessor clock T he external clock can continue running during power down without affecting the lowest power rat ing and 100 CLKIN cycle recovery Support for crystal operation includes disabling the oscil lator to save power the processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabi lize and letting the oscillator run to allow 100 CLKIN cycle start up Power down is initiated by either the power down pin PWD or the software power down force bit Interrupt
49. lation can be supported in final board designs T he EZ ICE performs a full range of functions including Stand alone or in target operation U p to 20 breakpoints Single step or full speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction level emulation of program booting and execution Complete assembly and disassembly of instructions C source level debugging See Designing An EZ ICE Compatible T arget System in the ADSP 2100 F amily EZ T ools M anual as well as page 11 of this data sheet for exact specifications of the EZ ICE target board connector EZ ICE and SoundPort are registered trademarks of Analog D evices Inc Additional Information T his data sheet provides a general overview of ADSP 2181 AD SP 2183 functionality For additional information on the architecture and instruction set of the processor refer to the ADSP 2100 Family User s M anual For more information about the development tools refer to the AD SP 2100 F amily D evelop ment T ools D ata Sheet ARCHITECTURE OVERVIEW TheADSP 2181 ADSP 2183 instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions Every instruction can be executed in a single processor cycle T he AD SP 2181 AD SP 2183 assembly language uses an algebraic syntax for ease of coding and read ability A comprehensive set of development tools supports pro gram developm
50. memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of one of four pos sible modify registers A length value may be associated with each pointer to implement automatic modulo addressing for cir cular buffers Efficient data transfer is achieved with the use of five internal buses Program M emory Address PM A Bus Program M emory Data PM D Bus D ata M emory Address DM A Bus Data M emory Data DM D Bus Result R Bus T hetwo address buses PM A and DM A share a single external address bus allowing memory to be expanded off chip and the two data buses PM D and DM D share a single external data bus Byte memory space and I O memory space also share the external buses REV 0 ADSP 2181 ADSP 2183 Program memorv can store both instructions and data permit Each port can generate an internal programmable serial clock or ting the AD SP 2181 AD SP 2183 to fetch two operands in a accept an external serial clock andere ane fom Modam memory and one Wem deta T he ADSP 2181 AD SP 2183 provides up to 13 general purpose memory The AD SP 2181 AD SP 2183 can fetch an operand from flag pins The data input and output pins on SPORT 1 can be program memory and the next instruction in the same cycle alternatively configured as an input flag and an output flag In In addition to the address and data bus for external memory addition
51. n additional external memory space called I O space T his space is designed to sup port simple connections to peripherals or to bus interface ASIC data registers I O space supports 2048 locations T he lower eleven bits of the external address bus are used the upper three bits are undefined T wo instructions were added to the core AD SP 2100 F amily instruction set to read from and write to I O memory space T he I O space also has four dedicated three bit wait state registers IOWAIT 0 3 which specify up to seven wait states to be automatically generated for each of four regions T he wait states act on address ranges as shown in T ablelV TablelV Address Range Wait State Register 0x000 0x1F F IOWAITO 0x200 0x3F F IOWAIT 1 0x400 0x5F F IOWAIT 2 0x600 0x7F F IOWAIT 3 Composite Memory Select CMS The ADSP 2181 AD SP 2183 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space T he CMS signal is generated to have the same timing as each of the individual memory select signals PMS DMS BMS IOMS but can com bine their functionality Each bit in the CMSSEL register when set causes the CMS signal to be asserted when the selected memory select is as serted F or example to use a 32K word memory to act as both program and data memory set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory
52. n the capacitive load C and the current load iL on the output pin It can be approximated by the fol lowing equation C 0 5V toecay HE TENE from which tois ty EASURED toecay is calculated If multiple pins such as the data bus are dis abled the measurement value is that of the last pin to stop driving 3 0V INPUT 1 5V 0 0V 2 0V OUTPUT 1 5V 0 3V Figure 12 Voltage Reference Levels for AC Measure ments Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when that have made a transition from a high impedance state to when they start driving T he output enable time tena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in the Output Enable D isable diagram If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL Vou OH MEASURED MEASURED VoH MEASURED 0 5V 2 0V OUTPUT VoL MEASURED 0 5V VoL toecay VoL MEASURED MEASURED OUTPUT STARTS OUTPUT STOPS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 13 Output Enable Disable loL TO OUTPUT 1 5V PIN Figure 14 Equivalent Device Loading for AC Measure ments Including All Fixtures 15 ADSP 2181 ADSP 2183
53. ng this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the mini mum pulse width specification tsp The RESET input contains some hysteresis however if you use an RC circuit to generate your RESET signal the use of an ex ternal Schmidt trigger is recommended T he master reset sets all internal stack pointers to the empty Stack condition masks all interrupts and clears the M STAT register When RESET is released if there is no pending bus request and the chip is configured for booting M M AP 0 the boot loading sequence is performed T he first instruction is fetched from on chip program memory location 0x0000 once boot loading completes 6 REV 0 ADSP 2181 ADSP 2183 Memorv Architecture The ADSP 2181 AD SP 2183 provides a variety of memory and peripheral interface options T he key functional groups are Pro gram M emory D ata M emory Byte M emory and I O Program Memory is a 24 bit wide space for storing both in struction opcodes and data T he ADSP 2181 AD SP 2183 has 16K words of Program M emory RAM on chip and the capabil ity of accessing up to two 8K external memory overlay spaces using the external data bus Both an instruction opcode and a data value can be read from on chip program memory in a single cycle Data Memory is a 16 bit wide space used for the storage of data variables and for memory mapped control registers T h
54. ns switching Each address and data pin has a 10 pF total load at the pin T he application operates at Vpp 5 0 V and tc 30 ns Total Power Dissipation Pint C xVpp x f Pint internal power dissipation from Power vs Frequency graph F igure 9 C x Vpp x f is calculated for each output of Pins x C x Vpop xf Address DMS 8 x10 pF x5 V x33 3MHz 66 6 mW Data Output WR 9 x10 pF x5 V x16 67 MHz 375 mW RD 1 x10pF x5 V x1667MHz 4 2 mW CLKOUT 1 xl0pF x59V x333MHz 83mW 116 6 mW Total power dissipation for this example is Pint 116 6 mW 570 550 2181 POWER INTERNAL 530 Vpp V Es 550mW 510 480 490mW 450 420 Vpp 5 0V 425mW 390 360 365mW POWER Py mW 330 300 Vpp 4 5V 4 330mMW 275mW 270 240 28 29 30 31 32 33 34 1 tck MHz POWER IDLE 2 POWER Pip g mW 9 30 31 32 33 34 1 fek MHz POWER IDLE n MODES POWER Pip gj mW l fek MHz VALID FOR ALL TEMPERATURE GRADES 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2IDLE REFERS TO ADSP 2181 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3TVPICAL POWER DISSIPATION AT 5 0V Vpp DURING EXECUTION OF IDLE n INSTRUCTION
55. ode debugger allows programs to be corrected in the C environment The Runtime Library includes over 100 AN SI standard mathematical and D SP specific functions The EZ KIT Lite is a hardware software kit offering a complete development environment for the entire AD SP 21xx family an AD SP 2181 based evaluation board with PC monitor software plus Assembler Linker Simulator and PROM Splitter software The ADSP 2181 EZ KIT Lite is a low cost easy to use hardware platform on which you can quickly get started with your DSP soft ware design T he EZ KIT Lite includes the following features 33M Hz ADSP 2181 Full 16 bit Stereo Audio 1 O with AD 1847 SoundPort C odec RS 232 Interface to PC with Windows 3 1 Control Software Stand Alone Operation with Socketed EPROM EZ ICE Connector for Emulator Control DSP Demo Programs TheADSP 2181 EZ ICE Emulator aids in the hardware de bugging of AD SP 2181 system T he emulator consists of hard ware host computer resident software and the target board connector T he ADSP 2181 AD SP 2183 integrates on chip emulation support with a 14 pin ICE Port interface T his inter face provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP 2100 Family EZ ICEs T he AD SP 2181 AD SP 2183 device need not be removed from the target system when using the EZ ICE nor are any adapters needed D ue to the small footprint of the EZ ICE connector emu
56. on then begins at address 0 T he ADSP 2100 F amily development software Revision 5 02 and later fully supports the BDM A booting feature and can generate byte memory space compatible boot code ThelDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BD M A interface IDMA Port Booting T he AD SP 2181 AD SP 2183 can also boot programs through its Internal DMA port If BM ODE 1 and MMAP 20 the AD SP 2181 AD SP 2183 boots from the IDM A port IDM A feature can load as much on chip memory as desired Program execution is held off until on chip program memory location 0 is written to T he AD SP 2100 F amily development software Revision 5 02 and later can generate ID M A compatible boot code Bus Request amp Bus Grant The ADSP 2181 AD SP 2183 can relinquish control of the data and address buses to an external device When the external de vice requires access to memory it asserts the bus request BR signal If the AD SP 2181 AD SP 2183 is not performing an ex ternal memory access then it responds to the active BR input in the following processor cycle by three stating the data and address buses and the PMS DMS BMS CMS IOMS RD WR output drivers asserting the bus grant BG signal and e halting program execution If Go M ode is enabled the AD SP 2181 AD SP 2183 will not halt program execution until it encounters an instruction that require
57. perform multiple operations in parallel In one processor cycle the AD SP 2181 AD SP 2183 can generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation Analog Devices Inc 1996 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 ADSP 2181 ADSP 2183 T his takes place while the processor continues to receive and transmit data through the two serial ports receive and or transmit data through the internal DM A port receive and or transmit data through the byte DM A port decrement timer Development System T he ADSP 2100 Family D evelopment Software a complete set of tools for software and hardware system development supports the AD SP 2181 AD SP 2183 T he System Builder provides a high level method for defining the architecture of systems under devel opment T he Assembler has an algebraic syntax that is easy to program and debug T he Linker combines object files into an executable file T he Simulator provides an interactive instruc tion level simulation with a reconfigurable user interface to dis play different portions of the hardware environment A PROM Splitter generates PROM programmer compatible files T he C Compiler based on the Free Software Foundation s GNU C Compiler generates AD SP 2181 AD SP 2183 assembly source code T he source c
58. ple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL tMEASURED Vou MEASURED Vou MEASURED VoH MEASURED 0 5V 2 0V OUTPUT VoL MEASURED 0 5V VoL VoL FK t MEASURED DESAN MEASURED OUTPUT STARTS OUTPUT STOPS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 20 Output Enable Disable loL TO OUTPUT 1 5V PIN 50pF I lon Figure 21 Equivalent Device Loading for AC Measure ments Including All Fixtures 19 ADSP 2181 ADSP 2183 ADSP 2181 Parameter Min Max Unit Clock Signals and Reset Timing R equirenents tcki CLKIN Period 60 150 ns tckiL CLKIN Width Low 20 ns tckiH CLKIN Width High 20 ns Switching Characteristics tekl CLKOUT Width Low 0 5tek 7 ns tckH CLKOUT Width High Q 5tck 7 ns tckon CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirements tasp RESET Width Low 5tck ns ADSP 2183 28 8 MHz Parameter Min Max Unit Clock Signals and Reset Timing R equirenents tek CLKIN Period 69 4 150 ns tekil CLKIN Width Low 20 ns tckiH CLKIN Width High 20 ns Switching Characteristics tekl CLKOUT Width Low 0 5tek 7 ns tcku CLKOUT Width H igh 0 5tck 7 ns tckoH CLKIN Highto CLKOUT High 0 20 ns Control Signals Timing Requirements tasp RESET Width Low Stekl ns NOTE 1A pplies after po
59. r it must comply with the memory interface guidelines listed below PM DM BM IOM amp CM D esign your Program M emory PM Data M emory DM Byte M emory BM I O Memory IOM and Composite M emory CM external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the D SP s data sheet T he performance of the EZ ICE may approach published worst case specification for some memory access timing requirements and switching characteristics Note f your target does not meet the worst case chip specifi cation for memory access parameters you may not be able to emulate your circuitry at the desired CLKIN frequency De pending on the severity of the specification violation you may have trouble manufacturing your system as D SP components statistically vary in switching characteristic and timing require ments within published limits Restriction All memory strobe signals on the AD SP 2181 ADSP 2183 RD WR PMS DMS BMS CMS and IOMS used in your target system must have 10 kQ pull up resistors connected when the EZ ICE is being used T he pull up resis tors are necessary because there are no internal pull ups to guarantee their state during prolonged three state conditions resulting from typical EZ ICE debugging sessions T hese resis tors may be removed at your option when the EZ ICE is not being used Target System Interface Signals When the EZ ICE board is in
60. re IACK Low use specifications tip su tion f Write Pulse ends after IACK Low use specifications tixsu tiu tkw p TACK tw Is twp IWR IAD 15 0 Figure 29 IDMA Write Short Write Cycle REV 0 27 ADSP 2181 ADSP 2183 ADSP 2181 Parameter Min Max Unit IDMA Write Long Write Cycle Timing R equirenents tikw IACK Low before Start of W rite 0 ns tiksu IAD 15 0 Data Setup before IACK L ow 0 5tcx 10 ns tiku IAD 15 0 Data H old after IACK L ow 3 2 ns Switching Characteristics tikLw Start of Write to IACK Low 1 5tck ns tikkw Start of Write to IACK High 15 ns ADSP 2183 28 8MHz Parameter Min Max Unit IDMA Write Long Write Cvcle Timing Requirements tikw IACK Low before Start of Write 0 ns tiksu IAD 15 0 Data Setup before IACK L ow 0 5tek 10 ns ku IAD 15 0 Data H old after IACK Low 2 ns Switching Characteristics tik Start of Write to ACK Low 1 5tck ns kuw Start of Writeto IACK H igh 17 ns NOTES Istart of Write IS Low and IWR Low 21f Write Pulse ends before IACK Low use specifications tipsu tipa 31f Write Pulse ends after IACK Low use specifications tixsy tikH T his is the earliest time for IACK L ow from Start of Write For IDM A Write cycle relationships please refer to the U ser s M anual tkw Ke TACK gt tikkw ha cw is WA IAD 15 0 Figure 30 IDMA Write Long Write Cycle 28 REV 0 ADSP 2181
61. ression routines U nbiased rounding is preferred for most algorithms Note BIASRND bitis bit 12 of the SPORT 0 Autobuffer Control register INSTRUCTION SET DESCRIPTION TheADSP 2181 AD SP 2183 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability T he assembly language which takes full advantage of the processor s unique architecture offers the following ben efits T he algebraic syntax eliminates the need to remember cryptic assembler mnemonics F or example a typical arithmetic add instruction such as AR AX0 AYO resembles a simple equation Every instruction assembles into a single 24 bit word that can execute in a single instruction cycle T he syntax is a superset AD SP 2100 Family assembly lan guage and is completely source and object code compatible with other family members Programs may need to be relo cated to utilize on chip memory and conform to the AD SP 2181 AD SP 2183 s interrupt vector and reset vector map Sixteen condition codes are available For conditional jump call return or arithmetic instructions the condition can be checked and the operation executed in the same instruction cycle M ultifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle 1 O Space Instructions T he instructions used to access the AD SP 2181 AD SP
62. s an external memory access ADSP 2181 ADSP 2183 If the AD SP 2181 AD SP 2183 is performing an external memory access when the external device asserts the BR signal then it will not three state the memory interfaces or assert the BG signal until the processor cycle after the access completes T he instruction does not need to be completed when the bus is granted If a single instruction requires two external memory ac cesses the bus will be granted between the two accesses When the BR signal is released the processor releases the BG signal reenables the output drivers and continues program ex ecution from the point where it stopped T he bus request feature operates at all times including when the processor is booting and when RESET is active T he BGH pin is asserted when the AD SP 2181 AD SP 2183 is ready to execute an instruction but is stopped because the exter nal bus is already granted to another device T he other device can release the bus by deasserting bus request Once the bus is released the AD SP 2181 AD SP 2183 deasserts BG and BGH and executes the external memory access Flag I O Pins T he ADSP 2181 AD SP 2183 has eight general purpose pro grammable input output flag pins T hey are controlled by two memory mapped registers The PFT Y PE register determines the direction 1 output and 0 input The PFDATA register is used to read and write the values on the pins Data being read from a pin configured as
63. ss System Design Programmable Wait State Generation Two Double Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On Chip Program Memory from Byte Wide External Memory e g EPROM or Through Internal DMA Port Six Extemal Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling ICE Port Emulator Interface Supports Debugging in Final Systems ICE Port is a trademark of Analog Devices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM POWERDOWN PROGRAMMABLE CONTROL VO MEMORY FLAGS EXTERNAL PROGRAM DATA BYTE DMA MEMORY MEMORY CONTROLLER ADDRESS BUS i k DATA BUS DATA ADDRESS GENERATORS DAG 1 DAG 0 PROGRAM MEMORY ADDRESS v DATA MEMORY ADDRESS PROGRAM MEMORY DATA Y DATA MEMORY DATA ARITHMETIC UNITS SERIAL PORTS SHIFTER SPORT 0 SPORT 1 N ADSP 2100 BASE ARCHITECTURE GENERAL DESCRIPTION T he ADSP 2181 AD SP 2183 is a single chip microcomputer optimized for
64. stalled the performance on some system signals change D esign your system to be compatible with the following system interface signal changes introduced by the EZ ICE board EZ ICE emulation introduces an 8 ns propagation delay between your target circuitry and the D SP on the RESET signal EZ ICE emulation introduces an 8 ns propagation delay be tween your target circuitry and the D SP on the BR signal EZ ICE emulation ignores RESET and BR when single stepping EZ ICE emulation ignores RESET and BR when in Emula tor Space D SP halted EZ ICE emulation ignores the state of target BR in certain modes As a result the target system may take control of the D SP s external memory bus only if bus grant BG is asserted by the EZ ICE board s DSP 11 ADSP 2181 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit Vpp Supply Voltage 4 5 5 5 4 5 5 5 V TAMB Ambient Operating T emperature 0 70 40 85 C ELECTRICAL CHARACTERISTICS K B Grades Parameter Test Conditions Min Max Unit Vin Hi Level Input Voltage 2 Vpp max 2 0 V Vin Hi Level CLKIN Voltage Vpp Max 2 2 V Vu Lo L evel Input Voltage 3 9 Vpp 2 min 0 8 V VoH Hi L evel Output Voltage 5 8 Vpp min lop 0 5 mA 2 4 V Vop min lon 100 pA Von 0 3 y VoL Lo L evel Output Voltage 5 8 Vpp min lo 22 mA 0 4 V liu Hi Level Input C urren 9 Vpp max
65. t loads 11 0 measurement taken with all instructions executing from internal memory 50 of the instructions are multifunction types 1 4 5 12 13 14 30 are type 2 and type 6 and 20 are idle instructions Py 70 4 V and 2 4 V For typical figures for supply currents refer to Power Dissipation section PApplies to T QFP and PQFP package types Output pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice 12 REV 0 ADSP 2181 ADSP 2183 ADSP 2181 ABSOLUTE MAXIMUM RATINGS Supply Voltage 0 3 V to 7 V Input Voltage cee eee 0 3 V to Vpp 0 3 V Output Voltage Swing 0 3 V to Vpp 0 3 V Operating T emperature Range Ambient 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature 5 se TQFP 000 280 C Lead T emperature 5 sec PQFP 4 280 C Stresses above those listed under Absolute M aximum Ratings may cause permanent damage to the device T hese are stress ratings only and functional operation of the deviceat theseor any other conditions abovethoseindicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD SENSITIVITY TheADSP 2181 is an ESD electrostatic discharge sensitive device Electrostatic ch
66. there are eight flags that are programmable as inputs connection the AD SP 2181 AD SP 2183 has a 16 bit Internal or outputs and three flags that are always outputs DMA port IDMA port for connection to external systems The IDMA port is made up of 16 data address pins and five A programmable interval timer generates periodic interrupts A l 16 bit count register T COUNT is decremented every n pro control pins The ID M A port provides transparent direct access cessor cycles Mid n is a scaling value stored in an 8 bit d d the iba program and gata RAM M ter T SCALE When the value of the count register reaches An interface to low cost byte wide memory is provided by the zero an interrupt is generated and the count register is reloaded Byte DMA port BDM A port The BDMA port is bidirectional from a 16 bit period register T PERIOD and can directly address up to four megabytes of external RAM Serial Ports or ROM for off chip storage of program overlays or data tables The AD SP 2181 AD SP 2183 incorporates two complete syn The byte memory and I O memory space interface supports slow chronous serial ports SPORT 0 and SPORT 1 for serial com memories and 1 0 memory mapped aes with pleas i munications and multiprocessor communication bis ee mde Gat BE end BG Here is a brief list of the capabilities of the AD SP 2181 ADSP One execution mode Go M ode allows the AD SP 2181 AD SP 2183 SPORT s Refer to the ADSP 2100 Family U ser s M
67. wer up sequence is complete Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN not including crystal oscillator start up time CLKIN CLKOUT Figure 22 Clock Signals 20 REV O ADSP 2181 ADSP 2183 ADSP 2181 Parameter Min Max Unit Interrupts and Flag Timing R equirenents tirs IRQx FI or PFx Setup before CLK OUT Low 0 25tck 15 ns tie IRQx FI or PFx Hold after CLKOUT Hight 3 4 0 25tck ns Switching C haracteristics trou Flag Output H old after CLK OUT Low 0 5tck 7 ns trop Flag Output D elay from CLK OUT Low 0 25tck 5 ns ADSP 2183 28 8 MHz Parameter Min Max Unit Interrupts and Flag Timing R equirenents tirs IRQx FI or PFx Setup before CLKOUT Low 0 25tc 15 ns ten IRQx FI or PFx Hold after CLKOUT High 34 0 25tck ns Switching C haracteristics trou Flag Output H old after CLKOUT Low 0 5tcyk 7 ns trop Flag Output D elay from CLK OUT Low 0 25tc 6 ns NOTES Nf IRQx and FI inputs meet tirs and tiry setup hold requirements they will be recognized during the current clock cycle otherwise the signals will be recognized on the following cycle Refer to Interrupt Controller Operation in the Program Control chapter of the U ser s M anual for further information on interrupt servicing 2E dge sensitive interrupts require pulse widths greater than 10 ns level sensitive interrupts must be held low until servic

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