Agilent Technologies ES Network Card User Manual
Contents
1. Pod 1 channel 0 can be configured to view any one of the four Viewing the PCI interrupts Move the jumper so that it corresponds to the interrupts desired interrupt and that interrupt line will be routed to POD 1 channel 0 The jumper and interrupt stake pins are clearly labeled and are located under POD 7 Interrupt Jumper 0 Channel 1 INT lt o o gt 2 2 2 Configuring the front Swen sme o panel switches and Parity On Parity Checking ON LEDs enabled Parity On Parity checking OFF disabled No Wait No Wait cycles ON acquired No Wait All Wait cycles OFF acquired No Idle No Idle cycles ON acquired No Idle All Idle cycles YES acquired TDO TDI TDO connected to No LED switch in TDI rightmost position TDO TDI TDO not connected No LED switch in to TDI leftmost position 10 Powering the PCI Active Analysis Probe Connecting to the PCI Active Analysis Probe No Idle PCI Active Analysis Probe front panel The active circuitry on the PCI Active Analysis Probe module gets its power from the logic analyzer PODs No power is taken from the target PCI system Please Note If the Analysis Probe is plugged into the PCI bus and the logic analyzer is not connected or powered up the input buffers on the Analysis Probe will create a low impedance path to ground thus inhibiting the PCI local bus and any card in the extender card connector f2. 32 bit Demultiplexed Analysis Probe PODS 0 1 6 connect to Logic Analyzer PODS 1 6 166x P64M 66 64 bit Multiplexed Analysis Probe PODS 1 0 4 7 8 11 to Logic Analyzer PODS 1 7 16550A 2 55 32 bit Multiplexed Analysis Probe PODS 1 4 0 connect to Logic Analyzer PODS 1 4 16550A P32D 55 32 bit Demultiplexed Analysis Probe PODS 0 1 6 connect to Logic Analyzer PODS 1 6 P 0 16550A 64AD55 32 bit address Demultiplexed and 64 bit data Analysis Probe PODS 1 6 7 8 and 11 connect to Logic Analyzer PODS 1 6 on the Master card and 1 3 on the Slave card respectively 16550A P64M 55 64 bit Multiplexed Analysis Probe PODS 1 0 4 7 8 11 connect to LA PODS 1 6 on the Master card and Pod 1 on the Slave card respectively 16550A P64D 55 64 bit Demultiplexed Analysis Probe PODS 0 1 11 connect to Logic Analyzer PODS 1 6 on the Master card and PODS 1 5 on the Slave Card respectively 1655x 167x P32M 55 32 bit Multiplexed Analysis Probe PODS 1 4 5 connect to Logic Analyzer PODS 1 4 1655x 1670 71 1655x 1670 The PCI Inverse Assembler The Format Menu P32D 55 32 bit Demultiplexed Analysis Probe PODS 5 1 6 connect to PODS 1 4 on the Master card and 1 2 on the Slave card 1 2 respectively PODS 1 6 on the 1670 71 P64M 55 64 bit Multiplexed Analysis Probe PODS 1 5 4 7 8 11 connect to Logic Analyzer PODS 1 4 on the Master card and PODS 1 3 on the Slave Card respectively PODS 1 7 on the 11670 P64D 55
3. 000DH 000 000 0018H 0020H 0021H 0040H 0042H 0043H 0044H 0047H 0060H 0061H 0064H 0070H 0071H 0074H 0075H 0076H 0081H 0082H 0083H 0087H 0089H 008AH 008BH 008FH 0090H 0091H 0092H 0094H 0096H 00A1H 00COH 00C2H 00C4H SLAVE DMA CH5 MEM ADDR 30 0000H 0001H 0002H 000 0004H 0005 0000H 0007H_ 0008 0009H 00044 0000 0005 0000 O00EH O00FH 0018 0020H O021H 00408 00428 00438 _____ 0044 0047H 0060H 0061 00648 _____ 00708 _____ 00711 004 0075H 0076H 0081H 0082H 0088H 0087H 0089H 008AH 0088 O08FH 00908 0091 0020 00948 00968 _____ 0025 NUMERIC COPROCESSOR PORT OOF9H NUMERIC COPROCESSOR PORT ADAPTER CARD POS REG 6 SERIAL PORT 2 MODEM CNTRL PARALLEL PORT 2 STAT PORT 03BAH VGA STAT 1 FEATURE CNTRL 03C8H VIDEO DAC PAL ADDR WRITE 03C9H VIDEO DAC PALETTE DATA 31 SERIAL PORT 1 XMIT RCV BUF O3FCH SERIAL PORT 1 MODEM CNTRL 32 Timing Analysis Installation Quick Reference Timing Mode Skew The following procedure describes the major steps required to perform timing analysis measurements with the PCI Active Analysis Probe module 1 Set the State Timing switch to TIMIN
4. Probe module 1 After removing the probe tip assemblies plug the logic analyzer cables into the Analysis Probe cable headers See page 11 of this manual for details 2 Setthe STATE TIMING switch to STATE The State LED will be lit 3 Power off the target Install the PCI Active Analysis Probe module into a slot in the target PCI Local bus Then power on the target Load the logic analyzer configuration file by loading the appropriate file from the Analysis Probe interface diskette See page 16 of this manual for details The front panel switches are only useful in STATE MODE They are clearly marked on the front panel Parity On switch controls parity checking If the Parity On LED is lit then parity checking will be done e The No Wait switch controls the acquisition of WAIT cycles If the No Wait LED is lit then no wait cycles will be acquired e No Idle switch controls the acquisition of IDLE cycles If the No Idle LED is lit then NO IDLE cycles will be acquired TDO TDI switch from the top connects TDO to TDI If the switch is to the rightmost position TDO is connected to TDI e The State Timing switch controls the on board latches When the State LED is lit then the PCI Active Analysis Probe is in State mode Refer to page 10 for more details on the LEDs and switches 23 Acquiring Data The State Display Touch RUN and as soon as there is activity on the bus the logic analyzer w
5. is not applicable to timing mode Therefore for 32 bit timing mode analysis does not require PODS 5 and 6 and 64 bit timing mode analysis does not require PODS 9 and 10 If switching between demultiplexed state and timing mode those PODS can be ignored when in timing mode If doing only timing mode the multiplexed files should be used Touch RUN and the logic analyzer will begin to acquire data The analyzer will continue to acquire data and will display the data when the analyzer memory is full the trigger specification is TRUE or when you touch STOP The logic analyzer will flash Waiting for Trigger while the trigger specification is NOT TRUE Captured data is displayed as shown in the following figure 34 100 500MHz LA E Control Run Bccumulate Current Sample Period 4 000 ns off Next Sample Period 4 000 ns sec Diy Delay Markers Acquisition Time 50 ns 192 6 ns off 21 Jul 1994 13 42 55 C B3_0all ee ADDR all 00000000 020 08080808 FRANE DEVSEL IDSEL 35 General Information This chapter provides additional reference information including the characteristics and signal connections for the PCI Active Analysis Probe module Characteristics The following operating characteristics are not specifications but are typical operating characteristics for the PCI Active Analysis Probe module Analysis Probe Interface 32 64 bit PCI Local bus accept
6. transaction Useful as a store qualifier In timing mode the GNT from the PCI bus is passed through to the logic analyzer L CMD The latched The C BE signals latched during the command lines command address phase and held until end of transaction AVALID_L Address Valid True on the first assertion of FRAME and the rising edge of the PCI clock True for one cycle except on Dual Address cycles when it is true for two cycles Parity checking is only available in STATE Mode and is controlled by the PARITY ON switch on the front panel The parity generation is done by the IDT 162511 latching buffers Only data parity is generated and then checked against the data parity that is transferred on the bus If they are not the same then the signal CPERR_L will be asserted on the cycle that the parity is valid This signal will remain valid for one clock tic 22 State Analysis Installation Quick Reference Using the front panel switches in state mode This chapter explains how to configure the PCI Active Analysis Probe to perform state analysis on the PCI Local Bus The configuration software on the flexible diskette sets up the format specification menu of the logic analyzer for compatibility with the PCI Local Bus The next chapter explains how to configure the PCI Active Analysis Probe to perform timing analysis The following procedure describes the major steps required to perform measurements with the PCI Active Analysis
7. will display the data when the analyzer memory is full the trigger specification is TRUE or when you touch STOP The logic analyzer will flash Slow or Missing Clock if the PCI Clock signal is not being detected by the logic analyzer In this case check the logic analyzer to PCI Active Analysis Probe connection refer to your User s Manual 25 The State Display with the PCI PC Mapper Captured data is as shown in the following figure The first figure displays the state listing after disassembly The PCI PC Mapper is constructed so the mnemonic output closely resembles the actual commands status conditions messages and phases specified in the PCI Local Bus specification Symbols have also been defined to help aid in analysis The non disassembled state listing displays bus mnemonics in addition to data All data is displayed in hex One exception is the decode of the address for a CONFIGURATION READ or a CONFIGURATION WRITE transaction The Function and Bus BUS data is displayed in decimal 1 5 La B Listing 1 Harkers Find 65 fram Specify Pattern X pattern Trigger Patterns Label Time FUTUREPLUS SYSTEMS c 1996 RDDR B Base Relative PCI BUS TRANSACTIONS REV 1 2 Hex 960 304 ns READ ADR O000F 1008 OOOF 1D 961 3 704 us D32 E0 154300 OOOF 1D 962 200 ns READ ADR O00F 1DCC OOOF 10 963 3 664 us D32 E9CSE40B OOOF 1D 964 264
8. 0 OBFFFF 0A0000H Video Memory O9FFFF 000400H System Memory 0003FF 000000H See Interrupt Vector Table 27 Interrupt Vector Address bits PC Mapper output Table 0003C4H 000200H 0001 0001DCH 0001D8H 0001D4H 0001D0H 0001CCH 0001 8 0001 4 0001 0 0001A0H 00019CH 000180H 00012CH 000128H 00011CH 000118H 000110H 00010CH 000108H 000104H 000100H 000080H 00007CH 000078H 000074H 000070H 00006CH 000068H 000064H 000060H 00005CH 000058H 000054H 000050H 00004CH 000048H 000044H 000040H 00003CH 000038H 000034H 000030H 00002CH 000028H 000024H 000020H 00001CH 000018H 000014H INT 405 PRINT SCREEN 28 23 0 0003C4H 000200H 0001E0H 0001DCH 0001D8H 000104 000100 00015 000128 0001C4H_ 0001120 00019CH 000180H 00012CH ____ 000128H 000110 0001184 00010 00010CH 000108 000104 000100H 000080 000070 00001 00004 00007 000066 0000688 000044 000080 000055 000058 000054 000050H 00004CH 000048H 000044 00040 0000550 000088H 000034H 000030 0000205 0000288 000044 000020 000104 00001184 000008H INT 02 000004 INT 01 SINGLE STEP 000000H INT 00 DIVIDE BY ZERO 29 Transactions 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000BH 000CH
9. 00003F 1 000005 5 000095 HEN READ ADR 000F 1000 OOOF 1D D32 DIEGB B 1 READ 000 1004 1D D32 1EC3C 303 aooF ID Error Messages INVASM OPTIONS Setting up the Analyzer to use the PC Mapper Inverse Assembler Acquiring Data The following error messages are reported by the PCI inverse assembler ERROR NO DEVICE SELECTED This error is displayed during a non special cycle data phase when IRDY and TRDY are asserted and DEVSEL is not asserted ERROR DEVSEL ASSERTED This error is displayed during a special cycle data phase if DEVSEL is asserted SYSTEM ERROR This error is displayed anytime SERR is asserted The INVASM OPTIONS feature is not included with the PCI Active Analysis Probe software The same or better capability for post processing acquired data can be achieved using the 16505A Pattern Filters After the configuration file is loaded the PCI PC Mapper software can be loaded 1 Install the PCI Analysis Probe software flexible diskette in the disk drive of the logic analyzer 2 Configure the menu to Load the analyzer that is connected to the PCI Active Analysis Probe with the file names IAP64EXM 3 Execute the load operation to load the file into the logic analyzer Data can be acquired by touching the RUN button As soon as there is activity on the bus the logic analyzer will begin to acquire data The analyzer will continue to acquire data and
10. 1 Header 1 POD 3 Header 3 POD 4 Header 4 POD 5 Header 5 16554 5 6 7 expander card POD 1 Header 6 16554 5 6 7 expander card POD 2 32 bit PCI Multiplexed Logic Analyzer Cann Probe 12 64 bit PCI Multiplexed Logic Analyzer PCI Active Analysis Comment Probe POD 5 Header 7 16554 5 6 7 expander card POD 1 POD 6 Header 8 16554 5 6 7 expander card POD 2 POD 7 Header 11 16554 5 6 7 expander card POD 3 16550 expander card Pod 1 64 bit PCI Demultiplexed Logic Analyzer PCI Active Analysis Comment Probe soos Wee Wee POD 5 Header 5 16554 5 6 7 expander card POD 1 POD 6 Header 6 16554 5 6 7 expander card POD 2 POD 7 Header 7 16554 5 6 7 expander card POD 3 16550 expander card Pod 1 POD 8 Header 8 16554 5 6 7 expander card POD 4 16550 expander card Pod 2 13 USER PINS Installing the PCI Active Analysis Probe Header 9 16554 5 6 7 expander 2 card POD 1 16550 expander card Pod 3 POD 10 Header 10 16554 5 6 7 expander card POD 2 16550 expander card Pod 4 POD 11 Header 11 16554 5 6 7 expander card POD 3 16550 expander card Pod 5 PCI Active Analysis Probe Header 4 contains 8 User Defined pins These pins are available to the user to connect whatever additional signals the users wishes to view along with the PCI bus These pins are located below POD 3 on the PCI Active Analysis Probe module and clearly marked
11. 64 bit Demultiplexed Analysis Probe PODS 5 1 11 connect to Logic Analyzer PODS 1 4 on the Master card 1 4 on the lower slave card positioned below the master card in the mainframe and PODS 1 3 on the slave card positioned above the master card in the mainframe respectively P64AD55 32 bit address Demultiplexed and 64 bit data 5 Analysis Probe PODS 1 6 7 8 and 11 to Logic Analyzer PODS 1 4 on the Master card 1 4 on the lower slave card positioned below the master card in the mainframe and POD 1 on the slave card positioned above the master card in the mainframe respectively The PCI Active Analysis Probe Inverse Assembler file IAP64E is automatically loaded into the logic analyzer when the configuration file is loaded If the Inverse Assembler does not appear on the state listing screen select the base of the label DATA From the menu that appears select INVASM The Inverse Assembler is only for use in state mode The PCI Active Analysis Probe diskette sets up the format menu to include all of the signals that are presented to the logic analyzer This format is the same for both Timing and State Analysis the labels STAT DATA DATA B ADDR and ADDR B are required in order run the Inverse Assembler They should not be changed or deleted 17 The STAT variable The STAT variable is used by the PCI inverse assembler to decode PCI bus transactions should not be changed deleted from the format menu sig
12. D05 42 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number Ps s 43 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number 05 tw s m O s s fon m s m s tw 44 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number m A 45 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number 46 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number xw Ps AD55 AD54 47 Analysis Probe Cable Header and Pin number Header 11 pin 3 1 1 1 1 1 2 2 2 2 2 3 3 3 5 7 1 3 5 7 9 1 3 5 7 9 1 3 5 7 48 Logic Analyzer channel number CLK 16 no connect 15 14 13 12 11 10 7 1 Signal name USER PIN 8 USER PIN 7 USER PIN 6 USER PIN 5 USER PIN 4 USER PIN 3 USER PIN 2 USER PIN 1 LOCK PAR64
13. FuturePlus Systems Corporation 9 Agilent Technologies SES Innovating the HP Way Premier Solution Partner LOCAL BUS Active Analysis Probe Users Manual FS2100 FS2101 For Agilent Technologies Logic Analyzers Revision 1 8 FuturePlus is a trademark of FuturePlus Systems Corporation Copyright 1998 FuturePlus Systems Corporation HOW TO REACH US PRODUCT WARRANTY Limitation of warranty Exclusive Remedies Assistance INTRODUCTION How to Use This Manual ANALYZING THE PCI LOCAL BUS Duplicating the Master Diskette Accessories Supplied Minimum Equipment Required Signal Naming Conventions Viewing the interrupts Configuring the front panel switches and LEDs Powering the PCI Active Analysis Probe Connecting to the PCI Active Analysis Probe Multiplexed versus Demultiplexed 32 bit PCI Demultiplexed 32 bit PCI Multiplexed 64 bit PCI Multiplexed 64 bit PCI Demultiplexed USER PINS Installing the PCI Active Analysis Probe How to install a PCI add in card into the extender card connector Operation of the PCI add in card The Extender Card Connector Setting up the Analyzer from the diskette The PCI Inverse Assembler 14 15 15 15 16 17 The Format Menu The STAT variable The ADDR ADDR C DATA B and DATA variables The BUS UT variable The CMD variable Theory of Operation The Input Buffers The Latching Buffers The interface to the Logic Analyzer The Clocking and Cycle bi
14. G The State LED will be doused See page 10 of this manual for details on the front panel switches After removing the probe tip assemblies plug the logic analyzer cables into the Analysis Probe cable headers See pages 12 and 13 of this manual for details Power down the PCI target Install the PCI Active Analysis Probe module into a slot in the non powered target PCI Local bus Then power up the target Load the logic analyzer configuration file by loading the appropriate file from the Analysis Probe interface diskette See pages 16 and 17 of this manual for details Since the PCI Active Analysis Probe contains active input buffers it introduces skew to the PCI Local Bus signals The skew is as follows Any PCI bus signal to the PCI clock 1 0 to 2 3ns maximum Any PCI bus signal to any other PCI bus signal 2 1ns maximum 33 Using the Cycle bits and L CMD lines Demultiplexed versus Multiplexed Acquiring Data The Waveform Display Although the Cycle bit and the CMD lines were designed for state analysis they can prove to be very useful in Timing analysis These bits can be effectively used to trigger the timing analyzer Note that the cycle bits and CMD lines pass through more active logic than the PCI signals directly from the bus For this reason they may not line up exactly with the ADDR lines and should not be used for precise timing measurements The demultiplexed feature of the PCI Active Analysis Probe
15. Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number Header 1 pin 3 CLK 16 PCI Clock 1 L CMDO s m s 38 Analysis Probe Logic Analyzer Signal name Cable Header and channel number Pin number Header 2 pin 3 CLK 16 GNT_L UN no connect 14 IDSEL Re mp ug WNODEV ae ACK64 DATA64 fd TABORT_L RETRY 0249 WTARGET a WINITI_L DVALID E 8 PVALID MABORT L CPERR L 1 EOFT 1 5 7 11 13 15 17 19 21 23 25 27 29 31 33 35 7 39 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number m m s ww 40 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number O s 7 s ew ew w wm wm m os ww COo 27 2 5 7 1 13 15 1 19 2 23 25 9 3 33 35 1 7 1 1 7 NEN Ep 4 AD ADS 8 197 0 fais 41 Analysis Probe Logic Analyzer PCI Signal name Cable Header and channel number Pin number Header 5 pin 3 CLK 16 Readers pnd s 3 s ww s w ww m s ww m s ww 27 A
16. These user pins are available on the logic analyzer on POD 11 channels 15 thru 8 These pins may be used to connect the individual IDSEL signals from other PCI slots or the bus grant signals from the PCI bus arbitration logic The PCI Active Analysis Probe can be installed in any slot of the PCI Local bus The following steps explain how to install the PCI Active Analysis Probe into the PCI Local bus 1 Install the logic analyzer cables as described in the previous section 2 Power off the PCI target Align the PCI module with the appropriate slot on the target system and plug the module into the PCI connector Power on the logic analyzer and then power on the target If your PCI Local bus is 32 bits the upper portion of the edge connector will not be inserted into any connector This will not affect the modules operation on a 32 bit PCI Local bus 14 How to install a PCI add in card into the extender card connector Operation of the PCI add in card The Extender Card Connector The card edge connector of the PCI Active Analysis Probe module can accommodate 32 or 64 bit 5V OR 3V PCI add in card extender card connector is either or 5V connector depending on how the board was ordered and configured at the factory Simply align the module with the connector and gently push the module in until it is seated in the connector There is sufficient clearance for the add in card front plate The PCI Active A
17. alyzer interface presents only one electrical load on each PCI bus signal However the extender card connector is an additional 4 inches beyond the maximum allowed stub length All PCI Local Bus operations supported Operating 0 to 55 degrees C 32 to 131 degrees F Non operating 40 to 75 degrees C 40 to 167 degrees F Operating 4 6000m 15 000 ft Non operating 15 3000m 50 000 ft Up to 9096 non condensing Avoid sudden extreme temperature changes which would cause condensation on the Analysis Probe module There are no automatic performance tests or adjustments for the PCI Active Analysis Probe module If a failure is suspected in the PCI Active Analysis Probe module contact the factory or your FuturePlus Systems authorized distributor The repair strategy for the PCI Active Analysis Probe is module replacement However if parts of the PCI Active Analysis Probe module are damaged or lost contact the factory for a list of replacement parts 37 Signal Connections The PCI Active Analysis Probe module monitors signals for both state and timing analysis The below figure displays how the cable headers are numbered 39 37 35 33 31 29 27 25 2321 19 17 15 13119 75 31 40 38 36 34 32 30 28 26 24 22 20 18 16 14 121086 42 The following tables list the PCI Active Analysis Probe cable headers and the corresponding PCI Local Bus signals after these signals have been terminated by the 90K ohm 10pf terminators Analysis
18. e will be uninterrupted or error free The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED FUTUREPLUS SYSTEMS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for FuturePlus Systems products For assistance contact the factory Introduction How to Use This Manual The PCI Active Analysis Probe module provides a complete interface between any PCI add in slot and Agilent Logic Analyzers The Analysis Probe interface buffers and in state mode latches and decodes all PCI cycle types and transactions The PCI Active Analysis Probe is a passive bus monitor which does not assert any signals on the PCI bus The PCI bus signals are buffered and then terminated with 90k ohm 10pf terminators so that they are impedance matched to the logic analyzer Since the PCI Active Analy
19. he rising edge of the PCI clock The input to the latching buffers is output port 1 from the input buffers The latching buffers are IDT 162511 latching buffers with party generation These buffers are tri stated in timing mode In state mode their outputs go directly to the logic analyzer input terminators The User pin signals are not latched The input to the logic analyzer consists of 3 parts 1 The RC terminators 90 1 2 The 40 pin headers 3 The 40 pin cables The user is instructed to remove the probe tip assemblies from the logic analyzer headers The 40 pin logic analyzer headers then go directly the 40 pin headers of the Analysis Probe provided cables Any unused cables can be removed from the Analysis Probe The logic analyzer provides the power to the onboard logic No power is obtained from the target The master clock is controlled by the front panel switches and is generated by the on board CPLD devices When the user has loaded the DEMULTIPLEXED configuration file an additional Slave clock is added This Slave clock is the falling edge of the Analysis Probe generated AVALID signal This signal asserts with the first assertion of FRAME and the rising edge of the PCI clock All of the PCI cycle bits are generated based on the latched version of the PCI control signals Their meaning is listed in the following table EOFT L End of Transaction True for one clock cycle and indicates the last cycle of a t
20. ill begin to acquire data The analyzer will continue to acquire data and will display the data when the analyzer memory is full the trigger specification is TRUE or when you touch STOP The logic analyzer will flash Slow or Missing Clock when the data is not being transmitted across the bus Captured data is as shown in the following figure The below figure displays the state listing after disassembly The inverse assembler is constructed so the mnemonic output closely resembles the actual commands status conditions messages and phases specified in the PCI Local Bus specification Symbols have also been defined to help aid in analysis The non disassembled state listing displays PCI bus mnemonics in addition to data All data is displayed in hex One exception is the decode of the address for a CONFIGURATION READ or a CONFIGURATION WRITE transaction The Function and Bus BUS data is displayed in decimal 100 500HHz LA B Listing 1 Run Harkers Find 65 from Specify Pattern x pattern Trigger Patterns FUTUREPLUS SYSTEMS c 1996 BDDR B PCI BUS TRANSACTIONS REV 1 2 1960 1961 3 1962 1963 3 1964 1965 1 1966 1967 a 1968 1969 3 304 704 200 664 264 200 272 600 200 654 ns us ns us ns us ns us ns us READ ABHDR 000FI1DCG OOOF 1D 652 015 5 0 aooF 10 READ ADR O00F 10CC OOOF 1D 52 I O WRITE nDR O0O
21. ing the short card length and Compatibility universal connector pinout All PCI local bus ground pins of the universal board pinout are connected to the ground plane of the PCI Active Analysis Probe module JTAG Boundary Scan The PCI Active Analysis Probe does not implement JTAG Boundary SCAN Pins TDI and TBO pins 4a and 4b are connected together so the scan chain is not broken The PCI Present Pins The PCI signals 1 and 5 2 are routed to the PCI Active Analysis Probe extender card connector Standards Supported The PCI Local Bus Specification Revision 2 1 Power Requirements The PCI Active Analysis Probe contains several active components that buffer the PCI signals before they are acquired by the logic analyzer The Analysis Probe takes no power from the PCI bus but is powered by the logic analyzer Logic Analyzer Required 1660A C 1661A C 1662A C 16550A 16554A 16555A 16556A 1670A 1671A 1672A Number of Probes Used 32 bit PCI multiplexed 4 cable headers 32 bit PCI demultiplexed 6 cable headers 32 bit address demultiplexed 64 bit data 9 headers 64 bit PCI multiplexed 7 cable headers 64 bit PCI demultiplexed 11 cable headers 36 Minimum Clock Period State Signal loading Operations Environmental Temperature Altitude Humidity Testing and Troubleshooting Servicing 0 to 33Mhz PCI clock for State mode and 0 100Mhz for Timing Mode The PCI Active Analysis Probe logic an
22. nals that make up the STAT variable are listed in the following table The STAT variable can be useful to set up SYMBOLS since it contains all of the key PCI control and status signals STAT Variable PCI Bus Signal Name C BE7 C BE6 C BE5 4 AVALID 1 WNODEV L ACK64 DATA64 Bit 21 TABORT_L mm mw mw mw bi mu wei so DEVSEL C we 18 The ADDR ADDR B ADDR C DATA B and DATA variables are defined in the format menu and used to pass the AD line The ADDR ADDR B information to the Inverse Assembler during state analysis They gt are mapped as shown in the below table These variables DANT should not be changed or deleted from the format Menu Mode ADDR ADDR ADDR C DATA DATA B NOT USED NOT USED NOT USED UPPER 32 AD LINES ADDRESS The BUS UT variable The Bus Utilization BUS UT variable is made up of the following cycle bits WNODEV ADVALID TABORT DVALID WTARGET WINITI RETRY IDLE MABORT The list of symbols defined for this variable are the signal names themselves This is a convenient grouping that helps make triggering and performance analysis easier This variable is the C BE 3 0 lines latched with the first rising The L CMD variable edge of the PCI clock with FRAME asserted These signals are held until the end of the
23. nalysis Probe PCI add in card combination can then be installed in any slot of the PCI Local bus For mechanical stability the PCI Active Analysis Probe front plate should be secured to the PCI target system chassis When removing the PCI add in card from the card edge extender connector grasp the PCI Active Analysis Probe with one hand and the PCI add in card with the other Gently rock the PCI add in card until it is free from the connector The nature of an extender card is that it extends the etch length of the bus Due to the sensitivity of most PCI designs extending the etch length can interfere with the PCI add in card operation Operation of the PCI add in card when installed in the card edge extender connector is not guaranteed Please check your system design if you experience failures due to poor signal fidelity The etch from the PCI local bus is routed directly from the PCI local bus to the extender card connector Although the etch is connected to the input of the PCI Active Analysis Probe input buffers the extender card connector is NOT buffered from the PCI local bus Please Note If the Analysis Probe is plugged into the PCI bus and the logic analyzer is not powered up the input buffers on the Analysis Probe will create a low impedance path to ground thus inhibiting the PCI local bus and any card in the extender card connector from working The PCI bus is extended up from the gold fingers to the input of the IDT162260 b
24. ns I O WRITE ADR 000003F 1 000003 965 1 200 us 32 000003 966 272 ns MEM READ ADR 000F 1000 QOF 1D 967 3 500 us D32 D1ESBCO7 OOOF 1D 968 200 ns READ ADR 000F 1004 DOOFID 969 3 664 us D32 1EC3C303 OOOF 1D The above display data using the PCI Inverse Assembly software without the PCI PC Mapper functionality is shown as follows 100 500nHz La Listing 1 Markers Find 65 from Specify Pattern M pattern Trigger Patterns Label Time FUTUREPLUS SYSTEMS c 1996 ADDR_B Base Relative PCI BUS PC MAPPER REV 1 2 Hex READ ADR 000F 1008 961 3 704 us D32 E015A3C0 OOOF 1D 962 200 ns SYSTEM BIOS OOOF 1D READ ADR 000F 1DCC 963 3 664 us D32 E9C3E40B OOOF 1D 964 264 ns FLOPPY STATUS REG B 000003 170 WRITE ADR 000003F 1 965 1 200 us 52 000005 966 272 ns SYSTEM BIOS OOOF 1D READ ADR 000F 1000 967 3 600 us D32 DIEGSBCa OOOF 1D 968 200 ns SYSTEM BIOS OOOF 1D 26 Error Messages The error messages reported by the PCI PC Mapper are the same as those reported with the standard non mapper version of the PCI Inverse Assembler PCI PC Mapping for This section lists the addresses the commands and the corresponding mapping done by the PCI PC Mapper software memory transactions For information on the standard PCI configuration register mapping please refer to the PCI Local Bus Specification Rev 2
25. opy of the master diskette Then store the master diskette and use the back up copy to configure your logic analyzer This will help prevent the possibility of losing or destroying the original files in the event the diskette wears out is damaged or a file is accidentally deleted To make a duplicate copy use the Duplicate Diskette operation in the disk menu of your logic analyzer For more information refer to the reference manual for your logic analyzer The PCI Active Analysis Probe product consists of the following accessories e Analysis Probe interface hardware which includes the interface circuit module e one jumper which is installed on the circuit module e The inverse assembly and configuration software on 3 5 inch diskette e 11 cables This operating manual The PCI Active Analysis Probe module Minimum Equipment The minimum equipment required for analysis of a PCI Local Bus consists of the following equipment Required oa e 1660 1661A C 1662A C 16550A 16554A 16555A 16556A 1670A 1671A 1672A e The PCI Active Analysis Probe Product e APOItarget bus Signal Naming This operating manual uses the same signal notation as the PCI Conventions LOCAL BUS SPECIFICATION REVISION 2 1 That is a symbol at the end of a signal name indicates that the signals active state occurs when it is at a low voltage The absence of a symbol indicates that the signal is active at a high voltage
26. ransaction CPERR L Calculated Parity True for one clock cycle and indicates that the on board parity logic has detected a parity that is different than the parity transmitted on the bus Please note that the Parity Checking switch must be in the ON position MABORT L Master Abort True when a Master Abort condition has been detected Five clock cycles on a single data transfer with no DEVSEL assertion and six clock cycles on a multi beat transfer with no DEVSEL asserted Remains true for one clock cycle 21 The Data Parity Checking Logic PVALID L Parity Valid True for the cycles in which parity is being transmitted on the PCI bus IDLE L Idle cycle True when the bus is IDLE False when the bus is busy DVALID L Data Valid True when data is being transferred on the PCI bus WINITI L Master Initiated True when a wait state is being initiated Wait State by the master WTARGET L Target True when a wait state is being initiated Initiated Wait State by the target Retry True when a retry condition has been detected on the PCI bus TABORT L Target Abort True when a Target Abort condition has been detected on the PCI bus This signal is true for one clock bit WNODEV Wait state True when a wait state has been caused by no assertion of caused by no assertion of DEVSEL DEVSEL GNT_L The Grant signal for In State Mode this signal is latched and that slot held until end of
27. rom working The Logic analyzer must be connected and powered on for the PCI Active Analysis Probe to work properly ONLY connect to the analysis probe headers 7 10 if you are doing 64 bit analysis Latchup may occur on the 64 bit interface parts if they are powered on and not on a 64 bit bus The following explains how to connect the logic analyzer to the PCI Active Analysis Probe for either state or timing analysis 1 Remove the probe tip assemblies from the logic analyzer cables 2 Plug the logic analyzer cables into the PCI Active Analysis Probe cable headers as shown in the appropriate following tables 11 Multiplexed versus The PCI Local Bus specification specifies that the AD lines and Demultiplexed the C BE lines carry different information at different times This is referred to as multiplexed Using the extra clocking features and additional pods of the logic analyzer the AD lines can be demultiplexed By using the PCI Active Analysis Probe in demultiplexed mode the address of the transaction can be held throughout the transaction thus making triggering and performance analysis easier Please note that the C BE lines have been demultiplexed on the PCI Active Analysis Probe Thus the command is held through the transaction and no additional clocking or pods is required The latched command CMD signals are on pod 1 channels 10 7 32 bit PCI Demultiplexed Logic Analyzer PCI Active Analysis Comment Probe Master POD
28. s Systems Corporation TEL 719 278 3540 FAX 719 278 9586 On the web http www futureplus com FuturePlus Systems has technical sales representatives in several major countries For an up to date listing please see http www futureplus com contact html Agilent Technologies is also an authorized reseller of many FuturePlus products Contact any Agilent Technologies sales office for details Product Warranty Limitation of warranty Exclusive Remedies Assistance This FuturePlus Systems product has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment During the warranty period FuturePlus Systems will at its option either replace or repair products proven to be defective For warranty service or repair this product must be returned to the factory For products returned to FuturePlus Systems for warranty service the Buyer shall prepay shipping charges to FuturePlus Systems and FuturePlus Systems shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to FuturePlus Systems from another country FuturePlus Systems warrants that its software and hardware designated by FuturePlus Systems for use with an instrument will execute its programming instructions when properly installed on that instrument FuturePlus Systems does not warrant that the operation of the hardware or softwar
29. sis Probe does contains high speed low skew buffers very little skew is introduced The configuration software on the diskette sets up the format specification menu of the logic analyzer for compatibility with your PCI bus When the state configuration file is loaded an inverse assembler is also loaded which decodes PCI transactions into easy to read mnemonics This manual is organized to help you quickly find the information you need Analyzing the PCI Local Bus chapter introduces you to the PCI Active Analysis Probe and lists the minimum equipment required and accessories supplied for PCI bus analysis e State Analysis chapter explains how to configure the PCI Active Analysis Probe to perform state analysis on your PCI bus e The Timing Analysis chapter explains how to configure the PCI Active Analysis Probe to perform timing analysis on your PCI bus e The General Information chapter provides some general information including the operating characteristics for the PCI Active Analysis Probe module and the cable header pinout Analyzing the PCI Local Bus Duplicating the Master Diskette Accessories Supplied This chapter introduces you to the PCI Active Analysis Probe and lists the minimum equipment required and accessories supplied for PCI Local Bus analysis This chapter also contains information that is common to both state and timing analysis Before you use the PCI Analysis Probe software make a duplicate c
30. t Generation Logic The Data Parity Checking Logic STATE ANALYSIS Installation Quick Reference Using the front panel switches in state mode Acquiring Data The State Display Error Messages INVASM OPTIONS Setting up the Analyzer to use the PC Mapper Inverse Assembler Acquiring Data The State Display with the PCI PC Mapper Error Messages PCI PC Mapping for memory transactions Interrupt Vector Table PCI PC Mapping I O Transactions TIMING ANALYSIS Installation Quick Reference Timing Mode Skew Using the Cycle bits and L CMD lines Demultiplexed versus Multiplexed Acquiring Data 23 23 23 24 24 25 25 25 25 26 27 27 28 30 33 33 33 34 34 34 The Waveform Display GENERAL INFORMATION Characteristics Analysis Probe Interface Compatibility JTAG Boundary Scan The PCI Present Pins Standards Supported Power Requirements Logic Analyzer Required Number of Probes Used Minimum Clock Period State Signal loading Operations Environmental Temperature Altitude Humidity Testing and Troubleshooting Servicing Signal Connections 34 36 36 36 36 36 36 36 36 36 37 37 37 37 37 37 37 37 38 How to reach us For Technical Support FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL 603 471 2734 FAX 603 471 2738 On the web http www futureplus com For Sales and Marketing Support FuturePlu
31. transaction They indicated the command that is being transmitted on the PCI Local bus Below is the encoding of these signals and the symbols defined for the L CMD variable These encodings can also be found in the PCI Specification Symbol L CMD encoding INTACK 0000 RD 0010 WR 0011 SPEC CYC 0001 19 Theory of Operation The Input Buffers RESRVD 0100 RESRVD 0101 MEM RD 0110 RESRVD RESRVD XACTIONS MEM XACTIONS 011X CONFIG_XACTIONS 101X The PCI Active Analysis Probe is a universal PCI short card that attaches to Agilent logic analyzers The Analysis Probe has five major parts 1 The input buffers The latching buffers 2 3 The interface to the logic analyzer 4 The clocking and cycle bit generation logic 5 The extender card connector The input buffers present a single electrical load on the PCI bus and are made up of IDT162260 tri port buffers The PCI clock is buffered by a Motorola 807 high speed clock buffer When the Analysis Probe is in Timing mode output Port 2 of the tri port buffers goes directly to the logic analyzer input terminators When in State mode output Port 2 is tri stated Output port 1 is always enabled and goes to the latching buffers The Latching Buffers The interface to the Logic Analyzer The Clocking and Cycle bit Generation Logic The latching buffers are used only for state mode The entire PCI bus except the clock is latched in these buffers on t
32. uffers From the buffer input the etch goes directly to the extender card connector The buffer input provides a clamping diode The etch is extended approximately 5 inches from the gold fingers and is on the inner most layer of the board There are no via s on this inner layer in order to give this etch a direct route One issue that has been encountered with using the extender card connector is that the buffers need power in order to provide a high impedance to the signal This means that the logic analyzer must be attached to the Analysis Probe and powered up The PCI Active Analysis Probe module itself is a universal card It can operate in either a 5V or 3V PCI system 15 The logic analyzer can be configured for PCI analysis by loading Setting up the the PCI configuration file Loading this file will load the PCI Analyzer from the Local bus inverse assembler and configure your logic analyzer diskette To load the configuration and inverse assembler 1 Install the PCI Active Analysis Probe software flexible diskette in the disk drive of the logic analyzer 2 Configure the menu to Load the analyzer with the appropriate configuration file see table below 3 Execute the load operation to load the file into the logic analyzer that the PCI Active Analysis Probe module is connected to DO NOT SELECT ALL OR SYSTEM 166x P32M 66 32 bit Multiplexed Analysis Probe PODS 1 4 0 connect to Logic Analyzer PODS 1 4 166x P32D 66
Download Pdf Manuals
Related Search