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MC81F8816/8616

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1. Address Register Name Symbol R W 76543210 00B8H Asynchronous Serial Mode Register ASIMR R W 10000 00 byte bit 00B9H Asynchronous Serial Status Register ASISR R 1 0 0 0 byte OOBAH Baud Rate Generator Control Register BRGCR R W 00110000 byte bit Receive Buffer Register RXBR R 00000000 Transmit Shift Register TXSR W 1111111111 byte 00C0H RO port data register RO R W 100000000 byte bit 00C1H RO Direction Register ROIO 00000000 byte 00C2H R1 port data register R1 R W 100000000 byte bit 00C3H R1 Direction Register R110 W 00000000 byte 00C4H R2 port data register R2 R W 100000000 byte bit 00C5H R2 Direction Register R210 00000000 byte 00C8H R4 port data register R4 R W 100000000 byte bit 00C9H R4 Direction Register R4IO W 00000000 byte R5 port data register R5 R W 00000000 byte bit 00CBH R5 Direction Register R5IO W 00000000 byte 00CCH R6 port data register R6 R W 00000000 byte bit 00CDH R6 Direction Register R6IO W 00000000 byte 00 Buzzer Driver Register BUZR W 1111111111 byte 00CFH Ram Page Selection Register RPR R W 1 0 0 1 byte bit 00DOH Timer 0 Mode Control Register TMO R W 000000 byte bit Timer 0 Register TO R 00000000 byte 00D1H Timer 0 Data Register TDRO W 11111111141 Timer 0 Capture Data Register CDRO R 00000000 byte 00D2 Timer 1 Mode Control Register TM1 R W 100000000 byte bit 00D3H Timer
2. NOTE means that the BRK software interrupt is using same address with TCALLO Figure 8 7 PCALL and TCALL Memory Area PCALL rel TCALL n 4F35 PCALL 35g 4A TCALL 4 s gt 4F 4A 01001010 35 o Reverse t 11111111 11080110 00125 FH DH N 5 lt orroo 9 OFFFFH OFFD6y 25 lt OFFD7H D1 OFFFFy 36 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR Example The usage software example of Vector address and the initialize part ORG OFFEOH Device MC81F8816 DW WT INT Watch Timer Watch Dog Timer DW BIT INT Basic Interval Timer DW ADC I2C INT AD converter I2C DW TMR3 INT Timer 3 DW TMR2 INT Timer 2 DW TMR1 INT Timer 1 DW TMRO INT Timer 0 DW SPI 2 SPI DW NOT USED Not used DW UARTO INT UART TXO RXO DW EX3 INT INT 3 DW EX2 INT INT 2 DW EX1 INT INT 1 DW EXO INT INT 0 DW NOT USED Not used DW RESET Reset pORCECkCKkCk ckck ok k k ok k k k k k k k KOK K K KOK KOK UK K KOR OR KOK KOR KOK OR KR K ke ke R K MAIN PROGRAM amp k k k k k k k k k k k k k k k k k k k k k k k k k k K K R K kO KOK e ke K KK K K ORG 0 RESFT DI Disable All Interrupts CLRG LDX 0 LDA 0 RAM CLR1 STA RAM Clear 0000 gt 009 CMPX 090H BNE RAM CLR1
3. In the left case Tr base current flows from port to GND To avoid power consumption there should be low output to the port Figure 23 7 Application Example of Unused Output Port December 3 2012 Ver 1 03 121 MC81F8816 8616 24 OSCILLATOR CIRCUIT The MC81F8816 8616 have three oscillation circuits inter nally and are input and output for main fre quency and SX y and SXour are input and output for sub ABOV SEMICONDUCTOR frequency respectively inverting amplifier which can be configured for being used as an on chip oscillator as shown in Figure 24 1 Example Crystal Oscillator Ceramic Resonator C1 C2 10 30pF Open Xout External Clock External Oscillator C1 C2 10 30pF The example load capacitor value C1 C2 C3 C4 is common value but may not be appropriate for some crystal or ceramic resonator SXour 32 768kHz Example C3 C4 10 30pF Crystal or Ceramic Oscillator No need exteranl component XouT R46 for oscillation XiN Xour pin can be used as normal I O pin R46 R45 XiN R45 Vss Internal 8MHz 4MHz Figure 24 1 Oscillation Circuit Oscillation circuit is designed to be used either with a ce ramic resonator or crystal oscillator Since each crystal and ceramic resonator have their own characteristics the user should consult the crystal manufac
4. Timer 3 Timer 2 4 5 Basic interval Timer 6 Watch Dog Timer wprrr m Watch Timer 4 Interrupt Enable Register Lower byte Internal bus line Interrupt Master Enable Flag Interrupt Vector Address Generator Figure 17 1 Block Diagram of Interrupt 82 December 3 2012 Ver 1 03 0 No Generation 1 Generation ABOV SEMICONDUCTOR MC81F8816 8616 IENH Interrupt Enable High Register R W R W RW R W R W R W Bit 7 6 5 4 3 2 1 0 INTE INT2E RXOE TXOE ADDRESS 0F6H RESET VALUE 00000 IENM Interrupt Enable Middle Register R W R W Bit 7 6 5 R W R W R W 4 3 2 1 ADDRESS 7 RESET VALUE 0000 0g IENL Interrupt Enable Low Register R W R W R W Bit 7 6 5 4 3 2 1 0 I I I I ADDRESS 0F8H SPIE i BITE WDTE WTE INT3E 12 RESET VALUE 000000 Enables or disables the interrupt individually 0 Disable 1 Enable IRQH Interrupt Request Flag High Register R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 INTOIF INT1IF INT2IF RXOIF ADDRESS 0F9H i RESET VALUE 00000 IRQM Interrupt Request Flag Middle Register R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 TOF T2IF ADDRESS 0FAH RESET VALUE 0000 IRQ
5. ABOV MC81F8816 8616 SEMICONDUCTOR Bit 7 6 5 4 3 2 1 0 ADDRESS TMO i CAPO i TOCK2 TOCK1 TOCKO i TOCN RESET VALUE 000000 1 X X x x x ADDRESS 0D2u TM1 POL 16BIT PWMOE CAP1 T1CK1 T1CKO T1CN RESET VALUE 0 0000 x 0 0 1 x x x x TOCK 2 0 TOST 0 Stop Edge Detector 1 Clear and Start n CLEAR TIMER 0 TOIF TOCH 155 INTERRUPT COMPARATOR CAPTURE CDRO 8 bit TDRO 8 bit SCMR 1 0 A INT 0 Into INTERRUPT D TIST 0 Stop IEDS 1 0 1 Clear and Start CLEAR TIMER 1 T1IF INTERRUPT T1CN TACK 1 0 M COMPARATOR CAPTURE CDR1 8 bit TDR1 8 bit INA 1 gt INTERRUPT IEDS 3 2 Figure 12 10 8 bit Capture Mode 0 Timer1 64 December 3 2012 Ver 1 03 SEMICONDUCTOR NBOV MC81F8816 8616 Bit C 2 t ADDRESS 0D6H i CAP2 T2CK2 T2CK1 T2CKO T2CN RESET VALUE 000000g 1 X X X X X ADDRESS 0D8y TM3 POL 16BIT iPWM1Ei CAP3 T3CK1 T3CKO T3CN RESET VALUE 000 0000 x 0 0 1 x x x x T2CK 2 0 T2ST 0 Stop Edge Detector 1 Clear and Start EC1 CLEAR var TIMER 2 T2IF COMPARATOR CAPTURE CDR2 8 bit TDR2 8 bit SCMR 1 0 P INT 2 2 FINITE INTERRUPT T3ST 0 Stop IEDS 5 4 1 Clear and Start CLEAR TIMER 3 be T3IF INT
6. Font data DB 1110 00118 2 DB 1010 01118 3 DB 0011 0110B 4 DB 1011 0101B DB 1111 0101B 6 DB 0000 0111B Ner DB 1111 0111 8 DB 0011 0111B wg LCD Waveform The LCD duty 1 4 1 8 can be selected by LCR register ure 18 7 The example of 1 4 duty 1 3 bias are shown in shown Fig 1 4 Duty 1 3 Bias Drive COMO s COM1 556565 O O SEGO SEG1 2 COMO COM1 COM3 COM2 SEGO 2 2 SEG1 SEGO COMO SEG1 COMO Figure 18 7 Example of LCD drive output 96 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 18 5 Duty and Bias Selection of LCD Driver 4 kinds of driving methods can be selected by LCDD 1 0 bits 3 nally Figure 18 8 shows typical driving waveforms for LCD and 2 of LCD control register and connection of BIAS pin exter one frame lt one frame VCL2 VCL1 VCLO GND VCLO VCL1 VCL2 Data 1 a Data 0 gt F Data 1 s Data 0 gt a 1 4 Duty 1 3 Bias b 1 8 Duty 1 4 Bias Figure 18 8 LCD Drive Waveform Voltage COM SEG Pins December 3 2012 Ver 1 03 97 MC81F8816 8616 19 SERIAL PERIPHERAL INTERFACE SPI The serial Input Output is used to transmit receive 8 bit data serially The Serial Input Output SPI module is a se rial interface u
7. L INT2 INT1 INTO Edge Selection Register 00 Reserved 01 Falling 1 to 0 transition 10 Rising 0 to 1 transition 11 Both Rising amp Falling MC81F8816 8616 Figure 17 6 External Interrupt Block Diagram Example To use as an INTO Set port as an input port RO LDM ROIO 1101 1111B Set port as an interrupt port LDM PSRO 40100 0000B Set Falling edge Detection LDM IEDS 0000 0001 Response Time The INTO INT1 INT2 and INT3 edge are latched into INTOF INTIF INT2F and INT3F at every machine cycle The values are not actually polled by the circuitry until the next machine cycle If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The DIV itself takes twelve cycles Thus a maximum of twelve complete machine cycles elapse be tween activation of an external interrupt request and the beginning of execution ofthe first instruction ofthe service routine Interrupt response timings are shown in Figure 17 7 lt max 12 fosc gt lt 8 fosc Interrupt Interrupt Interrupt goes latched processing active Interrupt routine Figure 17 7 Interrupt Response Timing Diagram December 3 2012 Ver 1 03 87 SEMICONDUCTOR MC81F8816 8616 NBOV 18 LCD DRIVER The MC81F8816 8616 has the circuit that directly drives the liquid crys
8. SEG28 SEG35 1 3 76 80 p tB 7 SEG36 COMT7 LCD segment out LCD common Output 72 75 62 59 O State of SEG39 COM4 put output port before COM3 COMO 34 37 dep 2019 out SIEGE Analog Power Volt AVref 56 45 age Input to A D Converter PLLC 60 47 PLL input R40 57 y o R41 INT3 58 General port Interrupt3 Input Input port R42 49 46 14 Table 5 1 Port Function Description December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 Pin No Primary Function Secondary PIN NAME Function State State Reset STOP MC81F8816Q MC81F8616Q I O Description y o Description Timer1 PWM 32 27 Output TimerO Output RO1 ECO 33 4 O p n Counter Input R02 34 35 R04 BUZO 36 28 Buzzer Output Timer2 Event RO5 EC1 INTO 37 29 Counter Input InterruptO Input RO6 INT 1 38 30 1 0 Interrupt1 Input RO7 INT2 39 31 Interrupt2 Input Timer3 PWM ie 40 32 Output Timer2 Output Asynchronous Serial Interface Clock Input State of R11 ACK SCK 41 33 ate o General I O port SIO Serial Input port before Clock STOP Input Output UART Serial Data Output R12 TX SOUT 42 34 ISIO Serial Data Output UART Serial Data Input R1
9. 0E OF ins _ seti PBS a apc apc ast ast TAL SETA pop pusH BRK 1 Abit bit dp bit el rel imm dp dp X labs A dp 0 bit dp A A Socio ssc ssc ssc ssec rot ror CAL POP PUSH BRA imm dp dp X labs A dp 2 bit dp X x rel din me cmp LSR TCAL Nori TST POP PUSH irn fimm dp dp X labs A dp 4 M bit dp Y Y Upage TCAL OR OR OR OR ROR ROR OR POP PUSH fimm dp dp X labs A dp 6 OR1B dp PSW PSW yas osos AND AND AND AND INC CAL SD CMPY INC fimm dp dp X labs A dp 8 B dp dp X X or lesere EOR EOR EOR EOR DEC pec CAL EORI DBNE r px DEC imm dp dp X labs A dp 10 B dp dp X X LDA LDA LDA LDA TAL pc ipx LDX DAS 110 SETG imm dp labs PA 12 LDCB dp dpty XON LDM TCAL STA sta STA STY STC STX STX ux El i dp tabs TAX Mbit dp XAX STOP LOW 10000 10001 10010 10011 10100 10101 10110 10111 14000 11001 11010 11011 11100 11101 11110 11111 HIGH 10 11 12 13 14 15 16 17 18 19 1A 4B 1 1D 1E 1F BPL CLR BBC DBC ADC qus apc apc ast ast jmp pris LDX JMP
10. 5 30 BOD BOD Flag 0110 VCL3 VDD 2 VDD 6 30 0 BOD No Detect 0111 VCL3 VDD 2 VDD 7 30 1 BOD Detect 1000 VCL3 VDD 2 VDD 8 30 1001 VCL3 VDD 2 VDD 9 30 BOD Brown out detector 1010 VCL3 VDD 2 VDD 10 30 1011 VCL3 VDD 2 VDD 11 30 1100 VCL3 VDD 2 VDD 12 30 1101 VCL3 VDD 2 VDD 13 30 1110 VCL3 VDD 2 VDD 14 30 1111 VCL3 VDD Block Diagram of LCD BIAS Vpp LCDEN gt o _ CTR_DSO CTR_DS1 K Contrast CTR_DS2 4 controller CTR DS3 S Voltage Selector gt VCL3 LCDDO 75K gt VCL2 75K VCL1 75K gt velo 75 77 Vss Figure 18 3 LCD Bias Control December 3 2012 Ver 1 03 93 MC81F8816 8616 18 3 LCD Display Memory Display data are stored to the display data area page 4 in the data memory The display datas which stored to the display data area ad dress 04604 0487 are read automatically and sent to the LCD driver by the hardware The LCD driver generates the segment signals and common signals in accordance with the display data and drive method Therefore display pat terns can be changed by only overwriting the contents of the display data area with a program The table look up in struction is mainly used for this overwriting Figure 18 4 shows the correspondence between the display data
11. Tel E mail POR R47 Use Yes Name amp Signature 3 Marking Specification ONP Use Yes X2EN Yes 16 or 60 If ONP is D MC81C86XXLE Yes INAM YYWW KOREA bise Free PKG Free PKG gt Crystal E Work Week ROM Code Number IFONPis Crystal Customer s logo No Use Mask Data File Name Check Sum YYWW KOREA Customer logo is not required If the customer logo must be used in the special mark please submit a clean original of the logo Customer s part number OTP file data Please check mark into 4 Delivery Schedule Quantity ABOV Confirmation Customer Sample pcs Risk Order pcs 5 ROM Code Verification Verification Date Tel Name amp Check Sum Signature ABOV semiconductor MC81F8816 8616 ABOV xvi December 3 2012 Ver 1 03
12. 0000 0001B Pagel RAM Clear 0100y gt 00 LDX 40FFH Stack Pointer Initialize TXSP RPR 0000 0000B Page0 selection CALL LCD CLR Clear LCD display memory RO 0 Normal Port O0 1000 0010B Normal Port Direction ROPU 1000 0010B Pull Up Selection Set ROOD 0000 0001B RO port Open Drain control UUUU Et tt kE LDM SCMR 1111_0000B System clock control December 3 2012 Ver 1 03 MC81F8816 8616 37 MC81F8816 8616 8 3 Data Memory Figure 8 8 shows the internal Data Memory space availa ble Data Memory is divided into four groups a user RAM control registers Stack and LCD memory 00004 USER MEMORY 144 Bytes gt 0090 PERIPHERAL CONTROL OOFFy REGISTERS 112Bytes 01004 USER MEMORY Including Stack Area EFi 256 Bytes 0200H USER MEMORY ES gt PAGE2 026 112Bytes Unimplemented 04604 LCD DISPLAY MEMORY 40 Bytes PAGE4 04874 Figure 8 8 Data Memory Map User Memory The MC81F8816 8616 have 256 x 8 bits for the user data memory RAM There are three pages internal RAM Page is selected by G flag and RAM page selection regis ter RPR When G flag is cleared to 0 always page 0 is selected regardless of RPR value If G flag is set to 1 page will be selected according to RPR value RPR 0 G 0 RPR 1 G 1 RPR 2 G 1 RPR 4 G 1 Page 0 0004 09F Page 1
13. 81 8816 xiii C MASK ORDER SHEET MC81C8616 xiv December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 MC81F8816 8616 CMOS SINGLE CHIP 8 BIT MICROCONTROLLER WITH LCD CONTROLLER DRIVER 1 OVERVIEW 1 1 Description The MC81F8816 8616 are an advanced CMOS 8 bit microcontroller with 16K bytes of FLASH ROM MTP This device is one of the MC800 family and a powerful microcontroller which provides a high flexibility and cost effective solution to many LCD applications The MC81F8816 8616 provide the following standard features 16K bytes of FLASH ROM 512 bytes of RAM 40 bytes of segment LCD display RAM 8 16 bit timer counter 10 bit A D converter 7 bit watch dog timer 21 bit watch timer with 7 bit auto reload counter I2C SPI 8 bit UART PLL on chip oscillator and clock circuitry In addition this device supports power saving modes to reduce power consumption So the MC81F8816 8616 is the best controller so lution in system which uses charatered LCD display and ADC Memory UARTI FLASHMCU MASK MCU Bytes SPI WO LCD Package ROM RAM 12C Tel 36SEG x 8COM MC81F8816 MC81C8816 16K 512 8ch 2ch b 56 40SEG x acom 80 bak 28SEG x 8COM 64MQFP MC81F8616 MC81C8616 16K 512 5ch 2ch 48 325EG x 4COM 64LQFP 1 2 Features 16K Bytes On chip FLASH ROM ISP FLASH Memory Endurance 1000 cycles Da
14. Figure 13 1 Watch Timer Mode Register 72 December 3 2012 Ver 1 03 SEMICONDUCTOR ABOV MC81F8816 8616 WTCK 2 0 WTR6 WTR4 WTR3 WTR2 WTR wrRo WTRH fsus fmain 28 14 BIT Timer Counter 2Hz x 7bit WT value 1 fmain 27 Binary Counter 7bit auto reload counter fMAIN WTIN 1 0 2 16 Hz gt 4 Hz MUX gt 2 WTIF when fwek 32 768 kHz or fMAIN 27 fuAIN 4 19MHz WTEN LOADEN i WTIN1 WTINO WTCK2 1 WTCK1 WTCKO WIMR LOADEN Data Writing Control bit for WDTR and WTR 0 Watchdog Timer Write Enable 1 Watch Timer Write Enable WTR Figure 13 2 Watch Timer Block Diagram Usage of Watch Timer in STOP Mode 4 Enters into STOP mode again When the system is off and the watch should be kept work 5 Repeats 3 and 4 usa When using STOP mode if the watch timer interrupt inter 1 Set the clock source of watch timer to sub clock val is selected to 2Hz the power consumption can be re 2 Enters into STOP mode 3 After released by watch timer interrupt counts up timer and refreshes LCD Display When performing count up and refresh the LCD the CPU operates in main frequen cy mode December 3 2012 Ver 1 03 73 MC81F8816 8616 14 WATCH DOG TIMER The watch dog timer WDT function is used for checking program malfunction due to external noise or other causes and return the operation to the normal contion
15. The watchdog timer consists of 7 bit binary counter and the watchdog timer register WDTR The source clock of WDT is overflow of Basic Interval Timer When the value of 7 bit binary counter is equal to the lower 7 bits of WDTR the interrupt request flag is generated This can be used as WDT interrupt or CPU reset signal in accordance with the bit WDTON When WDTCL is set 7 bit counter of WDT is reset After one cycle it is cleared by hardware When writing WDTR the LOADEN bit of WTMR regis ABOV SEMICONDUCTOR ter should be cleared to 0 Note WDTR and WTR has same address OE8h The LOADEN bit is used to select WDTR or WTR When LOAD EN of watch timer mode register WTMR is set to 1 WDTR can not be wrote and WTR is wrote The LOADEN bit should be cleared to 0 when writing any value to WDTR Note When using watch dog timer don t write WDT 6 0 to 0000000 BIT Overflow WDT6 i WDT5 WDT4 WDT3 WDT2 i WDT1 Clear To Reset Circuit gt WDTR Watch Dog Timer Register w w w w Bit 7 6 5 4 3 WDTCLi WDT6 WDTCL WDT Clear 0 Free Run 1 WDT Clear Auto clear after 1cycle WDT 6 0 WDT Interrupt Value WTMR Watch Timer Mode Register R W R W R W R W Bit 7 6 5 4 3 WTEN LOADEN 0 Watch Dog Timer Write Enable 1 Watch Timer Write Enable Comparator L WDTON LOADEN
16. C v M bit C 17 SET1 dp bit x1 2 4 Set bit M bit e 1 111 1 11111111 18 SETA A bit 0B 2 2 Set A bit lt o 19 SETC AO 1 2 SetC flag C 1 1 20 SETG CO 1 2 Set G flag G 1 1 21 STC M bit EB 3 6 Store C flag M bit lt C Test and clear bits with A 22 TCLR1 abs 5C 3 6 7 A M lt M a A 23 TSET1 labs 3C 3 6 Test and set bits with A Miser uz A M M lt M v A ABOV pc_ lt Table vector L lt Table vector H SEMICONDUCTOR MC81F8816 8616 Branch Jump Operation Op Byte Cycle Flag No Mnemonic Code No No Operation 1 A bit rel 2 2 4 6 Branchifbitclear _ 2 BBC dp bit rel y3 3 5 7 if bit 20 then pc lt pc rel 3 BBS A bit rel x2 2 4 6 Branchifbitset _ 4 BBS dp bit rel x3 3 5 7 if bit 1 then rel Branch if carry bit clear Mas is 2 24 if C 0 then pec pe trel 777777 Branch if carry bit set E ibi 2 24 if C 1 then pec pe trel 277 Branch if equal i i 2 if Z 4 then pec pe trel 77 Branch if minus Ads 24 1 77 Branch if not equal e 9 2 24 if Z 0 thenpec pc trel 777777 Branch if minus eee 19 2 0 11 BRA re
17. CN CN S LS ES IS cO CO CO CO CO CO O t x X X x X X x X X X x X y X uocoq eoooron0doq coo e 000000000000000 cg 0 00 00 00 O0 00 00 00 00 00 00 OD December 3 2012 Ver 1 03 9 MC81F8816 8616 4 PACKAGE DIAGRAM SEMICONDUCTOR 80MQFP 24 15 lt 23 65 20 10 19 90 xr 28 28 oy 770 Y 3 18 max 64MQFP 24 15 23 65 17 65 14 10 13 90 18 15 20 10 19 90 7 3 18 max ST 1 lt 0 50 1 0 35 SEE DETAIL UNIT MM MAS MIN gt 0 10 zl k 1 03 qe oo 0 73 ole lt 1 95 REF DETAIL A UNIT MM SEE DETAIL A i ae ale 1 03 oo 0 73 lt 1 95 REF DETAIL A 10 December 3 2012 Ver 1 03 SEMICONDUCTOR NBOV MC81F8816 8616 64LQFP 12 25 lt 11 75 gt UNIT 10 10 09 90 d NN gt 0 7 Y Y SEE DETAIL A k 26 0 75 n cls 0 45 1 60 max lt 1 00 Ju REF 0 27 0 50 Typ 0 17 lt DETAIL December 3 2012 Ver 1 03 11 MC81F8816 8616 5 PIN FUNCTION Vpp Supply Voltage Vss Circuit ground RESET Reset the MCU Reset Input to the i
18. Currentdissipationin sroP fmain off Vpp 5 5V fsug 0 7 pA stop mode IsuB Vpp 5 5V fsup 32 768kHz 7 14 OMZ Gaci ana VDD 5V 25 8410 8 8410 MHz 22 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 Specifications Parameter Symbol Pin Condition Unit Min Typ Max Internal 4MHz Oscil 25 0 0 lation Frequency fIN4M VDD 5V 25 10 4 10 MHz is the voltage when VCL3 VCL2 VCL1 and VCLO are supplied at pads Vora is the voltage when Vss is supplied at pad These parameters are presented for design guidance only and not tested or guaranteed Current dissipation is proportioned according to operation voltage and frequency In sleep mode oscillation continues and peripherals are operated normally but internal CPU clock stops In sub sleep mode sub oscillation continues and peripherals are operated normally but internal CPU clock stops Q V Vpp Tvpp 40ms V VppMIN pce a E Config POR Read Corffig POR Read Detection Point Defection Point 2 Vconrie H SSeS Sh SS P No Config POR Read V n VSTART OV Figure 7 1 Config Read Voltage including POR vs Supply Voltage 7 4 LCD Characteristics 40 85 C Vpp 2 2 5 5V Vss 0V Specifications Parameter Sy
19. Note Stresses above those listed under Absolute Maxi mum Ratings may cause permanent damage to the de vice This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability Specifications Parameter Symbol Condition Unit Min Typ Max 12 2 4 5 5 5 V Supply Voltage VDD fMAIN 4MHz 2 2 5 5 V Vpp 2 2 5 5V 1 4 0 fMAIN MHz Main Operating Frequency Vpp 4 5 5 5V 1 12 0 fsuB Vpp 3 0 5 5V 32 768 kHz Sub Operating Frequency fsuB Vpp Vpp 32 768 kHz Vpp72 2 5 5V 40 85 C Operating Temperature ToPR Vpp 4 5 5 5V 40 85 C December 3 2012 Ver 1 03 21 MC81F8816 8616 7 3 DC Electrical Characteristics 40 85 C Vpp 2 2 5 5V Vss 0V ABOV SEMICONDUCTOR Specifications lation Frequency Parameter Symbol Pin Condition Unit Min Typ Max RO R7 0 7Vpp Vpp 0 3 Input High Voltage RESET SI ACK Xin 5 V Vin2 INTO 3 ECO 1 0 8Vpp Vpp 0 3 RO R7 0 3 0 3Vpp Input Low Voltage RESET SI ACK Xin SXin V INTO 3 ECO 1 e 0 2Vpp VoH1 RO R4
20. R W ADDRESS 0904 RESET VALUE 0 001000 STT start condition generation 0 disable 1 enable SPT stop condition generation 0 disable 1 enable ADDRESS 0914 RESET VALUE 000000008 ADDRESS 092 RESET VALUE 111111118 ADDRESS 0934 RESET VALUE 111111118 ADDRESS 0944 RESET VALUE 000000008 Table 20 1 I2C Enable Registers December 3 2012 Ver 1 03 103 MC81F8816 8616 20 1 Bit Transfer Due to the variety of different technology devices CMOS NMOS bipolar which can be connected to I2C bus the lev els of the logical 0 LOW and 1 HIGH are not fixed and depend on the associated level of VDD see Section 15 for electrical specifications One clock pulse is generated for each data bit transferred The data on the SDA line must be SEMICONDUCTOR stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW see Figure 20 2 data valid SDA eo A SCL f ME data line stable change of except Sr P data allowed Figure 20 2 Bit transfer on I2C bus 20 2 Start Stop Conditions Within the procedure of the I2C bus unique situations ariswhich are defined as START S and STOP P conditions see Figure 20 3 A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case This situation indicates a START condition A
21. 9 1 lt dp 1 1 Increment memory pair 4 INCW d 9D 2 6 N 2 dp 1 dp lt dp 1 dp 1 Load YA 5 LDYA dp 7D 2 5 VAE dp 1 dp Neves Zz Store YA 6 STYA dp DD 2 5 16 Bits subtract without carry 7 SUBW dp 3D 2 5 YA lt YA 1 dp NV H ZC Bit Manipulation Op Byte Cycle Flag No Mnemonic Code No No Operation NUES ES 1 AND1 M bit 8B 3 4 Bit AND C flag C lt C A M bit J 2 AND1B M bit 8B 3 4 Bit AND C flag and NOT C lt C aA M bit 3 0C 2 4 Bit test A with memory MM Z 4 BIT labs 1C 3 5 Z lt Ne My lt 6 5 CLR1 dp bit y1 2 4 Clear bit M bit OP o 6 CLRA1 2B 2 2 Clear Abit Abit c 0 7 CLRC 20 1 2 Clear C flag Ce 0 0 8 CLRG 40 1 2 Clear G flag lt 0 0 9 CLRV 80 1 2 Clear V flag V lt 0 0 0 10 EOR1 M bit AB 3 5 Bit exclusive OR C flag C C M bit 41 EORIB Mbit AB 3 5 QR C flagandNOT C lt C M 12 LDC M bit CB 3 4 LoadC flag C lt Mbit 2 o 13 LDCB M bit CB 3 4 Load C flag with NOT C M bit 14 NOT1 M bit 4B 3 5 Bit complement M bit lt M bit 9 15 OR1 M bit 6B 3 5 Bit OR C flag C lt C v M bit December 3 2012 Ver 1 03 16 OR1B M bit 6B 3 5 Bit OR C flag and NOT C
22. Basic Interval Timer Register BITR R Undefined byte Clock Control Register CKCTLR 0111011111 byte 00E7H System Clock Mode Register SCMR R W 1 0 0 0 byte Watch Dog Timer Register WDTR W 01111111 byte Watch Dog Timer Data Register WDTDR R Undefined byte Watch Timer Register WTR W 01111111 Stop amp Sleep Mode Control Register SSCR W 00000000 byte Watch Timer Mode Register WTMR R W 100 0000 byte bit 00F4H Interrupt Generation Flag Register High INTFH R W 0100 byte bit 00F5H Interrupt Generation Flag Register Low INTFL R W 00 1 0000 byte bit OOF6H Interrupt Enable Register High IENH R W 00000 byte bit 00F7H Interrupt Enable Register Middle IENM R W 0 000 0 byte bit O0F8H Interrupt Enable Register Low IENL R W 000000 byte bit 00F9H Interrupt Request Register High IRQH R W 00000 byte bit OOFAH Interrupt Request Register Middle IRQM R W 10000 0 byte bit OOFBH Interrupt Request Register Low IRQL R W 000000 byte bit OOFCH Interrupt Edge Selection Register IEDS R W 100000000 byte bit Table 8 1 Control Registers 1 byte bit means that register can be addressed by not only bit but byte manipulation instruction 2 byte means that register can be addressed by only byte manipulation instruction On the other hand do not use any read modify write instruction such as bit manipulation 3 bit 0 of ADCM is read only December
23. Noise Canceller Vpp Vpp Vss Input Enable Priority ACK gt SCK in gt SCK out TX1 gt SOUT out gt SOUT in Pull up Tr Pin R20 AN0 R27 AN7 Open Drain Register Vpp Data Register Direction Register Vss ADC Input Data ADC Enable amp Channel Selectable Pull up Tr Vpp Pin Vss December 3 2012 Ver 1 03 17 MC81F8816 8616 ABO R02 R03 R14 R15 R40 R42 lt Pull up Register Open Drain Register Data Register Vpp Data Bus Vss Vss Direction Register 50 5 0 77 5 23 VCL2 or VCL1 LCD Data Registger Frame Counter LCD Control VO Data Bus Data Register Port Selection Register RD V Vss Vss Direction Register 18 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR COM0 COM3 MC81F8816 8616 Xour Crystal or Ceramic resonator VCL2 or VCL1 T VCL2 Frame Counter e j 4 ZN LCD Control Z Pn V VCLO or Vss Vss COM0 COM3 SEG24 SEG35 COM4 SEG39 COM7 SEG36 VCL2 or VCL1 T VCL2 LCD Data we OD A Frame Counter LCD Control EFE gt a Fin V V VCLO or Vs
24. 0 Seg Selection seg7 seg0 1 Port Selection Note R5 O is write only register It can not be read and can not be accessed by bit manipulation instruction Do not use read or read modify write instruction Use byte manip ulation instruction R6 Ports R6 is an 8 bit CMOS bidirectional I O port address 0 Each I O pin can independently used as an input or 49 MC81F8816 8616 an output through the R6IO register address R6 is multiplexed with LCD segment output SEG8 SEGI5 which can be selected by writing appropriate val ue into the R6PSR address ADDRESS R6 Data Register RESET VALUE 000000008 R6 R67 i R66 i R65 R64 R63 R62 R61 i R60 ADDRESS RESET VALUE 000000008 Port Direction 0 Input 1 Output R6 Direction Register R6 LCD Port Selection Register ADDRESS RESET VALUE 111111118 R6PSR R6PS7 R6PS6 R6PS5 REPS4 IRGPS3 IRGPS2 R6PS1 RePSO 0 Seg Selection seg15 seg8 1 Port Selection Note R6 O is write only register It can not be read and can not be accessed by bit manipulation instruction Do not use read or read modify write instruction Use byte manip ulation instruction R7 Ports R7 is a 8 bit CMOS bidirectional I O port address Each I O pin can independently used as an input or an out put through the R7IO register address 0B4y R7 is multiplexed with LCD segment
25. 1 corresponding your operation TOCK 2 0 TOST 0 Stop Edge Detector 1 Clear and Start ECO Ll Y T1 8 bit TO 8 bit TOIF TIMER 0 INTERRUPT COMPARATOR R00 PWMO TOO 2 SCMR 1 0 8 bit TDRO 8 bit PWMOO BE PSRO 0 Figure 12 8 16 bit Timer Counter Mode 0 Bit 6 5 2 1 0 ADDRESS 0D6 TM2 i CAP2 T2CK2 T2CK1 2 T2CN T2ST RESET VALUE 000000 0 X X x x x ADDRESS 0D8H TM3 POL i 16BIT CAP3 T3CK1 T3CKO T3CN T3ST RESET VALUE 000000005 X The value 0 or 1 corresponding your operation T2CK 2 0 T2ST 0 Stop Edge Detector 1 Clear and Start EC1 Y T3 8 bit T2 8 bit CURAR Xin TIMER 2 er INTERRUPT R10 PWM1 T2O COMPARATOR TDR3 8 bit TDR2 8 bit SCMR 1 0 PWM10 PME PSR1 0 Figure 12 9 16 bit Timer Counter Mode 2 62 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 12 3 8 Bit Capture Mode The Timer 0 capture mode is set by bit CAPO of timer mode register TMO bit CAPx of timer mode register TMx for Timer 1 2 3 as shown in Figure 12 10 As mentioned above not only Timer 0 but Timer 1 2 3 can also be used as a capture mode The Timer Counter register is increased in response inter nal or external input This counting function is same with normal timer mode and Timer interrupt is generated when timer register TO T1 2 3 increas
26. 82 SBC X 26 2 4 83 SBC abs 27 3 4 NV HZC 84 SBC abs Y 35 3 5 85 SBC dp X 36 2 6 86 SBC Y 37 2 6 87 SBC X 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero 00u N Z 89 XCN CE 4 5 within the accumulator gs December 3 2012 Ver 1 03 vii MC81F8816 8616 Register Memory Operation ABOV SEMICONDUCTOR No Mnemonic E 2 E Operation 1 LDA imm C4 2 2 Load accumulator 2 LDA dp C5 2 3 A M 3 LDA dp X C6 2 4 4 LDA abs C7 3 4 5 LDA abs Y D5 3 5 N 2 6 LDA 06 2 6 7 LDA dp Y D7 2 6 8 LDA X D4 1 3 9 LDA X DB 1 4 X register auto increment lt M X lt X 1 10 LDM dp imm E4 3 5 Load memory with immediate data 11 LDX fimm 1E 2 2 Load X register 12 LDX dp cc 2 3 X M N 2 13 LDX dp Y CD 2 4 14 LDX abs DC 3 4 15 LDY imm 3E 2 2 Load Y register 16 LDY dp C9 2 3 Y M N 2 17 LDY dp X D9 2 4 18 LDY abs D8 3 4 19 STA dp E5 2 4 Store accumulator contents in memory 20 STA dp X E6 2 5 M lt A 21 STA abs E7 3 5 22 STA abs Y F5 3 23 STA X F6 2 7 24 STA dp Y F7 2 7 25 STA X F4 1 4 26 STA X FB 1 4 X register auto increment M lt A Xe X 1 27 STX dp EC 2 4 Store X register contents in memory 28 STX dp Y ED 2 5 M eX s 29 STX abs FC 3 5
27. After reset this value is 0 port may be used as normal I O port To use alternate function such as External Interrupt rather than normal I O write 1 in the corresponding bit of PSRI Note R110 R1PU 1 and PSR 1 are write only regis ters They can not be read and can not be accessed by bit manipulation instruction Do not use read or read modify write instruction Use byte manipulation instruction 47 MC81F8816 8616 ADDRESS 0C2y R1 Data Register RESET VALUE 000000008 R1 R17 i R16 R15 R14 R12 i R11 i R10 ADDRESS RESET VALUE 000000008 R1 Direction Register R1IO Port Direction 0 Input 1 Output R1 Pull up ADDRESS Selection Register RESET VALUE 00000000 Pull up select 0 Without pull up 1 With pull up R1 Open Drain Sel Reaist ADDRESS 0A14 election Register RESET VALUE 000000008 R100 Open Drain select 0 No Open Drain 1 Open Drain Port ADDRESS 0AB Selection Register 1 S RESET VALUE 000g PSR1 i i INT3 INT2IPWM INT3 External Interrupt 3 0 R41 Port 1 INT3 input Port INT2 External Interrupt 2 0 RO7 Port 1 INT2 input Port PWM10 PWM1 Output 0 R10 Port 1 PWM10 T20 R2 Ports R2 is a 8 5 bit CMOS bidirectional I O port address 0 Each I O pin can independently used as an input or an output through the R2IO register address 0 5 R2 has intern
28. Direction m 212 v V Data Bus lt MUX q i Pull Up Enable D 4 VoD R45 Xin R46 Xour ABOV SEMICONDUCTOR Pull up Reg Open Drain Reg Data Reg 4 Tr Vpp Direction Reg e c Data Bus lt lt MUX 4 Xinout Disable RD 5l XIN RE Z 7 R45 vA Vss SS D gt Configuration V option bit Main Clock lt q 4 4 to ONP Block V DD Pull up Pull up Tr Reo E e Open Drain y Reg DD Data Reg 4 Direction Xout Reg alo R46 v V Vis ss Data Bus lt MUX q 20 RD December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 7 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Ratings Supply voltage Supply Voltage AVref Storage Temperature Voltage on any pin with respect to Ground Vss 0 3 to 0 3 20 mA Maximum current sunk by Ior per I O Pin 0 3 to 6 0 V Vpp 0 3 to Vpp 0 3 V 45 to 125 C Maximum output current sourced by Ion per I O Pin 7 2 Recommended Operating Conditions MC81F8816 8616 Maximum current 80 mA Total Power Dissipation PT 600 mW
29. H i i H 0 OE6 WDTCL WDT6 WDT5 WDT4 WDT3 WDT2 WDT1 H CKCTLR 0 Write Watch Dog Timer Register WDT5i WDT4 WDT3 i WDT2 WDT Interrupt Interval IFWDT BIT Interrupt Interval x WDT value WTIN1 2 WTINO iWTCK2 iWTCK1 i WTCKO LOADEN 7bit reload Counter Write Enable Bit w 2 1 0 ADDRESS 0 8 WDT1 WDTO INITIAL VALUE 0111 11118 R W R W R W 2 1 0 ADDRESS 0EAH INITIAL VALUE 00 0_0000g Figure 14 1 Block Diagram of Watch Dog Timer 74 December 3 2012 Ver 1 03 ABOV MC81F8816 8616 Sour Clock BIT Overflow Binary 0 Counter N Counter WDTR 7 0 WDTIF Interrupt WDT RESETB Figure 14 2 Watch Dog Timer Interrupt Time December 3 2012 Ver 1 03 75 MC81F8816 8616 15 ANALOG TO DIGITAL CONVERTER The analog to digital A D converter allows conversion of an analog input signal to an corresponding 10 bit digital value The A D module has six analog inputs which are multiplexed into one sample and hold The output of the sample and hold is the input of the converter which gener ates the result via successive approximation The analog supply voltage is connected to AVref of ladder resistance of A D module The A D module has three registers which are the control register ADCM and A D result register ADCRH and AD C
30. LDA LDX LDY OR SBC STA STX STY Example 073520 ADC 0F035g ROM 0F035g res PENNE OF035u data E 1 1 A data C gt A 100 07 101 35 _ address 0F035 0 102 FO c J T J December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR The operation within data memory RAM ASL BIT DEC INC LSR ROL ROR Example Addressing accesses the address 01354 regard less of G flag and RPR 981501 INC 10115 ROM 115g lt 115 data e data 1 data 0 100 98 1 OF101H 15 address 0115 OF 102H 01 5 Indexed Addressing X indexed direct page no offset X In this mode a address is specified by the X register ADC AND CMP EOR LDA OR SBC STA XMA Example 15 G 1 RPR 01y D4 LDA X ACC lt RAM X yersus ae 115u data ve 4 2 data gt A 0E550H D4 Te a December 3 2012 Ver 1 03 MC81F8816 8616 X indexed direct page auto increment X In this mode a address is specified within direct page by the X register and the content of X is increased by 1 LDA STA Example G 0 35 DB LDA X 35H data data gt A 35x DB k E SERRE X indexed direct page 8 bit offset gt dp X This address value is the second byte Operand of com mand plus the data of X register And it assigns the mem ory in Direct page
31. PWMOE CAP1 T1CK1 T1CKO I T1CN T1ST RESET VALUE 0 00000 X 1 0 1 1 1 X X X The value 0 or 1 corresponding your operation TOCK 2 0 TOST 0 Stop li 1 Clear and Start Edge Detector CLEAR TOIF TIMER 0 xn L INTERRUPT SCMR 1 0 INT 0 a INTERRUPT IEDS 1 0 Figure 12 14 16 bit Capture Mode 0 1 December 3 2012 Ver 1 03 67 MC81F8816 8616 SCMR 1 0 SEMICONDUCTOR Bit ADDRESS TM2 i RESET VALUE 000000g 1 x x x x ADDRESS 0D8y TM3 i 16BIT i PWM1E CAP3 T1CK1 T1CKO RESET VALUE 000 0000 x 1 0 x 1 x x X The value 0 or 1 corresponding your operation T2CK 2 0 T2ST 0 Stop Edge Detector 1 Clear and Start EC1 CLEAR TM2 2 2 T2IF TIMER 2 Xin INTERRUPT COMPARATOR wT2 A IEDS 5 4 INT 2 e ete INTERRUPT Figure 12 15 16 bit Capture Mode Timer2 3 12 5 8 Bit 16 Bit Compare Output Mode The MC81F8816 8616 have a function of Timer Compare Output To pulse out the timer match can goes to port pin R10 as shown in Figure 12 4 and Figure 12 8 Thus pulse out is generated by the timer match These operation is implemented to pin R10 PWM1 T20 In this mode the bit PVMIO of Port Mode Register RIFUNC should be set to 1 and the bit PWMIE of Timer3 Mode Register TM3 should be cleared to 0 12 6 PWM Mode
32. TOCK 2 0 Edge Detector TM 1 Clear and Start ud Y Y CLEAR gt TO 8 bit TIMER 0 TOIF X INTERRUPT us TOCN COMPARATOR TDRO 8 bit PWMOE PSR0 0 PWMO TOO or ROO 2 SCMR 1 0 TACK 1 0 TST i 1 Clear and Start gt por CLEAR PWM RO0 PWMO TOO D THIF gt TIMER 1 INTERRUPT TICN COMPARATOR TDR1 8 bit Figure 12 4 Block Diagram of Timer Event Counter0 1 December 3 2012 Ver 1 03 59 MC81F8816 8616 Bit 7 6 5 4 3 TM2 0 x x TM3 POL 16BIT PWM1E x 0 0 0 x T2CK 2 0 Edge Detector 1 L CAP3 i T3CK1 i T3CN ABOV SEMICONDUCTOR 2 1 0 CAP2 T2CK2 T2CK1 T2CKO T2CN ADDRESS T2ST RESET VALUE 000000 X x x ADDRESS 008 T3ST RESET VALUE 000 0000 X X X X The value 0 or 1 corresponding your operation T2ST 0 Stop 1 Clear and Start Y CLEAR T2 8 bit T2CN T3CK 1 0 SCMR 1 0 TIMER 2 gt gt INTERRUPT COMPARATOR TDR2 8 bit PWM1E PWM1 T20 or R10 T3ST 0 Stop 1 Clear and Start CLEAR R10 PWM1 T2O TIMER 3 INTERRUPT COMPARATOR TDR3 8 bit Figure 12 5 Block Diagram of Timer 2 3 These timers have each 8 bit count register and data regis ter The count register is increased by every internal or ex ternal clock input The internal clock has a prescaler divide rati
33. Timer 1 Capture Mode Selection CAP3 Timer 3 Capture Mode Selection 0 Timer Counter Mode 0 Timer Counter Mode 1 Capture Mode 1 Capture Mode The counter will be cleared and restarted only when the TxST bit cleared and set again If TxST bit set again when TxST bit is set the counter can t be cleared but only start again TOCK2 TOCK1 TOCKO 4MHz 8MHz 10MHz 0 0 0 fMAIN 2 500nS 250nS 200nS 0 0 1 22 1 5 500 5 400 5 0 4 O 23 245 1 5 80015 0 1 1 25 845 445 3 2uS 1 0 0 27 3205 16uS 12 8uS 1 0 1 29 1280 64uS 51 2uS 1 1 O 211 512uS 256uS 204 8uS Figure 12 1 Timer0 1 2 3 Registers 56 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 TO 0 Register 2 2 2 Bit 7 6 ADDRESS 001 INITIAL VALUE 00H CDRO 0 Input Capture Register R R R R R R R R Bit 7 6 5 4 3 2 1 0 ADDRESS 0D1H INITIAL VALUE 00H In Timer mode this register is the value of Timer 0 counter and in Capture mode this register is the value of input capture CDRO7 CDRO5 CDR04 CDR03 CDRO2i CDRO1 CDROO TDRO Timer 0 Data Register Ww w w w Bit 7 6 5 4 3 2 1 0 i TDRO6 TDROS TDRO4 TDRO3 TDRO2 TDRO1 TDROO ADDRESS 001 INITIAL VALUE FFy If the counter of Timer 0 and the data of TDRO is equal
34. corresponding your operation PWM1E 20 W COMPARATOR R10 PWM1 T2O 0 PWM10 PSR1 0 POL Figure 12 17 PWM1 Mode 70 December 3 2012 Ver 1 03 SEMICONDUCTOR NBOV MC81F8816 8616 fMAIN LILILILILPLILIL LIL LIL LIL LI LI LI LI n e s po Xo Xo de X JoJo s 8 PWM POL 1 PWM POL 0 Duty Cycle 80 1 20015 25 8 gt i Period Cycle 1 3FFH 200nS 204 8uS T3PWHR T r T3PPR FFH 0 0 80H Figure 12 18 Example of PWM at 5MHz T3CK 1 0 10 1 6uS T3PWHR 00H OEY Write T1PPR to 05 Source clock J Period changed Duty Cycle C bu Ge T soe 7 05 41 1 6uS 9 6uS 05 1 x 1 6uS 9 6uS 05 1 x 1 6uS 9 6uS lt gt lt gt Period Cycle 0 1 x 1 6uS 2405 Period Cycle 0 1 x 1 6uS 17 6uS Figure 12 19 Example of Changing the Period in Absolute Duty Cycle 5MHz Example Timerl 4Mhz 4kHz 20 duty PWM mode LDM R1IO 0000 XXX1B R00 output LDM 1TM3 0010 0000B pwm enable LDM T3PWHR 0000 1100B 20 duty T3PPR 1110 0111B period 25005 T3PDR 1100 01118 duty 50uS LDM PSR1 XXXX_XXX1B pwm port LDM 1TM3 0010 0011B timerl start X means don t care December 3 2012 Ver 1 03 71 MC81F8816 8616 13 WATCH TIMER The
35. 0 2 Continue Start 001 fMain 22 001 fMain 22 0 Pause Counting 010 fMAIN 23 010 fMAIN24 1 Continue Counting 011 fMAIN 25 011 26 100 fMAINT27 100 fMAIN7 28 TOST T2ST Timer 0 2 Start Control 101 fmain 29 101 fMAIN210 0 Stop Counting 110 fmain 211 110 fMmain 212 1 Clear the counter and Start counting again 111 External Event clock ECO 111 External Event clock EC1 main clock frequency TM Timer1 3 Mode Control Register R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 ADDRESS 0 2 TM1 i 16 PWMOE CAP1 TICK1 TICN INITIAL VALUE 00000000g R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 n ADDRESS 0D8y TM3 i 16BIT PWM1E T3CK1 T3CKO T3CN INITIAL VALUE 00000000g POL PWM Output Polarity Selection T1CK 1 0 T3CK 1 0 Timer 1 3 Input Clock Selection 0 Duty Active Low T1CK 1 0 T3CK 1 0 1 Duty Active High 00 fMAIN 00 16BIT 16 Bit Mode Selection 01 fain 2 01 fuAIN2 0 8 Bit Mode 10 2 10 fMAINT24 1 16 Bit Mode 11 TimerO Clock 11 Timer2 Clock PWMOE PWM Enable Bit T1CN T3CN Timer 1 3 Continue Start 0 PWMO Disable TOO Enable 0 Stop Counting 1 PWMO Enable TOO Disable 1 Start Counting PWMHE PWM Enable Bit T1ST T3ST Timer 1 3 Start Control 0 PWM1 Disable T2O Enable 0 Stop counting 1 PWM1 Enable 20 Disable 1 Clear the counter and start count again CAP1
36. 1 0 Parity Bit Specification 00 No Parity 01 Zero Parity always added during transmission No Parity detection during reception Parity errors do not occur 10 Odd Parity 11 Even Parity operation has stopped ASISR Parity Error Flag 0 No parity error 1 Parity error Received data parity not matched INITIAL VALUE 0000 00 g Receive Completion Interrrupt Control When Error Occurs 0 Receive completion interrupt request is issued when an error occured 1 Receive completion interrupt request is not issued when an error occured Stop Bit Length for Specification for Transmit Data 0 1 bit 1 2 bit Caution Do not switch the operation mode until the current serial transmit receive ADDRESS INITIAL VALUE 000p Frame Error Flag 0 No Frame error Overrun Error Flag 1 Framing error Note1 stop bit not detected 0 No Overrun Error Note2 when an overrun error has occurred 1 Next receive operation was completed before data was read from receive buffer register RXBR Note 1 Even if a stop bit length is set to 2 bits by setting bit2 SLO in ASIMR stop bit detection during a recive operation only applies to a stop bit length of 1bit 2 Be sure to read the contents of the receive buffer register RXBR Until the contents of RXBR are read futher overrun errors will occur when receiving data Figure 21 1 Asynchronous Serial Interface Mode amp Status Regist
37. 1 Data Register TDR1 Ww 1111111111 byte Timer 1 Register T1 R 00000000 byte 00D4H Timer 1 PWM Duty Register T1PDR R W 111111111111111 byte Timer 1 Capture Data Register CDR1 R 00000000 00D5H Timer 1 PWM High Register T1PWHR R W 0000 byte 00D6H Timer 2 Mode Control Register TM2 R W 000000 byte bit Timer 2 Register T2 R 00000000 00D7H Timer 2 Data Register TDR2 W 1111111111111 1 byte Timer 2 Capture data Register CDR2 R 00000000 byte 00D8H Timer 3 Mode Control Register R W 100000000 byte bit Spode Timer 3 Data Register TDR3 W 111111111111111 byte Timer 3 PWM Period Register T3PPR W 111111111111111 byte Table 8 1 Control Registers 40 December 3 2012 Ver 1 03 SEMICONDUCTOR NBOV MC81F8816 8616 Address Register Name Symbol R W oe ere 76543210 Timer 3 Register T3 R 00000000 byte 00DAH Timer 3 PWM Duty Register T3PDR R W 00000000 byte bit Timer 3 Capture Data Register CDR3 R 00000000 byte 00DBH Timer 3 PWM High Register T3PWHR W 0000 byte 00 2 10bit A D Converter Mode Control Register ADCM R W 00000001 byte bit 00 10bit A D Converter Result Register Low ADCRL R Undefined byte 00 4 10bit A D Converter Result Register High ADCRH W R 010 byte bit 00 5 BOD Control Register BODR R W 00000000 byte bit
38. 16 Bit Compare Output Mode PWM Mode In the timer function the register is increased every in ternal clock input Thus one can think of it as counting in ternal clock input Since a least clock consists of 2 and Example 1 Timer 0 8 bit timer mode 8ms interval at 4MHz Timer 1 8 bit timer mode 4ms interval at 4MHz LDM SCMR 0 Main clock mode LDM TDRO 249 LDM TMO 0001 0011B LDM TDR1 124 LDM TM1 0000 1111 1 TOE SET TLE EI Example 2 Timer0 16 bit timer mode 0 55 at 4MHz LDM SCMR 0 LDM TDRO 23H LDM TDR1 0F4H LDM 0FH LDM TM1 4CH Main clock mode 32 8us SET1 TOE EI December 3 2012 Ver 1 03 MC81F8816 8616 most clock consists of 2048 oscillator periods the count rate is 1 2 to 1 2048 of the oscillator frequency in Timer0 And Timerl can use the same clock source too In addition Timer has more fast clock source 1 1 to 1 8 In the counter function the register is increased in re sponse to a 0 to 1 rising edge transition at its correspond ing external input pin ECO Timer 0 In addition the capture function the register is increased in response external or internal clock interrupt same with timer counter function When external interrupt edge in put the count register is captured into capture data register TMx Timer3 is shared with PWM function and Timer2 is shared wit
39. 2 0 VDD 1 2 3 4 5 6 V Normal mode IDD1 imA 28 December 3 2012 Ver 1 03 SEMICONDUCTOR Sleep mode IDDAuA 1600 MC81F8816 8616 Stop mode IDDXuA December 3 2012 Ver 1 03 VDDCV 29 ABOV MC81 F8816 8616 SEMICONDUCTOR IOH V OH 00 4 5 VOH v v v v v v v v v AS AS AS AS SS a5 a IOHCm A IOL VOL DD 45V VOLEY 6 5 2m A 10mA 20m A 30m A 35mA 40 1 00 1 1 port 2 3v 4 Sv Bv VDDCV 30 December 3 2012 Ver 1 03 ABOV MC81F8816 8616 SEMICONDUCTOR YDD VIL1 normal port VILIC 2v av sv 8v VDD V 3v AV SV sy VDDV T Pa dii mis 2 3v av sv Bv VDD CV December 3 2012 Ver 1 03 31 MC81F8816 8616 8 MEMORY ORGANIZATION The have separate address spaces for Program memory Data Memory and Display memory Program memory can only be read not written to It can be up to 16K bytes of 8 1 Registers This device has six registers that are the Program Counter PC a Accumulator A two index registers X Y the Stack Pointer SP and the Program Status Word PSW The Program Counter consists of 16 bit register ACCUMULATOR X REGISTER Y REGISTER SP STACK POINTER PCH PCL PROGRAM COUNTER PROGRAM STATUS PSW WORD Figure 8 1 Configuration of Reg
40. 3 2012 Ver 1 03 41 MC81F8816 8616 8 4 Addressing Mode The MC81F8816 8616 use six addressing modes Register addressing Immediate addressing Direct page addressing Absolute addressing Indexed addressing Register indirect addressing 1 Register Addressing Register addressing accesses the A X Y C and PSW 2 Immediate Addressing gt imm In this mode second byte operand is accessed as a data immediately Example 0435 ADC 354 MEMORY HM LL 04 35 35 gt A When G flag is 1 then RAM address is defined by 16 bit address which is composed of 8 bit RAM paging register RPR and 8 bit immediate data Example G 1 RPR 014 E45535 LDM 35g 55 quse m ET O 0135 data data lt 55 100 4 OF101H 55 0F102y 35 ge anil 42 SEMICONDUCTOR 3 Direct Page Addressing dp In this mode a address is specified within direct page Example G 0 535 LDA 35g RAM 35g pastum M DE 35H data e o data gt A 0E550H C5 0E551H 35 NE 4 Absolute Addressing abs Absolute addressing sets corresponding memory data to Data i e second byte Operand I of command becomes lower level address and third byte Operand IT becomes upper level address With 3 bytes command it is possible to access to whole memory area ADC AND CMP CMPX CMPY EOR
41. 30 STY dp E9 2 4 Store Y register contents in memory 31 STY dp X F9 2 5 eY 32 STY abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X register X lt A N Z 34 TAY 9F 1 2 Transfer accumulator contents to Y register Y A N 7 35 TSPX AE 1 2 Transfer stack pointer contents to X register X lt sp N 7 36 C8 1 2 Transfer X register contents to accumulator A X N Z 37 TXSP 8E 1 2 Transfer X register contents to stack pointer sp X N Z 38 TYA BF 1 2 Transfer Y register contents to accumulator lt Y N Z viii December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 Exchange X register contents with accumulator X lt gt 39 XAX EE 1 4 40 DE 1 4 Y register contents with accumulator Y o ________ 41 XMA dp BC 2 5 Exchange memory contents with accumulator 42 XMA dp X AD 2 6 M oA N 2 43 X 1 5 44 XYX FE 1 4 Exchange X register contents with Y register XY 16 BIT operation Cycle Flag No Mnemonic i Code No No Operation NVGBHIZC 16 Bits add without Carry 1 ADDW dp 1D 2 5 YA lt YA dp 1 dp NV H ZC Compare YA contents with memory pair contents 2 CMPW d 5D 2 4 N ZC i YA dp 1 dp Decrement memory pair 3 DECW d BD 2 6 N 2 2
42. ADC AND CMP EOR LDA LDY OR SBC STA STY XMA ASL DEC INC LSR ROL ROR Example G 0 0 5 C645 LDA 45 s J e 3AH data 7536 data gt A 0E5504 c6 0 551 45 J x 45 0 5 13 SSS gl 43 MC81F8816 8616 Y indexed direct page 8 bit offset gt dp Y This address value is the second byte Operand of com mand plus the data of Y register which assigns Memory in Direct page This is same with above Use Y register instead of X Y indexed absolute abs Y Sets the value of 16 bit absolute address plus Y register data as Memory This addressing mode can specify mem ory in whole area Example 55 D500FA LDA 100 05 OF 1014 00 OF 102 FA 55 55 data data A 6 Indirect Addressing Direct page indirect dp Assigns data address to use for accomplishing command which sets memory data or pair memory by Operand Also index can be used with Index register X Y JMP CALL Example G 0 44 SEMICONDUCTOR 3F35 JMP 35g vA Ei ee 35H 0A 36H E3 J 1 jump to address 0E30AH lt OFA00H 3F 35 ass m TT X indexed indirect dp X Processes memory data as Data assigned by 16 bit pair memory which is determined by pair data dp X 1 dp X Operand plus X register
43. Bit WTRH 6 0 WT data capture Value WTR Watch Timer Register w 6 WT6 w 7 5 5 Bit WTCL WT Clear 0 Free Run 1 WT Clear Auto clear after 1cycle WTMR Watch Timer Mode Register R W R W 6 5 R W 4 R W 3 R W Bit 7 2 WTEN iLOADEN WTEN Watch Timer Enable Bit 0 Watch Timer Disable 1 Watch Timer Enable WTIN 1 0 Watch Timer Interrupt Interval Selection 00 21 16Hz 01 fuck 213 4Hz 10 fug 214 2Hz 11 fwek 214 x 7bit WT value 1 2Hz x 7bit WT value 1 i WTRH6 WTRHS WTRH4 WTRH3 i WTRH2 i WTRH1 WTRHO WT 6 0 WT Interrupt Interval Value WT Interrupt Interval IFWT fwck 214 x 7bit WT Value 1 WTIN1 1 WTINO iWTCK2 WTCK1 WTCKO ADDRESS 09 INITIAL VALUE xxx XXXXp ADDRESS 8 INITIAL VALUE 0111 11115 R W 1 R W 0 ADDRESS 0EAH INITIAL VALUE 00 0000g LOADEN 7bit reload Counter Write Enable Bit 0 Watch Dog Timer Write Enable 1 Watch Timer Write Enable WTCK 2 0 Watch Timer Clock Source Selection fuck 000 Sub Clock 001 Main Clock 28 010 Main Clock 27 011 Main Clock fain 100 Main Clock 2 When fsua 32 768 kHz and 4 19 MHz fain 27 Example 1 minute watch timer interrupt selection LDM WTMR 1101 1000B T 1 fsu x 214 x count 1 LDM WTR 1111 0111B 080h 119 count
44. ECO INT1 External Interrupt 1 0 R06 Port 1 INT1 input Port Timer2 Event Input BUZO Buzzer Output 0 R05 Port 0 R04 Port 1 EC1 input Port 1 BUZO INTO External Interrupt 0 0 ROS Port 1 INTO input Port ECOI TimerO Event Input 0 RO1 Port 1 ECO input Port PWMO Output 0 ROO Port 1 PWMO TOO December 3 2012 Ver 1 03 MC81F8816 8616 Port pin Alternate function ROO PWMO TOO Timer1 PWM Output TimerO Output R01 ECO Timer 0 Event Count Input R04 BUZO Buzzer Output R05 EC1 INTO Timer2 Event Count Input External Inter rupt 0 Request Input R06 INT1 External Interrupt 1 Request Input R07 INT2 External Interrupt 2 Request Input Note ROIO ROPU POOD and PSRO write only regis ters They can not be read and can not be accessed by bit manipulation instruction Do not use read or read modify write instruction Use byte manipulation instruction R1 Ports R1 is an 8 bit CMOS bidirectional I O port address 0 2 Each I O pin can independently used as an input or an output through the R11O register address has internal pull up that is independently connected or disconnected by register The control registers for are shown below In addition Port R1 is multiplexed with various special features The control register PSR1 address con trols the selection of alternate function
45. Event Count Input R04 BUZO Buzzer Output R05 INTO Timer2 Event Count Input External Inter rupt 0 Request Input R06 INT1 External Interrupt 1 Request Input R07 INT2 External Interrupt 2 Request Input Note 01 0 are not not supported in MC81F8616Q 64pin R10 R17 RI is an 8 bit CMOS bidirectional I O port R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs or schmitt trigger inputs Also pull up resistors and open drain outputs can be assigned by software In addition R1 serves the function of the following special fature Port pin Alternate function R10 PWM1 T2O Timer3 PWM Timer2 Output R11 ACK SCK R12 TX SOUT R13 RX SI R14 R15 R16 SDA R17 SCL R20 R27 R2 is a 5 8 bit CMOS bidirectional I O port 5 bit I O port at MC81F8616Q Each pins 1 or 0 written to the Port Direction Register can be used as outputs or in puts Also pull up resistors and open drain outputs can be assigned by software In addition R2 serves the functions of the various follow December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 ing special features units by R5PSR Register Port pin Alternate function Port pin Alternate function R20 ANO Analog Input PortO R50 SEGO Segment Output 0 R21 AN1 Analog Input Port1 R51 SEG1 Segment Output 1 R22 AN2 Analog Input Port2 R52 SEG2 Segment O
46. Interval Timer is con trolled by the clock control register CKCTLR shown in Figure 11 2 Source clock can be selected by lower 3 bits of CKCTLR When write 1 to bit BCL of CKCTLR BITR register is cleared to 0 and restart to count up The bit BCL be comes 0 automatically after one machine cycle by hard ware BITR and CKCTLR are located at same address and ad dress is read as a BITR and written to CKCTLR fsuB 23 gt fMmain 24 gt fMAIN7 25 fMAIN 2 gt fMAIN 27 fMAain 28 gt source IMAN 29 clock fuain 210 gt Select Input clock lt 2 0 gt main clock frequency fsup sub clock frequency CKCTLR Basic Interval Timer clock control register 8 bit up counter overflow Basic Interval Timer Interrupt clear BCL Figure 11 1 Block Diagram of Basic Interval Timer Source clock Interrupt overflow Period lt 2 0 gt SCMR 1 0 00 or 01 At 2 000 23 0 512 001 24 1 024 010 1 2 2 048 011 fMAIN 25 4 096 100 fMAIN 27 8 192 101 fMAIN 28 16 384 110 fmain 29 32 768 111 fmain 210 65 536 Table 11 1 Basic Interval Timer Interrupt Time December 3 2012 Ver 1 03 53 ABOV MC81F8816 8616 SEMICONDUCTOR ADDRESS CKCTLR INITIAL VALUE 0010111 Address
47. LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP con dition START and STOP conditions are always generated by the master The bus is considered to be busy after the START condition The bus is considered to be free again a certain time after the STOP condition The bus stays busy 104 If a repeated START Sr is generated instead of a STOP condition In this respect the START S and repeated START Sr conditions are functionally identical For the remainder of this document therefore the S symbol will be used as a generic term to represent both the START and repeated START conditions unless Sr is particularly rele vant Detection of START and STOP conditions by devic es connected to the bus is easy 1f they incorporate the necessary interfacing hardware However microcontrol lers with no such interface have to sample the SDA line at December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR least twice per clock period to sense the transition MC81F8816 8616 START Condition E l STOP Condition Figure 20 3 Start and Stop condition 20 3 Data Transfer Every byte put on the SDA line must be 8 bits long The number of bytes that can be transmitted per transfer is un restricted Each byte has to be followed by an acknowledge bit Data is transferred with the most significant bit MSB first see Figure 20 4 If a slave can t receive or transmit another complete byte of
48. LSB is send or is received 98 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 RW RW RW RW RW RW RW R 7 6 5 4 3 2 1 0 ADDRESS SPIM POL IOSW SM1 SMO SCK1 SCKO SPIST SPISF INITIAL VALUE 0000 00018 Serial transmission status bit 0 Serial transmission is in progress 1 Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission After one cycle bit is cleared to 0 by hardware Serial transmission Clock selection 00 fxin 4 01 16 10 TMROOV TimerO Overflow 11 External Clock Serial transmission Operation Mode 00 Normal Port R11 R12 R13 01 Sending Mode SCK R13 SO 10 Receiving Mode SCK SI R12 11 Sending amp Receiving Mode SCK SI SO Serial Input Pin Selection bit 0 SI Pin Selection R13 1 SO Pin Selection R12 Serial Clock Polarity Selection bit 0 Data Transmission at Falling Edge Received Data Latch at Rising Edge 1 Data Transmission at Rising Edge Received Data Latch at Falling Edge RW RW R W RW RW RW 7 6 5 4 3 2 1 9 ADDRESS 0 7 H SPIR INITIAL VALUE Undefined Sending Data at Sending Mode Receiving Data at Receiving Mode Figure 19 2 SPI Control Register 19 1 Transmission Receiving Timing The serial transmission is started by setting SPIST bitl of SPIM to 1 After one cycle of SCK SPIST is cleared aut
49. One Universal Asynchronous Receiver Trans mitter UART One Serial Peripheral Inter One Inter IC Communication I2C Wide Operating Voltage amp Frequency Range 2 2 5 5V 4 2Mhz 4 5 5 5V 12Mhz 80MQFP 64MQFP 64LQFP Package Types Available Pb free package MC81F8816 80MQFP MC81F8616 MC81C8616 64MQFP 64LQFP December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 1 3 Development Tools The MC81F8816 8616 are supported by a full featured macro assembler an in circuit emulator CHOICE Dr and OTP FLASH programmers There are two different type of programmers such as single type and gang type For mode detail Macro assembler operates under the MS Windows 95 and upversioned Windows OS And 5800 compiler only operates under the MS Windows 2000 and upversioned Windows OS Please contact sales part of ABOV semiconductor MC81F8816 8616 MS Windows based assembler Software MS Windows based Debugger MC800 C compiler Hardware CHOICE Dr Emulator CHOICE Dr EVA81F88 B D Rev2 0 POD80C73D 80MQ POD Name pOD80C74D 64MQ PGM Plus USB Single writer Stand Alone PGM Plus Single writer FLASH Writer Standalone GANG4 8 USB Gang writer USB SIO ISP Board Figure 1 2 PGMplus USB Single Writer Stand Alone PGM_Plus Figure 1 1 Choice Dr Emulator December 3 2012 Ver 1 0
50. RESET VALUE Undefined Figure 15 2 A D Converter Mode amp Result Registers December 3 2012 Ver 1 03 77 MC81F8816 8616 ENABLE A D CONVERTER A D INPUT CHANNEL SELECT A D START ADST 1 lt lt lt A Y gt NO YES READ ADCRL ADCRH DISABLE A D CONVERTER Figure 15 3 A D Converter Operation Flow A D Converter Cautions 1 Input range of ANO to AN7 The input voltages of ANO to AN7 should be within the specification range In particular if a voltage above AVref or below Vss is input even if within the absolute maxi mum rating range the conversion value for that channel can not be determinated The conversion values of the oth er channels may also be affected 2 Noise counter measures In order to maintain 8 bit resolution any attention must be paid to noise on pins AVref and ANO to AN7 Since the ef fect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor is 78 ABOV SEMICONDUCTOR connected externally as shown below in order to reduce noise Analog Input 100 1000 T 5 Figure 15 4 Analog Input Pin Connecting Capacitor 3 Pins ANO R20 to AN7 R27 The analog input pins ANO to AN7 also function as input output port PORT R2 pins When A D conversion is per formed with any of pins ANO to AN7 selected be sure not to execute a PORT input instruc
51. area and the SEG COM pins The LCD lights when the display data is 1 and turn off when 0 The SEG data for display is controlled by RPR RAM Pag ing Register 94 o m Q a SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 sEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEGO lt m ABOV SEMICONDUCTOR 04874 04864 0485H 04834 0482 0481 0480 047 047 047Dy 047 047 047 0479 0478 ma 0477 0476 0475 04744 04734 04724 04714 04704 046 046 0460 046 046 046 04694 04684 0467 0466 0465 0464 0463 0462 0461 0460 20117111 191 cc CX Only supported in MC81F8616 Figure 18 4 LCD Display Memory December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 18 4 Control Method of LCD Driver Initial Setting Flow chart of initial setting is shown in Figure 18 5 Example Driving of LCD Select Frame Frequency 4DH fp 64Hz 1 4 duty fsup 32 768kHz LDM RPR 4 Select LCD Memory 4 page SETG Clear LDX 60H LCD Display C_LCD1 LDA 0 RAM Clear 0460H gt 0487H STA XIF CMPX 088H BNE C LCD
52. counter SCLOUT ATE reset 1 SCL start HIGH counting wait HIGH counting Figure 20 6 Clock synchronization during the arbitration procedure 108 December 3 2012 Ver 1 03 ABOV MC81F8816 8616 arbitration process device1 loses device outputs not adapted arbitration HIGH DEVICE1 DATA OUT DEVICE2 DATA OUT SDA on BUS SCL Figure 20 7 Arbitration procedure of two masters December 3 2012 Ver 1 03 109 MC81F8816 8616 ABOV SEMICONDUCTOR 21 UNIVERSAL ASYNCHRONOUS SERIAL INTERFACE UART The Asynchronous serial interface UART enables full duplex operation wherein one byte of data after the start bit is transmitted and received The on chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates The UART driver consists of TXSR RXBR ASIMR and BRGCR register Clock asynchronous serial I O mode UART can be selected by ASIMR register Figure 21 1 shows a block di agram of the serial interface UART Tx R1 Internal Data Bus Receive Buffer Register RXR ASIMR PS0 PS1 SL ISRM Rx R1 Receive Buffer Register RXBR Transmit Shift Register TXSR 2 lt Controller Parity Check Transmit Controller
53. flickered be December 3 2012 Ver 1 03 fore the oscillation of sub clock is stabilized It is recom mended to use LCD display on after the stabilization time of sub clock is considered enough 91 MC81F8816 8616 18 2 LCD BIAS Control The MC81F8816 8616 has internal Bias Circuit for driving LCD panel It alse has the contrast controller of 16 step The LCD Bias control register and internal Bias circuit is as shown in the Figure 18 3 The SYS BOD 1 0 and BIF of LBCR register is used for controlling BOD Refer to 27 Brown out Detector BOD 92 SEMICONDUCTOR Note The self bias check reference can be applied to con trast adjustment with VDD voltage variation Because the VDD voltage can be calculated by reading the ADC value of self bias check reference Writing appropriate value to CTR 3 0 with VDD level LCD contrast variation with VDD can be reduced December 3 2012 Ver 1 03 NBOV MC81F8816 8616 SEMICONDUCTOR LBCR LCD Bias Control Register R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 ADDRESS RESET VALUE 01111000B CTR_S Voltage Source selection CTR_DS lt 3 0 gt Contrast Controller Level Selection 0 Direct Voltage 0000 VCL3 VDD 2 1 Contrast Controller voltage Sane e OE 2 ere i 2 M 4 Mode selection of BOD Result 0011 VCL3 VDD 2 VDD 3 30 10 Freeze mode 0100 VCL3 VDD 2 VDD 4 30 0101 VCL3 2
54. interrupt ECO UART interrupt and External interrupt Peripheral Sleep Mode Release method by RESET All interrupts Table 23 1 Peripheral Operation during Power Down Mode 1 Refer to the Table 10 2 Operating Sub Active Sub Sleep Stop Mode Stop Mode Clock source od g Sleep Mode Operating Mode Operating Mode 1 2 SCMR 2 SCMR 2 Main Clock Oscillation Oscillation 0 gt Oscillation 0 gt Oscillation Stop Stop 1 gt Stop 1 gt Stop Sub Clock Oscillation Oscillation Oscillation Oscillation Oscillation Stop System Clock Active Stop Active Stop Stop Stop Peri Clock Active Active Active Active Stop Stop 1 Except watch timer sub clock and LCD driver sub clock Table 23 2 Clock Operation of STOP and SLEEP mode Note Since the pin is connected internally to GND to avoid current leakage due to the crystal oscillator in STOP mode do not use STOP instruction when an external clock is used as the main system clock In the Stop mode of operation Vpp can be reduced to min imize power consumption Be careful however that Vpp is not reduced before the Stop mode is invoked and that Vpp is restored to its normal operating level before the Stop mode is terminated The reset should not be activated before Vpp is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize And
55. nl Figure 28 1 Block Diagram of ONP amp OFP and Respective Wave Forms December 3 2012 Ver 1 03 129 MC81F8816 8616 The oscillation fail processor OFP can change the clock source from external to internal oscillator when the oscil lation fail occured This function could be enabled or dis abled by the OFP bit of the Device Configuration Area MASK option for MC81F8816 8616 And this function can recover the external clock source when the external clock is recovered to normal state The INSMCLK IN4MCLK IN83MCLKXO 130 SEMICONDUCTOR INAMCLK XO option of the Device Configuration Area enables the function to operate the device by using the in ternal oscillator clock in ONP block as system clock There is no need to connect the x tal resonator RC and R exter nally After selecting the this option the period of internal oscillator clock could be checked by Xour outputting clock divided the internal oscillator clock by 4 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 29 FLASH PROGRAMMING SPEC 29 1 FLASH Configuration Byte Except the user program memory there is configuration byte address 20FFy for the selection of program lock ONP OPF oscillation configuration and reset configura tion The configuration byte of FLASH is shown as Figure 29 1 It could be served when user use the FLASH pro grammer MC81F8816 8616 Note The Configuration Option may not be read exactly when VD
56. of TM1 3 decides the polarity of duty cycle The duty value can be changed when the PWM outputs However the changed duty value is output after the current period is over And it can be maintained the duty value at present output when changed only period value shown as Figure 12 19 As it were the absolute duty time is not changed in varying frequency Note If the user need to change mode from the Timer3 mode to the PWM mode the Timer3 should be stopped firstly and then set period and duty register value If user writes register values and changes mode to PWM mode while Timer3 is in operation the PWM data would be different from expected data in the beginning The relation of frequency and resolution is in inverse pro portion Table 12 2 shows the relation of PWM frequency vs resolution PWM Period T1 3 PWHR 3 2 T1 3 PPR 1 X Source Clock PWM Duty T1 3 PWHR 1 0 T1 3 PDR 1 X Source Clock If it needed more higher frequency of PWM it should be reduced resolution T1PWHR 3 2 T1ST 0 Stop 1 Clear and Start TO clock source COMPARATOR T1CN T1CK 1 0 SCMR 1 0 Slave 8 bit ax T1PWHR 1 0 Master 7 6 5 4 3 2 1 0 I 7 7 7 T ADDRESS 0D2H TM1 POL 16BIT i PWMOE CAP1 i T1CK1 i TICK0 TICN TIST RESET VALUE 000000008 X 0 1 0 X X X X T ADDRESS 003 PWMOHR4PWMOHR2 PWMOHRtPWMOHRO RESET VALUE 00008 x
57. of the internal data memory The SP is not initialized by hardware requiring to write the initial value the loca tion with which the use of the stack starts by using the ini tialization routine Normally the initial value of 1FFy is used Stack Address 100 1 15 8 7 0 Hardware fixed RAM 1 page 01 Caution The Stack Pointer must be initialized by software be cause its value is undefined after RESET Example To initialize the SP LDX TXSP SP lt OFFg Program Counter The Program Counter is a 16 bit wide which consists of two 8 bit registers PCH and PCL This counter indicates the address of the next instruction to be executed In reset state the program counter has reset rou tine address PCy 0FFy PCL 0FEp Program Status Word The Program Status Word PSW contains several bits that reflect the current state of the CPU The PSW is described in Figure 8 3 It contains the Negative flag the Overflow flag the Break flag the Half Carry for BCD operation the Interrupt enable flag the Zero flag and the Carry flag Carry flag C This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR Zero flag Z This flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared
58. result of the A D conversion When the conversion is com pleted the result is loaded into the ADCR the A D conver sion status bit ADF is set to 1 and the A D interrupt flag ADIF is set The block diagram of the A D module is shown in Figure 15 1 The A D status bit ADF is automat ically set when A D conversion is completed cleared when A D conversion is in process The conversion needs 13 clock period of ADC clock fps It is recommended to use ADC clock of at least lus period Note The ADC value of self bias check refer ence Vbias ret is can be used to check the VDD voltage When reris 1 185V and VDD is 5 12V the ADC value is OEDh If VDD is changed and ADC value is 13Ch the VDD voltage is 3 84V the ADC value is changed to 13Ch The VDD voltage can be calculated by following formula VDD voltage 1024 ADC Value Successive Approximation Circuit ADC ADCIF INTERRUPT 8 bit Mode 98 32 10 bit ADCR M ADCRH ADCRL 8 bit TO ADC Result Register Figure 15 1 A D Converter Block Diagram amp Registers 76 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 ADCM A D Converter Mode Register RW RW R W R W R W R W RW R Bit 7 6 5 4 3 2 1 0 i i i ADDRESS 0 2 ADEN i ADS3 i ADS2 ADS1 ADSO ADST ADF RESET VALUE 000000016 ADEN A D Converter Enable bit ADS 3 0 A D Converte
59. riod and its HIGH period determined by the one with the shortest clock HIGH period A master may start a transfer only if the bus is free Two or more masters may generate a START condition within the minimum hold time tHD STA of the START condition which results in a defined START condition to the bus Arbitration takes place on the SDA line while the SCL line is at the HIGH level in such a way that the master which transmits a HIGH level while anoth er master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn t correspond to its own level Arbitration can continue for many bits Its first stage is comparison of the address bits addressing information is given in Sections 10 and 14 If the masters are each trying to address the same device ar bitration continues with comparison of the data bits if they are master transmitter or acknowledge bits if they are master receiver Because address and data information on the I2C bus is determined by the winning master no information is lost during the arbitration process A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration As an Hs mode master has a unique 8 bit master code it will always finish 107 MC81F8816 8616 the arbitration during the first byte If a master also incor porates a slave function and it loses arbitration during the addressing stage it s possible
60. that the winning master is trying to address it The losing master must therefore switch over immediately to its slave mode Figure 20 7 shows the arbitration procedure for two masters Of course more may be involved depending on how many masters are connected to the bus The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line its data output is switched off which means that a HIGH output level is then connected to the bus This will not af fect the data transfer initiated by the winning master Since control of the I2C bus is decided solely on the address or master code and data sent by competing masters there is no cen tral master nor any order of priority on the bus Special at ABOV SEMICONDUCTOR tention must be paid 1f during a serial transfer the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I2C bus If it s possible for such a situation to occur the masters involved must send this repeated START condition or STOP condition at the same position in the format frame In other words arbitration isn t al lowed between e A repeated START condition and a data bit e A STOP condition and a data bit e A repeated START condition and a STOP condition Slaves are not involved in the arbitration procedure FAST DEVICE SCLOUT LOW DEVICE n HIGH
61. their respective timer counter register The AD converter December 3 2012 Ver 1 03 MC81F8816 8616 Interrupt is generated by ADCIF which is set by finishing the analog to digital conversion The Basic Interval Timer Interrupt is generated by BITIF which is set by overflow of the Basic Interval Timer Reg ister BITR The Watch dog Interrupt is generated by WDTIF which set by a match in Watch dog timer register when the bit WDTON is set to 0 The Watch Timer In terrupt is generated by WTIF which is set periodically ac cording to the established time interval When an interrupt is generated the bit of interrupt request flag register IRQM IRQL that generated it is cleared by the hardware when the service routine is vec tored to only if the interrupt was transition activated Each bit of Interrupt flag register INTFH INTFL is set when corresponding interrupt flag bit as well as interrupt enable bit are set The bits of interrupt flag register are nev er cleared by the hardware although the service routine is vectored to Therefore the interrupt flag register can be used to distinguish a right interrupt source from two avail able ones in a vector address For example RX0 and TXO which have the same vector address FFF2y may be distin guished by INTFH register Interrupt enable registers are shown in Figure 17 2 These registers are composed of interrupt enable bits of each in terrupt source these bits determ
62. vector of TCALL 0 Refer to Program Memory Section When BRK interrupt is generated B flag of PSW is set to distin guish BRK from TCALL 0 Each processing step is determined by B flag as shown in Figure 17 4 17 3 Multi Interrupt If two requests of different priority levels are received si multaneously the request of higher priority level is ser viced If requests of the interrupt are received at the same time simultaneously an internal polling sequence deter mines by hardware which request is serviced However multiple processing through software for special features is possible Generally when an interrupt is accept ed the I flag is cleared to disable any further interrupt But as user sets I flag in interrupt routine some further inter rupt can be serviced even if certain interrupt is in progress Example Even though Timerl interrupt is in progress INTO interrupt serviced without any suspend TIMER1 PUSH A PUSH X PUSH Y December 3 2012 Ver 1 03 MC81F8816 8616 General purpose registers are saved or restored by using push and pop instructions main routine acceptance of interrupt interrupt service routine AN 8019 restoring registers BRK or TCALLO BRK INTERRUPT ROUTINE RETI TCALLO ROUTINE Figure 17 4 Execution of BRK TCALLO LDM IENH 40H LDM IENM 0 Disable other LDM IENL 0 Disable other EI Enable Interrupt Enable INTO o
63. watch timer generates interrupt for watch operation The watch timer consists of the clock selector 21 bit bina ry counter and watch timer mode register It is a multi pur pose timer It is generally used for watch design The bit 0 1 2 of WTMR select the clock source of watch timer among sub clock 29 fMAIN 27 f MAIN or fMAIN 2 of main clock and fMAIN of main clock The fMAIN of main clock is used usually for watch timer test so generally it is not used for the clock source of watch timer The fMainz2 or 29 clock is used when the single clock system is organized If fMAIN 28 or fMain 27 clock is used as watch timer clock source when the CPU enters into stop mode the main clock is stopped and then watch ABOV SEMICONDUCTOR timer is also stopped If the sub clock is used as the watch timer source clock the watch timer count cannot be stopped Therefore the sub clock does not stop and contin ues to oscillate even when the CPU is in the STOP mode The timer counter consists of 21 bit binary counter and it can count to max 60 seconds at sub clock The bit 3 4 of WTMR select the interrupt request interval of watch timer among 2Hz 4Hz 16Hz and 1 64Hz Note The Clock source of watch timer is also applied to LCD dirver clock source When selecting LCD dirver clock source the WTCK 2 0 should be set to appropriate value WTRH Watch Timer Read High Register R R R 6 5 4 x R 3 R 2
64. 04 1 302 0 651 10 14 706 7 353 3 676 1 838 30 5 102 2 551 1 276 0 638 11 13 889 6 944 3 472 1 736 31 5 000 2 500 1 250 0 625 12 13 158 6 579 3 289 1 645 32 4 902 2 451 1 225 0 613 13 12 500 6 250 3 125 1 563 33 4 808 2 404 1 202 0 601 14 11 905 5 952 2 976 1 488 34 4 717 2 358 1 179 0 590 15 11 364 5 682 2 841 1 420 35 4 630 2 315 1 157 0 579 16 10 870 5 435 2 717 1 359 36 4 545 2 273 1 136 0 568 17 10 417 5 208 2 604 1 302 37 4 464 2 232 1 116 0 558 18 10 000 5 000 2 500 1 250 38 4 386 2 193 1 096 0 548 19 9 615 4 808 2 404 1 202 39 4 310 2 155 1 078 0 539 1A 9 259 4 630 2 315 1 157 3A 4 237 2 119 1 059 0 530 1B 8 929 4 464 2 232 1 116 3B 4 167 2 083 1 042 0 521 1C 8 621 4 310 2 155 1 078 3C 4 098 2 049 1 025 0 512 1D 8 333 4 167 2 083 1 042 3D 4 032 2 016 1 008 0 504 1E 8 065 4 032 2 016 1 008 3E 3 968 1 984 0 992 0 496 1F 7 813 3 906 1 953 0 977 3F 3 906 1 953 0 977 0 488 80 Table 16 1 Buzzer Output Frequency December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 17 INTERRUPTS The MC81F8816 8616 interrupt circuits consist of Inter rupt enable register IENH IENM IENL Interrupt re quest flag register IROH IROM IRQL Interrupt flag register INTFH INTFL Interrupt Edge Selection Regis ter IEDS priority circuit and Master enable flag flag of PSW The interrupts are controlled by the interrupt master enable flag I flag bit 2 of PSW the interrupt en able register and the interrupt request
65. 1 CLRG Turn on LCD SET1 iCR 5 Enable display COMO Setting of LCD drive method Initialize of display memory Enable display A COM2 seco C Q iem SEG1 Example display 2 bit 7 6 5 4 39 2 1 0 Note are don t care Figure 18 5 Initial Setting of LCD Driver Display Data Normally display data are kept permanently in the pro gram memory and then stored at the display data area by the table look up instruction This can be explained using character display with 1 4 duty LCD as an example as well as any LCD panel The COM and SEG connections to the LCD and display data are the same as those shown is Fig ure 18 6 Following is showing the programming example for displaying character December 3 2012 Ver 1 03 Figure 18 6 Example of Connection COM amp SEG Note When power on RESET sub oscillation start up time is required Enable LCD display after sub oscillation is sta bilized or LCD may occur flicker at power on time shortly 95 SEMICONDUCTOR MC81F8816 8616 ABOV CLRG LDX lt DISPRAM Address included the data to be displayed GOLCD LDA X Write into the TAT LDA FONT Y LOAD FONT DATA LCD Memory LDMRPR 4 Set RPR 4 to access LCD SETG Set Page 4 LDX 60H STA X 2 LOWER 4 BITS OF ACC segO XCN a STA X UPPER 4 BITS OF ACC segl CLRG Set Page 0 FONT DB 1101 01118 0 DB 0000 0110B
66. 100 1 Page 2 200 26 Page 4 4604 4874 Figure 8 9 RAM page configuration 38 ABOV SEMICONDUCTOR RPR RAM Page Selection Register ADDRESS INITIAL VALUE _ 001 MSB LSB RW RW R W 2 1 zj RPR 2 0 RAM Page Selection RPR2 RPR1 RPRO RAM Page Selection 0 0 0 PAGE 0 0 0 1 PAGE 1 0 1 0 PAGE 2 0 1 1 1 0 0 PAGE 4 1 0 1 1 1 0 1 1 1 Caution1 After setting RPR be sure to execute SETG instruction Caution2 When executing instruction be selected PAGEO regardless of RPR Figure 8 10 RAM Page Selection Register Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device Therefore these registers contain control and status bits for the interrupt system the timer counters analog to digital converters and I O ports The control registers are in address range of 090g to OFF Note that unoccupied addresses may not be implemented on the chip Read accesses to these addresses will in gen eral return random data and write accesses will have an in determinate effect More detailed informations of each register are explained in each peripheral section Note Write only registers can not be accessed by bit ma nipulation instruction Do not use read modify write instruc tion Use byte manipu
67. 250 36H 0 52 0 00 2DH 170 28H 000 24H 000 21H 1 30 38 400 32H 0 00 2AH 0 6 28H 0 00 23H 279 20H 173 1BH 1 14 76 800 22H 0 00 0 16 18H 0 00 13H 279 10H 173 115 200 18H 000 11H 212 10H loo Table 21 2 Relationship Between Main Clock and Baud Rate 114 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 22 OPERATION MODE The system clock controller starts or stops the main fre quency clock oscillator which is controlled by system clock mode register SCMR Figure 22 1 shows the oper ating mode transition diagram System clock control is performed by the system clock mode register SCMR During reset this register is initial ized to 0 so that the main clock operating mode is select ed Main Active mode This mode is fast frequency operating mode The CPU and MC81F8816 8616 the peripheral hardwares are operated on the high frequen cy clock At reset release this mode is invoked SLEEP mode In this mode the CPU clock stops while peripherals and the oscillation source continue to operate normally STOP mode In this mode the system operations are all stopped holding the internal states valid immediately before the stop at the low power consumption level Main Oscillation Sub Oscillation System Clock Main LDM SCMR 02H Main Oscillation Sub Oscillation System Clock S
68. 3 Figure 1 3 Stand Alone PGM Plus ISP MC81F8816 8616 SEMICONDUCTOR Figure 1 4 Standalone Gang4 USB Gang Writer Figure 1 5 Standalone Gang8 Gang Writer Figure 1 6 USB SIO ISP Board December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 1 4 Ordering Information Device name ROM Size RAM size Package MC81F8816Q 80MQFP FLASH version MC81F8616Q 16K bytes 512 bytes 64MQFP MC81F8616L 64LQFP MC81C8616Q 64MQFP MASK version MC81C8616L 16K bytes 512 bytes 641 Pb package The P suffix will be added at original part number For example MC81F8816Q Normal package MC81F8816Q P Pb free package December 3 2012 Ver 1 03 SEMICONDUCTOR MC81F8816 8616 NBOV 2 BLOCK DIAGRAM 2 1 MC81F8816Q 80 pin package Common Drive Output Segment Drive Output COMO COM7 SEGO SEG35 COMO COM3 SEGO SEG39 BIAS selection circuit Intermal Resistor cy LCD Controller Driver for LCD Bias i 1 Power Supply PSW ALU Accumulator
69. 3 RX SI 43 35 1810 Serial Data Input R14 44 36 R15 45 37 SIO Serial Data R16 SDA 46 38 1 0 In Out 2 R17 SCL 47 39 Clock In Out R20 ANO A D Converter R24 AN4 ae 40 44 VO Analog Input R25 AN5 A D Converter R27 AN7 99799 I 9 Analog Input Table 5 1 Port Function Description December 3 2012 Ver 1 03 15 MC81F8816 8616 ABOV 6 PORT STRUCTURES R01 ECO RO5 EC1 INTO ROG INT1 07 1 2 R13 RX SI R16 SDA R41 IN3 Pull up Register gt L Pull up Tr Open Drain Register Vpp Data Register 1 Pin Direction Register J gt L1 gt Vss Vss 4 44 ub Func Noise Input Register Sub Func Input Enable Vpp Data Bus R00 PWMO TOO R04 BUZO R10 PWM1 T2O R17 SCL Vpp Pull up Register T gt 4 Pull up Tr Open Drain Register Data Register _ Output Register Vpp Data Bus Sub Func Output Enable T RD Direction Register V Vss Vss 16 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR R11 ACK SCK R12 TX SOUT MC81F8816 8616 Data Bus Pull up Register Open Drain Register Data Register ub Func ER Direction Register Output Register Sub Func Output Enable ub Func Input Register Sub Func
70. 5 4 3 2 1 0 PAMIHFG 2 1 1 1 ADDRESS 0DBH INITIAL VALUE 00000g Figure 12 3 Related Registers with Timer Counter2 3 58 December 3 2012 Ver 1 03 SEMICONDUCTOR NBOV MC81F8816 8616 16BIT CAPO TOCK 2 0 T1CK 1 0 Timer 0 Timer 1 0 0 XXX XX 8 Bit Timer 8 Bit Timer 0 0 111 XX 8 Bit Event Counter 8 Bit Timer 0 1 XXX XX 8 Bit Capture 8 Bit Compare Output 1 0 XXX 11 16 Bit Timer 1 0 111 11 16 Bit Event Counter 1 1 XXX 11 16 Bit Capture 1 0 XXX 11 16 Bit Compare Output Table 12 1 Operating Modes of Timer 0 and Timer 1 12 1 8 Bit Timer Counter Mode The MC81F8816 8616 have four 8 bit Timer Counters isters TMx x 0 1 2 3 as shown in Figure 12 1 and Table Timer0 Timerl Timer2 and Timer3 as shown in Figure 12 1 To use as an 8 bit timer counter mode bit CAPx of 12 4 TMx is cleared to 0 and bits 16BIT of TM1 3 should be The timer or counter function is selected by mode reg cleared te Table TUS E Bit 7 6 5 4 3 2 1 0 ADDRESS 0D0 TMO E ME TOCK2 TOCK1 TOCKO TOCN TOST RESET VALUE 0000008 0 X X X x x ADDRESS 0D2H TM1 POL 16BIT iPWMOE T1CK1 TICN T1ST RESET VALUE 000000006 X 0 0 0 X X X x X The value 0 or 1 corresponding your operation T1 8 bit
71. 7 6 5 4 3 2 1 0 ADDRESS 2 i LCDEN pape TEN RESET VALUE 000 0000B SCKD Sub Clock Disable LCDDO LCD Duty Selection 0 Sub Clock Oscillation SXIN SXOUT 0 1 8 Duty 1 4 Bias 1 Sub Clock Disable R43 R44 1 1 4 Duty 1 3 Bias COM 7 4 is used as SEG Port LCK lt 1 0 gt LCD Clock source selection LEDEN LCD Display Enable 00 fs 32 Frame Frequency 1024Hz When fs is 32 768kHz 0 LCD Display Disable E 1 LCD Display Enable 01 fs 64 Frame Frequency 512Hz When fs is 32 768kHz 10 fs 128 Frame Frequency 256Hz When fs is 32 768kHz Unused bit of LCR should be set as 11 fs 256 Frame Frequency 128Hz When fs is 32 768kHz Bit6 1 Bit4 0 fs Sub clock or fMain 27 or fain 28 or fain 2 Or Bit3 1 It can be selected by setting WTCK 2 0 of WTMR register R5 LCD Port Selection Register R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 ADDRESS 0EAH WTEN iLOADEN i WTIN1 WTINO WTCK2 WTCK1 WTCKO INITIAL VALUE 00 00008 WTEN Watch Timer Enable Bit LOADEN 7bit reload Counter Write Enable Bit 0 Watch Timer Disable 0 Watch Dog Timer Write Enable 1 Watch Timer Enable 1 Watch Timer Write Enable WTIN 1 0 Watch Timer Interrupt Interval Selection WTCK 2 0 Watch Timer and LCD Clock Source Selection fuck 00 211 16Hz 000 Sub Clock 01 fwek 213 4Hz 001 Main Clock fmain 28 10 fwok 214 2Hz 010 Mai
72. 7 6 AC Characteristics TA 25 C Vpp 4V AVref 4V Vss AVss 0V MC81F8816 8616 Specifications Parameter Symbol Pins Unit Min Typ Max Main Operating Frequency 0 4 12 MHz Sub Operating Frequency fscp SXIN 30 32 768 35 kHz System Clock Frequency tsys 166 5000 ns Main Oscillation Stabilization Time 4MHz Xin Xour 20 is Sub Oscillation Stabilization Time tssr SXIN SXour 1 2 z External Clock tMCPW XIN 35 nS H or L Pulse Width tscpw SXIN 5 _ _ uS External Clock Transition Time XIN 20 nS Interrupt Pulse Width tw INTO INT1 INT2 IN3 2 tsvs RESET Input Pulse L Width tRST RESET 8 tsys Event Counter Input H or L Pulse Width 2 tsys Event Counter Transition Time tREC tFEC ECO 1 20 nS 1 SCMR XXXX000Xg that is fMAIN 2 December 3 2012 Ver 1 03 25 MC81F8816 8616 ABOV SEMICONDUCTOR XIN INTO INT1 INT2 INT3 RESET ECO EC1 1 fMCP lt tRsT gt 0 2Vpp 26 Figure 7 2 AC Timing Chart December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 7 7 Serial I O Characteristics 40 85 C Vpp 5 0V 10 Vss 0V Specifications Parameter Symbol Pi
73. 8XXLE Yes INAM YYWW KOREA 8 Free PKG B Pb Halogen Free PKG gt Crystal E Work Week ROM Code Number IFONPis Crystal Customer s logo No Use Mask Data File Name Check Sum YYWW KOREA Customer logo is not required If the customer logo must be used in the special mark please submit a clean original of the logo Customer s part number OTP file data Please check mark into 4 Delivery Schedule Quantity ABOV Confirmation Customer Sample pcs Risk Order pcs 5 ROM Code Verification Verification Date Tel Name amp Check Sum Signature ABOV semiconductor C MASK ORDER SHEET MC81C8616 MASK ORDER amp VERIFICATION SHEET MC81C86 LE Customer should write inside thick line box 1 Customer Information 2 Device Information Free PKG B Pb Halogen Free PKG Company Name Package 64MQFP 64LQFP Application ROM Size 16K Order Date Unused 00H
74. ABOV SEMICONDUCTOR Co Ltd 8 BIT SINGLE CHIP MICROCONTROLLERS 81 8816 8616 User s Manual Ver 1 03 ABOV SEMICONDUCTOR Version 1 03 Published by FAE Team 2008 ABOV Semiconductor Co Ltd All rights reserved Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual ABOV MC81F8816 8616 SEMICONDUCTOR REVISION HISTORY VERSION 1 03 December 3 2012 This Book ABOV logo is renewed on this book Single and Gang writer are added in 1 3 Development Tools on page 3 VDD voltage for sub active mode is changed to 3 0 5 5V in 7 2 Recommended Operating Conditions on page 21 The notice of STOP mode is added in 23 2 STOP Mode on page 118 Notice If the STOP mode is used in the program BOD function should be disabled in the initial routine of software Block diagram of BOD is updated in Figure 27 1 Block Diagram of BOD Brown out Detector Reset on page 127 VERSION 1 02 February 11 2010 The caution for the ALE pin at ISP mode is added in 31 3 Hardware Conditions to Enter the ISP Mode on page 136 VERSION 1 01 Januar
75. D rising time is very slow It is recommended to adjust the VDD rising time faster than 40ms V 200ms from OV to 5V 7 6 5 4 3 2 Configuration Option Bits ONP OFP POR 47 2 CLK1 CLK0 L 1 0 ADDRESS 20FFH INITIAL VALUE 00H Oscillation confuguration 00 INAMCLK Internal 4MHz Oscillation amp R45 R46 Enable 01 X tal Crystal or Resonator Oscillation 10 IN8MCLK Internal 8MHz Oscillation amp R45 R46 Enable 11 Prohibited Systeam clock confuguration 0 Xin 2 1 Xin RESET R47 Port configuration 0 R47 Port Disable Use RESET 1 R47 Port Enable Disable RESET POR Use 0 Disable POR Reset 1 Enable POR Reset Security Bit 0 Enable reading User Code 1 Disable reading User Code OFP use 0 Disable OFP Clock Changer 1 Enable OFP Clock Changer ONP disable 0 Enable ONP Enable OFP Internal 8MHz 4MHz oscillation 1 Disable ONP Disable OFP Internal 8MHZ4MHz oscillation Figure 29 1 The FLASH Configuration Byte 29 2 FLASH Programming The MC81F8816 8616 is a MTP microcontroller Its internal user memory is constructed with FLASH ROM Blank FLASH s internal memory is filled by 00g not Note In any case you have to use the OTP file for pro gramming not the HEX file After assemble both OTP and HEX file are generated by automatically The HEX file is used during program emulation o
76. December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR ADDRESS 8 RESET VALUE 0000000 R4 R47 R46 R45 R44 R43 R42 R41 RAO R4 Data Register i i i ADDRESS 9 R4 Direction Register RESET VALUE 0000000 Port Direction 0 Input 1 Output R4 Pull up ADDRESS 0 9 Selection Register RESET VALUE 00000000 R4PU i i i Pull up select 0 Without pull up 1 With pull up R4 Open Drain Selection Register ADDRESS 0 4 RESET VALUE 0000000g ROOD ME Open Drain select 0 No Open Drain 1 Open Drain Port ADDRESS 0ABH Selection Register 1 RESET VALUE 0008 PSR1 i iINT3 INT2IPWM INT3 External Interrupt 3 0 R41 Port 1 INT3 input Port INT2 External Interrupt 2 0 R07 Port 1 INT2 input Port PWM10 PWM1 Output 0 R10 Port 1 PWM10 T20 ADDRESS 0B2 LCD Control Register RESET VALUE 00000000 LCR SCKD 1 iLCDEN 0 1 iLCDDGLCK1 iLOQO SCKD Sub Clock Disable 0 Sub Clock Oscillation Enable SXIN SXOUT 1 Sub Clock Oscillation Disable R43 R44 In addition Port R4 is multiplexed with oscillation input output reset and interrupt input pins The control register PSRI address controls the selection of alternate function After reset this value is 0 port may be used as normal I O port To use alternate function such as External Interrupt rather than normal I O write 1 in th
77. Disable all interrupts 1 0 0 3 EI EO 1 3 Enable all interrupt 1 lt 1 ee 1 4 1 2 Nooperation 5 00 1 4 sp lt sp 1 lt Msp 6 X 2 1 4 spesp 1 X M sp C 7 POP Y 4D 1 4 sp lt sp 1 Y lt M sp 8 POP PSW 6D 1 4 sp lt sp 1 PSW lt M sp restored 9 PUSH A 1 4 M sp lt A sp lt sp 1 10 PUSH X 2E 1 4 M sp eX spesp 1 j c 11 PUSH Y 4E 1 4 M sp lt Y sp lt sp 1 12 PUSH PSW 6E 1 4 M sp lt PSW sp lt sp 1 18 BE 2 2 sp lt sp 1 lt 5 Return from interrupt 14 RETI 1 6 sp lt sp 1 PSW lt Msp sp lt sp 1 restored lt M sp sp lt sp 1 lt M sp 15 STOP EF 1 3 Stop mode halt CPU stop oscillator 1 xii December 3 2012 Ver 1 03 B MASK ORDER SHEET MC81C8816 MASK ORDER amp VERIFICATION SHEET 81 88 Customer should write inside thick line box 1 Customer Information 2 Device Information Free PKG B Pb Halogen Free PKG Company Name Package 80MQFP Application ROM Size 16K order Date Unused 00H Tel E mail POR R47 Use Yes Name amp Signature 3 Marking Specification ONP Use Yes X2EN Yes 16 or 60 If ONP is D MC81C8
78. EC dp X B9 2 5 41 DEC abs B8 3 5 N Z 42 DEC X AF 1 2 43 DEC Y BE 1 2 44 DIV 9B 1 12 Divide YA XQ A R Y NV H Z 45 EOR imm 4 2 2 Exclusive OR 46 EOR dp A5 2 3 A lt 47 EOR dp X A6 2 4 48 EOR abs AT 3 4 N 2 49 EOR abs Y B5 3 5 50 EOR dp X B6 2 6 51 EOR dp Y B7 2 6 52 EOR X B4 1 3 53 INC A 88 1 2 Increment 54 INC dp 89 2 4 M lt M 1 55 INC dp X 99 2 5 56 INC abs 98 3 5 N 2 57 INC X 8F 1 2 58 INC Y 9E 1 2 2 wel 1 2 Logical shift right 60 LSR dp 49 2 4 76543210 N ZC 61 LSR dp X 59 2 5 v gt BRBPPPPPP gt 62 LSR abs 58 3 5 63 MUL 5B 1 9 Multiply YA lt Y xA N 2 64 OR imm 64 2 2 Logical OR 65 OR dp 65 2 3 A A v M 66 OR dp X 66 2 4 67 OR abs 67 3 4 N 2 68 OR labs Y 75 3 5 69 OR dp X 76 2 6 70 OR dp Y 77 2 6 71 OR X 74 1 3 L2 RORA 2 Rotate left through Carry 73 ROL dp 29 2 4 c 76543210 N ZC 74 ROL dp X 39 2 5 L I lt lt 75 ROL abs 38 3 5 vi December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 No Mnemonic 225 E E Operation v W 16 ee 59 2 Rotate right through Carry 77 ROR dp 69 2 4 76543210 C N ZC 78 ROR dp X 79 2 5 gt ace pt pst 79 ROR abs 78 3 5 80 SBC imm 24 2 2 Subtract with Carry 81 SBC dp 25 2 3 lt
79. ERRUPT T3CN T3CK 1 0 COMPARATOR CAPTURE CDR3 8 bit TDR3 8 bit b INT 3 gt INTSIF INTERRUPT IEDS 7 6 Figure 12 11 8 bit Capture Mode Timer2 Timer3 December 3 2012 Ver 1 03 65 MC81F8816 8616 T0 1 2 3 Ext 0 1 2 3 Pin Interrupt Request INTOF INT1F Ext INTO Pin Interrupt Request ABOV SEMICONDUCTOR This value is loaded to CDRO 1 2 3 ag TIME 20ns 5X1 N 5ns lt Interrupt Interval Period Lg j DD Interrupt Request INTOIF Interrupt Request TOIF TO INTOIF E ma Bns Delay Capture Clear amp Start Timer Stop Figure 12 12 Input Capture Operation Ext INTO Pin Interrupt Interval Period 01 FFH 014 FFH 01 134 214 66 Figure 12 13 Excess Timer Overflow in Capture Mode December 3 2012 Ver 1 03 SEMICONDUCTOR NBOV MC81F8816 8616 12 4 16 bit Capture Mode 16 bit capture mode is the same as 8 bit capture except In 16 bit mode the bits TxCK1 TxCKO and 16BIT of that the Timer register is running with 16 bits TMI1 TM3 should be set to 1 respectively The clock source of the Timer 0 2 is selected either internal or external clock by bit TxCK2 TxCK1 and TxCKO Bit 7 6 5 4 3 2 1 0 ADDRESS 0D04 TMO i CAPO i TOCK2 TOCK1 i TOCKO i TOCN TOST RESET VALUE 000000 1 X x x x x ADDRESS 0D2u TM1 POL i 16BIT
80. F FF FF FF FF FF AUTO CF12 EET 81F8816 T 4 Figure 31 1 ISP software 134 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 31 2 Basic ISP S W Information The Figure 31 1 is the ISP software based on Windows This software is only supporting devices with SIO In case of not detecting its baudrates an user manually have to se lect specific baudrates Function Description Load File Load the data from the selected file storage into the memory buffer Save File Save the current data in your memory buffer to a disk storage by using the Intel Motorola HEX format Blank Check Verify whether or not a device is in an erased or unprogrammed state Program This button enables you to place new data from the memory buffer into the target device Read Read the data in the target MCU into the buffer for examination The checksum will be displayed on the checksum box Verify Assures that data in the device matches data in the memory buffer If your device is secured a verification error is detected Erase Erase the data in your target MCU before programming it Option Selection Set the configuration data of target MCU The security locking is set with this button Option Write Progam the configuration data of target MCU The security locking is performed with this button 2 Starting address End End address AUTO Following sequence is performe
81. FFCOH DW FUNC A 7 DW FUNC B ICALL ADDRESS AREA The interrupt causes the CPU to jump to specific location where it commences the execution of the service routine The External interrupt 0 for example is assigned to loca tion OFFFAy The interrupt service locations spaces 2 byte interval OFF8y and OFFF9g for External Interrupt 1 and OFFFBy for External Interrupt 0 etc Any area from OFF00g to OFFFFy if it is not going to be used its service location is available as general purpose Program Memory Address Vector Area Memory OFFEOH Watch Timer interrupt Vector Area Watch dog timer interrupt Vector E2 Basic interval Timer interrupt Vector Area Fun AD Converter Interrupt Vector Area EG sec ie k ode Timer Counter 3 Interrupt Vector Area EA limerGoumer2imemuplVedorAa EG A Interrupt i Timer Counter 0 Interrupt Vector Area SPI Interrupt Vector Area UART TXO Interrupt Vector Area UART RXO Interrupt Vector Area vs Eemal interrupt 3 Vecior Area F8 e Fxtemal Interrupt 2 VOGIOFAIGR o s FA Eerste Deri NOE External Interrupt 0 Vector Area E Reset Interrupt Vector Area Figure 8 6 Interrupt Vector Area 35 SEMICONDUCTOR MC81F8816 8616 NBOV Address Program Memory Address PCALL Area Memory OFFOOH PCALL Area 256 Bytes OFFFFy
82. GN 6L ve 8L Ge m 9 9L 1 G S 9 vL 6 L Or zL Ly n ev LL OL lt 6 vy 8 Sr 2 9r 9 lv S gr v 0S Oz LS L CN CO st LO cO O CN CO F LO LO LO LO LO LO LO LO CO CO O CO O UUUUUUUUUUUUo ZEMOTAMNTNOORRO XaLZz2z2z2zz2zn08 5000505505000 999900090900 c yy Doro 0 s 9990 c W LLI LLI LU 9 0 002 184 93S 09 893S V9 693S 29H 0LO3S 9H LLO3S v9H cyo3s 594 6 LOAS 994 936 494 68 936 0 4 9 936 44 21936 22H 8L 93S 4H 6L O3S v2H 0cO3S S H LcO3S 97H cc93S LLY EZOAS v eOAS 56935 December 3 2012 Ver 1 03 ABOV SE ICONDUESOR MC81F8816 8616 5 O z sonco QH 2258899 pean View Q gt X lt X X 44 x x tx t X Vss 150 31 L3 R10 PWM1 T20 R45 XiN 151 30 73 INT2 46 152 29 3 ROG INT1 R47 RESETB 77153 28 7 R05 INTO EC1 COMO 454 27 1 R04 BUZO COM1 7155 26 3 PWMO TOO COM2 156 2514 SEGO R50 COM3 157 81 F8616L 247 SEG1 R51 SEG39 COM4 158 23L3 SEG2 R52 SEG38 COMS 59 22 5 SEG3 R53 SEG37 COM6 r 60 215 SEG4 R54 SEG36 COM7 C61 207 5 55 SEG27 462 19 SEG6 R56 SEG26 ES 18L3 SEG7 R57 SEG25 164 17 SEG8 R60 o lt oo o 9 NO UUUUUUUUUUUUE Uo Wf P CO LO x CO CN ON O LO st
83. L Interrupt Request Flag Low Register RW RW RW 4 3 2 1 SPIIF BITIF WDTIF WTIF Bit 7 6 5 ADDRESS 4 Cir 3 RESET VALUE 000000 B 0 Interrupt not occurred 1 Interrupt Request INTFH Interrupt Flag Register High RW RW R W R W R W Bit 7 6 5 4 3 2 1 ADDRESS 0F4y IFSPI IFRXO IFTXO i RESET VALUE 000 IFSPI SPI Interrupt Flag IFTXO TXO Interrupt Flag 0 No Generation 0 No Generation 1 Generation 1 Generation IFRXO RXO Interrupt Flag 0 No Generation 1 Generation INTFL Interrupt Flag Register Low RW RW RW RW Bit 7 6 5 4 3 2 1 0 ADDRESS 0F5H I2CF i ADCF i WTIF RESET VALUE 00 0000g T2F T2 Interrupt Flag T3F T3 Interrupt Flag I2CF I2C Interrupt Flag ADCF ADC Interrupt Flag WTF WT Interrupt Flag WDTF WDT Interrupt Flag 0 No Generation 0 No Generation 0 No Generation 0 No Generation 1 Generation 0 No Generation 1 Generation 1 Generation 1 Generation 1 Generation Figure 17 2 Interrupt Enable Registers and Interrupt Request Registers December 3 2012 Ver 1 03 83 MC81F8816 8616 17 1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an in struction Interrupt acceptance sequence requires 8 fosc 2 us at fuAIN 4MHZ after the completion of the current in struction execution The interrupt ser
84. Port turn off buzzer 1 BUZO port turn on buzzer 2 D st COMPARATOR R04 BUZO PIN BUZO PSRO 4 Figure 16 1 Buzzer Driver Example 2 5kHz output at 4MHz LDM LDM ROFUNC XXX1_XXXXB BUZR 1001_1000B December 3 2012 Ver 1 03 X means don t care 79 MC81F8816 8616 Buzzer Output Frequency When main frequency is 4MHz buzzer frequency is SEMICONDUCTOR shown as below Frequency Output kHz Frequency Output kHz BUZR BUZR 7 6 BUZR BUZR 7 6 5 0 5 0 00 01 10 11 00 01 10 11 00 250 000 125 000 62 500 31 250 20 7 576 3 788 1 894 0 947 01 125 000 62 500 31 250 15 625 21 7 353 3 676 1 838 0 919 02 83 333 41 667 20 833 10 417 22 7 143 3 571 1 786 0 893 03 62 500 31 250 15 625 7 813 23 6 944 3 472 1 736 0 868 04 50 000 25 000 12 500 6 250 24 6 757 3 378 1 689 0 845 05 41 667 20 833 10 417 5 208 25 6 579 3 289 1 645 0 822 06 35 714 17 857 8 929 4 464 26 6 410 3 205 1 603 0 801 07 31 250 15 625 7 813 3 906 27 6 250 3 125 1 563 0 781 08 27 778 13 889 6 944 3 472 28 6 098 3 049 1 524 0 762 09 25 000 12 500 6 250 3 125 29 5 952 2 976 1 488 0 744 0A 22 727 11 364 5 682 2 841 2A 5 814 2 907 1 453 0 727 0B 20 833 10 417 5 208 2 604 2B 5 682 2 841 1 420 0 710 0C 19 231 9 615 4 808 2 404 2C 5 556 2 778 1 389 0 694 00 17 857 8 929 4 464 2 232 2D 5 435 2 717 1 359 0 679 16 667 8 333 4 167 2 083 2 5 319 2 660 1 330 0 665 15 625 7 813 3 906 1 953 2F 5 208 2 6
85. R3 n M UU E pps 9 Tu Pcp x 407 8 gt lt ud S 7 6 5 4 3 2 1 0 gt TIME Interrupt period Pcp x n 1 Timer 0 1 2 3 TOIF T1IF T2IF T3IF Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 12 6 Counting Example of Timer Data Registers 70 123 TORO TORI TORA TORN eee disable enable clear amp start X i y stop E _ 1 gt FE I 7 gt TIME Timer 0 TOIF Interrupt Occur interrupt Occur interrupt T 0 3 ST Start amp Stop T 0 3 ST 0 T 0 3 ST 1 T 0 3 CN Control count T 0 3 CN 20 T 0 3 CN 1 Figure 12 7 Timer Count Operation 12 2 16 Bit Timer Counter Mode The Timer register is running with 16 bits A 16 bit timer The clock source of the Timer 0 is selected either internal counter register are increased from 0000 until it or external clock by bit TOCK2 TOCK1 and TOCKO matches TDRI and then resets to 0000 The match output generates Timer 0 interrupt not Timer 1 in terrupt In 16 bit mode the bits TICK 1 TI CK0 and 16BIT of TMI December 3 2012 Ver 1 03 61 SEMICONDUCTOR MC81F8816 8616 NBOV should be set to 1 respectively Bit 76 5 2 1 O0 ADDRESS TMO i CAPO TOCK2 TOCK1 TOCKO TOCN RESET VALUE 000000 0 X X x x x ADDRESS 002 TM1 POL i 16BIT PWMOE CAP1 T1CK1 T1CN RESET VALUE 0 00008 X The value 0 or
86. RL The ADCRH 7 6 is also used as ADC clock source selection bits The ADCM register shown in Figure 15 2 controls the operation of the A D converter module The port pins can be configured as analog inputs or digital I O To use analog inputs each port should be assigned analog input port by setting R2IO direction register as input mode and setting ADS 3 0 to select the corresponding channel The self bias check reference provides fixed voltage typi cal 1 185V tolerance to be defined which can be the in put of ADC when setting ADS 3 0 to 1111b This feature can be used to check the voltage of VDD pin The BOD ENB and AD REFB of BODR register should be set to 0 for using self bias check reference ADEN J AN3 AN Self Bias Check Reference ADS 3 0 1111b BOD ENB 0 REFB 0 ADS 3 0 ADCM 5 2 1 Self Bias check reference can operate normally when BOR ENB BODR 7 and AD REFB BODR 5 bit is set to 0 enable Resistor Ladder Circuit 10 bit ADCR ADCRH ADCRL 8 bit 10 ADC Result Register SEMICONDUCTOR The processing of conversion is start when the start bit ADST is set to 1 After one cycle it is cleared by hard ware The register ADCRH and ADCRL contain the result 10bit of the A D conversion If the ADC is set to 8 bit mode ADCS bit of ADCRH is 1 ADCRL contains the
87. RXIF Rx interrupt Parity Addition TXIF Tx interrupt ACK R11 Baud Rate O Generator 2 to 27 110 Figure 21 1 UART Block Diagram December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 RECEIVE RXE ACK fx 2 fx 22 5 bit counter fx 23 fx 24 HC fx 25 TX CLK 112 D 297 Divider fx 2 1 2 match BRGCR RX CLK Divider T T 7 T i TPS2 TPS1 TPSO MDL3 MDL2 MDL1 MDLO 5 bit counter lt TXE SEND S Data Bus 5 Figure 21 2 Baud Rate Generator Block Diagram 21 1 Asynchronous Serial Interface Configuration The asychronous serial interface UART consists of the follow ing hardware Item Configuration Transmit shift register TXSR Register Receive buffer register RXBR Genta Asynchronous serial interface mode register ASIMR register Baudrate generator control register BRGCR Table 21 1 Serial Interface Configuration Transmit Shift Register TXSR This is the register for setting transmit data Data written to TXSR is transmitted as serial data When the data length is set as 7 bit bit 0 to 6 of the data written to TXSR are transferred as transmit data Writing data to TXSR starts the transmit operation TXSR can be written by an 8 bit memory manipulation instruction It cannot be read Note Do not write to TXSR during a
88. SLEEP Mode niet rede eie ees 117 STOP MOdeG rnc eoe t tags 118 24 OSCILLATOR CIRCUIT 122 25 PIL u u u u u 123 External PLL Circuit 124 26 RESET 202440 aaa ssskasskspaansnaskaasasakakakaka 125 External Reset Input 125 Power On 126 Brown out Detector 126 Watchdog Timer Reset 126 27 Brown out Detector BOD 127 1 MC81F8816 8616 28 Osillation Noise Protector 129 29 FLASH PROGRAMMING SPEC 131 FLASH Configuration Byte 131 FLASH Programming 131 30 EMULATOR EVA BOARD SETTING 133 31 IN SYSTEM PROGRAMMING 134 Getting Started Installation 134 Basic ISP S W Information 135 SEMICONDUCTOR Hardware Conditions to Enter the ISP Mode 136 Sequence to enter ISP mode user mode 137 USB SIO ISP Board 138 A INSTRUCTION ii Terminology ii Instruction Map iii Instruction Set uuu ete V MASK ORDER
89. SRO to ec 1 272 6 bit buzzer counter is cleared and start the counting by writing signal to the register BUZR It is increased from 00g until it matches with BUR 5 0 Also it is cleared by counter overflow and count up to out put the square wave pulse of duty 50 The bit 0 to 5 of BUZR determines output frequency for buzzer driving BUZR 5 0 is initialized to after reset Note that BUZR is a write only register Frequency calcu lation is following as shown below n n RNC BUZ 9x DivideRatio x BUZR 5 0 1 The bits BUCK1 BUCKO of BUZR select the source clock from prescaler output feuz Buzzer frequency fxiN Oscillator frequency Divide Ratio Prescaler divide ratio by BUCK 1 0 BUZR 5 0 Lower 6 bit value of BUZR Buzzer control data BUZR Buzzer Driver Register w w w Ww Bit 7 6 5 4 3 BUR4 BUCK1 BCUKO BURS BUR3 Ww 2 BUR2 w 1 0 ADDRESS BUR1 BURO RESET VALUE FFy Bit manipulation is not available BUCK lt 1 0 gt Buzzer Clock Source 00 23 01 24 10 25 11 4 26 Port Selection Register 0 PSRO INTOE BUZO XIN L BUCK lt 1 0 gt COUNTER 6 bit BUZR 5 0 6 bit BUR 5 0 Buzzer Control Data ADDRESS 0AA PWMOE RESET VALUE 0000 00 BUZO Buzzer Output 0 R04
90. Sleep mode MC81F8816 8616 Sleep mode is entered by writing into Stop and Sleep Control Register SSCR and STOP mode is entered by writing SAg into SSCR and then executing STOP in struction Stop and Sleep Control Register ADDRESS 0 9 RESET VALUE 00H w to enable STOP Mode 5 to enter SLEEP Mode OFy note1 To get into STOP mode SSCR must be enabled just before STOP instruction At STOP mode SSCR register value is cleared automatically Figure 23 1 SLEEP Mode Register XiN Interrupt Set bit 0 of MN Oscillator u Internal CPU Clock IL TL ILTLILTLUILI Normal Operation Stand by Mode Normal Operation gt Figure 23 2 Sleep Mode Release Timing by External Interrupt December 3 2012 Ver 1 03 117 MC81F8816 8616 ABOV SEMICONDUCTOR Internal CPU Clock RESET Set bit 0 of SMR 1 Counter u Normal Operation Stand by Mode Release Clear amp Start 62 5ms Normal Operation gt at 4 19MHz by hardware 256 ST fMAIN 1024 Figure 23 3 SLEEP Mode Release Timing by RESET pin 23 2 STOP Mode Note If the STOP mode is used in the program BOD function should be disabled in the initial routine of soft ware For applications where power consumption i
91. Stack Pointer Data PC Circuit To b Memory Power Supply LCD Display Program Interrupt Controller Memory Memory RESET System controller 1 Data Table System 8 bit Basic Clock Controller _ Interval Timer Timing generator XIN PC Xour High freq clock ss Dog m EE 10 bit pwn rah SXDUT Low freq Generator Converter Timer Counter PLLC f 1 1 1 L xp T iL Buzzer nS R7 R6 R5 R4 R2 i R1 Ro Driver BOD Jj 8 8 8 R70 R60 R50 R40 R20 ANO R10 PWM1 T2O R00 PWMO TOO R71 R61 R51 R41 INT3 R21 AN1 R11 ACK SCK R01 ECO R72 R62 R52 R42 R22 AN2 R12 TX0 SOUT R02 R73 R63 R53 R43 SXIN R23 AN3 R13 RX0 SI R03 R74 R64 R54 R44 SXOUT R24 R14 R04 BUZO R75 R65 R55 R45 XIN R25 AN5 R15 R05 EC1 INTO R76 R66 R56 R46 XOUT R26 6 R16 SDA ROG INT R27 AN7 R47 SCL R77 R67 R57 R47 RESETB R07 INT2 6 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 2 2 MC81F8616Q 64 pin package RESET Common Drive Output COMO COM7 COMO COM3 Segment Drive Output SEGO SEG27 SEGO SEG31 BIAS selection circuit Power Supply Circuit System controller Internal Resistor E for LCD Bias LCD Controller Driver MC81F8816 8616 System Clock Controller PSW A Stack Pointer PC SG Program Interrupt Controller Mem
92. The MC81F8816 8616 has two high speed PWM Pulse Width Modulation function which shared with Timerl Timer3 In PWM mode RO0 PWMO and R10 PWM pins operate as a 10 bit resolution PWM output port For this mode the bit PVMO 1 O of Port Mode Reg ister RO 1 FUNC and the bit PWMO 1 E of 1 3 mode register TM 1 should be set to 1 respectively The period of the PWM output is determined by the T1 3 PPR T1 3 PWM Period Register and T1 3 PWHR 3 2 bit3 2 of T1 3 PWM High Register 68 In addition 16 bit Compare output mode is available also This pin output the signal having a 50 50 duty square wave and output frequency is same as below equation Dy fon eu COMP 9x PrescalerValue x TDR 1 and the duty of the PWM output is determined by the T1 3 PDR T1 3 PWM Duty Register and T1 3 PWHR 1 0 bit1 0 of T1 3 PWM High Register The user can use PWM data by writing the lower 8 bit pe riod value to the T1 3 PPR and the higher 2 bit period val ue to the T1 3 PWHR 3 2 And the duty value can be used with the T1 3 PDR and the T1 3 PWHR 1 0 in the same way The T1 3 PDR is configured as a double buffering for December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 glitchless PWM output In Figure 12 17 the duty data 1s transferred from the master to the slave when the period data matched to the counted value i e at the beginning of next duty cycle The bit POLO 1
93. Trap Reset Selection 0 Enable Adress Fail Reset Basic Interval Timer source clock select 1 Disable Adress Fail Reset 000 23 001 fmain 24 SUB Clock Selection 010 faint2 1 main clock frequency 0 Deselect Sub Clock 011 fMAIN 25 1 Select Sub Clock 100 fMAINT27 101 28 Watch Dog Timer Enable 410 fain 22 0 Operates as a 7 bit Timer 910 1 Enable Watchdog Timer 111 fain 2 Caution Clear bit auuon 0 Normal operation free run 1 Clear 8 bit counter BITR to 0 This bit becomes 0 automatically Both register are in same address after one machine cycle when write to be a CKCTLR when read to be a BITR 7 6 5 4 3 2 1 0 ADDRESS INITIAL VALUE 004 BITR 8 BIT BINARY COUNTER Figure 11 2 BITR Basic Interval Timer Mode Register Example 1 Interrupt request flag is generated every 8 192ms at 4MHz DM CKCTLR 0CH SET1 BITE EI 54 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 12 TIMER COUNTER Timer Event Counter consists of prescaler multiplexer 8 bit timer data register 8 bit counter register mode register input capture register and Comparator as shown in Figure 12 4 And the PWM high register for PWM is consisted separately The timer counter has seven operating modes 8 Bit Timer Counter Mode 8 Bit Capture Mode 8 Bit Compare Output Mode 16 Bit Timer Counter Mode 16 Bit Capture Mode
94. Vpp 4 5V lon1 1 6mA Vpp 0 3 Output High Voltage R5 R7 Vpp 4 5V 1 2 1 6 Vpp 1 0 V SEG0 39 0 3 1 E VOH3 Vpp 4 5V VCL3 0 3V 151 VoL1 RO R4 Vpp 4 5V loi 471 6mA 0 35 Output Low Voltage VoL2 R5 R7 Vpp 4 5V lo_2 1 6mA 0 4 V Vois SEG0 39 0 3 0 12 OLS Vpp 4 5V VCL3 0 3V loi 3715pA i Input High E Leakage Current All input pins including R5 R7 Vin Vpp 1 Input Low Leakage Current liL All input pins including R5 R7 ViN Vss 1 Vpp BODR lt 2 0 gt 000 2 0 15 2 0 2 0 15 V Brown out Detector Vpp BODR lt 2 0 gt 011 2 711596 2 7 2 711596 V Vpp BODR lt 2 0 gt 110 3 611596 3 6 3 611596 POR Power on m Reset Level VrPoR Ta 25 C 2 0 2 4 2 8 V VDD Start Voltage VsrART 25 Vss 0 3 V Config Read i 3 Vconfig Tvpp 40ms V VsrART Vss 1 8 V Voltage VDD rising Time Vpp Ta 25 C 40 ms V Hysteresis 2 RESET 0 3 ECO 1 Vpp 5V 0 2Vpp 0 8Vpp V Pull up Current Ipu RO R4 Vpp 3 0V 20 60 Curentdissipationin pp vop fain 12MHz Vpp 5 5V fsuB 0 5 15 active mode C T di sipationi mA urrent dissipation in E IsLEEP fmain 12MHz Vpp 5 5V fsug 0 E 2 4 sleep mode Current dissipation in subactive fMAIN Off Vpp 5V fsug 32 768kHz 67 sub active mode Isubsleep fMAIN Off Vpp 5V fsup 32 768kHz 32
95. Y Y Y X X X X 00 00 00 00 00 0 LELELELELELELELELELEL ELTE LL EL E KO LO t N O O r O LO lt cO cO cO cO CO CO cO cO cO CN CN N N Ly vz ev ez ec v Lz Sr 02 9 6l 9 G n 6v 9 09 LS 2 vL zg el 55 LL 21 rS LL 99 co OL 95 6 29 8 89 n 66 9 09 S L9 v 29 9 2 v9 O LO cO 00 O gt O z QN LO CO ODS CO O O r r r r UUHHUUUUUHHUUUUU Se SSS SSS SSB 8x400000909990999 9 999990900 0 DONG m c9 co 00 5000 c WW LLI LLI Lu 09 00 00 0 UUUUUUUUUUUUUUUUUUUUUUUU 18H 93S 095 893 1954 6935 9 01998 9MH LLO3S v9uH cyo3s S9H y 93s 99 7955 Z9Y SLOAS 024 91 93S VZH ZVO3S 81998 2H 6LO3S 713 0693 SZH Vc9O3S 97H cc93S v OAS 50945 90945 212918 80945 6693 06945 MOSPIOVIVLMH LNOS XL ZLY IS XU ELY vlad Vas 9ly TOS ZLY ONV OZS LNV L 3 VNV VOH ru NIXS evd LNOXS vy SSA 64MQFP Top View LTECLELELELTLELD ELTEELEL DL EL TL EL TL 8 5 8 E Q E 8588 2022200 Cee rreg S G 930606 Or xvci 0 x o000 0000 O O O O O LL LL LLI WU LLI LLI t X X 00 0202 0000 00 CO CN O O LO N O CN N N N GN
96. after STOP instruction at least two or more NOP in struction should be written as shown in example below Example Reset LDM 1100 0000B Main LDM 0000 1111B STOP December 3 2012 Ver 1 03 NOP NOP The Interval Timer Register CKCTLR should be initial ized by software in order that oscillation stabilization time should be longer than 20ms before STOP mode In case of releasing the STOP mode The exit from STOP mode is using hardware reset or exter nal interrupt watch timer ortimer interrupt ECO To release STOP mode corresponding interrupt should be enabled before STOP mode Specially as a clock source of Timer Event counter ECO pin can release it by Timer Event counter Interrupt re quest Reset redefines all the control registers but does not change the on chip RAM External interrupts allow both on chip RAM and Control registers to retain their values Start up is performed to acquire the time for stabilizing os cillation During the start up the internal operations are all stopped 119 SEMICONDUCTOR MC81F8816 8616 ABOV Oscillator Xin pin n lt Internal Clock External Interrupt STOP Instruction a Executed n 3 BIT Counter tst gt 20ms n by software Before executing Stop instruction Basic Interval Timer must be set properly by software to get stabilization time which is l
97. ait the SPISF is December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 changed to 1 for completion check Note When external clock is used the frequency should be less than 1MHz and recommended duty is 50 If both transmission LDM SPIR 0AAh set tx data mode is selected and transmission is performed simultaneously 5 0011 1100b set SPI mode error may be occur NOP ee SPIM 0011 1110b SPI Start SPI WAIT NOP BBS SPIST SIO WAIT wait first edge BBC SPISF SIO WAIT wait complete 19 3 The Method to Test Correct Transmission Serial Interrupt Service Routine 1 SPIE 0 Abnormal Write SPIM 1 Normal Operation Overrun Error SPIE Interrupt Enable Register Low IENL Bit7 SPIIF Interrupt Request Flag Register Low IRQL Bit7 Figure 19 5 Serial IO Method to Test Transmission December 3 2012 Ver 1 03 101 MC81F8816 8616 20 INTER IC COMMUNICATION I2C Generation of clock signals on the I2C bus is always the respon sibility of master devices each master generates its own clock signals when transferring data on the bus Bus clock signals from a master can only be altered when they are stretched by a slow slave device holding down the clock line or by another master when arbitration occurs Both SDA and SCL are bi directional lines connected to a pos iti
98. al pull ups that are independently connected or disconnected by R2PU address 7 The control reg isters for R2 are shown as below Note R21O R2PU and P2OD are write only registers They can not be read and can not be accessed by bit ma 48 ABOV SEMICONDUCTOR nipulation instruction Do not use read or read modify write instruction Use byte manipulation instruction Note The R25 and R27 are not supported in the MC81F8616Q ADDRESS 0C4y R2 Data Register RESET VALUE 000000008 R2 R27 R26i R25 i R24 i R23 i R22 i R21 R20 ADDRESS 0C5H RESET VALUE 000000008 R2 Direction Register Port Direction 0 Input 1 Output R2 Pull up ADDRESS 0A7H Selection Register RESET VALUE 000000008 R2PU Pull up select 0 Without pull up 1 With pull up R2 Open Drain ADDRESS 2 Selection Register RESET VALUE 000000005 Open Drain select 0 No Open Drain 1 Open Drain A D Converter 4 ADDRESS 2 Mode Register RESET VALUE 00000001 ADCM ADENADCK ADS3 0 2 0 1 0 ADF Analog input of A D converter is selected by ADSO ADS2 R4 Port R4 is a 8 bit CMOS bidirectional I O port address 8 Each I O pin can independently used as an input or an out put through the RAIO register address 0 9 R4 has internal pull ups that is independently connected or disconnected by R4PU The control registers for R4 are shown below
99. and the program execution starts at the vec tor address stored at FFFEg December 3 2012 Ver 1 03 A connection for normal power on reset is shown in Fig ure 26 2 Vpp VDD 47kQ Reset IC gt gt 0 1uF MCU GND GND Figure 26 2 Normal Power on Reset Circuit 125 MC81F8816 8616 System Clock RESET ADDRESS BUS DATA BUS q gt ABOV SEMICONDUCTOR LLIPI TIT Stabilization Time tsr 65 5mS at 4MHz MAIN PROGRAM RESET Process Step 1 tet x256 ST Fain 1024 Figure 26 3 Timing Diagram of RESET 26 2 Power On Reset The on chip POR circuit holds down the device in RESET until Vpp has reached a high enough level for proper op eration It will eliminate external components such as reset IC or external resistor and capacitor for external reset cir cuit In addition that the RESET pin can be used to normal input port R47 by setting POR and R47EN bit of the Configuration option area 20FFH in Flash programming When the device starts normal operation its operating 26 3 Brown out Detector Refer to 27 Brown out Detector BOD 26 4 Watchdog Timer Reset Refer to 14 WATCH DOG TIMER 126 parmeters voltage frequency temperature etc must be met Note When POR option is checked and RA7EN option is not checked RESET R47 pin acts as ex
100. ave Address Register I2CAR R W 100000000 byte 009AH PLL Control Register XPLLCR R W 100000000 byte 009BH PLL Data Register XPLLDAT R W 100000000 byte 009EH WT Read Data Register WTRH R 0000000 byte 00A0H RO Open Drain Control Register ROOD 00000000 byte 00A1H R1 Open Drain Control Register R1OD W 00000000 byte 00A2H R2Open Drain Control Register R20D W 00000000 byte 00A4H R4Open Drain Control Register R40D W 00000000 byte 00A5H RO Pull up Register ROPU W 00000000 00A6H R1 Pull up Register R1PU 00000000 byte R2 Pull up Register R2PU 00000000 byte 00A9H R4 Pull up Register R4PU W 00000000 byte 00AAH Port Selection Register 0 PSRO W 0000 00 byte Port Selection Register 1 PSR1 W 1 0 0 0 byte OOACH R5 Port Selection Register RSPSR R W 11111111 byte bit O0ADH R6 Port Selection Register R6PSR R W 1111 11 11 byte bit OOAEH R7 Port Selection Register R7PSR R W 1111 11 11 byte bit OOAFH R8 Port Selection Register R8PSR R W 1111 11 11 k d 00BOH R7 Data Register R7 R W 00000000 byte 00B2H LCD Control Register LCR R W 00000000 byte bit 00B3H LCD BIAS Control Register LBCR R W 01111000 byte bit 00B4H R7 Direction Register R7IO 00000000 byte 00B6H SPI Mode Control Register SPIM R W 100000001 byte 00B7H SPI Data Shift Register SPIR R W byte Table 8 1 Control Registers December 3 2012 Ver 1 03 39 SEMICONDUCTOR MC81F8816 8616 ABOV
101. by any other result MC81F8816 8616 MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when g 1 page is addressed by RPR LSB RESET VALUE 00 CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG BRK FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 8 3 PSW Program Status Word Register Interrupt disable flag I This flag enables disables all interrupts except interrupt caused by Reset or software BRK instruction All inter rupts are disabled when cleared to 0 This flag immedi ately becomes 0 when an interrupt is served It is set by the EI instruction and cleared by the DI instruction Half carry flag H After operation this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU This bit can not be set or cleared except CLRV instruction with Overflow flag V Break flag B This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad dress Direct page flag G This flag assigns RAM page for direct addressing mode In December 3 2012 Ver 1 03 the direct addressing mode addressing area is from zero page 00g to OFFy when this flag is 0 If it is set to 1 addressing area is assigned by RPR register address OF3g It is set by SETG instruction and cleared by CLRG Overflow flag V This flag is set t
102. count Usually a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received except when the mes sage starts with a CBUS address When a slave doesn t ac knowledge the slave address for example it s unable to receive or transmit because it s performing some real time function the data line must be left HIGH by the slave The 106 master can then generate either a STOP condition to abort the transfer or a repeated START condition to start a new transfer If a slave receiver does acknowledge the slave ad dress but some time later in the transfer cannot receive any more data bytes the master must again abort the transfer This is indicated by the slave generating the not acknowl edge on the first byte to follow The slave leaves the data line HIGH and the master generates a STOP or a repeated START condition If a master receiver is involved in a transfer it must signal the end of data to the slave trans mitter by not generating an acknowledge on the last byte that was clocked out of the slave The slave transmitter must release the data line to allow the master to generate a STOP or repeated START condition December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START condition wd X XX not acknowledge acknowledge clock pulse for acknowledgement Fig
103. cteristics 23 AC Characteristics 25 Serial I O Characteristics 27 Typical Characteristics 28 8 MEMORY ORGANIZATION 32 Registers 32 Program Memory a 35 Data Memory 222 38 Addressing Mode 42 9 PORTS quas nni ee 46 Registers for Ports 46 Ports Configuration 47 10 CLOCK GENERATOR 51 11 BASIC INTERVAL TIMER 53 12 TIMER COUNTER enne 55 8 Bit Timer Counter Mode 59 16 Bit Timer Counter Mode 61 8 Bit Capture Mode 63 16 bit Capture Mode 67 8 Bit 16 Bit Compare Output Mode 68 PWM Mode tete 68 13 WATCH TIMER eene 72 14 WATCH DOG TIMER 74 15 ANALOG TO DIGITAL CONVERTER 76 December 3 2012 Ver 1 03 MC81F8816 8616 16 BUZZER OUTPUT FUNCTION 79 17 INTERRUPTS nnn trn 81 Interrupt Seque
104. ction the main frequency clock oscillation stops and the STOP mode is invoked But sub frequency clock oscil lation is operated continuously 116 SEMICONDUCTOR After the STOP operation is released by reset the opera tion mode is changed to Main active mode The methods of release are RESET Key scan interrupt Watch Timer interrupt Timer Event counterl ECO pin and External Interrupt For more details see 23 2 STOP Mode on page 118 Note In the STOP and SLEEP operating modes the pow er consumption by the oscillator and the internal hardware is reduced However the power for the pin interface de pending on external circuitry and program is not directly associated with the low power consumption operation This must be considered in system design as well as interface circuit design December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 23 POWER DOWN OPERATION MC81F8816 8616 have 2 power down mode In power down mode power consumption is reduced considerably in Battery operation that Battery life can be extended a lot 23 1 SLEEP Mode In this mode the internal oscillation circuits remain active Oscillation continues and peripherals are operate normally but CPU stops The status of all Peripherals in this mode is shown in Table 23 1 Sleep mode is entered by writing into SSCR address 0 9 It is released by RESET or all interrupt To be released by interrupt interrupt should be enabled before
105. ction Set Arithmetic Logic Operation No Mnemonic 2 En Operation 422 1 ADC imm 04 2 2 Add with carry 2 ADC dp 05 2 3 A A M C 3 ADC dp X 06 2 4 4 ADC abs 07 3 4 NV H ZC 5 ADC abs Y 15 3 5 6 ADC dp X 16 2 6 7 ADC dp Y 17 2 6 8 ADC X 14 1 3 9 AND imm 84 2 2 Logical AND 10 AND dp 85 2 3 A lt A A M 11 AND dp X 86 2 4 12 AND abs 87 3 4 N 2 13 AND abs 95 3 5 14 AND dp X 96 2 6 15 AND dp Y 97 2 6 16 AND X 94 1 3 x ASLA og 1 2 Arithmetic shift left 18 ASL dp 09 2 4 76543210 N ZC 19 ASL dp X 19 2 5 lt eiecece lt 0 20 ASL abs 18 3 5 21 CMP imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp X 46 2 4 24 labs 47 3 4 Compare accumulator contents with memory contents 26 25 labs Y 55 3 5 A M 26 CMP dp X 56 2 6 27 CMP dp Y 57 2 6 28 CMP X 54 1 3 29 CMPX imm 5E 2 2 Compare X contents with memory contents 30 CMPX dp 6C 2 3 X M N ZC 31 CMPX abs 7C 3 4 32 CMPY imm 7E 2 2 Compare Y contents with memory contents 33 CMPY dp 8C 2 3 Y M N ZC 34 CMPY abs 9C 3 4 35 COM dp 2C 2 4 TS Complement dp dp N 7 36 DAA Not supported 37 DAS Not supported December 3 2012 Ver 1 03 ABOV MC81F8816 8616 SEMICONDUCTOR No Mnemonic ix p o ds Operation 38 DEC 8 1 2 Decrement 39 DEC dp AQ 2 4 M M 1 40 D
106. d 1 Erase 2 Program 3 Verify 4 Option Write Auto Option Write If you want to program the option config value after pressing the Auto Button chek this button Auto Show Option If you check this button the option config dialog is displayed whenever pressing the Auto button Checksum Display the checksum Hexdecimal after reading the target device Select Device Select target device You need to select a device before turning on the target VDD Update Buffer Update buffer by pressing this button Fill Fill the selected area with a data Goto Display the selected page Serial ID To program the serial ID Note MCU configuration value is erased after operation It Table 31 1 ISP Function Description sirable must be configured to match with user target board Other wise it is failed to enter ISP mode or its operation is not de December 3 2012 Ver 1 03 135 MC81F8816 8616 NBOV SEMICONDUCTOR 31 3 Hardware Conditions to Enter the ISP Mode The boot loader can be executed by holding ALE high RE SET Vpp as 9V SCLK SDA D x 9 lt 5 Vpp 5V 9 T Nx T Si Ln L 1 5 a Xour _ gt gt 9V L al ISP Vp RESET VeP Vpp 45V DD MC81F8816 8616Q RO4 ALE2 O User target reset circuitry USB SIO ISP B D 10 pin connector ODOC U PCB Top View RESETW OL DOCO w b
107. d the entry address of the interrupt service program An interrupt request is not accepted until the I flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced 84 When nested interrupt service is required the I flag should be set to 1 by instruction in the interrupt service program In this case acceptable interrupt sources are se lectively enabled by the individual interrupt enable flags Saving Restoring General purpose Register During interrupt acceptance processing the program counter and the program status word are automatically saved on the stack but accumulator and other registers are not saved itself If necessary these registers should be saved by the software Also when multiple interrupt ser vices are nested it is necessary to avoid using the same data memory area for saving registers December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR The following method is used to save restore the general purpose registers Example Register saving INTxx PUSH A SAVE ACC PUSH X SAVE X REG PUSH Y SAVE Y REG interrupt processing POP Y RESTORE Y REG POP X RESTORE X REG POP A RESTORE ACC RETI RETURN 17 2 BRK Interrupt Software interrupt can be invoked by BRK instruction which has the lowest priority order Interrupt vector address of BRK is shared with the
108. data in Direct page ADC AND CMP EOR LDA OR SBC STA Example G 0 10 1625 ADC 25g4X 35H 05 lt 36H EO 1 1 0E0054 data 4 25 X 10 354 16 25 LI A data C S A kes x December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR Y indexed indirect dp Y Processes memory data as Data assigned by the data dp 1 dp of 16 bit pair memory paired by Operand in Di rect page plus Y register data ADC AND CMP EOR LDA OR SBC STA Example G 0 10 1725 ADC 25g Y Ras RENE 25H 05 26 EO 1 10 0 015 0 015 data 17 25 A data C SA k u December 3 2012 Ver 1 03 MC81F8816 8616 Absolute indirect abs The program jumps to address specified by 16 bit absolute address JMP Example G 0 1F25E0 JMP 0 025 PROGRAM MEMORY ssp D n ED gt 0E0254 25 0 026 E7 J J jump to 1 address 0E7254 25 1F 25 EO a 45 MC81F8816 8616 9 PORTS The MC81F8816 8616 have seven I O ports LCD seg ment ports RO R2 R4 R50 SEGO0 R77 SEG23 SEG24 SEG35 and LCD common ports SEG39 COMA SEG36 COM7 COM0 COM3 These ports pins may be multiplexed with an alternate 9 1 Registers for Ports P
109. data until it has performed some other function for example servicing an internal interrupt it can hold the clock line SCL LOW to force the master into December 3 2012 Ver 1 03 a wait state Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL In some cases it s permitted to use a different format from the I2C bus format for CBUS compatible devices for example A message which starts with such an address can be termi nated by generation of a STOP condition even during the transmission of a byte In this case no acknowledge is gen 105 MC81F8816 8616 erated SEMICONDUCTOR SE Oy acknowledgement signal from slave byte complete interrupt within device clock line held low while interrupts are serviced me Pe acknowledgement signal from receiver P Sr zi S START or STOP or repeated START repeated START condition Condition Figure 20 4 Data transfer on I2C bus 20 4 Acknowledge Data transfer with acknowledge is obligatory The ac knowledge related clock pulse is generated by the master The transmitter releases the SDA line HIGH during the acknowledge clock pulse The receiver must pull down the SDA line during the acknowledge clock pulse so that it re mains stable LOW during the HIGH period of this clock pulse see Figure 20 5 Of course set up and hold times must also be taken into ac
110. e 9 1 Example of port I O assignment Pull up Control Registers The RO R1 R2 and R4 ports have internal pull up resis tors Figure 9 2 shows a functional diagram of a typical 46 SEMICONDUCTOR function for the peripheral features on the device Note SEG28 SEG35 are not not supported in MC81F8616Q 64pin pull up port It is connected or disconnected by Pull up Control register RnPU The value of that resistor is typi cally 100kO Refer to DC characteristics for more details When a port is used as key input input logic is firmly ei ther low or high therefore external pull down or pull up resisters are required practically The MC81F8816 8616 have internal pull up it can be logic high by pull up that can be able to configure either connect or disconnect indi vidually by pull up control registers RnPU When ports are configured as inputs and pull up resistor is selected by software they are pulled to high VDD i PULL UP RESISTOR Z PORT PIN i ees Pull up control bit 0 Disconnect 1 Connect Figure 9 2 Pull up Port Structure Open drain port Registers The RO R1 R2 and R4 ports have open drain port resistors ROOD R4OD Figure 9 3 shows an open drain port configuration by con trol register It is selected as either push pull port or open drain port by ROOD RIOD R2OD and RAOD PORT PIN Open drain port selection bit GND 0 Pu
111. e corre sponding bit of PSRI Main oscillation input output and reset pin can be used as normal I O ports R46 R45 and normal input port R47 by selecting configuration options in flash writing Sub oscil lation input output pin can be used as normal I O ports by December 3 2012 Ver 1 03 MC81F8816 8616 writing 1 to the SCKD bit of the LCR register Port pin Alternate function R40 R41 INT3 External Interrupt 3 Request input R42 R43 5 R44 SXout R45 XIN R46 XOUT R47 RESET Note R4PU P4OD PSR 1 write only regis ters They can not be read and can not be accessed by bit manipulation instruction Do not use read or read modify write instruction Use byte manipulation instruction R5 Ports R5 is an 8 bit CMOS bidirectional I O port address OCA p Each I O pin can independently used as an input or an output through the R5IO register address R5 is multiplexed with LCD segment output SEGO SEG7 which can be selected by writing appropriate value into the RSPSR address ADDRESS 0CAH R5 Data Register RESET VALUE 000000008 R5 R57 R56 R55 R54 R53 R amp 2 R51 R50 ADDRESS RESET VALUE 000000008 R5 Direction Register Port Direction 0 Input 1 Output ADDRESS RESET VALUE 111111118 R5 LCD Port Selection Register R5PSR R5PS7 5 6 R5PS5 R5PS4 R5PS3 R5PS2 R5PS1 R5PS0
112. eei segel UT AUT ISP_mode 1 If other signals affect SIO communiction in ISP mode disconnect these pins by using a jumper or a switch 2 If ALE is sharing with other function Toggle between ISP and user mode Caution The ALE is only used for the ISP entry connecting the ALE to Vss into user mode is more effective than connecting it to to prevent malfunction entering ISP mode by noise If the Vpp is changed from 0 to 9V Vdd 5V by a noise the ISP mode could be enabled Please make the ALE low to prevent unexpected entering the ISP mode from the user mode Figure 31 2 ISP Configuration 136 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 31 4 Sequence to enter ISP mode user mode Reset ISP mode e H lt min 10us 64ms 4MH Vpp J Vpp ALE logic high Sequence to enter user mode from ISP mode Figure 31 3 Timing diagram to enter the ISP mode Sequence to enter ISP mode from user mode December 3 2012 Ver 1 03 137 MC81F8816 8616 ABOV 31 5 USB SIO ISP Board The ISP software and hardware circuit diagram are provid To get a ISP B D contact to sales department The follow ed at www abov co kr ing circuit diagram is for reference use Connect USB mini type cable JSB SIO ISP B D 10 pin connector USB SIO ISP B D 10 pin Connector PCB Top View Figure 31 4 ISP board supplied by ABOV 138 Decembe
113. eleminates low level detection signal less than 32us BOD result can be selected by SYS_BOD 1 0 of LBCR register When SYS BOD 1 0 is set to 00 BOD gener ates reset singnal If 1 0 is set to 10 it gen erates freeze mode signal and CPU freeze until the VDD voltage returns to regular level The self bias check reference which can be used for calcu lating VDD voltage can be activated by setting the AD_REFB bit to 0 and BOD_ENB bit to 0 It is used for checking VDD voltage BIF is set to 1 when BOD occurs It can be used to dis tinguish reset caused by BOD and other When the POR is used the BOD detection level should be set to the level less than POR level If the POR level is 128 SEMICONDUCTOR 2 4V BOD level 2V and 2 4V can not operate RESET VECTOR H NO RAM Clear Initialize RAM Data BIF 0 Initialize All Ports Initialize Registers gt lt Function Execution Skip the initial routine Figure 27 2 Example Flow of Reset flow by BOD December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 28 Osillation Noise Protector The Oscillation Noise Protector ONP is used to supply stable internal system clock by excluding the noise which could be entered into oscillator and recovery the oscillation fail This function could be enabled or disabled by the ONP bit of the Device configuration area 20FFy for the MC81F8816 8616 The ONP fu
114. eneral call detection 0 no master 0 no detected 1 master 1 detected ALD arbitration lost detection COl selected as slave 0 no arbitration lost 0 no selected 0 no detected 1 arbitration lost 1 selected 1 detected I2CCR 2 Clock Control Register R W R W R W R W R W R W 7 6 5 4 3 2 CLK6 CLK5 CLK3 i FM protocol mode select CLK6 CLKO pre scale value 0 standard mode Fscl Fsys 4N 1 fast mode N Pre scale value I2CCR 6 0 I2CPR 2 Pipe and Shift Register R W R W R W R W R W R W Bit 7 6 5 4 3 2 note shift and pipe register have the same address shift register is only readable and pipe register is only writable 2 2 Slave Address Register R W R W R W R W R W R W Bit T 6 5 4 3 2 SVAD6 i SVAD5 SVAD4 SVAD3 SVAD2 i SVAD1 note SVAD is a 7bit slave address R W 1 STT TRC transmission status 0 no transmitter 1 transmitter ACKD acknowledge detection R W R W R W SVADO R W 0 WTIM when interrupt request occurs Sr 0 no operation 0 I after 8th clock s falling edge 122 1 release sel to high 1 after ACK clock s falling edge RESV SPIE interrupt enalbe after stop detection ACKE acknowledge enable 0 0 disable 0 no acknowledge 1 1 enable on STD start condition detection 0 no detected 1 detected SPD stop condition detection 0 no detected 1 detected R W R W
115. er 112 December 3 2012 Ver 1 03 ABOV MC81F8816 8616 SEMICONDUCTOR RW RW RW RW RW RW RW R 2 22 2 ADDRESS BRGCR TPS2 TPS1 TPSO MDL3 MDL2 MDL1 MDLO INITIAL VALUE 001 00008 Input clock Selection for Baud Rate Generator k 0000 fsck 16 0 1000 fsck 24 8 0001 17 ke 1001 fsck 25 9 0010 fsck 18 2 1010 fsck 26 10 0011 fsck 19 k 3 1011 fsck 27 k 11 0100 fsck 20 k 4 1100 fsck 28 k 12 0101 fsck 21 k 5 1101 fsck 29 k 13 0110 fsck 22 k 6 1110 fsck 30 k 14 0111 fsck 23 k 7 1111 Setting Prohibited Source Clock Selection for 5 bit Counter fsck n 000 R11 ACK 100 fMain 24 n 4 001 fuuN72 n 1 101 fMAIN 25 5 010 fmain 22 2 110 26 n 6 011 fmain 23 3 111 fMain 2 7 Cautions 1 Writing to BRGCR during a communication operation may cause abnormal output from the baud rate generatior and disable further communication operations Therefore do not write to BRGCR during a communication operation Remarks 1 fsck Source clock for 5 bit counter 2 Main Oscillation Frequency 3 n Value set via TPSO to TPS2 4 k Value set via MDLO to MDL3 5 The baud rate generated from the main system clock is determined according to the following formula 2n 1 16 Baud Rate ADDRESS 0BBH RXBR INITIAL VALUE 0000 00005 UART Receiving Data at Receiv
116. es and matches TDRO TDR1 TDR2 TDR3 This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer For example in Figure 12 13 the pulse width of captured signal is wider than the timer data value FFy over 2 times When external interrupt is occurred the captured value 13g is more little than wanted value It can be ob tained correct value by counting the number of timer over December 3 2012 Ver 1 03 MC81F8816 8616 flow occurrence Timer Counter still does the above but with the added fea ture that a edge transition at external input INTx pin causes the current value in the Timer x register TO T1 T2 T3 to be captured into registers CDRx x 0 1 2 3 respectively After captured Timer x register is cleared and restarts by hardware It has three transition modes falling edge rising edge both edge which are selected by interrupt edge selection register IEDS Refer to External interrupt section In ad dition the transition at INTx pin generate an interrupt Note The and are in same address In the capture mode reading operation is to read the CDRO and in timer mode reading operation is read the TO TDRO is only for writing operation The CDR1 T1 are in same address the is lo cated in different address In the capture mode reading operation is to read the CDR1 63
117. flag register except Power on reset and software BRK interrupt The configu ration of interrupt circuit is shown in Figure 17 1 and inter rupt priority is shown in Table 17 1 Table 17 1 Vector Table Reset Interrupt Symbol Priority Vector Addr pis Hardware Reset RESET 0 FFFEH INT15 External Int 0 INTRO 1 FFFAH INT13 External Int 1 INTR1 2 FFF8H INT12 External Int 2 INTR2 3 FFF6H INT11 External Int 3 INTR3 4 FFF4H INT10 UART RXO RXO 5 FFF2H INT9 UART TXO TXO 6 FFF2H INT9 SPI SPI 7 FFEEH INT7 Timer O Int TO 8 FFECH INT6 Timer 1 Int T1 9 FFEAH 5 Timer 2 Int T2 10 FFE8H INT4 Timer 3 Int T3 11 FFE6H INT3 2 12 12 FFE4H INT2 Int ADC 13 FFE4H INT2 BIT Int BIT 14 FFE2H INT1 Watch Dog timer int WDT 15 FFEOH INTO Watch timer int WT 16 FFEOH INTO Each bit of interrupt request flag registers IRQH IRQM IRQL in Figure 17 1 is set when corresponding interrupt condition is met The interrupt request flags that actually generate external interrupts are bit INTOF INTIF and INT2F in Register IROH and INT3F in Register IRQL The External Interrupts INTO INT1 INT2 and INT3 can each be transition activated 1 to 0 0 to 1 and both transi tion The RX0 and TX0 of UARTO Interrupts are generat ed by RXOIF and TXOIF which are set by finishing the reception and transmission of data The Timer 0 1 2 and Timer 3 Interrupts are generated by 21 and T3IF which are set by a match in
118. g of each segment output RESET clears the LCD control register LCR values to logic zero The LCD SEG or COM ports are selected by setting corresponding December 3 2012 Ver 1 03 MC81F8816 8616 bits of RSPSR R6PSR or R7PSR to 0 The LCD display can continue to operate during SLEEP and STOP modes if sub frequency clock is used as LCD 89 MC81F8816 8616 clock source ABOV SEMICONDUCTOR LCR LCD Control Register R5PSR R5PSR7 R5PSR6 R5PSR5 R5PSR4 5 R5PSR2 R5PSR1 RBPSRO R6 LCD Port Selection Register R W R W R W R W R W R W R W R W Bit T 6 5 4 3 2 1 0 R6PSR R6PSR7 R6PSR6 i R6PSR5 i R6PSR4 R6PSR3 R6PSR2 R6PSR1 R6PSR0 R7 LCD Port Selection Register R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 R7PSR R7PSR7 R7PSR6 R7PSR5 R7PSR4 R7PSR3 R7PSR2 R7PSR1 R7PSRO R8 LCD Port Selection Register EVA R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 R8PSR R8PSR7 R8PSR6 RBPSR5 R8PSR4 RBPSR3 RBPSR2 RBPSR1 R8PSRO EVA CHIP MAIN CHIP PSPSR RSPSR R7PSR 0 Seg Selection 0 Seg Selection 1 Port Selection 1 Port Selection WTMR Watch Timer Mode Register R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 0 Seg Selection 11 fuck 21 x 7bit WT value 1 2Hz x 7bit WT value 1 011 Main Clock fain 111 Main Clock 2 R W R W R W R W R W R W R W R W Bit
119. gt IR46 Oniy Pin N C NT RESET Only N C gt XOUT RESET XOUT 1842 OOOOOOOOOOOOOO00 J USER B vec O REMOUT O O GND O GND RsrRA7 R46 R45 O R43 O Rz2 R41 O R37 O R36 R35 O O Ra4 R33 O 2 R31 O Rao R27 O R26 R25 O IRA R23 O Rz2 R211 O R20 R171 O O R15 O Ir R13 O 12 R11 O O Into 7 O O O R01 O Roo OO GND D GND J USER A AVCC SEG41 COMO COM2 COM4 SEG39 COM6 SEG37 SEG35 SEG33 R87 SEG31 R85 SEG29 R83 SEG27 R81 SEG25 R77 SEG23 R75 SEG21 R73 SEG19 R71 SEG17 R67 SEG15 R65 SEG13 R63 SEG11 R61 SEG9 57 5 7 R55 SEG5 R53 SEG3 R51 SEG1 GND OOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOO AVCC SEG40 COM1 COM3 COMS SEG38 COM7 SEG36 SEG34 SEG32 R86 SEG30 R84 SEG28 R82 SEG26 R80 SEG24 R76 SEG22 R74 SEG20 R72 SEG18 R70 SEG16 R66 SEG14 R64 SEG12 R62 SEG10 R60 SEG8 R56 SEG6 54 5 4 R52 SEG2 R50 SEGO GND J USEC C is reserved for further use Unused in MC81F8816 8616 133 December 3 2012 Ver 1 03 MC81F8816 8616 31 IN SYSTEM PROGRAMMING 31 1 Getting Started Installation The In System Programming ISP is performed without rem
120. h Compare output function Example 3 Timer0 8 bit event counter Timer2 8 bit capture mode 2us sampling count LDM TDRO OF FH don t care LDM TMO 1FH event counter LDM ROIO 1XXX_XX1XB 7 RO7 ROL input DM IEDS XXXX_01XXB FALLING LDM PSRO 1XXX_XX1XB INTL ECO LDM TDR2 0FFH LDM 2 0010 1011B 2us SETI TOE ENABLE TIMER 0 SET1 T2E ENABLE TIMER 1 SET1 ENABLE INTL EI X don t care Example 4 Timer 16 bit capture mode 8us sampling count at 4MHz LDM LDM TDR1 0FFH LDM TMO 2FH LDM TM1 5FH IEDS XXXX 01 LDM PSR0 X1XX XXXXB AS INTO ENABLE TIMER 0 ENABLE EXT INTO SET1 TOE SET1 INTO EI Fl X don t care 55 MC81F8816 8616 ABOV SEMICONDUCTOR 2 0 2 Mode Control Register R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 7 7 ADDRESS 000 TMO i 2 TOCK1 TOCN INITIAL VALUE 0000008 R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 7 7 ADDRESS TM2 i CAP2 T2CK2 T2CK1 2 T2CN INITIAL VALUE 000000g CAPO CAP2 Capture Mode Selection Bit TOCK 2 0 T2CK 2 0 Timer 0 2 Input Clock Selection 1 TOCK 2 0 T2CK 2 0 PROPRAN 000 fMAINT2 000 fMAINT2 TOCN T2CN Timer
121. ine whether an interrupt will be accepted or not When enable bit is 0 a corre sponding interrupt source is prohibited Note that PSW contains also a master enable bit I flag which disables all interrupts at once When an interrupt is occurred the I flag is cleared and disable any further interrupt the return ad dress and PSW are pushed into the stack and the PC is vec tored to In an interrupt service routine any other interrupt may be serviced The source s of these interrupts can be deter mined by polling the interrupt request flag bits Then the interrupt request flag bit s must be cleared by software be fore re enabling interrupts to avoid recursive interrupts The Interrupt Request flags are able to be read and written 81 ABOV MC81F8816 8616 SEMICONDUCTOR Internal bus line I flag is PSW it is cleared by DI set by if El instruction When it goes interrupt service I flag is cleared by hardware thus any other Interrupt Enable interrupts are inhibited When interrupt service is IRQH Register Higher byte completed by instruction I flag is set to 1 by hardware Ext Int 0 INTOIF D Ext Int 1 gt INT1IF 5 Ext Int 2 Release STOP Ext Int 3 i 0 RXOIF 3 D 2 To CPU Internal bus line INTFH 5 o o gt 2 9 pm a Timer 1
122. ing Mode W W W W W W W W 7 6 5 4 3 2 1 0 ADDRESS H TXSR INITIAL VALUE 1111 1111 UART Sending Data at Sending Mode Figure 21 2 Baud Rate Generator Control Register Receive Buffer Register Transmit shift Register December 3 2012 Ver 1 03 113 SEMICONDUCTOR MC81F8816 8616 NBOV 21 2 Relationship between main clock and baud rate The transmit receive clock that is used to generate the baud rate is obtained by dividing the main system clock Transmit Receive clock generation for baud rate is made by using main system p clock which is divided BaudRate 29 16 The baud rate generated from the main system clock is deter fx main system clock oscillation frequency mined according to the following formula n value set via TPSO to TPS1 1 lt n x 7 value set via MDLO to MDL3 0 lt n x14 fx211 0592M fx 8 00M fx27 3728M fy 6 00M fx 5 00M fx 4 1943 Baud Rate bps BRGCR cA BRGCR A BRGCR zA BRGCR BRGCR a BRGCR c 600 7BH 1 14 1 200 zaH 0 6 78H 0 00 73H 279 173 6BH 1 14 2 400 72H 0 00 6AH 0 16 68H 0 00 63H 279 173 5BH 1 14 4 800 62H 0 00 0 16 58H 0 00 53H 279 50H 173 1 14 9 600 52H 000 4AH 0 46 48H 0 00 43H 279 40H 1 73 3BH 1 14 19 200 42H 0 00 0 16 38H 0 00 33H 279 173 2BH 1 14 31
123. interrupt is occurred TDR1 Timer1 Data Register w w w w Ww w Ww Ww Bit 7 6 5 4 3 2 1 0 TDR17 TDR16 TDR15 i TDR14 i TDR13 TDR12 TDR11 i TDR10 ADDRESS INITIAL VALUE FFH If the counter of Timer 1 and the data of TDR1 is equal interrupt is occurred T1PPR Timer1 PWM Period Register w w w w w w w w 7 6 Bit ADDRESS INITIAL VALUE FFH The period is decided by PWM T1 Timer1 Register Bit 7 6 ADDRESS 004 INITIAL VALUE 00H CDR1 Timer1 Input Capture Register R R R R R R R R Bit 7 6 5 4 3 2 1 0 CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 ADDRESS 0D4y INITIAL 00 In Timer mode this register is the value of Timer 1 counter and in Capture mode this register is the value of input capture T1PDR Timer1 PWMO Duty Register W R W R W R W R W R W R W R W R Bit 7 6 5 4 3 2 1 0 ADDRESS 0D4y INITIAL 00 In PWM mode decide the pulse duty T1PWHR Timer1 PWMO High Register w w w w w w w w Bit 7 6 5 4 3 2 1 0 ADDRESS 0D5y INITIAL VALUE 000008 Figure 12 2 Related Registers with Timer CounterO 1 December 3 2012 Ver 1 03 57 SEMICONDUCTOR MC81F8816 8616 ABOV T2 Timer2 Register Bit 7 6 ADDRESS 007 INITIAL VALUE 00H CDR2 Timer2 Input Capture Register R R R R R R R R Bit 7 6 5 4 3 2 1 0 ADDRESS 0D7H INITIAL VALUE 00H In Timer m
124. isters Accumulator The Accumulator is the 8 bit general pur pose register used for data operation such as transfer tem porary saving and conditional judgement etc The Accumulator can be used as a 16 bit register with Y Register as shown below Two 8 bit Registers can be used a YA 16 bit Register Figure 8 2 Configuration of YA 16 bit Register X Y Registers In the addressing mode which uses these index registers the register contents are added to the spec ified address which becomes the actual address These modes are extremely effective for referencing subroutine tables and memory tables The index registers also have in crement decrement comparison and data transfer func tions and they can be used as simple accumulators Stack Pointer The Stack Pointer is an 8 bit register used for occurrence interrupts and calling out subroutines Stack Pointer identifies the location in the stack to be accessed save or restore 32 SEMICONDUCTOR Program memory Data memory can be read and written to up to 512 bytes including the stack area Display memory has prepared 64bytes for LCD Generally SP is automatically updated when a subroutine call is executed or an interrupt is accepted However if it is used in excess of the stack area permitted by the data memory allocating configuration the user processed data may be lost The stack can be located at any position within 100g to
125. l 2F 2 4 Branch always L2 pc lt rel Branch if overflow bit clear 39 2 24 if V 0 then pee Branch if overflow bit set i eS 29 u 2 it y 1 then poe pe trel 7777 14 CALL abs 3B 3 8 Subroutine call sp lt sp lt sp 1 lt sp lt 1 is CALE oF iflabs pcc abs if dp lt dp lt dp t1 1 16 CBNE dp rel FD 3 5 7 Compare and branch if not equal 17 CBNE dp x rel 8D 3 6 8 M then pc lt pc rel 18 DBNE dp rel AC 3 5 7 Decrement and branch if not equal 1 19 DBNE Y rel 7B 2 4 6 if M 0 then pc lt pc rel 20 JMP abs 1B 3 3 Unconditional jump 21 JMP labs 1F 3 5 lt jump address 22 JMP dp 3F 2 4 U page call 23 PCALL upage 4F 2 6 M sp lt sp lt 1 lt pa sp lt sp 1 lt lt OFFu Table call sp sp lt sp 1 24 TCALL n nA 1 8 M sp per spesp 1 _ December 3 2012 Ver 1 03 xi MC81F8816 8616 Control Operation amp Etc ABOV SEMICONDUCTOR No Mnemonic ote Eo Operation Software interrupt lt 1 lt sp lt sp 1 4 BRK OF 4 8 s lt pcL sp lt sp 1 M sp lt PSW sp lt sp Y pe lt lt OFFDFy 2 DI 60 1 3
126. lation instruction Example To write at CKCTLR LDM CKCTLR 05H Divide ratio 8 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR routine at the execution of a subroutine call instruction or the acceptance of an interrupt When returning from the processing routine executing the subroutine return instruction RET restores the contents of the program counter from the stack executing the interrupt return instruction RETI restores the contents of the pro gram counter and flags MC81F8816 8616 the stack pointer SP The SP is automatically decreased after the saving and increased before the restoring This means the value of the SP indicates the stack location number for the next save Refer to Figure 8 4 on page 34 LCD Display Memory LCD display data area is handled in LCD section The save restore locations in the stack are determined by See 18 3 LCD Display Memory on page 94 Address Register Name Symbol R W eee i es 76543210 0090H I2C Mode Control Register I2CMR R W 100001000 byte 0091H I2C Status Register I2CSR R 00000000 byte 0092H I2C Clock Control Register I2CCR R W 1111111111111 1 byte 0093H I2C Pipe and Shift Register I2CPR R W 111111111 byte 0094H I2C Sl
127. mbol Condition Unit Min Typ Max LCD Common ae Output Current Icom Output Voltage Deviation 0 2V 30 LCD Segment DU Output Current IsEG Output Voltage Deviation 0 2V 5 _ 7 5 A D Converter Characteristics 40 85 C Vpp AVref 5 12V 3 072V Vss 0V Specifications Parameter Symbol Pin Condition Unit Min Typ Max Resolution NR 10 Bit Analog Power Supply Input Voltage Range AVREF AVss VDD Analog Input Voltage Range VAIN AVss AVref Vpp 5 12 Conversion Current ICON 8MHz 80 200 December 3 2012 Ver 1 03 23 ABOV MC81F8816 8616 SEMICONDUCTOR Specifications Parameter Symbol Pin Condition Unit Min Typ Max Overall Accuracy NACC 1 0 3 0 Non Linearity Error NNLE 3 0 Differential Non Linearity Error NDNLE 3 0 v Zero Offset Error NzoE fXiN 4MHz 3 0 Full Scale Error 3 0 Gain Error NcE 3 0 Conversion Time Clock uM 1 0 us Analog Input Impedance RAN 5 100 MO 1 If the AVnzgr voltage is less than Vpp voltage and anlalog input pins ANX shared with various alternate function are used bidirectional l port the leakage current may flow Vpp pin to pin in output high mode or anlalog input pins ANX to AVger pin in input high mode 24 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR
128. n Clock 27 ADDRESS RESET VALUE 1111 1111B Seg7 Seg0 ADDRESS RESET VALUE 1111 1111B Seg15 Seg8 ADDRESS RESET VALUE 1111_1111B Seg23 Seg16 ADDRESS 0 RESET VALUE 1111_1111B Seg31 Seg24 Figure 18 2 LCD Control Register 90 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR Note If the SCKD is set to 1 the SXIN and SXOUT pin is used as normal I O pin R45 R46 Note When the Sub clock is used as internal bias source clock stabilization time is needed Normally the stabiliza tion time is need more than 500ms Selecting Frame Frequency Frame frequency is set to the base frequency as shown in the following Table 18 1 The fs is selected to sub clock which is 32 768kHz MC81F8816 8616 Note When selecting Sub clock as the LCD clock source the WTCK 2 0 bit of WTMR Watch Timer Mode Register should be set to 000 as well as SCKD bit of LCR be set to 0 Note Bit 6 Bit 4 Bit 3 of LCR should be set to 1 0 1 respectively Frame Frequency Hz LCR 1 0 LCD clock Duty 1 4 Duty 1 8 00 fsup 32 128 64 01 fsuB 64 64 32 10 fsup 128 32 16 11 fsup 256 16 8 Table 18 1 Setting of LCD Frame Frequency The matters to be attended to use LCD driver In reset state LCD source clock is sub clock So when the power is supplied the LCD display would be
129. n the emulator December 3 2012 Ver 1 03 How to Program To program the FLASH or MTP devices user can use ABOV own programmer ABOV own programmer list Manufacturer ABOV Semiconductor Programmer Choice Sigma StandAlone Gang4 PGM plus The Choice Sigma is a ABOV Universal Single Programmer for 131 MC81F8816 8616 all of ABOV FLASH OTP devices also the StandAlone Gang4 can program four FLASH OTPs at once for ABOV device Ask to ABOV sales part for purchasing or more detail Programming Procedure 1 Select device MC81F8816 8616 2 Load the OTP file from the PC The file is composed of Motorola S1 format 132 ABOV SEMICONDUCTOR 3 Set the programming address range as below table Address Set Value Buffer start address 000 Buffer end address FFFFH Device start address 000 4 Mount the socket adapter on the programmer 5 Start program verify December 3 2012 Ver 1 03 MC81F8816 8616 SEMICONDUCTOR ABOV 30 EMULATOR EVA BOARD SETTING B e gt c e E NR e e gt LLI G LLI L O 32 768kHz CONNECTA CONNECTB OOOOOOOOOO OOOOOOOOOO OOOO OOOOOO O ABOV MC80073 74_EVA RESET XOUT SXin ISXOUT T_RST R47 NT R42 om R45 NT SXOUT R46
130. nce 84 BRK Interrupt 85 Multi Interrupt 85 External Interrupt 87 18 LOD DRIVER ERR TER ERE 88 Control of LCD Driver Circuit 89 LCD BIAS Control 92 LCD Display Memory 94 Control Method of LCD Driver 95 Duty and Bias Selection of LCD Driver 97 19 SERIAL PERIPHERAL INTERFACE SPI 98 Transmission Receiving Timing 99 The usage of Serial 100 The Method to Test Correct Transmission 101 20 INTER IC COMMUNICATION 2 102 Bit Transfer ten 104 Start Stop Conditions 104 Data Transfer 105 Acknowledge seen 106 Syncronization Arbitation 107 21 UNIVERSAL ASYNCHRONOUS SERIAL IN TERFAGCE UART 110 Asynchronous Serial Interface Configuration 111 Relationship between main clock and baud rate 114 22 OPERATION MODE 115 Operation Mode Switching 116 23 POWER DOWN OPERATION 117
131. nction is like below Recovery the oscillation wave crushed or loss caused MC81F8816 8616 by high frequency noise Change system clock to the internal oscillation clock when the high frequency noise is continuing Change system clock to the internal oscillation clock when the XrN Xour is shorted or opened the main oscillation is stopped except by stop instruction and the low frequency noise is entered XIN OFP 1 XIN_NF HF Noi ips oise HF Noise Canceller 05 Internal FINTERNAL Observer gt OSC en INT_CLK Y LF Noise ONP Observer ONP gt en OFP m INSMCLK XO INAMCLK XO olf en OFP ONPb 0 CK PIU 8 Bit counter LF_on 1 IN CLK 0 INT_CLK 8 periods PS10 INT_CLK 512 256 periods High Frq Noise 250ns x 8 2us 250ns x 512 x 256 33 ms 1 gt a XIN 20 7 Noise Cancel Low Frq Noise or Oscillation Fail XIN NF d INT CLK reset INT CLK NE _ CHG_END 2 I 2 j CLK_CHG r LAN Clock Change Start XIN to INT CLK Clock Change End INT to XIN fINTERNAL
132. nly LDM IENH 4OFFH Enable all interrupts LDM IENM OFFH LDM IENL 0FOH POP Y POP X POP A RETI 85 MC81F8816 8616 Main Program service TIMER 1 service INTO enable INTO Servis disable other El Occur gt Occur TIMER1 interrupt INTO enable INTO enable other In this example the INTO interrupt can be serviced without any pending even TIMER7 is in progress Because of re setting the interrupt enable registers IENH IENM IENL and master enable in the TIMER1 routine Figure 17 5 Execution of Multi Interrupt 86 ABOV SEMICONDUCTOR December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 17 4 External Interrupt The external interrupt on INTO INT1 INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS address as shown in Figure 17 6 The edge detection of external interrupt has three transition activated mode rising edge falling edge and both edge INTO L INTOIF gt INTO INTERRUPT ae H INT1IF gt INT1 INTERRUPT duis edge selection INT2 _ INT2IF gt INT2 INTERRUPT ase H IEDS 0FCu INT3IF INT3 INTERRUPT dua IEDS Ext Interrupt Edge Selection Register ADDRESS RESET VALUE 000000008 R W R W R W R W R W R W Bit 7 6 5 4 3 1 0 N IED3H IED3L IED2H IED2L IED1H IED1L IEDOH IEDOL
133. ns Unit Min Typ Max Input Clock Pulse Period tscyc 2tsyst 200 Input Clock H or L Pulse Width sckw tsyst70 Input Clock Pulse Transition Time tesck tRsck I i 30 SCK Ouput Clock Cycle Time tscvc Atsys 16tsys Output Clock H or L Pulse Width sckw 2tsys 30 I Output Clock Transition Time tesck trscK 30 ns Output Clock Delay Time tps 100 Input Pulse Transition Time tRSIN 5 30 Input Setup Time E I External SCK tEsus 100 Input Setup Time Internal SCK uisus 200 Input Hold Time tus tsyst 70 SCLK SI tFSIN RSIN tps so 0 8Vpp 0 2Vpp Figure 7 3 Serial I O Timing Chart December 3 2012 Ver 1 03 27 MC81F8816 8616 7 8 Typical Characteristics These graphs and tables are for design guidance only and are not tested or guaranteed In some graphs or tables the data presented are out side specified operating range e g outside specified Vpp range This is for information only and devices are guaranteed to operate properly only within the specified range SEMICONDUCTOR The data is a statistical summary of data collected on units from different lots over a period of time Typical repre sents the mean of the distribution while max or min represents mean 36 and mean respectively where o is standard deviation Operating Area MHz 40 85 C Main clock 12 10 8 6 4
134. nverting oscillator amplifier and input to the internal main clock operating circuit Output from the inverting oscillator amplifier Input to the internal sub system clock operating cir cuit SXour Output from the inverting subsystem oscillator amplifier SEG0 SEG39 Segment signal output pins for the LCD display See 18 LCD DRIVER on page 88 for details Also SEGO SEG23 are shared with normal I O ports and SEG24 35 are only segment output port SEG24 31 are shared with normal I O port at EVA chip and SEG36 39 are multiplexed with COM7 COMA Note SEG28 SEG35 are not supported in MC81F8616Q 64pin COM0 COM7 Common signal output pins for the LCD display See 18 LCD DRIVER on page 88 for details Also COM0 COM are only common output ports and COM4 COM7 are multiplexed with SEG36 SEG39 COM4 COM7 and SEG36 SEG39 are selected by LCDDO of the LCR register LCDDO 4 SEG39 SEG36 0 1 SEG39 SEG36 R00 R07 RO is 8 bit CMOS bidirectional I O port 5 bit I O port at MC81F8616Q RO pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs Also pull up resistors and open drain outputs can be as signed by software In addition RO serves the functions of the various follow 12 SEMICONDUCTOR ing special features Port pin Alternate function ROO PWMO TOO Timer1 PWM Output TimerO Output R01 ECO Timer 0
135. o 1 when an overflow occurs as the result of an arithmetic operation involving signs An overflow occurs when the result of an addition or subtraction ex ceeds 127 7 or 128 80g The CLRV instruction clears the overflow flag There is no set instruction When the BIT instruction is executed bit 6 of memory is copied to this flag Negative flag N This flag is set to match the sign bit bit 7 status of the re sult of a data or arithmetic operation When the BIT in struction is executed bit 7 of memory is copied to this flag 33 MC81F8816 8616 ABOV SEMICONDUCTOR At execution of a CALL TCALL PCALL 01 01FD 01 O1FF SP before execution O1FF SP after execution 01FD Push down At acceptance of interrupt 01FC 0120 01 O1FF Push down O1FF 01FC At execution of PUSH instruction PUSH A X Y PSW 01 0120 01 O1FF SP before execution SP after execution Push down O1FF Y O1FE 01FC O1FE O1FF At execution of RET instruction 01 0120 01 O1FF At execution of POP instruction POP A X Y PSW Pop up At execution of RETI instruction 0100 O1FFH Pop up Stack depth 34 Figure 8 4 Stack Operation December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 8 2 Program Memo
136. o option of 2 4 8 32 128 512 2048 selected by con trol bits TxCK2 and TxCKO of register TM0 2 and 1 2 8 selected by control bits and TxCKO of register TM1 3 In the Timer timer register Tx increases from 00g until it matches TxDR and then reset to 00g If the value of Tx is equal with TxDR Timer x interrupt is occurred latched in TxIF bit TxDR and TO register are in same address so this register is read from and written to 60 In counter function the counter is increased every 0 to 1 rising edge transition of ECO pin In order to use counter function the bit R01 of the RO Direction Register ROIO should be set to 0 and the bit ECOE of Port Selection Register PSRO should set to 1 The Timer 0 can be used as a counter by pin ECO input but other timers can not used as a event counter Note The contents of TDRO TDR1 TDR2 and TDR3 must be initialized by software with the value be tween 1 not Og December 3 2012 Ver 1 03 SEMICONDUCTOR NBOV MC81F8816 8616 T0 1 2 34 TDRO TDR1 TDR2 TD
137. ode this register is the value of Timer 2 counter and in Capture mode this register is the value of input capture CDR27 CDR26 CDR25 CDR24 CDR23 CDR22 CDR21 CDR20 TDR2 Timer2 Data Register w w w w w w Bit 7 6 5 4 3 2 1 0 TDR27 TDR26 TDR25 TDR24 TDR23 i TDR22 i TDR21 TDR20 ADDRESS 007 INITIAL VALUE FFH If the counter of Timer 0 and the data of TDRO is equal interrupt is occurred TDR3 Timer3 Data Register w Ww Ww Ww w Ww w w Bit f 6 5 4 3 2 1 0 TDR37 TDR36 TDR35 i TDR34 TDR33 i TDR32 i TDR31 i TDR30 ADDRESS 0D9H INITIAL VALUE FFH If the counter of Timer 1 and the data of TDR1 is equal interrupt is occurred T3PPR Timer3 PWM Period Register w Ww w w w Bit 7 6 5 4 3 2 1 0 ADDRESS 9 INITIAL VALUE FFH The period is decided by PWM T3 Timer3 Register Bit 7 6 ADDRESS INITIAL VALUE 00H T3PDR Timer3 PWM Duty Register W R W R W R W R W R W R W R W R Bit 7 6 5 4 3 2 1 0 ADDRESS 0DAH INITIAL VALUE 00u In PWM mode decide the pulse duty CDR3 Timer3 Input Capture Register R R R R R R R R Bit 7 6 5 4 3 2 1 0 ADDRESS 0DAH INITIAL VALUE 00H In Timer mode this register is the value of Timer 2 counter and in Capture mode this register is the value of input capture CDR37 CDR36 CDR35 CDR34i CDR33 CDR32 CDR31 CDR30 T3PWHR Timer3 High Register w w w w w w w w Bit 7 6
138. omatically to 0 At the default state of POL bit clear the serial output data from 8 bit shift register is output at falling edge of SCLK and input data is latched at rising edge of SCLK pin Refer to Figure 19 3 When transmis sion clock is counted 8 times serial I O counter is cleared as 0 Transmission clock is halted in H state and serial I O interrupt SPIIF occurred December 3 2012 Ver 1 03 99 MC81F8816 8616 SEMICONDUCTOR SIOST SCK R11 POL 0 soria Ver ee re 0 Y SI R13 IOSW 0 IOSWIN R12 IOSW 1 SPIIF SPI Int Req Figure 19 3 Serial I O Timing Diagram at POL 0 SPISF SPI Status SIOST SCK R11 POL 1 SO R12 SI R13 IOSW 0 IOSWIN R12 IOSW 1 SPIIF SPI Int Req Figure 19 4 Serial I O Timing Diagram at POL 1 SPISF SPI Status 19 2 The usage of Serial I O 1 Select transmission receiving mode 5 In case of receiving mode the received data is acquired In case of sending mode write data to be send to SPIR By reading Mia AEUR 6 When using polling method the completion of 1 byte 2 3 Set SPIST to 1 to start serial transmission 4 The SPI interrupt 1s generated at the completion of SPI and SPIIF is set to 1 100 serial communication can be checked by reading SPIST and SPISF As shown in example code wait until SPIST is changed to 0 and then w
139. onger than 20ms Figure 23 4 STOP Mode Release Timing by External Interrupt Oscillator X pin Internal Clock L RESET STOP Instruction Executed N BIT Counter at 4 19MHz by hardware 1 x 256 ST fMAIN 1024 Figure 23 5 STOP Mode Release Timing by RESET 120 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR Minimizing Current Consumption The Stop mode is designed to reduce power consumption To minimize current drawn during Stop mode the user should turn off output drivers that are sourcing or sinking current if it is practical Note In the STOP operation the power dissipation asso ciated with the oscillator and the internal hardware is low ered however the power dissipation associated with the pin interface depending on the external circuitry and pro gram is not directly determined by the hardware operation of the STOP feature This point should be little current flows when the input level is stable at the power voltage level Vpp Vss however when the input level becomes higher than the power voltage level by approximately 0 3V a cur rent begins to flow Therefore if cutting off the output tran sistor at an I O port puts the pin signal into the high impedance state a current flow across the ports input tran sistor requiring it to fix the level by pull up or other means MC81F8816 8616 It sh
140. ors which are main frequency clock oscil lator and a sub frequency clock oscillator The system clock can also be obtained from the external oscillator By setting configuration option the internal SMHz 4MHz can also be selected for system clock source The clock generator produces the system clocks forming clock pulse which are supplied to the CPU and the periph eral hardware MC81F8816 8616 The internal system clock should be selected to main oscil lation by setting and bitO of the system clock mode register SCMR The registers are shown in Figure 10 2 To the peripheral block the clock among the not divided original clocks divided by 2 4 up to 4096 can be pro vided Peripheral clock is enabled or disabled by STOP in struction The peripheral clock is controlled by clock control register CKCTLR See 11 BASIC INTERVAL TIMER on page 53 for details FXTS XPLLCR 1 sub clk CONFIG 1 0 Internal 8MHz configuration option Internal 4MHz SCMR CS 1 0 1 2 Internal System Clock X2EN CONFIG 2 1 8 XIN E PS10 PS11 PS12 2 4 8 16 32 64 128 256 512 1024 2048 4096 Peripheral clock 2 PSO PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 Frequency 4M 2M 1M 500K 250K 125K 62 5K 31 25K 15 63K 7 183K 3 906K 1 953K 976 4M period 250n 500n 1u 2
141. ort Data Registers The Port Data Registers are represented as a D Type flip flop which will clock in a value from the internal bus in re sponse to a write to data register signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read data register signal from the CPU The level of the port pin itself is placed on the internal bus in response to read data register signal from the CPU Some instructions that read a port activating the read reg ister signal and others activating the read pin signal Port Direction Registers All pins have data direction registers which can define these ports as output or input A 1 in the port direction register configure the corresponding port pin as output Conversely write 0 to the corresponding bit to specify it as input pin For example to use the even numbered bit of RO as output ports and the odd numbered bits as input ports write 55 to address RO port direction reg ister during initial setting as shown in Figure 9 1 All the port direction registers in the MC81F88 16 8616 have 0 written to them by reset function Therefore its in itial status is input WRITE 55 TO PORT RO DIRECTION REGISTER 011 011 011 0 1 0C1H RO DIRECTION f 6 5 4 3 2 1 0 0 15 PORT 76543210 0COH RO DATA 0CCu 0CDH INPUT PORT O OUTPUT PORT Figur
142. ory 1 1 Data Table 8 bit Basic Interval Timer 5 Timing generator High freq clock Watch Watch Dog Timer PLL 10 bit A D 8 16 bit Low freq Generator Converter SIO UART PWM timer Counter ili i POR R7 R6 R5 R4 R2 i R1 i RO Buor amp BOD 8 8 8 6 5 8 5 R70 R60 R50 R42 R20 ANO R10 PWM1 T2O PWMO TOO R71 R61 R51 R43 SXIN R21 AN1 R11 ACK SCK R04 BUZO R72 R62 R52 R44 SXOUT R22 AN2 R12 TX0 SOUT R05 EC1 INTO R73 R63 R53 R45 XIN R23 AN3 R13 RX0 SI 06 INT1 R74 R64 R54 R46 XOUT R24 R14 INT2 R75 R65 R55 R47 RESETB R15 R76 R66 R56 R16 SDA R77 R67 R57 R17 SCL December 3 2012 Ver 1 03 SEMICONDUCTOR ABOV MC81F8816 8616 3 PIN ASSIGNMENT MOSPOVIVLMH LNOS XL ZLY IS XW L4 9 5 9 TOS ZLY ONV OZ4 LNV L 3 NV q ENV ETH SNV SZd 9NV 924H ZNV 42H Ov LNI LvH cra NIXS vd InOoxS vvH SSA 80MQFP Top View DUDA ONAN ONO ORO Q x g E gt SEEEN 85985988588 222 x occ 94 ASS vc N c sf LO cO Or d cioxowa oOoooooo O O O O O O O O LLI LLI LLI LLI LLI LLI
143. ould be set properly that current flow through port doesn t exist First consider the setting to input mode Be sure that there is no current flow after considering its relationship with external circuit In input mode the pin impedance viewing from external MCU is very high that the current doesn t flow But input voltage level should be Vss or Vpp Be careful that 1f unspecified voltage i e if uniformed voltage level not Vssor Vpp is applied to input pin there can be little current max 1mA at around 2V flow If it is not appropriate to set as an input mode then set to output mode considering there is no current flow Setting to High or Low is decided considering its relationship with external circuit For example if there 1s external pull up re sistor then it is set to output mode i e to High and if there is external pull down resistor it is set to low INPUT PIN VDD internal pull up OPEN Weak pull up current flows O V INPUT PIN DD FU i i 0 OPEN O Very weak current flows X i 0 When port is configured as an input input level should be closed to OV or Vpp to avoid power consumption Figure 23 6 Application Example of Unused Input Port OUTPUT PIN In the left case much current flows from port to GND OUTPUT PIN
144. output SEG16 SEG23 which can be selected by writing appropriate val ue into the R7PSR address 50 ABOV SEMICONDUCTOR ADDRESS 0B0H R7 Data Register RESET VALUE 000000008 R77 76 R75 R74 R73 i R72 R71 i R70 ADDRESS 0B4y RESET VALUE 000000008 Port Direction 0 Input 1 Output R7 Direction Register R7 LCD Port Selection Register ADDRESS RESET VALUE 11111111 R7PSR 7 7 7 56 7 5 R7PS4 R7PS3 IR7PS2 IR7PS1 IR7PSO 0 Seg Selection seg16 seg23 1 Port Selection Note R7 O is write only register It can not be read and can not be accessed by bit manipulation instruction Do not use read or read modify write instruction Use byte manip ulation instruction SEG0 SEG35 Segment signal output pins for the LCD display See 18 LCD DRIVER on page 88 for details SEG24 SEG31 is multiplexed with normal I O port EVA chip which can be selected by writing appropriate value into the R8PSR address OAFy COM0 COM7 Common signal output pins for the LCD display See 18 LCD DRIVER on page 88 for details SEG36 SEG39 and COM7 COM4 are selected by LCDD of the LCR register December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 10 CLOCK GENERATOR As shown in Figure 10 1 the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware It con tains two oscillat
145. oving the microcontroller from the system The In System Programming ISP facility consists of a series of internal hardware resources coupled with internal firm ware through the serial port The In System Programming ISP facility has made in circuit programming in an em bedded application possible with a minimum of additional expense in components and circuit board area The follow ing section details the procedure for accomplishing the in stallation procedure 1 Power off a target system ABOV SEMICONDUCTOR 2 Configure a target system as ISP mode Refer to 31 3 Hardware Conditions to Enter the ISP Mode 3 Attach a USB SIO ISP B D into a target system 4 Run the ABOV USB SIO ISP software Down load the ISP S W from http www abov co kr Unzip the download file and run USB SIO ISP exe 5 Select a device in the USB SIO ISP S W 6 Power on a target system 7 Execute ISP command such as read program auto by pressing buttons on the USB SIO ISP S W usB sio 1sP s w X m Los Load File ABOV f Save File Blank Check HE Program i Read Verify D Info JO r Log P E Option Sel H 00000 Success to open the ISPBDUSB driver editor x Option Write D JM FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FFFF FF FF FF FF FF F
146. r 3 2012 Ver 1 03 APPENDIX SEMICONDUCTOR MC81F8816 8616 ABOV A INSTRUCTION A 1 Terminology List Terminology Description A Accumulator X X register Y Y register PSW Program Status Word imm 8 bit Immediate data dp Direct Page Offset Address labs Absolute Address Indirect expression Register Indirect expression Register Indirect expression after that Register auto increment bit Bit Position A bit Bit Position of Accumulator dp bit Bit Position of Direct Page Memory M bit Bit Position of Memory Data 000 rel Relative Addressing Data upage U page OFFOOH OFFFFy Offset Address n Table CALL Number 0 15 Addition 0 Upper Nibble Expression Opcode Bit Position 1 Upper Nibble Expression in Opcode y FPBit Position Subtraction x Multiplication Division Contents Expression AND v OR Exclusive OR NOT lt Assignment Transfer Shift Left gt Shift Right o Exchange Equal Not Equal ii December 3 2012 Ver 1 03 ABOV MC81F8816 8616 SEMICONDUCTOR A 2 Instruction Map LOW 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH 00 01 02 03 04 05 06 07 08 09 0A 0B oc
147. r Input Selection 1 Enable 0000 Channel 0 R20 ANO 0 Disable 0001 Channel 1 R21 AN1 0010 Channel 2 R22 AN2 ADST A D Start bit 1 A D Conversion is started 0011 Channel 3 R23 AN3 0100 Channel 4 R24 AN4 0101 Channel 5 R25 AN5 0110 Channel 6 R26 AN6 After 1 cycle cleared to 0 2 0 Bit force to zero ADF A D Status bit 0111 Channel 7 R27 AN7 n 0 A D Conversion is in process 1000 Reserved 1 A D Conversion is completed 1001 Reserved ADCK A D Converter Clock source bit 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Self Bias Check Reference 0 A D Converter Clock source fps 1 1 A D Converter Clock source fps 2 Note R25 AN5 R26 AN6 and R27 AN7 are not supported in MC81F8616Q ADCRH A D Converter Result High Register w w w R R R R R Bit 7 6 5 4 3 2 1 0 i ADDRESS 4 PSSEL1 PSSELO ADC8 i ADR9 ADR8 RESET VALUE Undefined PSSEL 1 0 A D Converter PS Clock selection bit ADC8 A D Convertr Mode bit 00 A D Converter PS Clock fps fxin 4 0 10 bit Mode 01 A D Converter PS Clock fps fxiN 8 1 8 bit Mode 10 A D Converter PS Clock fps fxin 16 11 A D Converter PS Clock fps 32 ADCRL A D Converter Result Low Register R R R R R R R R Bit 7 6 5 4 3 2 1 0 ADDRESS ADR i ADR6 ADRS ADR4 ADR3 ADR2 ADR1 ADRO
148. r reset generation sources external reset input power on reset POR brown out detector reset BOD and watch dog timer re MC81F8816 8616 set Table 26 1 shows on chip hardware initialization by reset action On chip Hardware Initial Value On chip Hardware Initial Value Program counter PC FFFEH Operation mode Main frequency clock RAM page register RPR 0 Peripheral clock On G flag G 0 Control registers Refer to Table 8 1 on page 39 Table 26 1 Initializing Internal Status by Reset Action RESET Noise Canceller BOD Internal BOD Reset POR Power On Reset WDT 5 RESET Overflow gt R WDT Timeout Reset Clear BIT Figure 26 1 RESET Block Diagram 26 1 External Reset Input The reset input is the RESET pin which is the input to a Schmitt Trigger A reset accomplished by holding the RE SET pin to low for at least 8 oscillator periods within the operating voltage range and oscillation stable it is applied and the internal state is initialized After reset 65 5ms at 4MHz and 7 oscillator periods are required to start execu tion as shown in Figure 26 3 Internal User RAM is not affected by reset When Vpp is turned on the RAM content is indeterminate Therefore this RAM should be initialized before read or tested it When the RESET pin input goes to high the reset opera tion is released
149. re dp bit Abitrel pg Y dp X dp Y abs dp X 1 labs labs dp imm labs os BVC spc SBO spc sec test SUP coy ump re xX I Y dp X dp Y abs dp X 3 labs labs dp fimm dp 1 BCC cmp CMP cmp cmp LSR isr TOAL wu TOR CALL L re xX Y dp X dp Y abs dp X 5 labs dp imm dp ow BNE OR OR OR ROR ROR CAL CMPX LDYA CMPY pey re xX Y dp X dp Y abs dp X 7 Y labs dp imm ioo AND AND AND AND INC TOAL pwy CMPY INC TAY re k Y dp X dp Y abs dp X 9 labs dp Y 1 1 BYS EOR Eor Eor AY xma xma PFC DEC A re xX Y dp X dp Y abs dp X 14 X dp dp Y December 3 2012 Ver 1 03 iii MC81F8816 8616 NBOV SEMICONDUCTOR 10 BCS LOA D 1 Lpa Lov TSA ipA Lox STYA DAA rel xX Y dp X dp Y abs dp X 13 X labs dp N A BEQ STA sta sta sty sty TAL sta SIX NOP rel xX Y dp X dp Y abs dp X 15 X labs dp iv December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 A 3 Instru
150. rt pin Alternate function R60 SEG8 Segment Output 8 R61 SEGO9 Segment Output 9 R62 SEG10 Segment Output 10 R63 SEG11 Segment Output 11 R64 SEG12 Segment Output 12 R65 SEG13 Segment Output 13 R66 SEG14 Segment Output 14 R67 SEG15 Segment Output 15 R70 R77 R7 is a 8 bit CMOS input port or LCD segment output Each pins can be set in digital input or segment out put mode in 1 bit units by R7PSR Register Port pin Alternate function R70 SEG16 Segment Output 16 R71 SEG17 Segment Output 17 R72 SEG18 Segment Output 18 R73 SEG19 Segment Output 19 R74 SEG20 Segment Output 20 R75 SEG21 Segment Output 21 R76 SEG22 Segment Output 22 R77 SEG23 Segment Output 23 13 ABOV MC81F8816 8616 SEMICONDUCTOR Pin No Primary Function Secondary PIN NAME Function State State Reset STOP MC81F8816Q MC81F8616Q I O Description 1 0 Description Vpp 61 48 Supply Voltage Vss 64 51 Circuit Ground RESET R47 67 54 Generall Oport Reser low 1 input H input active Xin R45 Main clock oscilla Wa du Xout R46 65 66 52 53 or Oscillation L H SXIN R43 SXour R44 62 63 49 50 LO Sub clock oscillator Oscillation R50 SEGO X LCD segment R77 SEG23 8 31 3 26 General port output Input port SEG24 SEG25 6 7 12 gi on out SEG26 SEG27 4 5 63 64 gi cee 27
151. ry A 16 bit program counter is capable of addressing up to 64K bytes but this device has 16K bytes program memory space only physically implemented Accessing a location above FFFFy will cause a wrap around to 0000 Figure 8 5 shows a map of Program Memory After reset the CPU begins execution from reset vector which is stored in address FFFEy and FFFFy as shown in Figure 8 6 As shown in Figure 8 5 each area is assigned a fixed loca tion in Program Memory Program Memory area contains the user program n 5 FFOOH oO TCALL area a FFDFH 5 FFEOH a Interrupt Vector Area FFFFH Figure 8 5 Program Memory Map Page Call PCALL area contains subroutine program to reduce program byte length by using 2 bytes PCALL in stead of 3 bytes CALL instruction If it is frequently called it is more useful to save program byte length Table Call TCALL causes the CPU to jump to each TCALL address where it commences the execution of the service routine The Table Call service area spaces 2 byte for every TCALL OFFCOy for TCALL15 OFFC2y for TCALLI4 etc as shown in Figure 8 7 December 3 2012 Ver 1 03 MC81F8816 8616 Example Usage of TCALL LDA 5 TCALL OFH BYTE INSTRUCTION i INSTEAD OF 2 BYTES NORMAL CALL TABLE CALL ROUTINE e FUNC A LDA RGO RET FUNC B LDA RG1 s a TABLE CALL ADD AREA ORG O
152. s Vss RESET R47 Pull up gt amp Pull up Tr Reg L RD D sri Internal RESET F QH RESET Disable Vss Configuration option bit PLLC VDD ZN 7 Vss December 3 2012 Ver 1 03 VoD MAIN CLOCK ZN lt e 75 _ Vss VDD ZN XIN STOP 7 bd iB Vss Xin Xout RC Vpp T fyin 4 H Output STOP ZN Vss VDD VDD ZN STOP ae 75 y Main X T Vss ten 2 lt SXin SXour Vpp VoD 7 POWER VrREG 7 gt SXIN 75 Vss Vss DIASBLE o 19 MC81F8816 8616 R43 SXin RA4 SXour T Pull up Pull up gt d Tr Reg Open Drain T Vpp Data Reg a Direction SXiN Reg il L 1 R43 Y V 4 Ves ss Data Bus lt MUX 1 RD an Disable pm Sub Clock lt Open Drain Vi Reg DD Data Reg 4 4
153. s a critical factor this device provides STOP mode for reducing pow er consumption In case of starting the Stop Operation The STOP mode can be entered by STOP instruction dur ing program execution In Stop mode the on chip main frequency oscillator system clock and peripheral clock are stopped Watch timer clock is oscillating continuous ly With the clock frozen all functions are stopped but the on chip RAM and Control registers are held The port pins output the values held by their respective port data register and the port direction registers The status of peripherals during Stop mode is shown below Peripheral STOP Mode Sleep Mode CPU All CPU operations are disabled All CPU operations are disabled RAM Retain Retain LCD driver Operates continuously Operates continuously Basic Interval Timer Halted Operates continuously Timer Event counter 0 1 Halted Only when the Event counter mode is enabled Timer 0 1 operates normally Timer Event counter 0 1 operates continuously Watch Timer Operates continuously Operates continuously Main oscillation Stop Xin L Xour H Oscillation Sub oscillation Oscillation Oscillation ports Retain Retain Control Registers Retain Retain 118 Table 23 1 Peripheral Operation during Power Down Mode December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 STOP Mode by RESET Watch Timer interrupt Timer
154. seful for communicating with other periph eral of microcontroller devices These peripheral devices may be serial EEPROMs shift registers display drivers A D converters etc This SPI is 8 bit clock synchronous type and consists of serial I O data register serial I O mode register clock selection circuit octal counter and control SEMICONDUCTOR circuit as illustrated in Figure 19 1 The SO pin is designed to input and output So the Serial I O SPI can be operated with minimum two pin Pin R11 ACK SCK R13 RXO SI and R12 TX0 SO pins are controlled by the Serial Mode Register The contents of the Serial I O data register can be written into or read out by software The data in the Serial Data Register can be shifted synchronously with the trans fer clock signal SCK 1 0 Xin PIN Prescaler Overflow P SCK PIN Doe not 11 SIOST Start Clock CONTROL Y SIOSF clear Complete SPI overflow lt 31 CIRCUIT Octal Counter 3 bit Serial communication Interrupt SCK 1 0 IOSW SOPIN SIPIN Input shift register Internal Bus Figure 19 1 SPI Block Diagram Serial I O Mode Register SPIM controls serial I O func tion According to SCK1 and SCKO the internal clock or external clock can be selected Serial I O Data Register SPIR is an 8 bit shift register First
155. sh pull 1 Open drain Figure 9 3 Open drain Port Structure December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 9 2 I O Ports Configuration RO Port RO is a 8 bit CMOS bidirectional I O port address Each I O pin can independently used as an input or an out put through the register address RO has internal pull ups that is independently connected or disconnected by ROPU The control registers for RO are shown below In addition Port RO is multiplexed with various special features The control register PSRO address con trols the selection of alternate function After reset this value is 0 port may be used as normal I O port To use alternate function such as External Interrupt rather than normal I O write 1 in the corresponding bit of PSRO ADDRESS 0 RESET VALUE 00000000 RO R07 ROG R05 R04 RO2 R01 ROO RO Data Register ADDRESS 0C1u RO Direction Register RESET VALUE 00000000 ROIO i i i Port Direction 0 Input 1 Output R0 Pull up i ADDRESS 0A5H Selection Register RESET VALUE 000000006 Pull up select 0 Without pull up 1 With pull up RO Open Drain i i ADDRESS 0 0 Selection Register RESET VALUE 000000008 ROOD i i i Open Drain select 0 No Open Drain 1 Open Drain Port ADDRESS 0AA Selection Register 0 RESET VALUE 0000 00 PSRO INTO BUZO
156. t selection XPLLE Oscillator PLL Enable Controll 0 Select fxtin 0 Disable PLL 1 Select fxout 1 Enable PLL XPLLDAT Oscillator PLL Data Register Rw RW RW RW RW RW RW RW Bit 7 6 5 4 3 2 1 0 XPLLFD2XPLLFD t XPLLFDGXPLLPSZXPLLPS fi XPLLPSq ADDRESS 09 INITIAL VALUE 000000g XPLLFD Oscillator PLL Feedback Divider Control XPLLPS Oscillator PLL Post Scaler Control 000 fyco 32768 fxin 978 32 047Mhz 000 fout fvco 1 001 fout fyco 2 010 fout fvco 22 011 fout fvco 23 100 fout fvco 24 101 fout fvco 25 110 fout fuco 2 111 fout fuco 7 28 Note 1 After reset the oscillator PLL block is disabled and fxtin is selected for the fxt with the XPLLCR 00 2 It should be written to the XPLLCR 1 0 with an 11 to use the oscillator PLL output frequency fout as system clock 3 If the oscillator PLL block is disabled with the XPLLE 0 the current through the oscillator PLL block should be under 1uA 4 The oscillator PLL block should be disabled by software before entering power down mode STOP mode Figure 25 1 OSCILLATER PLL CIRCUIT Diagram December 3 2012 Ver 1 03 123 MC81F8816 8616 25 1 External PLL Circuit A External connection for normal PLL is shown in Figure 25 2 PLLC MCU 0 47uF 5 5V 21 124 SEMICONDUCTOR Figure 25 2 External Circuit December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 26 RESET The MC81F8816 8616 have has fou
157. ta Retention 10 years 512 Bytes On chip Data RAM 40 bytes Display RAM 32 MHz PLL Oscillator Instruction Cycle Time 167ns at 12MHz NOP instruction LCD display controller 1 4 Duty Mode 40Seg x 4Com 1 3 Bias 1 8 Duty Mode 36Seg x 8Com 1 4 Bias Four 8 bit Timer Counter They can be used as two 16 bit Timer Counter One 7 bit Watch Dog Timer December 3 2012 Ver 1 03 One 21 bit Watch Timer 1 minute interrupt available One 8 bit Basic Interval Timer One 6 bit Buzzer Driving Port Dual Clock Operation Main Clock 400kHz 12MHz Sub Clock 32 768kHz Main Clock Oscillation Crystal Ceramic Resonator Internal Oscillation 8 2 4 2 Operating Temperature 40 85 C Built in Noise Immunity Circuit Noise Filter BOD Brown out Detector Power Down Mode MC81F8816 8616 Main Clock STOP SLEEP SUB Active mode 400kHz to 12MHz Wide Operating Frequency On Chip POR Power On Reset and BOR Brown Out Reset Internal Resistor for LCD Bias 56 48 Programmable I O Pins 31 MC81F8816 1 1 with SEG COM 24 MC81F8616 with SEG COM 24 8 5 channel 10 bit On chip A D Converter MC81F8816 8 channel ADC MC81F8616 MC81C8616 5 channel ADC 2 SEMICONDUCTOR Two 10 bit High Speed PWM Output 16 Interrupt sources External Interrupt 4 Timer 4 UART 2 12C SPI ADC WDT WT BIT
158. tal display LCD and its control circuit The segment common driver directly drives the LCD panel and the LCD controller generates the segment common signals according to the RAM which stores display data VCL3 VCLO voltage are made by the internal bias resis tor circuit The MC81F8816 8616 has the segement output port 36 pins SEGO SEG35 and Common output port 8 pins COMO COM7 If the LCDDO bit of LCR is set to 1 COM7 is used SEG39 SEG36 The Figure 18 1 shows the configuration of the LCD driv er Display Memory 460H 487H 40bytes SEGo Display Data Select Control WTMR 2 0 000 001 fmain 28 010 lt fmain 2 INTERNAL BUS LINE clock Display Data Buffer register Segment Common Driver 128 BL 9 256 pote Prescaler Timing Control Select clock LCD SEG35 SEG27 In MC81F8616 SEG36 COM7 SEG37 COM6 LCDEN gt Control Register SEG38 COMs5 Select Duty LCR OB2H LCD Driver Power Circuit SEG39 COM4 cov2 como Figure 18 1 LCD Driver Block Diagram 88 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 18 1 Control of LCD Driver Circuit The LCD driver is controlled by the LCD Control Register LCR The LCR 1 0 determines the frequency of COM signal scannin
159. ternal Reset in put pin In this case the external reset circuit should be con nected to RESET pin If external reset is not needed not only but also R47EN option should be checked December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 27 Brown out Detector BOD The MC81F8816 8616 has an on chip BOD Brown out Note If the STOP mode is used in the program BOD Detector circuitry to immunize against power noise The function should be disabled in the initial routine of soft BOD control register BODR can enable or disable the built ware in reset circuitry The Block diagram of BOD is shown in the Figure 27 1 MSB LSB BODR BOD RW RW RW RW RW RW RW RW DDRESS OE5 Control Register I HESR g TRM2 AD_REFB TRM1 TRMO BIS2 BIS1 BISO INITIAL VALUE 0100 0000g BOD ENB BOD disable 0 BOD Enable BIS 2 0 BOD Detection Level 1 BOD Disable TRM 2 0 Detection Level Trim selection 000 2V typical 000 Detection Level d 0 2V TBD 001 2 4V typical AD REFB Disable self bias check reference J 001 Deteccion own 010 2 5V typical 0 Enable self bias check reference voltage operation 010 Detection Level down 0 105V TBD 01 T 2 7V typical 011 Detection Level down 0 052V TBD 100 2 9V typical 1 Disable self bias check reference voltage operation 100 Default 101 3 2V typical 101 Detection Level
160. tion while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion 4 AVref pin input impedance A series resistor string of approximately 10KQ is connect ed between the AVref pin and the Vss pin Therefore if the output impedance of the reference voltage source is high this will result in parallel connection to the series resistor string between the AVref pin and the Vss pin and there will be a large reference voltage error Note If the AVggr voltage is less than Vpp voltage and an lalog input pins ANX shared with various alternate func tion are used bidirectional I O port the leakage current may flow Vpp pin to AVggr in output high mode or an lalog input pins ANX to AVggr in input high mode December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 16 BUZZER OUTPUT FUNCTION The buzzer driver consists of 6 bit binary counter the buzzer driver register BUZR and the clock selector It gen erates square wave which is very wide range frequency 500 Hz 125 kHz at fMAIN 4MHz by user programma ble counter Pin R04 BUZO is assigned for output port of Buzzer driver by setting the bit BUZO of Port Selection Register0 P
161. transmit operation The same address is assigned to TXSR and the receive buffer register RXBR A read operation reads values from December 3 2012 Ver 1 03 RXBR Receive Buffer Register RXBR This register is used to hold received data When one byte of data is received one byte of new received data is transferred from the receive shift register When the data length is set as 7 bits re ceived data is sent to bits 0 to 6 of RXBR In this case the MSB of RXBR always becomes 0 RXBR can be read by an 8 bit mem ory manipulation instruction It cannot be written Note The same address is assigned to RXBR and the tansmit shift register TXSR During a write operation val ues are written to TXSR Asynchronous serial interface mode control reg ister ASIMR This is an 8 bit register that controls asynchronous serial interface UART s serial transfer operation ASIMR is set by a 1 bit or 8 bit memory manipulation instruction Baud rate generator control register BRGCR This register sets the serial clock for asynchronous serial inter face BRGCR is set by an 8 bit memory manipulation instruction 111 ABOV MC81F8816 8616 SEMICONDUCTOR RW RW RW RW RW RW 7 6 5 4 1 o0 ADDRESS 0B8H ASIMR PS1 PSO RXM Operation modej 00 Operation stop R12 R13 01 UART mode Receive only 10 UART mode Transmit only 11 UART mode Transmit and receive PS
162. turer for appropriate values of external components In addition see Figure 24 2 for the layout of the crystal Note Minimize the wiring length Do not allow the wiring to intersect with other signal conductors Do not allow the wir ing to come near changing high current Set the potential of the grounding position of the oscillator capacitor to that of Vss Do not ground it to any ground pattern where high cur rent is present Do not fetch signals from the oscillator 122 Xour Figure 24 2 Layout of Oscillator PCB circuit December 3 2012 Ver 1 03 SEMICONDUCTOR ABOV MC81F8816 8616 25 PLL The phase locked loop PLL is used to a fixed frequency lection circuit Feedback divider phase comparator using a phase difference comparison system Phase Locked Loop VCO and Post scaler Figure 25 1 shows the PLL block diagram PLL consists of 8 bit XPLLCR register and XPLLDAT As shown in Figure 25 1 the PLL consists of an input se WT gt fxt fxtin Selector Phase Looked fvco fout vco Post Scaler Loop XPLLE Feedback XPLLPS FXTS Divider XPLLFD XPLLCR Oscillator PLL Controll Register R W R W R W R W R W R W R W R W Bit IM MEE HMM RE NOE i ADDRESS 09AH FXTS i XPLLE INITIAL VALUE 008 FXTS fx
163. u 4u 8u 16u 32u 64u 128u 256u 512u 1 024m Figure 10 1 Block Diagram of Clock Generator December 3 2012 Ver 1 03 51 SEMICONDUCTOR MC81F8816 8616 NBOV The SCMR should be set to operate by main oscillation 001 to select main oscillation Bit2 and bitO of the SCMR should be set to 000 or SCMR System Clock Mode Register MSB LSB oe ADDRESS 0E7 H oL em INITIAL VALUE 000 OL CS 1 0 CPU clock selection 00 main clock 01 main clock 10 sub clock fsub 11 Setting prohibited MCC Main Clock Oscillation Control 0 main clock oscillation possible 1 main clock oscillation stopped 52 Figure 10 2 SCMR System Clock Mode Register December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR 11 BASIC INTERVAL TIMER The MC81F8816 8616 have one 8 bit Basic Interval Timer that is free run and can not stop Block diagram is shown in Figure 11 1 The Basic Interval Timer Register BITR is increased ev ery internal count pulse which is divided by prescaler Since prescaler has division ratio from 8 to 1024 the count rate is 1 8 to 1 1024 of the oscillator frequency After reset the BCK bits are all set so the longest oscillation stabiliza tion time is obtained It also provides a Basic interval timer interrupt BITF The count overflow of BITR from FFy to 00g causes the MC81F8816 8616 interrupt to be generated The Basic
164. ub Main Active Sub Active Mode ES ON ZSION LAON Main Stop or Oscillation Y Sub Oscillation System Clock Stop Stop Sleep LDM SCMR 01H Note1 Note2 Mode 1 A n 3 2 2 8 lt lt A 8 N N M Main Stop Sub Oscillation System Clock Sub z Sub Active Mode lt Mode 2 Note1 Stop released by Reset Key Scan Watch Timer interrupt Timer interrupt event counter and External interrupt Note4 CLR1 SCMR 2 Main osc ON NOP NOP Required osc stabilization time NOP LDM SCMR 01H Note2 Sleep released by Reset or All interrupts Note3 1 stop mode admission LDM SSCR 5AH STOP 2 sleep mode admission LDM SSCR 0FH Sub clock cannot be stopped by STOP instruction Figure 22 1 Operating Mode December 3 2012 Ver 1 03 115 MC81F8816 8616 22 1 Operation Mode Switching Shifting from the Normal operation to the SLEEP mode By writing into SSCR which will be explained in 23 1 SLEEP Mode on page 117 the CPU clock stops and the SLEEP mode is invoked The CPU stops while other peripherals are operate normally The way of release from this mode is RESET and all avail able interrupts For more detail See 23 1 SLEEP Mode on page 117 Shifting from the Normal operation to the STOP mode By writing 5 into SSCR and then executing STOP in stru
165. up 0 052V TBD 110 3 6V typical 110 Detection Level up 0 105V TBD 111 Detection Level up 0 157 V TBD MSB LSB LBCR LCD Bias RW RW RW RW RW RW RW RW Control Register ADDRESS RESET VALUE 01111000B CTR 8 iCTR DSSiCTR DSZCTR DS1CTR DSO YS BODSYS BOD BOD BOD ENB SYS BOD 1 0 Mode selection of BOD Result BOD BOD Flag amp 00 Reset mode 0 BOD No Detect AD REFB 01 no operation mode oniy BIF setting 1 BOD Detect 10 Freeze mode 11 no operation mode oniy BIF setting BOD_ENB_p STOP eae Low Level nternal Reset Voltage comparator 32us Noise Operation Signal Selector PS7 mode BIF setting d Canceller Selector Resistor Array Freeze Mode Sub CLK BOD ENB LCR T ENP y TOP V Vss AD_REFB STOP AD_REFB dL Self Bias Reference Check Reference Voltage Source Figure 27 1 Block Diagram of BOD Brown out Detector Reset December 3 2012 Ver 1 03 127 MC81F8816 8616 The BOD of MC81F8816 8616 has 8 detection level which can be selected by BIS 2 0 and each level can be trimmed by TRM 1 0 The NC_SEL bit of BODR is used for selecting BOD noise canceller For example if the NC_SEL bit of BODR is set to 1 and VDD voltage falls below the BOD detection level during 20us BOD does not generates internal reset signal or freeze mode signal because the 32us noise cancel ler
166. ure 20 5 Acknowledge transfer on I2C bus 20 5 Syncronization Arbitation All masters generate their own clock on the SCL line to transfer messages on the I2C bus Data is only valid during the HIGH period of the clock A defined clock is therefore needed for the bit by bit arbitration procedure to take place Clock synchronization is performed using the wired AND connection of DC interfaces to the SCL line This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and once a device clock has gone LOW it will hold the SCL line in that state until the clock HIGH state is reached see Figure 20 6 However the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period The SCL line will therefore be held LOW by the device with the longest LOW period Devices with shorter LOW periods enter a HIGH wait state during this time When all devices concerned have counted off their LOW period the clock line will be released and go HIGH There will then be no difference between the device clocks and the state of the SCL line and all the devices will start counting their HIGH periods The first device to complete its HIGH peri od will again pull the SCL line LOW In this way a syn chronized SCL clock is generated with its LOW period December 3 2012 Ver 1 03 determined by the device with the longest clock LOW pe
167. utput 2 R23 AN3 Analog Input Port3 R53 SEG3 Segment Output 3 R24 ANA Analog Input Port4 R54 SEGA Segment Output 4 R25 AN5 Analog Input Port5 R55 SEG5 Segment Output 5 R26 6 Analog Input Port6 R56 SEG6 Segment Output 6 R27 Analog Input Port R57 SEG7 Segment Output 7 Note R25 AN5 R27 AN7 are not supported in MC81F8616Q 64pin R40 R47 R4 is a 6 8 bit CMOS bidirectional I O port 6 bit I O port at MC81F8616Q Each pins 1 or 0 written to the Port Direction Register can be used as outputs or in puts Also pull up resistors and open drain outputs can be assigned by software In addition R4 serves the functions of the various follow ing special features Port pin Alternate function R40 R41 INT3 External Interrupt 3 Request input R42 R43 SXIN R44 SXouT R45 XIN R46 XOUT R47 RESET Note R40 R41 are not supported in MC81F8616Q 64pin R50 R57 R5 is an 8 bit CMOS bidirectional I O port or LCD segment output Each pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs And each pins can also be set in segment output mode in 1 bit December 3 2012 Ver 1 03 R60 R67 R6 15 an 8 bit CMOS bidirectional I O port or LCD segment output Each pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs And each pins can also be set in segment output mode in 1 bit units by R6PSR Register Po
168. ve supply voltage via a current source or pull up resistor When the bus is free both lines are HIGH The output stages of devices connected to the bus must have an open ABOV SEMICONDUCTOR drain or open collector to perform the wired AND function Data on the DC bus can be transferred at rates of up to 100 kbit s in the Standard mode up to 400 kbit s in the Fast mode or up to 3 4 Mbit s in the High speed mode The number of interfaces connected to the bus is solely depen dent on the bus capacitance limit of 400 pF For informa tion on High speed mode master devices IICE RESV WRE SPIE WTIMi STT SPT TICE lt SDA R16 noise G canceller 60ns noise canceller SDAOUT 15ns SDAOUT CONTROLLER Vss SCL R17 noise O canceller 50ns SCLIN noise SCLOUT canceller lt _ 5ns Ws SCLOUT CONTROLLER MSTS ALD EXC TRC STD SPD 2 data in shift register SHFTR I2C slave address register SVADR I2C data out register PIPER I2C clock control register CLKCR Figure 20 1 12 Block Diagram 102 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR MC81F8816 8616 I2CMR I2C Mode Control Register R W R W R W R W R W R W Bit 7 6 5 4 3 2 I2CE RESV i WREL WTIM i I2CE I2C Enable WREL cancel wait 1 acknowledge I2CSR I2C Status Register Bit 7 6 5 MSTS master device status EXC g
169. vice task is terminat ed upon execution of an interrupt return instruction RETI Interrupt acceptance 1 The interrupt master enable flag I flag is cleared to 0 to temporarily disable the acceptance of any follow ing maskable interrupts When a non maskable inter rupt is accepted the acceptance of any following interrupts is temporarily disabled ABOV SEMICONDUCTOR 2 Interrupt request flag for the interrupt source accepted is cleared to 0 3 The contents of the program counter return address and the program status word are saved pushed onto the stack area The stack pointer decreases 3 times 4 The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter 5 The instruction stored at the entry address of the inter rupt service program is executed Instruction Fetch Address Bus Data Bus Internal Read Internal Write V L and V H are vector addresses Sysemcock LJ LJ LJ LJ LJ LJ LI LI LI LI vu a Interrupt Processing Step gt lt Interrupt Service Routine ADL and ADH are start addresses of interrupt service routine as vector contents Figure 17 3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Basic Interval Timer Vector Table Address Entry Address OFFE2u OFFE3H Correspondence between vector table address for BIT interrupt an
170. x x x Bit Manipulation Not Available Period High Duty High T1PPR 8 bit T1 8 bit ITIPDR T1PDR 8 bit X The value 0 or 1 corresponding your operation PWMOE TOO ROO PWMO TOO gt 5 PWM00 PSR0 0 POL Figure 12 16 PWM0 Mode December 3 2012 Ver 1 03 69 MC81F8816 8616 Note If the duty value and the period value are same the PWM output is determined by the bit POL1 1 High 0 Low And if the duty value is set 00 the PWM output is determined by the bit POL1 1 Low 0 High The period value must be same or more than the duty value and 004 cannot be used as the ABOV SEMICONDUCTOR period value Frequency Resolution T3CK 1 0 T3CK 1 0 T3CK 1 0 200 250nS 01 500nS 10 2uS 10 bit 3 9kHz 1 95kHz 0 49kHz 9 bit 7 8kHz 3 9kHz 0 98kHz 8 bit 15 6kHz 7 8kHz 1 95kHz 7 bit 31 2kHz 15 6kHz 3 90kHz Table 12 2 PWM Frequency vs Resolution at 4MHz Bit 7 6 5 4 3 POL i 16BIT PWM1E X 0 1 0 x T3PWHR x T3CK1 i T3CKO X x x IPWM1HR3PWM1HR2IPWM1HRTPWM1HRO0 2 1 0 ADDRESS 008 i T3CN T3ST RESET VALUE 00 ADDRESS 0DBu RESET VALUE 0000 X X X Bit Manipulation Not Available T3PWHR 3 2 T3ST 0 Stop 1 Clear and Start TO clock source Period High SCMR 1 0 Duty High X The value 0 or 1
171. y 11 2010 The block diagram of LCD Bias is modified in Figure 18 3 LCD Bias Control The figures of flash writer were updated in 1 OVERVIEW on page 1 Config Read Voltage VconFiIG maximum VDD Start Voltage VsTART and description were added in 7 3 DC Electrical Characteristics on page 22 In case AVREF voltage was less than VDD voltage for ADC the table note and note were added in 7 5 A D Converter December 3 2012 Ver 1 03 3 MC81F8816 8616 ABOV 4 December 3 2012 Ver 1 03 ABOV SEMICONDUCTOR Table of Contents 1 OVERVIEW 1 DESCHIPTIOMN EE 1 Features nra uu ex e UM Qa ua asta kaqa 1 Development Tools 3 Ordering Information 5 2 BLOCK DIAGRAM eene 6 MC81F8816Q 80 pin package 6 MC81F8616Q 64 pin package 7 3 PIN ASSIGNMENT 2 8 4 PACKAGE DIAGRAM 10 5 PIN FUNCTION esee 12 6 PORT STRUCTURES 16 7 ELECTRICAL CHARACTERISTICS 21 Absolute Maximum Ratings 21 Recommended Operating Conditions 21 DC Electrical Characteristics 22 LCD Characteristics 23 A D Converter Chara

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