Home

PowerDAQ User Manual - United Electronic Industries

1. 78 81 buffer done 78 81 89 buffer ertror esne nr i ih 78 81 buffer wrapped sss 81 checkng oes 78 166 frame done ssssseeeee 78 80 frame recycled ssssssssss 82 PAVATE ed odere ttes 83 Status bits nent tn le 77 Stop trigger 81 Event counter 103 Event handler sess 89 91 Event mode 43 Example programs 109 F FIFO upgrades 13 Filter highpass ssh 150 ln Dt cscs 150 dcin PEE RNA 64 148 SIZE oe eT RI RR 80 u read ei eR t ER 81 FSMLabs 22e 146 G Gain option MFS boards 13 Gains banni Eder P et 46 H option 8 40 46 L option 8 40 46 impact on rates 133 Gains MF Series 8 Gated mode PDL MF sosssssssseeeeesseseess 59 GlOSsSaEy em eet 153 H Hardware installation 17 I Immediate Update 68 Input impedance eee 51 Input mode Differential eene nu 49 Pseudodtfferenta 48 Single ended sss 48 Input ranges eek oie Ro RORIS 45 Installation multiple boards 22 IntettUDis doeet tore RHET 23 J J2 Glocks on ttes 57 L Lab Board 14 LabVIEW for Linux support 111 LabVIEW Real Time support 0 111 LabVIEW support 111 LabWindows CVI support 111 Lateh be Ene den EE 97 Libraries eene ette 143 Life Support Policy 151
2. K Loal Data Bus 3 Digita Out put Driver Andog K Dan Output gt Amplifiers kK pact Weel Gonfiguration AOut Calibration Voltage Motorola 66MHz DSP 56301 amp GER DAS Re erence Bus Master PO Interface L 32 Bit Fd Bus Figure 4 3 PowerDAQ PDL MF block diagram AOut A FO AOut Q ock Addres The heart of each board in the MF MFS Series is a Motorola 56301 a 66 MHz DSP That device ensures a highly efficient interface with the PCI PXI bus and it also provides control over all board subsystems The Analog Input subsystem includes e Aninput multiplexer Mux selects which channels to acquire The Channel List FIFO contains a list of each channel to be acquired along with its gain the subsystem reads this data and sets up the input mux accordingly PD2 MFS boards have per channel sample hold amplifiers S Hs preceding the mux The S Hs acquire a signal from all input channels simultaneously and then hold the acquired voltages while the A D digitizes them channel by channel e A Programmable Gain Amplifier PGA increases the level of an input signal in order to provide an adequate voltage to the A D The PGA s level of amplification depends on the board model and can be software selected on a per channel basis Models in the MF 39 4 PowerDAQ Architecture Series come with one of two sets of amplification levels For low level signals that need considera
3. Q Acquisition stopped Table 5 4 External trigger modes If you prefer to use an external clock you apply it to Pin 29 on the J2 connector also Pin 26 on the J1 connector This line as are all logic inputs on the board is supplied with a 4 7 KQ pull up resistor Note though that this pin also serves as the input for the Analog Output subsystem s external clock input and obviously you can t use that line for both purposes at the same time The external trigger input on a PowerDAQ board is edge sensitive that is you can trigger the acquisition to begin on either a rising or falling edge by setting the appropriate configuration bits in the dwAInCfg word in the _PdAlnSetCfg function Generally data acquisition begins immediately upon a trigger signal In some cases however it s desirable to have analog pretriggering examining input levels to trigger an acquisition run and then retrieving data that led up to an external event or analog posttriggering starting data collection after one of the inputs reaches a certain level In the analog input subsystem such functionality must be implemented in the user application with the Advanced Circular Buffer see Appendix E Note also that digital pretriggering is not possible Software can examine the value of incoming samples and compare them to a setpoint Many third party applications include built in functions for this task among them are LabVIEW DASYLab DIADem TestPoint
4. cccceecceeseeeseeeseeseeeteeesees 139 Realtime Linux cc eceeseeeseeeeeeteeeees 146 Recycled mode 70 Recycled buffer mode 82 La E EE 146 RL oeren 20 S S H amplifiers sse 54 Sandwich format DI 20 Scaling raw readings sss 71 SCAM i 64 Schmidt trigger 41 Screw terminal panels 137 Sense ee sce entes tee ae 97 Sequential sampling e seeseeseeeeeseeees seee 52 Signal conditioning options 140 Simple Test program 35 Simultaneous sampling 52 54 settling time issues 56 167 Single Buffer mode 70 Single scan operation ssseeseesesseeessseeeesee 73 Single ended sss 48 KO Wistert sree ni He Mh dures 52 Sleep Modes i eene es 80 Slow Bit aeter 46 75 133 Software installation 16 Software Suite 141 Solid state relay modules 140 Specifications sss 113 PD2 MF Series 114 PD2 MFS Series 118 PDL MF Board 122 PDXI MF Series 124 PDXI MFS Series sssses 128 Squarewave Generator 103 Start trigger ii csset 59 Stop trigger csse eae 59 Strain gages esae tse 140 Strain gauges eee 50 Synchronization sss 88 cable iot he en nn 22 CODDECLOF wave ccce teo ertet eee 31 multiple boards
5. Table 5 2 Programmable Gains Channel List Often you want to sample only over a certain subset of channels sample them in various orders or apply different gains to each channel These options are all possible with an A D Channel List which you create with the PdAJnSetChList command It is mandatory that you create a channel list otherwise the board will not collect the correct data The Channel List is resident in the on card memory known as the Channel List FIFO and thus must be programmed every time you power up the card It contains from one to 256 entries 64 entries maximum on the PDL MF Each reading of the full list is called a scan Configuration data for each entry includes the channel number gain and Slow Bit setting A Channel List remains active until you overwrite it with a new set of entries Writing a Channel List with 0 entries clears the list To effectively change the sampling rate of just one channel make multiple entries for it in the Channel List instead of reading it just once per scan You can use averaging over several scans to increase the effective resolution and reduce noise For applications where the dc value is crucial consider using a software filter that consists of an averaging window over an array of averages Each time you calculate the average value of a channel you put it into an array and if that array is already full you replace the oldest one Then your program calculates the average val
6. 16 8192 8192 4096 32 8192 8192 4096 64 8192 8192 4096 Table 5 6 Default Bus Mastering parameters for various FIFO sizes Our tests show that with the maximum number of boards tested simultaneously four boards this mode achieves rates of 3M samples sec per board With a 1 GHz CPU the load per board at this rate is less than 5 3b Bus Master Short Burst We developed this mode to accommodate industrial PCs with secondary bridges on the PCI bus and that don t properly handle PCI Abort errors and where a bus lockup can occur In this mode the firmware shortens the number of 32 bit transfers per master cycle from 32 to 8 and if the firmware encounters PCI Abort termination it retransmits the burst completely In this mode our tests show transfer rates of 1 3M samples sec per board again with four boards running simultaneously The CPU load per board using this mode is 395 Some legacy PowerDAQ PD2 MF MFS boards cannot guarantee sustained bus mastering operation especially on some PCs with a secondary PCI bridge such as large industrial PCs or on machines with a PCI bus extender You can identify these boards by going to the PowerDAQ Control Panel applet Ver 3 13 or higher and checking which version of the Motorola DSP is on the board a version 2 DSP indicates a board in this legacy category You can examine a PowerDAQ board s data transfer mode settings by going to the PowerDAQ Control Panel applet In the screen
7. 114 Appendix A Specifications Analog Outputs all PD2 MF models Number of Channels 2 Resolution 12 bits Update Rate 200k S sec each Onboard FIFO Size 2k samples on DSP Analog Output Range 10V Error Gain 1 LSB Zero Calibrated to 0 Current Output 20 mA max Output Impedance 0 30 typ Capacitive Drive Capability 1000 pF Nonlinearity 1 LSB Protection Short circuit to analog ground Power on Voltage OV 10 mV Setting Time to 0 01 of FSR 10 usec 20V step 1 psec 100 mV step Slew Rate 30 V usec Counter Timer all PD2 MF models Number of Counters 3 available to user Intel 82C54 Resolution 16 bits on each counter Clock Inputs Software configurable Internal 1M S sec External lt 10M S sec High level Input voltage 2 0V min Low level Input voltage 0 8V max High level Input current 20 pA Low level Input current 20 pA Gate Inputs Maximum Pulse Width 100 nsec High 100 nsec Low Counter Outputs Inverted Output Driver High Voltage Output Driver Low Voltage 2 5V min IOH 24 mA 0 55V max IOH 48 mA 115 Appendix A Specifications 116 Digital I O all PD2 MF models Input Bits 16 8 can generate IRQ Output Bits 16 Inputs High level Input Voltage 2 0V min Low level Input Voltage 0 8V max High level Input Current 20 pA Low level Input Current 20 pA Outputs
8. r3 Buffer Tail Buffer Tail Frame Markers c CEN Figure E 1 Advanced Circular Buffer The application can be synchronized to the acquisition process by either timer notification or by an event from the driver notifying that a certain sample count boundary has been passed In order to receive notification on a sample or scan count boundary the buffer is segmented into frames Whenever the data transferred to the buffer crosses a frame boundary the driver sends an event to the application This event wakes up the application thread that is responsible for processing data in the buffer To keep the frame boundaries at fixed buffer locations the buffer size should be a multiple of the frame size If multichannel acquisition is performed then the frame size should also be a multiple of the scan size Doing so keeps the pointer arithmetic from becoming unnecessarily complex With the ACB three modes of operation are possible e Single Buffer e Circular Buffer e Recycled Circular Buffer In all three modes data is written to the beginning of the buffer at the start of acquisition The three modes differ in what is done when the end of the buffer is reached and if the buffer head catches up with the buffer tail 148 Appendix E Application Notes Single Buffer In the Single Buffer mode acquisition stops when the buffer end 1s reached In this mode the application can access the buffer and process the data any time during acq
9. sees 64 Connectors custom pinouts 139 Continuous acquisition essesesss 79 C Control Panel Application 18 C examples ER 109 Conversion clock see CV clock Cables master list 138 Counter timer Calibration certificate s s11se1esee01e100 15 82054 modes etage 104 165 clock sources sess 104 configuration sse 106 delay mode 104 event Tags 106 for A D control 105 gate sources 104 pulse train mode 104 rate mode 104 single pulse mode 104 Counter Timer subsystem 41 Crosstalk eee 51 CX Glock sonne RT 22 57 D DA FIEQ itte hist 40 DASY Lab support 111 Data formats has 71 Data transfers Bus Master standard 66 Bus Master Short Burst 67 Fast mode sss 65 Normal mode 65 Delphi examples 110 Device drivers enanos 142 DG MFS option 13 DIADEM support 111 Differential cannone tentes 49 Digital I O configuration 100 edge detection 100 event handler 5e 100 polled D OX insane roes 98 Digital I O subsystem 41 97 Digital one hot 103 Disk streaming sse 109 Distribution panels sssseseeeeeseeees seene 138 DIMA eere TEE E t 23 E Event acquisition stopped
10. Common Mode Rejection Ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB A software program controlled from an intuitive user interface that creates syntactically correct high level source code in languages such as C or Basic The means to compensate for the ambient temperature in a thermocouple measurement circuit The input range over which a circuit can handle a common mode signal The mathematical average voltage relative to the computer s ground of the signals going into a differential input An application that contains one or more component objects that can freely interact with other component software Examples include OLE enabled applications such as Microsoft Visual Basic and OLE Controls The time in an analog input or output system from the moment a channel is interrogated such as with a Read instruction to the moment that accurate data is available A circuit that counts external pulses or clock pulses timing such as the Intel 8254 device The manner in which a signal is connected from one location to another An unwanted signal on one channel due to an input on a different channel The amount of current a digital or analog output channel can source or sink while still operating within voltage range specifications The ability of a DAQ board to dissipate power from an output signal either analog or digital Some senso
11. Minimum Pulse Width 20 nsec Output High Level 2 0V min 4 mA Output Low Level 0 5V max 4 mA Protection 7 kV ESD 30V overshoot undershoot Input Low Voltage 0 0 0 8V Input High Voltage 2 0 5 0V Appendix A Specifications PDXI MF Multifunction Boards Model PDXI MF xx 2M 14H 1M 12x 500 16x Resolution 14 bits 12 bits 16 bits Number of Channels Single Ended 16 or 64 Differential 8 or 32 Maximum Sampling Rate 2 2M S sec 1 25M S sec 500k S sec Onboard FIFO Size 4k samples 2k samples upgradeable to 16k 32k 64k Channel Gain List 256 entries Input Ranges 0 5V 5V 0 5V 0 10V 5V 10V 0 8V 8V software selectable 10V ranges Programmable Gains by channel H 1 2 4 8 L 1 10 100 1000 H 1 2 4 8 Drift Zero 30 pV C Gain 30 ppm C Input Impedance 10 MO Input Bias Current 20 nA Input Overvoltage 20V 2000V ESD 10 35V continuous mA max A D Conversion Time 0 45 usec 0 8 usec 2 usec A D Settling Time 0 37 psec 0 6 usec 1 2 usec DC Accuracy Nonlinearity 2 LSB 0 5 LSB 1 LSB System Noise 1 2 LSB 0 3 LSB 1 3 LSB AC Accuracy Effective Number of Bits 12 2 11 63 14 5 Total Harmonic Distortion 76 dB 71 8 dB 88 dB Nonlinearity Noise Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 2200k S sec 1 ch 1250k S sec 500k S sec Ag
12. PowerDAQ User Manual PD2 PDXI MF Series Multifunction DAQ Boards PD2 PDXI MFS Series Simultaneous Sampling DAQ Boards PDL MF Lab Series Multifunction DAQ Boards March 2006 Edition PN PDAQ MAN MFX Rev 6 0 0 Copyright 1998 2006 United Electronic Industries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission March 2006 Printing Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies Contacting United Electronic Industries Mailing Address 611 Neponset St Canton MA 02021 U S A Support Telephone 781 821 2890 Fax 781 821 2891 Also see the FAQs and online Live Help feature on our web site Internet Access Support support ueidaq com Web site www ueidaq com FTP site ftp ftp ueidaq com ii Table of Contents T It OCU COO i s ieu eec eset nono ena sune in etat aee aaa eoo catenseveceaccacseesdevsoseacsoecssessveoce Who Should read this manual sentis er Ete m E D Cereris 1 Con venti Ons E 2 Organization of this manual tp ie ee e 3
13. Single update Buffered Waveform Generation e Method B Single shot waveform generation e Method C Continuous waveform generation e Method D Repetitive waveform generation Non buffered Waveform Generation backward compatibility e Method E Auto regeneration e Method F Events in non buffered mode Single value update method Single update Method A The single update method uses an API command from the user program to write the digital representation of the desired analog output value directly into the output register of a D A converter This digital word remains in the output register indefinitely until you overwrite it with a new value The maximum rate at which you can update the actual analog output generated from the D A depends on the configuration of the host PC system but it is at least 1 kHz Buffered waveform generation methods When you are working with waveforms whose shape you know in advance it is possible to calculate the corresponding values for the D A s output register and send multiple datapoints to the analog output subsystem all at once There are several ways to transfer these points Single shot waveform generation Method B This method outputs the waveform only once and then the subsystem stops 84 6 Analog Output Subsystem Continuous waveform generation Method C This method allows the continuous generation of waveforms and there is no limit to the total amount of data the system can
14. all PD2 MFS models Number of Counters 3 available to user Intel 82C54 Resolution 16 bits on each counter Clock Inputs Software configurable Internal 1M S sec External 10M S sec High level Input voltage 2 0V min Low level Input voltage 0 8V max High level Input current 20 pA Low level Input current 20 pA Gate Inputs Maximum Pulse Width 100 nsec High 100 nsec Low Counter Outputs Inverted Output Driver High Voltage Output Driver Low Voltage 2 5V min IOH 24 mA 0 55V max IOH 48 mA 119 Appendix A Specifications 120 Digital I O all PD2 MFS models Input Bits 16 8 can generate IRQ Output Bits 16 Inputs High level Input Voltage 2 0V min Low level Input Voltage 0 8V max High level Input Current 20 pA Low level Input Current 20 pA Outputs Output Driver High Voltage Output Driver Low Voltage 2 5V min 3 0V typ IOH 32 mA 0 55V max IOL 64 mA Current Sink 32 64 mA max 250 mA per port Pulse Width 20 nsec min interrupt bit latched on rising falling or either edge Power on Voltage Logic Zero General Specifications and Connectors all PD2 MFS models Power Requirements 5V Physical Dimensions 10 5 x 3 8 262 x 98 mm Environmental Operating Temperature Range Storage Temperature Range Relative Humidity 0 to 70 C 25 to 85 C to 95 noncondensing Conn
15. ss 46 T ble 5 3a Channel List format 4 2 ceat AA b en opa eroe Potete 47 Table 5 3b Programmable gain codes 47 vi List of Tables and Figures Figure 5 1 Wiring for single ended and pseudodifferential inputs sss 49 Figure 5 2 Wiring for differential inputs essent eene 50 Figure 5 3a Analog front end of a PowerDAQ MF Series board ssesssess 53 Figure 5 3b Acquisition sequence for multiplexed inputs on ME Series ap PDL boatrdS eta etii e eE te eere as ententes 53 Figure 5 4a Analog front end on PowerDAQ MFS simultaneous sampling boards with both SE and DI modes available sssssssssseseee 55 Figure 5 4b Acquisition sequence for simultaneous inputs using S H amplifiers on MFS Series boards 56 Table 5 4 External trigger modes ses 60 Table 5 5 Possible clocking combinations the shaded rows at the bottom indicate rarely used combinations essen 63 Table 5 6 Default Bus Mastering parameters for various FIFO atzes eee 67 Figure 5 5 Control Panel applet with typical PowerDAQ board settings eseeeeeeeereeeeeeeeee 68 Figure 5 6 Advanced Circular Buffer ss 69 Figure 5 7a PowerDAQ 16 bit data format esses 71 Figure 5 7b PowerD AQ 14 bit data format 71 Figure 5 7c PowerDAQ 12 bit data format ss 71 Table 5 8 Bit weigh
16. 14 bit A D 4 SE simultaneous inputs two 12 bit D As PD2 MFS 8 2M 14 2M samples sec 14 bit A D 8 SE simultaneous inputs two 12 bit D As PD2 MFS 4 1M 12 1M samples sec 12 bit A D 4 SE simultaneous inputs two 12 bit D As PD2 MFS 8 1M 12 1M samples sec 12 bit A D 8 SE simultaneous inputs two 12 bit D As PD2 MFS 4 800 14 800k samples sec 14 bit A D 4 SE simultaneous inputs two 12 bit D As PD2 MFS 8 800 14 800k samples sec 14 bit A D 8 SE simultaneous inputs two 12 bit D As PD2 MFS 4 500 16 500k samples sec 16 bit A D 4 SE simultaneous inputs two 12 bit D As PD2 MFS 8 500 16 500k samples sec 16 bit A D 8 SE simultaneous inputs two 12 bit D As PD2 MFS 4 500 14 500k samples sec 14 bit A D 4 SE simultaneous inputs two 12 bit D As PD2 MFS 8 500 14 500k samples sec 14 bit A D 8 SE simultaneous inputs two 12 bit D As PD2 MFS 4 300 16 300k samples sec 16 bit A D 4 SE simultaneous inputs two 12 bit D As PD2 MFS 8 300 16 300k samples sec 16 bit 8 SE simultaneous inputs two 12 bit D As Table 2 2 PowerDAQ PD2 MFS Models Note All PD2 MFS Series models also include three counter timers and 32 digital I O lines Note PD2 MFS Series boards provide a dedicated sample hold amplifier S H for each analog input channel These S Hs are integrated into the board s hardware design and do not require any user software pro
17. 2 PowerDAQ ME MES Series Features Overview ssssssssssccssssssssssssssscceees 7 VET VIG West tase hot At cht berets bt aces ba gee aces Uae ots ones hte kth ne nt Ee 7 IW Re 7 Power DAQ e miennes eme ee su cosas eee We o teer ER terme 8 3 Installation and Configuration L5 Before you begin see haine ne ho ne er ete ed utens 15 Installing the software ete eee ee RR HERR p e vite 16 Installing PowerDAQ hardware sise 17 Confirming the installation t eei eH Re p rend 18 Configuring a PowerD AQ board ss 19 Connector Tor PDL ME EE 31 Connectors for PDXI MF S Series boards 33 Simple Test program adesto ot hei dite eie eee eite TN Ri VIE er 35 Calibration e 36 4 PowerDAQ Architecture cccccscorsrsscssssssssosssssscsssssssssscssssscessssssssosscssessess 37 Eunctiotal OVervis ES at stasis hed echt o cce nd US UR ERUIT eR US 37 Programming Model d eure tie ee Ree ie i OE ues 42 5 Analog Input Subsystem ceres eee ee eee e eese teen se eee sesso se ense sess sese essceesss 45 Architecture eH e A He dp DI HE e pn d OC o EG ca d ete eo 45 Input Ranges eco ree EGO REEF EUG RENS aaa CU TEES TENE UR ERU ERU TERRE EAR US 45 Gait Settings ice He n OR DR RENE REND He ENTIRE RE es duree be 46 Channel List EE 46 Input modes coe en n EROR GU ERE tienne ea UNS nes Ua E 47 Sequential vs simu
18. AOB_CVSTARTO0 to use the 11 MHz internal base clock Set the timebase with _PdAOutSetCvClk and use the same calculations to set up the timebase as described in the analog input subsystem Set up an event object _PdAOutSetPrivateEvent Enable the interrupt _PdAdapterEnableInterrupt Set the events about which you wish to be notified PdSetUserEvents and set dwEventsNotify eFrameDone eBufferDone eBufferError eStopped You need these all for event based waveform mode Don t forget to set the subsystem parameter to AnalogOut Write the first block of data PdAOutPutBlock Enable and start analog waveform generation _PdAOutEnableConv using 1 for dwEnable _PdAOutSwStartTrig To start waveform generation with a software command use PdAOutSwStartTrig If you wish to synchronize an analog output with an external trigger set the appropriate flags in_PdAOutSetCfg Note that the flags AOB_STARTTRIGO AOB_STARTTRIG1 AOB_STOPTRIGO and AOB STOPTRIGI have the same functionality as for the analog input subsystem Wait for events and process them using the Win32 API call WaitForSingleObject Event handler Check why the event object was set with PdGetUserEvents 94 6 Analog Output Subsystem Examine the return from this function for these events eFrameDone means that the D A has output a voltage for half the values in the D A FIFO eBufferDone eBufferError means that the
19. LINUX rein nn tin aa 146 Loopback tests 35 Low level signals sss 50 M Mating cables sss 139 MATLAB support 111 Motor controller 103 Mu ltiplexer 4 eite en 39 N Negative delay ssesseessseseeseeserserseeesssee 54 0 Operational test program 35 P P cer clock wt Rs see CV clock PD2 ME Series eH Ed 8 PD2 MFS Series 10 PDEME Sn es 14 OS support eese 142 PDXI Configurator 23 PDXI MF Seties eerte etes 11 PDXI MFS Series 12 Polled 5 usse ear Set eech 43 Polled mode 43 Posttriggering anal g i d ssa n Ed 61 PowerDAQ models 8 PowerDAQ Software Suite 15 16 141 Pretriggering analog osse 61 digitale eU 61 Programmable gain amplifier PGA 39 Programmable rate generator 103 Programming general model 42 opening closing a subsystem 43 OS SUPPORT rames 142 PowerDAQ APT 42 PowerDAQ De 42 PowerDAQ DLLs 142 PowerDAQ include files 144 PowerDAQ language libraries 143 PowerDAQ OS drivers 142 PowerDAQ SDK 16 PowerDAQ SDK structure 141 PowerDAQ Software Suite 15 141 Pseudodifferential sss 48 Pull up resistors 58 60 97 Q ONJ rath dan tette e E Lt Me 146 R Rack mounts
20. Mode constants for use in analog input configuration word Almost every digitization task falls into one of the following categories e Method A Single scan e Method B Burst buffered acquisition 1 shot e Method C Continuous acquisition using Advanced Circular Buffer ACB e Method D Recycled buffer mode Method A Single scan A single scan where you take one reading across the Channel List is useful when you need to get one set of datapoints where a scan might even consist of just one entry in the Channel List Applications such as a multichannel voltmeter or sensor thermocouple monitor are well suited for this method Depending on the Channel List size maximum number of entries equals 256 and maximum board speed you can acquire as many as 100 scans sec in non realtime applications and roughly 10 scans sec in a realtime application You can initiate an acquisition with a software command or by monitoring the external CL Clock The maximum number of samples acquired is less then the minimal size of the A D FIFO so all data stay in that FIFO and there s no need to work with an ACB in host memory 73 5 Analog Input Subsystem The PowerDAQ Software Suite CD ROM contains a large number of functioning sample programs written for various languages They might come close to approximating what you would like an application to do so you might want to take a closer look at them The examples in the SDK that fall into the categor
21. Timeout Event handler Check why the event object was set with _PdGetUserEvents 91 6 Analog Output Subsystem Re enable events with PdSetUserEvents Stop waveform generation Stop asynchronous operation PdAOutAsyncStop PdAOutAsyncTerm Deinitialize the subsystem Release event object handle optional PdAOutClearPrivateEvent Release the buffer _PdReleaseBuffer Clear the subsystem and set both outputs to 0V optional _PdAOutReset Method E Autoregeneration Use this method to create fixed length waveforms 2048 samples maximum or 65536 with external memory without using any host CPU cycles the onboard DSP handles all subsystem operations It s easier than using Method D but the size is limited to the D A FIFO size After an application writes data to the D A FIFO the board starts to output the waveform and the subsystem restarts automatically when the pointer reaches the end of the buffer This method is suitable when you need a continuous repetitive waveform less than or equal to the D A FIFO size Examples in the SDK that fall into the category of Method E are e SimpleTest dpr Initialization Reset the analog output optional _PdAOutReset Set the analog output configuration _PdAOutSetCfg 92 6 Analog Output Subsystem setting dwConfig AOB CVSTARTO AOUB DACBLK0 AOB DACBLKI AOB REGENERATE to use the 11 MHz internal clock for auto
22. e L 3intended for low level signals that might need considerable amplification so gains are typically 1 10 100 and 1000 e H intended for higher level signals that need less amplification so gains are typically 1 2 4 and 8 or 1 2 5 and 10 depending on the model PowerDAQ PD2 MF Series Model Analog features PD2 MF 16 2M 14H 2 2M samples sec 14 bit A D 16 SE 8 DI inputs Gains 1 2 4 8 two 12 bit D As PD2 MF 64 2M 14H 2 2M samples sec 14 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D As PD2 MF 64 1M 12L 1 25M samples sec 12 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 64 1M 12H 1 25M samples sec 12 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D As PD2 MF 16 1M 12L 1 25M samples sec 12 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 16 1M 12H 1 25M samples sec 12 bit A D 16 SE 8 DI inputs Gains 1 2 4 8 two 12 bit D A PD2 MF 16 500 16L 500k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 16 500 16H 500k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 4 4 8 two 12 bit D A 2 PowerDAQ MF MFS Series Features Overview PD2 MF 64 500 16L 500k samples sec 16 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 64 500 16H 500k samples sec 16 bit A D 64 SE 32 DI inp
23. transfer for small amounts of data We recommend that the minimum size of a frame for bus mastering should be 4096 samples Two modes of bus master transmissions are available and you switch between them using the PowerDAQ Control Panel application or the pdDiagSetPrm command mentioned earlier 3a Bus Master standard Bus Master mode is employs a standard method of data transmission over the PCI bus The board transfers samples into locked pages of host memory that are preallocated by the VMM virtual memory manager It moves data over the bus in bursts of 32 transfers each with 32 bits of data Bus Master mode transfers at least 4k samples at a time regardless of the FIFO size Note that the PowerDAQ driver includes a special function call pdDiagSetPrm to adjust bus master operating parameters However the initial page allocation size equals two sets of four pages 4096 samples and that allocation cannot be changed on the fly Boards with larger FIFOs can allocate more memory as much as 16 384 samples in a single contiguous block When the data transfer is complete the board fires an interrupt to the driver A D FIFO Size Bus Master Transfers Bus Master Transfer Size in k bytes when FIFO Half Full Transfers per Normal and Fast samples Interrupt modes k bytes samples 1 512 4096 512 2 1024 4096 1024 4 2048 4096 2048 8 4096 4096 4096 66 5 Analog Input Subsystem
24. 10 0 usec 50 0 usec PDXI MF xx 100 16H 16 100 kHz High 10 0 usec 50 0 usec PDXI MES Series Timing Board Model Resolution Fast Acq Slow Acq SSH Acq SSH Hold Speed Delay Delay using Delay Delay Slow Bits PDXI MFS x 2M 14 14 2 2 MHz 450 nsec 2 0 usec 700 nsec 500 nsec PDXI MFS x 1M 12 12 1 25 MHz 800 nsec 2 0 usec 700 nsec 500 nsec PDXI MFS x 800 14 14 800 kHz 1 25 usec 3 0 usec 900 nsec 700 nsec PDXI MFS x 500 14 14 500 kHz 2 0 psec 3 0 usec 900 nsec 700 nsec PDXI MFS x 333 16 16 333 kHz 3 0 psec 10 0 usec 900 nsec 700 nsec 135 Appendix B PowerDAQ A D Timing 136 Appendix C Accessories UEI supplies a wide range of accessories for the PowerDAQ PD2 PDXI boards They greatly expand the core functionality of standard MF S hardware and allow you to employ these cards in very demanding applications These accessories also provide the means for implementing custom interconnection schemes for OEM applications Screw Terminal Panels PD2 PDXI PD PDXI STP 96 Screw terminal panel with 96 and 37 pin connector suited for boards with as many as 64 analog channels PD PDXI STP 96 KIT Complete kit Includes PD STP 96 PD CBL 96 and PD CBL 37 for 64 channel boards PD PDXI STP 9616 Screw terminal panel with 96 pin and 37 pin connector for 4 8 16 channel boards PD PDXI STP 9616 KIT Complete kit Includes PD STP 9616 PD CBL 96 and PD CBL 37 for 4 8 16 channel boards PD
25. 3 Installation and Configuration Connector pin assignments for J6 The J6 intraboard synchronization connector contains two pairs of clock signal lines e The CV Clock the conversion clock also known as the Pacer clock e The CL Clock the Channel List clock also known as the Scan clock or Burst clock 2 4 6 8 10 11002 O 0 0 0 0 3 D 4 ojopjojojo 50e 13579 7 iB 8 Figure 3 11a Physical layout of J6 on PD2 MF S Series boards Fig 3 11a gives a view looking into the connector socket mounted on the board The J6 connector on full slot MF S boards uses an 8 pin connector for J6 whereas the newer sandwich boards generally use a 10 pin connector Furthermore the PD CBL SYNC synchronization cable is equipped with 10 position connectors When using this 10 pin cable on an 8 pin connector leave the two lowest holes pins 9 and 10 free CV START OUT 2 oGND CL START OUT DGND CV START IN DGND CL START IN 8 DGND At o0 2 Figure 3 11b Pin assignments for J6 Connector on PD2 MF MES boards Connector for PDL MF X PowerDAQ PDL Series multifunction boards have one connector a main bracket connector J1 100 pin male pinless connector manufactured by Fujitsu PN TYCO 787169 9 see details for this connector on the datasheet for the corresponding PowerDAQ boards on the UEI website Figure 3 12a Physical layout of J1 on PDL MF X board Fig 3 12a shows the view
26. 3 3b At the time of this writing they include all PD2 MFS Series boards as well as the PD2 MF xx 2M Series boards We anticipate that other boards will use this form factor in the future The location of the headers might change from the previous long card format but the connector pinouts remain the same JA1 Figure 3 4 Connector layout for PDXI MF S Series boards When working with PDXI MF S boards note that you make external connections to the analog I O section with the JA1 Connector the J1 Connector serves to make electrical connections between the motherboard and the daughtercard This diagram points out any on board connectors or headers of interest to end users all others are reserved for factory use 21 3 Installation and Configuration Figure 3 5 Connector layout for PDL MF board The PDL MF layout diagram in Fig 3 5 points out any on board connectors or headers of interest to end users all others are reserved for factory use Installing synchronizing multiple boards Some systems require more channels than are available on a single board Even so it s possible to configure a system in which you coordinate the actions of channels from multiple boards To synchronize a multiboard acquisition run program the master board s Burst clock the CL clock or its Pacer clock the CV clock to use the internal timebase an external clock or software clocking Then set the slave bo
27. Click Next to continue with the Setup program Industries WARNING This program is protected by copyright law and international treaties Unauthorized reproduction or distribution of this program or any portion of it may result in severe civil and criminal penalties and will be prosecuted to the maximum extent possible under law Cancel Figure 3 1 PowerDAQ Software Installation Startup Screen 6 As the Setup program runs you will be asked to enter information about your PowerDAQ configuration Unless you are an expert user and have specific 16 3 Installation and Configuration requirements you should select a Typical installation and accept the default configuration If the Setup program asks for information about third party software packages that you do not have installed on your PC leave the text box blank and click the Next button When the installation is complete restart your PC when prompted Installing PowerDAQ hardware To install your PowerDAQ board l 2 3 Turn off your PC and remove its cover Locate an empty PCI slot and remove the slot cover on the back panel of the chassis Save the screw Insert the board into the PCI slot If you plan to work only with analog I O the connector on the board s mounting bracket that shows through the chassis slot carries all necessary signals However if you plan to use digital I O or the counter timer features in most cases depending on m
28. For faster update rates either use a _PdImmediate Update call on a timer loop or let the driver do the same thing by calling PdAInEnableTimex Both functions force the board to move all samples from the A D FIFO to the buffer the difference is that PdAInEnableTimer also starts and stops the built in timer in the driver By making the frame sizes smaller you get events more quickly Note that PdImmediateUpdate doesn t work in Bus Mastering mode Method D Recycled buffer mode If you want to make certain that the entire buffer contains only the latest data use the recycled buffer method of working with the ACB explained in detail in Appendix E It overwrites the oldest frames with new data without the requirement that the data first be read For example you can run an acquisition continuously as in Method C However if at some time the application needs much more time to process data than the time needed to fill the frame the acquisition doesn t halt and you don t get an error message Instead the driver continues the acquisition and all frames that the application hasn t yet retrieved get overwritten with new data When the application receives the next event that event sets the eFrameRecycled event flag One obvious situation in which to use this mode is when you cannot predict the exact time needed to process the data Consider the case when a control application monitors input datastreams and at some point it n
29. Glossary PCI PDXI PGA PID control pipeline PLC Polled mode port postriggering potentiometer pretriggering programmable gain amplifier programmed I O propagation delay proportional control protocol 160 Peripheral Component Interconnect an expansion bus architecture originally developed by Intel to replace ISA and EISA It offers a theoretical maximum transfer rate of 132M bytes sec PowerDAQ eXtensions for Instrumentation UEI s implementation of the PXI bus standard see Programmable gain amplifier A 3 term control algorithm combining proportional integral and derivative control actions A high performance processor structure in which the completion of an instruction is broken into its elements so that several elements can be processed simultaneously from different instructions Programmable logic controller a special purpose computer used in industrial monitoring and control applications PLCs typically have proprietary programming and networking protocols and special purpose digital and analog I O ports DAQ board operating mode whereby the user application queries the board about the status of various subsystems as needed A communications connection on a computer or a remote controller The technique used on a DAQ board to acquire a programmed number of samples after trigger conditions are met An electrical device whose resistance you can manually adjusted known among enginee
30. STP 3716 Low cost screw terminal panel with 37 pin connector for 16 channel boards PD STP 3716 KIT Complete kit Includes PD STP 3716 and PD CBL 9637 for 16 channel boards PD STP DIO Screw terminal panel with 37 pin connector handles digital I O and counter timer signals only Screw Terminal Panels PDL MF only PDL STP 100 way screw terminal with dual 50 pin IDC connectors PDL CBL 100 18 cable connects 100 way connector on PDL MF board and is terminate with dual 50 way IDC connectors for the PDL STP PDL MF CONN Connector for direct attachment of signal leads to PDL MF board no cablg required 137 Appendix C Accessories BNC amp Distribution Panels PD2 PDXI PD BNC 16 BNC panel for 16 channel boards PD BNC 16 KIT Complete kit Includes PD BNC 16 PD CBL 96 PD CBL 37 for 16 channel boards PD PDXI BNC 64 BNC panel for 64 channel boards PD PDXI BNC 64 KIT Complete kit Includes PD BNC 64 PD CBL 96 PD CBL 37 for 64 channel boards Note See Appendix E for PD BNC wiring tips Cables PD2 PDXI PD PDXI CBL 96 96 way pinless round 1m shielded cable with metal cover plates PD PDXI CBL 96 6FT 96 way pinless round 6 ft shielded cable with metal cover plates PD PDXI CBL 96 9FT 96 way pinless round 9 ft shielded cable with metal cover plates PD PDXI CBL 37 DIO cable set 37 way 1m D sub cable intern
31. act of digitizing multiple channels simultaneously with interchannel skew often being measured in psec a term used to describe an analog input configuration where you measure each channel with respect to a common analog ground a control bit in the analog input configuration word that instructs the A D to wait a short while before actually digitizing the input voltage it gives the input amplifier time to settle and is very useful when working with very high gains also S N ratio or Signal Noise ratio the ratio of the peak power level to the remaining noise power expressed in dB A programmed event that triggers an event such as a data acquisition Single pole double throw a switch in which one terminal can be connected to one of two other terminals Simultaneous Sample Hold see simultaneous sampling see samples sec A sensor that converts mechanical motion into an electronic signal A change in capacitance inductance or resistance is proportional to the strain experienced by the sensor but Appendix G Glossary subroutine subsystem successive approximation A D synchronous system noise T TCP IP THD THD N thermistor thermocouple throughput rate resistance is the most widely used characteristic that varies in proportion to strain A set of software instructions executed by a single line of code that may have input and or output parameters On PowerDAQ cards a group of circuits that perfo
32. also see A D ADC conversion ADC conversion Start ADC Channel List Start Advanced Circular Buffer alias analog trigger API asynchronous see Advanced Circular Buffer Analog digital often used in connection with an A D converter Alternate designation for a function card that plugs into a backplane often a PC Analog to Digital Converter An integrated circuit that converts an analog voltage to a digital number The process of converting an analog input to its digital equivalent Signal used to start the process of converting an analog input to a digital value The source of this signal can be an internal clock or an external asynchronous signal Signal used to start the acquisition of digitized values as defined in the Channel List The triggering edge of this signal falling edge enables the ADC conversion Start signals A special user defined buffer in host memory that stores frames of collected data The PowerDAQ driver allows the user application to fetch data from this buffer in several modes A false lower frequency component that appears in sampled data that has been acquired at an insufficiently high sampling rate A trigger that occurs when an analog signal reaches a user selected level Users can configure triggering to occur at a specific level on either an increasing or a decreasing signal positive or negative slope Application Programming Interface a collection of high level language
33. bit7 bit6 bit5 bd bit3 bit2 bt bit 0 0 0 0 Figure 5 7c PowerDAQ 12 bit data format In an application you ll generally want to convert these raw values in hexadecimal into a scaled value typically a voltage To do so use the following formula Output V HexData XOR 0x8000 BitWeight Displacement Gain You needn t place this equation in a user application because the PowerDAQ API includes two useful functions for this purpose PdAInRawToVolts and PdAInScanToVolts However should you want to include a conversion function in the user code perform the following calculations to convert raw hex data to scaled voltage data 1 Determine the value of a single bit bit weight in volts This value depends on the input range Input Range Bit Weight Span 65535 0 5V unipolar 5V span 0 000076295 V bit 0 10V unipolar 10V span 0 000152590 V bit 5V bipolar 10V span 0 000152590 V bit 10V bipolar 20V span 0 000305180 V bit Table 5 8 Bit weight by input range 2 Determine the zero offset or displacement which again depends on the input range 71 5 Analog Input Subsystem Input Range Displacement 5V or 10V unipolar 0 5V bipolar SV 10V bipolar 10V Table 5 9 Displacement by input range 3 Perform an arithmetical XOR on the raw data value with 0h8000 4 Multiply this intermediate result by the Bit Weight from Step 1 5 Add the Zero O
34. block of samples While the ACB might seem a departure from single and double buffer schemes you ll see on most other DAQ cards it s actually a superset of them In Single Buffer mode the ACB behaves like a single buffer Configured as Circular Buffer with two frames it behaves as a double buffer With multiple frames the ACB can function in algorithms designed for buffer queues The only limitation which results in more efficient performance is that the logical buffers in the queues can t be dynamically allocated or freed and their order is fixed Data format When working with data in the host memory space you must be aware of the format in the datastream Every two consecutive bytes in the stream make up one sample from the A D converter These datapoints appear in a file in the order they come from the A D converter following the order defined in the Channel List The format for each data word differs according to the A D s resolution PowerDAQ boards automatically place Zeros in any unused bit locations as shown in Fig 5 7 where bitO is the LSB 70 5 Analog Input Subsystem Ist channel 2nd channel s last channel Ist channel sample sample sample sample bit15 bit14 bit13 bit12 ba 1 bit10 bit9 ba bit7 bit6 bit5 bd bit3 bit2 ba bitO Figure 5 7a PowerDAQ 16 bit data format bitl3 bitl2 bitll bitlO bam bit8 bit7 bit6 bits bd bit3 bit2 bitl bm 0 0 Figure 5 7b PowerDAQ 14 bit data format bitll bitlO big bit8
35. boards Wisesouceu stk CE dBoccoooocooocococoocococococol S5ococcooocooocoocoooccococoosc 49 S6 ococooocooocoocoocoocccccB Figure 3 8a Physical layout of J1 JA1 Connector on PD2 MF S Series boards Fig 3 8a gives a view looking at the connector as mounted on the board 25 3 Installation and Configuration AGND4 1 49 AGND AGND 2 50 AOUTO AGND4 _3 51 AGND AGND4 4 52 AOUT1 DGND _5 53 AGND AGND 6 54 AGND AIN55 7 55 AIN54 AIN53 8 567 AIN52 AIN51 9 57 AIN5O AIN49 10 58 AIN48 AGND 11 59 AIN39 AIN38 5 12 60 AIN37 AIN36 13 617 AIN35 AIN344 14 62 AGND AIN33 15 63 AIN32 AIN23 16 64 AIN22 AIN21 17 65 AIN20 AGND 18 66 AIN AIN18 1 19 67 FAINT AIN 20 68 AIN7 AIN6 21 69 AGND AIN5 122 70 AIN4 AIN3 1 23 71 AIN2 AIN14 24 72 AINO AGND 25 73 AGND DSP Trigger Input AO External Clock 26 74 5V 100 mA max ADC Conversion Start Out Pacer clock out 27 75 ADC Conversion Start Input Pacer clock N C4 28 76 AGND AGND 29 77 N C ADC Channel List Start Input Burst Clock 30 78 AIN63 AIN62 31 79 AIN61 AIN60 32 80 AGND AIN59 33 817 AIN58 AIN57 34 82 AIN56 AIN47 35 83 AIN46 AGND 36 84 AIN45 AIN44 1 37 85 AIN43 AIN42 138 86 AINA1 AIN40 1 39 87 AIN31 AGND 40 88 AIN30 AIN29 1 41 89 AIN28 AIN27 1 42 90 AIN26 AIN25 43 91 AGND AI
36. empty the FIFO into host memory at your convenience but at the latest before another acquisition run Starting another acquisition run adds more samples to the existing values in the FIFO For this type of operation you work with the first two modes Normal and Fast If the FIFO is full the board ignores any additional samples When you set Normal mode active the driver transfers one half the A D FIFO buffer 512 samples for a 1k sample buffer per interrupt but for larger buffers this transfer is never any larger than 4k samples While it empties one half of the FIFO the board places newly acquired values in the other half The driver runs in a loop moving a sample at a time into host memory Further the driver verifies the availability of each individual sample in the before it retrieves it Thus this is the safest transfer mode but it s also the slowest This mode works with any PCI bus implementation The PDL MF board does not include an onboard A D FIFO memory Thus Normal mode which transfers data samples individually is the only data transfer method available for that card 2 Fast mode This is the default transfer mode for most MF S cards Here the driver transfers samples from the A D FIFO into host memory using programmed I O but without checking whether a given sample is actually available Thus it consumes fewer processor resources than Normal mode As is the case in Normal mode the transfer size in Fast mode is the lesser
37. for analysis e eBufferError Data integrity was compromised because of a lack of performance or system latency while serving interrupts In such cases the on board A D FIFO overflows If this error persists check the interrupt settings purchase a larger A D FIFO option or consider using Method D with bus mastering Reset events Call this function to notify the driver that events are processed PdSetUserEvents Restart The following calls stop asynchronous operation You need to call them before you again call PdAInAsyncInit and PdAInAsyncStart You can start and restart acquisition as many times as the application requires Each time you restart an acquisition the board overwrites data in the buffer with a new values PdAInAsyncStop PdAInAsyncTerm De Initialization Stop asynchronous operation PdAInAsyncStop PdAInAsyncTerm Release event object handle PdAInClearPrivateEvent Unregister and deallocate buffer _PdReleaseBuffer 78 5 Analog Input Subsystem Method C Continuous acquisition using the Advanced Circular Buffer ACB Method C employs the PowerDAQ Advanced Circular Buffer mechanism see Appendix E Here you work with one part of a buffer you set up in host memory while the A D FIFO fills the other half In this way an acquisition can run continuously and each time an event occurs such as frame filled the application receives program control ag
38. gate from the following sources e Software command e External gate input line You can operate each UCT in several modes for details see the 82C54 datasheet available on the Intel web site e Single pulse 82C54 Mode 1 The output line is initially High and it goes Low on the clock pulse following a trigger on the gate line to begin a 1 shot pulse It remains Low until the counter reaches zero At that point the output again goes High and remains in that state until the clock pulse after the next trigger e Pulse train 82C54 Mode 2 This mode functions like a divide by N counter so the pulse length equals 1 clock frequency The output line is initially High When the initial count decrements to 1 the output goes Low for one clock pulse and then it goes High again at which time the counter reloads the initial count and the process repeats This mode is periodic and the same sequence repeats indefinitely until it is instructed to stop e Rate 82C54 Mode 3 This mode is similar to Pulse train mode except for the output line s duty cycle That line is initially High and when half the initial count has expired it goes Low for the remainder of the count The sequence repeats indefinitely An initial count of N results in a square wave with a period of N clock cycles e Delay 82C54 Mode 5 This mode generates a single pulse after waiting a programmed amount of time The output line is initially High The rising edge of the gate line t
39. generaton 88 Method C Continuous waveform generation cccceccceseesseeeeeseeeeceeecescenseceseesaeeseceeceeeaeeses 89 Method D Repetitive waveform generation s ssssessessesersresteeesstsrestesetsestesesstsressesresreserseesee 91 Method E Autoregeneration see 92 Method F Event based waveforms using PCI interrupts 93 7 Digital I O Tir DO TECH 2s ished ee DRE RR ER e ER II REA NUR Fer ER ENDS 96 Programming Techniques ses 97 Method A Polled RL e EE 97 Method B Generate an event upon edge detecton 99 8 User Counter Timer Subsystem ss 102 Architecture 102 RIDER eene 104 Programming Techniques eoe bete eR e e vetere VUE dte Ie A eS ie de 105 9 Support US LOS PowerDAQ Example Programs ss 108 Third Party Software Support see 110 Appendix A Specifications ores oe eeso eorura torno n atr eae bo Fea ene eene ethic osessoseeesesiesssee L12 PD2 MF Multifunction Boards 113 PD2 MFS Simultaneous Sampling Boards 117 PDL MF Lab Multifunction Board ss 121 PDXI MF Multifunction Boards 123 PDXI MFS Simultaneous Sampling Boards 127 Appendix B PowerDAQ A D Timing eeeeeeeee rennen ente eneeenneeneeess 132 PD2 MF Series Timing sd eiconsectet inp bete ES 133 PD2 MES Series Timing eoe e NO ORE ORENSE 133 IN BIEVER LTE 133 PDXI ME Series T
40. i Examples 3 C Builder H O Delphi DI i Visual Basic c Visual C El ic Include Ci 16 bit oldinclude Ca vb3 CH VB4 c Lib E Figure D 1 PowerDAQ Software Structure 141 Appendix D PowerDAQ SDK Structure PowerDAQ Windows device drivers Windows 9x windows system pwrdaq95 vxd Windows NT winnt system32 drivers pwrdaq sys Windows 2000 winnt system32 drivers PwrDAQ2K sys winnt inf PwrDAQ2K inf Windows XP windows system32 drivers PwrDAQ2K sys windows inf PwrDAQ2K inf The PDL MF works on all operating systems except Windows 9x and it also runs under Linux and QNX The PowerDAQ Software Suite Version 3 or above is required PowerDAQ Windows DLLs The PowerDAQ Software Suite includes various DLLs dynamic linked libraries for different versions of the Windows operating system The location of these DLLs is as follows Windows 9x windows system PwrDAQ32 dll 32 bit PwrDAQ16 dil 16 bit Windows NT 2000 winnt system32 PwrDAQ32 dil PwrDAQ16 dil Windows XP windows system32 PwrDAQ32 dil PwrDAQ16 dil The DLLs have identical names for Windows 9x and NT 2000 XP but note that they are implemented differently Both support the same API so PowerDAQ applications that don t use functions specific to Win9x or WinNT 2000 XP should run on any version of Windows 142 Appendix D PowerDAQ SDK Structure Aib PowerDAQ Language Libraries PowerDAQ SDK contains libraries for all major software develo
41. it s generally advisable to set the other clock to continuous mode so it has no effect on the speed of the overall operation Clearly these two clocks often run at different speeds Unless the board is sampling just one channel the maximum CL clock has a value of CV clock number of channels As just mentioned setting one clock to continuous is an easy way to avoid any timing conflicts between the two clocks In fact there are few cases where you might want to set both clocks exactly In addition anytime you apply a clock signal before the subsystem 1s ready to process it the board generates an error condition For example if you input a clock at a frequency higher than the rated aggregate rate the board sets a bit in one of the status registers whenever a CL or CV clock pulse occurs before it s ready to process the pulse Triggering Once you set up the Channel List clock and the Conversion clock with the commands just described the board doesn t yet start collecting data You must also supply a start trigger to activates both clocks The clocks are like runners at the starting line sitting still waiting for the starting gun Once the trigger signal arrives the clocks start running Thus the maximum possible delay from the time the trigger arrives to when the board digitizes its first sample is the period of the CV clock Similarly you later need a stop trigger to halt both clocks In this way the application has control over the ex
42. looking into the connector socket mounted on the board 31 3 Installation and Configuration AIN8 1 5 1 am AGND AGND AIN9 AINI AGND AGND AIN10 AIN AGND AGND AIN AGND AGND AIN12 AGND AGND AIN13 AIN AGND AGND AIN14 AINS AGND AGND AIN15 AIN AGND GND AOUTO AQUT1 Figure 3 12b Pin assignments for J1 Connector on PDL MF X Series board 32 3 Installation and Configuration Connectors for PDXI MF S Series boards PowerDAQ PDXI MF S Series multifunction boards have two connectors e A main bracket connector for analog I O signals J1 A 96 contact pinless male connector manufactured by Fujitsu PN FCN 245P096 G U see details for this connector on the datasheet for the corresponding PowerDAQ boards on the UEI website The connector pinout for J1 on the PDXI MF MFS Series is identical to the pinouts on the PD2 MF MFS Series See Figures 3 8a d e On card connector for digital I O and counter timer signals J2 An 80 pin flat cable to pc board connector male IDC header manufactured by Methode Adam Tech PN HBMR A 80 VSG see details for this connector on the datasheet for the corresponding PowerDAQ boards on the UEI website PDXI CBL 96 l 80 2 Figure 3 14a Physical layout of J2 on PDXI MF MES Series boards Fig 3 14a gives a view looking into the connector socket mounted on the board 33 3 Installation and Confi
43. new configuration to an EEPROM that stores these connections Z PDXI Configurator PI x PDXI MFS 8 2M 14 ER Ext Trig In CH none PoxI a0 32 16 CV Start In CL Start In CV Start Out xz Q none none 3 A OE p TC T Additional amp Slots Apply amp Save PXLTrig2 PXLTrig3 PXLTrig4 PXLTrig5 PXLTrig6 PXLTrig Star Trig PXLTrigO PXLTrig1 Figure 3 6 PDXI Configurator Base address DMA and interrupt settings When you power up your PC the PCI bus automatically configures any PowerDAQ boards that are installed You don t have to set any base address DMA channels or interrupt levels Be aware though that performance problems can arise when the system has insufficient interrupts and can t assign a unique one to each peripheral so that a PowerDAQ board must share an interrupt with some other device One solution is to decide which system resources you do not need candidates being serial ports the parallel port USB ports or network interfaces and disable their interrupts thereby freeing those lines up for assignment to other devices This can lead to the optimal case where a PowerDAQ board is assigned a dedicated IRQ line 23 3 Installation and Configuration A data acq card s interrupt is generally assigned by the PC BIOS and some PC systems even let you reassign it during the boot process If your moth
44. of Counters 3 available to user Intel 82C54 Resolution 16 bits on each counter Clock Inputs Software configurable High level Input voltage Low level Input voltage High level Input current Low level Input current Internal 1M S sec External 10M S sec 2 0V min 0 8V max 20 pA 20 pA Gate Inputs Maximum Pulse Width 100 nsec High 100 nsec Low Counter Outputs Output Driver High Voltage Output Driver Low Voltage Inverted 2 5V min IOH 24 mA 0 55V max IOH 48 mA General Specifications and Connectors all PDXI MF models 126 Power Requirements 5V Physical Dimensions 7 x A 177 x 101 mm Environmental Operating Temperature Range Storage Temperature Range Relative Humidity 0 to 70 C 25 to 85 C to 95 noncondensing Connector J1 96 pin high density Fujitsu connector male Fujitsu PN FCN 245P096 G U Connector J2 80 pin header connector male Adam Tech PN HBMR A 80 VSG Appendix A Specifications PDXI MFS Simultaneous Sampling Boards Model PDXI MFS xx 2M 14 1M 12 800 14 Resolution 14 bits 12 bits 14 bits Number of Channels Single Ended 4 or 8 Differential optional 4 or 8 Maximum Sampling Rate 2M S sec 1M S sec 800k S sec multiple channels Onboard FIFO Size 4k samples 1k samples upgradeable to 16k 32k 64k Input Ranges 0 5V 5V 0 8V 8V 10V ran
45. output When a frame of the buffer has been output the driver Issues an event to allow you to write more data to the buffer Repetitive waveform generation Method D This method can create fixed length waveforms greater than 2048 samples The size of the buffer is limited by the amount of physical memory in the PC An application writes data to the PowerDAQ driver buffer and each time the end of the buffer is reached the PowerDAQ driver resends the same buffer until instructed to stop Non buffered waveform generation methods Autoregeneration Method E This method can create fixed length waveforms maximum size limited by the D A FIFO without any host PC intervention An application writes data to the FIFO buffer and each time the end of buffer is reached the DSP resends the same buffer until instructed to stop Rev 3 x of the PowerDAQ SDK allows you to create waveforms up to the size of the memory available on your PC See Method D Events in non buffered mode Method F The events in this method allow the continuous generation of waveforms and there is no limited to the total amount of data the system can output When the FIFO on the DSP drops to less than half full the board issues an interrupt requesting more data Thus with a 2k sample FIFO you can load a maximum of 1024 samples at a time Ifthe FIFO is empty and the card has sent out the last value it continues outputting that last value until the program instructs it
46. plug in board or controller that can read and write to devices on the computer bus without the assistance of the host CPU Eight related bits of data an 8 bit binary number Also used to denote the amount of memory required to store one byte of data High speed processor memory that buffers commonly used instructions or data to increase processing throughput The setting or correcting of a measuring device or base level usually by adjusting it to match or conform to a dependably known and unvarying measure A variable length list of from 1 to 256 entries each of which defines a channel its gain any Slow Bits In continuous A D acquisition mode the list wraps around to the first channel after it reaches the end The channels need not be in any particular order and may appear multiple times in the list The on board memory that holds the Channel List 153 Appendix G Glossary CL clock control register CMRR code generator cold junction compensation common mode range common mode signal component software conversion time counter timer coupling crosstalk current drive capability current sinking current sourcing 154 The Channel List clock also known as the Burst clock tells the control logic how quickly to move to the next entry in the Channel List and set up the front end operating parameters such as gain Register containing control bits that set up and configure various onboard subsystems
47. samples 4k samples 2k samples upgradeable to 16k 32k 64k Channel Gain List 256 entries Input Ranges 0 5V 0 10V 5V 10V software selectable Programmable Gains L 1 10 100 1000 L 1 10 100 1000 by channel H 1 2 4 8 H 1 2 4 8 H 1 2 4 8 Drift Zero 30 pV C Gain 30 ppm C Input Impedance 10 MO Input Bias Current 20 nA Input Overvoltage 20V 2000V ESD 35V continuous 10 mA max A D Conversion Time 283 ns 0 45 usec 0 8 usec 2 usec A D Settling Time 250 ns 0 37 usec 0 6 usec 1 2 usec DC Accuracy Nonlinearity 1 LSB 2 LSB 0 5 LSB 1 LSB System Noise 0 8 LSB 1 2 LSB 0 3 LSB 1 3 LSB AC Accuracy Effective Number of Bits 11 2 12 2 11 63 14 5 Total Harmonic Distortion 72 dB 76 dB 71 8 dB 88 dB Nonlinearity Noise Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 2200k S sec 1 ch Aggregate Throughput 3000k S sec 1800k S sec all 1250k S sec 500k S sec 0 01 Accuracy External A D Sample Clock 2200k S sec 1 ch Maximum Frequency 3000k S sec 1800k S sec all 1250k S sec 500k S sec Minimum Pulse Width 20 nsec External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec 113 Appendix A Specifications Model PD2 MF xx 400 14x 333 16x 150 16x Resolut
48. some slight delay in starting another run and that delay could vary from run to run In addition you might think that a good option would be to set both clocks to software but that setup actually isn t terribly productive In this setup you would theoretically call one function to start the CL clock and then call another function to read each entry in the list this operation would essentially single step through the list If you wish to single step in this fashion it s far easier to set the CL clock to continuous at the start of the program and then just use the CV clock when you want another sample because the CL clock is continuous it will set the list pointer to the top of the Channel List at the first available opportunity For an application that requires repeated runs through the Channel List the recommended setup is CL clock internal and CV clock continuous The CV clock thus will step through the Channel List as quickly as possible and the CL clock activates the list according to the internal timebase either 11 or 33 MHz modified by a user applied divisor Be careful when setting the timebase because the subsystem ignores any interim clock pulses that arrive before it is able to handle them That situation will set an error bit but it won t halt activity Alternately you could reverse the configuration and set the CL clock continuous and the CV clock internal Table 5 5 examines all the possible clock combinations and gives
49. to do otherwise 85 6 Analog Output Subsystem Channel List Just as the analog input subsystem offers a Channel List so does the analog output subsystem in buffered mode There is a fixed Channel List for the analog output on the PD2 MF S boards and it always contains values for both analog outputs Ch 0 and Ch 1 and they are updated simultaneously Because both output channels are updated at the same time you must configure both D As for the same mode of operation Data format 31 24 23 12 11 0 Unused 12 bit data 12 bit data for AOutl for AOut 0 Figure 6 1 Analog output data format The analog outputs have a fixed output range of 10V The data representation is straight binary To convert a voltage into binary codes use the following formula HexValue Voltage 10V 20 OXFFF You can combine the two Hex values that Aout Ch 0 and Ch 1 should write as follows Value To Write HexValuel lt lt 12 OR HexValue0 To convert floating point values to raw voltages use the function PdAOutVoltsToRaw Clocking You must clock the analog output subsystem for each new voltage level being generated Specifically every time a clock pulse occurs the board reads the next value from the D A FIFO converts it into a voltage representation and generates the analog voltage on the selected channel You can clock the subsystem using a software command the internal 11 or 33 MHz base frequency or from with a si
50. tuned to take advantage of this flexible buffering mechanism the system as a whole runs much more efficiently Driver Asserts Frame Done Events d When Data Written Advanced Circular Passes Frame Boundry B uffe r Board Driver Write New Data At Buffer Head U pe Buffer Head Application Reads Data From I Buffer Tail Buffer Tail Frame Markers RE Figure 5 6 Advanced Circular Buffer Once an acquisition is started the board driver stores data into the buffer at a known point called the head while the application generally reads data at another position known as the tail Both operations occur asynchronously and can run at different rates However you can synchronize 69 5 Analog Input Subsystem them by either timer notification or by a driver event To be able to issue a notification to the user application upon receipt of a specific sample or when incoming data reach a scan count boundary the driver segments the buffer into frames Whenever incoming data crosses a frame boundary the driver sends an event to the application If multichannel acquisition is performed the frame size should be a multiple of the scan size to keeps pointer arithmetic from becoming unnecessarily complex With the ACB three modes of operation are possible depending on the action taken when the end of the buffer is reached or if the buffer head catches up with the tail e In Single Buffer mode acquisition stops when t
51. uses the word PowerDAQ to collectively reference all the models listed above Other boards in the PowerDAQ Series see separate manuals include the e PD2 PDXI AO Series Analog Output with digital I O counter timers e PD2 PDXI DIO Series Digital I O with counter timers e PDL DIO Series Lab Series Entry level Digital I O with counter timers Who should read this manual This manual has been written to make the installation configuration and operation of our PowerDAQ multifunction boards as straightforward as possible However it assumes that the user has basic PC skills and is familiar with the Microsoft Windows XP 2000 NT 9x QNX or Linux RTLinux RTAI Linux operating environments 1 Introduction Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss or system crash Text formatted in bold typeface generally represents type that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe 1 Introduction Organization of this manual Chapter 1 Introduction The section you ar
52. waveform seseesesee 86 92 PDL MF iens 59 single update 85 88 Eleng essen ies 57 software command 96 BOUFER nara panny ie 57 triggering iris 88 96 Clocking inse eei 17 57 Analog output multiplexer 140 multichannel esses 62 Analog input subsystem 39 45 preferred oe ette 54 Analog output subsystem 40 85 repeated scans ssssssssesss 62 ASTP see Active Screw Terminal Panel single sample 61 MERL ee Mn een son 46 source combinations 62 Clocking timing examples 61 B Combining analog digital subsystems 83 Base address cia ueste pA RR 23 Me vo i ney WATT CL eae 58 Binary rate multiplier 103 Connector Block diagram PD2 MF S un oF Ji PD2 MF S Lans 24 DAS ER P DI ME en 2 TD EM rame 33 Block diagram PDXI MF S 38 12 PD2 MF S ne 24 BNC panels 138 J2 PDXI MF S in 33 Board families 8 J4 PD2 MF S nr 24 Board ypes tite ner 8 J6 PD2 MF S e 25 Borland C examples 110 Connector layout PZ MES 19 Buffer size rennes 80 Connector layout PD MF 22 Burst buffered acquisition 76 Connector layout PDXI MF S 21 Burst clock GEET see CL clock Connector summary PD2 MF S 24 Bus mastering
53. 22 34 Synchronous operation 83 System requirements sss 15 T TestPoint support 111 Thermocouples sss 140 168 Thermocuple readings 82 Timeout nt tede tes 77 TIS SOPs ees eee r 17 59 analog output ssssesessseserseeseeeessrseesseee 88 external m a me ea 60 posttriggering 61 pretriggering 0 ee eeeeeseeeseeeeeseeeteeeees 61 rising falling edge 60 Gen 60 Slat o er ERREUR OE 59 do MP P 59 U Unused channels 51 User Counter Timer Subsystem 103 V Visual BASIC examples 109 Visual C examples ssssesseeseeeesseeees ee 109 Voltage divider 150 W KE E 151 Waveform generator s seeessseesee 85 103 X xPC Target support 111 Reader Feedback We are committed to improving the quality of our documentation in order to serve you better Your feedback will help us in the effort Thanks for taking the time to fill out and return this form Is the manual well organized Can you find information easily Were you able to install the PowerDAQ boards Were you able to connect the PowerDAQ board to the accessories Did you find any technical errors Is the manual size appropriate Are the design type style and layout attractive Is the quality of illustrations satisfactory How would you rate
54. D A has emptied the entire buffer and that no more datapoints are available Re enable events with PdSetUserEvents Write additional data to the D A FIFO with PdAOutPutBlock Continue waveform generation _PdAOutEnableConv and use 1 for dwEnable PdAOutSwStartTrig Stop waveform generation Issue a stop trigger if you haven t configured the external trigger _PdAOutSwStopTrig and then disable D A conversions _PdAOutEnableConv and use 0 FALSE for dwEnable De initialize the subsystem Disable the board interrupt if no other subsystem are using the interrupt at the time PdAdapterEnableInterrupt and use dwEnable 0 Release the event object _PdAOutClearPrivateEvent Clear the subsystem and set both outputs to OV PdAOutReset 95 7 Digital I O Subsystem Architecture The digital I O subsystem in almost all PD2 PDXI MF MFS Series boards contains one 16 bit input register and one 16 bit output register The only exception is the PDL MF which uses two 24 bit registers In all cases the digital I O registers do not support clocked operation so this subsystem can be used only in software polled mode 16 bit Input Register 8 bit Edge Latch Status Detector and Latch Config Latch IRQ Logic Figure 7 1 Digital input subsystem hardware block diagram On all dedicated digital input lines the board comes with 4 7kQ pull up resistors We supply these pull
55. Ext Aln Scan Gock Ext Trigger Aln Calibration Aln Power DAG Conditioner 12 4 16 bit Sampling AID Converter Aln Control PowerDAQ II Data Acquisition Control and Timing Logic Ext An nv Clock _ Ext Aln Scan Gock Ext Trigger Aln Clock Out Internal Digital H O Connector J2 Local Data Bus K Qock ing A Triggering Lines KC DAC1 Qock Clock Aln Scan Aln Conv AOut AD AOut Clock 6 Channel DMA 12k Program RAM Bootstrap ROM 2kDaa RAM A Out Calib rat ion DACs Votage Refere nce Motorola 66MHz D 56301 Bus Master FCI Interface P 8 eum Configuration PXI A Calibraion Control R Logic k Bit CompactFCI a gt lt PXI A Figure 4 2 PowerDAQ PDXI MF MES Series block diagram 4 PowerDAQ Architecture External Ando g Digital UV OCom ector 3 Volt age An Caibration Aln Power Reference DACs Conditioner DP pun o5 eynowey 6 INO o uv 200 AUCH uiv PS J25 Bul pq Counter Timer Hee Ss R 16 anna PGIA L 16 bit Upgraiablel Andog Gain Multiplexer 24 Sampling K Sanple AID ADC Converter HFO Amp EC dck SW ES FFO FowerDAQ II Dod gic Input 24 Data Acquisition CD Beter GEET BE Dy Pr Timing Logic DOut Gntrol
56. N24 44 92 AIN AIN 5 45 93 AIN 13 AIN2 46 94 AIN AGND 47 95 AIN10 AIN9 48 96 AIN8 Figure 3 8b Pin assignments on J1 JA1 Connector on PD2 MF boards in single ended mode In Fig 3 8b the symbol means that the line is disconnected by default consult factory if you need this clock on the J1 connector 26 3 Installation and Configuration AGND DS Trigger Input AO External Clock ADC Conversion Start Out Pacer clock ot N C4 AGND ADC Channel List amp art Input Burst Clock AIN54 Return AIN52 Return AIN51 Return AIN49 Return AIN39 Return AGND AIN36 Return 35 AIN34 Return AIN32 Return 38 39 AGND 40 AIN21 Return AIN19 Return 41 42 AIN 17 Return 43 AIN Return AIN6 Return AIN4 Return 44 45 46 AGND AIN Return 47 48 Figure 3 8c Pin assignments on J1 JA1 Connector on PD2 MF boards in differential mode AGND AOUTO AGND AOUT1 AGND AGND AIN54 AIN52 AIN50 AIN48 AIN39 AIN37 AIN35 AGND AIN32 AIN22 AIN20 AIN AIN 17 AIN7 AGND AIN4 AIN2 AINO AGND 5V 100 mA max ADC Conversion Start Input Pacer clock AGND N C AIN55 Return AIN53 Return AGND AIN50 Return AIN48 Return AIN38 Return AIN37 Re
57. Output Driver High Voltage Output Driver Low Voltage 2 5V min 3 0V typ IOH 32 mA 0 55V max IOL 64 mA Current Sink 32 64 mA max 250 mA per port Pulse Width 20 ns min interrupt bit latched on rising falling or either edge Power on Voltage Logic Zero General Specifications and Connectors all PD2 MF models Power Requirements 5V Physical Dimensions 10 5 x 3 8 262 x 98 mm Environmental Operating Temperature Range Storage Temperature Range Relative Humidity 0 to 70 C 25 to 85 C to 95 noncondensing Connector J1 96 pin high density Fujitsu connector male Fujitsu PN FCN 245P096 G U Connector J2 36 pin header connector male Thomas and Betts PN 609 3627 Connector J4 36 pin header connector male Thomas and Betts PN 609 3627 Connector J6 8 pin male connector Adam Tech PN PH2 SMT 8 SGA Appendix A Specifications PD2 MFS Simultaneous Sampling Boards Model PD2 MFS xx 2M 14 1M 12 800 14 Resolution 14 bits 12 bits 14 bits Number of Channels Single Ended 4 8 optional Differential 4 8 optional Maximum Sampling Rate 2M S sec 1M S sec 800k S sec multiple channels Onboard FIFO Size upgradeable 4k samples 1k samples to 16k 32k 64k Input Ranges 0 5V 5V 0 5V 0 10V 5V 10V 0 8V 8V 10V ranges software selectable Channel Gain List 256
58. RTI AIB_CVSTART0 AIB CVSTARTI Continuous Internal Primary mode for use with MF boards do not AIB CLSTARTO or Software use with MFS boards The internal CV clock AIB CLSTARTI sets the time between conversions Use this AIB CVSTARTO type of clocking when you want to increase the or settling time between acquisitions especially AIB CVSTARTO when the signal source has a high output impedance Continuous External Used with MF boards only This mode is useful AIB CLSTARTO when acquiring data from just one channel or if AIB CLST ARTI you want to start a channel conversion exactly at AIB CVSTARTI an external pulse edge 8 External or Internal Use internal CV clock on MF board to set the AIB CLSTART Software time between conversions AIB CVSTARTO or AIB CVSTARTO External External This mode provides full control of the board s AIB CLSTARTI timing from an external device It is rarely used AIB CVSTARTI because it requires the external device it sophisticated enough to assume all timing functions Software Software Although this mode gives full control of the 0 0 default board s timing to the user application it is rarely used because you can t achieve high precision compared to that possible with a hardware clock source Table 5 5 Possible clocking combinations the shaded rows at the bottom indicate rarely used combinations 63 5 Analog Input Subsystem The A D Sample FIFO When you collect analog samp
59. Rate 30 V usec Counter Timer all PDXI MFS models Number of Counters 3 available to user Intel 82C54 Resolution 16 bits on each counter Clock Inputs Software configurable Internal 1M S sec External 10M S sec High level Input voltage 2 0V min Low level Input voltage 0 8V max High level Input current 20 pA Low level Input current 20 pA Gate Inputs Maximum Pulse Width 100 nsec High 100 nsec Low Counter Outputs Inverted Output Driver High Voltage Output Driver Low Voltage 2 5V min IOH 24 mA 0 55V max IOH 48 mA 129 Appendix A Specifications Digital I O all PDXI MFS models Input Bits 16 8 can generate IRQ Output Bits 16 Inputs High level Input Voltage 2 0V min Low level Input Voltage 0 8V max High level Input Current 20 pA Low level Input Current 20 pA Outputs Output Driver High Voltage 2 5V min 3 0V typ IOH 32 mA Output Driver Low Voltage 0 55V max IOL 64 mA Current Sink 32 64 mA max 250 mA per port Pulse Width 20 ns min interrupt bit latched on rising falling or either edge Power on Voltage logic Zero General Specifications and Connectors all PDXI MFS models Power Requirements 5V Physical Dimensions 7 x A 177 x 101 mm Environmental Operating Temperature Range 0 to 70 C Storage Temperature Range 25 to 85 C Relative Humidity to 95 noncondensing Connecto
60. SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 8 2M 14 2M samples sec 14 bit A D 8 SE simultaneous inputs G 1 two 12 bit D As G 1 PDXI MFS 4 1M 12 1M samples sec 12 bit A D 4 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 8 1M 12 1M samples sec 12 bit A D 8 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 4 800 14 800k samples sec 14 bit A D 4 SE simultaneous inputs G 1 two 12 bit D As G 1 PDXI MFS 8 800 14 800k samples sec 14 bit A D 8 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 4 500 16 500k samples sec 16 bit A D 4 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 8 500 16 500k samples sec 16 bit A D 8 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 4 500 14 500k samples sec 14 bit A D 4 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 8 500 14 500k samples sec 14 bit A D 8 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 4 300 16 300k samples sec 16 bit A D 4 SE simultaneous inputs G 1 two 12 bit D As PDXI MFS 8 300 16 300k samples sec 16 bit A D 8 SE simultaneous inputs G 1 two 12 bit D As Table 2 4 PowerDAQ PDXI MFS Models Note All PDXI MFS Series models also include three counter timers and 32 digital I O lines Note PDXI MFS Series boards provide a dedicated sample hold amplifier S H for each analog input channel These S Hs are integrated into the board s hardware design and do n
61. Subsystem Acquire the named subsystem for use if you set dwAcquire 1 and the parameter dwSubsystem can be one of the following as defined in typedef enum 43 4 PowerDAQ Architecture 44 _PD SUBSYSTEM AnalogIn AnalogOut DigitalIn DigitalOut CounterTimer let the user app work with the subsystem then PdAcquireSubsystem Release the subsystem from use if you set dwAcquire 0 PdAdapterClose Close the adapter PdDriverClose Close the drive 5 Analog Input Subsystem Architecture The analog input subsystem consists of an A D converter signal conditioning circuitry and control of other front end devices such as a multiplexer or multiple sample hold amplifiers The subsystem s first stage multiplexes raw signals from the input channels into a successive approximation A D with a resolution of 12 14 or 16 bits The A D subsystem also includes selection of input mode single ended or differential polarity gain settings range settings set up of the Channel List trigger and clocking control The multiplexer on MF boards is located at the signal inputs and can be switched to function either in single ended SE or differential DI mode Fig 5 1 The selected mode is applied to all input channels The output of the mux feeds an instrumentation amplifier and then the signal goes into a custom programmable gain amplifier PGA Channel numbers along with their gains are sto
62. Subsystem Sequential vs simultaneous sampling Users have several choices in determining the relationship of one sample to the next You can sample a series of signals sequentially and you can simulate simultaneous sampling by sampling adjacent signals at the highest possible rate to minimize the time skew among them pseudosimultaneous both of those methods are possible with MF Series boards For true simultaneous sampling where you must eliminate time skew among multiple channels the best solution is to work with MFS Series boards The fact that all MFx boards use one A D converter determines their front end architecture ahead of the converter Sequential sampling For sequential sampling a multiplexer feeds signals to a common input amplifier which then feeds the A D converter Fig 5 3 Clearly the front end needs some time to switch from one input to the next and allow the amplifier time to settle In the MF Series cards there is very little difference between the time the multiplexer switches to a new signal when the front end sees a new signal and when that new signal is digitized On MF and PDL MF Series boards the minimum delay between each channel readings is limited by the rated speed of the board which you can calculate as 1 rate For instance for a board rated at 2 2M samples sec the interchannel digitization delay is 1 2 2 x 105 1 x 10 2 2 450 nsec By selecting a card with a fast front end such as UEI ca
63. a likely requires buffered D A FIFO writes Consequently this method requires initialization and use of the PowerDAQ buffering mechanism see Appendix E Method B uses an asynchronous notification from the driver through Win32 events Thus you should program the board for asynchronous operation and use Win32 function such as WaitForSingleObject to initiate a wait until the driver notifies that the data has been successfully output Initialization Reset analog output from previous operation _PdAOutReset Acquire buffer for analog output _PdAcquireBuffer without setting the BUF_BUFFERWRAPPED flag and fill the buffer with data Initialize asynchronous operation _PdAOutAsynclnit and set dwConfig AOB CVSTARTO to use internal clock and calculate the divisor as described above Set up event notification _PdAOutSetPrivateEvent Start waveform generation Start asynchronous operation _PdAOutAsyncStart Wait for an eBufferDone event from the board or a timeout WaitF orSingleObject hEventObject Timeout Event handler Check why the event object was set with _PdGetUserEvents Re enable events with PdSetUserEvents 88 6 Analog Output Subsystem Restart Stop asynchronous operation PdAOutAsyncStop PdAOutAsyncTerm before starting again _PdAOutAsynclnit PdAOutAsyncStart only include PdAOutAsyncTerm and _PdAOutAsynclnit if you need to chang
64. act time during which it digitizes signals The trigger signal can be either a software command or an external pulse with the software trigger being the default you must either put a trigger command in the application or enable an external trigger Ifthe CV clock is set to continuous or internal the trigger is guaranteed to start and stop acquisition at the beginning of a Channel List scan If the CV clock is external the external equipment is responsible for providing enough clock pulses to complete a pass through the Channel List Don t forget that if you set up the board to start on an external trigger the analog input subsystem ignores both the CL and CV clocks until the pulse arrives Acquisition continues until the stop trigger occurs Within an application program you generate a software trigger with the command PdAInSwStartTrig Using this command a program can request immediate acquisition or it can trigger an acquisition based on a review of incoming data to see if they meet some user specified requirement such as a certain level see Table 5 4 59 5 Analog Input Subsystem Start Stop Constants to use in trigger trigger External TTL signal dwAlnCfg edge edge configuration word AIB_STARTTRIGO AIB_STARTTRIGO Falling AIB_STOPTRIGO AIB_STOPTRIG1 AIB_STARTTRIGO AIB STARTTRIG1 Falling AIB_STOPTRIGO AIB_STOPTRIG1 AIB STARTTRIGO Falling Rising AIB STARTTRIGT AIR STOPTRIGO Acquisition started
65. ain The data acq thread waits on the function call and won t do anything until that call comes You can create separate threads for each board in your application to run the acquisition process Examples in the SDK that fall into the category of Method C are e Stream e Set up the buffers The analog input configuration is very similar to Method B except you set up the buffer in a different way First allocate the buffer and register it with the board Make the buffer as large as necessary Here you define a frame which is a user defined number of scans and you define how many frames and thus number of scans must be in the buffer before the driver issues an eFrameDone event to notify the application that data is ready for retrieval Each user application processes events in different ways but each time an application detects an eFrameDone event it knows that one or more frames are filled with data For Method C the minimum buffer size is two frames which implements the classic double buffering mechanism The largest possible size is limited by the amount of free memory in the host A larger number of frames makes the operation more flexible and decreases probability of buffer overflow because the host CPU isn t involved as frequently PdAcquireBuffer When registering the buffer and if you want to use the ACB be sure to set Set dwWrapAround AIB BUFFERWRAPPED PdAcquireBuffer How can you determine the optimal buffer s
66. al consists of two sinewaves added together Integral Nonlinearity a measure in LSB of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry The current that flows into the inputs of a circuit The measured resistance and impedance between the input terminals of a circuit The difference in the input bias currents of the two inputs of an instrumentation amplifier A circuit whose output voltage with respect to ground is proportional to the difference between the voltages at its two inputs 157 Appendix G Glossary integral control integrating A D interrupt UO IPC isolation voltage K k L linearity LSB M M Mbytes s MMI multiplexer 158 A control action that eliminates the offset inherent in proportional control An A D whose output code represents the average value of the input voltage over a given time interval A computer signal indicating that the CPU should suspend its current task to service a designated activity Input Output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces Interprocess Communication protocol by which processes can pass messages Messages can be either blocks of data and information packets or instructions and requests for process es to perform actions A process can send messages to itself other proce
67. al cable with mounting bracket PD CBL 37 6FT DIO cable set 37 way 6 ft D sub cable internal cable with mounting bracket PD CBL 37 9FT DIO cable set 37 way 9 ft D sub cable internal cable with mounting bracket PD CBL 37BRKT DIO cable 37 way 1m internal cable with mounting bracket PD CBL 37TP DIO twisted pair cable set 37 way 1m D sub cable internal cable with mounting bracket PD CBL 3650 8 8 DIO cable set 36 50 way 1m ribbon cable internal cable with mounting bracket for 8 DI and 8 DO PD CBL 3650 16I DIO cable set 36 50 way 1m ribbon cable internal cable with mounting bracket for 16 DI PD CBL 3650 160 DIO cable set 36 50 way 1m ribbon cable internal cable with mounting bracket for 16 DO PD CBL 5B 18 ribbon cables that connect from the PD 5BCONN to 5B xx racks PD CBL 7B 18 ribbon cables that connect from the PD 7BCONN to 7B xx racks PD CBL SYNCA Internal cable to synchronize up to four PowerDAQ MF S boards PD CBL SYNCS Internal cable to synchronize up to five PowerDAQ MF S boards PD CBL SYNCIO Internal cable to synchronize up to ten PowerDAQ MF S boards 138 Appendix C Accessories Mating cables connectors rack mounts PD2 PDXI PD CONN Mating connector with metal cover includes Fujitsu PN FCN 230C096 C E and FCN 247J096 G E Allows users to create custom conn
68. and Agilent VEE UEI has implemented analog trigger support in our drivers for these packages For example in our LabVIEW VI named PD A Read that VI supplies a node where you can activate analog triggering as well as specify parameters such as the threshold 60 5 Analog Input Subsystem Clocking Triggering Examples A few brief examples should help you get a better idea of how to work with the clocks and triggers 1 Single sample Suppose you want to take just one sample and no more First make sure that you have defined a Channel List where the first entry defines the channel number and its gain setting Next set the CL clock to continuous and then activate the Start trigger Now any call to the function _PdAInSwCvStart generates a single pulse on the CV clock and so it reads the next value in the Channel List and then pauses Because the CL clock is continuous it effectively pulses again as quickly as possible once again setting the pointer to the top of that list Thus calling PdAInSwOCvStart again at any desired time digitizes just that one desired channel as before Recall once more that the function call will have no effect unless you have already activated the Start trigger Note that you could exchange the order of the clocks that is you could set the CV clock to continuous so a reading is made immediately whenever the board activates the Channel List and you could use the function PdAInSwClStart to issue one pul
69. ards to use an external CL or CV clock The best way to set up multiboard operation is to launch separate execution threads for each board Start the slave boards threads first and then execute the master board s thread To route these clock signals among multiple boards you need a special synchronization cable the PD CBL SYNCA see Appendix C This cable has one connector for a master board and three connectors for slaves Synchronization cables for more than four boards are available from your distributor or the factory 22 3 Installation and Configuration You synchronize a PDL MF board to a system that also uses MF MFS Series boards through clock connections you make on an external screw terminal panel If the PDL MF is the master connect CL Out or CV Out to CL In or CV In of the slave boards If the PDL MF is a slave connect the CL Out or CV Out of the master to EXTCLK To use more than four PCI slots the configuration in a standard PC under control of one Master requires a PCI bridge chip While these chips support additional PCI slots they also reduce PCI bus throughput and thus reduce the boards maximum sampling rate The reduction depends on the PC configuration but a typical value is near 1096 per board For PDXI boards you must make all synchronization settings over the PXI backplane with the PDXI Configurator software see Fig 3 6 By clicking on the lines you wish to connect you instruct the software to write the
70. asic boards capabilities definition file for C C PowerDAQ Firmware PCI interface definitions file for Visual Basic PowerDAQ Firmware PCI interface definitions file for C C PowerDAQ Firmware PCI interface definitions file for Delphi driver constants and definitions file for C C driver constants and definitions file for Delphi driver constants and definitions file for Visual Basic API function prototypes and structures file for C API function prototypes and structures file for C API function prototypes and structures file for Delphi API function prototypes and structures file for Visual Basic PXI related function definitions file for Visual Basic PXI related function definitions file for C C PowerDAQ FFT and windows routines definition file for C PowerDAQ FFT and windows routines definition file for C Appendix D PowerDAQ SDK Structure vbdll bas include vb3 pwrdaq16 bas pdfw_def bas pd_hcaps bas daqdefs bas include 16 bit pwrdaq16 h pwrdaq h pdd_vb3 h pd_hcaps h auxiliary functions to access PowerDAQ buffer from within VB API function prototypes and structures file for Visual Basic v 3 0 firmware constant definition file for Visual Basic v 3 0 boards capabilities definition file for Visual Basic v 3 0 event word definition for Visual Basic v 3 0 API function prototypes and structures file for 16 bit C C driver constants and definitions file for 16 bit C C auxiliary functions to access Powe
71. at all subsystems are operating properly From the Start menu select Programs PowerDAQ gt Simple Test and the utility s dialog box appears Analog In Analog Out Digital In Digital Out Counters Number of adapters installed 1 PD2 MF 1 6 333 16H 001176 Figure 3 15 Simple Test application Use the Analog In Analog Out Digital In Digital Out and Counters tabs to observe your application running on the board From these pages you can control the mode single ended or differential range gain number of channels activated and the channel whose value appears on the screen It s often helpful to run an analog I O loopback test with the help of this utility First wire AOut0 to all even numbered Aln channels and then wire AOutl to all odd numbered Aln lines Be sure to increase the number of active channels in the AnalogIn tab to the maximum and click Start Now go to the AnalogOut tab select two different waveforms for the two active channels and click Start Return to the Analogin tab and scroll through various channels to verify the operation of each You can similarly run a digital I O loopback test Wire Dout channels to corresponding Din channels Click Start on the DigitalOut tab then return to the DigitalIn tab and verify the operation of each line 35 3 Installation and Configuration Calibration All PowerDAQ hardware ships fully calibrated and do not require additional calibration
72. bility in how fast they digitize and collect real world samples To set up any analog input operation you must configure both of two clocks to activate this operation the subsystem must also receive a trigger pulse Clocking Let s first examine the two clocks the CL clock or Channel List clock also known as the Burst clock it tells the control logic when to start processing a full scan through the Channel List the CV clock or Conversion clock also known as the Pacer clock it triggers individual acquisitions or entries in the Channel List and thus tells the A D how fast to digitize successive samples When the CL clock has read the last entry in the Channel List it automatically fetches a new set of entries for the Channel List from the CL FIFO and sets up the mux and amplifiers to be ready to take the next sample when a new CL clock pulse arrives For both of these clocks you have the choice of four sources Software clock a software command in the application program issues a clock pulse Internal clock derived from a timebase on the board Each PowerDAQ board offers two software selectable base frequencies 11 and 33 MHz You obtain lower frequencies by dividing the base frequency with a 24 bit divisor that has a value from 1 to 2 16 777 216 To calculate the new frequency use the formula Timebase Base Frequency divisor 1 To implement this new timebase pass the required value in the divisor variable in
73. ble boosting select the L option G 1 10 100 or 1000 for high level signals that don t require as much amplification select the H option G 1 2 4 or 8 The PDL MF board ships two versions both with G 1 2 5 or 10 MFS Series boards ship standard only with unity gain for other gains G 1 2 5 or 10 you must purchase the DG option An A D FIFO holds digitized samples until the DSP transfers them into host memory over the PCI PXI bus The default A D FIFO size starts at 1k samples and depending on the board model can be as large as 4k samples You can upgrade the FIFO to 16k 32k or 64k samples depending on application requirements Note that while larger FIFOs achieve smoother operation especially at high acquisition rates there is a tradeoff in terms of response time Specifically the driver normally transfers data from the buffer only when the FIFO is half full so a larger buffer means you wait longer for a transfer This extra time can degrade system response in closed loop control applications A calibration D A generates voltages to adjust the offset and gain settings on the analog input section to ensure accurate performance As noted in the previous section all boards are factory calibrated for each input range and mode The timing triggering and clocking controls allow you to select the timebase clock and triggering sources a slow bit and other options An interrupt mechanism notifies the DSP of special conditi
74. c PD2 MFS x 800 14 14 800 kHz 1 25 usec 3 0 usec 900 nsec 700 nsec PD2 MFS x 500 14 14 500 kHz 2 0 usec 3 0 usec 900 nsec 700 nsec PD2 MFS x 333 16 16 333 kHz 3 0 usec 10 0 usec 900 nsec 700 nsec PDL MF Series Timing Board Model Resolution Speed Gain Fast Acq Slow Acq Delay no Delay Slow Bits PDL MF PDL MF 50 16 50 KkHz 1 2 5 10 20 usec N A PDL MF 333 16 333 kHz 1 2 5 10 3 usec N A 133 Appendix B PowerDAQ A D Timing 134 Appendix B PowerDAQ A D Timing PDXI MF Series Timing Board Model Resolution Speed Fast Acq Slow Acq Delay Gain Delay using Slow Bits PDXI MF xx 2M 14H 14 1 65 MHz Low 450 nsec 3 0 usec PDXI MF xx 1M 12L 12 1 25 MHz High 800 nsec 20 0 user PDXI MF xx 1M 12H 12 1 25 MHz Low 800 nsec 5 0 usec PDXI MF xx 800 14L 14 800 kHz High 1 25 usec 20 0 user PDXI MF xx 800 14H 14 800 kHz Low 1 25 usec 10 0 usec PDXI MF xx 500 16L 16 500 kHz High 2 0 usec 20 0 user PDXI MF xx 500 16H 16 500 kHz Low 2 0 usec 10 0 usec PDXI MF xx 400 14L 14 400 kHz High 2 5 usec 25 0 usec PDXI MF xx 400 14H 14 400 kHz Low 2 5 usec 10 0 usec PDXI MF xx 333 16L 16 333 kHz High 3 0 usec 20 0 user PDXI MF xx 333 16H 16 333 kHz Low 3 0 user 10 0 usec PDXI MF xx 150 16L 16 150 kHz High 6 0 usec 20 0 user PDXI MF xx 150 16H 16 150 kHz Low 6 0 usec 10 0 usec PDXI MF xx 100 16L 16 100 kHz Low
75. c so you have access to data every 5 msec In Bus Mastering you have no access to new data until incoming data can fill a full bus master page which is at least 4096 samples Thus you would have to wait 41 msec to have access to that data Another factor to consider is that under Normal and Fast modes but not Bus Master modes you can take advantage of the PdlmmediateUpdate command Among other things it immediately fetches all acquired samples from the board This command is particularly useful in these cases 1 Acquisition rates 10k samples sec If a board running at 100 Hz has the default A D FIFO of 1k samples and if you select a frame size of 50 samples you ll get 11 68 5 Analog Input Subsystem frames per event a frame every 5 5 sec To achieve better response time include PdimmediateUpdate call in a timer loop 2 When you want to clock an acquisition externally and the clock frequency can vary we recommend you call PdImmediateUpdate periodically to see if any scans are available 3 Be aware that PdImmediateUpdate consumes some processor time Thus for boards running at high acquisition rates 7100k samples sec we do not recommend that you call this function more then 10 times sec Host based buffer usage What you do with the data once they arrive in host memory can also have a major impact on system performance The PowerDAQ drivers set up an Advanced Circular Buffer ACB When combined with applications
76. cations running on the PC during acquisition so that the system cannot service the interrupt in time Consider using an A D FIFO upgrades to improve system performance PD 16KFIFO or PD 32KFIFO or try Method 3 bus mastering Initiate asynchronous operation PdAInAsynciInit This command sets up the data acquisition hardware with all its basic parameters such as input mode type range and clock sources Again you define these settings in the bits of dwAInCfg Provide a value for dwAInCICIKkDiv to set the desired scan rate Fill and pass the Channel List as explained in Method A Make sure that that the aggregate rate you have set up scan rate number of channels is lower or equal to the maximum board rate Set up event notification PdAInSetPrivateEvent The API creates Win32 events and returns a valid event handle Acquisition Start asynchronous operation PdAInAsyncStart and either have the user app issue a software trigger or wait for a hardware trigger and then wait for event notification that the card has digitized some data The following function puts your program into Sleep mode and gives the system CPU time for other processes The function returns control when the board signals an event or the timeout period has expired The timeout period should be long enough to fill your buffer with samples When this function returns an event from the board you must check to see what caused it WaitForSingleObject hEv
77. channel 1 2 5 10 Drift Zero Gain E30 uV C 30 ppm C Input Impedance 1MQ Input Bias Current Input Overvoltage 18V SE 40V DI A D Conversion Time 2 usec 2 0 usec 3 psec SSH Amp Settling Time 1 2 usec 1 2 usec 1 2 usec A D Settling Time 1 5 usec 1 2 usec 2 7 usec DC Accuracy Nonlinearity 1 LSB 1 LSB 1 LSB no missing codes AC Accuracy Effective Number of Bits 13 8 12 7 13 8 Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 500k S sec 300k S sec External A D Sample Clock Maximum Frequency 500k S sec 300k S sec Minimum Pulse Width 20 nsec External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec 118 Appendix A Specifications Analog Outputs all PD2 MFS models Number of Channels 2 Resolution 12 bits Update Rate 200k S sec each Onboard FIFO Size 2k samples on DSP Analog Output Range 10V Error Gain 1 LSB Zero Calibrated to 0 Current Output 20 mA max Output Impedance 0 30 typ Capacitive Drive Capability 1000 pF Nonlinearity 1 LSB Protection Short circuit to analog ground Power on Voltage OV 10 mV Setting Time to 0 01 of FSR 10 psec 20V step 1 usec 100 mV step Slew Rate 30 V usec Counter Timers
78. ckel copper and Balco nickel iron alloys are also used Platinum is popular due to its wide temperature range accuracy stability as well as the degree of standardization among manufacturers RTDs are characterized by a linear positive change in resistance with respect to temperature They exhibit 161 Appendix G Glossary RTSI S samples sec scan SDK SE self calibrating sensor S H simultaneous sampling single ended Slow Bit SNR software trigger SPDT SSH S s S sec strain gage 162 the most linear signal over temperature of any electronic sensing device Real Time Systems Integration bus developed by National Instruments this intercard bus allows you to transfer data and control signals without using the backplane bus expresses the rate at which a DAQ board digitizes an analog signal one run through the presently configured Channel List Software developer s kit a collection of drivers and utilities that allow engineers to write their own application programs see single ended reference to a DAQ board that calibrates its own A D and D A circuits with a reference source sometimes provided internally with a precision D A converter A device that generates an electrical signal in response to a physical stimulus such as heat light sound pressure motion or flow Sample Hold a circuit that acquires and stores an analog voltage on a capacitor for a short period of time the
79. cumentation The CD label shows the version number of the SDK Precautions PowerDAQ boards contain sensitive electronic components When handling your PowerDAQ board you should ensure that you are properly grounded discharge any static electricity by touching the metal part of your PC while holding the board in its antistatic bag 15 3 Installation and Configuration Installing the software Note All third party software must be installed prior to installing the PowerDAQ SDK Note The PowerDAQ SDK must be installed before you plug in a PowerDAQ board to ensure that the driver properly detects the board To install the PowerDAQ SDK 1 Start your PC and if running Windows NT 2000 or XP log in as an administrator 2 Insert the PowerDAQ Software Suite CD into your CD ROM drive Windows should automatically start the PowerDAQ Setup program If you see the UEI logo and then the PowerDAQ Welcome screen go to Step 6 If the Setup program does not start automatically select Run from the Start menu 4 Enter D Setup exe in the Open textbox substitute the correct letter if D is not the drive letter for your CD ROM drive 5 Click OK Welcome to the PowerDAQ Setup program This program will install PowerDAG on your computer LA It is strongly recommended that you exit all windows programs before running this Setup program United Click Cancel to quit Setup and then close any programs you DER 10 UA have unning
80. detected using a configuration word as described earlier in this section PdAdapterEnablelnterrupt with dwEnable set to 1 _PdDInSetPrivateEvent sets up event object PdSetUserEvent and use Digitalln as a subsystem name The driver defines only one digital input event eDInEvent which means that one or more edges were detected Event handler Check event _PdGetUserEvent should return the eD nEvent flag in the status word Read the status of the digital input latch _PdDInGetStatus 99 7 Digital O Subsystem This function returns the current state of the digital input lines in one byte and the status of the digital input latch register in a second byte If the specified edge was detected the latch contains a One in the appropriate bit Clear the status of the digital input latch with _PdDInClearData It clears the latch register and re enables edge detection on the line that previously caused an event Re enable events with PdSetUserEvent and use Digitalln as a subsystem name The driver defines only one digital input event eDInEvent which means that one or more edges were detected De Initialization Disable interrupts if there is no other subsystem running _PdAdapterEnableInterrupt with dwEnable set to 0 Release the event object and clear user level events _PdDInClearPrivateEvent PdClearUserEvent and use DigitalIn as the subsystem name Reset the digital inputs
81. e e when measuring the output from high impedance sensors such as strain gauges because their high impedances can lead to higher common mode voltages which the differential inputs are able to remove thus leading to higher resolution Instrumentation Source 1 Bing Amplifier z ni Source 2 Figure 5 2 Wiring for differential inputs In the pin assignment of Fig 3 8c Aln8 has the name AInOReturn while AIn9 has the designation AInl Return 50 5 Analog Input Subsystem Do not drive positive and negative differential inputs with voltages that exceed a value of AGND 4 14V otherwise the input multiplexers could lock up and even be damaged Always connect equipment grounds together in a star configuration with low resistance Overall Recommendations In summary when wiring applications the analog input subsystem keep the following factors in mind Pseudodifferential inputs cannot eliminate the effects of noise Use differential inputs when working in an environment with electrical noise or when using gains to amplify the raw signal Use individually shielded twisted pair wires between the sensor and the terminal panel and also connect the shield to analog ground when working in an environment with electrical noise Run signal lines near devices that create high levels of electrical noise through a metal cable tray above or below the work area Keep wiring paths or conduit
82. e based Start trigger Now if you have selected the software clock clock the first scan into the A D FIFO PdAInSwClsStart Acquisition Now the user application can instruct the board to collect analog samples as required using the onboard timer or a program loop In either case you must allow sufficient time for the A D to acquire all points in a scan and digitize the entire Channel List You normally allow 1 maximum board rate seconds for each channel As described earlier PowerDAQ boards have a special Slow Bit you can insert in the Channel List You might want to increase settling time for a particular channel when you ve selected a high gain setting or for a channel connected to a signal with a high output impedance See Appendix B for each specific board to determine how much a Slow Bit affects the time needed to acquire a channel Get the samples already acquired out of the A D FIFO and move them into the array declared in the user application PdAInGetSamples If you have selected the software clock clock in the next scan PdAInSwClsStart If you are using external pulses to start clocking of the Channel List make sure to address the situation whereby the next scan clock comes during the PdAInGetSamples call This function returns the number of points stored in the buffer If the number of scans equals the A D FIFO size the subsystem could lose scan synchronization because you might not be aware of an ov
83. e device on the back side of the board that combines an instrumentation amp and a programmable gain amplifier As with MF Series 54 5 Analog Input Subsystem boards you store channel numbers along with their respective gains in the Channel List memory This mechanism allows you to select different gains on a per channel basis Analog Input 0 to range control calibration Analog circuitry and Input 0 ADC S H Channel select acquire signal selection control signal signal Figure 5 4a Analog front end on PowerDAQ MFS simultaneous sampling boards with both SE and DI modes available Here again t is the board s conversion time which is limited by the A D s maximum speed and the ability of the board s input amplifiers to settle Compared to a multiplexed MF Series board though t represents the hold time after the board has switched the sample hold amp into the Hold state t is the time the sample hold amp requires to once again start tracking the input signal after the board has switched it back into Sample mode Given these parameters you can determine t the minimum time between scans as the sum of t2 t3 t number of channels The maximum scan rate now equals 1 tn PowerDAQ boards use analog pipelines to cut down both the settling time and the sample hold times 55 5 Analog Input Subsystem LEE T Hold Sample lime EH Moment of Digiti
84. e only limitation which consequently results in more efficient performance is that the logical buffers in the buffer queues cannot be dynamically allocated and freed In addition their order is fixed 149 Appendix E Application Notes 2 PD BNC xx wiring options Voltage dividers To build a voltage divider install resistors in the ROA RSA and ROC positions for the Ch and Ch8 pair and similarly for other pairs Note that when supplied by the factory the RxA resistors have 0Q wire jumpers installed Lowpass filtering To build a lowpass filter install resistors in the ROA and R8A positions Also install a capacitor in the COB position for the Ch 0 and Ch 8 pair and for other pairs as well Note that when supplied by the factory the RxA resistors have 0Q wire jumpers installed Highpass filtering In order to build a highpass filter install capacitors in the ROA and R8A positions Also install a resistor into the COB position for the Ch 0 and Ch 8 pair and for other pairs as well Note that when supplied by the factory the RxA resistors have 0Q wire jumpers installed 150 Appendix F Warranty All PowerDAQ boards have received CE Mark certification according to the following EN55011 EN50082 1 UEI Terms and Conditions for all products are available as copies on demand and online at http ueidag com company terms aspx 151 Appendix G Glossary A ACB A D see ADC adapter ADC
85. e parameters Deinitialize the subsystem Stop asynchronous operation PdAOutAsyncStop PdAOutAsyncTerm Release event object handle optional PdAOutClearPrivateEvent Release the buffer _PdReleaseBuffer Clear the subsystem and set both outputs to OV optional _PdAOutReset Method C Continuous waveform generation Method C uses the PowerDAQ Advanced Circular Buffer mechanism see Appendix E Here you work with one frame of a buffer you set up in host memory while the driver empties the other frames In this way the output can run continuously and each time an event occurs the application takes control You can create separate threads in your application to run the acquisition process Initialization Reset analog output if required _PdAOutReset 89 6 Analog Output Subsystem Acquire buffer for analog output _PdAcquireBuffer set the BUF BUFFERWRAPPED flag and fill the buffer with data Initialize asynchronous operation _PdAOutAsynclnit and set dwConfig AOB CVSTARTO to use internal clock and calculate the divisor as described above Set up event notification PdAOutSetPrivateEvent Start waveform generation Start asynchronous operation PdAOutAsyncStart Wait for an event from the board or a timeout WaitForSingleObject hEventObject Timeout Event handler Check why the event object was set with PdGetUserEvents Check where to put new data
86. e reading now It explains which products are covered and gives you tips on how to best use this manual Chapter 2 PowerDAQ MF MES Series Features Overview This chapter provides an overview of the key features of the PowerDAQ series and detailed information on the various PowerDAQ models currently available It also lists what you need to get started Chapter 3 Installation and Configuration This chapter explains how to install and configure your PowerDAQ board Among other things it shows where various I O connectors are located on various boards and also shows their pinout definitions Chapter 4 PowerDAQ Architecture This chapter discusses the subsystems of your PowerDAQ board and it gives an overview of the programming model showing how various cards and software modules intercommunicate Chapter 5 Analog Input Subsystem This and the following three chapters are each devoted to one of the PowerDAQ MF MFS Series subsystems Each chapter is divided into two major sections The first gives a description of the hardware and gives tips for making best use of these features in a test system The second section introduces you to the best way to program this subsystem and reviews the most frequently used commands and operating methods Chapter 6 Analog Output Subsystem This chapter contains two major sections the first describes the hardware and its features the second introduces you into techniques for programming this subsystem Cha
87. ector J1 96 pin high density Fujitsu connector male Fujitsu PN FCN 245P096 G U Connector J2 36 pin header connector male Thomas and Betts PN 609 3627 Connector J4 36 pin header connector male Thomas and Betts PN 609 3627 Connector J6 8 pin male connector Adam Tech PN PH2 SMT 8 SGA Appendix A Specifications PDL MF Lab Multifunction Boards upgradeable to 32k Model PDL MF x 50 333 Resolution 16 bits Number of Channels Single Ended 16 Pseudo Differential 16 Differential 8 Maximum Sampling Rate 50k S sec 333k S sec single or multiple channel Onboard FIFO Size 1k samples 64k samples with SRAM option Channel Gain List 64 entries Input Ranges 0 10V 5V 10V software selectable Programmable Gains 1 2 5 10 Drift Zero 30 pV C Gain 30 ppm C Input Impedance 10 MO Input Bias Current 20 nA Input Overvoltage 35V cont 10 mA max A D Conversion Time 2 7 usec 1 8 usec A D Settling Time gain 1 20 usec 3 usec DC Accuracy Nonlinearity 1 LSB System Noise 1 2 LSB AC Accuracy Effective Number of Bits 14 8 Total Harmonic Distortion 91 dB Nonlinearity Noise Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 50k S sec 333k S sec Aggregate Throughput 0 01 Accuracy External A D Sample Clock Maximu
88. ector pinouts from PowerDAQ board PD CONN CBL 96 way pinless 0 5m round shielded cable with metal cover plate bare wires at one end PD CONN PCB PowerDAQ mating connector with pc board attached PD CONN 9696 PowerDAQ connector for interfacing to custom OEM boxes or equipment PD CONN NI Converts 100 way NI multipurpose analog digital connector to the PowerDAQ 96 way analog and 37 way digital connectors PD CONN STR Individual Fujitsu connector PN FCN 244P096 G E with a vertical pc board mount PD CONN RTA Individual Fujitsu connector PN FCN 245P096 with a right angle pc board mount version used on PowerDAQ boards PD 19RACK 19 rack holds 3 5 deep terminal panels such as the PD STP 96 PD STP 9616 and PD BNC 16 PD 19RACKW 19 rack wide version holds 7 deep terminal panels such as the PD TCR 16 x or PD BNC 64 PD SBCONN Connects 16 or 64 channel PowerDAQ board to one to four 5B xx racks PD 7BCONN Connects 16 or 64 channel PowerD AQ board to one to four 7B xx racks PD 100HDR Connects 16 or 64 channel PowerDAQ board to two 50 way IDC headers 139 Appendix C Accessories Signal Conditioning all boards PD PSU 5 15 Power supply 110 200V ac in 5V 5V dc out for use with PD TCR4 16 x racks or with PD ASTPs PD SCXU AOMUX 8 channel analog output multiplexer PD ASTP 16 16 channel AlIn active screw terminal panel G 1 6 dB cutoff 100 Hz PD ASTP 16X 16 channel ASTP pane
89. eeds to perform exhaustive calculations and change equipment settings Instead of stopping and restarting the process Recycling buffer mode allows the data acquisition to keep running After processing is completed the control application catches up with the latest data This mode is also suited for pretriggering applications 81 5 Analog Input Subsystem Examples in the SDK that fall into the category of Method D are e Stream e To switch your buffer into this mode first call PdAcquireBuffer and be sure to set dwWrapAround BUF BUFFERRECYCLED to use the ACB s Recycled mode Combining Analog and Digital subsystems It s often desirable to coordinate analog inputs with digital inputs When doing so the part that requires special attention is event handling The PowerDAQ API has two sets of functions to address this issue 1 Set up all subsystem operations in one thread and create an event using PdSetPrivateEvent This function creates a single event that is set when either subsystem needs attention Be sure to retrieve and process each active subsystem event in the order they arrive To release a event object use PdClearPrivateEvent 2 Set up each subsystem operation in a separate thread You can create a separate event object for each subsystem using PdAInSetPrivateEvent PdAOutSetPrivateEvent _PdDInSetPrivateEvent PdUctSetPrivateEvent When one of these subsystem needs atte
90. entObject Timeout If the board is clocked from the low frequency internal timebase or a slow external clock you likely won t get an immediate event notification upon the acquisition of the first datapoints This is because the board transfers data from the on board A D FIFO into host memory only when the FIFO reaches 50 capacity For example if your board s FIFO size is 1k samples the acquisition rate is 100 Hz and you put only one channel into the Channel List the board notifies the driver and thus the application only after 500 samples 5 sec of acquisition no matter how small your frame is If you clock the board externally no response comes from the board until it gets enough pulses to fill its FIFO half full with samples However you can use _PdImmediate Update on a timer loop to force data from the A D FIFO into the host buffer Don t call this function too often because it can degrade system performance Note also that this function does not work in Bus Mastering mode 77 5 Analog Input Subsystem Check events with the function PdGetUserEvents This function returns events for the specified subsystem here be sure to specify Analogin The user application should analyze the events and take appropriate action An event word can contain following flags e eFrameDone a frame of data is ready for retrieval e eBufferDone eStopped Acquisition is complete All data is stored in the buffer and is available
91. entries Programmable Gains 256 entries by channel Drift Zero 30 uV C Gain 30 ppm C Input Impedance 1MQ Input Bias Current 100 pA Input Overvoltage A D Conversion Time 0 45 psec 0 8 usec 1 25 usec SSH Amp Settling Time 0 7 usec 0 9 usec 1 0 usec A D Settling Time 0 4 usec 0 6 usec 1 25 usec DC Accuracy Nonlinearity 2 LSB 0 5 LSB 0 5 LSB no missing codes AC Accuracy Effective Number of Bits 12 1 11 3 12 7 Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 1500k S sec 4 ch 975k S sec 4 ch 800k S sec 1700k S sec 8 ch 1095k S sec 8 ch External A D Sample Clock 1500k S sec 4 ch 975k S sec 4 ch Maximum Frequency 1700k S sec 8 ch 1095k S sec 8 ch 800k S sec Minimum Pulse Width 20 nsec External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec 117 Appendix A Specifications Model PD2 MFS xx 500 16 500 14 300 16 Resolution 16 bits 14 bits 16 bits Number of Channels Single Ended 4 8 optional Differential 4 8 optional Maximum Sampling Rate 500k S sec 500k S sec 300k S sec multiple channels Onboard FIFO Size upgradeable to 1k samples 16k 32k 64k Input Ranges 0 5V 0 10V 5V 10V software selectable Channel Gain List 256 entries Programmable Gains by
92. ep up with the acquisition process and the buffer overflows then the acquisition is stopped and the error condition is reported Recycled Circular Buffer The Recycled Circular Buffer mode is similar to the Circular Buffer mode except that when the head pointer catches up with the tail pointer the tail pointer is automatically incremented to the next frame boundary This buffer space recycling occurs irrespective of whether the application read the data or not In this mode a buffer overflow condition never occurs The Recycled Circular Buffer is best suited for applications that monitor acquired signals at periodic intervals The application may require the signals to be acquired at a high rate but not all acquired samples need to be processed Also an application may only need the latest block of samples acquired As the buffer fills up the driver is free to recycle frames automatically incrementing the buffer tail and using the space to store new samples While the Advanced Circular Buffer may appear a much different buffering mechanism when compared to the much simpler single and double buffer mechanisms it is actually a superset of the simpler buffers The ACB configured in the single buffer mode will behave just as the simple ordinary single buffer If the ACB is configured as Circular Buffer with two frames it will behave as a double buffer With multiple frames the ACB can be used in algorithms that were designed for buffer queues Th
93. er ground Digital input output Dynamic Link Library a software module in Microsoft Windows containing executable code and data that can be called or used by Windows applications or other DLLs Functions and data in a DLL are loaded and linked at run time when they are referenced by a Windows application or other DLLs Differential nonlinearity a measure in LSBs of the worst case deviation of code widths from their ideal value of 1 LSB Direct Memory Access a method of transferring data to from computer memory from to a device or memory on the bus taking place while the host processor does something else DMA is the fastest method of transferring data to from computer memory Software that controls a specific hardware device such as a DAQ board 155 Appendix G Glossary DSP dual access memory dual port memory dynamic range E EEPROM encoder EPROM event event based mode external trigger F FIFO fixed point floating point 156 Digital signal processing Memory that can be sequentially accessed by more than one controller or processor but not simultaneously Also known as shared memory Memory that can be simultaneously accessed by more than one controller or processor The ratio normally expressed in dB of the largest signal level in a circuit to the smallest signal level In DAQ boards it typically refers to the range of signals a board can handle or the amount of noise it su
94. er line motors generators transformers fluorescent lights soldering irons CRT displays computers electrical storms welders radio transmitters as well as internal sources such as semiconductors resistors and capacitors Object Linking and Embedding a set of system services that provides a means for applications to interact and interoperate Based on the underlying Component Object Model OLE is object enabling system software Through OLE Automation an application can dynamically identify and use the services of other applications OLE also makes it possible to create compound documents consisting of multiple sources of information from different applications see ActiveX controls Base level software that controls a computer runs programs interacts with users and communicates with installed hardware or peripheral devices The technique of using an optoelectric transmitter and receiver to transfer data without electrical continuity to eliminate high potential differences and transients see operating system The amount of time required for the analog output voltage of an amplifier to reach its final value within specified limits The rate of change of an analog output voltage from one level to another The amount of computer processing resources such as time or memory required to accomplish a task A technique used for extending the address range of a device to point into a larger address space 159 Appendix G
95. erboard has an Advanced Interrupt Controller simply enable it in the BIOS This allows you to use more than 16 generic interrupt lines If you don t have this facility use manual settings to assign the interrupt to the PCI slot where PowerDAQ board is installed Modern motherboards can easily contain four five or even more PCI slots plus integrated PCI devices such as networking modules and a video driver Usually only three of these slots are independent and don t share interrupts with these host system peripherals Please refer to your motherboard manual to find out which slots share interrupts and cannot be used for fast data acquisition PowerDAQ boards are designed to share interrupts but we do not recommend that they share interrupts with devices such as video drivers network cards or hard disks These devices tie up interrupt lines extensively and can significantly delay responding to an interrupt from a data acquisition board Although Windows 9x NT 2000 are not realtime operating systems your PowerDAQ board is a real time system within the PC thanks to its own DSP and realtime kernel Many motherboard manufacturers allow you to set an IRQ level to a particular PCI slot If you do not use your PC s serial or parallel ports you can disable them and use IRQ 3 4 5 or 7 for your data acquisition boards Connectors for PD2 MF MFS Series boards PowerDAQ PD2 Series multifunction boards have four connectors e A main bracket connector fo
96. errun condition It s possible to enable disable conversions on the fly with PdAInEnableConw and you can clear the A D FIFO with _PdAlnClearData Method B Burst buffered acquisition 1 shot This method is useful when you need a series of 1 shot acquisitions with a significant delay between runs An example of such an application might be when simulating an oscilloscope or signal analyzer where you run an acquisition one time stop the process analyze the data and run it again as required However the size of the acquired data likely require buffered A D FIFO reads Consequently this method requires initializing and use of the PowerDAQ buffering mechanism see Appendix E Method B uses an asynchronous notification from the driver through Win32 events Thus you should program the board for asynchronous operation and use Win32 function such as WaitForSingleObject to initiate a wait until the driver notifies that the data has been successfully acquired 75 5 Analog Input Subsystem Examples in the SDK that fall into the category of Method B are e Stream e SimpleExample vbp Programming Model Initialization Reset the board PdAInReset Allocate and register a buffer for the board The buffer should be accessible in both the user and kernel spaces and it should be locked to the physical pages Use as big a buffer as you need its size is limited by the amount of memory installed on your PC The buffe
97. es sec 14 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 16 400 14H 400k samples sec 14 bit A D 16 SE 8DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 64 400 14L 400k samples sec 14 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 64 400 14H 400k samples sec 14 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 16 333 16L 333k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 16 333 16H 333k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 64 333 16L 333k samples sec 16 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 64 333 16H 333k samples sec 16 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D A PDXI MF 16 150 16L 150k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 16 150 16H 150k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 2 4 8 two 12 bit D As Table 2 3 PowerDAQ PDXI MF Series Models All PDXI MF Series models also include three counter timers and 32 digital I O lines 11 2 PowerDAQ MF MFS Series Features Overview PowerDAQ PDXI MFS Series Model Analog features PDXI MFS 4 2M 14 2M samples sec 14 bit A D 4
98. ess DE 8000000 IRQ number 5 m Driver Information Version 23 Build Type Release Build Timestamp Mon Jan 22 13 34 31 2001 Figure 3 2 Control Panel Application 18 3 Installation and Configuration Configuring a PowerDAQ board Figure 3 3a Connector layout for long slot PD2 Family boards The layout in Fig 3 3a is used for old legacy PD2 MF boards and legacy PD2 MFS boards which have since been converted to a sandwich design Fig 3 3b This diagram points out any on board connectors or headers of interest to end users all others are reserved for factory use 19 3 Installation and Configuration A0 JA1 Figure 3 3b Connector layout for sandwich format PD2 family boards The Sandwich format Fig 3 3b is used for all MFS Series boards and MF Series boards Note that you make external connections to the analog I O section with the JAI Connector the J1 Connector serves to make electrical connections between the motherboard and the daughtercard This diagram points out all available on board connectors or headers of interest to end users all others are reserved for factory use PowerDAQ MF S cards using the sandwich form factor add support for the RTSI intercard communications bus on J10 20 3 Installation and Configuration Some PD2 Family boards now ship in the alternate short slot sandwich form factor in Fig
99. ffset from Step 2 6 Ifthe board applied a gain other than 1 to a selected channel as defined in the Channel List divide the value from Step 5 by this gain factor this step guarantees maximal data accuracy 72 5 Analog Input Subsystem Programming Techniques With this knowledge of the analog input hardware you are better prepared to understand how to program the board to perform various digitizing functions This subsystem is very flexible and it offers a variety of operating methods Before selecting one it s wise to read through this manual to understand what each does and then compare it to the application requirements With any of these methods you must first specify how you are using the analog inputs whether in single ended or differential mode and indicate the range of the raw inputs prior to applying any gain To tell a user program which you have selected you must OR the analog input configuration word dwAInCfg with one of the Mode constants in Table 5 10 Input Mode Constant for use in dwAInCfg Single Ended 0 5V 0 Single Ended 0 10V AIB INPRANGE Single Ended 5V AIB INPTYPE Single Ended 10V AIB INPTYPE AIB INPRANGE Differential 0 5V AIB INPMODE Differential 0 10V AIB INPMODE AIB INPRANGE Differential 5V AIB INPMODE AIB INPTYPE Differential 10V AIB INPMODE AIB INPTYPE AIB INPRANGE Not available in PDL MF Table 5 10
100. function calls that provide access the functions in a driver or other utility 1 Hardware A property of an event that occurs at an arbitrary time without synchronization to a reference clock 152 Appendix G Glossary B background acquisition base address bipolar bit Block mode Burst mode bus bus master byte C cache calibration channel list Channel List FIFO 2 Software A property of a function that begins an operation and returns prior to the completion or termination of the operation Data is acquired by a DAQ system while another program or processing routine is running without apparent interruption A memory address that serves as the starting address for programmable registers All other addresses are located by adding to the base address A signal range that includes both positive and negative values for example 5V to 5V also represented as 5V One binary digit either 0 or 1 A high speed data transfer in which the address of the data is sent followed by a specified number of back to back data words A high speed data transfer in which the address of the data is sent followed by back to back data words while a physical signal is asserted The group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected Examples of PC buses are the PCI bus and the PXI bus A type of
101. ges 0 5V 0 10V 5V 10V software selectable Channel Gain List 256 entries Programmable Gains by channel 1 2 5 10 Drift Zero 30 uV C Gain 30 ppm C Input Impedance 1 MO Input Bias Current 100 pA Input Overvoltage 18V SE 40V DI A D Conversion Time 0 45 usec 0 8 usec 1 25 usec SSH Amp Settling Time 0 7 usec 0 9 usec 1 0 usec A D Settling Time 0 4 usec 0 6 usec 1 25 usec DC Accuracy Nonlinearity 2 LSB 0 5 LSB no missing codes AC Accuracy Effective Number of Bits 12 1 11 3 12 7 Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 1500k S sec 4 ch 975k S sec 4 ch 800k S sec 1700k S sec 8 ch 1095k S sec 8 ch External A D Sample Clock 1500k S sec 4 ch 975k S sec 4 ch Maximum Frequency 1700k S sec 8 ch 1095k S sec 8 ch 800k S sec Minimum Pulse Width 20 ns External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec 127 Appendix A Specifications Model PDXI MFS xx 500 16 500 14 300 16 Resolution 16 bits 14 bits 16 bits Number of Channels Single Ended 4 or 8 Differential optional 4 or8 Maximum Sampling Rate 500k S sec 300k S sec multiple channels Onboard FIFO Size 1k samples u
102. gnal on an external trigger input line To calculate the output frequency use the following formula Acquisition Rate Base Frequency divisor 1 To calculate the divisor use Divisor Base Frequency Acquisition Rate 1 86 6 Analog Output Subsystem Triggering The external trigger line can serve as a Start Stop trigger for free running analog outputs You can select the internal clock as the analog output timebase and then use the trigger line to start and stop the output Additionally the external trigger line can synchronize the analog input and the analog output subsystems Programming Techniques Let s now take a look at how to program a PowerDAQ MF MFS card s analog output subsystem for each of the operating methods described above Method A Single update This simple method allows you to update the analog output value on either or both D As immediately Examples in the SDK that fall into the category of Method A are e SimpleAOut cpp e SimpleTest vbp Initialization Reset the board if required _PdAOutReset Generate output Output the analog output value _PdAOutPutValue 87 6 Analog Output Subsystem Method B Single shot waveform generation This method is useful when you need a series of single shot waveforms with a significant delay between runs where you output the waveform one time stop the process and run it again as required However the size of the waveform dat
103. gramming to enable their operation All PD2 MFS Series models come standard only with G 1 for other gains you can purchase the DG option outlined in Table 2 5 10 2 PowerDAQ MF MFS Series Features Overview PowerDAQ PDXI MF Series Model Analog features PDXI MF 16 2M 14H 2 2M samples sec 14 bit A D 16 SE 8 DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 64 2M 14H 2 2M samples sec 14 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 16 1M 12L 1 25M samples sec 12 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 16 1M 12H 1 25M samples sec 12 bit A D 16 SE 8 DI inputs Gains 1 2 4 8 two 12 bit D A PDXI MF 64 1M 12L 1 25M samples sec 12 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 64 1M 12H 1 25M samples sec 12 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 16 500 16L 500k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 16 500 16H 500k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 64 500 16L 500k samples sec 16 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PDXI MF 64 500 16H 500k samples sec 16 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D As PDXI MF 16 400 14L 400k sampl
104. gregate Throughput 1800k S sec all 0 01 accuracy External A D Sample Clock 2200k S sec 1 ch 1250k S sec 500k S sec Maximum Frequency 1800k S sec all Minimum Pulse Width 20 nsec External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec 123 Appendix A Specifications Model PDXI MF xx 400 14x 333 16x 150 16x Resolution 14 bits 16 bits 16 bits Number of Channels Single Ended 16 or 64 16 Differential 8 or 32 8 Maximum Sampling Rate 400k S sec 333k S sec 150k S sec Onboard FIFO Size 1k samples upgradeable to 16k 32k 64k Channel Gain List 256 entries Input Ranges 0 5V 0 10V 5V 10V software selectable Programmable Gains by channel L 1 10 100 1000 H 1 2 4 8 Drift Zero 30 pV C Gain 30 ppm C Input Impedance 10 MQ Input Bias Current 20 nA Input Overvoltage 35V continuous A D Conversion Time 2 5 usec 2 0 usec 6 usec A D Settling Time 2 0 usec 1 2 usec 5 psec DC Accuracy Nonlinearity 0 5 LSB 1 LSB 1 LSB System Noise 0 8 LSB 1 3 LSB 1 2 LSB AC Accuracy Effective Number of Bits 13 1 14 5 14 8 Total Harmonic Distortion 81 dB 89 dB 91 dB Nonlinearity Noise Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 400k S sec 333k S sec 150k S sec Aggregate Throughput 0 0196 acc
105. guration DOUT1143 1 2 DIN DIN 3 4 DOUT O DOUTE 5 6 FoNN DINN 7 8 r DOUTO DOUTB 4 9 DIN O DIN5 11 12 DOUTS pouT 13 4 DIN9 DOUT lp F DGND DGND4 17 18 DIN8 DGND4 9 20 5VP2 DGND4 21 22 DGND DGND 23 24 CL DONE OUT DGND 25 26 CL START OUT BACK DGND 27 28 DGND DGND 129 30 DGND DGND 31 32 CL START OUT DGND 433 34 CL START IN BACK DGND 35 36 DGND DGND 137 38 L TRIG IN BACK DGND 39 40 DOUT7 DGND 41 42 CL START IN BACK DGND 43 44 DOUT6 DGND 145 46 DIN7 DGND47 48 DOUTS DGND 49 50 DING DGND 51 52 DOUT4 DGND 153 54 DINS DGND 55 56 DOUT3 DGND 157 58 DIN4 DGND 59 60 DOUT2 DGND 61 62 DIN3 DGND 63 64 DOUT1 DGND 165 66 DIN2 UCTO_CLK_IN 67 68 DOUTO UCT2_CLK_IN 69 70 DIN1 UCTO OUT471 72 DGND UCT2 OUT473 74 DINO UCTO_ GATE 75 76 5VP2 UCT2 GATE477 78 UCT1 OUT UCT1 OK IN 179 80 UCTI GATE Figure 3 14b Pin assignments of J2 Connector on PDXI MF MES Series boards The PXI TRIG 0 7 and PXI STAR lines on the PXI system backplane located on Connector P2 above Connector P1 can be used for interboard synchronization 34 3 Installation and Configuration Simple Test program After wiring external signals to your PowerDAQ board run the PowerDAQ Simple Test program to verify th
106. gured Channel List In contrast a frame consists of a user defined number of scans and these datapoints reside in a predefined portion of a buffer in host memory This host memory buffer is also known as the Advanced Circular Buffer ACB We elected to define these two objects to give you the utmost in flexibility when deciding how to collect data Keeping both scans and frames in mind we will now examine the various methods of moving data from the data acq card into the host PC where the application can use it Moving data into the host PC Once you have acquired samples into the A D FIFO buffer you can choose from four modes that transfer data into host memory for use by the user application e Normal Mode e Fast Mode e Bus Mastering e Bus Mastering Short Burst It s unusual that a program will use more than one of these methods Thus the normal procedure is to select the desired transfer mode by going to the PowerDAQ Control Panel application clicking on the Driver Settings tab and selecting the mode In the unusual event that you do want to change transfer modes from within a user application use the software command 64 5 Analog Input Subsystem _pdDiagSetPrm However use this function with great caution If not set up exactly right the host system could easily lock up 1 Normal mode In some cases all the datapoints from an acquisition run fit easily into the A D FIFO In that case you can use software commands to
107. h counter timer eUct0Event eUctl Event and eUct2Event 105 8 User Counter Timer Subsystem Event handler Check for an event _PdGetUserEvent can return either the eUctOEvent eUctI Event or eUct2Event flag in the status word Read the status of the UCT output PdUctGetStatus Re enable events PdSetUserEvent Deinitialization Disable interrupts if no other subsystem is running PdAdapterEnablelnterrupt while setting dwEnable 0 Release the event object and clear user level events PdUctClearPrivateEvent PdClearUserEvent using CounterTimer as the subsystem name Reset the UCT to clear its configuration and stop ongoing operations PdUctReset 106 8 User Counter Timer Subsystem 107 9 Support Software PowerDAQ Example Programs A complete range of sample programs with source code is included with each PowerDAQ board as part of the PowerDAQ Software Suite CD ROM For complete details on programming the PowerDAQ board refer to the PowerDAQ Software Manual Listed below are summaries of just a few of the examples we supply Please review the installation directories for new examples or visit us online at www PowerDAQ com Visual C examples Versions supported VC 1 5 16 bit VC 5 and 6 32 bit Examples supplied e VM16 exe simple voltmeter application displaying as many as 64 channels e Stream4 exe continuous acquisition and stream to disk applicatio
108. he driver reaches the buffer s end The user app can access the buffer and process data during acquisition or wait until the buffer is full This approach is appropriate when you re not acquiring data in a continuous stream and it resembles the way a digital scope operates e InCircular Buffer mode the head and tail each wrap to the buffer start when they reach the end If the head catches up to the tail pointer the buffer is considered full and acquisition stops This mode is useful in applications that must acquire data with no sample loss Data acquisition continues until either a predefined trigger condition or the application stops the driver If the app can t keep up with the acquisition process and the buffer overflows the driver halts the acquisition and reports an error condition e Recycled mode resembles Circular Buffer mode except that when the head catches up with the tail pointer it doesn t stop but instead overwrites the oldest scans with the new incoming scans As the buffer fills up the driver is free to recycle frames automatically incrementing the buffer tail This buffer space recycling occurs irrespective of whether or not the application reads the data In this mode a buffer overflow never occurs It s best for applications that monitor acquired signals at periodic intervals The task might require that the system digitize signals at a high rate but not need to process every sample Also an application might need only the latest
109. hermistors usually have negative temperature coefficients They tend to be more accurate than thermocouples or RTDs but they have a much more limited temperature range A temperature sensor created by joining two dissimilar metals The junction produces a small voltage as a function of temperature The flow of data measured in bytes sec for a given continuous operation 163 Appendix G Glossary transducer transfer rate Trigger U UCT unipolar Z zero offset zero overhead looping zero Wait State memory Index A device that converts energy from one form to another Generally applied to devices that convert a physical phenomenon such as pressure temperature humidity or flow to an electrical signal The rate measured in bytes sec at which data is moved from a source to a destination after software initialization and setup operations the maximum rate at which the hardware can operate A signal in either hardware or software that initiates or halts a process In DAQ boards it generally refers to a signal that starts or stops an A D D A or DIO operation User counter timer A signal range that is always positive for example 0 to 10 V The difference between true zero and an indication given by a measuring instrument The ability of a high performance processor to repeat instructions without requiring time to branch to the beginning of the instructions Memory fast enough that the processor d
110. ically If you install a third party software package after installing the PowerDAQ software you must reinstall our software to include support for this new third party package As of the writing of this manual we support the following third party software Software Version Supports What s included Package multiple PowerDAQ boards LabVIEW 5 x or greater Yes Extensive VIs including click and replace low level VIs LabVIEW for Linux 6 x or greater Yes VIs that mirror standard LabVIEW support but run under Linux LabVIEW Real 6 x or greater Yes VIs that mirror standard Time LabVIEW support but run under this environment Agilent VEE 5 x or greater Yes Examples DASYLab 4 x or greater No Examples TestPoint 3 3 or greater Yes Examples LabWindows CVI 5 x or greater Yes Callable from our VC support DIADEM 6 x or greater Yes Examples MATLAB Data 6 x or greater Yes Examples Acquisition Toolbox xPC Target 2 x or greater Yes Examples Table 9 1 Third party software support 110 9 Support Software 111 Appendix A Specifications 112 Appendix A Specifications PD2 MF Multifunction Boards Model PD2 MF xx 3M 12x 2M 14H 1M 12x 500 16x Resolution 12 bits 14 bits 12 bits 16 bits Number of Channels Single Ended 16 or 64 Differential 8 or 32 Maximum Sampling Rate 3M S sec 2 2M S sec 1 25M S sec 500k S sec Onboard FIFO Size 16k
111. iming een eee e NI RE REOR EG GT REQUE ERIS 135 PDXI MES S ries Femme ere ee e ROO RR ep re ERE 135 iv Table of Contents Appendix C Accessories s ciccissicacccosseceousescounsoscosecssenvonsiondvousencetanseoserercenceeentcensl 137 Screw Terminal Panels PD2 PDXI inse eee me e eR Ree 137 Screw Terminal Panels PDL MF only 137 BNC amp Distribution Panels PD2 PDXT sees enne ene 138 Cables PD2 PDXT oieri ment oe ated aee ete bee a pee rete eerte 138 Mating cables connectors rack mounts PD2 PDXT 139 Signal Conditioning all boards 140 Appendix D PowerDAQ SDK Structure eeeeeeeeeeeeeeeeeee eere eeeeees LAL PowerDAQ Windows device drivers 142 PowerDAO Wndows DLLEs tret e e e eI eee r euch eo tts 142 PowerDAQ Language Libraries te ett ee ee RU HE a RR dee det ds 143 PowerDAQ Include Files eros rtr e Pee eed ere tetes ee ats 144 PowerDAQ Linux Support 5 cct teo RR e e HE e eee RU He eee Rene detta 146 PowerDAQ ONX SUpport nisen aree tar thee ee eo b are exeo Eo tee tt end nes 146 Appendix E Application Notes 147 1 PowerDAQ Advanced Circular Buffer ACB 147 Appendix FE Warranty EN EOL Appendix G ET e EE Index qe 104 Reader Feedback Ie eoe snainsnern ten co eso eene 109 List of Tables and Figures Table 2 1 PowerDAQ PD2 MF Series models sess 9 Table 2 2 PowerDAQ PD2 MFS Model
112. in the buffer _PdAOutGetBufState and write the new data Re enable events with PdSetUserEvents Stop waveform generation Stop asynchronous operation PdAOutAsyncStop PdAOutAsyncTerm Deinitialize the subsystem Release event object handle optional PdAOutClearPrivateEvent 90 6 Analog Output Subsystem Release the buffer _PdReleaseBuffer Clear the subsystem and set both outputs to 0V optional _PdAOutReset Method D Repetitive waveform generation Use this method to create fixed length waveforms The PowerDAQ buffering mechanism handles all data transfers to the D A FIFO After an application writes data to the buffer the board starts to output the waveform and restarts automatically when the pointer reaches the end of the buffer This method is suitable when you need a continuous repetitive waveform Initialization Reset analog output if required _PdAOutReset Acquire buffer for analog output PdAcquireBuffer set BUF BUFFERWRAPPED BUF BUFFERRECYCLED flags and fill the buffer with data Initialize asynchronous operation _PdAOutAsynclnit and set dwConfig AOB_CVSTARTO to use internal clock and calculate the divisor as described above Set up event notification _PdAOutSetPrivateEvent Start waveform generation Start asynchronous operation _PdAOutAsyncStart Wait for an event from the board or a timeout WaitF orSingleObject hEventObject
113. internal and the CV clock to continuous use AIB CLSTARTO AIB CVSTARTO AIB CVSTARTI which sets CL to 0 1 and CV to 1 1 Note On the PDL MF board you can specify only one clock at a time If you configure the CV clock as internal or external you must then set the CL clock to continuous If you set the CL clock to internal or external the board ignores the CV clock and runs the A D at its maximum speed Note The PDL MF board provides a Gated mode when you work with the external trigger line to activate the clock you have selected as active If you set the bit AIB EXTGATE by including it in the dwAInCfg configuration word then the board uses the ExtTrig terminal as a gate for the selected A D clock regardless of the clock source selected A High on the ExtTrig terminal enables conversions and a Low disables them This mode is incompatible with other trigger modes and you should clear all AIB xxTRIGxx bits when working with this mode Note also that you can implement Gated mode on any MF MFS boards using the 8254 counter timers 58 5 Analog Input Subsystem It s important to realize that you can scan channels in two basic ways either very fast by using the CL clock to control the speed at which you start a new scan of the Channel List or you can allow for a specific amount of time between adjacent samples such as to ensure that the front end amplifiers settle by using the CV clock In either case when you set a speed on one clock
114. ion 14 bits 16 bits 16 bits Number of Channels Single Ended Differential 16 or 64 8 or 32 16 8 Maximum Sampling Rate 400k S sec 333k S sec 150k S sec Onboard FIFO Size upgradeable to 16k 32k 64k 1k samples Channel Gain List 256 entries Input Ranges 0 5V 0 10V UA lt 10V software selectable Programmable Gains by channel L 1 10 100 1000 H 1 2 4 8 Drift Zero Gain 30 pVv C 30 ppm C Input Impedance 10 MQ Input Bias Current 20 nA Input Overvoltage 35V continuous A D Conversion Time 2 5 usec 2 0 usec 6 usec A D Settling Time 2 0 usec 1 2 usec 5 usec DC Accuracy Nonlinearity 0 5 LSB 1 LSB 1 LSB System Noise 0 8 LSB 1 3 LSB 1 2 LSB AC Accuracy Effective Number of Bits 13 1 14 5 14 8 Total Harmonic Distortion Nonlinearity Noise 81 dB 89 dB 91 dB Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock Aggregate Throughput 0 01 Accuracy 400k S sec 333k S sec 150k S sec External A D Sample Clock Maximum Frequency 400k S sec 333k S sec 150k S sec Minimum Pulse Width 20 ns External Digital TTL Trigger High level Input Voltage Low level Input Voltage Minimum Pulse Width 2 0V min 0 8V min 20 nsec
115. ion command all the S H amplifiers track their respective input signals and change their outputs to reflect the value of the continually varying input However when the analog front end sees a conversion command all the S Hs immediately stop tracking their input values and instead freeze and hold the last values until they are once again freed up to track the inputs While the S Hs are holding the inputs the A D converter can service them in turn through the multiplexer Thus even though the A D cannot digitize more than one signal simultaneously the use of the S Hs allows the card to achieve true simultaneous sampling regardless of the input signal s frequency Always use MFS Series boards if you require the exact difference between input levels at a specific time or if you are working with signals close to their Nyquist frequencies The MFS Series boards have a unique exact timing feature An MFS board s control logic needs 15 nsec to process an external Hold signal To compensate for this small delay the S H amps have a negative delay In other words the signal level that such an amp captures when the board logic switches it into Hold mode is the level that appeared at the input 15 nsec earlier This guarantees that the board acquires a signal level at the exact time you apply an external pulse The standard configuration on MFS Series boards is for single ended inputs with unity gain however the PD2 MFS DG differential input option adds on
116. ion and control logic An interrupt mechanism notifies the DSP of special conditions on this subsystem so the user application can take appropriate action 41 4 PowerDAQ Architecture Programming Model No matter which subsystem you choose to work with the way you initialize and set up the board Is very much the same so before digging into details of individual subsystems 1t makes sense to review these general procedures An onboard DSP controls all subsystems User applications communicate with the board via the PowerDAQ API which is integrated into the PowerDAQ dynamic link library DLL To inform an application about hardware events the driver creates kernel events Data is transferred from the board through the PCI bus and stored in the user level buffer The PowerDAQ API includes a set of information functions that allow user applications to get board specific information such as model serial number and IRQ line PowerDAQ Board Using PD2 as an example PCI Bus Interface Data Buffer PowerDAQ Driver PowerDAQ DLL Figure 4 4 Communication between a user application and a PowerDAQ multifunction board User Application 42 4 PowerDAQ Architecture Programming subsystems All PowerDAQ subsystems have two modes of operation e Polled e Event based In Polled mode the user application queries the board about the status of various subsystems as needed This method is preferred when the applicat
117. ion does not need to be notified about hardware events In Event based mode the board notifies the user application of certain predefined subsystem events using Win32 calls With this mode you can write truly asynchronous applications Opening a subsystem Before starting any board operations whatsoever you must first open the driver open the adapter another term that refers to a specific board and acquire the subsystem After completion of a specific task the user application can release the subsystem and when the application has completed its work make sure it closes the adapter and driver This manual explains the general procedures for creating a program and important API calls The following calls outline the sequence you must make when programming under Win32 in particular the calls to open close the driver and open close the adapter are specific to Windows The remaining calls are valid for any OS For details on various functions and their calling parameters see the PowerDAQ Programmer Manual The specific calls and their names might vary with other operating systems so once again you might want to refer to that manual API calls required for opening closing a subsystem e PdDriverOpen Open the driver e PdAdapterOpen Open the adapter only one process can open a given adapter at a time This function returns phAdapter a handle for the adapter and you will need this variable in many later functions e PdAcquire
118. is typically referenced to a remote source and it is separated from the PC ground thus it can float at a different level The maximum difference between common ground and PC ground should never exceed 10V You can remove the effect of this voltage offset from measurement results by subtracting the difference between AGND and COM from the measured result Because the AGND line in a pseudodifferential setup 1s not connected to the computer ground it is not subject to the associated digital noise within the PC Instrumentation Amplifier Source 1 Figure 5 1 Wiring for single ended and pseudodifferential inputs Differential A PowerDAQ card operating in differential mode digitizes across as many as 32 channels Each channel uses two lines on the data acquisition system s input amplifier Fig 5 2 you connect one lead from the signal source to the channel s High input the positive input of the amp and 49 5 Analog Input Subsystem connect the other signal lead to the channel s Low input the amp s negative input Each signal floats at its own level without any reference to ground or other inputs For example when working with a 16 channel PowerD AQ board in differential mode Ch 0 and 8 form the High and Low inputs of differential input Ch 0 next for differential input Ch 1 you use Ch 1 and 9 follow this pattern for all eight differential input pairs Follow this procedure when wiring the PDL MF board according to the pin as
119. ize and number of frames Normally four frames in a buffer are enough to achieve smooth operation They provide enough time to avoid a buffer overflow if the OS encounters a delay in responding The buffer should be big enough to accommodate from 0 33 to 1 sec of incoming data 79 5 Analog Input Subsystem How can you determine the optimal frame size for an acquisition run When selecting the frame size take the following items into account Events consume host CPU and on board DSP time so a small frame needs servicing more often and thus decreases overall system performance On the other hand larger frames decrease the event rate which isn t desirable in situations where you need faster response especially in control loop applications We recommend setting a frame size so the application receives from 4 to 10 events per second For example if the Channel List has four entries and the acquisition rate is 100k scans sec the recommended frame size is from 10 000 scans calculated as 100k scans 10 to 25 000 scans calculated as 100k scans 4 Acquisition Wait for event notification with WaitForSingleObject hEventObject Timeout This function puts the user application into Sleep mode and gives the host CPU time for other processes The user app gets activated when the board signals an event or the timeout period has expired The timeout period should be long enough to fill the host buffer with samples When this function ret
120. l layout of J2 on PD2 MF MFS Series boards seeeeeeeeeeeeeeereereeer 29 Figure 3 9b Pin assignments for J2 Connector on PD2 MF MES boards 29 Figure 3 10a Physical layout of J4 on PD2 MF MFS Series boards 30 Figure 3 10b Pin assignments for J4 Connector on PD2 MF MFS boards eeeeeeeeeeeeeeee 30 Figure 3 11a Physical layout of J6 on PD2 MF S Series boards 31 Figure 3 1 1b Pin assignments for J6 Connector on PD2 MF MFS boards sseeeeeeeeeeeeee 31 Figure 3 12a Physical layout of J1 on PDL MF board 31 Figure 3 12b Pin assignments for J1 Connector on PDL MF Series board 32 Figure 3 13 Cable connection diagram for PDXI MF S boards sss 33 Figure 3 14a Physical layout of J2 on PDXI MF MFS Series boards 33 Figure 3 14b Pin assignments of J2 Connector on PDXI MF MFS Series boards 34 Figure 3 15 Simple Test application eoo trece tete ql eel ee ei eH egent 35 Figure 4 1 PowerDAQ PD2 MF MFS Series block diagram 37 Figure 4 2 PowerDAQ PDXI MF MFS Series block diagram 38 Figure 4 3 PowerDAQ PDL MF block diagram en 39 Figure 4 4 Communication between a user application and a PowerDAQ multifunction boards ie Asawa det oan fe eot etn ted iet aa te 42 Table 5 1 PowerDAQ analog input ranges sssssseseeeeeeeeneenennnen eene nnns 45 Table 5 2 Programmable Gains
121. l that adds 2 analog excitation voltage channels PD ASTP 16SG Precision version of ASTP 16X with G 100 cutoff of 10 Hz for use with strain gages and thermocouples PD 5B CONN Connects 64 channel PowerDAQ board to four ASTPs PD2 DIO BPLANE16 16 channel backplane for solid state relay modules PD2 DIO CONN64 4 Distribution board converts 100 way connector to four 50 way IDC headers PD2 DIO CBL 100 100 way 1m cable PD2 DIO CBL 50 18 50 50 way IDC ribbon cable connects PD2 DIO CONN64 4 to PD2 DIO BPLANE16 PD 5B 04 2 channel backplane mounts 5B analog I O modules to MF S boards PD 5B 08 8 channel backplane mounts 5B analog I O modules to MF S boards PD 5B 01 16 channel backplane mounts 5B analog I O modules to MF S boards UEI supplies a wide range of analog and digital signal conditioning modules for use on these racks The list is far too extensive to publish in this manual For the latest list contact the factory or your local distributor or review the list on our web site at www ueidaq com 140 Appendix D PowerDAQ SDK Structure The installation will create the following directory structure in Program Files This assumes you selected the SDK installation default This software ships on the PowerDAQ Software Suite CD ROM that accompanies each board A i3 PowerDAQ 3 i Applications FH i73 PowerDAQ Example Browser C3 Documentation A SDK E
122. les with a PowerDAQ board they do not go directly into host memory Instead all digitized values first go into an onboard A D FIFO memory The standard size of this FIFO starts at Ik samples 4k samples for high speed 2 MHz boards but you can purchase options that upgrade the FIFO size to as many as 64k samples Keep in mind that a DAQ card driver differs from one for a printer CD ROM or other peripheral in one fundamental way realtime operation A printer can wait before it gets the next data to print and a CD ROM can pause for a short while to let other activity go on A data acq board however typically collects data continuously and can pause only as long as its onboard FIFO has sufficient room to store intermediate results If this buffer overflows incoming data is lost This combination of an onboard DSP and a data FIFO has several advantages First a PowerDAQ board can collect data at its full rated speed no matter what the host PC 1s doing The DSP controls the acquisition process and stores the data locally So even if you re running a graphics intensive application it has no negative impact on the data collection process Further virtually all of the host CPU s horsepower is available for post acquisition analysis such as running a control loop Before moving on to other issues related to acquiring digitized data it s important to understand the distinction between a scan and frame A scan is one run through of the presently confi
123. ls into a single 12 14 or 16 bit successive approximation A D The boards can be configured to work with either single ended 16 to 64 or differential 8 to 32 inputs and the selected mode must be the same for all channels This selection of input mode can lead to some confusion No matter what the underlying test system configuration all voltage measurements are made between two points and thus are inherently differential One node is at a potential as compared to the level on the other input terminal and that level can be at a ground reference or at an elevated voltage level On a PC based data acq card one line of the input amplifier is always connected to the signal of interest To what level the second referenced line on the input amp is connected determines in which of three possible input modes the amp is operating e Single ended channels refer all their inputs to a common ground that is also connected to the computer ground e Pseudodifferential channels refer all their inputs to a common ground but this ground is not connected to the computer ground 47 5 Analog Input Subsystem e Differential inputs use an independent reference for each channel and these references are not connected to the computer ground and instead are generally a return path directly to the source of the signal being digitized Each mode has its strengths and weaknesses so you should pay close attention to the connection on the input s refere
124. ltaneous sampling sss renes 52 Clocking and Triggermg eee vein e ERR ERNEUT Ie eee es 56 Clockang Triggering Examples 2 te erre pe t e RA SERA Re e tee 61 The AD Sample FIFO asc otro cete tetro tette Ar eset eei elec e Nee ee 64 Moving data into the host PC nce ERREUR IRR RSEN EMEN ee ne 64 Host based buffer usage tee re ERSTE RATE en rene ISIN IE REINES 69 D ta format ees 70 Programming Techniques ios ees 73 Method A Single scaniz finisse D ERE UREEINRN MI DERE EE 73 Method B Burst buffered acquisition short 75 Method C Continuous acquisition using the Advanced Circular Buffer ACB 79 iii Table of Contents Method D Recycled buffer mode 81 Combining Analog and Digital subsystems sese 82 Synchronous stimulus response ener ennt nene trennen ener enne nnns 82 6 Analog Output Subsystem e eeee eee e eren eee ener en esee ea sees seen sese esse sees sees OF Architecture iuit oe E eL e ap E edie Mis an HERR EE d RE Dn 84 Single value update metliod 5 iot te SAT ete TINTA TA Poi DE Sie ete Tx 84 Buffered waveform generation methods 84 Non buffered waveform generation methods 85 Channel E 86 Elektreschen dati ae Was 86 PHA ROTI Go C S 87 Programming Techniques ie Ade eed he recie iet chi was E E 87 Method A Single update eden er de Heide tele oe a er eed etes 87 Method B Single shot waveform
125. m Frequency 50 kHz 333 kHz Minimum Pulse Width 20 nsec 20 nsec External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec Analog Trigger 2 channels level and edge 121 Appendix A Specifications Analog Outputs PDL MF Number of Channels 2 Resolution 12 bits Update Rate 100k S sec each Onboard FIFO Size 2k samples Analog Output Range 10V Current Output 20 mA max Output Impedance 0 3Q typ Capacitive Drive Capability 1000 pF Nonlinearity 1 LSB Protection short circuit to analog ground Power on Voltage OV 10 mV Setting Time to 0 01 of FSR 10 psec 20V step 1 usec 100 mV step Slew Rate 30 V usec Digital I O PDL MF Input Bits 24 Output Bits 24 High level Input Voltage 2 0V min Low level Input Voltage 0 8V max High level Input Current 20 pA Low level Input Current 20 pA Output Driver High Voltage 2 5V min 3 0V typ OH 32 mA Output Driver Low Voltage 0 55V max IOL 64 mA Current Sink 32 64 mA max lines 8 16 24 24 mA max lines 0 7 250 mA per port Counter Timer PDL MF Number of Channels 3 Resolution 24 bits 122 Maximum Frequency 16 5M S sec for external clock and 33M S sec for internal DSP clock Minimum Frequency 0 00002 Hz for internal clock no low limits for external clock
126. n Visual BASIC examples Versions supported VB 3 16 bit VB 5 and 6 32 bit Examples supplied e The SimpleTest utility SimpleTest vbp which allows the simultaneous operation if desired of all subsystems Analog Input Analog Output Digital Input Digital Output and Counter Timer operation e Additional examples are located on the PowerDAQ Software Suite CD ROM in the VBExecutables directory After running the installation look in the PowerDAQ SDK Examples VisualBasic VB5 OR VB6 Example Name directory Delphi examples Versions supported Delphi 3 and 4 32 bit 108 9 Support Software Examples supplied include the following e The SimpleTest utility SimpleTest dpr which allows the simultaneous operation if desired of all subsystems Analog Input Analog Output Digital Input Digital Output and Counter Timer operation Borland C Builder examples Versions supported Inprise Borland 3 5 Examples supplied e Stream4 exe continuous acquisition and stream to disk application The files included for the above programming languages may have the same file name This means they can be used with either language 109 9 Support Software Third Party Software Support The PowerDAQ CD contains drivers for most popular third party software packages The installation procedure automatically detects 1f you have installed any of the third party packages and will install the drivers and examples automat
127. n To determine which line has caused an interrupt the user program must read the digital input status bits in the latch register Programming Techniques The digital input output subsystem can be used in two ways and recall that this subsystem has no clocked operations available Method A Polled I O This method works by using software to poll 16 digital inputs and 16 digital outputs Examples in the SDK that fall into the category of Method A are e SimpleTest dpr Initialization Reset the digital subsystem PaDOutReset sets the output lines to Zero PaDInReset clears the latch and the configuration register 97 7 Digital I O Subsystem Set up the digital input configuration Set up edge sensitivity configuration with _PdDInSetCfg Specify an input line and an edge to be detected using a configuration word as described earlier in this section Read the status of the digital input latch with _PdDInGetStatus This function returns the current state of the digital input lines in one byte and the status of the digital input latch register in a second byte If the specified edge was detected the latch contains a One in the appropriate bit Clear the status of the digital input latch with _PdDInClearData This function clears the latch register and re enables edge detection on the line that previously caused an event Input output Read digital inputs _PdDInRead Write digital outpu
128. nal This column tells you exactly how much time you can expect to wait until the next channel is digitized We are working constantly to improve these specifications and so they are subject to change Please check with the factory for the latest values 132 Appendix B PowerDAQ A D Timing PD2 MF Series Timing Board Model Resolution Speed Fast Acq Slow Acq Delay Gain Delay using Slow Bit PD2 MF xx 3M 12L 12 3 MHz High 283 nsec 800 usec PD2 MF xx 3M 12H 12 3 MHz Low 283 nsec 800 usec PD2 MF xx 2M 14H 14 2 2 MHz Low 450 nsec 3 0 usec PD2 MF xx 1M 12L 12 1 25 MHz High 800 nsec 20 0 usec PD2 MF xx 1M 12H 12 1 25 MHz Low 800 nsec 5 0 usec PD2 MF xx 500 16L 16 500 kHz High 2 0 usec 20 usec PD2 MF xx 500 16H 16 500 kHz Low 2 0 usec 10 usec PD2 MF xx 400 14L 14 400 kHz High 2 5 usec 25 0 usec PD2 MF xx 400 14H 14 400 kHz Low 2 5 usec 10 0 usec PD2 MF xx 333 16L 16 333 kHz High 3 0 usec 20 0 usec PD2 MF xx 333 16H 16 333 kHz Low 3 0 usec 10 0 usec PD2 MF 16 150 16L 16 150 kHz High 6 usec 20 usec PD2 MF 16 150 16H 16 150 kHz Low 6 usec 10 usec PD2 MES Series Timing Board Model Resolution Fast Acq Slow Acq Delay SSH Acq SSH Hold Speed Delay using Slow Bits Delay Delay IPD2 MFS x 2M 14 14 2 2 MHz 450 nsec 2 0 usec 700 nsec 500 nsec PD2 MFS x 1M 12 12 1 25 MHz 800 nsec 2 0 usec 700 nsec 500 nse
129. nce terminal No matter whether you choose single ended pseudodifferential or differential mode be sure to short unused channels to ground using a 1 KO to 10 kQ resistor Signal Source Type Floating Signal Source Not connected to ground Grounded Signal Source Examples Thermocouples Examples Input e Signal Conditioning e Plug in instruments with configuration with Isolated Outputs Non isolated Inputs e Battery Devices PD STP 96 PD STP 96 Differential PD STP 96 PD STP 96 Single Ended Ground Referenced Table 5 3c Analog Input Configurations 48 5 Analog Input Subsystem Single ended A PowerDAQ card operating in single ended mode Fig 5 1 digitizes across as many as 64 channels For single ended inputs you connect one wire from each signal source to the High input of the data acq system s input amplifier and all signals share a common return path connected to analog ground AGND You should connect this common return path to both a ground near the signal source and also to the ground on the PC which in this way gets set at the same level as the signal ground Pseudodifferential The PDL MF card allows operation in pseudodifferential mode Fig 5 1 For pseudodifferential inputs you connect one wire from each signal source to the High input of the data acq system s input amplifier and all signals again share a common return path to AGND However this ground signal
130. ncrease the settling time between samples slow down the board by decreasing its digitization rate 53 5 Analog Input Subsystem Next t is the minimal time between scans of the Channel List it depends on t1 and the number of entries in the Channel List The value of 1 ts is the maximum scan rate in Hz If the board is set up such that the CL Clock comes before the board is ready to accept a new scan the board ignores the clock and sets an Error bit When driven with the internal clock the preferred configuration for MF Series boards is CL continuous and CV internal For MFS Series boards the preferred configuration is the reverse specifically CL internal and CV continuous see following section on clocking The effective per channel sampling rate also depends on the number of channels in the Channel List In this case a PowerDAQ board acquires data across all channels sequentially at the selected speed which need not be the peak speed and this rate is referred to as the aggregate rate When the Channel List contains two channels the per channel rate is one half of the aggregate rate For multiple channels you can thus calculate the maximum per channel rate as Per channel rate Aggregate rate Number of channels Simultaneous sampling In contrast our MFS Series cards Fig 5 4 achieve true simultaneous sampling To do so they supply a sample hold amplifier S H at each signal input When waiting for a convers
131. ntion it sets the appropriate event Subsystem threads wake up on WaitForSingleObject Win32 API calls and process events as described above To release event objects use the appropriate PdxxxClearPrivateEvent call Examples in the SDK that fall into the category of Method G are e SimpleTest dpr Synchronous stimulus response Some applications require that a test setup apply an analog stimulus to an experimental system and then read the response read To address this task use a subset of Method A Set the analog output to generate its next datapoint on a pulse connected to that output s external trigger line Apply that same pulse to one of the UCTs user counter timers and have it start counting down from a predetermined value Upon reaching the terminal value it generates a pulse which you connect to the external clock CL Clock line on the analog input subsystem to start a scan This setup provides a user defined delay from the analog output to the time you read the response with an analog input scan 82 5 Analog Input Subsystem 83 6 Analog Output Subsystem Architecture The analog output subsystem on every PowerDAQ multifunction board PD2 PDL or PXI is the same it consists of two 12 bit D A converters and supports several operating methods one single value update method and several waveform generation or streaming methods The following methods are available Single value update e Method A
132. odel you must attach a second cable to a header on the board that cable requires a second empty chassis slot as detailed in the following section It is also recommended that you use this second cable for external clocking and triggering signals It is advisable to plug in all headers and closely examine the board in relationship to free PCI slots before actually inserting the board and going any further NOR 3 Inspect the board and ensure that you have inserted it properly into the slot Fasten the board s mounting bracket to your PC s back panel with the screw that held the slot cover Replace the PC s cover and turn on the power The PowerDAQ PCI interface must be set to 32 bit 5V power and signaling the default setting for most PCs To limit noise interference install the board as far as possible from other devices and hardware 17 3 Installation and Configuration Confirming the installation Once you have installed the PowerDAQ board and software on your PC you should confirm the installation e Select Programs PowerDAQ gt Control Panel from the Start menu see Fig 3 2 If the Control Panel applet is displayed and correctly identifies your PowerDAQ board the installation is correct PowerDAGQ Control Panel x Boards Installed ce RAR ET Status READY Ie Serial Number 0017036 San ADC FIFO Size 1 kS Manufacture Date 01 SEP 2001 Calibration Date 25 SEP 2001 Logic Revision 00831 Base addr
133. oes not have to wait during any reads and writes to the memory 5 56301 xa cett 5B modules 8 RE 164 A Rite 7 105 A D Arts 140 peak rates sante ml successive approximation 45 AJD FEIEO EE 40 64 ACB see Advanced Circular Buffer It 41 103 CC SSOTIES einen Anne 137 Active screw terminal panel 140 Adapter itte iUe IE 43 Advanced Circular Buffer64 69 79 90 147 circular buffer mode 70 Calibration procedures 36 recycled mode 70 CE Mark Certification s seeseeeeseeeeesee 151 single buffer mode 70 Channel List 45 46 Agilent VEE support 111 Channel List clock see CL clock Analog output Channel List FIFO sess 39 1 shot waveform esses 86 89 Circular Buffer mode 70 asynchronous ssssesesseeseeeessrsresreserseesee 89 EB OO 22 57 autoregeneration sese 86 93 Clock backward compatibility 94 analog output 87 Channel Eistz nex 87 GE clocka nes 22 31 57 clocking scsi 87 configuration bits 58 configuration bits 94 continuous seen e 58 continuous waveform 86 90 Melek o nere 22 31 57 data conversion eeeeee 87 EE GE 58 event based waveform 86 94 external ze nere hes 57 events ine emper oe mess 86 internal his oO HH e 57 repetitive
134. of one half the A D FIFO or 4k samples We have found that 99 of all PCI motherboards handle this mode well However a few systems with PCI bridges can ignore the situation that data is not yet available and nonetheless complete the PCI Read cycle normally but with zero data In those systems you should revert to Normal mode 3 Bus Mastering In many cases programmed I O Method 2 can empty the A D FIFO in sufficient time so there is always room in the FIFO for data coming from the next scan However if you collect data at a 65 5 Analog Input Subsystem very high rate 1 MHz or greater the potential exists for a buffer overrun where incoming data wants to overwrite the half of the FIFO that hasn t yet been transferred to host memory Such conditions will result in an error message If a PowerDAQ board is configured such that the amount of incoming data could eventually exceed the size of the FIFO buffer you should set this mode active whereby the DSP uses bus mastering to handle buffer maintenance automatically Specifically the DSP detects when the FIFO becomes half full and at that point initiates a data transfer from the FIFO into host memory This mode thus unloads the host processor from the task of transferring samples into host memory But because the PowerDAQ board takes control of the system bus it might interrupt other host processes that require bus access Thus you should set up the system so it doesn t request a DMA
135. on the part of the user The boards store calibration values for each range and each gain in EEPROM When you initially load the PowerDAQ board driver and configure the analog input subsystem that process loads the calibration values from EEPROM However to ensure peak performance from your PowerDAQ hardware we suggest that a PowerDAQ board be recalibrated every 12 months 36 4 PowerDAQ Architecture Functional Overview The PowerDAQ MF MFS Series features extensive input modes clocking and capabilities It also provides simultaneous subsystem operation External Analog UO Connector y Aln Calibration DACs Aln Power Conditioner Upgradable k Sample ADC AFO Ext Aln Conv Gock Ext Aln Scan Glock Ext Trigger Aln Clock Out Digital Input Buffer Latch Interrupt Digital Output Driver Aln Clocking amp Triggering Motorola 66MHz DSP 56301 AOut Calibration Voltage DACs Reference Bus Master PCI Interface Configuration amp Calibration lt 32 Bit PO Bus gt Figure 4 1 PowerDAQ PD2 MF MFS Series block diagram 6 Internal Digital I O Connectors DR S 3 E E E D D o z triggering 37 4 PowerDAQ Architecture 38 External A ndogl O Comector 6 or64 Channel An zo Multiplexer Ext Aln Conv Clock
136. onent instead is an integer and represents the Appendix G Glossary frame function G gain gain accuracy GUI H handler hardware IMD INL input bias current input impedance input offset current instrumentation amplifier number of places any binary number must be shifted left or right in order to yield the desired value A user defined number of scans and these datapoints reside in a predefined portion of a buffer in host memory This host memory buffer is also known as the Advanced Circular Buffer ACB A set of software instructions executed by a single line of code that may have input and or output parameters and returns a value when executed The factor by which a signal is amplified sometimes expressed in dB A measure of the deviation of an amplifier s gain from the ideal gain Graphical User Interface an intuitive means of communicating information to and from a computer program by means of graphical screen displays GUIs can resemble the front panels of instruments or other objects associated with a computer program A device driver installed as part of the computer s OS The physical components of a computer system such as the circuit boards plug in boards chassis enclosures peripherals cables and so on Intermodulation Distortion the ratio in dB of the total RMS signal level of harmonic sum and difference distortion products to the overall RMS signal level The test sign
137. ons on this subsystem so the user application can take appropriate action The Analog Output subsystem includes A DSP based FIFO that holds as many as 2k samples of digitized waveform values to feed to the output D A A 12 bit D A that converts digitized waveform values into analog output voltages A calibration D A that provides voltages to adjust offset and gain on the analog output to ensure accurate performance Timing triggering and clocking controls that allow you to select the analog output rate and clock source An interrupt mechanism that notifies the DSP of special conditions on this subsystem so the user application can take appropriate action The Digital Input Output subsystem includes A 16 bit register to read logic levels on digital input lines 24 bit register on PDL MF An 8 bit Schmidt trigger to catch logic level changes on digital input lines not present on PDL MF 4 PowerDAQ Architecture A 16 bit register to hold logic levels on digital output lines once the program has written data to the outputs 24 bit register on PDL MF An interrupt mechanism notifies the DSP of special conditions on this subsystem so the user application can take appropriate action The User Counter Timer subsystem includes Three 16 bit Intel 82C54 counter timers fully accessible by the user the counter timers on the PDL MF are shared with the 24 bit DSP 56301 Clock source selection and control logic Gate source select
138. ontrol Instead of setting up timing loops in software the programmer configures the chip to meet system requirements and programs one of the counters for the desired delay After the desired delay the 82C54 interrupts the CPU Software overhead 1s minimal and variable length delays can easily be accommodated Some other counter timer functions you can easily implement with the 82C54 are e Event counter Digital one shot Programmable rate generator Squarewave generator Binary rate multiplier Complex waveform generator Complex motor controller The UCT is extremely useful in combination with the external clock and trigger lines Using the UCT you can create very sophisticated acquisition setups 102 8 User Counter Timer Subsystem At a high level the programmer need only be concerned with selecting the input clock source and then selecting the gate signal setting the Gate to Logic 1 enables counting setting it to Logic 0 disables counting it has no effect on the counter timer output lines The UCT generates an output signal depending on its operating mode and the input conditions In addition a counter timer s outputs can also generate an interrupt to the host PC when a change in state occurs You can feed a clock input from one of the following sources e Software command e MHz internal timebase e External clock input line 10 MHz max e Output from UCTO available as input for UCTI and 2 It is possible to control the
139. ot require any user software programming to enable their operation All PDXI MFS Series models come standard only with G 1 for other gains you can purchase the DG option outlined in Table 2 5 12 2 PowerDAQ MF MFS Series Features Overview PowerDAQ PD2 PDXI MFS Series differential upgrade with gains DG option The PD2 PDXI MFS simultaneous sampling Series can be upgraded from single ended to differential inputs with gains for each channel One programmable gain amplifier PGA per channel is installed on the board Upgrade Part Number Additional features added PD2 MFS 4 DG4 Upgrade any PD2 MFS board from 4 SE to 4 DI and add Gains PD2 MFS 8 DG8 DES PD2 MFS board from 8 SE to 8 DI and add Gains PDXI MFS 4 DG4 KSE PDXI MFS board from 4 SE to 4 DI and add Gains 4 PDXI MFS 8 DG8 KC PDXI MFS board from 8 SE to 8 DI and add Gain 1 2 5 10 Table 2 5 MES Differential Upgrade Options PowerDAQ MFS boards with the DGx option installed have the same number of single ended or differential channels PowerDAQ MF MFS FIFO upgrade options You can upgrade the analog input FIFOs on PD2 PDXI PowerDAQ multifunction boards Below is a list of currently available upgrade options Upgrade part number Additional features added PD 16KFIFO Upgrade onboard analog input FIFO buffer to 16k samples PD 32KFIFO Upgrade onboard analog input FIFO buffer to 32k samples PD 64KFIFO Upgrade onboa
140. pgradeable to 16k 32k 64k Input Ranges 0 5V 0 10V 5V 10V software selectable Channel Gain List 256 entries Programmable Gains by channel 1 2 5 10 Drift Zero 30 uV C Gain 30 ppm C Input Impedance 1MQ Input Bias Current 100 pA Input Overvoltage 18V SE 40V DI A D Conversion Time 2 psec 2 0 usec 3 usec SSH Amp Settling Time 1 2 usec 1 2 usec 1 2 usec A D Settling Time 1 5 usec 1 2 usec 2 7 usec DC Accuracy Nonlinearity 1 LSB no missing codes AC Accuracy Effective Number of Bits 13 8 12 7 13 8 Channel Crosstalk 80 dB 1k S sec Clocking and Trigger Input Maximum A D Pacer Clock 500k S sec 300k S sec External A D Sample Clock Maximum Frequency 500k S sec 300k S sec Minimum Pulse Width 20 nsec External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec 128 Appendix A Specifications Analog Outputs all PDXI MFS models Number of Channels 2 Resolution 12 bits Update Rate 200k S sec each Onboard FIFO Size 2k samples on DSP Analog Output Range 10V Error Gain 1 LSB Zero Calibrated to 0 Current Output 20 mA max Output Impedance 0 3W typ Capacitive Drive Capability 1000 pF Nonlinearity 1 LSB Protection Short circuit to analog ground Power on Voltage OV 10 mV Setting Time to 0 01 of FSR 10 usec 20V step 1 usec 100 mV step Slew
141. pment tools pwrdaq32 lib pd32bb lib pd16bb lib pwrdaq16 lib MSVC MSVS v 5 x 6 x Borland C Builder v 3 0 4 0 16 bit Borland compilers 16 bit MSVC 1 5x 143 Appendix D PowerDAQ SDK Structure PowerDAQ Include Files include aliases bas DAQDefs bas DAQDefs pas pdApi bas pd dsp ct h pd dsp ct pas pd dsp es h pd dsp es pas pd32hdr h pd32hdr pas pdfw bitsdef bas pdfw bitsdef pas pdfw defh pdfw defpas pdfw defbas pd hcaps h pd hcaps pas pdpcidef h pdpcidef pas pwrdaq h pwrdaq pas pwrdaq bas pwrdaq32 h pwrdaq32 hpp pwrdaq32 pas pwrdaq32 bas pxi bas pxi h sigproc h sigproc hpp 144 auxiliary functions to access PowerDAQ structures from within VB DAQ constant and variable definitions file for Visual Basic DAQ constant and variable definitions file for Delphi module used in SimpleTest VB example DSP counter timer register definitions file for C C DSP counter timer register definitions file for Delphi ESSI port register definitions file for C C ESSI port register definitions file for Delphi PowerDAQ DLL driver interface function definitions file for C C PowerDAQ DLL driver interface function definitions file for Delphi PowerDAQ Firmware Command definitions file for Visual Basic PowerDAQ Firmware Command definitions file for Delphi firmware constant definition file for C C firmware constant definition file for Borland Delphi firmware constant definition file for Visual B
142. pplications The inherent uncertainty in digitizing an analog value due to the finite resolution of the conversion process A system in which the desired action takes place immediately when all input conditions are fulfilled it never has to wait for other processes to complete before it can start In DAQ terms it generally refers to the processing of data as it is acquired instead of being accumulated and getting processed at a later time A measure in LSB of the accuracy of an A D It includes all nonlinearity and quantization errors It does not include offset and gain errors of the circuitry feeding the ADC The smallest signal increment that a measurement system can detect Resolution can be expressed in bits in proportions or in percent of full scale For example a system has a resolution equal to 12 bits one part in 4 096 0 0244 of full scale A technique whereby a device is signaled not to use one of its resources often local memory while that resource is being used by another device generally the system bus A flat cable in which conductors are placed side by side Root mean square computed by squaring the instantaneous voltage integrating over the desired time and taking the square root Resistance temperature detectors operate based on the principle that electrical resistance varies with temperature They generally use pure metal elements platinum being the most widely specified RTD element type although ni
143. ppresses Electrically Erasable Programmable Read Only Memory a nonvolatile memory device you can repeatedly program for storage erase and reprogram A device that converts linear or rotary displacement into digital or pulse signals The most popular type of encoder is the optical encoder Erasable Programmable Read Only Memory A nonvolatile memory device that can be erased usually by ultraviolet light exposure and reprogrammed A signal or interrupt generated by a device to notify another device of an asynchronous event The contents of events are device dependent A board operating mode whereby it notifies the user application of certain predefined subsystem events using Win32 calls It allows you to write asynchronous applications A voltage pulse from an external source that triggers an event such as an A D conversion First In First Out usually used in reference to a memory buffer where the first data stored is the first sent out A format for processing or storing numbers as digital integers In fixed point arithmetic all numbers are represented by integers fractions usually restricted between 1 0 or a combination of both integers and fractions Thus integer mathematics can be implemented on all general purpose processors Representing data as a combination of a mantissa and an exponent The mantissa is usually described by a signed fractional value that has a magnitude gt 1 0 and restricted to lt 2 0 The exp
144. pter 7 Digital I O Subsystem This chapter contains two major sections the first describes the hardware and its features the second introduces you into techniques for programming this subsystem Chapter 8 User Counter Timer Subsystem This chapter contains two major sections the first describes the hardware and its features the second introduces you into techniques for programming this subsystem Chapter 9 Support Software 1 Introduction This chapter outlines the various example programs supplied with the PowerDAQ Software Suite CD ROM It also describes the third party software we support with PowerDAQ hardware Appendix A Specifications This appendix lists the hardware specifications of the PowerDAQ product series Appendix B PowerDAQ A D Timing This appendix gives tables that help you determine the fastest acquisition times when using various options such as Slow Bits Appendix C Accessories This appendix provides a list of available PowerDAQ accessories Appendix D PowerDAQ SDK Structure This appendix shows the directories and files that are created when you install the PowerDAQ Software Developers Kit Appendix E Application Notes This appendix provides application notes to enhance your understanding of PowerDAQ products Appendix F Warranty This appendix contains a detailed explanation of PowerDAQ warranty Appendix G Glossary This is an alphabetical listing of the terms used in this manual along with thei
145. pts can be applied to output signal generation e Asynchronous operation e Nondeterministic processor time slots per thread e Dynamic processor loading e Nondeterministic user operation The ACB requires that the DAQ interface library allocate a large circular buffer in the application s memory space The buffer size must be no larger than the available physical memory with sufficient physical memory left over for most of the executable portion of the OS and active applications to reside in memory This prevents code or data from frequently being swapped to disk Consequently if continuous gap free acquisition 1s to be performed the buffer should be large enough to hold all the acquired data for the maximum time period expected between application execution latency and the time required for the application to process all data in a full buffer This also implies that the application must be able to process the data at a rate faster than the rate of acquisition Once acquisition is started the DAQ board driver transfer and store data into the buffer at one rate and the application generally reads the data from the buffer at another rate Both operations occur asynchronously of each other 147 Appendix E Application Notes Driver Asserts Frame Done Events When Data Written Advanced Circular Passes Frame Boundry Buffer Write New Data At Buffer Head l Buffer Head Board Driver REESE Application Reads Data From
146. r J1 96 pin high density Fujitsu connector male Fujitsu PNZFCN 245P096 G U Connector J2 80 pin header connector male Adam Tech PN HBMR A 80 VSG 130 Appendix A Specifications 131 Appendix B PowerDAQ A D Timing The following tables are intended to help you determine the fastest acquisition rates for various models when working with various gains In the Board Model column note that an x is a placeholder for various models and represents the number of channels on the board In the Resolution Speed Gain column Low refers to a board with modest gain capabilities either 1 2 4 8 or 1 2 5 10 and are intended to work with high level signals and hence the H suffix on the board model number Conversely High in the second column refers to a board with high gain capabilities 1 10 100 1000 and are intended to work with low level signals and hence the L suffix on the board model number The column Fast Acq Delay gives the minimum time between conversions when the board is digitizing at its maximum rate The column Slow Acq Delay using Slow Bit gives the minimum time between conversions when you activate the Slow Bit for a channel Recall that a Slow Bit setting instructs the board to wait an extra amount of time before taking the next sample thereby giving the amplifier and other front end elements time to settle to the next value before actually digitizing the sig
147. r analog I O signals J1 A 96 contact pinless male board edge connector manufactured by Fujitsu PN FCN 245P096 G U see details for this connector on the datasheet for the corresponding PowerDAQ boards on the UEI website The pin assignments on this connector differ depending on whether you configure the analog inputs as single ended or differential and whether you are dealing with MF or MFS Series boards e On card connector for digital I O and counter timer signals as well as external clocks and triggering lines J2 A 36 pin flat cable to pc board connector male IDC header manufactured by Thomas and Betts PN 609 3627 see details for this connector on the datasheet for the corresponding PowerDAQ boards on the UEI website e On card connector for additional digital I O signals J4 A 36 pin flat cable to pc board connector male IDC header manufactured by Thomas and Betts PN 609 3627 see details for this connector on the datasheet for the corresponding PowerDAQ boards on the UEI website e On card connector for intraboard synchronization clock signals J6 An 8 pin flat cable to pc board connector male IDC header manufactured by Methode Adam Tech PN PH2 08 TA SMT see details for this connector on the datasheet for the corresponding PowerDAQ boards on the UEI website 24 3 Installation and Configuration J2 PD CBL 37 DIO cable set PD STP 9616 Figure 3 7 Cable connection diagram for PowerDAQ MF S
148. r definitions Index This is an alphabetical listing of the topics covered in this manual 1 Introduction Other PowerDAQ Documentation The PowerDAQ PD2 PDXI PDL MF Manual is one part of the documentation available for the PowerDAQ system There are several other manuals you might want to read before programming your application They are available either on the PowerDAQ Software Suite CD or can be downloaded from the UEI web site Software PowerDAQ Programmer Manual PowerDAQ for LabVIEW User Manual Hardware PowerDAQ ASTP User Manual PowerDAQ Thermocouple Rack User Manual Feedback We are interested in any feedback you might have concerning our products and manuals A Reader Evaluation form is available on the last page of the manual 1 Introduction 2 PowerDAQ MF MFS Series Features Overview This chapter provides an overview of the key features of the PowerDAQ Series and detailed information on the various PowerDAQ models currently available It also lists what you need to get started Overview Thank you for purchasing a PowerDAQ board These advanced multifunction boards all feature an onboard DSP that allows simultaneous operation of all I O subsystems without host intervention In addition the DSP runs a firmware based command interpreter that makes it easy and convenient to program these cards from virtually any programming language using the same API Features Key features of PowerDAQ boa
149. r should contain at least two frames so you can empty one while the A D fills the other The PowerDAQ API allocates buffers for you PdAcquireBuffer Register the buffer with the AnalogIn subsystem Use dwMode with BUF BUFFERWRAPPED and BUF BUFFERRECYCLED for single run operation whereby acquisition stops when the buffer is filled PdAcquireBuffer Set up the analog input configuration and events about which you want to be notified The analog input configuration bits are defined in the file pdfw def h Here are the recommended configurations for Method B e For the internal software clock dwAlnCfg AIB CVSTARTO AIR CVSTARTI AIR CLSTARTO e foran external clock dwCfg AIB CVSTARTO AIB CVSTARTI AIR CLSTARTI Add the AIB_INTCLSBASE constant to select the 33 MHz base frequency instead of the default of 11 MHz The application needs to know what s going on in the buffer so set up the board to fire events on certain conditions To do so use the function PdSetUserEvents Analog input event bits are defined in the file pwrdaq h The recommended event notification method is dwEvents eFrameDone eBufferDone eBufferError eStopped Your application 1s notified when at least one frame is complete Upon notification the buffer in 76 5 Analog Input Subsystem host memory is filled with data or you will receive a buffer error The most common reason for buffer errors is heavy loading from other appli
150. rDAQ structures from within VB v 3 0 boards capabilities definition file for 16 bit C 145 Appendix D PowerDAQ SDK Structure PowerDAQ Linux support The PowerDAQ API for Linux which also supports two variations of realtime Linux the kernels from RTAI and FSMLabs is very similar to the Windows API Kernel driver lib modules lt kernel_version gt misc pwrdaq o Shared library usr local lib libpowerdaq32 so 1 0 Header files win sdk types h datatype definitions needed by the files above pdfw defh firmware constant definition file for C C powerdaq h driver constants and definitions file for C C powerdaq32 h API function prototypes and structures file for C C PowerDAQ QNX Support QNX driver usr bin dev pwrdaq Shared library usr lib libpwrdaq so usr lib libpowerdaq32 so Header files pdl headers h header files specific to QNX6 and QNX4 powerdaq h driver constants and definitions file for C C powerdaq32 h API function prototypes and structures file for C C pdfw defh firmware constant definition file for C C win2qnx h DDK types conversion into QNX types 146 Appendix E Application Notes 1 PowerDAQ Advanced Circular Buffer ACB The Advanced Circular Buffer ACB solves many of the problems associated with high throughput data acquisition on a multithreaded multitasking operating system For simplicity data acquisition as an input process is discussed here However the same conce
151. rd analog input FIFO buffer to 64k samples Table 2 6 PD2 PDXI FIFO upgrade option 13 2 PowerDAQ MF MFS Series Features Overview PowerDAQ PDL MF Lab Board This budget priced Lab Series board features the following PDL MF PDL MF 50 50k samples sec 16 bit A D 16 SE 16 PDI 8 DI inputs PDL MF 333 333k samples sec 16 bit A D 16 SE 16 PDI 8 DI inputs Table 2 7 PDL MF board specifications The PDL MF board has the following additional features 14 e Analog Outputs Two 12 bit 100 kHz D As e Digital Inputs 24 lines e Digital Outputs 24 lines e Counter Timers Three 24 bit counters run at 16 5 MHz from external clock or 33 MHz from internal clock 3 Installation and Configuration Before you begin Before installing your PowerDAQ board be sure to read and understand the following information System requirements To install and run a PowerDAQ board you need the following A PCI bus system a PXI bus system or a CompactPCI bus system with a free slot a Pentium class processor and a BIOS compliant with PCI Local Bus Specification Rev 2 1 or greater Windows 95 98 NT 4 0 2000 XP Linux Realtime Linux or QNX Packing list In your PowerDAQ package you should have received the following a PowerDAQ board a calibration certificate this User Manual a CD containing the PowerDAQ Software Suite including the full Software Development Kit SDK and do
152. rds include 24 bit Motorola 56301 digital signal processor PCI bus host interface PCI 2 1 compliant Custom designed programmable gain amplifier Analog inputs from 16 to 64 channels 12 14 or 16 bit resolution A D FIFO buffer size varies with board and options Analog outputs 2 channels 12 bit resolution 2k sample DSP based FIFO Digital inputs 16 or 24 points Digital outputs 16 or 24 points Three user counter timers 8254 based each with its own Clock In Gate controls the PDL MF uses the three 24 bit counters on the DSP Auto calibration Extensive triggering and clocking of analog inputs Extensive triggering and clocking of analog outputs Simultaneous operation of all subsystems Analog In Analog Out Digital In Digital Out and Counter Timer For the full list of specifications see Appendix A Specifications 2 PowerDAQ MF MFS Series Features Overview PowerDAQ Models PowerDAQ model numbers are based on the following conventions Family Type of Board Channels Speed Resolution Gain Family e PD2 PowerDAQ PCI bus boards e PDXI PowerDAQ PXI CompactPCI boards The types of boards currently available include the following e MF Multifunction MES Multifunction with simultaneous sampling AO Analog Output details supplied in separate PD2 AO manual DIO Digital Input Output details supplied in separate PD2 DIO manual In the gain position you sometimes find one of these two types
153. rds that operate at megahertz speeds and collecting samples as quickly as possible the delay between samples ie the time between to t t2 and so on can be extremely short If the input signal s frequency is relatively low 5 10 times lower than the acquisition rate the difference in the acquired signal level from one sample to the next is minimal For many applications especially where the signals you are measuring change slowly this interchannel delay is so small that you can consider the samples to be virtually simultaneous This is also referred to as pseudosimultaneous operation If you are interested in phase differences between channels an MFS board is more suitable for such an application 52 5 Analog Input Subsystem Channel and gain control to range control calibration circuitry and ADC SE DI PDI PDL MF only switch control signal Analog Input N Figure 5 3a Analog front end of a PowerDAQ MF Series board In Fig 5 3b CL refers to the CL Clock also known as the Channel List clock or the Scan Clock CV refers to the CV Clock also known as the Conversion Clock EH Moment of Digitization Signal level at the moment of digitization Figure 5 3b Acquisition sequence for multiplexed inputs on MF Series and PDL boards Note that t shows the time between individual samples on the A D the time between CV clocks is limited by the board s maximum digitization rate If you need to i
154. red in a Channel List With this mechanism you can select the order in which the channels are read as well as set different gains on a per channel basis Input Ranges The majority of PowerDAQ boards feature four possible input ranges which are applied globally across all input channels and are applied to all signals You select the input mode SE DI and range from Table 5 1 with the PdAInSetCfg command Unipolar Bipolar 0 10V 10V 0 5V t5V Table 5 1 PowerDAQ analog input ranges The only exception to this table is the PDL MF which does not offer the 0 5V range 45 5 Analog Input Subsystem Gain Settings You can set a gain for each channel on an MF MFS Series board prior to acquisition and you do so by setting up a Channel List as described in the next section There are three gain ranges In Table 5 2 below the L or H appears at the end of the model number as appropriate such as PD2 MF 64 1M 12L and applies to the MF Series boards only An L indicates that a board is appropriate for working with low level signals that need a large gain An H indicates that a board is appropriate for high level signals that need less gain The PDL MF boards and the standard MFS Series are available only with one set of gains MF Series L Suffix MF Series H Suffix Preselected gains on PDL MF or options for MFS Series cards G 1 10 100 1000 G 1 2 4 8 G 1 2 5 10
155. retriggerable waveform generation Setthe timebase PdAOutSetCvCIk using the same calculations to set up the timebase as described in the analog input subsystem Write data to the D A FIFO with PdAOutPutBlock Start waveform generation _PdAOutEnableConv using 1 as the value for dwEnable _PdAOutSwStartTrig Stop waveform generation Reset the analog output subsystem optional _PDAOutReset The board also stops waveform generation when it reaches the end of the buffer Method F Event based waveforms using PCI interrupts There are several ways to generate long continuously changing waveforms The event based waveform technique empties the board s onboard FIFO memory into the analog output subsystem When the FIFO is less than half full the board sends an interrupt to the host to request additional data You can process analog output events in a separate event handler or in the common event handler for all subsystems Please note that Method C has replaced Method F which we include for backward compatibility Examples in the SDK that fall into the category of Method F are e AOEvents c e AEOutBlk vbp 93 6 Analog Output Subsystem Initialization Reset the analog output _PdAOutReset This function resets both analog outputs to OV and you must reset all operating parameters before running an analog output Set the analog output configuration with _PdAOutSetCfg and set dwConfig
156. riggers counting When the initial count has expired the output line goes Low for one clock pulse and then returns to a High state A special frequency measurement mode is implemented on PD2 PDXI boards Using this mode you can measure an external frequency you connect the signal to the counter s input terminal and measure the number of counts up to 65 535 that arrive in a l sec interval see the UCTMeasFrequency example program It s not necessary to implement an event handler and enable interrupts for most UCT applications Set one up only if the application must be informed on specific countdown conditions 103 8 User Counter Timer Subsystem You can use UCT to stop an analog acquisition run after acquiring N scans To do so program the device to count the N scans and also connect its output to the analog input s external trigger Then set up the A D to stop on the external trigger s falling edge of the external trigger PDL MF X The PDL MF also supplies three user counter timers but they are implemented with 24 bit registers on the 56301 DSP They are independent of each other and can generate interrupts The maximum clock frequency is 16 5 MHz for an external clock and 33 MHz for an internal clock Please refer to Motorola DSP56301 user manual for details This UCT functions in the following modes e timer external event counting pulse output squarewave output PWM pulse width modulation output width period capture mea
157. rm either analog input analog output digital input digital output or counter timer functions An A D that sequentially compares a series of binary weighted values with an analog input to produce an output digital word in n steps where n is the A D s resolution in bits A property of a function that begins an operation and returns only when the operation is complete A measure of the amount of noise seen by an analog circuit or an A D when the analog inputs are grounded Transmission Control Protocol Internet Protocol the basic 2 layer communication protocol of the Internet but that is also used in a private network either an intranet or an extranet The higher layer TCP manages the assembling of a message or file into smaller packets that are transmitted and received by a TCP layer that reassembles the packets into the original message IP handles the address portion of each packet so it gets to the right destination Total harmonic distortion the ratio of the total RMS signal due to harmonic distortion to the overall RMS signal expressed in dB or percent The percentage of Total Harmonic Distortion Noise THD N of a sine wave equals 100 times the ratio of the RMS voltage measured with the fundamental component of a sine wave removed by a notch filter to the RMS voltage of the fundamental component A temperature sensing element that exhibits a large change in resistance proportional to a small change in temperature T
158. rs apply a voltage to a loop and the DAQ card must be able to accept the resulting current flow The ability of a DAQ board to supply current for analog or digital output signals Appendix G Glossary CV clock D A DAC DAC conversion Start DAQ dB differential input DIO DLL DNL DMA drivers The Conversion Clock also known as the Pacer clock it triggers individual acquisitions and thus tells the A D how fast to digitize successive samples Digital to analog digital analog Digital to Analog Converter an integrated circuit that converts a digital value into a corresponding analog voltage or current Signal used to start the process of converting a digital value to an analog output The source of this signal can be either an internal synchronous clock or an external asynchronous signal Data Acquisition 1 Collecting and measuring electrical signals from sensors transducers and test probes or fixtures and moving them to a computer for processing 2 Collecting and measuring the same kinds of electrical signals with A D or DIO boards plugged into a PC and possibly generating control signals with D A or DIO boards in the same PC Decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log 5 V1 V2 for signals in volts An analog input configuration that measures the difference between signals on two terminals both of which are isolated from comput
159. rs as a pot The technique used on a DAQ board to keep a continuous buffer filled with data so that when the trigger conditions are met the sample includes the data leading up to the trigger condition also see PGA an amplifier where you can change the amount of gain applied to the inputs Gain settings today are usually made with software instead of setting jumpers as was necessary with first generation DAQ boards The standard method a CPU uses to access an I O device each byte of data is read or written by the CPU The amount of time required for a signal to pass through a circuit A control action whose output is proportional to the deviation of the controlled variable from a desired setpoint The exact sequence of bits characters and control codes used to transfer data between computers and peripherals through a communications channel Appendix G Glossary pseudodifferential PXI Q quantization error R real time relative accuracy resolution resource locking ribbon cable RMS RTD An analog input configuration where all channels refer their inputs to a common ground but this ground is not connected to the computer ground PCI eXtensions for Instrumentation a bus standard that combines the mechanical form factor of the CompactPCI specification and the electrical aspects of the PCI bus It also adds integrated timing and triggering designed specifically for measurement and automation a
160. s cccccccssccessceeseecessceeseeceseeesseeceseeseseecsseeeeseecsseeeeseeces 10 Table 2 3 PowerDAQ PDXI MF Series Models 11 Table 2 4 PowerDAQ PDXI MFS Model 12 Table 2 5 MEFS Differential Upgrade Options 13 Table 2 6 PD2 PDXI FIFO upgrade option uses 13 Table 2 7 PDL MF board specifications ccccscceseceseeesecseeeseeeseeeeeeeceeseeneeenseeeseceaeeseceeeaeeeneeses 14 Figure 3 1 PowerDAQ Software Installation Startup Screen 16 Figure 3 2 Control Panel Application ss 18 Figure 3 3a Connector layout for long slot PD2 Family boards eee 19 Figure 3 3b Connector layout for sandwich format PD2 family boards 20 Figure 3 4 Connector layout for PDXI MF S Series boards 21 Figure 3 5 Connector layout for PDL MF board ss 22 Figur 3 6 PDXTI Configurator eoe eet Ae rte ea tee t Red repeated es 23 Figure 3 7 Cable connection diagram for PowerDAQ MF S boards 25 Figure 3 8a Physical layout of J1 JAI Connector on PD2 MF S Series boards 25 Figure 3 8b Pin assignments on J1 JAI Connector on PD2 MF boards in single ended mode ct ee eerte i eie ee 26 Figure 3 8c Pin assignments on J1 JAI Connector on PD2 MF boards in differential mode i uini oet eee bte Ee bk de ha ere e ES Bie Ree 27 Figure 3 8d J1 JAI Connector on PD2 MFS boards single ended or differential modes sisirin iino ane RS dt ENEE RU 28 Figure 3 9a Physica
161. s it tells you how much new data there is and where it is located If incoming data has passed the buffer boundary and starts filling it from the beginning the eFrameDone event occurs twice 80 5 Analog Input Subsystem once to let the user application retrieve data at the end of the buffer that is from the point of the last retrieval to the end of the buffer and a second time to let the application retrieve data from the beginning of the buffer to the latest complete frame During any PdAInGetBufState call the application gets the data in one piece This eliminates the need for the user application to deal with wraparound situations Finally note that PdAInGetBufState has a side effect When called it marks frames it returns as read and thus these frames can be reused for new data Reset events with PdSetUserEvents Call this function to tell the driver that events have been processed Now perform application specific tasks on the data Make sure that each procedure is short enough to process everything required before the next eFrameDone event arrives Otherwise the buffer can overflow and the driver can stop acquisition Tips for reading thermocouples and other slow speed processes There are two ways of reading slow speed processes Method A is better when the application doesn t require a precise timebase and needs 10 or fewer datapoints per sec Method C is better for rates exceeding 10 datapoints per sec
162. s carrying power lines and signal lines physically separate Never put signal cables in the same wiring harness as high current or high voltage cables Avoid routing signal and power cables together in parallel paths unless a reasonable distance separates the paths reasonable being determined by the strength of the power signals and the amount of shielding Be aware that many external factors among them power lines poorly designed video monitors or switching power supplies solenoids electric arcs from circuit breakers or welders and unshielded signal cables can have a negative impact on the accuracy of your measurements Single ended inputs are appropriate when you need to measure a large number of signals but you also need to keep system costs to a minimum and you are confident that the above noise inducing situations can be avoided Input multiplexers have a high input impedance It is highly recommended that you ground all unused channels using a 1 kOto 10 kQ resistor Further try to use signal sources with a low output impedance lt 100Q to avoid crosstalk To limit signal bandwidth you can also place a capacitor on the screw terminal panel between the signal and ground single ended mode or for differential mode between signal and return lines The suggested capacitor values are between 1000 pF and 0 047 uF depending on the input frequency and the impedance of the signal source according to F 1 21 RC 51 5 Analog Input
163. se in the CL clock from an application program This has the same effect of reading one channel because this setup allows one pass through the Channel List but for this application the list contains only one entry 61 5 Analog Input Subsystem 2 Single scan through Channel List As you might surmise only a slight variation in the procedure could allow the board to make one reading from multiple channels simply expand the number of entries in the Channel List In addition you now work with clocks a bit differently First set the CV clock to continuous for the fastest stepping through the list For the CL clock use a software source and have the application program make a call to the PdAInSwClStart function to start one run though the Channel List assuming that you have also set the Start trigger active Note that you need one CV clock pulse for each entry in the Channel List but you first need a CL clock pulse to activate the list and set the pointer to the first entry For instance you can set the CV clock running free but nothing happens until you pulse the CL clock 3 Multiple scans through Channel List If you want multiple runs through the Channel List you must pulse the CL clock each time you want to enable another run although the CV clock steps through the list You might think it would be convenient to set both clocks to continuous but that setup is not advised because you don t have a reliable timebase there might be
164. shot in Fig 5 5 the last line shows some typical settings for a board that has a 1k sample A D FIFO xMd 1 Transfer mode Fast mode 1 xFh 1 Transfer size move one 512 sample block upon FIFO half full event xPg 8 Page size interrupt the driver after it makes eight transfers or 4k samples This value depends on the size of the FIFO installed on the board and these transfer parameters default to the values in Table 5 6 67 5 Analog Input Subsystem PowerDAQ Control Panel x PowerDAQ Boards Installed Serial Number 0015677 Close About System Bus PCI v 2 2 DSP v 2 ADC FIFO Size 1 kS DAC FIFO Size 2 kS Manufacture Date 01 4PR 2001 Calibration Date 18 4PR 2001 Firmware type MFx rev 3 24 30311 Logic Revision 00311 Base address OxFO800000 IRQ number 10 xMd 1 Eh xPg 8 zl 9 6 6 9 9 Driver Information Version 31 Build Type Release Build Timestamp Tue Mar 11 19 49 00 2003 Figure 5 5 Control Panel applet with typical PowerDAQ board settings Data transfer method tradeoffs Depending on the speed of your board and how often you want to read new data from the board you must choose between programmed I O and bus mastering In general if you need a short response time use Normal mode or Fast mode Consider an example of a 100 kHz board with a 1k sample A D FIFO The FIFO gets emptied when it is half full or 512 samples 100k samples se
165. sical layout of J2 on PD2 MF MES Series boards Fig 3 9a gives a view looking into the connector socket mounted on the board CTRO IN 2 CTR2 IN CTRO OUT 4 LCTR2 OUT CTRO GA 6 CTR2 GATE CTR IN 8 H CTR GATE CTRt OUT4 9 10 5V 100 mA max DINO 12 DGND DIN 44 DOUTO DIN2415 6 DOUT1 DIN34 17 8 H DOUT2 DIN44 20 DOUT3 DIN54 21 22 DOUTA DIN6 23 24 DOUTS 26 DOUT6 Burst Clock ADC Channel List Sart Input 27 28 DOUT DSP Trigger Input AO External Clock 30 DGND Pacer Clock ADC Conversion Start Input 32 ADC Conversion Start Output Pacer Clock Output DGND4 33 34 DGND Burst Clock ADC Channel List Sart Output 36 NC Figure 3 9b Pin assignments for J2 Connector on PD2 MF MFS boards 29 3 Installation and Configuration Connector pin assignments for J4 The J4 Connector handles an additional eight digital input and eight digital output lines on boards with these extra DIO features 2606492090000 044060448 36 Jeesa99 00 co ooee ve oi Figure 3 10a Physical layout of J4 on PD2 MF MES Series boards Fig 3 10a gives a view looking into the connector socket mounted on the board DGND PF DGND F DGND F DGND F 5V 100 mA max FDGND DOUT DOUTS FDOUT10 DOUT11 F DOUT12 F DOUT 3 DOUT DOUT DGND r DGND F DGND F DGND Figure 3 10b Pin assignments for J4 Connector on PD2 MF MES boards 30
166. signments in Fig 3 12b However we have prepared separate differential input pin assignment diagrams for the PD2 PDXI MF S boards and they appear in Figs 3 8c and 3 8d The voltage between the inputs and the PC ground is monitored by two high impedance amplifiers A third amplifier measures the difference between the Positive and Negative inputs eliminating any voltage common to both wires This method eliminates problems that can arise with a single ended system because this configuration attenuates noise common to both channel inputs common mode noise Thus it s wise to use twisted pair cable to bring signals to the data acq card because that setup ensures that any noise generated along the wiring path is the same for each line and this noise gets subtracted by the amplifier Although using differential inputs on MF Series and PDL MF boards cuts in half the number of channels you can read with a given data acq card compared to single ended or pseudodifferential setups there are several cases where you are well advised to use differential inputs e when signal leads are over a few meters in length because the instrumentation amp can eliminate the effect of noise pickup from signal leads and also eliminate the possibility of ground differentials e when measuring signals less than approximately 100 mV because such low level signals can otherwise be easily overwhelmed by noise and ground differentials that only the differential mode can remov
167. sses on the same machine or processes located anywhere on the network The voltage that an isolated circuit can normally withstand usually specified from input to input and or from any input to the amplifier output or to the computer bus kilo the standard metric prefix for 1000 or 10 used with units of measure such as volts Hertz and meters The adherence of device response to the equation R KS where R response S stimulus and K is a constant Least significant bit mega the standard metric prefix for 1 million or 105 when used with units of measure such as volts and Hertz the prefix for 1 048 576 or PN when used to quantify data or computer memory A unit for data transfer that means 1 million or 10 bytes sec Man machine interface the means by which an operator interacts with an industrial automation system often called a GUI A switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel Appendix G Glossary multitasking mux N noise OLE OLE controls operating system optical isolation OS output settling time output slew rate overhead P paging A property of an operating system in which several processes can run simultaneously see multiplexer An undesirable electrical signal Noise comes from external sources such as the AC pow
168. surement On the MF PDL card TMRO is shared with the AIn clock TMR2 is shared with the AOut clock 104 8 User Counter Timer Subsystem Programming Techniques Programming the Intel 82C54 can be difficult because of its various modes and settings To ease this job the PowerDAQ SDK provided the definitions you need along with a set of example functions in the file uct progr c which is located in the same folder with the UCTEvents Visual C example Please refer to that file and to the Intel 82C54 datasheet to assist you in learning how to program the UCT subsystem Please be aware that the PowerDAQ API provides separate event flags for each counter timer Note To write to the counter timer you must apply an input clock to the selected UCT You can control its Gate line using the PdUctSwSetGate function Note Examples in the SDK that fall into the UCT category are e DlEvents c e uct progr c e SimpleTest dpr e SimpleTest vbp Using UCT events Initialization Reset the UCT subsystem with PdUctReset to clear the latch and configuration register Set up UCT configuration Set up the edge sensitivity configuration PdUctSetCfe and refer to uct_progr c in the SDK files for bit definitions PdAdapterEnablelnterrupt using dwEnable 1 PdUctSetPrivateEvent sets up event object PdSetUserEvent and use CounterTimer as the subsystem name The driver defines three events one for eac
169. t by input range ses 71 Table 5 9 Displacement by input range s sesseessssesssssesersreseeessstsressestesestestssreresststessesresesseene 72 Table 5 10 Mode constants for use in analog input configuration word 73 Figure 6 1 Analog output data format ss 86 Figure 7 1 Digital input subsystem hardware block diagram eee 96 Figure 7 2 Digital input configuration word esee enne eere 97 Table 9 1 Third party software support 110 Figure D 1 PowerDAQ Software Structure sse 141 Figure E 1 Advanced Circular Buffer NENNEN 148 vii 1 Introduction This manual describes the features and functions of hardware in the PowerDAQ series of PCI and PXI multifunction data acquisition boards These high performance systems support functions including analog input AI analog output AO digital I O DIO and user counter timer I O UCT for either PCI bus or PXI CompactPCI based systems All PDXI cards support the PXI Trigger Bus Star Trigger lines and Local Bus on the P2 connector Nonetheless they run without modification in any C sized CompactPCI backplane except they lose support for PXI specific functions These boards all fall into one of the following broad classifications e PD2 PDXI MF Series Multifunction analog I O digital I O counter timer e PD2 PDXI MES Series Simultaneous Sampling Multifunction e PDL MF Lab Series Entry level Multifunction This manual
170. t create a minimal Channel List Failure to create this list and activate it with the CL clock before activating the CV clock will result in false data Put another way a PowerDAQ card ignores the CV clock until it senses a CL clock pulse until you activate the Channel List the A D doesn t do any digitizing You define the source of each of the two clocks during the card s configuration and initialization stages specifically with the command PdAlnSetCfg One of the parameters you pass to that command dwAlnCfg is a configuration word whose bits set the values of various analog input parameters More specifically you set two configuration bits in dwAInCfg to establish the source of each clock signal For the Channel List clock you work with AIB CLSTARTO and AIB CLSTARTI and for the Conversion clock you work with AIB CVSTARTO and AIB CVSTARTI To specify a clock source set the bits as follows Bit 1 Bit 0 software clock internal clock external clock continuous The default value for each of these four bits 1s Zero so not setting any of the bits leaves the default value of the two setup pairs 0 0 software clock To change a value there is no need to insert a line of code that toggles the bit value rather merely placing its variable name in the configuration word will change it to a One In many situations you will want to change the values of multiple bits to a One you do so by ORing them For instance to change the CL clock to
171. the configuration function External clock the user connects this signal to a terminal panel For instance you might want to export a clock from one card and have another card read that clock so both work in a synchronized fashion All the signals of interest on MFx Series boards are located on the J2 digital I O connector Pin 27 read external CL clock Pin 35 export CL clock Pin 31 read external CV clock Pin 32 export CV clock Note that most of these signals are also available on J1 the main connector on the mounting bracket that carries the analog I O signals However we recommend you working with clock signals from J2 where there is no chance that they could potentially degrade the quality of the analog signals on which the board is operating However if you are not planning to use digital I O using the J2 clock lines means you must purchase an additional cable Note further that on its external clock inputs the board provides 4 7 kQ pull up resistors Continuous clocking essentially gates the clock always On sending the next pulse at the earliest possible opportunity 57 5 Analog Input Subsystem CAUTION If you define a clock whose speed is too high for the subsystem to handle the board simply ignores any pulses that arrive before it is ready to respond to them but it does not issue an error message Both the CL and CV clocks are required Even if your application takes just one sample from one channel you mus
172. this manual DW Excellent DW Good Why Suggested improvements Other Comments Your background optional Your application Lj Yes DW Yes DI Yes E Yes _ ves Lj Yes _ Yes ves Fair 169
173. to clear the configuration and latch registers PdDInReset 100 7 Digital O Subsystem 101 8 User Counter Timer Subsystem Architecture Unlike the counter timers on many other data acq boards those on the MF MFS Series boards are fully dedicated to user tasks You can set up the three on board counter timers to any mode compatible with the Intel 82C54 chip Using a counter timer output to control the analog input and output subsystems can result in setups that perform sophisticated data acquisition tasks Certain applications though might require you to build external digital circuitry Additionally when they reach Zero counts these counter timers can generate events which can clock other subsystems and perform various operations The user counter timer UCT subsystem on MF MFS Series boards is based on Intel s 16 bit 82C54 counter timer chip again the PDL MF has a different configuration as described below That device contains three counter timers that are not required by any PowerDAQ subsystems and thus are fully dedicated to user applications Further the three counter timers are fully independent so that each can function in a different mode if desirable Note You can combine UCTO with UCTI to implement a 32 bit counter or use UCTO as a common prescaler for UCT1 and UCT2 The 82C54 solves a common problem that arises in setting up test systems the generation of accurate time delays under software c
174. ts _PdDOutWrite It s possible to acquiring a digital signal using analog techniques as analog In an application where you need to acquire some digital signals along with an analog input you can build a simple D A converter using a resistor ladder It allows you to convert up to eight digital input lines into one analog signal which you then digitize and from its value you can determine the values of the original digital bits for reliable detection using a 12 bit PowerDAQ board 98 7 Digital I O Subsystem Method B Generate an event upon edge detection In this scheme you set up an input configuration and the subsystem fires an event when it detects a specified edge on the corresponding input line The eight lower lines of the 16 bit digital input subsystem are edge sensitive The setup parameters for this method are very similar to those used in Method A The difference is that you should additionally enable and set up event notification As does the analog output subsystem digital inputs can share an event handler with other subsystems or have a dedicated event handler Examples in the SDK that fall into the category of Method B are e DIEvents c Initialization Reset the digital input subsystem with _PdDInReset to clear the latch and configuration register Set up the digital input configuration Set up the edge sensitivity configuration _PdDInSetCfg Specify an input line and an edge to be
175. turn AIN35 Return AIN33 Return AIN23 Return AIN22 Return AIN20 Return AIN18 Return AGND AIN7 Return AINS return AIN3 Return AIN2 Return AINO Return 27 3 Installation and Configuration AGND F AGND AGND AOUTO AGND AGND AGND AOUT1 DGND AGND AGND F AGND AGND AGND AGND F AGND AGND AGND AGND F AGND AGND AGND AGND AGND AGND AGND AGND F AGND AGND AGND AGND AGND AGND H AGND AGND AGND AGND H AGND AGND AIN7 AING Fr AGND AINS AIN4 AIN3 F AIN2 AIN1 AINO AGND AGND DSP Trigger Input AO External Clock ADC Conversion Start Out Pacer clock out 5V 100 mA max ADC Conversion Start Input Pacer clock H AGND AGND ch ADC Channel List Start Input Burst Clock AGND AGND FAGND AGND H AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND F AGND AGND F AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AIN7 Return AIN6 Return AINS Return AIN4 Return F AIN3 Return AGND AIN2 Return AIN Return F AINO Return Figure 3 8d J1 JA1 Connector on PD2 MFS boards single ended or differential modes 28 3 Installation and Configuration Connector pin assignments for J2 The J2 digital internal connector handles eight digital input and eight digital output lines the counter timers and an external A D pacer clock 2664444 00 00 084060048 6 Jpeaaaaoaoooenpeppeaa ii Figure 3 9a Phy
176. ue of the array of averages and uses it as a final value Giving you added flexibility in setting up a Channel List is the Slow Bit feature It is a special marker you can activate in every channel and it instructs the analog front end to insert a delay in the acquisition sequence thus allowing the input amplifier to settle before it clocks the A D to make a conversion This feature is useful if you are applying a high gain 100 or 1000 to a signal 46 5 Analog Input Subsystem With a Slow Bit you can give that channel extra time without slowing down all the others Be aware though that turning on the Slow Bits can result in a reduction in a board s maximum throughput rate The amount of delay due to a Slow Bit varies with each PowerDAQ model A table giving the minimum time between conversions you can expect with any particular model with the Slow Bit active appears in Appendix B The Channel List has the following format Bit 8 Bits 7 6 Bits 5 0 Slow bit Gain Channel to acquire 0 Off see Table 5 3b 000000 Ch 0 1 On 111111 Ch 63 Table 5 3a Channel List format Gain coding L Gains H Gains Gains for MFS Bits 7 6 MF Series MF Series and PDL MF boards 00 1 1 1 01 10 2 2 10 100 4 5 11 1000 8 10 Table 5 3b Programmable gain codes Input modes The analog input section on all PowerDAQ boards multiplexes the active input channe
177. uisition or wait until the buffer 1s full and acquisition stops The Single Buffer mode is the simplest to program and it s also the most common It is useful in applications where acquiring data in a continuous stream 1s not required This is similar to the way digital multimeters and storage scopes acquire signals whereby a single buffer is filled and then the waveform is displayed This process can also be repeated any number of times Circular Buffer In the Circular Buffer mode the buffer head and tail wrap to the beginning of the buffer when the end is reached Data is written at the location pointed to by head and the head pointer is incremented and likewise data is read from the location pointed to by the tail and the tail pointer is incremented When the head pointer wraps around and reaches the tail pointer then the buffer is considered full and acquisition stops with a buffer overflow condition To prevent unintentional incrementing of the tail pointer the pointer should be incremented after the application has finished reading the data in the buffer and has indicated that the buffer space is relinquished for the write operation The Circular Buffer mode is useful in applications that must acquire data with no sample loss Each acquired sample must be stored by the hardware driver and read by the application The data acquisition operation continues until the application issues a stop command to the driver If the application cannot ke
178. up resistors on all digital inputs including all external trigger lines all external clock inputs and counter timer inputs In the standard configuration excluding the PDL MF the eight lower lines of the digital input connect to a latch register You can then program this register to detect rising or falling edges on these lines 96 7 Digital O Subsystem To configure the latch you send a 16 bit word two bits being assigned to each of the eight sense inputs Setting the F bit for a given input to a One makes that input sensitive to a falling edge setting the R bit to a One makes that input sensitive to a rising edge Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 F R F R F R F R F R F R F R F R Figure 7 2 Digital input configuration word The latch register in the digital input subsystem provides one status bit for each line When it detects the configured edge falling or rising the detection latch logic does two things First it sets this status bit to a One second it fires an interrupt to inform the DSP that the configured conditions have been met If you set up a latch to watch for edges on several lines the interrupt fires as soon as any of the selected conditions happens However the interrupt will not refire until the user application clears the status bit for that first line Then when the logic detects another change on any line the interrupt fires agai
179. uracy External A D Sample Clock 400k S sec 333k S sec 150k S sec Maximum Frequency Minimum Pulse Width 20 nsec External Digital TTL Trigger High level Input Voltage 2 0V min Low level Input Voltage 0 8V min Minimum Pulse Width 20 nsec 124 Appendix A Specifications Analog Outputs all PDXI MF models Number of Channels 2 Resolution 12 bits Update Rate 200k S sec each Onboard FIFO Size 2k samples on DSP Analog Output Range 10V Error Gain 1 LSB Zero Calibrated to 0 Current Output 20 mA max Output Impedance 0 3W typ Capacitive Drive Capability 1000 pF Nonlinearity 1 LSB Protection Short circuit to analog ground Power on Voltage OV 10 mV Setting Time to 0 01 of FSR 10 usec 20V step 1 psec 100 mV step Slew Rate 30 V usec Digital I O all PDXI MF models Input Bits 16 8 can generate IRQ Output Bits 16 Inputs High level Input Voltage 2 0V min Low level Input Voltage 0 8V max High level Input Current 20 pA Low level Input Current 20 pA Outputs Output Driver High Voltage Output Driver Low Voltage 2 5V min 3 0V typ IOH 32 mA 0 55V max IOL 64 mA Current Sink 32 64 mA max 250 mA per port Pulse Width 20 nsec min interrupt bit latched on rising falling or either edge Power on Voltage Logic Zero 125 Appendix A Specifications Counter Timer all PDXI MF models Number
180. urns an event from the board the application must check to see what caused it Check events with PdGetUserEvents This function returns events for the specified subsystem The user application should analyze the events and take appropriate action An event word can contain following flags e eFrameDone a frame of data is ready for retrieval e eBufferDone eStopped The acquisition is complete All data is stored in the buffer and is available for analysis e eBufferDone eBufferWrapped Incoming data has reached the end of the buffer The next frame that will be filled is at the start of the buffer e eStopped The acquisition has stopped The reason could be a trigger pulse on the external trigger line a software command or a buffer error It s possible that the user application is not retrieving data from the buffer fast enough and there s no room for new incoming data Check other events to find out what caused the acquisition to stop e eBufferError Data integrity was compromised because of a lack of performance or system latency while serving interrupts see note about interrupts e eStopTrig The acquisition stopped because it received the Stop trigger pulse or a software command Retrieve data with PdAInGetBufState This function retrieves information about the position of unread frames in the buffer n scans ScanIndex and the number of scans available for the application NumValidScans In other word
181. uts Gains 1 2 4 8 two 12 bit D A PD2 MF 16 400 14L 400k samples sec 14 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 16 400 14H 400k samples sec 14 bit A D 16 SE 8 DI inputs Gains 1 1 4 8 two 12 bit D As PD2 MF 64 400 14L 400k samples sec 14 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 64 400 14H 400k samples sec 14 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D A PD2 MF 16 333 16L 333k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 16 333 16H 333k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 4 4 8 two 12 bit D A PD2 MF 64 333 16L 333k samples sec 16 bit A D 64 SE 32 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 64 333 16H 333k samples sec 16 bit A D 64 SE 32 DI inputs Gains 1 2 4 8 two 12 bit D A PD2 MF 16 150 16L 150k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 10 100 1000 two 12 bit D As PD2 MF 16 150 16H 150k samples sec 16 bit A D 16 SE 8 DI inputs Gains 1 4 4 8 two 12 bit D A Table 2 1 PowerDAQ PD2 MF Series models All PD2 MF Series models also include three counter timers and 32 digital I O lines 2 PowerDAQ MF MFS Series Features Overview PowerDAQ PD2 MFS Series Model Analog features PD2 MFS 4 2M 14 2M samples sec
182. y of Method A are simpleAin c simplescan pas simplescan bas vm64 pas voltmeter vbp V116 cpp PDGABoards cpp Programming Model Now let s take a detailed look at what s involved when working with a program that follows the model of Method A We urge you to read through this and all other programming models because they will give you valuable tips on how best to work with the PowerDAQ API Initialization Reset the board PdAInReset Set up configuration PdAInSetCfe where dwAlnCfg is the analog input configuration word whose bits define the operating parameters for the subsystem including the mode SE or DI input range clock and trigger sources Analog input configuration bits are defined in the file pdfw def h Note that if you want to change any parameter you must make a function call that includes all the parameters not just the one you wish to modify The recommended configurations for Method A are for software clocking dwAlnCfg AIB CVSTARTO AIR CVSTARTI or for an external clock dwAlnCfg AIB CVSTARTO AIR CVSTARTI AIR CLSTARTI For details on clocking options refer back to Table 5 5 Set up the Channel List PdAInSetChList where one parameter indicates the number of channels in the list and another parameter represents the Channel List data array 74 5 Analog Input Subsystem Enable conversions _PdAInEnableConv with dwEnable 1 PdAInSwStartTrig to issue the softwar
183. you some comments on where they are best applied The last column tells you which bits to mention and thereby set to One in the configuration word not including the bits in this word uses the default value of Zero Clock combination Bits to set in the CL Clock CV Clock Typical use dwAInCfg source source configuration word Software Continuous Toacquire one set of data points one scan A AIB CVSTARTO 62 5 Analog Input Subsystem software clock initiates one pass through the AIB CVSTARTI Channel List and then the board waits for another CL clock before restarting This method is useful in voltmeter type programs as well as in realtime control and hardware in the loop systems Internal Continuous For continuous acquisition with an accurate AIB CLSTARTO timebase After each CL Clock pulse the AIB CVSTARTO Channel List is executed at the maximum AIB CVSTARTI acquisition rate This is the primary mode for use with MFS cards and use it with MF cards when it s critical to minimize channel skew External Continuous For continuous acquisition when each run of AIB CLSTARTI the Channel List is triggered by an external AIB_CVSTARTO signal Use this mode to synchronize scans with AIB CVSTARTI external events Continuous Continuous To perform acquisition at the maximum speed AIB CLSTARTO possible Less accurate than using the timebase AIB CLSTA
184. zation Signal level at the moment of digitization Figure 5 4b Acquisition sequence for simultaneous inputs using S H amplifiers on MFS Series boards Simultaneous sample hold settling time issues The analog input timing on MFS Series boards in which dedicated sample hold amplifiers on each channel feed a common multiplexer is slightly different than the timing on MF Series boards where the analog input channels feed directly into a multiplexer Specifically on MF Series boards the front end can start an A D conversion on the first channel in the current run through the Channel List immediately after it has digitized the last channel in the previous Channel List On MFS boards in contrast an additional delay is required when the sequencer starts to work from the first entry of a Channel List because before a new Channel List can be read the board must instruct the bank of S H amps to hold at a new set of values Thus the sample hold amps need a certain amount of time to settle to sufficient accuracy prior to the digitization stage Note that acquiring a lower number of channels leads to a lower maximum aggregate speed for the board This drop in speed arises due to S H amp settling time delay which must allow for every time the Channel List is processed Clrate 1 S H settling time A D conversion time Number of channels Clocking and Triggering 56 5 Analog Input Subsystem PowerDAQ cards offer considerable flexi

PowerDAQ User Manual - United Electronic Industries

Contents

Download Pdf Manuals

Related Search

Related Contents