`Basics` in `ICE Emulator for 68HC11`
Contents
1. org 27FFH db 2 8 bank org 52800 8 ldx SA000 jsr 1800 2 rts select external mode accu a is bank address destination area in system memory set IX to banked area subroutine to write byte to emulation ram setting bank register IX is address A is date return 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 30 Banked Target Systems next examples shows the map load commands for translated bank numbers This example uses common program area on 0x0 0x7fff and a banked area from 0x8000 Oxffff with 2 banks system bankfile banksel bnk load bank file uses physical system mode ai banks map res reset mapper map mirror p 0x0 0x7fff 0 10000 mirror for common area map ram p 0x0 OxOffff map memory in banks and common map ram p 0x18000 0x1ffff map intern symbol reset mmu reset mmu create p 0x00000 0x07fff p 0x00000 0x07fff mmu create p 0x08000 0x0ffff p 0x08000 0x0ffff mmu create p 0x00000 0x07fff p 0x10000 0x17fff mmu create p 0x18000 0x1ffff p 0x18000 0x1ffff mmu on d load u applic dbg nc load file from ICC6811 IAR Memory Access Routines Addr Function Address Data Result 1800H MemWrite IX A 1808H MemRead IX A 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 31 Banked Target Systems MMU Using the MMU for 68HC11K This command and the commands MMU and SYStem Option MMU support the built in MMU of the 68HC11K P processor2. 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 46 EmulationFrequency Emulation Modules Module Overview LA 6680 MC68HC11G PLCC68 3 0 5 5 a MC68HC11A DIL48 L 6632 MC68HC11A PLCC52 LA 6681 MC68HC11C FP64 MC68HC11D DIL40 LA 6682 PLCC52 3 0 5 5 LA 6684 A 669 A 668 MC68HC711D DIL40 x MC68HC711D oS PLOC44 MC68HC711E DIL48 x MC68HC711E L MC68HC711E PLCC52 GE 668 668 668 po 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 47 Emulation Modules Order Information Order No Code Text LA 6680 ICE 11 ICE 11 Base Module LA 6681 M MC68HC11 C Module MC68HC11 C LA 6682 M MC68HC11 E 5V Module MC68HC11 E 5V LA 6690 M MC68HC11 E 3 3V Module MC68HC11 E 3 3V LA 6683 M MC68HC11 F Module MC68HC11 F1 LA 6684 M MC68HC11 K Module MC68HC11 K4 LA 6685 M MC68HC11 D Module MC68HC11 D3 LA 6688 M MC68HC11 P2 Module MC68HC11 P2 LA 6693 M MC68HC11 KW Module MC68HC11 KW Additional Options TO 1250 100 49 Emul Adapter for TO socket ET100 QF49 TO 1255 ET100 ETO SE Emul Adapter for TO socket ET 100 SE 0 4mm YA 1091 ET100 EYA QF49 Emul Adapter for YAMAICHI socket ET100 QF49 ET 1092 ET100 SET QF49 Surface Mountable Adapter for ET 100 QF49 TO 1251 ET100 STO QF49 Emul Adapter TO surface mount ET100 QF49 ET 1000 ET132 ETS QF03 Surface Mountable Adapter for ET132 QF03 LA 1004 ET132 FP132
3. If an address is larger than 64K the address bits A16 to A23 define the physical address A10 to A17 offset for MXADR used for the access To distinguish an access to page zero absolute from a logical address A24 must be set Otherwise the address would be interpreted as a logical address in the current CPU space A logical address alone doesn t unique identify the physical address as the address depends also on the setup of the VA PSA PEA and PGEN registers As a result logical addresses should only be used if the mmu registers were already setup Accessing internal resources RAM or peripherals is handled like an access outside of the MMU window Accesses outside the MMU set A16 and A17 according to the MXADRH register except CSV accesses This feature can also be used for a second banking outside the CSPROG area If this area is not banked it must be mirrored by MAP MIRROR commands The following schematic shows these relations for some examples 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 35 MMU preset PGEN xF MXADRH 03 MXADRL FC 0 PSA 60 0 01 logical address 1 5 0 6 7 8 9 Hex 16 bit MXADR logical CPU address gt address 1 0 logical MXADR gt address 0 0 logical physical address 14000 6789 6000 14789 0 6 7 8 9 16 bit logical CPU address Hex physical address 00000 6789 6000 00789 0 6 7 8 9 16 bit Hex current mmu logical CPU a
4. Memory Access Routines 31 32 Using the MMU for 68HC11K de SYStem Option MMU MMU usage 32 Using the MMU for 68HC11C 35 Memory CLASSES eegener 38 39 Keywords for the Trigger Unit 39 Keywords for the Display 40 LN EE 41 Keywords for the Port Analyzer 41 Additional Trace Channels 41 Modul M68HC11 A E D 42 Modul M68HC11 F 42 exonerat M M 43 Paris Hd 24 Realtime Operation Systems 45 Emulation FreqUeney EE 46 Emulation Moduls TE 47 Module Overview 47 Order Information 48 DER p Mee PR 49 Physical Dimensions nenne nennen aan 50 Dir ein ide 57 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 2 ICE Emulator for 68HC11 Version 06 Nov 2015 006980 IAR11 iarl1l sieve t5 HLL AI E w d 1 addr line source register int i primz k int anzahl 515 anzahl 0 517 for i 0 i lt SIZE flags i TRUE i lt SIZE 144 1 Ze flags 1 1 5 H end of frame 5
5. mmu c 0x00d000 0x00ffff 0x03d000 0x03ffff mmu on Glos 30 075 d s Ox3f 0x05 d s 0x40 0 0 0 d s 0x42 0x60 d s 0x43 0x0b0 Oyi y res Glo 1261 see tapp Mie ae r res probe mirror common area and Lime memory at physical locations select TEST mode activate MMU mode for with CSPROG common area memory and internal I O and RAM ROM page 0 ROM page 1 20K 20K ROM page 11 ROM page 12 common area CSV activate 20K 4K 12 turn off bootprom disable watchdog VA 0d000 PSA 6000 PEA 0b000 PGEN enable MMU and CSPROG clear symbols load application get reset vector for PC The MMU translation table is used for translating physical addresses analyzer trigger to logical addresses and logical addresses to physical addresses a logical address is not defined in the table the logical to physical translation is done by reading the MMU registers of the CPU and calculating the physical address This calculation doesn t take care about memory areas which are overlaid by internal memory or i o It is strongly recommended to defined all logical and physical addresses in the MMU table NOTE When accessing memory with physical addressing A by the CPU the address for the CPU is transformed to a bank and offset using the MMU table Physical addressing of emulation memory is always possible without transformation EA 1989 2015 Lauterbach GmbH ICE Em
6. Bootstrap The emulator starts in Test mode the Bootstrap mode is selected on CPU reset Expanded by the target No change in the downloaded program is necessary The emulation must run in denied mode until the bootstrap sequence has been completed It is highly recommended to test software in Test or Single Test mode When starting emulation in Test mode the IRV bit is automatically set to 1 to show internal read accesses on the data bus In this way the analyzer may trace and trigger on internal data read cycles On starting the emulation monitor the EEPROM block protection is disabled Some control bits which may only be changed within the first 64 clock cycles are open in Test mode 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 13 Basics Bootstrap mode emulated in Test mode sys cpu singletest Start in Test or SingleTest mode Glos 1036 0525 Switch RBOOT flag to ON map ram 0x0bf40 0x0bfff Map memory in boot area 0x0bf40 0xObfff 8 Cam OxOffc0 OxOffff vector table d copy OxObfc0 OxOfbff 0 0 0 Copy Vector table d s 103c 0x075 Switch RBBOT off r s 0x0bf40 Set program counter The boot program may be now tested with breakpoints and single step If running in bootstrap mode no trace or breakpoint is possible as the emulation CPU has set the internal bus to single chip mode 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 14 Basic
7. L Adapter ET132 to Footprint AMP 3M sockets LA 1003 ET132 FP132 R Adapter ET132 to Footprint AMP 3M socket LA 6450 PA64 Port Analyzer LA 1923 PLCC BLOCK 68 PLCC Block 68 Pins LA 1926 PLCC TEST ADAPTER 68 PLCC Test Adapter 68 Pins LA 8806 SIM 12 2 Instruction Set Simulator for 11 12 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 48 Emulation Modules Operation Voltage CPU Module Adapter Voltage Range MC68HC11E LA 6690 3 0 5 5 MC68HC11G 3 0 5 5 V ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 49 Operation Voltage Physical Dimensions Dimension LA 6681 M MC68HC11 C cable 400 64 gt 37 LE rt 9 O 1 lt 93 mi 103 gt SIDE VIEW i rcc i Isocket 64 2116 1272 2525 1 3 30 VIEW all dimensions mm 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 Physical Dimensions Dimension LA 6682 M MC68HC11 E 5V LA 6690 M MC68HC11 E 3 3V cable 400 4 63 68HC11A E Port dieu gt E Li 9 PLCC 52 11 48 lt 93 gt 103 gt SIDE VIEW ner UJ T r 1 lsoc
8. MN 11 PORR A li bocket 64 1 d 11 21 17 TOP VIEW all dimensions mm ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 54 Physical Dimensions Dimension LA 6688 M MC68HC11 P2 cable 400 lt 66 gt 68HC11P Port Repl 37 1 13 9 PLCC84 97 107 SIDE VIEW HC11 P ee rary ee SE NI socket w L 4 18 gt 6 VIEW all dimensions mm ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 55 Physical Dimensions Dimension LA 6693 M MC68HC11 KW cable 400 9 105 115 gt SIDE VIEW E e 4 11 I I I 69 L pm ar 8 1 VIEW all dimensions mm 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 56 Physical Dimensions Adapter Not necessary 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 57 Adapter
9. When accessing memory with physical addressing A by the CPU the address for the CPU is transformed to a bank and offset using the MMU table Physical addressing of emulation memory is always possible without transformation EA ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 34 MMU Using the MMU for 68HC11C This command and the commands MMU and SYStem Option MMU support the built in MMU of the 68HC11C processors Format SYStem Option MMU lt mask gt The mask defines which port pins are used for the address extension The following table shows the possible values mask mode 00 No MMU used 01 MMU 64K expansion 03 MMU 128K expansion 07 MMU 256K expansion 11 MMU 64K expansion CSPROG used 13 MMU 128K expansion CSPROG used 17 MMU 256K expansion CSPROG used WARNING Switch off the internal ROM when using the 68 11 0 with MMU in TEST mode bit in HPRIO In TEST mode the external memory at the address of the internal RAM or I O location cannot be accessed When CSPROG is used to distinguish different memories is will be used as physical A19 for the emulator The analyzer and all memory systems and breakpoints are based on the physical address The display in the analyzer can be both physical or logical addresses A logical address can have two formats smaller than 64 K or larger Smaller addresses are assumed to be a logical address as seen by the CPU in the current MMU configuration
10. diodes RESET Target R1 R2 R3 S1 52 53 54 RESET input vec R1 R3 51 GND 22K 4 7K 220 Reset Target Reset Out Reset In Internal Reset ICE Emulator for 68HC11 vcc R2 RESET Emulation CPU 2 3 54 GND X Activate PerReset X Puls PerReset running running X Enable Reset running Emulator Control X Activate CpuReset running X Puls CpuReset running 1989 2015 Lauterbach GmbH 22 Exception Control eXception Activate Force exception Format Format Format Format Format eXception Activate CpuReset ON OFF eXception Activate PerReset ON OFF eXception Activate IRQ ON OFF eXception Activate XIRQ ON OFF eXception Activate OFF CpuReset PerReset IRQ XIRQ OFF Activates the RESET line of the CPU Activates the RESET line on target side Activates the IRQ line Activates the XIRQ line No activation of any exception line 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 23 Exception Control eXception Enable Enable exception Format eXception Enable CpuReset ON OFF Format eXception Enable PerReset ON OFF Format eXception Enabke IRQ ON OFF Format eXception Enabke XIRQ ON OFF Format eXception Enable OFF Format eXception Enable ON CpuReset Enables the RESET line of the CPU PerReset Enables the RESET line on target side IRQ Enables the IRQ line XIRQ Enables t
11. w Banking and K4 MMU HICROSS C Freescale HICROSS Semiconductor Inc 11 Freescale COFF Semiconductor Inc GCC11 Generic DBX C ICC681 1 IAR Systems AB UBROF Banking support C C11 Introl Corporation ICOFF 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 43 Compilers 3rd Party Tool Integrations CPU Tool Company Host ALL ADENEO Adeneo Embedded ALL X TOOLS X32 blue river software GmbH Windows ALL CODEWRIGHT Borland Software Windows Corporation ALL CODE CONFIDENCE Code Confidence Ltd Windows TOOLS ALL CODE CONFIDENCE Code Confidence Ltd Linux TOOLS ALL EASYCODE EASYCODE GmbH Windows ALL ECLIPSE Eclipse Foundation Inc Windows ALL RHAPSODY MICROC Corp Windows ALL RHAPSODY IN C IBM Corp Windows ALL CHRONVIEW Inchron GmbH Windows ALL LDRA TOOL SUITE LDRA Technology Inc Windows ALL UML DEBUGGER LieberLieber Software Windows GmbH ALL ATTOL TOOLS MicroMax Inc Windows ALL VISUAL BASIC Microsoft Corporation Windows INTERFACE ALL LABVIEW NATIONAL Windows INSTRUMENTS Corporation ALL CODE BLOCKS Open Source ALL C TEST Parasoft Windows ALL RAPITIME Rapita Systems Ltd Windows ALL DA C RistanCASE Windows ALL TRACEANALYZER Symtavision GmbH Windows ALL SIMULINK The MathWorks Inc Windows ALL TA INSPECTOR Timing Architects GmbH Windows ALL UNDODB Undo Software Linux ALL VECTORCAST Vector Software Win
12. will set the default update frequency of Data List Data dump Variable windows to 1 second the slowest possible setting prevent unneeded memory accesses using MAP UPDATEONCE address range for RAM and MAP CONST address range for ROM FLASH Address ranged with MAP UPDATEONCE will read the specified address range only once after the core stopped at a breakpoint or manual break MAP CONST will read the specified address range only once per SYStem Mode command e g SYStem Up ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 7 Target Power Supply Switch Is there a simple way to control target power supply via the ICE to prevent problems after the ICE has been powered off Follow the sequence below If you own an output probe COUTS connect it to the STROBE output con nector Type PULSE2 and press F1 You will get the pin out of the output probe COUTS Pin 13 OUT6 delivers 5 V after the emulator has finished its ini tialization and 0 V if the emulator is powered off This can be used to drive a relay via a transistor to switch the target power on and off automatically if the Pulse Generator is not used for other purposes The schematic of the switching unit can be found in the TARGETC CMM Additionally Pin 13 OUT6 can be controlled by ICE commands Target power supply off PULSE2 P Target power supply on PULSE2 P The following Practice command file creates 3 buttons in the Too
13. 0 SP gt 00 001 primz 3 x B 0 01 00 1 15 D 0 02 03 W per 3 03 00 sieve imer 0 04 03 000 sieve FORC 00 FOC1 L FOC2 i 3 00 1 7 OffOC1M primz 3 00 1 7 L k 3 CNT 32CD anzahl 3 FFFF Z SP 240F 05 00 6980 06 03 CCR OD4 07 00 5 N 2 For general informations about In Circuit Debugger refer to the ICE User s Guide ice user pdf general commands are described in IDE Reference Guide ide ref pdf and General Commands and Functions 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 3 WARNING NOTE Do not connect or remove probe from target while target power is ON Power up Switch on emulator first then target Power down Switch off target first then emulator 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 4 WARNING Quick Start tod 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 5 QuickStart Troubleshooting Hang Up If you are not able to stop the emulation there may be some typically reasons Clock Error The clock lines between the target and the CPU on the probe are very short Therefore normally no problems should occur when using an external crystal Be sure that the capacitors on the target have a value of 20 pF minimum and are with short routes connected to the CPU socket Dualport Errors Dualport errors may o
14. 4 5 EEPROM 0xB600 2 3 4 5 setting bytes d s EEPROM 0xB600 0x1ff OxOff clear EEPROM d load b epromdata EEPROM 0xB600 loading data 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 27 EEPROM Management Banked Target Systems In banked systems the upper address lines are either supplied internally or by the external bank probe 8 additional lines offer 256 different memory banks Accessing the different pages is done by extending all memory and pc addresses to 24 bit The address bits A16 to A23 select the memory bank Every command which makes a memory access first calls a special bank driver subroutine to select the temporary memory bank On realtime emulation the bank number is traced on the upper 8 bits of the address bus On breakpoints the bank address is stored back to the MSB of the program counter Format SYStem BankFile lt file gt This command load the bank driver The bank driver is a special subroutine to select the actual bank Loading a special bank driver gives a maximum in flexibility to the user A bank address delivered by the emulator may be used to set microcontroller ports or external MMUs in the target system The bank file consists of a code number defining the bank operation mode and a code area which consists of a subroutine to set the correct bank state Writings to internal CPU ports may be executed directly while ports in target systems must be accessed by a special system call to address 1800H Th
15. 5 rd 04 000012 P 0069F3 opfetch 30 ldd 4 X tsx 000012 D 00FFFF 00 000011 P 0069F4 opfetch EC 000011 D 002414 rd 00 000010 P 0069F5 sfetch 04 000010 D 002415 rd 12 4 x 000009 0069 6 opfetch 83 000009 002414 rd mem 00 000008 0069 7 00 000008 002415 rd mem 03 000007 P 0069F8 rd 12 000007 P 0069F6 opfetch 83 subd 12 000006 P 0069F7 sfetch 00 000006 D 00FFFF rd 00 000005 P 0069F8 sfetch 12 000005 P 0069F9 opfetch 2E subd 12 000004 P 0069FA rd 14 000004 P 0069F9 opfetch 2E bgt 6A0F 000003 P 0069FA sfetch 14 000003 D 00FFFF rd 00 bgt 6A0F 000002 P 0069FB opfetch 3F 000002 P 0069FB opfetch 3F Without Sequencer With Sequencer Perfect coverage analysis prefetch cycles don t set read flags No trigger on prefetch to data fields within code area Program breakpoints may be in data area to protect Data breakpoints may be in code area for protection Select trace data transfers only Easy trigger on exception cycles Selective trace 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 16 Basics General SYStem Settings and Restrictions General Restrictions Program Break and Sin gle Stepping in Internal Memory Program breakpoints are not executed if set in internal RAM Single stepping is not possible EPROM ROM versions Versions with internal program memory must be used in Test or SingleTst mode or the inte
16. ICE Emulator for 68HC11 2 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ICE In Cireuit Emulator ntm t nno ICE Target Guides d M ICE Emulator for 68HC11 PED rm EN ads Troubleshooting Dualport Errors ce Emulation Modes CPU Modes SYStem Clock SYStem Access Code Sequencer General SYStem Settings and Restrictions General Restrictions SYStem Option Trace SYStem Option PerReset SYStem Option TestClock SYStem Option BASE SYStem Option PLL SYStem Option RWMC SYStem Option TRANS SYStem Line EC Exception Control lt lt nra RESET Control eXception Activate eXception Enable eXception Trigger eXception Pulse 1989 2015 Lauterbach GmbH Clock generation Dualport Modes Trace options Reset target Clock sense RAM and register mapping PLL mode Memory strobe mode Transparent mode Strobe control Force exception Enable exception Trigger on exception Stimulate exception ICE Emulator for 68HC11 1 EEPROM Management n 27 Target Systems ai 28 Internal 29 External 29
17. OFF TraceAll Normally dummy cycles and prefetches are not traced by the analyzer All CPU cycles are traced if this option is set ON TraceWait Normally wait cycles the cycles between the WAIT command and the next opcode fetch cycle TraceRes The reset line on the CPU disables the trace analyzer To see also this cycles switch on this option SYStem Option PerReset Reset target Format SYStem OptionPerReset ON OFF When activated the reset output line is active while the system is down This ensures that the target peripherals in reset state after the emulation is activated SYStem Option TestClock Clock sense Format SYStem Option TestClock ON OFF The emulator measures the system clock and switches down the emulator if a clock fail is detected Some derivatives stop also the oscillator when the STOP command is executed To prevent from switching down the emulation when the oscillator is stopped set this option to OFF 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 General SYStem Settings and Restrictions SYStem Option BASE RAM and register mapping Format SYStem Option BASE lt value gt The INIT register may be only set in the first 64 clock cycles after reset Therefore the monitor program on the emulator uses this value to remap internal memory and ports This value must be same value used in the program On reset when running in realtime the target program must set t
18. SM command When starting program execution at an address where a breakpoint is already set the emulator will immediately execute the interrupt program After returning from interrupt it will stop at the breakpoint without moving to the next instruction ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 17 General SYStem Settings and Restrictions Port Replacement HC11D The ports D6 and D7 may be not replaced directly on the 68HC11 D probe Writing to Port D in single chip mode is fully compatible to the original CPU The tristate function is the same as on the original CPU The port read function must on be done at address IOBASE 5 05H 1005H Port Replacement HC11F Port C direction register cannot be read back The function of port C in single chip mode is not affected I O Relocation HC11C Internal I O and RAM must be relocated within the first 2 KByte of a 4 KByte block A11 must be 0 Access to Protected Registers The values for the INIT registers must be set by the SYStem Option INIT command All other 64 cycle protected registers can only be set in the TEST modes or when a CPU reset is generated while the emulation is running ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH General SYStem Settings and Restrictions SYStem Option Trace Trace options Format SYStem Option lt option gt lt option gt TraceAll ON OFF TraceWait ON OFF TraceRes ON
19. c 0x01c000 0xO1ffff mmu c 0x04c000 0x04ffff mmu c 0x34c000 0x34ffff mmu c 0x3cc000 Ox3cffff mmu on Zl 122 56 0532 6557 Oc 5 0 58 0 3 0525 y res d load ws applic h11 iP Xe 0x38000 0x3bfff 0x0b0000 0x0b02ff 0x80300 0x80fff 0x0b1000 0x0b107 0x81080 0x87cff 0x0b74d00 0x0b7fff 0x00000 0x03fff 0x04000 0x07fff 0x34000 0x37fff 0x3c000 0Ox3ffff probe memory at physical locations select TEST mode activate MMU mode for with CSPROG common area memory 16K internal RAM RAM memory internal registers RAM memory 32K RAM memory ROM page 0 ROM page 1 ROM page 13 ROM page 15 activate PGAR PINs XA13 XA17 used as address lines two windows window 1 at 000 window 2 at 0000 offset values for and MM2CR 32K CSPROG size clear symbols load application get reset vector for BE The MMU translation table is used for translating physical addresses analyzer trigger to logical addresses and logical addresses to physical addresses a logical address is not defined in the table the logical to physical translation is done by reading the MMU registers of the CPU and calculating the physical address This calculation doesn t take care about memory areas which are overlaid by internal memory or i o It is strongly recommended to defined all logical and physical addresses in the MMU table NOTE
20. ccess X X INTREAD INTWRITE INTREAD Read internal memory X X INTWRITE Write internal memory IREQ Interrupt request line X X MEM Memory cycle X X MEMREAD MEMWRITE MEMREAD Memory read cycle MEMWRITE Memory write cycle Fetch data cycle FETCH DATA OPFetch 1st cycle of command X X X PDO PD5 Port D lines access X X PIRQ Interrupt request for port B or C port X X replacement PORT Input line from port analyzer X X PREFETCH Prefetch cycle normally not sampled X X X X Read Read access X X X X FETCH PREFETCH DUMMY MEM READ STACKREAD INTREAD XREAD SFETCH Sequential fetch 2nd opcode X Stack access X X X X STACKREAD STACKWRITE STACKREAD Stack read cycle internal or memory STACKWRITE Stack write cycle internal or memory X X 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 39 State Analyzer WAIT Wait cycle cycles between WAIT opcode and interrupt normally not sampled Write Write access MEMWRITE STACK WRITE INTWRITE XWRITE Exception cycle XREAD XWRITE XIREQ XIRQ input X XREAD Exception read e g vector read X X XWRITE Exception write e g interrupt stack X X For not CPU specific keywords see non declarable input variables in ICE FIRE Analyzer Trigger Unit Programming Guide analyzer prog pdf Keywords for the Display WAIT Wait for interrupt n
21. ccur by the following conditions 1 The operation frequency in GAP access mode is higher than 3 MHz 2 The clock signal is switched off 3 The CPU is hold in STOP state for a too long time To solve problems with dualport error first increase the SYStem TimeReq value Be sure that SYStem TimeOut value is bigger than the access time limit If it is not possible to solve the problem by changing the values you must switch to DENIED mode In this mode no access to memory is possible while running realtime emulation The dualport access has no effect on CPU performance 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 6 Troubleshooting Debugging The debugger is accessed via and the performance is very slow What can be done to improve debug performance The main cause for bad debug performance via Internet or VPN are low data throughput and high latency The ways to improve performance by the debugger are limited in practice scripts use SCREEN OFF at the beginning of the script and SCREEN ON at the end SCREEN OFF will turn off screen updates Please note that if your program stops e g on error without executing SCREEN OFF some windows will not be updated SYStem POLLING SLOW will set a lower frequency for target state checks e g power reset jtag state It will take longer for the debugger to recognize that the core stopped on a breakpoint SETUP URATE 1 s
22. cecute a RESET The following example shows how the eXception Activate instruction can be used for generating an immediate reset setup operation modes sys res sys cpu expanded sys m ee disable EPROM d s 04 Map memory map det 0 Offff define reset vectors d s Offfe w 1000 d s Obffe w 1000 load sample program d a 1000 101f nop d a 1020 bra 1020 example for option register programming d a 1010 ldaa 0 staa 39 set lst breakpoint typically on main program b s 1020 p activate cpu reset cpureset on start emulation g release cpu reset x a cpureset off check if o k wait 0 15 if n state run a r pc 1020 print Startup o k enddo 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 10 FAQ Basics The ICE 11 emulation head supports all 68HC11 derivatives from Freescale Semiconductor and Toshiba The adaption to different probes is done by changing the module Modules support both DIL and PLCC versions where applicable The maximum frequency of the base modul is 6 24 MHz however the emulation is only possible to the max speed of the MCU s available from the chip manufacturer All emulation probes support single chip and expanded modes The probes for 68HC1 K N C may run with or without MMU The emulator supports either 1 MByte directly or 256 pages with 64 K each together with banked target systems or paged EPROMs An additional slot in the base modul offers upg
23. ddress gt gt logical address 0 MMU window physical address MXADR 06789 3 c00 06389 0 16 bit Hex current mmu logical CPU address gt gt logical address 0 outside mmu windows physical address Ocdef set MXADRH 30000 19 no CSPROG 80000 bcdef 0 da e f 16 bit Hex current mmu logical CPU address gt gt ICE Emulator for 68HC11 inside CSV physical address Ofdef set A16 A17 30000 19 CSPROG 00000 3fdef 1989 2015 Lauterbach GmbH 36 MMU activate the correct address translation for breakpoints the MMU command must be activated following script demo m68hc1 1 etc mmu c0 cmm will prepare the 68HC11C0 for using the MMU in 256K mode with CSPROG line to select between RAM and ROM the example was taken from the MC68HC11C0 User Manual map mirror p 0x80000 0x85fff 0x090000 map mirror p 0x80000 0x85fff 0x0a0000 map mirror P 0x80000 0x85fff 0 050000 map ram a 0x0 0x3fffFf map ram a 0x80000 0x7fff map i Sys cpu test Sys o mmu 17 sys m ai mmu res mmu c 0x000000 0x005fff 0x080000 0x085fff mmu c 0x000000 0x005fff 0x090000 0x095fff mmu c 0x000000 0x005fff 0x0a0000 0x0a5fff mmu c 0x000000 0x005fff 0x0b0000 0x0b5Sfff mmu c 0x1006000 0x100afff 0x00000 0x04fff mmu c 0x1146000 0x114afff 0 05000 0 09 mmu c Oxldc6000 0x1dcafff 0x37000 0x3btft mmu c 0x1 06000 0x1f0afff 0x3c000 0x3cfff
24. dows ALL WINDOWS CE PLATF Windows Windows BUILDER ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 44 3rd Party Tool Integrations Realtime Operation Systems Name Company Comment CMX RTX Systems Inc RTX51 tiny ARM Germany GmbH 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 Realtime Operation Systems Emulation Frequency Module CPU F wo F wo S wo S WO S W1 S W1 DRAM 15 35 15 35 15 35 LA 6682 MC68HC11A 20 20 20 20 20 12 0 LA 6681 68 11 3 0 190 30 150 30 36 LA 6685 68 110 40 40 40 40 40 40 LA 6682 68 11 20 20 20 20 2 0 20 LA 6683 MC68HC11F 40 40 40 40 40 40 MC68HC11G 40 40 40 40 40 40 LA 6684 MC68HC11K 40 40 40 40 40 40 LA 6684 MC68HC11KA 40 40 40 40 40 40 LA 6693 MC68HC11KW 40 406 406 406 40 40 LA 6684 MC68HC11N 40 40 40 40 40 40 LA 6688 68 11 40 40 40 40 40 406 6688 MC68HC11PH 40 406 40 406 40 40 LA 6685 68 7110 20 2 0 20 206 206 20 LA 6682 MC68HC711E 20 20 20 2 0 20 20 LA 6684 68 711 40 4086 406 40 40 40 LA 6684 68 711 40 40 40 40 40 40 LA 6688 68 711 40 406 40 40 40 40 LA 6682 MC68HC811E 20 20 20 208 20 20
25. e internal bank address is places in accu A when calling the subroutine The reason for the call is placed in B O init 1 read 2 write 3 go 4 breakpoint Register holds the address for read or write functions After a breakpoint code 4 the current bank can be stored at the address pointed to by register plus 21 decimal The write function to the target system needs the address in IX and the data in accu A The BNK register holds the physical bank number The PP Program Pointer register hold the logical 24 bit PC address The translation between logical bank and physical bank also for the common areas is done by the MMU command Format SYStem Bank lt option gt lt option gt OFF Internal External 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 28 Banked Target Systems Internal Internal bank to support paged EPROMs e g 27C513 The internal bank register is set by writing to an address range selected by the command MAP Bank This example uses a common program area on 0x0 0x3fff a banked area from 0x4000 0x7fff with 4 banks map res reset mapper map mirror p 0x0 0x03fff 0 10000 mirror for common area map mirror p 0x0 0x03fff 0x20000 map mirror p 0x0 0x03fff 0x30000 map bank 0x4000 0x7fff Set area of banked eprom system bankfile banksel bnk load bank file and activate system up banking mode Bank drivers are special subroutines max length 256 bytes to set the bank or an exter
26. he INIT register again to the same value This value must be set correctly it also defines the chip select of the port replacement chip and the bus control while accessing internal memory On the 68 11 0 the lower byte defines the start address of the I O and the upper byte the start address of the RAM INIT2 A value of Off in the upper byte disables the internal RAM of the 68 11 0 SYStem Option PLL PLL mode Format SYStem Option PLL ON OFF OFF The PLL operation is disabled ON The PLL operation is enabled Derivatives with PLL like 68HC11P inside must be set to the correct mode before starting up the emulation system SYStem Option RWMC Memory strobe mode Format SYStem Option RWMC ON I OFF OFF The CPU memory access uses the R W and E signal ON The CPU memory access uses the RD and WR signal The bus interface of the 68HC11C derivatives has 2 modes 6811 like mode with E and R W function and an INTEL like mode with RD and WR signals 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 20 General SYStem Settings and Restrictions SYStem Option TRANS Transparent mode Format SYStem Option TRANS ON OFF The SYStem Option Trans has effect on logical addresses smaller then 64K If it is on then accesses to this area show the 64K of memory as seen by the CPU in the current paging configuration This is the transparent mode If it is off then in banked areas page zero of t
27. he XIRQ line OFF Disable all exception line ON Enables all exception lines 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 24 Exception Control eXception Trigger Trigger on exception Format eXception Trigger RESET ON OFF Format eXception Trigger STOP ON OFF Format eXception Trigger IRQ ON OFF Format eXception Trigger XIRQ ON OFF Format eXception Trigger Pulse ON OFF Format eXception Trigger OFF Format eXception Trigger ON RESet Trigger on RESET line STOP Trigger on STOP line IRQ Trigger on IRQ line XIRQ Trigger on XIRQ line Pulse Trigger on Pulse line ON Trigger on all exception lines OFF No trigger on any exception lines 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 25 Exception Control eXception Pulse Stimulate exception Format Format Format Format Format eXception Pulse PerReset ON OFF eXception Pulse CpuReset ON OFF eXception Pulse IRQ ON OFF eXception Pulse XIRQ ON OFF eXception Pulse OFF CpuReset PerReset IRQ XIRQ OFF Stimulate RESET line of the CPU Stimulate RESET line on target side Stimulate on IRQ line Stimulate on XIRQ line No stimulation on any exception line 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 26 Exception Control EEPROM be initialized with standard set or load commands using the storage class EEPROM
28. his area is shown and the contents of the according page register has no influence It has no effect on the memory access of the CPU executing user code Address Access to 000000 00ffff current 64K address space when TRANS is on 000000 00ffff page 0 when TRANS is off 010000 Offffff pages 1 0 100000 Offffffff current 64K address space SYStem Line EC Strobe control Format SYStem Line EC ON OFF OFF E signal is low if emulation is stopped and active if emulation is running ON E signal is always active In Expanded and Test mode the access to peripheral devices is controlled by the E line and the address bus To stop access while the emulation is stopped the emulator sets address output to Offxxh and switches of the Write line In this address range from OxFFOO OxFFFF no I O ports should be mapped The CPU accesses Offffh in idle dummy cycles Additionally the E line may also be stopped Off However some targets use this line as clock signal Stopping the E clock will force fatal errors in the target system 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 General SYStem Settings and Restrictions Exception Control E W X CpuReset PerReset IRQ XIRQ OFF CpuReset YCpuReset PerReset YPerReset IRQ Y XIR Puls XIRQ RESET Control The reset line input and output is controlled by a bridge with analog switches and
29. ket 64 20 MM 15 4 VIEW all dimensions mm 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 Physical Dimensions Dimension LA 6683 M MC68HC11 F cable 400 63 68HC11F Port Repl 37 11 13 9 PLCC 68 lt 93 103 gt SIDE VIEW PC 1 Bee Se TUE sn 20 1 TOP VIEW all dimensions mm 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 52 Physical Dimensions Dimension LA 6684 M MC68HC11 K cable 400 m 67 gt 68HC11K N Port Repl 34 1218 9 PLCC84 PLCC68 26 lt 97 107 gt SIDE VIEW HC11 K N 11 Games PLCC prcc I socket 1 Isocketl ees Se Seo 2 VORNE 17 21 IN 38 VIEW all dimensions mm ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 53 Physical Dimensions Dimension LA 6685 M MC68HC11 D cable 400 68 gt 68HC11D Port Repl 11 1 37 IT 9 PLCC44 DIL 40 lt 97 gt 108 SIDE VIEW A
30. lbox for Target power on Target power off Target power off and QUIT Adding that file to T32 cmm loads the buttons automatically after startup http www lauterbach com faq targetc cmm Wrong Location after Break Why is the location after break wrong Most emulators use some bytes of user stack for the break system Therefore it is necessary to have valid stack if single step or breakpoints are used 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 8 FAQ CONFIG Register Cannot be The CONFIG Register is implemented with EEPROM cells It can be written Modified anytime in any mode with the mechanism for programming EEPROM Writing has no immediate effect The new value gets active with the next reset See also chapter 4 4 1 6 CONFIG Register Programming in M68HC11 E Series Technical Data Book The CONFIG Register does not react on modifications So for changing the value use the following PRACTICE commands SYStem Down SYStem CPU SingleTst SYStem Mode AloneInt Data Set EEPROM 103f value SYStem Down SYStem Mode AloneInt Data dump 103f Then you can see the changed value 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 9 68 11 How program registers which be accessed through the first 64 CPU cycles only Start up Problems In TEST mode the emulator can access all registers at any time In EXPANDED or SINGLE mode the processor must run ex
31. nal mmu org 27FFH db 1 select internal mode bank accu is bank address org 2800 destination area in system memory ldx 4000 set to banked area jsr 1800 subroutine to write byte to target system setting the page register in the EPROM IX is address A is date AES return External External banked systems use a register or output pins of the CPU to generate the upper memory addresses These lines must be feedbacked to the emulator with the bank probe Unused inputs of the bank probe must be grounded or jumpered to ground pin 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 29 Banked Target Systems This example uses a common program area on 0x0 0x3fff a banked area from 0x4000 0x7fff with 4 banks In this example the bank is selected by bit 6 and 7 of Port A map res map mirror p 0x0 0x03fff 0 10000 map mirror p 0x0 0x03fff 0x20000 map mirror p 0x0 0x03fff 0x30000 system bankfile banksel bnk system up org 27FFH db 2 8 bank org 52800 7 ldab 503 1000 9 stab 51000 2 asla asla 5 asla asla asla asla oraa 1000 staa 1000 rts reset mapper mirror for common area load bank file and activate banking select external mode accu a is bank address destination area in system memory mask bit 6 7 store back shift 6 times store back and set bank address return Now the bank select is done by an external register selected at
32. ormally not sampled EC E clock of CPU PAO PA7 Port A PDO PD5 Port D PIRQ Port Interrupt XIRQ 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 40 State Analyzer Port Analyzer Keywords for the Port Analyzer Port AO Port A Port BO Port PB Port CO Port C7 Port DO Port D7 Port EO Port E7 not Version D Port FO Port F7 Port G0 Port G7 Port HO Port H5 Port WR Port WR Port IRQ P IRQ Version A D E F Port XIRQ P XIRQ Version A D E F Port H6 Port H7 Version H J Port EC Version Port AS Version A D E Additional Trace Channels Not used trace channels on Port Analyzer are connected to pins placed on the emulation module 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 41 Port Analyzer Modul M68HC11 A E D 25 23 21 19 17 15 13 11 9 26 24 22 20 18 16 14 12 10 1 Port PO 2 Port PL 3 Port F2 4 Port F3 5 Port F4 6 Port F5 7 Port P 8 Port F7 9 Port GO 10 Port Gil 11 Port G2 12 Port G3 13 Port G4 14 Port G5 15 Port G6 16 Port G7 17 Port HO 18 Port H1 19 Port H2 20 Port H3 21 Port H4 22 Port H5 23 26 GND Modul M68HC11 F w N Port H0 Port H1 Port H2 Port H3 Port H4 Port H5 au fF WN BP 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 42 Port Analyzer Compilers Language Compiler Company Option Comment ASM A6801 IAR Systems AB UBROF Source level debugging CX68HC11 Cosmic Software COSMIC
33. rading with the port analyzer to get timing and state trace features for all MCU I O ports Emulation Modes E w sys RESet Analyzer Monitor YResetDown ResetUp NoProbe AloneInt AloneExt EmulInt YTestClock TraceWait TraceRes 11 PerReset BAS 01 MMU cpu type M68HC11E Prefetch EmulExt Denied Expanded SingleTst BankFile Test EXTern Bootstrap BootExp The emulation head can stay in 6 modes The modes are selected by the SYStem Up or the SYStem Mode command Format SYStem Mode mode mode ResetDown ResetUp Alonelnt AloneExt Emullnt EmulExt 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 11 Basics Reset Down Reset Up Alone Internal Alone External Emulation Internal Emulation External Target is down all drivers a in tristate mode Target has power drivers are logically in inactive state but not tristate Probe is running with internal clock driver inactive Probe is running with external clock driver inactive Probe is running with internal clock strobes to target are generated Probe is running with external clock strobes to target are activated In active mode the power of the target is sensed and by switching down the target the emulator changes to RESET mode The probe is not supplied by the target When running without target the target voltage is simulated by an internal pull up resis
34. re already setup Accessing internal resources RAM or peripherals is handled like an access outside of the MMU window The following schematic shows these relations for some examples 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 32 MMU preset PGAR 3F MMSIZ 22 MMWBR 84 MM1CR 10 MM2CR 20 01 logical address 5 0 4 5 6 7 Hex 16 bit XA18 XA13 logical CPU address gt physical address 50567 logical address 0 1 4 5 6 7 Hex 16 bit 18 13 logical CPU address gt physical address 00567 logical address 0 0 4 5 6 7 16 bit current mmu logical CPU address mmu window 1 at logical address 4000 7fff 00567 10 10567 gt gt physical address logical address 0 0 16 bit current mmu logical CPU Hex address gt outside mmu windows gt physical address Ocdef 7 7cdef 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 33 MMU activate the correct address translation for breakpoints the MMU command must activated The following script will prepare the 68HC11K4 for using the MMU with 13 17 and CSPROG line to select between RAM and ROM map ram a 0x0 0x3ffff map ram a 0x80000 0x7fff sys cpu test sys o mmu 5f sys m ai mmu res mmu c 0x008000 0x00bfff mmu c 0x000000 0x0002ff mmu c 0x000300 0x000fff mmu c 0x001000 0x00107f mmu c 0x001080 0x007cff mmu c 0x007d00 0x007fff mmu
35. rnal EPROM must be turned off EPON bit in CONFIG register Stack Usage If the stack pointer is placed in external memory no stack memory is needed for emulation The stack size should be 9 bytes longer than used by the program In internal memory area 9 bytes below the stack limit are first written before starting realtime emulation Stackpointer should never be set to register area COP Function If the watchdog function is activated in the Option Register EEPROM the emulator is not able to start in Single or Expanded mode In this case start the emulator has to start in Test Mode and then the Option Register may be changed X Register The X register may be set or reset in the register window This does not change the status of the X register in the CPU When starting in realtime the value of this shadow register is copied to the CPU If reset the X register may never be set again with the Register command till the CPU is reset again either on target or by selecting an emulation mode SYStem Mode 4XCLK The output pin 4XCLK should not be switched off because this signal is used for the emulator logic On Board Programming On Board Programming with external programmers is not allowed with the emulation probe may be damaged Pending Interrupts If interrupts from internal sources are pending single stepping will go into the interrupt routine This behavior can be controlled by the SETUP IMASKA
36. s SYStem Clock Clock generation Format SYStem Clock lt option gt lt option gt vco High Mid Low vco Variable frequency 1 35 MHz Low Mid 2 5 5 0 or 10 0 MHz High SYStem Access Dualport Modes Format SYStem Access lt mode gt lt mode gt GAP DUMMY Prefetch Denied GAP The dualport access is done while E signal is low As two memory cycles appear in one CPU cycle this way of dualport access is limited to bus frequencies up to 3 MHz Dynamic emulation memory may only be used in this operation mode otherwise refresh error occurs DUMMY The dualport access is made on CPU idle cycles address Offffh Prefetch Dualport access is done on prefetch cycles marked by the code sequencer Denied No dualport access is allowed while the realtime emulation is running This mode must be used if the CPU is hold in stop state for long time or if the clock signal is switched off 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 15 Basics Code Sequencer TRACE32 ICE11 uses a special code sequencer to classify CPU bus cycles on realtime emulation This feature allows perfect trigger and trace functions as prefetch cycles or idle cycles are not traced The sequencer offers many functions not available on competitive emulation systems 000016 D 0069F4 rd EC st 4 x 000015 D 00240F rd 01 000014 D 002414 wr mem 00 000014 P 0069F4 opfetch EC 000013 D 002415 wr mem 03 000013 P 0069F
37. s SYStem Option MMU MMU usage Format SYStem Option MMU lt mask gt The mask defines which port pins are used for the address extension Bits zero to five correspond directly to the pins of port G XA13 to XA18 A set bit will activate the MMU function on the pin Bit six is used to control the behavior of the CSPROG line If set the CSPROG line is used as A19 for the emulator 68HC11 Multiplexer controlled by SYStem Option MMU CSPROG 1 0 A19 18 1 0 18 17 1 0 17 16 1 Emulator Address Bus 0 16 15 1 15 0 15 14 1 14 0 14 13 1 A13 0 A13 0 12 A0 A12 The analyzer and all memory systems and breakpoints are based on the physical address The display in the analyzer can be both physical or logical addresses A logical address can have two formats smaller than 64K or larger Smaller addresses are assumed to be a logical address as seen by the CPU in the current mmu configuration If an address is larger than 64K the address bits A17 to A22 define the physical page XA13 XA18 used for the access To access page zero absolute address A16 must be set otherwise the address would be interpreted as a logical address in the current CPU space A logical address alone doesn t unique identify the physical address as the address depends also on the setup of the PGAR MMSIZ CSCTL INIT INIT2 and MMWBR registers As a result logical addresses should only be used if the mmu registers we
38. tor ICE Emulator for 68HC11 1989 2015 Lauterbach GmbH 12 Basics 5 The emulator single mode is made by port replacement chips 68 24 MC68HC26 MC68HC27 The emulator may run in Single Chip in Expanded and in Test mode A special mode named Single Test is available to use all the features of the Test mode together with targets in single chip mode This command selects the operation mode of the emulator The command may only be executed in SYS RES mode and must be set to the correct operation mode External mode pins on the emulator probe are not sensed Format SYStem CPU lt mode gt lt mode gt Single Expanded SingleTest Test Bootstrap BootExp Single The CPU is running in Expanded mode the port replacement chip is active Expanded The CPU is running in Expanded mode the port replacement chip is switched off Single Test The CPU is running in Test mode but the port replacement is switched on Test The CPU is running in Test mode but may be switched to Expanded mode under software control Bootstrap The emulator starts in SingleTest mode but the Bootstrap mode is selected if the CPU is forced to RESET in realtime emulation The boot program which is downloaded must set the CPU to expanded mode while running in the internal RAM Don t set breakpoints on the bootstrap program internal The emulation must run in denied mode until the bootstrap sequence has been completed
39. ulator for 68HC11 37 MMU Memory Classes Memory Class Description C Specify the same address area CPU access D P A Absolute memory access requires MMU table AD AP EEPROM EEPROM write E Emulation memory access dualported ED EP EA Physical address 68HC11 K4 KA4 N4 only C P and D This storage classes operate on the same physically memory They are only used to be compatible with other emulation probes CPU internal registers and memory may not be accessed dualported by mapping memory to the same address range data written to the internal memory are also present in the emulation memory EEPROM This storage class is used to program the internal EEPROM On read cycles there is no difference to the access mode with C or D On write cycles the monitor program executes an EEPROM write protocol d s 0 00 Test H d load b test bin EEPROM 0 00 EA The storage class EA is only used for the 68HC11 K P C CPU and only if the MMU option is selected 1989 2015 Lauterbach GmbH ICE Emulator for 68HC11 38 Memory Classes State Analyzer Keywords for the Trigger Unit Input Event Meaning Analyzer Hardware ECC8 HAC 120 SA120 DATA Data access X X MEM STACK INT X DUMMY DUMMY cycle X X X X FETCH any fetch cycle X X X X OPFETCH SFETCH INT Internal memory a
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