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2. 2 4 Table 2 7 J35 P24T Clock Stop 2 2 4 Table 2 8 J36 DX SX Select 0 0 00 05 2 4 Table 2 9 J37 Cyrix CPU Select 0 2 5 Table 2 10 Board Jumpers 000085 2 6 Table 2 11 J1 IDE IRQ Enable 2 6 Table 2 12 J7 IDE Frequency Select 2 7 Table 2 13 J8 IDE Read Prefetch Enable 2 7 Table 2 14 J10 IDE Mode Select 2 7 Table 2 15 J11 IDE Drive Select 2 8 Table 2 16 J13 Floppy Select 00 4 2 8 Table 2 17 J15 Cache Select 0 0 0 4 2 8 Table 2 18 J16 SRAM Select 4 2 9 Table 2 19 J17 CMOS Clear Battery Enable 2 9 Table 2 20 J18 Mouse IRQ Enable 2 9 Table of Contents List of Tables continued Table 2 21 J19 Security Password Enable 2 10 Table 2 22 J28 Processor Speed 4 2 10 Table 2 23 J30 Video Enable Disable 2 10 Table 2 24 J31 Video IRQ Enable 2 11 Table 2 25 J32 DMA Channel for LPT 2 11 Table 2 26 J39 Video Enable Disable 2 11 Table 2 27 Connectors 0 000 eee eee 2 12 Table 2 28 J2 IDE Connector 00005 2 13 Table 2 29 J3 Floppy Connector 2 14 Table 2 30 J4 Parallel Port 0005 2 15 Table 2 31
3. Real Time Clock Information Addresses 00 0D ISA Connector Pin Assignments Appendix 2 Glossary of Terms Appendix 3 Illustration Orca Passive Backplane CPU Board Index List of Figures Figure 1 1 Orca CPU Board Jumpers Connectors amp Components Figure 4 1 Summary Screen Figure 4 2 Energy Screen Figure 4 3 Clock Screen Figure 4 4 Keyboard Screen Figure 4 5 Floppy Screen Figure 4 6 Fixed Disk Screen Figure 4 7 VL Bus IDE Screen Figure 4 8 Boot Sequence Screen Figure 4 9 Security Screen Table of Contents List of Figures continued Figure 4 10 Speed Screen 00 00005 4 29 Figure 4 11 Cache Screen ordni poon ooer Onn o aa ea 4 30 Figure 4 12 Shadow RAM Screen 4 32 Figure 4 13 Chipset Screen 00000005 4 35 Figure 4 14 37C665 Screen 0 000000 eee 4 37 List of Tables Table 1 1 DRAM Configurations 1 6 Table 2 1 CPU Jumpers 0000 00085 2 2 Table 2 2 J23 DX4 Internal Multiplier 2 2 Table 2 3 J24 486SL P24T Write 0 2 3 Table 2 4 J27 Clock Frequency 2 3 Table 2 5 J29 CPU Select tsas a saene n naa 0 000005 2 3 Table 2 6 J34 CPU Functions Enable
4. Local Bus IDE Controller Configuration Drive 80 C 6 Drive 81 D VL Bus LRDY Selectable Rate External Jumper Default F10 to Record and Exit Home End Moves Cursor Figure 4 7 VL Bus IDE Screen Explanation This screen allows you to get the maximum transfer rate possible from your IDE drives When you enter a question mark in the Drive 80 field the ATA rating reported by the drive will display in the bottom of the screen By selecting Selectable Rate in the Drive 80 field you can then enter the rate shown on the screen in the Selectable Rate field For two IDE drives repeat the process for Drive 81 If you have only one IDE drive select External Jumper in the Drive 81 field 4 23 Setup Screens Entry Fields ee Drive 80 C Enter a question mark 7 to Selectable Drive 81 D display the ATA rating of the drive Rate in the bottom of the screen External Select Selectable Rate for any Jumper IDE drive present Select External Jumper if no IDE drive is present VL Bus LRDY Select the ws access of the IDE controller For example if you re running at 50MHz select 1ws Selectable Rate Enter the transfer rate displayed at the bottom of the screen when 2 is entered in a Drive field External CPU jumpers determine the Jumper transfer rate of the drive Table 4 7 VL Bus IDE Screen Entry Fields 4 24 Chapter 4 B
5. lt Alt gt lt Enter gt during runtime or by pressing lt Enter gt during the cold boot memory test This is a convenient way to occasionally boot from floppy when the C Ist order is selected here as the default The following prompt will appear Press F1 to Boot A F2 to Boot C Respond by pressing lt A gt or lt F1 gt to boot from floppy or press lt C gt or lt F2 gt to boot from the fixed disk Memory Priming During cold boot BIOS conducts a memory test that both initializes and verifies the entire memory subsystem In sys tems with a large memory capacity boot speed can be significantly increased by selecting Quick Scan to clear the memory Cold Boot Delay can provide additional power up time required by some slow mechanical devices e g fixed disks A delay before Power On Self Test POST may be needed to allow proper initialization of various slow mechanical devices This is especially true of certain IDE drives that are unprepared for the unusually swift execution of this BIOS If you experience powerup difficulties try a delay of 1 to 30 seconds Entry Fields Ce ee e Operating Select OS 2 if the system is Not OS 2 System running the OS 2 operating OS 2 system Arts C22 C 1 A 2nd Auto Search Screen Prompt Boot Specify the drive order used to Sequence load the Operating System Memory Specify the memory testing Full Test Priming method Quick Scan Cold
6. Set keyboard typematic rate Initialize floppy disk drive Initialize fixed disk Clear screen and set mode for primary video adapter Hook 06 Setup 64K segments Adapter checksums Enable NMI Reserved Reserved Interrupt 19H Boot OS Table 4 15 Orca Post Codes 4 39 Orca Post Codes Post Code Test CPU Burst Power management warm boot disable Determine 8042 type Test High Memory Wrap around Determine CPU Validate CPU Green PC setup Reserved Reserved Reserved Set OEM defaults for bridge Identify AT BUS CDE space Reserved Reserved ATA mode support Reserved Reserved Reserved Reserved Determine PS 2 mouse Reserved Reserved Setup Utility Table 4 15 Orca Post Codes continued 4 40 Chapter 4 BIOS 00 00H 01 01H 02 02H 03 03H 04 04H 05 05H 06 06H 07 07H 08 08H 09 09H 10 0A H 11 0B H 12 0C H 13 0D H 14 0E H 15 0F H 19 13H 16 10H 17 11H 18 12H 20 14H 21 15H 22 16H 23 17H 24 18H 25 19H 26 1A H 27 1B H 28 1C H 29 1D H 30 1E H 31 1FH 32 20H 33 21H 34 22H 35 23H 36 24H 40 28H 37 25H 38 26H 39 27H 41 29H 42 2A H 43 2B H 44 2C H 45 2D H 46 2E H 47 2FH Cold Boot commences Not seen with warm boot Hook 00 OEM specific Disable critical I O 6845s BIOS checksum test Page register test Ports 818F 8042 Keyboard Controller Self test Gang Port Init 8237 m s Hook 01 OEM specific Refresh toggle test PORTB Pattern t
7. 08 08H LHHLH Slave 8 bit DMA Controller Failure 10 0AH LHLLLL Memory Bank 0 Pattern Test Failure 10 0AH LHHLLL Memory Bank 0 Parity Circuitry Failure 10 0AH LHLHLL Memory Bank 0 Parity Error 10 0AH LHHHLL Memory Bank 0 Data Bus Failure 10 0AH LHLLHL Memory Bank 0 Address Bus Failure 10 0AH LHHLHL Memory Bank 0 Block Access Read Failure 10 0AH LHLHHL Mem Bank 0 Block Access Read Write Failure 11 0BH LHHHHL Master 8259 Port 21 Failure 11 0BH LHLLLH Slave 8259 Port A1 Failure 12 0CH LHHLLH Master 8259 Port 20 Interrupt address Error 12 0CH LHLHLH Slave 8259 Port AO Interrupt Address Error 12 0CH LHHHLH 8259 Port 20 A0 Interrupt Address Error 12 0CH LHLLHH Master 8259 Port 20 Stuck Interrupt Error 12 0CH LHHLHH Slave 8259 Port AO Stuck Interrupt Error 12 0CH LHLHHH System Timer 8254 CHO IRQO Interrupt Failure 13 0DH LHHHHH 8254 Channel 0 System Timer Failure 14 0EH LHLLLLH 8254 Channel 2 Speaker Failure 14 0EH LHHLLLH 8254 OUT2 Speaker Detect Failure 15 0FH LHLHLLH CMOS RAM Read Write Test Failure 15 0FH LHHHLLH RTC Periodic Interrupt IRQ8 Failure 16 10H LHLLHLH Video ROM Checksum Failure at Address XXXX Mono Card Memory Error at Address XXXX Mono Card Mem Address Line Error at Address XXXX Color Graphics Card Memory Error at Address XXXX Color Graphics Card Address Line Error Address XXXX 17 11H None Real Time Clock RTC Battery is Discharged 17 11H None Battery Backed Memory CMOS is Corrupt 18 12
8. Shadow RAM is either cacheable or non cacheable Enable Cache Disable Cache Cache Size The BIOS enters this number automatically Table 4 11 Cache Screen Entry Fields 4 31 Setup Screens e Shadow RAM Screen Chipset 37C665 Best performance is usually obtained by copying ROMs into Shadow RAM F000 SYSTEM E000 ADAPTER F000 UMB User Info DC00 ADAPTER D800 ADAPTER BIOS FBEC FFFF D400 ADAPTER UTILS FA90 FBEB D000 ADAPTER POST F61C FA8F CC00 ADAPTER SETUP FISE F61B C800 ADAPTER C400 VIDEO AVAIL F000 FA51 C000 VIDEO Default WP2 Write Protected like a ROM RW Read Write F10 to Record and Exit Home End Moves Cursor Figure 4 12 Shadow RAM Screen Explanation Shadow RAM is a mechanism that copies Read Only Memory into main memory then substitutes that memory image for the original ROM This increases the execution speed of programming that resides in ROM BIOS and VGA Adapters are two main examples of ROMs that demonstrate significant performance gains when they are shad owed Since ROMs are by definition Read Only it is usually desirable to write protect the Shadow RAM However Shadow RAM can also be used as general purpose memory by certain programs In this case it should be enabled as Read Write memory While most Adapter ROMs can be shadowed either way some permit only the RW or WP option and a rare few cannot be shadowed at all You may need
9. 1 4 Chapter 1 Introduction Features The key features of the Orca CPU board are Supports 486SX through P24T Pentium Upgrade Central Processing Units CPUs 256K or 512K cache memory Supports up to 128MB DRAM Two high speed serial ports 16550 type UARTS One bidirectional parallel port with DMA access Floppy disk interface supporting up to two 2 88MB disk drives Local bus Enhanced Integrated Drive Electronics EIDE hard disk interface Real time clock with on board battery backup On board battery with 2 year life expectancy Keyboard mouse speaker and reset ports Watchdog timer two level Local bus SVGA video with up to 2MB display memory The following are detailed descriptions of the above features 486SX through P24T Pentium Upgrade CPU The Orca supports the 486SX 25MHz and 33MHz 486DX 33MHz and 50MHz 486DX2 50MHz and 66MHz DX4 100MHz and the P24T Pentium Upgrade CPUs Cache The Orca is equipped with 256K write back cache 1 5 Features gt DRAM The Orca CPU board supports up to 128MB of 72 pin DRAM SIMMs located in four sockets Sockets are labeled SM1 through SM4 Total SM1 sm2 SM3 SM4 4MB 4MB 1MB x 36 8MB 8MB 2MB x 36 16MB 16MB 4MB x 36 32MB 32MB 8MB x 36 8MB 4MB 1MB x 36 4MB 1MB x 36 16MB 8MB 2MB x 36 8MB 2MB x 36 32MB 16MB 4MB x36 16MB 4MB x 36 32MB 8MB x 36 32MB 8MB x 36 64MB 16MB x 36 _ 64MB 16MB x 36 16MB
10. Access Memory made from CMOS transistors D DMA Direct Memory Access Channel A channel for transferring data from host main memory to and from peripherals without direct involvement of the CPU resources DRAM Dynamic Random Access Memory The main memory in your computer It needs to be refreshed by a memory controller or it will lose its information A2 1 Appendix 2 Glossary of Terms E EPROM Erasable Programmable Read Only Memory A programmable device which stores information regardless of power The information can be erased and new information written F flash BIOS BIOS that is stored in flash memory rather than in a ROM Flash BIOSs can be upgraded in place whereas ROM BIOSs must be replaced with a newer chip Floating Point Unit FPU A device which can perform calculations on numbers in floating point format as opposed to simple integers IDE Integrated Drive Electronics A standard of signalling and communicating with a device interleave Multiple banks of memory that overlap to reduce the access time and eliminate wait states interrupt Temporarily halting the operation of a digital computer to respond to service an external event interval timer A device that can generate a pulse at a defined interval for background tasks IRQ Interrupt Request A signal channel used to trigger the CPU to temporarily change tasks K Kilobyte KB 1 024 bytes A2 2 Appendix 2 Glossary
11. Boot Unless required select None to None Delay avoid an unnecessary delay 5 Sec Initialization Select Active to enable Active Error Halts Inactive Table 4 8 Boot Sequence Screen Entry Fields 4 26 Chapter 4 BIOS e Security Screen VL Bus IDE Boot Seq Ports Speed More Security Security switch on system board must be enabled F10 to Record and Exit Home End Moves Cursor Figure 4 9 Security Screen Explanation A jumper must be installed on J19 before you can change or access the security password function Once the jumper is installed you can select a security code or password which you must then enter to access the computer The message Security Switch on system board must be enabled displays at the bottom of the screen when Disable appears in the entry field It reminds you the jumper must be installed before you can enter this field When the jumper is installed setting the entry field to Powerup Setup allows you to select a security code or password You will then be prompted to enter your password on this screen and to verify it You are also given the option of selecting Setup Only Disable or Change Code Setup only allows you to view the Summary Screen without allowing you to change anything in Setup Disable allows you to enter the computer without a password and Change code allows you to change your password once you ve assigned it 4 27 Set
12. C Status Register D Status Register E Table A1 7 Real Time Clock Information A1 6 Appendix 1 Technical Reference ISA Connector Pin Assignment IOCHCHK GND EMCS16 SD7 RESETDRV IOCS16 SD6 5V IRQ10 SD5 IRQ9 IRQ11 DRQ2 IRQ15 12V IRQ14 ENDXFR DACKO SDO 12 V DRQO IOCHRDY GND 2 DACK5 AEN SMEMW DRQ5 SMEMR DACK6 IOW DRQ6 IOR DACK7 DACK3 DRQ7 Dos D16 D17 MASTER DRQ1 REFRSH SYSCLK IRQ7 IRQ5 IRQ4 IRQ3 i Table A1 8 ISA Connector Pin Assignments A1 7 Appendix 2 Glossary of Terms B bidirectional parallel port An eight bit port that can be used for an input as well as an output device BIOS Basic Input Output System The on board firmware which communicates with the display keyboard printers and other peripheral devices bus A common pathway or channel between multiple devices consisting of one or more electrical conductors that transmit power or binary data to the various sections of a computer C cache A collection of the most recently accessed data or instructions CMOS Complementary Metal Oxide Semiconductor A technique of using PMOS and NMOS transistors in a complementary fashion where power is consumed only during the switching phase With the input statically high or low the power dissipa tion is essentially zero CMOS RAM Random
13. DB25 Connector 0 200000 eee 2 16 Table 2 32 J5 COMI1 Port sacnia wise soti veti wiu suom 2 17 Table 2 33 J6 COM2 Port 0 00 00 eee 2 18 Table 2 34 Serial Port Cable Wire List 2 19 Table 2 35 J9 Hard Drive LED Connector 2 20 Table 2 36 J14 Keyboard Connector 10 pin 2 20 Table 2 37 J20 Keyboard mini DIN 2 21 Table 2 38 J21 Mouse mini DIN 2 21 Table 2 39 J22 Reset Connector 00005 2 22 Table 2 40 J25 Speaker Connector 2 22 Table 2 41 J26 CPU Fan Power Connector 2 22 Table 2 42 J33 SVGA Connector 0 005 2 23 Table 3 1 Environmental Specifications 3 2 Table 4 1 Summary Screen Viewing Fields 4 10 Table 4 2 Energy Screen Entry Fields 4 13 Table 4 3 Clock Screen Entry Fields 4 15 Table 4 4 Keyboard Screen Entry Fields 4 17 Table of Contents List of Tables continued Table 4 5 Floppy Screen Entry Fields 4 19 Table 4 6 Fixed Disk Screen Entry Fields 4 22 Table 4 7 VL Bus IDE Screen Entry Fields 4 24 Table 4 8 Boot Sequence Screen Entry Fields 4 26 Table 4 9 Security Screen Entry Fields 4 28 Table 4 10 Speed Screen Entry Fields 4 29 Table 4 11 Cache Screen Entry Fields 4 31 Ta
14. Figure 4 11 Cache Screen Explanation The purpose of a cache is to optimize system performance by increasing throughput of the memory subsystem This is achieved through the use of a small quantity of Static RAM SRAM As data is fetched from slower main memory it is copied into the faster SRAM Subsequent references to this data are directed to the SRAM occurring more swiftly than is possible from main memory The main objective of this utility is to allow you to enable the cache s in your system As a general rule you will obtain best results by mak ing all memory present in your computer cacheable disabling any non cache blocks and selecting the most aggressive timing parameters Non cache blocks are used if a component or program in the system needs to have a non cached memory area The address of the non cached block can start in the beginning of the base memory all the way to the end of the available memory 4 30 Chapter 4 BIOS Entry Fields es ee rmen 486 CPU Cache The cache can be enabled or disabled in this field Enable Disable External Cache Indicates the amount of SRAM in the cache Usually BIOS detects this value automatically None Enable Disable SRAM Burst Read Indicates the number of wait states per cache read access Ows 2 1ws SRAM Write Cycle Indicates the number of wait states per cache write access Ows Tws Shadow RAM
15. Input Power with DX4 100 CPU and 4MB DRAM 5V 46A 12V 50mA 12V 50mA 256K or 512K standard write back cache 2MB to 128MB on board 36 bit DRAM SIMM Contains system amp video BIOS Real time clock backed by an on board lithium battery IDE amp floppy shrouded headers Bidirectional parallel port shrouded header Serial port 1 shrouded header Serial port 2 shrouded header Keyboard mini DIN on retaining bracket PS 2 Mouse mini DIN on retaining bracket Keyboard Ten pin header Speaker header Reset header Hard Drive LED header SVGA 15 pin connector on retaining bracket Two stage software programmable 3 1 Environmental Specifications SVGA Connector Configurable resolutions up to 1280 x 1024 256 colors non interlaced 32 bit wide DRAM interface with 1MB display memory 64 bit wide DRAM interface with 2MB display memory Up to 2MB display memory 16 8 million color capability 640 x 480 800 x 600 Backward compatible with VGA EGA CGA MDA 15 16 or 24 bit True Color Refresh rates up to 72Hz non interlaced Hardware bit BLT for Microsoft Windows Independent video and DRAM timing Environmental Specifications Temperature 0 to 550C 40 to 650C ae 5 to 95 40C 5 to 95 40C Humidity non condensing non condensing Table 3 1 Environmental Specifications Agency All I Bus CPU boards meet UL 1950 CSA 22 2 No 950 TUV and IEC 950 and FCC
16. Jeusequl sr zur ur 939S gt xd Aouenbai4 Faq ezr 10 9 uu09 qeu4 OsplA K 9 8S Spo 3dI ze yesoy is 40 99UUOD Ten orr eiqeuz Oul 3d eer J0 98uti0 4JOJ Q UUOD FCI ir uod leled 3 zr a37 aug prey aiqeug we 6f y98 1d PeOY FI sr Index Numerics 8042 82C802G Bus Drivers Cache Clock Calendar CMOS RAM Address Map Connectors DB25 Connector J2 IDE Connector J3 Floppy Connector J4 Parallel Port J5 COM 1 Port J6 COM 2 Port J9 Hard Drive LED Connector J14 Keyboard Connector 10 pin J20 Keyboard mini DIN J21 Mouse mini DIN J22 Reset Connector J25 Speaker Connector J26 CPU Fan Power Connector J33 SVGA Connector 1 8 1 7 1 8 1 9 1 5 3 1 3 1 Al 5 2 12 2 16 2 13 2 14 2 15 2 17 2 18 2 20 2 20 2 21 2 21 2 22 2 22 2 22 2 23 Idx 1 Index Counter Timer CPU Direct Memory Access DMA DMA Channel I O Addresses DMA Channel Assignments DMA Controller Register Functions DRAM Electrostatic Discharge ESD Environmental Specifications EPROM External Connections Floppy Disk Drive Interface Form Factor ISA Connector Pin Assignments IDE Controller Integrated Peripheral Controller IPC Interrupts 1 7 1 5 3 1 1 8 Al 2 Al 2 Al1 3 1 6 3 1 1 3 2 1 3 2 1 9 3 1 1 7 3 1 1 6 1 7 1 7 3 1 Al 4 Idx 2 Index Jumpers Board 2 6 J1 IDE IRQ Enable 2 6 J7 IDE Frequency Select 2 7 J8 IDE Read Prefetch Enable 2 7 J10 IDE Mode Sel
17. Part 15 Class A in I Bus enclosures Customer requested FCC VDE and CISPR Class B certification available 3 2 Chapter 4 BIOS The BIOS Setup Utility allows you to configure your CPU Central Processing Unit board to your system The BIOS or Basic Input Output System is the on board firmware that communicates with the display keyboard printers and other peripheral devices Starting and Exiting the BIOS Setup When you turn on your computer a test is conducted called the Power On Self Test or POST During this test the system checks for certain hardware configurations and compares them to the BIOS Setup Utility If at boot the system status does not match the system configuration stored in CMOS you will be prompted to start the BIOS Setup Utility This occurs if the Initialization Errors Halt prompt is set to Active in the Boot Sequence setup screen If set to Inactive the system con tinues to boot To Start the BIOS Setup e During a cold boot press lt Esc gt while the memory size is scrolling on the screen e While in DOS press lt Ctrl gt lt Alt gt lt Esc gt When you exit the BIOS the system automatically reboots To Exit the BIOS Setup and boot the computer e While in a utility screen move the cursor to the menu line at the top of any screen and press lt F10 gt All configuration changes edited in the various screens are recorded in CMOS memory at this time If however you turn o
18. amp 8 Enable P24T Write Back 7 0 0 8 No Jumpers Enable P24T Write Through Table 2 3 J24 486SL P24T Write J27 Clock Frequency J27 contains jumper settings for the slow clock frequency at 8MHz or 16MHz for the DX4 CPU 3 2 16MHz DX4 Table 2 4 J27 Clock Frequency J29 CPU Select Jumpers must be set on J29 if an Intel AMD or Cyrix CPU is present Table 2 5 J29 CPU Select 2 3 CPU Jumpers e J34 CPU Functions Enable J34 contains a jumper setting to activate the warm reset for a Cyrix CPU It also contains a setting if a 486SL CPU with power man agement feature is present Two settings enable the write back and write through cache for the P24D CPU with special write back cache 5 3 1 Activat ix CP ctivate Cyrix CPU ooe 486SL CPU OOO Enable P24D write back cache 6 4 2 Enable P24D write through cache Table 2 6 J34 CPU Functions Enable e J35 P24T Clock Stop J35 contains a jumper setting if a P24T CPU is present Jumpers are also installed on J35 to select bit 0 or bit 1 of the green port to stop the clock 5 3 1 CPUis other than P24T P24T O00 Bit 0 to stop clock Bit 1 to stop clock ane Table 2 7 J35 P24T Clock Stop e J36 DX SX Select Set jumpers on J36 for 486DX or 486SX operation 4 3 2 1 1 amp 2 384 486DX Operation 283 486SX Operation Table 2 8 J36 DX SX Select Chapter 2 Jumpers and Connectors J37
19. and AT Bus timing are managed here 4 35 Setup Screens Pree secon Paani MEMORY TIMING Wait States Specified in terms of wait states 1 1 0 2 0ws Read or ns rating nanosecond 2 60 100ns Numerically lower ws values and ns values cause faster access giving better performance Common ns values range from 60 to 100ns and common ws values are 1 2 Wait States Specified in terms of wait states O 1ws Write or ns rating nanosecond See 2 60 100ns above A20 Gate General system failure during Normal Control Protected Mode programs e g 2 Always On Windows OS 2 or EMS drivers may be correctable by keeping the A20 Gate Enabled To do so set this field to Always On Set this field to Normal for standard A20 handling MEMORY REFRESH Method Standard refresh synchronizes Standard the AT Bus memory refresh and Hidden the on board memory refresh Hidden refresh decouples these two to refresh them independently Specified in terms of ys rating microsecond AT BUS TIMING Wait States Many AT Bus devices especially Normal IDE drives require an extra delay 2 Extra between back to back cycles when running with an increased AT Bus clock or in a high speed system I O Recovery A delay state between back to Normal back I O cycles Extra AT Bus Clock The normal dropout rate for 8 3 MHz peripherals is 11 MHz Itis 11 1 MHz possible
20. be installed unless it is disabled Primary IDE 2 Secondary IDE Enable IDE port O00 Disable IDE port 6 4 2 Table 2 15 J11 IDE Drive Select e J12 Reserved no jumper e J13 Floppy Select Select the density of the floppy disk drive enabled in the BIOS 5 3 1 O O OOO 6 4 2 Table 2 16 J13 Floppy Select e J15 Cache Select Place the jumper on the designated pins for the amount of cache on your CPU board no jumpers ile ol2 5 amp 6 3 0 O 4 3 amp 4 5 amp 6 5 O Ofe 1 amp 2 384 5 amp 6 Table 2 17 J15 Cache Select 2 8 Chapter 2 Jumpers and Connectors e J16 SRAM Select J16 contains jumper settings for single bank SRAMs or double bank SRAM s in the cache 1 amp 2 Single Bank 4 283 Double Bank 8 3 Table 2 18 J16 SRAM Select e J17 CMOS Clear Battery Enable J17 contains jumper settings for clearing the system information stored in CMOS and enabling the on board battery Table 2 19 J17 CMOS Clear Battery Enable e J18 Mouse IRQ Enable Placing a jumper on J18 enables IRQ12 for the mouse If no jumper is placed on J18 the mouse is disabled and IRQ12 is avail able for other use roson neon IRQ12 Available Table 2 20 J18 Mouse IRQ Enable 2 9 Board Jumpers e J19 Security Password Enable Installing a jumper on pins 1 and 2 of J19 enables the security pass word option in the BIOS Setup Utility Wit
21. depending upon the CPU Event Local corresponds to the Monitoring keyboard input Idle Video State When the system goes to slow speed operation the screen blanks if this is set to Off Table 4 2 Energy Screen Entry Fields 4 13 Setup Screens e Clock Screen Summary Energy Keyboard Floppy Fixed Disk More United States 12 16 19p 11 1 96 Disable F10 to Record and Exit Home End Moves Cursor Figure 4 3 Clock Screen Explanation The time and date are maintained in the real time clock RTC It s bat tery powered when the computer is shut off The RTC needs to be set with the initial time date Adjustments are required periodically for continued accuracy Variations in voltage power supply or battery and other technical issues make it impractical to tune the RTC with the same degree of precision as a dedicated timepiece To change the time or date move the cursor into the field and press lt Enter gt Enter the new data and press lt Enter gt again or lt Esc gt 4 14 Chapter 4 BIOS Entry Fields CO e oe Display Format Select the display format for time 1 U S and date 2 International Time Press lt Enter gt and move the 1 12hr am pm cursor under the number to 2 24hr change and enter 0 9 or or ni Press lt Enter gt and move the mm dd yyyy cursor under the number to dd mm yyyy change and enter 0 9 or or Mom Daylight The RTC ca
22. of Terms N ns nano seconds 1 x 10 seconds There are one billion nanoseconds in one second P page mode The ability to read a whole line page of memory to reduce access time parity A way to detect corrupted data in DRAM parallel port An eight bit port usually used for connecting a printer PCI Peripheral Component Interconnect Local bus for PCs that provides a high speed data path between the CPU and peripher als video disk network etc The PCI bus coexists in the PC with the ISA or EISA bus ISA and EISA boards still plug into an ISA or EISA slot while high speed PCI controllers plug into a PCI slot The PCI bus runs at 33MHz supports 32 bit and 64 bit data paths and bus mastering The first PCs with PCI buses became available toward the end of 1993 port Ports are used to connect peripheral devices such as external drives and printers to your computer R RAM Random Access Memory The memory used to execute applications while your computer is turned ON When you turn your computer OFF all data stored in RAM is lost real time clock RTC A CMOS counter used to maintain local time retaining bracket The bracket on the end of the board that attaches to the back of the chassis and contains connectors usually key board mouse serial port and or parallel port A2 3 Appendix 2 Glossary of Terms S serial port A two channel port one channel used for In transmis sions and o
23. selection video enabled or disabled must be the same as jumper J30 Video Enabled i Video Disabled Table 2 26 J39 Video Enable Disable Connectors The following connectors can be located in Figure 1 1 ORCA CPU Board Jumpers Connectors and Components on page 1 4 and on the fold out illustration at the back of this manual Description IDE Connector Floppy Connector Parallel Port COM1 Port COM2 Port Hard Drive LED Connector Keyboard Connector 10 pin Keyboard mini DIN Mouse mini DIN Reset Connector Speaker Connector CPU Fan Power Connector SVGA Connector Table 2 27 Connectors Chapter 2 Jumpers and Connectors e J2 IDE Connector Indicates connector key position 2 13 Connectors e J3 Floppy Connector Table 2 29 J3 Floppy Connector The remainder of the odd numbered pins are GND Chapter 2 Jumpers and Connectors e J4 Parallel Port Strobe Fn a o oe a is E C 21 2 15 Connectors e DB25 Connector The optional parallel port cable connects to J4 on the CPU board and contains a DB25 connector which attaches to the I O panel on the back of the chassis Strobe Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 ACK1 O O O O O O O O O O O O Busy e O O O O O O
24. to 128KB while the eight bit DMA channels transfer up to 64KB e IDE Hard Disk Interface The Orca CPU board provides a Local Bus Enhanced Integrated Drive Electronics EIDE interface for up to two IDE hard disk dri ves through the header at J2 J2 accepts a forty pin IDE connector e Keyboard Interface The Orca CPU board uses the 8042 keyboard controller A six pin mini DIN connector is provided at J20 A ten pin header is also provided at J14 A keyboard adapter cable is available for key boards with a five pin DIN connector Contact I Bus for ordering information e Real time Clock Calendar The Orca CPU board has a real time clock calendar backed by an on board battery It has 114 bytes of CMOS RAM included with the clock The battery has a two year life expectancy and is field replaceable e Reset An external reset can be attached to the Orca CPU board through the connector at J22 e Speaker The Orca CPU board provides an on board speaker and the capabil ity of adding an external speaker at connector J25 Chapter 1 Introduction EPROM The 27C010 EPROM contains the BIOS for the system The sys tem BIOS is mapped from F0000h to FFFFFh Bus Drivers The Orca CPU board uses buffered bus drivers which are capable of driving nineteen additional expansion cards Watchdog Timer To operate the watchdog timer on the Orca CPU board several pro gramming steps are required After booting the system perform a b
25. to experiment a little Unshadowed segments display Vacant if no adapter ROM is present there Unshadowed segments containing a ROM will indicate ROM n where n is a number from 0 through 9 Each ROM is assigned a unique number If a single ROM spans several segments then the same ROM n will appear multiple times ROM 0 is always the system BIOS 4 32 Chapter 4 BIOS Shadow RAM is obtained from a gap in the otherwise contiguous mem ory space of the computer The 384K region between the 640K and 1MB boundaries is occupied not by memory but instead by ROMs video memory and possibly other system level devices The memory that should appear there is simply inaccessible and unused One way to make use of this lost memory is to activate it as Shadow RAM Certain designs can also remap a portion of this 384K into the Extended Memory pool provided it is not already enabled as Shadow RAM In most designs with this capability remap will be prevented if any Shadow segment is enabled in the D000 through E000 regions View the Extended Memory field in the Summary screen to see how or if a particular Shadow configuration affects your computer s memory The critical runtime programming in the BIOS section cannot be assigned to UMB space The UTILS section should not be assigned to UMBs either since the speed and cache hotkey functions lt Ctr gt l lt Alt gt lt gt and lt Ctrl gt lt Alt gt lt gt are contained in this sec ti
26. to settings for the CPU installed on your CPU board Board Jumpers listed in Table 2 10 pertain to functions of the CPU board and its peripherals CAUTION Components on this board are sensitive to damage from Electrostatic Discharge ESD Handling of this board should ONLY be done by a properly trained technician in an approved ESD work area 2 1 CPU Jumpers The following jumpers are factory set for the CPU installed on your CPU board If you upgrade to another CPU or reconfigure your system you may need to reset some of the jumpers sumer __beseipion noop a Dena main fe es eea fe sr orons fe ss ereas fs Table 2 1 CPU Jumpers e J23 DX4 Internal Multiplier J23 contains a jumper setting if a Cyrix CPU is present Otherwise the jumper settings pertain to the internal multiplier of the DX4 Position Function 531 Cyrix CPU olen DX4 2 5X 000 DX4 2X 6 4 2 DX4 3X Table 2 2 J23 DX4 Internal Multiplier Chapter 2 Jumpers and Connectors J24 486SL P24T Write Two jumpers must be placed on J24 if your CPU board contains a 486SL CPU with power management feature Or if you have a P24T CPU installed you can select burst writes write back or write through cache Removing the jumper from pins 7 and 8 enables the write through cache for a P24T CPU 182 3 amp 4 486SL CPU 1j e 0oj2 4 5 amp 6 Enable P24T Burst Writes 3 O O 5 O OJ6 7
27. 4MB 1MB x 36 4MB 1MB x 36 24MB _ 4MB 1MBx36 4MB 1MBx36 8MB 2MBx36 8MB 2MB x 36 40MB _ 4MB 1MBx36 4MB 1MBx36 16MB 4MBx36 16MB 4MB x 36 72MB 4MB 1MBx36 4MB iMBx36 32MB 8MBx36 32MB 8MB x 36 32MB 8MB 2MB x 36 8MB 2MB x 36 8MB 2MB x 36 8MB 2MB x 36 48MB 8MB 2MB x 36 8MB 2MB x 36 16MB 4MB x 36 16MB 4MB x 36 80MB 8MB 2MB x 36 8MB 2MB x 36 32MB 8MB x 36 32MB 8MB x 36 64MB 16MB 4MBx36 16MB 4MBx36 16MB 4MBx36 16MB 4MB x 36 96MB 16MB 4MBx36 16MB 4MBx36 32MB 8MBx36 32MB 8MB x 36 128MB 32MB 8MBx36 32MB 8MBx36 32MB 8MBx36 32MB 8MB x 36 Table 1 1 DRAM Configurations For other possible configurations contact I Bus e Multifunction Controller XIO The multifunction controller provides two high speed serial ports one bidirectional parallel port and a floppy disk controller IDE Controller The IDE controller is supported by VESA 32 bit local bus with four level read prefetch e Serial I O Interface There are two RS232 compatible serial communication ports with 16550 type UARTS a primary serial port at JS and a secondary serial port at J6 1 6 Chapter 1 Introduction Parallel I O Interface The Orca CPU board provides a parallel I O interface at J4 While it is conventionally a printer port it can be reconfigured by software to be a bidirectional parallel port Contac
28. Control Memory Refresh Period AT BUS Timing TO Recovery Parallel Port Floppy Setup Screens This section describes each setup screen in the Orca BIOS Setup Utility Screens are identified in the menu line as e Summary e Ports Energy e Security e Clock Speed Keyboard e Cache Floppy Shadow RAM e Fixed Disk e Chipset VL Bus IDE 37C665 lt Boot Sequence In this section each utility is represented by e Screen Illustration e Explanation e Entry Fields Screen Illustration The screens presented in this manual reflect the same format as your screens but they do not contain parameters Explanation The Explanation following each screen illustration describes the utility and the available choices Entry Fields Each entry field in the body of the screen is described and all available choices or parameters are listed in table form 4 8 Chapter 4 BIOS Summary Screen Summary Energy Clock Keyboard CPU Code Cache CPU Data Cache External Cache Memory Memory Memory Memory Floppy Fixed Disk More Chipset BIOS ID BIOS Date Keyboard NumLock PS2 Mouse Video Primary Video Secondary F10 to Record and Exit Home End Moves Cursor Figure 4 1 Summary Screen Explanation The Summary Screen contains information about the hardware on your system No user entry is allowed This screen allows you to view system information and indicates w
29. Cyrix CPU Select Set jumpers on J37 if your CPU board contains a Cyrix CPU 1 amp 2 384 Cyrix CPU OFF CPU Other than Cyrix Table 2 9 J37 Cyrix CPU Select 2 5 Board Jumpers The following jumpers control functions of the CPU board and its peripherals IDE IRQ Enable IDE Frequency Select Video Enable Disable 2 Table 2 10 Board Jumpers e J1 IDE IRQ Enable Placing a jumper on J1 enables IRQ14 for the IDE If no jumper is placed on J1 IRQ14 is available for other use Enable IRQ14 1 IRQ14 Available fd 2 2 6 Chapter 2 Jumpers and Connectors J7 IDE Frequency Select This jumper setting must match the frequency of the CPU installed on your CPU board 486 3 amp 5 3 amp 5 2 amp 4 1 amp 3 4 amp 6 1 amp 3 2 amp 4 Table 2 12 J7 IDE Frequency Select e J8 IDE Read Prefetch Enable Read prefetch allows the controller to access data off the disk in anticipation of its use Note If WindowsNT is being used jumpers must be placed on pins 2 and 3 for proper operation 1 amp 2 Enable IDE Read Prefetch 283 Disable IDE Read Prefetch M Table 2 13 J8 IDE Read Prefetch Enable e J10 IDE Mode Select Select the appropriate disk drive cycle time by placing jumpers on the designated pins Table 2 14 J10 IDE Mode Select 2 7 Board Jumpers e J11 IDE Drive Select Select the address for the IDE port Either one or the other must
30. H LHHLHLH Keyboard Controller Failure 20 14H 24 18H 25 19H LHLHHLH Memory Parity Error 20 14H Table 4 17 Beep Codes and Error Messages Beep Codes L low tone and H high tone 4 42 Chapter 4 BIOS Port 80H 24 18H 25 19H 20 14H 24 18H 25 19H 18 12H 21 15H 23 17H 23 17H 23 17H 26 1AH 26 1AH 30 1EH 31 1FH 33 21H 41 29H LHHHHLH None None LHLLLHH LHHLLHH None LHLHLHH None None V O Channel Error RAM Pattern Test Failed at XXXX Parity Circuit Failure in Bank XXXX Data Bus Test Failed Address XXXX Address Line Test Failed at XXXX Block Access Read Failure at Address XXXX Block Access Read Write Failure Address XXXX Banks Decode to Same Loc XXXX amp YYYY Keyboard Error Stuck Key Keyboard Failure or no Keyboard Present A20 Test Failure Due to 8042 Timeout A20 Gate Stuck in Disabled State A20 0 A20 Gate Stuck in Asserted State A20 Follows CPU Real Time Clock RTC is Not Updating Real Time Clock RTC Settings are Invalid Diskette CMOS Configuration is Invalid Diskette Controller Failure Diskette Drive A Failure Diskette Drive B Failure Fixed Disk CMOS Configuration is Invalid Fixed Disk C 80 Failure Fixed Disk D 81 Failure Please Wait for Fixed Disk to Spin Up 32 Diskette Configuration Change20H None Fixed Disk Configuration Chg Serial Port Configuration Change Parallel Port Configuration Change Video Configuration Change Memory Confi
31. I Bus Refer to the Limited Warranty in the back of this manual for further instructions 1 3 Features Keyboard Connector J14 J6 COM2 Port J5 COM1 Port J39 Video Enable Disable J4 Parallel Port J13 Floppy Select J12 Reserved J3 Floppy Connector J11 IDE Drive Select J10 IDE Mode Select J9 Hard Drive LED Connector J8 IDE Read Prefeti Enable J7 IDE Frequenc Select J2 IDE Connector J1 IDE IRQ Enable J23 DX4 Internal Multiplier J22 Reset Connector J25 Speaker Connector J20 J18 Keyboard mini DIN ID OF eI GD Ate a he 1 iy O EPA m Les eS aL z 3 Mouse IRQ Enable J21 Mouse mini DIN J33 SVGA Connector J19 Security Password Enable J17 Clear CMOS Battery Enable J32 Select DMA Channel for LPT1 J31 Video IRQ Enable J30 Video Enable Disable y co F ss o d J26 CPU Fan Power Connector J38 oo Reserved J16 Sel SRAM Select Soj A J29 CPU Select J28 Processor Speed J27 Clock Frequency J15 Cache Select of klos Blon Bos Ei o2 o2 fos fos J24 5 s es ge 486SL P24T Writ SM1 22 gs 25 rite ge ee e ell 33 SMe 55 83 a J37 3 gs 3 3 Cyrix CPU Select ge ge e ee ae 2SM et CPU is o2 o2 5 J36 go SM4 DX SX Select J35 P24T Clock Stop J34 CPU Functions Enable Figure 1 1 Orca CPU Board Jumpers Connectors and Components
32. IOS e Boot Sequence Screen More VL Bus IDE Boot Seq Ports Security Speed More Operating System Boot Sequence Memory Priming Cold Boot Delay Initialization Error Halts Cold Boot Key Sequence Boot to Screen Prompt Boot to Setup Utility Warm Boot Key Sequence CTRL ALT DEL Standard Warmup Restart CNTRL ALT Boot to Screen Prompt CNTRL ALT ESC Boot to Setup Utility F10 to Record and Exit Home End Moves Cursor Figure 4 8 Boot Sequence Screen Explanation This utility allows you to configure your system s start up functions Boot Sequence The following four choices are provided e A Ist C 2nd This is an industry standard boot order where Drive C is booted only when drive A is empty e C Ist A 2nd Most installations use drive C as the primary boot device This eliminates the opportunity for a virus to enter your computer when a floppy is unintentionally left in the drive e Auto Search instructs the system to first search the floppy drives then the fixed disk drives to find a bootable system disk If nothing is found it displays a non system disk error message When it finds a bootable drive it automatically makes it the primary boot device until you program it differently e Screen Prompt instructs the BIOS to pause and display a short menu that requests your selection of the boot drive A or C 4 25 Setup Screens NOTE A prompted boot can also be invoked by pressing lt Ctrl gt
33. NBENCH 3 1 when using a DX4 100 CPU with 2MB display memory This provides a dramatic improvement in performance over ISA video cards Configurable resolutions up to 1280 x 1024 256 colors non interlaced 32 bit wide DRAM interface with IMB 64 bit wide DRAM interface with 2MB Up to 2MB display memory 16 8 million color capability 640 x 480 800 x 600 Backward compatible with VGA EGA CGA MDA 15 16 or 24 bit True Color Refresh rates up to 72Hz non interlaced Hardware bit BLT for Microsoft Windows Independent video and DRAM timing Chapter 2 Jumpers and Connectors This chapter describes the jumpers and connectors on the Orca CPU board Jumpers and connectors are identified by the label shown beside them on the board e g J36 followed by the description e g DX SX Selection A table shows the jumper settings or connector pin outs for each jumper and connector Illustrations of jumpers and con nectors are shown from the component side of the board Pin 1 is iden tified by the black pin All of the jumpers and connectors are shown on the illustration on page 1 4 Figure 1 1 Orca CPU Board Jumpers Connectors and Components and on the fold out illustration on page A3 1 Pin 1 can be identified on the solder side of the board by the square pad in a connector or jumper For clarity in this manual jumpers are divided into two types CPU Jumpers and Board Jumpers e CPU Jumpers listed in Table 2 1 pertain
34. O O O O O O Paper Empty SLCT AutoFeed Error Init SLCT IN GND 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 Table 2 31 DB25 Connector 2 16 Chapter 2 Jumpers and Connectors J5 COM1 Port The primary serial port is a ten pin header located at J5 You can terminate the primary serial port in a DB9 connector by obtaining the optional serial port cable from I Bus A wire list is also provid ed on page 2 19 if you want to make your own cable Another optional cable from I Bus contains a retaining bracket with a DB9 and a DB25 connector terminating in a ten pin and twenty six pin header respectively Table 2 32 J5 COM1 Port 2 17 Connectors e J6 COM2 Port The secondary serial port is a ten pin header located at J6 You can terminate the secondary serial port in a DB9 connector by obtaining the optional serial port cable from I Bus A wire list is also provid ed on page 2 19 if you want to make your own cable Another optional cable from I Bus contains a retaining bracket with a DB9 and a DB25 connector terminating in a ten pin and twenty six pin header respectively Table 2 33 J6 COM2 Port 2 18 Chapter 2 Jumpers and Connectors Serial Port Cable Wire List The following wire list is provided for users who want to make a cable that connects to a serial port connector J5 or J6 and termi nates with either a DB9 or DB25 RS232 connector For the
35. Table of Contents Chapter 1 Introduction About this manual o i ssi aiai aa 0 0 0 0 0 0 ee eee 1 2 Preparing the board 0 eee eee eee 1 3 Features nante ken ea eee ot ie ee x ee esl to es es Gales ee tee 1 5 Chapter 2 Jumpers and Connectors CPU Jumpers yer 2 eee Sere es be eee ce EEEE ee eae be 2 2 Board Jumpers o c 4 5 ecc os e aces ele ae a aya wots An EA AE uk ae 2 6 CONMECIOLS wise cee cease Beas cage cee ia hel E let ed anette aig 2 12 Chapter 3 Specifications System Components 0 0 eee ee eee eee 3 1 Environmental Specifications 0000 3 2 Chapter 4 BIOS Starting and Exiting the BIOS Setup 4 1 Operating the BIOS Setup 004 4 2 Your System s Parameters 0 0 00000 4 4 Setlip Screens nen crtere addenda ade E e 4 8 Orca Post Codes cocco 0 eee ee eee 4 39 Diagnostic Port 80h Post Codes 0 4 4 Beep Codes and Error Messages 55 4 42 Fixed Disk Parameters 0 0 0 0 4 44 Memory Map 0 eee eee 4 45 ORA oae ben tar ett E e E ele eae eB lone ok 4 46 Table of Contents Appendix 1 Technical Reference Standard PC AT I O Map DMA Channel Page Register and I O Addresses DMA Channel Assignments DMA Controller Register Functions inemupis gt seors aa eaaa avatars gi erste e e ae CMOS RAM Address Map
36. Total Chipset BIOS ID BIOS Date Energy IDE Drive Timer System Activity Clock Display Format Time Floppy 0 Floppy 1 Floppy 2 Floppy 3 Fixed 80 Fixed 81 Keyboard NumLock PS2 Mouse Video Primary Video Secondary Event Monitoring Idle Video State Date Daylight Savings 4 4 Chapter 4 BIOS Keyboard NumLock State at Bootup Keyboard Typematic Speed Delay Before Keys Repeat Floppy Floppy 0 Floppy 2 Floppy 1 Floppy 3 Step Rate Fixed Disk 80 Fixed Disk 81 Size Size Type yp Type Cylinders Cylinders Heads Heads Precomp Precomp Landing Landing Sectors Sectors Translate Translate Xfer Mode Xfer Mode Anti Virus 4 5 Your System s Parameters VL Bus IDE Drive 80 C Selectable Rate Drive 81 D External Jumper VL Bus LRDY Boot Sequence Operating System Boot Sequence Memory Priming Cold Boot Delay Initialization Error Halts Ports COM 1 L LPT1 COM 2 LPT 2 COM 3 LPT 3 COM 4 LPT 4 Security Security Speed System Speed Cache 486 CPU Cache SRAM Write Cycle External Cache Shadow RAM SRAM Burst Read Cache Size Chapter 4 BIOS Shadow RAM F000 System E000 Adapter DCO00 Adapter D800 Adapter D400 Adapter Chipset Wait States Read Wait States Write Method Wait States AT Bus Clock 37C665 Primary Serial Secondary Serial D000 Adapter CCO00 Adapter C800 Adapter C400 Video C000 Video Memory Timing A20 Gate
37. able fields A few fields require alphanumeric entry When all changes have been made to the entry fields press lt Esc gt to return the cursor to the menu line The bottom line changes back to its previous condition When the cursor is in the menu line you can press lt F10 gt to save your changes and reboot the computer Chapter 4 BIOS e Keystrokes The following keys are available while the cursor is on the menu line Keystroke Right Left Arrow Space BackSpace Tab Shift Tab Home End DownArrow Enter PgDn F10 Movement right and left movement right and left movement right and left movement leftmost and rightmost entry move down into edit window record and exit Setup The following keys are generally available within the body Keystroke Arrows Space BackSpace Plus Minus AlphaNumeric Enter Esc Esc PgUp Movement up down left right scroll choices in field scroll choices in field letters and numbers begin end abort mode or A N entry exit current window go back to menu Your System s Parameters Once you have set your system s parameters record the settings below If for any reason you should lose the parameter settings on your system e g the CMOS is reset you will then be able to easily re enter them Summary CPU Type CPU Rev CPU MHz PLL Ratio CPU Code Cache CPU Data Cache External Cache Memory Base Memory System Memory Extended Memory
38. and Off selects cursor control Parameters Keyboard Typematic Speed Select the default rate of 10cps or select from 2 cps to 30 cps Default 2 0 30 0 cps Delay Before Keys Repeat Select one of four settings between 0 25 to 1 0 seconds that comfortably allows you to release the keys before they begin to repeat Note This field will display Default and cannot be changed ifthe Keyboard Typematic Speed field is set to Default Default 0 25 1 0 sec Table 4 4 Keyboard Screen Entry Fields 4 17 Setup Screens e Floppy Screen Summary Energy Clock Keyboard Floppy Fixed Disk More Floppy Drive Configuration F10 to Record and Exit Home End Moves Cursor Figure 4 5 Floppy Screen Explanation Your system can have as many as four floppy disk drives referred to as Floppy 0 through Floppy 3 corresponding to A B etc respectively depending on your operating system Each floppy drive in your system must be identified as one of the following e 5 360K low density e 3 fi 720K low density e 5 1 2MB high density e 3fi 1 4MB high density e 3fi 2 8MB extra density The BIOS will support 2 88MB floppy drives or A second controller card or Four floppy drives 4 18 Chapter 4 BIOS Step Rate This is the radial track to track speed of the recording heads Entry Fields Ore en O eee Floppy 0 3 Indicate the drives present by 1 n a specifying
39. ary of Terms contains definitions of terms used in this manual as well as terms that refer to items discussed Appendix 3 Illustration provides a convenient fold out illustration of the Orca CPU board Appendix 4 BIOS explains the setup utility and how to use it Chapter 1 Introduction Index provides easy access to page numbers of items discussed Preparing the board Unpacking your CPU board The Orca CPU board is shipped in a sealed anti static shielded bag Open the bag at a static free workstation while observing proper Electrostatic Discharge ESD practices When not installed in a computer chassis this board must be sealed in an ESD approved shielded bag This board must be shipped in a sealed ESD approved shielded bag and protected with anti static packaging material e g bubble wrap I Bus reserves the right to refuse warranty service on units not properly packaged to protect against ESD damage CAUTION Components on this board are sensitive to damage from Electrostatic Discharge ESD Handling of this board should ONLY be done by a properly trained technician in an approved ESD work area Packaged with the Orca CPU board are e an Orca Passive Backplane CPU Board User Manual e Optional memory e a Keyboard adapter cable e Optional cables If any of the items have been damaged in shipping notify the transit company and initiate an insurance claim If any items are missing contact
40. ble 4 12 Shadow RAM Screen Entry Fields 4 33 Table 4 13 Chipset Screen Entry Fields 4 36 Table 4 14 37C665 Screen Entry Fields 4 38 Table 4 15 Orca Post Codes 020 0000 eee 4 39 Table 4 16 Diagnostic Port 80h Post Codes 4 41 Table 4 17 Beep Codes and Error Messages 4 42 Table 4 18 Fixed Disk Parameters 4 44 Table 4 19 Memory Map 0 000 eee 4 45 Table Al 1 Standard PC AT I O Map Al 1 Table Al 2 DMA Channel Page Register and I O Add A1 2 Table Al 3 DMA Channel Assignments Al 2 Table Al 4 DMA Controller Register Functions Al1 3 Table Al 5 Interrupts 0 0 0 2 00 008s Al 4 Table Al 6 CMOS RAM Address Map Al 5 Table A1 7 Real Time Clock Information A1 6 Table A1 8 ISA Connector Pin Assignments Al 7 Chapter 1 Introduction Welcome to the I Bus family of passive backplane CPU boards This manual contains the information necessary to configure your CPU board to your specific needs The Orca passive backplane CPU board is IBM PC AT compatible utilizing 5V or 3 3V 486 compatible processors This chapter is divided into three sections About this manual explains how this manual is laid out and what you can expect to find in it Preparing the board describes the procedure for unpacking the Orca CPU board an
41. d preparing it for use in your system Features of the board provides a brief overview of the major components of the Orca CPU board accompanied by an illustration of the board showing its jumpers connectors and components For convenient reference a fold out version of this illustration is provided at the back of this manual 1 1 About this manual The first three chapters of this manual pertain to your specific CPU board The appendices contain technical reference material a glossary of terms a fold out illustration of the board and the BIOS setup utility followed by an index Chapter 1 Introduction introduces you to this manual and to the Orca CPU board Chapter 2 Jumpers and Connectors describes the jumpers and connectors on the Orca CPU board First each jumper is described A table shows on which pins to place the jumper for your specific configuration and an illustration of the jumper shows the pin locations Then each connector is described A table shows the pin out descriptions and an illustration shows the pin locations for each connector Chapter 3 Specifications provides the component data and environmental characteristics of the Orca CPU board Appendix 1 Technical Reference provides additional information that can help you configure your CPU board and attach external peripheral devices These include TVO Maps I O Channels Interrupts and Address Maps and ISA pin assignments Appendix 2 Gloss
42. ect 2 7 J11 IDE Drive Select 2 8 J12 Reserved 2 8 J13 Floppy Select 2 8 J15 Cache Select 2 8 J16 SRAM Select 2 9 J17 CMOS Clear Battery Enable 2 9 J18 Mouse IRQ Enable 2 9 J19 Security Password Enable 2 10 J28 Processor Speed 2 10 J30 Video Enable Disable 2 10 J31 Video IRQ Enable 2 11 J32 DMA Channel for LPT1 2 11 J39 Video Enable Disable 2 11 Jumpers CPU 2 2 J23 DX4 Internal Multiplier 2 2 J24 486SL P24T Write 2 3 J27 Clock Frequency 2 3 J29 CPU Select 2 3 J34 CPU Functions Enable 2 4 Idx 3 Index J35 P24T Clock Stop J36 DX SX Select J37 Cyrix CPU Select Keyboard interface Multifunction Controller XIO Parallel I O Interface Pentium upgrade Power Requirements printer port Programmable Interrupt Controller Real Time Clock Information Real time Clock Calendar Reset RS232 2 4 2 4 2 5 1 8 1 6 1 7 1 5 3 1 1 7 1 7 Idx 4 Index S Screens 37C665 Boot Sequence Screen Cache Screen Chipset Screen Clock Screen Energy Screen Fixed Disk Screen Floppy Screen Keyboard Screen Security Screen Shadow RAM Screen Speed Screen Summary Screen VL Bus IDE Screen Serial I O Interface Serial Port Cable Wire List Speaker Enabling on board speaker Standard PC AT I O Map SVGA System ROM 4 37 4 25 4 30 4 35 4 14 4 13 4 20 4 18 4 16 4 27 4 32 4 29 4 9 4 23 1 6 2 19 1 8 2 22 A1l 1 1 10 2 23 3 1 Idx 5 Index Unpacking your CPU boa
43. em Then find an available appropriate address to set the SCSI BIOS to YOU MUST DISABLE THE ON BOARD IDE CON TROLLER IF YOU WANT THE SCSI CONTROLLER TO BE THE BOOT DEVICE Q8 Can I use an ESDI controller and where should I set the address Al You can use an ESDI controller The address should be set for the primary controller in the system Then find an available appropriate address to set the ESDI BIOS to A2 YOU MUST DISABLE THE ON BOARD IDE CON TROLLER IF YOU WANT THE ESDI CON TROLLER TO BE THE BOOT DEVICE Q9 What preventive maintenance steps can I take A Ensure all fans in the chassis are working Clean the filter with warm water or compressed air Replace brittle or torn filters Allow ample air circulation behind the chassis Keep all cables free from tangles CAUTION Electrostatic Discharge ESD may damage memory chips pro grammed devices and other electrical components ESD can be prevented by wearing a wrist strap attached to a ground post on a static mat Grounding can also occur by touching a chassis that is plugged into a power outlet 4 47 Appendix 1 Technical Reference Standard PC AT I O Map Address Hex 000 01F DMA Controller 020 03F Interrupt Controller 1 040 O5F Timer 060 O6F Keyboard Controller 070 O7F Real Time Clock non maskable interrupt 080 O9F OAO OBF DMA Page Registers Interrupt Controller 2 0CO ODF DMA Controller 2 OF8 OFF Math Co proce
44. emory at and below the 640K boundary found to be in working order auto sensed during POST A portion of memory typically 384K reserved for special uses Some may be allocated to Shadow RAM and the remainder might automatically be remapped to the Extended Memory pool This field shows the amount of memory retained for system use Table 4 1 Summary Screen Viewing Fields 4 10 Chapter 4 BIOS ee ae e Memory Extended The amount of Extended Memory above the 1MB boundary found to be in working order Parameters Memory Total The total amount of memory installed in the system It is the sum of the three preceding quantities Base System Extended Total auto sensed during POST Serial ports auto sensed by the BIOS n a Port address es Parallel ports auto sensed by the BIOS n a Port address es Chipset Permits optional fine tuning of certain chipset parameters Opti 802G BIOS ID BIOS Type Optl9Cl BIOS Date Date BIOS was built mm dd yy Floppy 0 3 The floppy drives configured in the system and usually named A or B auto sensed during POST None 5 360K 30 720K 5 1 2MB 30 1 4MB 30 2 8MB Fixed 80 81 The configured Size and Type for Fixed Disk Drives 80 and 81 usually named C and D respectively auto sensed during POST None Size type Keyboard Keyboard ty
45. est master slave 8237s Base 64K memory test Pattern test master slave 8259 mask regs 8259 IRQ tests 8254 channel0 test and initialization 8254 channel2 toggle test RTC tests inits Init REGB Hook 02 OEM specific Video Initialization CMOS Checksum test Sign on message Size Test base memory low 64K already done Perform 2nd try KB init Hook 03 OEM specific Size Test cache Test A20 gate Size Test extended memory Hook 04 and Size Test system memory special OEM memory Test RTC Update In Progress and validate time Serial port determination Parallel port determination Coprocessor determination initialization Floppy controller test determination Fixed Disk controller test determination Rigorous CMOS parameter validation Front Panel lock check Set NumLock Hook 05 OEM specific Set typematic rate Hook 06 OEM specific Floppy subsystem initialization Fixed subsystem initialization ACK errors Disable A20 gate ACK errors Enable parity checking and NMI Install E000 ROM ACK errors Hook 07 OEM specific Login EMS if built in Pass control to INT19 boot disk Table 4 16 Diagnostic Port 80h Post Codes 4 41 Beep Codes and Error Messages Port 80H 03 03H LHLLL ROMBIOS Checksum Failure 04 04H LHHLL DMA Page Register Failure 05 05H LHLHL Keyboard Controller Selftest Failure 07 07H LHHHL Memory Refresh Circuitry Failure 08 08H LHLLH Master 16 bit DMA Controller Failure
46. ff the power or press the front panel reset button without pressing lt F10 gt the changes you made in the BIOS will not be saved and the origi nal configuration will remain unchanged Operating the BIOS Setup The screens presented in this manual reflect the same format as your screens but they do not contain parameters e All BIOS screens contain menu line at the top of the screen containing names of the utili ties available from that screen body consisting of the entry fields containing the utility s para meters bottom line indicating the keystrokes that you can use to manipulate the cursor in that screen e Manipulating the screens A reverse video cursor is always present either on the menu line or in the body Use the lt Right Arrow gt and lt Left Arrow gt keys to move the cursor across the menu line highlighting the name of the cur rent utility When a utility s name is highlighted in the menu line the entry fields of that utility are displayed in the body Press the lt Down Arrow gt key to move the cursor into the first entry field You can move the cursor through the entry fields using the lt Down Arrow gt key To change an entry field press lt Enter gt then follow the instruc tions in the bottom line The instructions change depending on the current field You can scroll through the available choices for that field by pressing the lt Spacebar gt or the and keys in all adjust
47. guration Change Numeric Coprocessor Configuration Change System Key is in Locked Position Turn Key to Unlocked Position Adapter ROM Checksum Failure at Address XXXX Table 4 17 Beep Codes and Error Messages continued Beep Codes L low tone and H high tone 4 43 Fixed Disk Parameters fasta Reed feed aed aka Zone Track 128 305 17 17 4 4 6 8 6 4 8 5 5 3 5 7 8 7 0 4 5 7 7 5 7 5 4 4 9 8 5 8 aooo oOoONaA ak ak k aoouw Table 4 18 Fixed Disk Parameters 4 44 Chapter 4 BIOS Conventional Memory Oh 10000h 20000h 30000h 40000h 50000h 60000h 70000h OK 64K 128K 192K 256K 320K 384K 448K QQ A Re OXY 512K 576K 640K 704K 768K 832K 896K 960K 1MB 80000h 90000h A0000h B0000h CO000h D0000h E0000h F000 109000h gt t Upper Memory J RAM Se ROM IEMS FFFF F BIOS BIOS F800 0 Could be Page F000 0 Frame for EMS E800 0 Could be Page Frame for EMS ee a Network Cards D800 0 often use this area Booo Hard Drive ROMs C800 0 EGA VGA ROM Co000 0 CGA RAM EGA VGA Text Modes B800 0 MONO RAM Bo00 0 EGA VGA RAM Graphics Modes A800 0 EGA VGA RAM Graphics Modes A000 0 0040 0 0000 0 Table 4 19 Memory Map 4 45 Q amp A Q amp A This section contains questions that are most frequently asked of our Customer Support Department about the BIOS setup utility You may be able to diagnose any difficulty you have by referring to them prior
48. h this jumper installed the password selection is available in BIOS 2 Password Enabled Bk OFF Password Disabled Table 2 21 J19 Security Password Enable e J28 Processor Speed Select the clock speed of your CPU 6Jo O 5 1 amp 2 5 amp 6 alo ols 384 5 amp 6 lo ol 1 amp 2 384 5 amp 6 Table 2 22 J28 Processor Speed e J30 Video Enable Disable Installing a jumper on pins 2 and 3 enables the on board video con troller To disable the on board video controller install the jumper on pins and 2 This video selection video enabled or disabled must be the same as jumper J39 Video Disabled 5 Video Enabled 3 Table 2 23 J30 Video Enable Disable 2 10 Chapter 2 Jumpers and Connectors e J31 Video IRQ Enable Placing a jumper on J31 enables IRQ9 for video If no jumper is placed on J31 IRQ9 is available for other use IRQQ Enabled R 2 IRQ9 Available Table 2 24 J31 Video IRQ Enable e J32 DMA Channel for LPT1 Using DMA Channels enables high speed transfers from memory to the parallel port You can select DMA Channels 1 or 3 to be used for the parallel port 1 amp 2 7 amp 8 DMA Channel 3 3 amp 4 5 amp 6 DMA Channel 1 VAO O000 ooo vaN Table 2 25 J32 DMA Channel for LPT1 e J39 Video Enable Disable Installing a jumper on pins 1 and 2 enables the on board video con troller To disable the on board video controller remove the jumper This video
49. hen a system component has been properly installed and recognized by the BIOS Some of the items on this screen are auto sensed during the Power On Self Test POST Others are determined by selections you make on the following screens Items that are auto sensed are CPU Type and MHz CPU Rev CPU Code Cache CPU Data Cache RAM Cache Memory Base and Total Video Type Keyboard Type Floppy Fixed Disk Setup Screens Review this screen after making configuration changes and prior to exit ing the Setup Utility Viewing Fields There is no user entry allowed on this screen The parameters displayed are auto sensed during POST or they are selectable on other screens If the BIOS recognizes any serial and parallel ports their addresses will appear next to the port If not n a will appear res seinen rama Part number of the 1 486DX4 microprocessor installed in your 2 P24T system auto sensed during POST CPU Rev Revision level of the CPU auto sensed during POST CPU MHz Operating frequency auto sensed during POST PLL Ratio The factor by which the external operating frequency of the system board is multiplied to obtain the internal CPU MHz CPU Code Amount of internal CPU cache Cache allocated for code CPU Data Amount of internal CPU cache Cache allocated for data instructions External Cache How much cache is on the CPU board Memory Base The amount of Base M
50. ini DIN mouse connector located on the retaining bracket View from end of board Table 2 38 J21 Mouse mini DIN 2 21 Connectors e J22 Reset Connector An external reset cable can be attached to the ORCA at J22 Table 2 39 J22 Reset Connector e J25 Speaker Connector Placing a jumper on pins and 2 of J6 enables the on board speak er You can attach an external speaker to the ORCA by connecting a four position connector to J25 External Speaker Internal Speaker VCC VCC Table 2 40 J25 Speaker Connector e J26 CPU Fan Power Connector You can connect a CPU fan by connecting a four position connector to J26 Table 2 41 J26 CPU Fan Power Connector 2 22 Chapter 2 Jumpers and Connectors e J33 SVGA Connector J33 is a 15 pin connector located on the retaining bracket and con necting the SVGA with the system monitor 1 Red Drive Blue Drive N C GND GND GND M a AUN 3 4 5 6 7 8 9 z 2 ojo GND N C N C HORIZ SYNC VERT SYNC N C oO Table 2 42 J33 SVGA Connector 2 23 Chapter 3 Specifications System Components CPU Form Factor Interrupts Power Requirements Cache Dynamic RAM System ROM Clock Calendar External Connections Watchdog Timer 486SX 33 amp 100 486DX 50 amp 66 DX4 P24T Standard full length AT 15 levels available
51. loca tions of J5 and J6 refer to Figure 1 1 ORCA CPU Board Jumpers Connectors and Components on page 1 4 Connector Onboard 10 Pin Connector J5 or J6 Table 2 34 Serial Port Cable Wire List The following cable assembly shows the Pin 1 locations for the DB9 and ten pin connectors Serial port cables with DB9 and DB25 connectors are also available through I Bus O OOOO e 0o 000 O O O 0 O00000 O a DB9 Connector 10 pin Connector 2 19 Connectors e J9 Hard Drive LED Connector An LED can be connected at J9 to display hard drive activity 1 Anode 2 Cathode Table 2 35 J9 Hard Drive LED Connector e J14 Keyboard Connector 10 pin 2 4 6 8 10 00080 oooo 13579 Indicates connector key position Table 2 36 J14 Keyboard Connector 10 2 20 Chapter 2 Jumpers and Connectors e J20 Keyboard mini DIN J20 is a six pin mini DIN keyboard connector located on the retain ing bracket You can also use a standard PC AT compatible key board fitted with the keyboard adapter cable furnished with your CPU board Or you can use the ten pin keyboard header at J14 View from end of board Table 2 37 J20 Keyboard mini DIN CAUTION The mouse and keyboard mini DIN connectors are identical Make sure the correct accessory is plugged into it s proper connector e J21 Mouse mini DIN J21 is a six pin m
52. n be instructed to Enable Savings automatically correct the time on Disable the two daylight savings days of the year Altering this field will not cause an immediate change The RTC adjusts the time only when a daylight savings transition occurs Table 4 3 Clock Screen Entry Fields 4 15 Setup Screens e Keyboard Screen Summary Energy Clock Floppy Fixed Disk More NumLock State at Bootup Keyboard Typematic Speed Delay Before Keys Repeat F10 to Record and Exit Home End Moves Cursor Figure 4 4 Keyboard Screen Explanation From this screen you can control the power up state of NumLock Keyboard Typematic Speed and Delay Before Repeat NumLock State at Bootup This parameter sets the Numlock state of the numeric keypad of your keyboard at power up You can change it at any time by pressing the NumLock key When set to Off the numeric keys will produce special control func tions PgUp PgDn Home End Ins Del and cursors When set to On the numeric keys will produce the indicated numbers Keyboard Typematic Speed This is the rate in characters per second at which a key will repeat when depressed Delay Before Keys Repeat This is the length of time a key can be depressed before it will begin to repeat 4 16 Chapter 4 BIOS Entry Fields es e NumLock State at Bootup The initial NumLock state is programmable for cursor or numeric operation On selects numeric entry
53. n of its content appears on this Setup screen for your convenient reference You will need to furnish this information to your Memory Manager software in order to create a UMB in the F000 BIOS region BIOS Fzzz FFFF vital runtime BIOS UTILS Fyyy Fzzz speed amp cache on off POST Fxxx Fyyy power up code SETUP Fwww Fxxx Setup Utility AVAIL Fzzz Fyyy available for UMBs NOTE The actual values entered for w x y and z will vary depending upon the BIOS version 4 34 Chapter 4 BIOS Security Speed Cache Shadow 37C665 MEMORY TIMING Wait States Read Wait States Write A20 Gate Control MEMORY REFRESH Method AT BUS TIMING Wait States I O Recovery AT Bus Clock Default F10 to Record and Exit Home End Moves Cursor e Chipset Screen Figure 4 13 Chipset Screen Explanation This utility permits optional fine tuning of certain chipset parameters that are very technical in nature In modern ISA designs practically the entire system logic is contained in a few large chips called the chipset Its primary responsibility is to service and maintain the CPU and associated logic circuits The chipset is typically programmable by BIOS allowing it to be adapt ed to a broad range of designs and operating environments Most chipset functions are presented elsewhere in the Setup Utility as stan dard BIOS features The more technical core logic functions including Memory
54. ne for Out transmissions SCSI Small Computer System Interface A high speed general purpose interface to storage devices SRAM Static Random Access Memory As opposed to DRAM this memory does not need to be refreshed by a controller and holds its information as long as the power is on T tag comparator A memory that tells whether an address is available in the cache U UART Universal Asynchronous Receiver Transmitter A circuit that transmits and receives data on the serial port It converts bytes into serial bits for transmission and vice versa and generates and strips the start and stop bits appended to each character A2 4 Appendix 2 Glossary of Terms W wait states Extra time inserted to allow access to slower devices e g DRAM or EPROMS watchdog timer A device that watches for CPU inactivity and then resets the CPU after a specified duration of inactivity write back cache The process where the CPU updates the cache and the DRAM simultaneously but does not wait for the DRAM to complete the update write through cache The process where the CPU updates the cache and the DRAM simultaneously but the CPU waits for the DRAM to complete the update resulting in more time being consumed than in write back A2 5 L EV peog Ndd suejdyoeg aa
55. on Both the POST and SETUP regions may always be reclaimed for UMBs since they contain only power up and boot time code The AVAIL field shows the entire recommended range beginning at the bot tom of the F000 EPROM oe essere ms The system BIOS occupies this ROM 64K segment For best results WP Shadow always enable WP Shadow here C800 If present Adapter ROMs for non Vacant through video devices e g disk RW Shadow E000 controllers or LAN adapters are ROM 2 Adapter found in one or more of these seven segments While C800 DCOO are 16K segments E000 is 64K C000 amp Video Adapter ROMs e g VGA ROM 1 C400 Video usually occupy both of these 16K WP Shadow segments They appear collectively as ROM 1 when shadow is disabled Best performance is usually obtained when shadow is enabled here Entry Fields 4 33 Setup Screens Table 4 12 Shadow RAM Screen Entry Fields Fixed Disk Types 46 amp 47 can be used with Novell 2 X only when F000 is shadowed F000 UMB Upper Memory Block User Info This region of memo ry is traditionally reserved for BIOS and ROMs A maximum of 640K can be installed as Base Memory Various Memory Manager programs are able to increase the Base Memory by reclaiming unused gaps between the 640K and 1 MB boundaries Approximately the bottom 3 4 of the BIOS EPROM contains expend able code that may be reclaimed as UMB space A view only break dow
56. on the COM1 4 backplane first then on the CPU Disable board The port can also either be disabled or it can be identified as a specific port Parallel Port When the port is set to Auto the Auto BIOS looks for ports on the Video 3BC backplane first then on the CPU LPT1 378 board The port can also either LPT2 278 be disabled or it can be identified Disable as a specific port The floppy drive can be enabled Enable or disabled Disable Entry Fields Table 4 14 37C665 Screen Entry Fields 4 38 Chapter 4 BIOS Cold Start Hook 00 Custom 8042 Disable critical I O Reset DMA FDC Checksum EPROM Test Page Registers Page Register Boot Keyboard controller self test Enable A20 gate Initialize ISA I O Hook 01 Refresh toggle test Test DMA master slave registers Test base 64K memory Test interrupt controller mask Test interrupt controllers and initialize interrupt vectors Test 8254 timer Test speaker channel Test Real Time Clock Hook Video Test CMOS memory battery Display signon message Size and test base memory Retry keyboard initialization Size and test cache Test A20 gate Size extended memory check for Stuck NMI Size system memory Test real time clock Determine Comm Ports Print screen vector Initialize numeric coprocessor Determine FDC type Determine IDE type Check CMOS for FDC FIXED type Keyboard locked Setup numlock check security Final port setup
57. pe auto sensed during POST PC AT AT PS2 NumLock The NumLock state auto sensed during POST This field is only meaningful for 101 key keyboards See Keyboard Screen description in this Chapter Off On Table 4 1 Summary Screen Viewing Fields continued Setup Screens Fid Description Parameters PS2 Mouse Video Primary The main video display adapter which will be in use when control is passed to an Operating System at power up auto sensed during POST Video Indicates the presence of a Secondary second video adapter It will remain idle until activated by specialized software Table 4 1 Summary Screen Viewing Fields continued Chapter 4 BIOS Energy Screen Summary Clock Keyboard Floppy Fixed Disk More Energy Management Idle Timers IDE Drive Timer System Activity Event Monitoring Idle Video State Default F10 to Record and Exit Home End Moves Cursor Figure 4 2 Energy Screen Explanation Options available on this screen enable the user to reduce power con sumption when the system is idle Entry Fields ro sions IDE Drive Timer This switch can be set to 1 2 or 5 1 1 20r5 minutes After this duration with minutes no activity the hard drive is spun down System Activity After the above time has elapsed 2 5 15 30 with no activity the system 40 60 240 operating frequency is reduced to minutes 8 or 16MHz
58. r i ooun z834 r O afe l cua nooo pono gooioano nooo oooooanon na q nom of B S nonononn Op g Tom foonoonnog i 1004 aooo amp oooooonoor ooononnnor pong pauu z fee ooooonooo ooon Q STS lols amp frooommnnno 22 annonnnnnen rae noon le nonong aes 5 aooo 000000000 NIQ u1w off O O be i ik T nou nonne ooooononr asnon Ogle Zeo mmmn LI ie pon ni pa 5 an Ge 5 slal lgi ooa Yy ooooonont f ooooogung S PPn DONOOODON nee e syed nage Aino no fon A aand Umeocogccocecsagcad ecaccogcecacocas o U Niq luiw O O js aL a pum anon rl a oo0000000000 INS poGgocoo0cGoOoCOdS NJ paeoghey fe onomu oe nounnnn amp Bs z 0000 D000 nnnnonont ZHE O00000D 0000000 _ S B S I ain bait 0000000 U noocooococooocoo oooocoocoocooagdoo U ozr E Tin J D000 0000 LZ eoacooacoaao EWS OooCooCoGoCoOooooa NI OF mgpa vooon DODDO Tom z E 3 aia ooocg 000 A000 D00 mn en E C0000 moun Si oor U noocooocoocooa ZNS ooooooooooooogooo l aoaaa em ook TA o OO O00 er eoooocaooco0gcoo s oooocoocooccCooo oa ooo pone oon r e eoefer lasofer nood lar sr e oof M oo oj joo ejor ar tf THE qooog oooog ogoo0o0o0o0000g000gm ooo ooo0000fmooo opoponoocoocoorgooooooon E Upooooooooooona eoo0ocaoacnocoooogjo0o05 U oog00 oooga oo0000000000 oog opoooooopooa oboooopoonoopooqoooo Oon0o0iT soacocoacoaaar LNS 3000000000000 p000 JOyaUUOD p eoq y vir pajas Addo 4 ypsjas ayoeg er yod ZOO sir Jardin or Od LWOO p m s y l SAU ACI
59. rd 1 3 W Watchdog Timer 1 9 3 1 Idx 6
60. ssor 1FO 1FF Hard Disk Controller 200 207 Game I O 278 27F Prototype Card 2F8 2FF Serial Port 2 300 31F Prototype Card 360 36F Reserved 378 37F Parallel Printer Port 380 38F SDLC Bisynchronous 2 3A0 3AF Bisynchronous 1 3B0 3BF Monochrome Display Printer 3C0 3CF Reserved 3D0 3DF Color Graphics Display Adapter 3F0 3F7 Floppy Disk 3F8 3FF Serial Port COM1 Table A1 1 Standard PC AT I O Map DMA DMA Channel Page Register and I O Addresses Controller 1 8 bit ports 000 00F I O Hex Address Controller 2 16 bit AT Only ports 0C0 0DF Table A1 2 DMA Channel Page Register and I O Addresses DMA Channel Assignments es ee a EE Spare Reserved Table A1 3 DMA Channel Assignments Appendix 1 Technical Reference DMA Controller Register Functions een ce a F200 Ree sinus regier commana reaser Cons wreme Table A1 4 DMA Controller Register Functions A1 3 Interrupts a o ro oronro ros Feesn res eomas maroon E Table A1 5 Interrupts These interrupts exist on the system board and are not available on the ISA Bus Connectors Appendix 1 Technical Reference CMOS RAM Address Map Table A1 6 CMOS RAM Address Map These addresses are not verified by CHECKSUM A1 5 Real Time Clock Information Addresses 00 0D Seconds Seconds alarm Minutes Minutes alarm Status Register B Status Register
61. t I Bus for information Floppy Disk Drive Interface Any combination of up to two 3 5 and or 5 25 disk drives or up to two 2 88MB drives can be installed on the Orca CPU board at J3 The interface can also be disabled through the BIOS OPTi 82C802G The OPTi 82C802G provides the major portion of the system con trol Its features include cache interface buffer controller memory interface system and cache controllers The G indicates support for green functions Integrated Peripheral Controller IPC The 82C802G integrates two 8237 DMA controllers two 8259 interrupt controllers and one 8254 timer counter Programmable Interrupt Controller The 82C802G provides 15 user selectable interrupt channels Counter Timer The 82C802G provides three independent counter channels Counter 0 is used as a system timer Counter 1 is used to generate pulses for DRAM refresh Counter 2 is a full function counter timer 1 7 Features e Direct Memory Access DMA The 82C802G provides seven DMA channels The first four DMA channels are used for eight bit DMA transfers The remaining three channels are used for sixteen bit DMA transfers The sixteen bit DMA channels function identically to the eight bit DMA channels except that bit 0 of the address and the length fields are assumed to be zero All transfers must begin on an even address boundary and the length must be an even number of bytes The sixteen bit DMA channels transfer up
62. t sector by enabling this option You will need to disable it prior to running fixed disk maintenance programs e g FDISK No writes to boot sector Yes disallows writes to boot sector 4 21 Setup Screens Entry Fields ee oe This field is auto sensed None MB capacity Scroll through 1 47 or enter None numerically 1 45 46 amp 47 Cylinders These fields are auto sensed Heads When type 46 or 47 is entered these Precomp fields can be edited Landing Sectors Translate A large drive up to 16K cylinders can be fully utilized by enabling BIOS translation Otherwise the traditional 1K cylinder interface is employed No indicates 1K cylinders or less Yes indicates more than 1K cylinders Xfer Mode A Standard Data transfer is 1 sector per interrupt B Poll No interrupts Strictly polls the drive for ready C Block Transfers data based on the block size that the disk drive reports D 32 Bit Block Uses 32 bit instructions to transfer data Anti Virus Select Yes to enable Table 4 6 Fixed Disk Screen Entry Fields NOTE If your documentation does not indicate a Precomp value you can make None appear by entering the same number as the Cylinders value Similarly if your documentation does not indicate a Landing Zone use the same value as Cylinders 4 22 Chapter 4 BIOS VL Bus IDE Screen More Boot Seq Ports Security Speed More
63. ters directly from the disk Fixed disk parameters are sorted into a universal standard for fixed disk types When the computer is booted a table is constructed in main memory with these parameters If your computer has Shadow RAM capability and the BIOS shadow is enabled the table is generated in the EPROM image to assure 100 compatibility with all software NOTE Novell 2 X requires the BIOS to be shadowed when using types 46 amp 47 4 20 Chapter 4 BIOS Translate If your fixed disk has more than 1024 cylinders you can instruct the BIOS to translate the parameters A drive with as many as 16K cylinders can be supported through this technique Otherwise the fixed disk interface is limited to the traditional 1K cylinders Anti Virus The Anti Virus option offers a measure of protection against malicious programs which infect the main boot sector or low level format destroy your data Since viruses often gain entry when an infected floppy disk is booted you should supplement this defense with the C 1st boot order in the Boot Sequence Utility NOTE You will need to disable this option while using certain fixed disk maint enance programs e g DOS FDISK because their actions would be interpreted as a violation WARNING Many classes of viruses will not be detected and even when a virus is detect ed it may have already infected the disk corrupted data spread through a network etc Write protect the main boo
64. their types Floppy 0 2 None and Floppy 1 correspond to 3 5 360K Drives A and B respectively 4 30 720K The drive letters for Floppy 2 and 5 5 1 2MB 3 depend on your Operating 6 30 1 4MB System 7 30 2 88MB Step Rate Set to Fast for best 1 Fast performance A Slow setting is 2 Slow provided for backward compatibility with 8MHz data transfer standards Table 4 5 Floppy Screen Entry Fields 4 19 Setup Screens e Fixed Disk Screen Summary Energy Clock Keyboard Floppy Fixed Disk More Fixed Disk 80 C Fixed Disk 81 D Low Level Format Size Type Precomp Cylinders Precomp Landing Heads Landing Sectors Precomp Sectors Translate Xfer Mode Anti Virus F10 to Record and Exit Home End Moves Cursor Figure 4 6 Fixed Disk Screen Explanation The Fixed Disk Screen allows you to define the hard disk drives on your system and to program the Low Level Format utility Fixed Disk 80 amp 81 Fixed disks are referenced as Units 80 and 81 corresponding to C and D depending on your operating system The BIOS is unaware of any partitions or other logical mappings When you enter the fixed disk Type from 1 to 45 the system automat ically enters the parameters When you enter types 46 and 47 you can either enter the parameters from the documentation furnished with your drives or you can also enter a question mark after entering 46 or 47 The BIOS will then enter the parame
65. to calling our Customer Support Q1 Q2 Q3 Q4 Q5 How do you setup the board in the extended setup Al Try using the defaults first defaults have an asterisk at the beginning of the line item A2 Set the COM ports IDE and Floppy for enabled or dis abled as needed A3 The defaults are Read cycle wait states 2 Write cycle wait states 3 Refresh Normal AT wait cycle wait states 0 Video BIOS Non cacheable SRAM wait states 1 Non cacheable blocks 1 amp 2 Disabled What are the non cacheable blocks for A These are used if a component or program in the system needs to have non cached memory area What is the starting address for these non cacheable blocks A The non cacheable block can start in the beginning of the base memory all the way to the end of the available memory The largest block size is 412k times two non cache blocks 1 and 2 Do I have to use the on board IDE or floppy disk controllers A No Do you have to use the serial or parallel ports built onto the CPUs A No you may relocate or disable them 4 46 Chapter 4 BIOS Q6 What if you are using a different controller other than the one built into the CPU A This is not a problem if you adjust the BIOS to use an off board controller Q7 Can I use a SCSI controller and where should I set the address Al A2 You can use a SCSI controller You must set the card address for the primary controller in the syst
66. to operate the Orca 14 3 2 MHz board at 11 MHz but it will involve 5 6 MHz finding expansion cards that will 6 7 MHz operate at that speed The speed selected will affect all I O transmissions In systems set to run without any additional cards network video controllers modems the Orca can run at the highest available speed Default is 8 3 MHz 4 36 Chapter 4 BIOS Entry Fields More Chipset 37C665 ON BOARD PERIPHERAL OPTIONS 37C665 I O Chip Primary Serial Secondary Serial Parallel Port Default F10 to Record and Exit Home End Moves Cursor Table 4 13 Chipset Screen Entry Fields e 37C665 Screen Figure 4 14 37C665 Screen Explanation The 37C665 Multifunction Controller XIO provides two serial ports one parallel port an IDE interface and a floppy disk controller The controller determines the address to respond to and the IRQ to use for each port NOTE If you use an external I O card you must disable the Floppy field on this screen To disable the internal IDE you must place a jumper on pins 4 and 6 on J11 4 37 Setup Screens ee oe Primary Serial When the port is set to Auto the 1 Auto BIOS looks for ports on the 2 COM1 4 backplane first then on the CPU 3 Disable board The port can also either be disabled or it can be identified as a specific port Secondary When the port is set to Auto the Auto Serial BIOS looks for ports
67. up Screens When you assign a security code you are required to enter it when the computer boots and again on the Summary Screen in order to enter the Setup Utility Entry Fields e ee Security Select the security option desired Disable Power Setup Setup only Change code Table 4 9 Security Screen Entry Fields 4 28 Chapter 4 BIOS e Speed Screen More VL Bus IDE Boot Seq Ports Security More System Speed Runtime Hot Key Sequence CTRL ALT Low Speed CTRL ALT High Speed F10 to Record and Exit Home End Moves Cursor Figure 4 10 Speed Screen Explanation The operating speed of the CPU is configured here High speed turbo will maximize the system performance Low speed reduces perfor mance to simulate the original slower personal computers You can change the speed during normal runtime by pressing lt Ctrl gt lt Alt gt lt gt for High speed or lt Ctrl gt lt Alt gt lt gt for Low speed Entry Fields oe System Speed Select the computer s operating 1 Low speed according to your 2 High preference Table 4 10 Speed Screen Entry Fields 4 29 Setup Screens e Cache Screen Security Speed Shadow Chipset 37C665 486 CPU Cache External Cache SRAM Burst Read SRAM Write Cycle Shadow RAM Cache Size Runtime Hot Key Sequence CTRL ALT Disable Cache CTRL ALT Enable Cache F10 to Record and Exit Home End Moves Cursor
68. yte write to port 160H to reset the watchdog data value is unim portant Set the divisor for the RTC square wave output by per forming the following steps 1 Write a OAH to port 70H to access port A of the RTC 2 Read port 71H to retrieve value 3 Logically OR the value read with OFH 4 Write a OAH to port 70H to access port A of the RTC Write the modified value to port 71H Enable the square wave output by executing the following steps 1 Write a OBH to port 70H to access port B of the RTC 2 Read port 71H to retrieve value 3 Logically OR the value read with 08H 4 Write a OBH to port 70H to access port B of the RTC Write the modified value to port 71H The watchdog timer is now running To reset the watchdog timer perform a byte write to port 160H The watchdog timer will time out if no write to port 160H is executed within 16 seconds At this point interrupt 11 is asserted If another 16 seconds passes without a write to port 160H the board is reset Features To disable watchdog timer operation 1 Write a OBH to port 70H to access port B of the RTC Read port 71H to retrieve value Logically AND the value read with F7H Write a OBH to port 70H to access port B of the RTC a e p p Write the modified value to port 71H e Local Bus Video The Orca is equipped with on board local bus SVGA with up to 2MB video RAM It incorporates the Cirrus Logic CL GD5434 and runs at up to 41 million WINMARKS WI

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