(USB Function Controller) EIFUFAL501 User`s Manual
Contents
1. USB Function Controller Please design your circuit so that USBFC can be seen from outside chip as the diagram below in the USBFC test mode aa Ge EET 8 s EE N DS 5 E La ey a LONE S lt u p SH 8 ven l N 5 5 ME Pn Oscillator cell OSC8C is included just for a design example OSC RUN however should be able to control the clock input into CLK48 EARLY CLKOUT pin is not included in the test pattern LCLK OUT pin of USSBFC is not tested This sample circuit can be an example of a minimam addition to USBFC to make a simple usb chip when a CPU is external to the chip EPSON 352. 3 2 3 DMA Controlled USB to Local Bus Transfers A Direct Memory Access DMA controller may be used on the local bus to transfer data to and from the USBFC For host to device transfers the local and host CPUs first arrange to transfer a block of data from host memory to local shared memory The local CPU then programs the DMA controller for fly by demand mode transfers In this mode transfers occur only when the USBFC requests them and the data is read from the USBFC receive FIFO and written into local memory during the same bus transaction The DMA address counter is programmed to point to the destination memory block in local shared memory and the byte count to the number of bytes in the block to be transferred After the DMA controller has been programmed the DMA request enable bit is set in the USBFC The USB host performs USB bulk or isochronous data transfers over the USB bus to the receive FIFO in the USBFC If the FIFO fills up during a bulk transfer the USBFC will return a USB NAK acknowledge to the host signaling that the data could not be accepted Packet data which is in the FIFO or has already been transferred by the DMA should be discarded If the local CPU has stalled this endpoint the USBFC will not store any data into the FIFO and will respond with a STALL acknowledge As long as there is data available in the FIFO the USBFC will request local DMA transfers by asserting DRQ The DMA controller then requests the local bus
3. If it is asserted during a DMA cycle the current byte will be transferred but no additional bytes will be requested POT can be programmed to cause a USB interrupt INT_ Output Interrupt Request Output The interrupt request output is used to interrupt a processor on the local bus There are several sources of this interrupt which are described in the Register Description Section DEVCFG_ Output Device Configured This active low output is true when the USBFC has been configured by the USB host SUSP_ Output Device Suspended This active low output is true when the USBFC has been suspended by the USB host OSC_RUN Output Oscillator Run Clock input to CLK48_EARLY shoud be enabled depend on OSC_RUN LCLK_OUT Output Local Clock This is a buffered output from the internal 48 MHz oscillator This signal is not driven while the device is suspended LRESET_ Output Local Reset This active low output is asserted when either the RESET pin is asserted or a USB port reset is detected ISO_ Input Isochronous Mode Select This active low input selects isochronous mode for USB transfers to and from the FIFOs WAKEUP_ Input Wakeup This active low input causes the USBFC to perform a USB remote wakeup BUSPWR_ Input Bus Powered This active low input indicates that the logic external to the USBFC is powered by the USB bus If this input is high then the external logic is self powered PWRGOOD_ Input Power Good This active low in
4. e e e Interrupts EPSON User s Manual 1 3 USBFC Block Diagram USB Function Controller D 7 0 E A 4 0 ____ CS_ OR gt IOW _ gt DRQ DACK bi EOT gt RO RESET AN Configuration Control Bi and Status r Endpoint 0 8 Byte Mailbox lt Bulk Endpoint_1 USB Serial Local Bus 8 Byte Mailbox __ b p Interface Engine Controller Interrupt Endpoint_2 and Controller 64 Byte Rev FIFO 4 Bulk amp lsochonous Le Endpoint_3 64 Byte Xmt FIFO p Bulk amp Isochronous kuch Endpoint_4 d D gt USB PORT lt D gt 1 4 USBFC Typical System Block Diagram Scanner Camera Controller Shared Memory Microprocessor Data Bus DMA Controller Optional USB Function Controller USB PORT EPSON User s Manual USB Function Controller 2 Signal Description 2 1 Symbol Diagram for USBFC SH CLK48_EARLY SH ROOT DATAIN P Sc ROOT DATAIN M ROOT DATAOUT P SH SIE XRXD ROOT DATAOUT M p e E __ LDIN7 ROOT DATA OE e N e e H LDING E SH LDIN5 DEQ ST LDM LDOUT7 re STI LDIN3 LDOUT6 e LDIN2 LDOUTS Le 2 LDIN1 LDOUT4 ke e LDINO LDOUT3 kg FEED ay USBFC LDOUT2 re o e LAS LDOUT1 oe d s LDOUT
5. the peripheral may not draw more than 500 uA from the USB connector s power pins If these power considerations can be met without the use of an external power supply the peripheral can be bus powered otherwise a self powered design should be implemented In case of self powered and also power sensitive applications the USBFC can be forced to enter low power suspend mode when disconnected from the USB Setting bit 7 of the USBSTAT register when USB power has been removed forces the USBFC to enter low power suspend mode The USBFC will EPSON 12 User s Manual USB Function Controller automatically wake up when the peripheral is re connected to the USB Do not force suspend mode unless the peripheral is disconnected from the USB EPSON 13 User s Manual USB Function Controller 4 Local Registers 4 1 Register Description The USBFC occupies a 32 byte local register space which can be accessed by a CPU on the local bus The Endpoint 1 Receive Mailbox Registers are written by the USB host and the Endpoint 2 Transmit Mailbox Registers are read by the USB host After the USBFC is powered up or reset the registers are set to their default values Writes to unused registers are ignored and reads from unused registers return a value of 0 For compatibility with future revisions unused bits within a register should always be written with a zero NOTE The USB device and configuration descriptors cannot be read by the USB host u
6. from the local CPU After the DMA controller has been granted the bus it drives a valid memory address and asserts DACK_ IOR_ and MEMW_ thus transferring a byte from the USBFC receive FIFO to memory This process continues until the DMA byte count reaches zero A local bus interrupt may be programmed to occur when the DMA has finished Once an end of packet occurs an interrupt can be generated to the local CPU The local CPU can read a status port to detect whether the packet was acknowledged with an ACK NAK or STALL If none of these acknowledge bits are set then a timeout has occurred For NAK or timeout conditions at the completion of bulk transfers the USB host will send another OUT token and the USBFC should receive the same packet again An early end of packet EOP can be detected by the local CPU if the DMA count is non zero The local and host CPUs should then decide how to proceed 3 2 4 DMA Controlled Local Bus to USB Transfers For device to host transfers the local and host CPUs first arrange to transfer a block of data from local memory to host memory The local CPU then programs the DMA controller for fly by demand mode transfers In this mode transfers occur only when the USBFC requests them and the data is read from local memory and written into the USBFC FIFO during the same bus transaction The DMA address counter is programmed to point to the source memory block in local memory and the byte count to the number of byte
7. timeout has occurred For NAK or timeout conditions at the completion of bulk transfers the USB host will send another IN token and the USBFC should re transmit the same packet 3 2 5 Terminating DMA Transfers The EOT_ signal is used to halt a DMA transfer and is typically provided by an external DMA controller It should be asserted while DACK_ and IOR_ or IOW_ are simultaneously active to indicate that DMA activity has stopped Although an EOT_ signal indicates that DMA has terminated the USB transfer is not complete until the last byte has been transferred from the FIFO to the USB bus The EOT_ resets the USBFC DMA request enable bit If no EOT_ signal is provided by the DMA controller the DMA transfer can be halted at any time by resetting the USBFC DMA request enable bit If the USBFC DMA request enable bit is cleared during the middle of a DMA cycle the current cycle will complete before DMA requests are terminated 3 2 6 USB Endpoint 1 Receive Mailboxes Endpoint is used for bulk transfers from the USB host to a set of 8 receive mailbox registers which are read by the local CPU The format of the data written to the mailbox is user defined To transfer an 8 byte packet the host first performs a USB 8 byte bulk transfer to the endpoint receive mailbox registers A receive mailbox valid bit bit 1 of register IRQSTAT1 is then set which can cause a local bus interrupt If the USB host tries to write to these registers when the valid
8. 2 3 3 2 Device Remote Wake Up saves Ed SEER giereg DEERE GE Ge see Bek Ge Aea e DAG GEE ee Ee ge DE RE Ee ches 12 33 3 Host Initiated Wake Up ss avid ord RE atheist btn ere eed in reas 12 3 4 USBFC Power Confteuraton sesse see se ee Ge ee ek ee GRA Ge ee Ge Re GR ee GRA Ge ee Ge Re eke ee ETE E Ge Re GR ee ee 12 A Local SOLO EE EE RO EO EE N 14 4 1 Register Description sirenes renni e GED EE Ee DR GESE Ge GED SERE SEGE ee ER ee Ge eed EEeEed ee 14 4 2 Register SUMMALY ER EE ER OE EE N EE 14 4 3 Address 00h DCTL DMA Control Register 15 4 4 Address 01h IRQENB1 Interrupt Enable Register 1 15 4 5 Address 02h IROSTAT 1 Interrupt Status Register 1 16 4 6 Address 03h IRQENB2 Interrupt Enable Register 2 16 4 7 Address 04h IROSTAT 2 Interrupt Status Register 2 16 4 8 Address 08h EPIIDX Endpoint 1 Index Register esse ese sesse see se ee Gee see ek ee eed Ge ee Ge ee Ge ee ee ee 17 4 9 Address 09h EP1DATA Endpoint 1 Receive Mailbox Data 17 4 10 Address OCh EP2IDX Endpoint 2 Index Register 17 4 11 Address ODh EP2DATA Endpoint 2 Transmit Mailbox Data 17 4 12 Address OEh EP2POLL Endpoint 2 Interrupt Polling Interval Register sesse sesse sesse ee ees ee se ee 17 4 13 Address 10h EP3DATA Endpoint 3 Receive FIFO Data Register sesse ese se ese se esse sees se ee ee ee se ee 18 4 14 Address 11h EP3COUNT Endpoint 3 Receive FIFO Count Register 18 4 15 Address 12h EP3STAT Endpoint 3 Receive FIFO Status Register ess
9. Bus Read from Re istets sc e0 ege eee ede ep end senor dee Aan tds 32 Ed PMA Write t T O OE EE EE N EE EE N N OO IE 33 74 DMA Read from HRC eieiei er ses bons es te es ee bee ese ek ee ek eek eege Ge bessie ee 34 8 Test Olie ri AE Ee EE EE RE 35 EPSON User s Manual USB Function Controller 1 Highlights 1 1 Features e USB Specification Version 1 0 Compliant e Bridges between a Processor Independent local bus and a USB bus e USB device bandwidth of up to 12Mb sec e USB Bulk Isochronous Interrupt and Control transfers e Independent 64 byte transmit and receive FIFOs to maximize throughput e Supports local CPU or DMA data transfers e 3 3V operating voltage 1 2 Overview The USB Function Controller USBFC allows bulk or isochronous data transfers between a generic local bus and a Universal Serial Bus USB The USBFC supports the connection between a host computer and an intelligent peripheral such as a digital camera or scanner The three main components of the USBFC are the USB Bus Interface the dual 64 byte FIFOs and a Local Bus Interface The USB Interface is responsible for the following functions Host to device Communication Bulk or isochronous endpoints to access FIFOs Interrupt endpoint to access Local to USB Mailboxes Bulk endpoint to access USB to Local Mailboxes The Local Bus Interface is responsible for the following functions FIFO Control Local CPU interface Local DMA controller interface KL
10. FIFO to be flushed Yes Clr Reading this bit always returns a 0 Receive FIFO Overflow If set this bit indicates that an attempt was made by the Yes Clr USB host to write to the receive FIFO when the receive FIFO was full Writing a 1 clears this bit Receive FIFO Underflow If set this bit indicates that an attempt was made to Ed EE the receive FIFO when the receive FIFO was empty Writing a 1 clears this bit Receive FIFO Full If set this bit indicates that the receive FIFO is full Ep WE 0 Receive FIFO Empty If set this bit indicates that the receive FIFO is empty 4 16 Address 13h EP3PKSZ Endpoint 3 Maximum Packet Size Register Wee EE EE Bits Description Read Write Value id Endpoint 3 Max Packet Size Register This register specifies the maximum seg a packet size for endpoint 3 in units of 8 bytes default 64 bytes It can be read by the host through the endpoint 3 descriptor 4 17 Address 14h EP4DATA Endpoint 4 Transmit FIFO Data Register Default Bits Description Ken Se Value 7 0 Transmit FIFO Data Register This register is used by the local CPU to write data to the transmit FIFO The FIFO is read by the USB host using bulk or isochronous transfers from endpoint 4 4 18 Address 15h EPACOUNT Endpoint 4 Transmit FIFO Count Register Default Ga Description re Value EE FIFO Count This register returns the number of transmit FIFO entries ee eee valid entries Values range from 0
11. IFO Writing a 1 clears this bit USB Endpoint 3 ACK The last USB packet received OUT packet was Yes Yes Clr successfully acknowledged with an ACK Writing a 1 clears this bit Endpoint 2 Valid When this bit is set the 8 byte endpoint 2 mailbox registers Yes Yes have been written by the local CPU but not yet read by the USB host The local CPU should not write into these registers while this bit is set 4 23 Address 1Ah FRAMEMSB Frame Counter MSB Register Default Bits Description Read Write Value 3 Reserved ______ ye No 0 2 0 Frame Counter MSB This register contains the most significant bits of the frame counter from the most recent start of frame packet 4 24 Address 1Bh FRAMELSB Frame Counter LSB Register Default Bits Description Read Write Value 7 0 Frame Counter LSB This register contains the least significant bits of the frame Yes No counter from the most recent start of frame packet 4 25 Address 1Ch EXTIDX Extended Register Index Default Bits Description Read Write Value 7 0 Extended Register Index This register selects which extended data register is Yes Yes accessed when the EXTDATA port is read or written EPSON 20 User s Manual USB Function Controller 4 26 Address 1Dh EXTDATA Extended Register Data Default a Description Read Write Value ETE Data This port provides access to one of the extended data registers The See See See EES of the current re
12. LSB Index of string descriptor describing manufacturer 0x01 Index of string descriptor describing product 0x02 Index of string descriptor describing serial number 0x00 Number of configurations 0x01 EPSON 24 User s Manual USB Function Controller 5 1 5 Get Configuration Descriptor 46 bytes Note that all interface and endpoint descriptors are returned when this request is issued Offse Number of Description Default Value t Bytes Configuration Descriptor o IJL emg OO 1 Type configuration KOR 2 2 Total length returned for this configuration 0x002E 4 Number of Interfaces OE P 5 Number ofthis configuration OO 7 Attributes 0x60 if self powered bit 7 Bus Powered depends on BUSPWR_ input pin Us AO if bus powered bit 6 Self Powered depends on BUSPWR_ input pin bit 5 Remote Wakeup bits 4 0 Reserved 1 Maximum USB power required in 2 mA units 0x32 if self powered EE EN empowered Interface 0 Descriptor 0 1 i Size ofthis descriptorinbytes KO Number of endpoints used by this interface excluding endpoint 0 6 1 SubClassCode SH 8 1 Index of string descriptor describing this interface 0x00 Endpoint 1 Descriptor oo ft Size ofthis descriptor OT 2 1 Endpoint Address bit 7 direction 1 IN 0 OUT bits 6 4 reserved bits 3 0 endpoint number Endpoint Attributes bits 7 2 reserved bits 1 0 00 Control 01 Isochronous 10 Bu
13. O s LAl LDOUT OE 2 LAO DEVCFG_ ke kg o _ RESET_ SURES ESE o cs LRESET_ e e Ion OSC RUN eo ow LCLK OUT SH DACK_ SH EOT WH ISO _ WAKEUP_ BUSPWR_ SH PWRGOOD_ Gi TEST EPSON User s Manual USB Function Controller 2 2 Signal Description NOTE Input signal must be driven externally when the USBFC is in the suspended state The signal which has underscore _ at the end of its name is active low CLK48 EARLY 48 MHz Oscillator input RESET_ Input Reset External reset Connect to local or power on reset To reset when oscillator is stopped initial power up or in suspend state assert for at least one ms When oscillator is running assert for at least five 48 MHz clock periods ROOT DATAIN P Input USB Data Input Two differential input signals DP amp DM of ROOT_DATAIN_M the USB port SIE XRXD Input USB Data Differential Receiver Amplified input signal extracted from the two incoming differential input signals of the USB data port DP gt DM 1 DP lt DM 0 ROOT DATAOUT P Output USB Data Output Two differential output signals DP amp DM ROOT_DATAOUT_M of the USB port ROOT DATA OE Output USB Port Output Enable This active low output is true when USBFEC is driving the USB port data output lines ROOT DATAOUT P amp ROOT DATAOUT Mi LDIN 7 0 Data Input LDIN7 is the most significant bit LDOUT 7 0 Data Output LDOUT7 is the most signif
14. USBEC USB Function Controller EIFUFALS01 User s Manual Doc 88 02 E01 Revision 2 0 Date 03 24 98 SEIKO EPSON CORPORATION User s Manual USB Function Controller USB Function Controller USBFC Vi Gh Shs OE EE EE E EEE EE A ti Features ET 4 Ee SA EE R EE O A RR 4 1 3 USBFE Block Diagram nn r a n ee eg ee Ee E R EE ee AD tine Rec tesa 5 1 4 USBFC Typical System Block Diagram esse sesse se ese see see ek ee GR Ge GR Ge Re Ge ee eke SA Ge ee Ge Re GR ee Re 5 2 Sisnal leet OR N ER dee E 6 2 1 Symbol Didgtam for USR ki aa Shale Eeer 6 2 2 S1grial DEseripHOOM ss ss Re REENEN Ee ek AN Ee erer Ain es Ee eg SE ee Ee Ee ees Bats 7 3 Functional Descriptions neisi oien de ee eb GR ek ees Da SR EED eek a En GE aad atest aidan noes Ge Dee ee Ee 9 Bl GLY ER Oues RE OE IE EA OE EE 9 J32 Local EL EE N NE DE N EE N OER EN 9 3 2 1 CPU Controlled USB to Local Bus Transfers 9 3 2 2 CPU Controlled Local Bus to USB Transfers 9 3 2 3 DMA Controlled USB to Local Bus Transfers 10 3 2 4 DMA Controlled Local Bus to USB Transfers 10 3 25 Terminatidig DMA Transfers ese sense EL SeSe ee Edel Rek Es ee ESE Re e bee ee ES ge ie 11 3 2 6 USB Endpoint 1 Receive Mailboxes 0 ee cesseessesecseeeecseeecsaeceeesesaeceeesecaesseenesseesaeeeeeaecaeeseenees 11 3 2 7 USB Endpoint 2 Transmit Mailboxes sesse ee se ee Ge ee ek ee GR Ge ee Gee Re GR ee GR ek ee SA Ge ee Ge ek Ge ee 11 3 3 Suspend RE 12 3 3 1 HA Ee RE DEE RE OE ER EE EE RE EE TEES ai 1
15. a three millisecond period of inactivity on the USB the USB specification requires a device to enter into a low power suspended state The device may not draw more than 500 HA of current while in this state To facilitate this the USBFC provides a suspend request interrupt and a suspend bit in the USB status register Additionally the USBFC allows the local CPU to send a device remote wake up request arequest from the local CPU to wake up the USB 3 3 1 The Suspend Sequence The typical sequence of operation is as follows during device configuration the local CPU will configure the USBFC to interrupt on a suspend request using the IRQENBI register When the USB is idle for three milliseconds the USBFC will generate a suspend request interrupt The local CPU accepts this interrupt by clearing the corresponding bit in the IROSTAT1 register and performs the tasks required to ensure that not more than 500 HA of current is drawn from the USB power bus Then it writes a 1 to bit 7 of the USB status register USBSTAT to initiate the suspend In suspend mode OSC_RUN output pin goes low and therefore the clock input into CLK48_EARLY shoud be stopped The SUSP_ output pin will be low while the device is in the suspended state Note that input pins on the USBFC should not be allowed to float during suspend mode The USBFC will leave suspend mode by detecting traffic on the USB bus or by a device remote wake up from the local CPU 3 3 2 D
16. bit is set a NAK acknowledge will be returned When the local CPU receives the interrupt it reads the 8 bytes and clears the valid bit The USB host can then send another 8 byte packet to this endpoint An index pointer is used to access the receive mailboxes It must be initialized by the local CPU and is automatically incremented after the local CPU reads the receive mailbox data register 3 2 7 USB Endpoint 2 Transmit Mailboxes Endpoint 2 is used for interrupt transfers to the USB host from a set of 8 transmit mailbox registers which are written by the local CPU To transfer an 8 byte packet the local CPU writes data into the 8 registers and sets the transmit mailbox valid bit The host performs a USB 8 byte interrupt transfer from the endpoint 2 transmit mailbox registers After the USB interrupt transfer has completed the transmit mailbox valid bit is cleared The CPU should only write to the transmit mailbox registers when the valid bit is not set This guarantees that a previous interrupt transfer has completed before the register values are changed If the USB host tries to read endpoint 2 when the valid bit is not set a NAK acknowledge is returned An index pointer is used to access the transmit mailboxes It must be initialized by the local CPU and is automatically incremented after the local CPU reads or writes the transmit mailbox data register EPSON 11 User s Manual USB Function Controller 3 3 Suspend Mode When there is
17. chronous Determined by Local Register EP3PKSZ 0x00 for bulk 0x01 for isochronous 0x07 0x05 0x84 0x02 for bulk 0x01 for isochronous Determined by Local Register EP4PKSZ 0x00 for bulk 0x01 for isochronous 26 User s Manual USB Function Controller 5 1 6 Get String Descriptor 0 Offse Number of Description Default Value t Bytes 2 Language ID English 09 U S 04 0x0403 0x0409 5 1 7 Get String Descriptor 1 Offse Number of Description Default Value t Bytes 24 Manufacturer Descriptor 0x1803 SEIKO EPSON 5 1 8 Get String Descriptor 2 ie EE Product Descriptor 0x4203 USB Interface Controller TEST2 0 5 1 9 Get Configuration Number of Description Default Value Bytes LU 1 Returns current device configuration JL Dat 5 1 10 Get Interface Number of Description Default Value Bytes 1 Returns current alternate setting for the specified 0x00 interface EPSON 27 User s Manual 5 2 Control OUT Transactions 5 2 1 Set Address ae Number of Sets USB address of device Value device address Index 0 USB Function Controller WR Sets the device configuration Value Configuration value 0 or 1 supported Selects alternate setting for specified interface Value Alternate setting Index specified interface mas Clear the selected device feature Value feature selector FS 1 gt Device Remote Wakeup disable a S
18. dress 1Dh Index 06h RCVAFTH Receive FIFO Almost Full Threshold ees sees see 22 4 26 8 Address 1Dh Index 07h XMTAETH Transmit FIFO Almost Empty Threshold 0000 0 22 4 26 9 Address 1Dh Index 08h USBCTL USB Control 22 4 26 10 Address 1Dh Index 09h MAXPWR Maximum Power Consumption esse ese se se seg 22 4 26 11 Address 1Dh Index OAh PKTCTL Packet Control esse es see se ee ER Re Ge RA ee GR ee ee 22 4 26 12 Address 1Dh Index OBh LOCALCTL Local Side Control 23 4 26 13 Address 1Dh Index OCh FIFOCTL FIFO Control 23 5 Standard Device Requests 33 ssttece ell EENEG 24 5 1 Control IN Transaction iss Ve EE n EER EELER 24 K EN Get Device Stil SE AK ER EE Ee GE E GE ee Ee ie 24 3 12 Getlnterface Stats EER GE EE ee Ee EE aaa EE ee EE Gee GE RE DE Ee Ge Ee GEL eer ee 24 5 1 3 Get Endpoint 0 1 2 34 Status ee Pe ie dere eege gede N RR GN Dee STEE dE 24 5 1 4 Get Device Descriptor 18 Bytes ees see se ee Ge Re GR ee GRA Ge AR Ge Re GR ee RA Ge GRA Ge Re Gee Re eke ee 24 5 1 5 Get Configuration Descriptor 46 bytes 25 3 16 Get String Deserteur SERE GEE ee Ve EE sites chastise Re BEE De ee GE Ese sb REE Re ge a ea an gee Dies 27 3 1 7TGet String Descriptor d i EE tere Es ede ee de ege de ee ee by gesedeer ee dee 27 5 1 8 Get String Descriptor NE AE EE EE N RE OR EE 27 GAAS AGV NELIE DS AR OE ENEE 27 5310 Get EE 27 5 2 Control OUT TransactONS ee sees ee se ee ee Re RA AE ee RA AE ee RA AE
19. e ese se esse see se esse ee ese ee ee se ee 18 4 16 Address 13h EP3PKSZ Endpoint 3 Maximum Packet Size Register 18 4 17 Address 14h EP4DATA Endpoint 4 Transmit FIFO Data Register esse ee se esse sesse sees se ese ee ee se ee 18 4 18 Address 15h EP4COUNT Endpoint 4 Transmit FIFO Count Register sesse sesse see se ese ee ee se ee 18 4 19 Address 16h EP4STAT Endpoint 4 Transmit FIFO Status Register cee sesse see se esse se ese ee ee se ee 19 4 20 Address 17h EP4PKSZ Endpoint 4 Maximum Packet Size Register 19 4 21 Address 18h REVISION Revision Register 19 4 22 Address 19h USBSTAT USB Status Register 20 4 23 Address 1Ah FRAMEMSB Frame Counter MSB Register 20 4 24 Address 1Bh FRAMELSB Frame Counter LSB Register 20 4 25 Address 1Ch EXTIDX Extended Register Index iese esse ese se ee ee ee Re GR ee GR ee Gee Gee ee ee ee ee ee 20 4 26 Address 1Dh EXTDATA Extended Register Data 21 EPSON User s Manual USB Function Controller 4 26 1 Address 1Dh Index 00h VIDMSB Vendor ID Map 21 4 26 2 Address 1Dh Index 01h VIDLSB Vendor ID LS 21 4 26 3 Address 1Dh Index 02h PIDMSB Product ID MSB c ees ee se ee ee ee ee GR ee ee RR ee 21 4 26 4 Address 1Dh Index 03h PIDLSB Product ID LSB ees sees sees ee Ee ee Ge ee ee ee ee 21 4 26 5 Address 1Dh Index 04h RELMSB Release Number MSb se ke ee oe ee Ge ee ee 21 4 26 6 Address 1Dh Index 05h RELLSB Release Number LS 21 4 26 7 Ad
20. ee RA AE ee RA ee RA ee RA ee 28 ONE Si EE EE SE EE EO EER EE E 28 5 22 Set Comb aie ARE De EO EE RE EG 28 9 25 Set Intertacer 6243 RR EE EES GR EE EE GO EE ES RR Ee GE ES ROER a 28 5 2 4 Device Clear oe OO N OE N EO EO EE N N HE EE 28 3 25 DevicsSet Features GE ED EE GE E GE Ee Ge ed RO ee 28 5 2 6 Endpomt 0 1 2 3 4 Clear Features ses esse se ees REG DOE SG GEKEER Ge Ge eb ee se Ke GEE Ge SSES ENEE 28 5 2 7 Endpoint 0 1 2 3 4 Set Feature esse se se ea RA RA Re Ge ee ee ee ee Re Re GR Re ee Re GR ae GRA Gee Ga ee ee ee 29 5 3 Endpoint 1 OUT Transactions Receive MailboxeS esse see see ee ee ee se ee ee ee ee ee Re GR Re RR RA GR ee Gee 30 5 4 Endpoint 2 IN Transactions Transmit Mailboxes iis see ee ee Ge ee ee ee ee Re GR Re RR RA GR ee Gee 30 5 5 Endpoint 3 OUT Transactions Receive PlPO see sees se ee se ee se ee ee ee Re Ge ee ee Re GR Re RR ee de ee ee Gee 30 5 6 Endpoint 4 IN Transactions Transmit FIFO e esse see ese ee ee ee ee Ge ee Ge ee Ge ee ee ee ee ee ee ee Ge Re ee Re ee Re 30 6 Vendor Device Requests ur ee EERDER ES Ee Ee Dee Ee Ee ee A eel ed SEE EE Oe eer 30 6 1 Device Clear Feattire ie SG RE SO ee et ege e BEEN Eege GR EG De GE se 30 60 2 DEVICE Set Heature Ee SE Be ese ER cathe EE ee EE Di ene EE GR ued ons Ee bes ee oek se Ge DE ee ee Ge De 30 oi nt ER ARE EO EE EE EE OE aie 31 T Local Bus Writ to Reflst r EE Re DEERE IKE EDE SEE EED ES AD RE Ee De EES 31 7 2 Local
21. empty to 64 full EPSON 18 User s Manual USB Function Controller 4 19 Address 16h EP4STAT Endpoint 4 Transmit FIFO Status Register Default Bits Description Read Write Value E E ft E Transmit FIFO Valid If set this bit allows the data in the FIFO to be read by the next read from the host This bit is automatically cleared by a host read This bit is only used if bit 0 in register FIFOCTL is set Transmit FIFO Flush Writing to this bit causes the transmit FIFO to be flushed Reading this bit always returns a 0 Transmit FIFO Overflow If set this bit indicates that an attempt was made by the local CPU to write to the transmit FIFO when the transmit FIFO was full Writing a 1 clears this bit Transmit FIFO Underflow If set this bit indicates that an attempt was made by the USB host to read the transmit FIFO when the transmit FIFO was empty Writing a 1 clears this bit WW did Ed Transmit FIFO Full If set this bit indicates that the transmit FIFO is full Yes No 0 0 Transmit FIFO Empty If set this bit indicates that the transmit FIFO is empty 4 20 Address 17h EP4PKSZ Endpoint 4 Maximum Packet Size Register Default a Description Read Write Value Endpoint 4 Max Packet Size Register This register specifies the maximum packet size for endpoint 4 in units of 8 bytes default 64 bytes It can be read by the host through the endpoint 4 descriptor 4 21 Address 18h REVISION Revisio
22. et the selected device feature Value feature selector FS 1 gt Device Remote Wakeup enable Clear the selected endpoint feature Value feature selector Index endpoint number FS 0 gt Endpoint stall clears stall bit EPSON Default Value 28 User s Manual 5 2 7 Endpoint 0 1 2 3 4 Set Feature vc Set the selected endpoint feature Value feature selector Index endpoint number FS 0 gt Endpoint stall sets stall bit EPSON USB Function Controller Default Value 29 User s Manual USB Function Controller 5 3 Endpoint 1 OUT Transactions Receive Mailboxes Offse Number of Description Default Value t Bytes Host writes 8 bytes to the receive mailboxes using bulk OUT transactions 5 4 Endpoint 2 IN Transactions Transmit Mailboxes Offse Number of Description Default Value t Bytes Host reads 8 bytes from the transmit mailboxes using interrupt IN transactions 5 5 Endpoint 3 OUT Transactions Receive FIFO Offse Number of Description Default Value t Bytes up to 64 Host writes data into the receive FIFO using bulk or isochronous OUT transactions 5 6 Endpoint 4 IN Transactions Transmit FIFO Offse Number of Description Default Value t Bytes up to 64 Host reads data from the transmit FIFO using bulk or isochronous IN transactions 6 Vendor Device Requests 6 1 Device Clear Feature Number of Description Default Value Byte
23. evice Remote Wake Up The local CPU signals a device remote wake up by driving the WAKEUP_ input pin low The USBFC will send a 10 ms wake up signal to the USB host and drive OSC_RUN high and restart the clock input into CLK48_EARLY Two milliseconds after the WAKEUP_ pin is asserted the SUSP_ line is driven high to indicate that the USBFC has completed its wake up 3 3 3 Host Initiated Wake Up The host may wake up the USBFC by any non idle state on the USB The USBFC will detect the host s wake up request and drive OSC RUN high and restart the clock input into CLK48_EARLY Two milliseconds later the SUSP_ output signal is driven high to indicate that the USBFC has completed its wake up 3 4 USBFC Power Configuration The USB specification defines both bus powered and self powered devices A bus powered device is a peripheral which derives all of its power from the upstream USB connector while a self powered device has an external power supply The USBFC is well suited for both types of applications The most significant consideration when deciding whether to build a bus powered or a self powered device is power consumption The USB specification lays out the following requirements for maximum current draw e A peripheral not configured by the host signified on the USBFC by the DEVCFG_ output pin can draw only 100 mA from the USB power pins e A device may not draw more than 500 mA from the USB connector s power pins e In suspend mode
24. gister is held in the EXTIDX register Below Below Below 4 26 1 Address 1Dh Index OOh VIDMSB Vendor ID MSB EE EE er Bits Description Read Write Value EE ID MSB This register determines the most significant byte of the Vendor EIER EK EE during a Get Device Descriptor request 4 26 2 Address 1Dh Index 01h VIDLSB Vendor ID LSB EE Bits Description Read Write Value Ed Vendor ID LSB This register determines the least significant byte of the Vendor EIE SEL EE during a Get Device Descriptor request 4 26 3 Address 1Dh Index 02h PIDMSB Product ID MSB Mime EER Bits Description Read Write Value Fee Product ID MSB This register determines the most significant byte of the Product KEE SSC KEE Ets during a Get Device Descriptor request 4 26 4 Address 1Dh Index 03h PIDLSB Product ID LSB EE Bits Description Read Write Value Ed Product ID LSB This register determines the least significant byte of the Product EES EIE during a Get Device Descriptor request 4 26 5 Address 1Dh Index 04h RELMSB Release Number MSB Fe EE Bits Description Read Write Value Eid Release Number MSB This register determines the most significant byte of the EEE a EIE release number during a Get Device Descriptor request 4 26 6 Address 1Dh Index 05h RELLSB Release Number LSB Default a Description Kees Se Value EES Number LSB This register determines the least significan
25. icant bit LDOUT_OE_ Output Data Output Enable This active low output is true when the USBFC is driving the Data Output Bus LDOUT LA 4 0 Input Address Bus The local address bus is used by devices on the local bus to select registers within the USBFC CS_ Input Chip Select The chip select is used by devices on the local bus to enable access to registers within the USBFC This signal is ignored if DACK_ is asserted IOR_ Input VO Read The I O read strobe is asserted along with CS_ and LA 4 0 when a device on the local bus reads from an internal register or the FIFO It also allows the FIFO to be read during DMA transfers when DACK is asserted IOW_ Input VO Write The I O write strobe is asserted along with CS_ and LA 4 0 when a device on the local bus writes to an internal register or the FIFO It also allows the FIFO to be written during DMA transfers when DACK_ is asserted Output DMA Request This signal indicates to an external DMA controller that a byte should be transferred to from the FIFO During a transfer DRQ remains asserted until the DACK_ input goes active DACK_ Input DMA Acknowledge This signal from the external DMA controller is used to transfer data to from the FIFO in response to EPSON User s Manual USB Function Controller DRQ TOR and IOW_ determine the direction of the DMA transfer EOT_ Input DMA End of Transfer This signal from the external DMA controller is used to terminate a DMA transfer
26. is bit indicates when a start of frame packet has been Yes Yes CLR received by the USBFC This status bit is cleared by writing a 1 EE Yes EOT Interrupt Status This bit indicates when the EOT_ input has been asserted simultaneously with DACK_ and either IOR_ or IOW_ indicating the completion of a DMA transfer This status bit is cleared by writing a 1 Endpoint 4 Interrupt Status This bit indicates when a USB Endpoint 4 Data packet has been sent by the USBFC This status bit is cleared by writing a 1 USB Endpoint 3 Data packet has been received by the USBFC This status bit is cleared by writing a 1 Endpoint 2 Interrupt Status This bit indicates when the USB Endpoint 2 Mailbox registers have been read by the USB host This status bit is cleared by writing a 1 Endpoint 1 Interrupt Status Receive Mailbox Valid This bit indicates when the USB Endpoint 1 Mailbox registers have been written to by the USB host This status bit is cleared by writing a 1 Endpoint 3 Interrupt Status Receive FIFO Valid This bit indicates when a Yes CLR Yes CLR Yes CLR Yes CLR Yes CLR Upper Interrupt Active At least one interrupt status bit is set in the IRQSTAT2 a eS ee register 4 6 Address 03h IRQENB2 Interrupt Enable Register 2 Default Bits Description Read Write Value p12 Reserved ____ Yes No 9 Transmit FIFO Almost Empty Interrupt Enable When set this bit enables a local interrupt to be generated when the T
27. lk 11 Interrupt ze a Ze Maximum packet size of this endpoint 0x0008 EE Interval for polling endpoint not used EPSON 25 User s Manual Get Configuration Descriptor continued Number of Bytes Description Endpoint 2 Descriptor 1 1 Endpoint Address bit 7 direction 1 IN 0 OUT bits 6 4 reserved bits 3 0 endpoint number Endpoint Attributes bits 7 2 reserved bits 1 0 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 Maximum packet size of this endpoint 1 Interval for polling endpoint Endpoint 3 Descriptor l 1 Endpoint Address bit 7 direction 1 IN 0 OUT bits 6 4 reserved bits 3 0 endpoint number Endpoint Attributes bits 7 2 reserved bits 1 0 00 Control 01 Isochronous 10 Bulk 11 Interrupt Maximum packet size of this endpoint for bulk mode Bus Time for isochronous mode 1 Interval for polling endpoint Endpoint 4 Descriptor l l Endpoint Address bit 7 direction 1 IN 0 OUT bits 6 4 reserved bits 3 0 endpoint number Endpoint Attributes bits 7 2 reserved bits 1 0 00 Control 01 Isochronous 10 Bulk 11 Interrupt Maximum packet size of this endpoint for bulk mode Bus Time for isochronous mode 1 Interval for polling endpoint o i EI a N EPSON USB Function Controller Default Value 0x0008 Determined by Local Register EP2POLL 0x07 0x05 0x03 0x02 for bulk 0x01 for iso
28. n n T5 Datasetup to end of write enable 5 In T6 Lian hold time fromendofIOW 3 J n n T7 WidhofEOT_pulse see note 20 Io T8 DACK recovery time _ 20 LL n n T9 DMAreeoverytme o dl n Write enable is the occurrence of both IOW_ and DACK_ Note EOT_ IOW_ and DACK_ must be concurrently true for at least T7 for proper recognition for the EOT_ pulse EPSON User s Manual USB Function Controller 7 4 DMA Read from FIFO TI DRQfalse from DACK te 3 n n T2 DACK_falsetoDRQtue 9 In T3 DACK_hold time fromendof JOR 0 J n T4 Data access time from read enable LL 8 n T5 Datahold timefromendofIOR 9 J n n T6 Width of EOT pulse see note 20 Io T7 LDACK recovery time _ 20 LL n n T8 DMArecoverytime 20 dl n Read enable is the occurrence of both IOR_ and DACK_ Note EOT_ IOR_ and DACK_ must be concurrently true for at least T6 for proper recognition of the EOT_ pulse EPSON 34 User s Manual 8 Test Circuit
29. n Register ia il ace Default Bits Description a Value EIE Revision This register returns current silicon revision number of the ETES EPSON Current Revision 19 User s Manual USB Function Controller 4 22 Address 19h USBSTAT USB Status Register ae Bits Description Read Write Value Suspend Control If set this bit indicates that there is a pending suspend request Yes Clr from the USB host Writing a 1 clears this bit and causes the USBFC to enter suspended mode USB Endpoint 4 STALL The last USB IN token could not be serviced because Yes Clr the endpoint was stalled DCTL register bit 4 set and was acknowledged with a TALL Writing a 1 clears this bit JSB Endpoint 4 NAK The last USB packet transmitted IN packet encountered Yes Yes Clr FIFO underrun condition and was acknowledged with a NAK Writing a 1 clears this bit JSB Endpoint 4 ACK The last USB packet transmitted IN packet was Yes Yes Clr successfully acknowledged with an ACK from the USB host Writing a 1 clears this bit USB Endpoint 3 STALL The last USB packet received OUT packet could not Yes Yes Clr be accepted because the endpoint was stalled DCTL register bit 3 set and was acknowledged with a STALL Writing a 1 clears this bit USB Endpoint 3 NAK The last USB packet received OUT packet could not be Yes Yes Clr accepted and was acknowledged with a NAK The receive FIFO data will be corrupted and the local CPU should flush the F
30. n set this bit enables a local interrupt to Yes Yes Es er wen he USB on NE EER Rd Aid Mi SOF Interrupt Enable When set this bit enables a local interrupt to be set when a Yes Yes ENE EG 3 EOT Interrupt Enable When set this bit enables the local interrupt to be asserted Yes Yes IL 4 Endpoint 4 Interrupt Enable When set this bit enables a local interrupt to be set Yes Yes Ka when a USB Endpoint 4 Data Packet has been sent by the USBFC 3 Endpoint 3 Interrupt Enable When set this bit enables a local interrupt to be set E when a USB Endpoint 3 Data Packet has been received by the USBFC Endpoint 2 Interrupt Enable When set this bit enables a local interrupt to be set when the USB Endpoint 2 Receive Mailbox registers have been read by the USB host Endpoint 1 Interrupt Enable When set this bit enables a local interrupt to be set when the USB Endpoint 1 Transmit Mailbox registers have been written to by the USB host 0 Reserve es No o l EPSON 15 User s Manual USB Function Controller 4 5 Address 02h IRQSTAT1 Interrupt Status Register 1 NOTE These status bits are set independently of the corresponding interrupt enable bits these bits has no effect Writing a 0 to RE DEE Bits Description Read Write Value Suspend Request Interrupt Status This bit indicates when a suspend request has Yes Yes CLR been received by the USBFC This status bit is cleared by writing a 1 ed MES SOF Interrupt Status Th
31. ntil the USBENB bit in the DMA control register is set Until then the device enumeration process cannot complete so the device will not be recognized on the USB 4 2 Register Summary Address Register Register Description US Name Endpoint Cd Reserved S O EPIIDX Endpoint Index Register ___ EPI1IDX Endpoint 1 Index Register EPIDATA Endpoint 1 Receive Mailbox Data Port USB to Local B 5 7 erved i i 1 AB Reserved S O c EP2DATA Endpoint 2 Transmit Mailbox Data Port 2 ee a e E ara 3 1 13 4 15 17 1B EXTDATA Extended Register Data EIE el Mey zeen rn lr TIA gt o 00 a E EPSON 14 User s Manual USB Function Controller 4 3 Address 00h DCTL DMA Control Register Default Bits Description Read Write Value E SRR Sn NG 0 Software EOT This bit determines the response to an IN request from Endpoint 4 Yes Yes when the transmit FIFO is empty If either this bit or the DMA EOT input pin are asserted the USBFC responds to an In request from Endpoint 4 with an ACK and a zero length packet if the FIFO is empty If neither this bit nor the DMA EOT input are asserted the USBFC responds to an In request from Endpoint 4 with an NACK if the FIFO is empty indicating that it expects to transmit more data This bit can be cleared by an I O write with a data value of 0 Itis automatically cleared when the USBFC responds to the host with a zero length packet when the FIFO is emp
32. put indicates that an external power supply used for self powered mode is operational TEST Test For normal operation connect this pin to ground EPSON User s Manual USB Function Controller 3 Functional Description 3 1 USB Interface The USBFC is a USB function device and as a result is always a slave to the USB host All USB data transfers to and from the USBFC USB port are initiated by the USB host There are five USB endpoints associated with the USBFC e Endpoint 0 This control endpoint is used to initialize the device and provides access to USB configuration control and status registers e Endpoint 1 This endpoint supports bulk transfers from the USB host to the USBFC receive mailboxes e Endpoint 2 This endpoint supports interrupt transfers from the USBFC transmit mailboxes to the USB host e Endpoint 3 This endpoint supports bulk or isochronous data transfers from the USB host to the USBFC Receive FIFO e Endpoint 4 This endpoint supports bulk or isochronous data transfers from the USBFC Transmit FIFO to the USB host 3 2 Local Bus Bulk or isochronous data passes between the local bus and the USB bus through a pair of 64 byte FIFOs A CPU on the local bus can provide data to or accept data from the USB bus via the FIFOs in the USBFC A pair of 8 byte mailbox registers provide a means for the local and host CPUs to exchange messages The receive mailbox is implemented as a Bulk Data endpoint and the transmi
33. ransmit FIFO Almost Empty status bit is Receive FIFO Almost Full Interrupt Enable When set this bit enables a local interrupt to be generated when the Receive FIFO Almost Full status bit is set 4 7 Address 04h IRQSTAT2 Interrupt Status Register 2 NOTE These status bits are set independently of the corresponding interrupt enable bits these bits has no effect Writing a 0 to Default Bits Description Read Write Value 2 Reserved ______ Yes No_ 9 Transmit FIFO Almost Empty Status This bit is set when the number of bytes Yes Clr in the Transmit FIFO is equal to the Transmit FIFO Almost Empty Threshold and another byte is sent to the USB bus from the FIFO This status bit is cleared by writing a 1 Receive FIFO Almost Full Status This bit is set when the number of bytes in the Yes Clr Receive FIFO is equal to the Receive FIFO Almost Full Threshold and another byte is received from the USB bus into the FIFO This status bit is cleared by writing a 1 EPSON 16 User s Manual USB Function Controller 4 8 Address 08h EP1IDX Endpoint 1 Index Register Default Bits Description Read Write Value 7 3_ Reserved Ed Endpoint 1 Index Register This register determines which Endpoint 1 Receive Mailbox is accessed when the Endpoint 1 Receive Mailbox Data port is read This register is automatically incremented after the Endpoint 1 Receive Mailbox Data port is read This index register wrap
34. riptor The default is 500 mA OxFA 2 mA 4 26 11 Address 1Dh Index OAh PKTCTL Packet Control Default a Description Ss ni Value EP4 Data Toggle Bit Contains the value of the Data Toggle bit to be sent in 0x0 Ox1 response to the next IN token to endpoint 4 from the USB host Toggle EP3 Data Toggle Bit Contains the value of the Data Toggle bit expected in the next 0x0 Ox1 DATA packet to endpoint 3 from the USB host Toggle EP2 Data Toggle Bit Contains the value of the Data Toggle bit to be sent in 0x0 Ox1 response to the next IN token to endpoint 2 from the USB host Toggle EP1 Data Toggle Bit Contains the value of the Data Toggle bit expected in the next 0x0 Ox1 DATA packet to endpoint 1 from the USB host Toggle EP4 Data Toggle Mode When set this bit resets the Data Toggle bit to zero at the 0x0 end of a USB transfer from EP4 When cleared the Data Toggle bit strictly toggles EP3 Data Toggle Mode When set this bit resets the Data Toggle bit to zero at the 0x0 end of a USB transfer to EP3 When cleared the Data Toggle bit strictly toggles Reserved 0x0 EP1 Data Toggle Mode When set this bit resets the Data Toggle bit to zero at the end of a USB transfer to EP1 When cleared the Data Toggle bit strictly toggles EPSON 22 User s Manual USB Function Controller 4 26 12 Address 1Dh Index OBh LOCALCTL Local Side Control Default Bits Description Read Write Value 7 1 Reser
35. s Clear the selected device feature Value feature selector FS 0x80 gt Timing test mode clears test bit Set the selected device feature Value feature selector FS 0x80 gt Timing test mode sets test bit EPSON 30 User s Manual USB Function Controller 7 Timing 7 1 Local Bus Write to Register TI Address setup to writeenable 10 In T2 __ Address hold from end of write enable Lu fJ n T3 Writeenable width 53 J n n T4 Chip selectholdfromendofJOW_ J n T5 Datasetup to end of write enable 5 J n n T6 Lian hold time fromendofIOW 5 J n n T7 WORecoveryTime CT o n e Write enable is the occurrence of both JOW and CS_ EPSON 31 User s Manual USB Function Controller 7 2 Local Bus Read from Register NAME DESCRIPTION UNIT TI Address setuptoreadenable JL J0 LL nm T Address hold fromendofreadenable 0 nm T3 Chipselecthold fromendofJOR_ 0 J n T4 Dataaccess time from read enable 8 n T5 Datatri state time from endof1OR 9 J n n T6 WORecoveryTime CT o Im e Read enable is the occurrence of both IOR_ and CS_ EPSON 32 User s Manual USB Function Controller 7 3 DMA Write to FIFO TI LDRO false fromDACK_tme LL 383 n n T2 LDACK fasetoDROWue LL 2 J n n T3 Writeenablewidth 20 n T4 DACK_hold fromendof FOWL 0 J
36. s around to zero when it reaches the maximum count 4 9 Address 09h EP1DATA Endpoint 1 Receive Mailbox Data Default Bits Description Read Write Value Yes USB 0 7 0 Endpoint 1 Receive Mailbox Data This port is used to read data from one of the receive mailbox registers Data is returned from the register selected by the Endpoint 1 Index Register The eight receive mailbox registers are written by a USB bulk transfer to endpoint 1 and can be used to pass messages from the USB host to the local CPU The format and content of the messages are user defined If enabled USB writes to this register can generate a local interrupt 4 10 Address 0Ch EP2IDX Endpoint 2 Index Register Default Bits Description Read Write Value 7 3_ Reserved _ ____ _Yes NO 0 2 0 Endpoint 2 Index Register This register determines which Endpoint 2 Transmit Mailbox is accessed when the Endpoint 2 Transmit Mailbox Data Port is read or written This register is automatically incremented after the Endpoint 2 Transmit Mailbox Data port is read or written This index register wraps around to zero when it reaches the maximum count 4 11 Address ODh EP2DATA Endpoint 2 Transmit Mailbox Data Default Bits Description Read Write Value Endpoint 2 Transmit Mailbox Data This port is used to read or write one of the transmit mailbox registers The register being accessed is selected by the Endpoint 2 Index Register The eight Transmit Mailbox Regi
37. s in the block to be transferred After the DMA controller has been programmed the DMA request enable bit is set in the USBFC As long as there is space available in the FIFO and the byte count is non zero the USBFC will request DMA transfers by asserting DRQ The DMA controller then EPSON 10 User s Manual USB Function Controller reguests the local bus from the local CPU After the DMA controller has been granted the bus it drives a valid memory address and asserts DACK MEMR_ and IOW_ thus transferring a byte from memory to the USBFC Transmit FIFO After the DMA has been started the local CPU can signal the USB host to start a bulk read using endpoint 2 Isochronous packets occur at pre arranged intervals so no signaling is required The USB host sends an IN token to the USBFC and starts a USB bulk or isochronous data transfer from the transmit FIFO The DMA transfers continue until the DMA byte count reaches zero An interrupt can be generated to the local CPU when the DMA has finished When the transmit FIFO becomes empty the USBFC will terminate the packet with an EOP end of packet signaling that there is no more data available Once an end of packet occurs an interrupt can be generated to the local CPU The local CPU can read a status port to detect whether the packet was acknowledged with an ACK from the host or whether the USBFC responded to the IN token with a NAK or STALL If none of these acknowledge bits are set then a
38. sters are written by the local CPU and are read by a USB interrupt transfer from endpoint 2 They can be used to pass messages from the local CPU to the USB host The format and content of the messages are user defined If enabled USB reads from this register can generate a local interrupt 4 12 Address 0Eh EP2POLL Endpoint 2 Interrupt Polling Interval Register Default Bits Description Read Write Value Interrupt Polling Interval Register This register specifies the Endpoint 2 OxFF interrupt polling interval in milliseconds It can read by the host through the endpoint 2 descriptor EPSON 17 User s Manual USB Function Controller 4 13 Address 10h EP3DATA Endpoint 3 Receive FIFO Data Register Default Bits Description Read Write Value 7 0 Endpoint 3 Receive FIFO Data Register This register is used by the local CPU to read data from the USB receive FIFO The FIFO is written by the USB host using bulk or isochronous transfers to endpoint 3 4 14 Address 11h EP3COUNT Endpoint 3 Receive FIFO Count Register PA Fe Fe EL Bits Description Read Write Value GEN Receive FIFO Count This register returns the number of receive FIFO entries ae a ESE valid entries Values range from 0 empty to 64 full 4 15 Address 12h EP3STAT Endpoint 3 Receive FIFO Status Register Default Bits Description Read Write Value 1 5 _ Reserved EES EES Not Receive FIFO Flush Writing to this bit causes the receive
39. t byte of the 0x00 EET revision code during a Get Device Descriptor request EPSON 21 User s Manual USB Function Controller 4 26 7 Address 1Dh Index 06h RCVAFTH Receive FIFO Almost Full Threshold Default Bits Description Read Write Value 76 Reserved _ ____ _Yes Ne 0x00 __ 0 Receive FIFO Almost Full Threshold This register determines the threshold at which the receive FIFO almost full status bit is set 4 26 8 Address 1Dh Index 07h XMTAETH Transmit FIFO Almost Empty Threshold Default Bits Description Read Write Value 5 0 Transmit FIFO Almost Empty Threshold This register determines the threshold Yes Yes 0x04 at which the transmit FIFO almost empty status bit is set 4 26 9 Address 1Dh Index 08h USBCTL USB Control Default Bits Description Read Write Value 7 1 Reserved tes No mm USB String Enable When set this bit allows the default Vendor and Product ID Yes Yes 0x1 String Descriptors to be returned to the host When this bit is cleared the string index values in the Device Descriptor are set to zero and string descriptor reads are acknowledged with a stall 4 26 10 Address 1Dh Index 09h MAXPWR Maximum Power Consumption PE Bits Description Read Write Value Maximum Current The amount of current drawn by the peripheral from the USB ee cae eg port in increments of 2 mA The USBFC reports this value to the host controller in the configuration desc
40. t mailbox as an Interrupt endpoint 3 2 1 CPU Controlled USB to Local Bus Transfers For host to device transfers the local and host CPUs first arrange to transfer a block of data from host memory to local shared memory The USB host performs a bulk or isochronous data transfer over the USB bus to the receive FIFO in the USBFC If the FIFO fills up during a bulk transfer the USBFC will return a USB NAK acknowledge to the host signaling that the data could not be accepted Packet data which is in the FIFO or has already been read by the CPU should be discarded If the local CPU has stalled this endpoint the USBFC will not store any data into the FIFO and will respond with a STALL acknowledge The local CPU can either start polling for valid FIFO data immediately after setting up the transfer with the USB host or can wait for a packet complete interrupt As the FIFO is filling up from the USB side the local CPU can poll the FIFO status register to determine when a byte is available Otherwise it can wait until the packet complete interrupt and read the entire packet at once Once an end of packet occurs an interrupt can be generated to the local CPU The local CPU can read a status port to detect whether the packet was acknowledged with an ACK NAK or STALL If none of these acknowledge bits are set then a timeout has occurred For NAK or timeout conditions at the completion of bulk transfers the USB host will send another OUT token and
41. the USBFC should receive the same packet again 3 2 2 CPU Controlled Local Bus to USB Transfers For device to host transfers the local CPU first writes the data block from local memory into the transmit FIFO While writing data into the USBFC the local CPU must keep track of whether there is space available in the FIFO by monitoring the Transmit FIFO Count register EPSON User s Manual USB Function Controller After the block has been loaded into the transmit FIFO the local and host CPUS arrange to transfer the block of data from the transmit FIFO to host memory The USB host sends an IN token to the USBFC and starts a USB bulk or isochronous read from the transmit FIFO The CPU writes and USB read operations could occur concurrently if the local CPU can provide data at a fast enough rate to keep up with the USB bus When the transmit FIFO becomes empty the USBFC will terminate the packet with an EOP end of packet signaling that there is no more data available Once an end of packet occurs an interrupt can be generated to the local CPU The local CPU can read a status port to detect whether the packet was acknowledged with an ACK from the host or whether the USBFC responded to the IN token with a NAK or STALL If none of these acknowledge bits are set then a timeout has occurred For NAK or timeout conditions at the completion of bulk transfers the USB host will send another IN token and the USBFC should re transmit the same packet
42. ty USB Enable Any device or configuration descriptor reads from the host will be Yes Yes acknowledged with a NAK until this bit is set This allows time for the local CPU to set up the interrupt polling register maximum packet size registers and other configuration registers e g Product ID and Vendor ID before the host reads the descriptors Endpoint 4 Stall If this bit is set host bulk reads from the transmit FIFO will result Yes Yes in a STALL acknowledge by the USBFC No data will be returned to the USB host Endpoint 3 Stall If this bit is set host bulk writes to the receive FIFO will result in Yes Yes a STALL acknowledge by the USBFC Receive data will be discarded DMA Request This status bit reflects the state of the DRQ output pin and allows a CPU on the local bus to monitor DMA transfers DMA Request Enable Writing a 1 to this bit causes the USBFC to start requesting DMA cycles from a DMA controller on the local bus If the POT input is asserted this bit is automatically reset A CPU on the local bus may also explicitly reset this bit to terminate a DMA transfer This bit can be read to determine whether a DMA transfer is still in progress DMA Direction This bit determines the direction of data flow during a DMA transfer 1 Local bus to USB 0 USB to Local bus 4 4 Address 01h IRQENB1 Interrupt Enable Register 1 EE EE EE EIE Bits Description Read Write Value 7 Suspend Request Interrupt Enable Whe
43. ved es No w Local Clock Output This bit controls the output of the LCLK pin Yes Yes 0x0 0 48 MHz clock derived from CLKIN signal 1 12 MHz clock derived from USB bitstream for testing purposes 4 26 13 Address 1Dh Index OCh FIFOCTL FIFO Control Default a Description Write Value Reserved Transmit FIFO Valid Mode When set this bit causes a NAK response to a host read request from the transmit FIFO EP4 unless the FIFO Valid bit in register EP4STAT is set When this bit is cleared any data waiting in the transmit FIFO will be sent in response to a host read request and the FIFO Valid bit is ignored EPSON 23 User s Manual USB Function Controller 5 Standard Device Requests 5 1 Control IN Transactions 5 1 1 Get Device Status vc GE bits 15 2 Reserved 0x0001 bit 1 Device Remote Wakeup enabled bit 0 Device is operating in Self Powered mode depends on PWRGOOD_ input pin 5 1 2 Get Interface Status Number of Description Default Value Bytes po 2 bits 15 0 Reserved EE 5 1 3 Get Endpoint 0 1 2 3 4 Status Number of Description Default Value Bytes bits 15 1 Reserved 0x0000 bit 0 Endpoint is stalled 5 1 4 Get Device Descriptor 18 Bytes vc EE H LJ Llegb KI 0x00 0x00 0x08 Vendor ID Determined by Local Register VIDMSB VIDLSB 2 Product ID Determined by Local Register PIDMSB PIDLSB 2 Device Release Number Determined by Local Register PIDMSB PID
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