R8C Family Implementing Interrupts in MR8C/4
Contents
1. CENESAS APPLICATION NOTE R8C Family R20AN0088ES0100 Rev 1 00 Implementing Interrupts in MR8C 4 Mar 01 2010 Introduction The ability to handle multi tasks simultaneously is important in embedded systems Such capability is achieved by having external hardware devices that perform device specific operations in parallel to the core processor This concurrency is achieved using interrupts RTOSs handle interrupts in different ways and require varying methods of implementing interrupt handlings This document describes interrupts Renesas R8C family interrupts architecture and how they are implemented in MR8C 4 their impact on scheduling and real time and some interrupt management strategies Target Device Applicable MCU R8C Family Contents 1 GuUIde IN USING this DOCUMENE vezsicccctscccecccessndedoceccdscndsecctecttcuedsdecedede catdeedasdeoceteccedeedacunedsndedduadabedaatetsts 2 2 Introduction to Interrupts in Embedded SystemS ccccccecccssseeeeeeceeeeeeeeeeeeceeeseaaeeeeeessaaeeeeeesaaees 3 3 Overview of Renesas R8C Family Interrupts ArchiteCtures cccccseeecceeeceeeeeeeeesaeeeeesseeeeeeesenaaees 5 4 Understanding RTOS Interrupt Architecture ccccccccccseeeseeeeeeeeeaeseeeeeeeeseseaeeeeeeeeeeesseeeeeeeeeessaaas 10 5 Implementing Interrupts in MR8C 4 0 eee ccccecccsseseeeeeeeeeeeaeeeeeeeeeeeeseeeeeeeeesessseaseeeeeeeeessaaaaeseeeeees 13 6 Reference DOCUMGING vac aiicies died tondseactsas2. 1 2 3 Avoid improper usage of RTOS service calls in ISRs 4 5 Keep interrupt disabling regions as short as possible R8C family devices leverage on an efficient and versatile instruction set and register architecture Equipped with fast instruction execution time which has 20 out of total 89 instructions that execute in a single cycle powerful mathematical instructions and frequently used instructions MOV ADD SUB JMP that are just 1 byte long interrupt latency incurred by R8C MCUs is minimal MR8C 4 provides an adequate set of absolutely necessary and deterministic RTOS service calls that can be executed from ISRs This gives users the convenience and ensures improper RTOS service calls are not used in ISRs By employing unified interrupt architecture MR8C 4 ensures interrupt disabling regions are kept sufficiently short 5 Implementing Interrupts in MR8C 4 MR8C 4 RTOS provides a flexible interrupt control mechanism that is fast and deterministic with the following characteristics e Options to create interrupt handlers in C or Assembly e Selection for OS dependent kernel or OS independent non kernel interrupts e Support for nested interrupts e Support up to 7 priority levels Highest priority at 7 e Execute at higher precedence than dispatcher e Execute in own independent contexts non task e Dedicated interrupt stack 5 1 Understanding Interrupt Processing in MR8C 4 There are basically three different kind of s
3. Comparator A 5 Resets Figure 3 Fixed Vector Tables of R8C Lx Devices Software Interrupt Vector Addresses 1 Address L to Address H BRK instruction 3 0 to 3 0000h to 0003h Flash memory ready 4 to 7 0004h to 0007h Interrupt Source Number Reswen O O OOO O S o O 20 to 23 0014h to 0017h 24 to 27 0018h to 0O1Bh 40 to 43 0028h to 002Bh UART2 transmitiNACK2 T 9 UART receivelACK2 Synchronous serial 60 to 63 003Ch to OOSFh communication unit 2C bus interface Reserve OSS y UART receive 72 to 75 0048h to O04Bh UART1 transmit 76 to 79 004Ch to OD4Fh Reserved O 96 to 99 0060h to 0063h Resne Reese SSOSC SSOSCSS 116 to 119 0074h to 0077h INTO 120 to 123 0078h to OOF Bh 7 1 0 1 2 m j my m a ra 5 6 2 29 UART 2 bus collision detection 30 Reserved o Software 126 to 131 0080h to 0083h to 164 to 167 00A4h to DIAT Reserved O 172 to 175 00ACh to OOAFh 32 to 41 ri Reseved o Voltage monitor 2 comparator A2 Reserved Software 224 to 227 OOEOh to OOESh to 252 to 255 00FCh to OOFFh 50 51 a2 to 55 56 to 63 a ts to a il s fs fe ta ia bao oo ae i f Las Interrupt Coniral Reference Register R Tiny Series Software Manual FMRDYIC Flash Memory re INTFIC 35 l 25 Serial Interface UART2 ADIC 30 AD Conv
4. recoverable hardware errors methods for system debugging and special case handling such as system resets R20AN0088ES0100 Rev 1 00 Page 4 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 3 Overview of Renesas R8C Family Interrupts Architectures In the pITRON4 0 specification implementation of an interrupt handler is generally dependent on the processor interrupt architecture and the Programmable Interrupt Controller PIC As MR8C 4 conforms to uITRON4 0 specification and specifically designed for R8C family devices users are required to understand the interrupt architectures of the R8C family devices in the setup of interrupt handlers and interrupt service routine For R8C family devices there are two main types of interrupts Software and Hardware For hardware interrupt it is further categorized into Special and Peripheral I O interrupts as shown in Figure 2 Undefined instruction UND instruction Software J Overflow INTO instruction nonmaskable interrupt j BRK instruction INT instruction oe Watchdog timer Oscillation stop detection Special Single step nonmaskable interrupt Address match Hardware s Peripheral 1 01 maskable interrupt Notes 1 Peripheral function interrupts are generated by the peripheral functions built into the microcomputer system 2 This is a dedicated interrupt for development support tools Do not use this interrupt Figure 2 Classifications o
5. 10 RENESAS R8C Family Implementing Interrupts in MR8C 4 2 Introduction to Interrupts in Embedded Systems 2 1 Why Interrupts To satisfy end consumers increasingly demands more functionality is consistently added to the embedded system As the functional requirements proliferate size of the software grows Thereby it becomes more difficult to ensure that time critical items e g capture data from external inputs are performed properly Interrupts was introduced to handle this problem Interrupt signals an event to the microprocessor to instruct it to stop what it is doing and handle the incoming task 2 2 Types of Interrupts There are two types of interrupts Hardware and Software Software interrupts are generated from software through the issuance of a specified command Hardware interrupts are triggered by peripherals and external devices connected to the microprocessor 2 3 Interrupts Components 2 3 1 Programmable Interrupt Controller PIC PIC is a device that accept and prioritize multiple interrupt sources so that the highest priority interrupt is directed to core CPU for processing at any point of time In addition PIC helps core CPU to determine an interrupt s exact source 2 3 2 Interrupts Service Routine ISR ISRs are software routine that handle and process interrupt requests as specified by users When an interrupt is generated processor breaks away its present task switch to interrupt stack pointer
6. 2 Reserved bi 1 ag l OU defined MEE aagi Using service calls loc_cpu and unl _cpu to enable disable NT 1 interrupt fHinclude lt itron h gt Hinclude lt kernel h gt fHinclude kernel _itd h oe taski YP_INT stacd intlic 0x03 sDefine INT 1 erieritv 2 47 ercd loc_cpu Kernel interrupts disabled ercd unl_cpu Kemel interrupts enabled Figure 22 Enable Disable Kernel Interrupts R20AN0088ES0100 Rev 1 00 Page 19 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 5 4 Coding Interrupts in C Language 5 4 1 Defining Interrupt Vector Tables Figure 23 illustrates the definition of vector tables in c_sec inc file for R8C Lx devices __ITNT_ ECTOR section INTERRUPT YECTOR ___ Defines Relocatable Vector org Of d00H _ Table to starts from 0fd00H INT VECTOR Section FIX _INTERRUPT_YECTOR _ Defmes Fized Vector Table Org OFFOSH ___ te starts from Offd8H reserved addr OFFFFFFH OFS byte OFFH SWOT disable Important lt OTSres OFFH To disable Watchdog Timer Interrupt Figure 23 Defining Vector Tables in c_sec inc in C Language 5 4 2 Writing Kernel Interrupt Handler Step 1 Define kernel mask level The kernel mask level is defined in configurator file e g template cfg under the system definition ff System Definition system stack size 400 alae pr
7. OrFFanwoorrem SST SCCCSCSC SY Reserved OFFFantoOFFFBn a SSCS Reset__ _ OFFFCht0OFFFFn a RS Relocatable Interrupt Vector Table Vector Addresses 1 Software Interrupt Interrupt Source Address L to Address H Interrupt Control Reference a Number Register me O S a O Sofware Manual Reserved E C 28 to 31 001Ch to 001Fh TRCIC 20 Timer RC 32 to 35 0020h to 0023h iss TRDOIC 21 Timer RD 36 to 39 0024h to 0027h TRD1IC 40 to 43 0028h to 002Bh TREIC 44 to 47 002Ch to 002Fh S2TIC 48 to 51 0030h to 0033h S2RIC 1 0 1 2 52 to 55 0034h to 0037h 3 KUPIC 12 5 Key Input Interrupt 4 5 6 z 3 g a O a ajol ct lt alala 5 ass 3 ajajad gt mojo 3 56 22 Timer RE UART2 transmit NACK2 25 Serial Interface UART2 UART2 receive ACK2 A D conversion 56 to 59 0038h to O03Bh ADIC 30 A D Converter Synchronous serial 60 to 63 003Ch to 003Fh SSUICIIIC 27 Synchronous Serial communication unit Communication Unit SSU 12C bus interface 2 28 12C bus Interface Reserved 34 Serial interave UART 77210 75 0048h to 0046h Dor 1 76 to 79 004C to O04Fh UART1 receive 80 to 83 0050h to 0053h 20 84 to 87 0054h to 0057h 21 INT2IC 88 to 91 0058h to 005Bh 22 TRAIC 24 12 4 INT Interrupt Ce A E A Reserved a E 116 to 119 0074h to 0077h INTOIC U2BCNIC Reserved Cd 2 i 3 50 alalis zZ 3j4 N g a P wn a 5 Reserve
8. R8C family refer to Figure 10 They are 1 Define interrupt service routine for the hardware interrupt To be executed by user 2 Register interrupt service routine in interrupt vector table Automatically generated by compiler R20AN0088ES0100 Rev 1 00 Page 9 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 T a Preprocessor directive to pragma interrupt timer refyect 1 0 define interrupt handler void timer re void i interrupt routine for Timer RE peripheral interrupt handling codes interrupt i section vector ROMDATA org VECTOR ADR df 0 tword dummy int vector word dummy int vector 1 dword dummy int vector 2 Registering interrupt word dummy_int vector 3 handler for peripheral word dummy int vector 4 Timer RE word dummy int vector word dummy int vector 6 dummy int vector 7 dummy int vector 3 vector 10 dummy if vector 11 tword dummy int vector 12 tword dummy int vector 13 tword dummy int vector 14 Figure 10 Writing Hardware Interrupts 4 Understanding RTOS Interrupt Architecture Interrupts are part of a mechanism provided by embedded processor architectures to allow for disruption of processor s normal execution path and attend to external events Generally handling of interrupts in an embedded application with RTOS is implemented in two layers namely RTOS layer first layer and application layer second layer R20AN0088ES0100
9. Rev 1 00 Page 10 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 The RTOS layer being the first layer functions as an interrupt handler in accepting the control of an interrupt when it occurred Upon receiving the control the RTOS interrupts handler calls the application layer interrupt service routine corresponding to the interrupt for processing 4 1 RTOS Interrupt Architecture Design Challenges Generally there are two fundamental challenges in the designing of RTOS interrupt architecture The first challenge 1s to ensure the integrity of internal RTOS data when servicing interrupt s The second challenge is to achieve a deterministic and low interrupt latency that will not affect the real time performance of the system 4 1 1 Challenge 1 Ensure Integrity of Internal RTOS Data A major challenge in RTOS design involves supporting asynchronous access by interrupt routines and RTOS service calls to internal RTOS data structures An ISR or RTOS service call while modifying a data structure should not be allowed to be interrupted that allows a different ISR or RTOS service call to make unrelated modifications to the same data structure as shown in Figure 11 CODES A Read RTOS data Z and store value in local variable T E Decrement variable T C Store variable T value in RTOS data Z D Read RTOS data 2 and store value in local variable x E Increment variable x F Store variable x value in R
10. TOS data Z Figure 11 Race Condition of Interrupts Unified and segmented interrupt architectures are two common approaches to prevent corruption to internal RTOS data structures by interrupt service routines ISRs and RTOS service calls In unified interrupt architecture refer to Figure 12 interrupts are temporarily disabled when ISR or RTOS service calls is accessing the critical sections of code data This prevents other interrupts from making uncoordinated changes to the same critical sections R20AN0088ES0100 Rev 1 00 Page 11 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 All interrupt processing is done in ISR Figure 12 Unified Interrupt Architecture In segmented interrupt architecture interrupts are not disabled during ISR To prevent interrupts occurring during ISR from accessing the same RTOS data structure and thereby corrupting it segmented architecture disable the application scheduler and divide the ISR into two or more pieces as shown in Figure 13 Jnterrupt processing is split into multiple pieces Le SAI amp SK2 JSAl behaves like traditional ISR but does not access RTOS data JSA2 performs RTOS data access at application level under scheduler control Figure 13 Segmented Interrupt Architecture In unified interrupt architecture approach interrupt latency is introduced while the interrupts are temporary disabled Additional system resources are also required for t
11. and points to its ISR to process the interrupt Execution control is returned to the main program when the ISR completed 2 3 3 Interrupt Vector Table Interrupt vector table carries a list of all interrupt service routine and their corresponding properties e g priority level address descriptions etc that define the dynamic characteristics of the interrupt sources Interrupt vector table provides processor the means to jump into the ISR of the corresponding interrupt by extracting its ISR address listed in the table R8C family devices consist of two interrupt vector tables fixed and relocatable interrupt tables shown in Figure 1 R20AN0088ES0100 Rev 1 00 Page 3 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 Fi tV Tab Vector Addresses Interrupt Source Address L to H Remarks Reference Undefined instruction OFFDCh to OFFDFh Interrupt with R8C Tiny Series Overflow OFFEOh to OFFE3h Interrupt with BRK instruction OFFE4h to OFFE7h If the content of address OFFE7h is FFh program execution starts from the address shown by the vector in the relocatable vector table Address match OFFE8h to OFFEBh 12 6 Address Match Interrupt Single step 1 OFFEChtoOFFEFh i Watchdog timer 15 Watchdog Timer Oscillation stop detection 9 Clock Generation Circuit Voltage monitor 1 6 Voltage Detection Circuit comparator A1 32 Comparator A Voltage monitor 2 comparator A2 Address break 0
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13. askable interrupts are used to response to events triggered by peripherals built into the microcomputer MCU system With the types of peripheral features vary with each R8C model so do the types of Peripheral I O interrupts For R8C family software interrupt numbers are appended to the peripheral I O interrupts This implies MCU will execute the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt is generated Figure 9 shows few of peripheral I O interrupts available for R8C Lx devices R20AN0088ES0100 Rev 1 00 Page 8 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 R C22 23 Group R8 amp CLX Group outa Interrupt Source Interrupt Source pas cg 1 CANOWakew 3 Fme 3 CANO Successful wansmit 5 Timer s 4 CAN0 Enor O s rmen O S Timer RD Chonn 8 Time ooo Ce Timer RD Channel 9 UART manema O Ce kym n keym nn Co fao O OOO ADeowean o Clock Synchronous Serial I O synchronous serial with Chip Select 12C bus communication unit I C bus Interface interface a E E S i7 TART bus colbzion ue recoon 18 a t a Figure 9 Comparing Peripheral I O Interrupts of R8C22 23 and R8C Lx Devices 3 2 3 Writing Hardware Interrupts For hardware interrupts only peripheral interrupts that resides in relocatable vector table may be defined by users There are two steps involved in writing a hardware interrupt in
14. cally designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire contro
15. cbeasavenduatieccawantennienliudaselsieeduuliessadeeiedeandabaneduasdacdeisietbesters 26 R20AN0088ES0100 Rev 1 00 Page 1 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 1 Guide in using this Document This document aims to equip users with the confidence and capability of implementing interrupts in MR8C 4 With sufficient coverage ranging from introduction of interrupts in embedded systems to an overview of Renesas R8C Family interrupt architectures users will be able to relate the explanation on the implementation of interrupts in MR8C 4 for the R8C Family devices Table 1 Explanation of Document Topics Topic Objective Introduction to Interrupts in Embedded Systems Fundamental knowledge in embedded A basic introduction to interrupts systems Overview of Renesas R8C To reinforce users understanding on Knowledge in Microcontroller Family Interrupts the interrupt architectures of R8C Architectures Family devices Provide a brief overview of interrupts Knowledge in RTOS implementation in RTOS and its associated challenges and concerns Understanding RTOS Interrupt Architecture Knowledge in interrupts architecture of Implementing Interrupts in Guide users in the implementation of MR8C 4 interrupts in MR8C 4 R8C Family devices Listing of documents that equip users Reference Documents with knowledge in the pre requisite requirements R20AN0088ES0100 Rev 1 00 Page 2 of 27 Mar 01 20
16. ce 3 1 Software Interrupts Software interrupts refers to interrupt requests that are put up by instructions in the R8C instruction set Figure 6 provides a list of software interrupts for R8C22 23 devices Activation Method Undefined When an UND Instruction instruction is executed Interrupt Overflow Interrupt When an arithmetic operation overflow When a BRE instruction ig executed BRE Interrupt When an INT INT Instruction instruction followed by Interrupt an interrupt number 0 to 63 is executed Location Maskable Property Fixed vector table NM on maskabl OFFDCh to 0FFDFh mEnE R Fixed vector table Non maskabl OFFEOh to OFFE3h Paneth ee Fixed vector table Non maskabl OFFE4h to OFFE7h aii Relocatable vector n i 75 Chip Non maskable 0 to 63 Figure 6 Types of Software Interrupts The maskable property of INT instruction interrupt differs for R8C Lx devices In R8C Lx devices software interrupt numbers 0 to 31 and 42 to 55 are maskable whereas software interrupt numbers 32 to 41 and 56 to 63 are non maskable 3 1 1 Writing Software Interrupts With reference to the software interrupts listing in Figure 6 only INT instruction interrupt that resides in relocatable vector table may be defined by users Therefore software interrupts are written by defining the INT number as illustrated in Figure 7 R2Z0AN0088ES0100 Rev 1 00 Mar 01 2010 Page 7 of 27 CENESAS R8C Fam
17. cenarios of interrupt processing in MR8C 4 1 Interrupt occurs when processing task refer Figure 14 2 Interrupt occurs when processing service call refer Figure 15 3 Interrupt occurs within interrupt handler refer Figure 16 R20AN0088ES0100 Rev 1 00 Page 13 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 Current MR amp C 4 Interrupt Handler Task of Execution Interrupt Service Routine Figure 14 Interrupt Occurring when Processing Task Current MR8C 4 MR8C 4 Service Interrupt Handler Task of Execution Call Execution Interrupt Service Routine Interrupt Savic Call Interrupt Processing Processing Figure 15 Interrupt Occurring when Processing Service Call R20ANO0088ES0100 Rev 1 00 Mar 01 2010 tENESAS Page 14 of 27 R8C Family Implementing Interrupts in MR8C 4 Current MR8C 4 Interrupt Handler1 Interrupt Handler2 Task of Execution Interrupt Service Routinel Interrupt Service Routine2 Interrupt Processing Interrupt Interrupt Processing Figure 16 Interrupt Occurring within Interrupt Handler 5 2 Defining Kernel Non Kernel Interrupts In MR8C 4 interrupts are classified into kernel and non kernel types A kernel interrupt allows kernel service calls to be issued within its ISR Longer interrupt processing time will be incurred for kernel interrupts as their ISRs can only be completed after the service calls within the ISRs are being processed refer to F
18. d 12 4 INT Interrupt 25 Serial Interface UART2 R8C Tiny Series Software Manual Software 3 128 to 131 0080h to 0083h to 32 to 41 164 to 167 O0A4h to 00A7h TRGIC 23 Timer RG Reseved Ed Reserved 4 to 9 Voltage monitor 1 comparator A1 VCMP1IC 6 Voltage Detection Circuit Voltage monitor 2 comparator A2 32 Comparator A Reserved ebs Software 3 224 to 227 00E0h to OOESh to 56 to 63 R8C Tiny Series 252 to 255 OOFCh to OOFFh Software Manual Figure 1 Interrupts Vector Tables of R8C Lx Devices 2 3 4 Interrupt Priority Level To facilitate nested interrupts a priority level is generally provided for each interrupt An interrupt priority level IPL is assigned by users to individual interrupts to represents how critical the interrupt is When two interrupts happen at the same time the higher priority interrupt will take precedence over the lower priority one 2 3 5 Masked Unmasked Interrupts A processor can mask or block interrupts requests to perform a task Hardware interrupts can be further categorized into maskable interrupts IRQ and non maskable interrupt NMI IRQs are interrupts that can be disabled to let higher priority ISRs be executed uninterruptedly Interrupt masking is usually done by clearing the Interrupt Enable Flag NMI is a special type of interrupt that cannot be disabled by standard masking technique and is typically used to signal attention for reporting of non
19. e include lt itron h gt include lt kernel h gt MRSC 4 files to be included include kernel_id h void onfigurelnterrupts void INT1 mterrupt priority level defined at 6 Intlen 1 higher than system IPL iat hie vt oa Function name of interrupt handler vord must be specified for both return value and ii INT_INTI void e ricaiaie Processing starts No service calls may be issued withm the non kemel interrupt handler Processing ends Figure 29 Defining Interrupt Handler R20AN0088ES0100 Rev 1 00 Page 22 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 5 5 Coding Interrupts in Assembly Language 5 5 1 Defining Interrupt Vector Tables Figure 30 illustrates the definition of vector tables in asm_sec inc file for R8C Lx devices VECTOR TABLE _INT_VECTOR Defines Kelocatable Vector ARC i a S Table to starts from OFDOQH INT VECTOR SECTION FIX INTERRUPT YECTOR Defines Fixed Vector Table Org UFFUSH lt gt to starts from 0FFD8H reserved addr OFFFFFFH OFS byte UFFH Important ils FFE o To disable Watchdog Timer Interrupt Figure 30 Defining Vector Tables in asm_sec inc 5 5 2 Writing Kernel Interrupt Handler Step 1 Define kernel mask level The kernel mask level is defined in configurator file e g template cfg under the system definition This step is identica
20. erter SSUICAIC 27 Synchronous Serial Ic Communication Unit SSL 28 ZC bus Interface a Sa 24 Serial Interface UARTI i O or 1 a Sree 21 Timer RD ae So fs 12 4 INT Interrupt 25 Serial Interface UART R amp G Tiny Series So ware Manual 23 Timer RG TRGIC TR 6 Voltage Detection Circuit 32 Comparator A Rac Tiny Series Software Manual GIC Figure 4 Relocatable Vector Tables of R8C Lx Devices Figure 5 illustrates an example of defining the starting address locations of Fixed Vector Table and Relocatable Vector Table for a R8C23 device R20ANO0088ES0100 Rev 1 00 Mar 01 2010 RENESAS Page 6 of 27 R8C Family Address size OOOO COO0400 000400 CO002Be OO0BBc O02 a O0090e 00001 000926 CO000al O009e7 000230 O00bt 7 CO00150 000d4 0032593 O04000 COONS 004008 COO0001 004009 00026 0042 75 000018 00428 dC000001 0042 8e O05b33 J gt gt 009de1 COO0001 00Sde 00001 009ea3 006039 00fede 000100 OOF f de O00024 010000 et ttt Ottttt Sect jon _intbh_ 0x00 Implementing Interrupts in MR8C 4 INTB register defined zero relative adde smg thus set Fixed Vector Table starting address at OO0fe dc i set varlable tector address 2 Freed Vector Table starting address defined at OOffdc f A terasna sectaddress fwector ROMUATA Oxttde Figure 5 Vector Tables Definition for R8C23 Devi
21. f Interrupts For R8C family devices there are two vector tables namely Fixed Vector Table and Relocatable Vector Table As the names imply Fixed Vector Table resides in allocated addresses e g OFFDCh to OFFFFh Whereas Relocatable Vector Table can be allocated at any desired location within the devices entire memory space by INTB register relative addressing Figure 3 and Figure 4 provide the Fixed Vector Table and Relocatable Vector Table of R8C Lx devices respectively R20AN0088ES0100 Rev 1 00 Page 5 of 27 Mar 01 2010 RENESAS R8C Family Vector Addresses Address L to H Undefined instruction OFFDCh to OFFDFh Overflow OFFEOh to OFFE3h OFFE4h to OFFE7h Interrupt with UND instruction Interrupt with INTO instruction BRK instruction OFFE7h is FFh program executi Starts from the a shown by the ve Implementing Interrupts in MR8C 4 Remarks Reference R8C Tiny Series Software Manual If the content of address on ddress ctor in the relocatable vector table Address match OFFE8h to OFFEBh OFFECh to OFFEFh OFFFOh to OFFF3h Single step 1 Watchdog timer Oscillation stop detection Voltage monitor 1 comparator A1 Voltage monitor 2 comparator A2 Address break 1 OFFF4h to OFFF7h Reserved OFFF8h to OFFFBh OFFFCh to OFFFFh 12 6 Address Match Interrupt 15 Watchdog Timer 9 Clock Generation Circuit 6 Voltage Detection Circuit 32
22. g from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different tyoe numbers may differ because of the differences in internal memory capacity and layout pattern When changing to Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illust
23. he allocation of separate system stack used to process all interrupts and nested interrupts However unified interrupt architecture is easier to implement introduce less system overhead less likely to result in stack resource problems and shorter interrupt completion time as compared with segmented interrupt architecture MR8C 4 employs unified interrupt architecture and thus enjoys its benefits 4 1 2 Challenge 2 Achieve Deterministic and Low Interrupt Latency The deterministic characteristic of an embedded system and its corresponding worse case interrupt latency can be computed by examining all of the sources of interrupt response delays to ascertain which particular source causes the longest delay to the servicing and completion of the highest priority interrupt Areas of examination encompass e Worse case hardware induced delay e Worse case software induced e g by RTOS kernel delay e Longest interrupt disabling region by a lower priority interrupt To achieve a deterministic and low interrupt latency system quality programming techniques coupled with proper RTOS interrupt architecture are required R20AN0088ES0100 Rev 1 00 Page 12 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 Quality programming techniques generally involves Keeping ISRs as simple and short as possible Avoid using instructions that take many cycles to execute Prioritize interrupts appropriately with relative to tasks
24. he interrupt handler is the same as being defined in step 2 Figure 26 illustrates an example of this step include lt itron h gt Hinclude lt kernel h gt tinclude kernel id h MR8C 4 files to be mchided void Contigurelnterrupts void a pts INT 1 mterrupt priority level defined at 2 intlen 1 lower than system IPL tlie 0x02 47 Function name of mterrupt handler void must be specified for both retum value and old INT INTI void 477 ss argument of handler Processing starts 7 Other than ret_int all service calls may be issued within the kernel mterrupt Processing ends handler Figure 26 Defining Interrupt Handler R20AN0088ES0100 Rev 1 00 Page 21 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 5 4 3 Writing Non Kernel Interrupt Handler Step 1 Define kernel mask level The kernel mask level is defined in configurator file e g template cfg under the system definition System Definition system stack size priority AQQ faa ae h a Kernel mask level defmed a5 i ie system IPL tic nume tic deng Figure 27 Defining Kernel Mask Level Step 2 Define interrupt vector Non kemel mterrupt ie ile ee So Zo handler specified entry address INT INTIC pragma switch E Figure 28 Defining Interrupt Vector Step 3 Define interrupt handler Figure 29 illustrates an example of defining non kernel interrupt handler in C languag
25. igure 17 Therefore non maskable interrupts and Watchdog Timer interrupt must not be defined as kernel interrupts A non kernel interrupt does not allow kernel service calls to be issued within its ISR Since service call is not allowed within the non kernel interrupt service routine no extra delay will be incurred due to the service call processing Non kernel interrupts are therefore generally reserved for the NMI and critical interrupts Service Service call call begins ends Interrupt handler begins gt service Call Processing Time Interrupt Termination p Time Interrupt Processing Time Interrupt Latency Service call processing resulting in Jonger interrupt processing duration Figure 17 Kernel Interrupt Service Routine with Service Call R20AN0088ES0100 Rev 1 00 Page 15 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 The interrupt priority level and kernel interrupt mask level dictates whether it is a kernel or non kKernel interrupts To define an interrupt as a kernel interrupt assign its priority level to be lower or equal to the kernel interrupt mask level Conversely assign an interrupt priority level to be higher than the kernel interrupt mask level if it is designated to be a non kernel interrupt refer to Figure 18 Kernel Non Kernel O5 dependent O35 independent Interrupt Handler Interrupt Handler The above illustration assumes kernel mask level set a
26. ily Implementing Interrupts in MR8C 4 void sw inti _ Declare function protoype before pragam declaration pragma INTCALL 10 sw intl p reprocessor directive to define interrupt handler void sw intlO void Interrupt routine for Timer RE peripheral interrupt handling codes interrupt Figure 7 Writing Software Interrupts 3 2 Hardware Interrupts Hardware interrupts comprise of Special and Peripheral I O interrupts 3 2 1 Special Interrupts Special interrupts are used to handle non recoverable errors pertaining to the processor which need immediate attention They are therefore non maskable Listings of special interrupts vary from one device to another in the R8C family Figure 8 shows classification of special interrupts for R8C22 23 and R8C Lx devices respectively R8C22 23 Group RS amp CLX Group aa was Watchdog timer Watchdog timer af Oscillation stop detection Oscillation stop detection A Voltage monitor 2 Voltage monitor 2 comparator A2 M ee i ap ooo ooo o o Figure 8 Comparing Special Interrupts of R8C22 23 and R8C Lx Devices With reference to Figure 8 R8C Lx devices consist of one additional special interrupts Voltage monitor 1 comparator Al as compared to R8C22 23 devices even though they belonged to the same R8C family Thus it is crucial for users to find out the Special interrupts available to the specific device prior to using it 3 2 2 Peripheral I O Interrupts These m
27. iority h a Kernel mask level defmed 5 l le system_IPL tic nume tic deno Figure 24 Defining Kernel Mask Level in C Language Step 2 Define interrupt vector The interrupt vector is defined in the configurator file e g template cfg Figure 25 illustrates an example of defining INTI vector as a kernel interrupt R20AN0088ES0100 Rev 1 00 Page 20 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 A 1 Vector number I Kernel Non kernel interrupt_vector l25 7 os int YES e interrupt handler definition entry address l pragma switch E NT OINT1 0 3 lnterrupt handler E function name Options for pragma Extended functions l Refersto the software interrupt number as specified for the particular interrupt in the dewice user manual 2 YES denotes kernel interrupt handler pragma INTHANDLER E INT_INT1 will be output NO denotes non kemel interrupt handler pragma INTTERRUFPT E INT_INT1 will be output A Refersto the function name of the interrupt handler 4 Two switch options are available B and E for non kernel interrupt handlers Only one option E is available for kernel interrupt handlers F indicates bank switching with register bank 1 specified E specify nested interrupts allowed Figure 25 Defining Interrupt Vector Step 3 Define interrupt handler The final step is to define the interrupt handler in the c file The function name for t
28. l and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics CENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refe
29. l to step 1 of coding interrupts in C language f f System Definition system stack size A00 priority Zea system IPL h a Kernel mask level defined a5 tic nume se tic deno is Figure 31 Defining Kernel Mask Level Step 2 Define interrupt vector interrupt vector 25 Kernel interrupt se tank orbZSdL handler specified entry address INT INT1I pragma switcn E Figure 32 Defining Interrupt Vector R20AN0088ES0100 Rev 1 00 Page 23 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 Step 3 Define interrupt handler INCLUDE str r S35a ine GLE Configurelnterrupts BSET intlen MOY B O2ZH intlic WW INTI Interrupt priority level defined at 2 lower than system IPL INCLUDE mr6e ine GLE NT_INT Global declaration of interrupt handler function name INT_INT1 a Save registers to stack PUSHM RO AQ service calls may be issued within irel_wal 1D task 4k the kernel interrupt handler PUOPM RU AQ ret int hi a l Registers are restored ret_mt must be used to return from Interrupt handler Figure 33 Defining Interrupt Handler 5 5 3 Writing Non Kernel Interrupt Handler Step 1 Define kernel mask level System Definition system stack size AQ priority foo system FL h a Kemel mask level defined 2 5 tic nume l tic deno l Figure 34 Defining Kernel Mask Level Step 2 Define interrupt vector interrupt vector 25 Ma ne aoa
30. mpt os int No co handle specified entry_address INT_INTIQ F pragma switcn i Figure 35 Defining Interrupt Vector R20AN0088ES0100 Rev 1 00 Page 24 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 Step 3 Define interrupt handler INCLUDE str r635a ine GLE Configurelnterrupts BSET Intlen MOV PUGH intlic H INT1 interrupt priority level defined at higher than system IPL INCLUDE mr8c ine GLE NT_INT 4 Public declaration of interrupt handler function name INT_INTT Save registers to stack PUSHN RO AQ Interrupt Processing q Service calls cannot be issued within PUPM RO AQ the kernel mterrupt handler REIT Registers are restored REIT must be used to retum from Interrupt handler Figure 36 Defining Interrupt Handler R20AN0088ES0100 Rev 1 00 Page 25 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 6 Reference Documents User s Manual e MRS8C 4 V1 00 User s Manual e R8C Family Hardware Manual The latest version can be downloaded from the Renesas Technology website Document e Pardon the Interruption Two Approaches to RTOS Interrupt Architectures William E Lamie R20AN0088ES0100 Rev 1 00 Page 26 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 Website and Support Renesas Technology Website e _ http www renesas com Inquiries http www renesas com i
31. nd Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifi
32. nquiry All trademarks and registered trademarks are the property of their respective owners R20AN0088ES0100 Rev 1 00 Page 27 of 27 Mar 01 2010 RENESAS Revision Record Description Rev Date Page Summary 1 00 March 01 10 First edition issued General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence Handling of Unused Pins e Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on e The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of regi
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34. rate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality a
35. ster settings and pins are undefined at the moment when power is supplied e In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power Is supplied until the reset process is completed e In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power Is supplied until the power reaches the level at which resetting has been specified Prohibition of Access to Reserved Addresses e Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals e After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable Differences between Products e Before changin
36. t elect bit bO ILVLO Interrupt priority level select bi 000 Level 0 interrupt disabled 001 Level 1 T 010 Level 2 D1 1 Level 3 100 Level 4 101 Level 5 110 Level amp 111 Level 7 w emt request bit Le No interrupt request Da el ee Nothing i is assigned lf necessary set to 0 When the content is undefined bs et Modifying TRBIC mterrupt control register to enable disable Timer RB interrupt include lt itron h gt include lt kernel h gt include kernel_id h m taskI P INT staed trbic 0 Timer RB interrupt disabled Time RB mtermupt enabled and trbic interrupt priority level 5 defmed II 7 Figure 21 Enable Disable Non Kernel Interrupts R20AN0088ES0100 Rev 1 00 Page 18 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 G INTI declared as kernel interrupt in template cfg f f System Definition system stack size 400 priority foo system IPL 4 tic nume D tic deno az ie interrupt vector 25 oS int YES entry address INT_INTIC pragma switch E 2 Bit b7 b b5 b4 b3 b2 b1 bo symbol Pol Rie et to After Reset MM mM g 0 A 0 0 0 ayy my Level 0 interrupt disabled Level 1 Level 2 gt Level 3 gt Level 4 Level 5 Level 6 Level T Interrupt reguest bit 0 No interrupt requested 1 Interrupt requested POL 0 Falling edge selected 1 Rising edge selected
37. t 3 Figure 18 Defining Kernel and Non Kernel Interrupts Handler Figure 19 provides an example of defining INT1 as a kernel interrupt handler System Definition system stack_size 400 priority n oe system_IPL 4 I3 3 Kernel mask level defined at 4 tic _nume tic _deno Defme INT1 handler as inter rupt_vector 2 ee kernel interrupt handler os_int YES entry_address NT_INTI pragma_switch void ConfigurelInterrupts void x Enable INTIn Interrupt x intlen 1 x Set INTIn Interrupt priority intlic 0x02 te INT1 priority level defined at 2 below kernel mask level Figure 19 Defining INT1 as Kernel Interrupt Handler 5 3 Enabling Disabling Interrupts Although it is possible to control enable disable interrupts by manipulating the IPL value it is not recommended as the manipulation can only be done by resetting the interrupt flag to zero However there are two other methods that are more appropriate to fulfill this requirement 1 Modify corresponding interrupt control register SRF of the interrupt 2 Utilitize service calls loc_cpu and unl_cpu 3 Setting T flag to enable disable maskable interrupts R20AN0088ES0100 Rev 1 00 Page 16 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 Method 3 uses the least overhead among the three methods mentioned above Inaddition it is the easier to execute However it is important to take no
38. te that no service call is allowed to be invoked in the setting of the I flag Figure 20 illustrates this concern asmi FELA I 7 Maskable Interrupts Disabled Service calls not dlowed in the setung of T flag sent fect a J Waskable Interrupts Enabled Figure 20 Setting T Flag for Controlling Interrupts 5 3 1 Enable Disable Non Kernel Interrupts Method 1 as mentioned above is used to control non Kernel interrupts Figure 21 illustrates the process of disabling enabling a non kernel interrupt in R8C Lx devices by modifying its SRF register 5 3 2 Enable Disable Kernel Interrupts To control kernel interrupts user is only required to use the loc_cpu and unl_cpu service calls loc_cpu disable kernel interrupts by placing system in CPU locked state unl_cpu release system from CPU locked state Figure 22 illustrates the process of disabling enabling a kernel interrupt in R8C Lx devices by using service calls loc_cpu and unl cpu R20AN0088ES0100 Rev 1 00 Page 17 of 27 Mar 01 2010 RENESAS R8C Family Implementing Interrupts in MR8C 4 G Timer RB declared as non kernel mterrupt f f System Definition system stack size 400 priority ie ag system IPL 4 tic nume tic deno i interrupt vector 4 os_ int NO TimerRBHandler ti entry address pragma switch be TRBIC interrupt control register of R8CLX Spt ee ee E e a Afer Reset A LLA ni
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