User`s Manual
Contents
1. Figure 4 3 12 25 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 3 About communication with CPU FL PR4 and MINICUBE2 support only communication by UART for circuit simplification 3 wire serial mode is not supported Please use FL PR4 and MINICUBE2 by UART mode Please refer to the user s manual of each equipment for details With a later USB circuit since P31 RXDO is common please set a jumper JP8 to the 2 3 side and perform debugging and flash writing JP8 1 2 3 CPU RXDOY PSTD 1 2 short circuit TXD of USB connects default 2 3 short circuit TXD of CN5 connects Table 4 3 12 3 4 Self programming By operating FLMDO signal by P62 a self program function is realizable P62 is connected to FLMDO through an OR gate P62 will become effective if FLMDO from a debugger and a flash writer is made into a LO level or in the state of un connecting a debugger and a flash writer P62 output Status Explanation Conditions Lo Normal Normal state Hi Self programming MODE FLMDO of a debugger and a flash writer Lo or it un connects Table 4 3 12 4 Refer to the user s manual etc for a setup of P62 Refer to the user s manual for the details of self programming 26 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 13 The connector for MINICUBE CN6 It is a connector for connecting MINIC2. P50 KRO PCS2 CS2 N C P53 KR3 DDO P37 IERXO N C P51 KR1 PCS3 _CS3 N C P54 KR4 DCK PCT5 N C P52 KR2 DDI P73 ANI3 N C P55 KR5 DMS PCT7 N C P90 TXDA1 A0 P72 ANI2 N C P95 A5 P60 INTP11 Expansion CAN CAN2 RS P91 RXDA1 A1 P61 INTP12 Expansion CAN CAN3 RS P96 A6 P70 ANIO N C P92 A2 P71 ANI1 N C P97 SIB1 A7 P65 CTXD2 Expansion CAN CAN2 TXD P93 A3 P66 CRXD2 Expansion CAN CAN2 RXD CPOW 5V 5V P67 CTXD3 P94 A4 _ RESET Expansion CAN CAN3 TXD Expansion CAN CAN3 RXD P68 CRXD3 Table 5 4 J3 is connected to J5 of CEB V850ES FJ3 J4 is connected to J6 of CEB V850ES FJ3 37 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 5 5 Evaluation board mating The following figure illustrates mating of the V850ES FJ3 evaluation CPU board and expansion board Longitudinal View FJ3 Evaluation CPU board CAN connector BESW J6 connector CAN expansion board Expansion CAN connector MINICUBE connector Transversal View FL PR4 MINICUBE2 connector Power supply jack FJ3 Evaluation CPU board CAN expansion board Expansion CAN connector Figure 5 1 5 38 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual Revision History Edition Description Pag e s The 1 0 th Apr 2
3. C E The installation part of each jumper is shown below Function CANO Between CAN transceiver 0 CAN connector Between CAN transceiver CAN connector Between CPU CAN transceiver Table 4 3 2 5 CANO Between CPU CAN transceiver 13 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 3 LIN I F 1 LIN I F outlline Two LIN interfaces are mounted as standard A block diagram is shown below LIN transceiver TJA1020 Open setting jumper JPX5 8 Master Slave Change jumper Open setting JP3 5 jumper JPX7 9 3 pin connector Master Slave Change jumper JP4 6 Cmaster V 850ES FJ 3 SJ3 Figure 4 3 3 1 2 LINE I F connector CN3 CN4 LINO is assigned to CN3 and LIN1 is assigned to CN4 respectively Connector pin distribution table is shown below LIN I F connector pin description CNS LINOL 1 LIN_Bus LIN_Bus 2 12V 12V 3 GND GND Table 4 3 3 2 Connector part number IL SP S3FP2 J S T Mfg Co Ltd 14 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 3 LIN transceiver TJA1020T made by Philips Corp are mounted in this board as a LIN transceiver Refer to the applicable data sheet for the details of a device Connection of CPU and a LIN transceiver is shown below LINO RXDD2 P39 RXD Reception P63 NSLP SLEEP MODE pullup NWAKE TXD
4. In case FL PR4 or MINICUBE are used a JP7 short pin is set to the 1 2 side and it is set as the course of dashed and dotted line FL PR4 and a dotted line MINICUBE Refer to Figure 4 3 7 In case is used a JP7 short pin is set to the 2 3 side and it is set as the course of a solid line MINICUBE2 Please use a JP7 short pin for the 1 2 side at the time of real operation setting it up when you do not use a debugger 3 RESET SW SW4 If SW4 is pushed CPU and an evaluation board will be in a reset state 4 3 8 INTPO SW SW2 SW2 on a board is connected to PO3 INTPO port A push SW2 inputs 0 into POS INTPO port 4 3 9 NMI SW SW3 SWS on a board is connected to P02 NMI port A push SW3 inputs into PO2 NMI port 20 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 10 CLOCK 1 Main Clock The crystal oscillator is connected to X1 and X2 terminals of CPU Oscillation frequency is 6MHz in FJ3 and it is 4MHz in SJ3 Since the socket is mounted a crystal oscillator is exchangeable if needed Please purchase a HC49 U S type crystal oscillator Since it operates by the CPU internal clock by the default in case an external clock is used an inside register setup of CPU is changed Please refer to an applicable CPU user s manual for details 2 Sub Clock The crystal oscillator is connected to XT1 and XT2 terminals of CPU Oscillation frequency is 32 768kHz Sinc
5. connecting USB with PC However since drive current is restricted to 500mA as a standard of VBUS which is bus power the drive of CAN is not recommended Please confirm that the whole board consumption current is 500mA or less Since 12V are required about LIN it cannot operate by USB bus power When you operate LIN please supply 12V from this board power supply jack 23 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 12 Evaluation environment 1 Overview The development environment which can be used on this board is as follows Built in FLASH writing FL PR4 Debugging MINICUBE MINICUBE2 It is designing on the assumption that the three above mentioned kinds This board mounts the connector for FL PR4 connection in built in FLASH writing The connector for FL PR4 connection is as common as MINICUBE2 Moreover the connector for MINICUBE connection is mounted A block diagram is shown in the following clause In circuit composition FL PR4 and MINICUBE2 and MINICUBE constitute exclusion use as a premise If FL PR4 or MINICUBE2 and MINICUBE are simultaneously connected to a connector since a signal collision will occur please avoid simultaneous use absolutely 2 Setup A setup of the following jumper JP7 is changed according to the development environment to be used JP7 Normal use During connecting FL PR4 During connecting MINICUBE default 2 3 short circuit During connecting
6. subject to change without notice Trademarks CEB V850ES FJ3 SJ3 is a trademark of COSMO Co Ltd Other company names and product names provide in this document are either registered trademarks or trademarks of respective companies CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual CONTENTS 1 OVelIVIQW iet s eb 4 2 Evaluation CPU Board CEB V850ES F4J3 SJ3 eene nennen nennen ennt nnne nnne ns 4 3 Document A eee ie ee eere ce eo aaa E 4 4 1 Hardware Specifications ake itn eis egi Don pti eel etat dena kaso 5 4 2 Block Diagrami s Fh on p IBI eB Eee eee 6 4 3 Configuration pu a tt eh a a cute eta anal k d ata Pe ie ataca 7 4343 Power supply ee a TE 8 43 22 p S e dm 10 4 3 3 EINA E S ie teen e T RUE eb 14 4 3 4 Exparnsion connectors J5 6 cists creuse e eines haere 17 4 3 5 7 segmentiLED LED1 rnt ed e Er et eee RA eee 18 43 6 8 bit DIP SW SW IT i tec tte echter te Doc ee dee E rato nala SLE 18 433 7 RESET qe ns s pa eite 19 4 3 8 INTPO SW SWO Ves ccn 20 4 3 9 NMI SW SW3 eee 20 LIN a fiue esi ico ee or un 21 434T USB iue adea ee eb RISE eus 22 4 3 12 Evaluation cce ren espe
7. 007 The first edition issue 39
8. 1 P97 SIB1 A7 P65 CTXD2 Expansion CAN CAN2 P93 A3 P66 CRXD2 Expansion CAN CAN2 CPOW 45V P94 A4 P67 CTXD3 Expansion CAN RESET Push SW RESETT P68 CRXD3 Expansion CAN CAN3 GND 12V GND GND Table 4 3 4 The pull up of each signal is carried out by resistance 47kQ CPOWZCPU power supply FJ3 5V SJ3 4 3 3V CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 5 7 segment LED LED1 The seven segment LED is mounted on a board The LED can be statically switched on the light or put out from the port of CPU In case you make each segment turn on please set a corresponding port as a E b He fd d 9 DP 9 D Figure 4 3 5 Correspondence port Light Extinguish default PCDO 0 1 pullup PCD1 0 1 pullup PCD2 0 1 pullup pullup pullup pullup pullup pullup ojo L E EE E E U Table 4 3 5 4 3 6 8 bit DIP SW SW1 8 bit DIP SW is mounted on a board ON OFF of DIP SW can be checked in a CPU port If DIP SW is turned ON a port will be set to 0 and a port will be set to 1 if it turns OFF DIP SW1 DIP SW2 DIP SW3 DIP SW4 DIP SW5 DIP SW6 DIP SW7 DIP SW8 Table 4 3 6 CEB V850ES FJ3 S
9. CEB V850ES FJ3 8J8 EVALUATION BOARD HARDWARE USER S MANUAL Date Published April 2007 The 1st edition COSMO Co Ltd Control No CCEB HUMFJ3SJ3_010E CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual Cautions e The information in this document is subject to change without notice Before using this document please confirm that this is the latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of COSMO Co Ltd COSMO Ltd does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of device described herein or any other liability arising from use of such device license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of COSMO Co Ltd Descriptions of circuits and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits and information in the design of the customer s equipment shall be done under the full responsibility of the customer COSMO Co Ltd assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits and information The information in this document is current as of 2007 The information is
10. D2 P380 TXD Transmission LIN LIN JP3 INH MASTER SLAVE BAT GND Powersupply 12V supply Table 4 3 3 3 1 LIN1 RXDD3 P800 RXD Reception P64 NSLP SLEEP MODE pullup NWAKE TXDDS3S P81 TXD Transmission LIN LIN JP5 INH MASTER SLAVE BAT GND Power supply 12V supply Table 4 3 3 3 2 4 LIN MASTER SLAVE setting A jumper is set up by the mode of LIN of operation 6 1 2 3 LINO MASTER SLAVE MASTER setting SLAVE setting 2 3 short circuit default 1 2 short circuit 1 2 short circuit default 2 3 short circuit Table 4 3 3 4 1 LINT MASTER SLAVE MASTER setting SLAVE setting JP5 2 3 short circuit 1 2 short circuit default JP6 1 2 short circuit 2 3 short circuit default Table 4 3 3 4 2 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 5 About JPX5 JPX10 Although the pattern connects between 1 2 and between 3 4 of JPX5 JPX8 and between 1 2 of JPX6 JPX9 JPX10 a signal is separable by cutting the pattern on the back side soldering side of each jumper As standard the following jumper is un mounting JPX5 8 JPX6 7 9 10 4 2 12 OO 3 1 The installation part of each jumper is shown below Function LINO Between CPU LIN transceiver LINO Between CPU LIN transceiver NSLP LINO Between LIN transceiver LIN connector LIN1 Between CPU
11. DL2 AD2 PDL4 AD4 PDL3 AD3 Signal name PDL5 FLMD1 PDL6 AD6 PDL7 AD7 PDL8 AD8 PDL9 AD9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL13 AD13 PDL14 AD14 P127 ANI23 PDL15 AD15 P126 ANI22 P125 ANI21 P124 ANI20 P123 ANI19 P122 ANI18 P121 ANI17 P120 ANI16 P715 ANI15 P713 ANI13 P714 ANI14 P712 ANI12 P711 ANI11 P713 ANI10 P79 ANI9 P78 ANI8 P77 ANI7 P76 ANI6 P75 ANIS P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 Table 4 3 15 4 30 P70 ANIO CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 4 Memory map 1 V850ES FJ3 F3380 Built in FLASH 512KB Built in RAM32KB 32KB 80KB Prohibition of use Area for AFCAN 12KB x3FFFFFFH x3FFF000H Built in peripheral area 4KB x3FFFFFFH x3FECOO0H x3FEBFFFH Built in RAM area x3FF7000H x3FEF000H x3FEC000H x1000000H 8MB CS3 x0800000H x07FFFFFH External memory area 4MB CS2 x0400000H External memory x01FFFFFH x0200000H CS1 x01FFFFFH x0100000H x0000000H x0000000H Figure 4 4 1 31 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 2 V850ES SJ8 F3368 Built in FLASH 1024kB Built in RAM60kB x3FFFFFFH Built in x3FFFFFFH ar
12. GND 3 P10 INT9 3 4 P11 INT10 4 5 GND 6 POO 6 7 PO1 7 8 FLMDO 8 9 GND 10 GND 11 GND 12 GND 13 GND 14 RESET 14 15 GND 16 GND 17 P02 NMI 17 18 PO3 INTO 18 19 PO4 INT1 19 20 POS INT2 20 21 PO6 INT3 21 22 P40 22 23 41 23 24 P42 24 25 PSO TXDO 25 26 P31 RXDO 26 27 P32 27 28 P33 28 29 P34 29 30 5 30 31 P36 CTXD1 31 32 P37 CRTX1 32 GND GND P38 TXD2 P39 RXD2 Signal name Signal name P51 KR1 CPUpin P5S KR3 P6O INT11 P55 KR5 P61 INT12 P62 INT12 P63 SCKB3 P64 SCKB3 P65 CTXD2 P66 CRXD2 P67 CTXD3 P68 CRXD3 P610 P69 P611 P612 P613 P614 P615 P80 RXD3 P90 KR6 P81 TXD3 P91 KR7 P93 P95 P97 SIB1 P98 SOB1 P910 SIB2 Table 4 3 15 2 29 P99 SCKB1 P911 SOB2 P912 SCKB2 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual Signal name P913 INT4 CPUpin P914 INTS P915 INT6 PCDO PCD1 PCD2 PCD3 50 50 PCS1 CS1 PCS2 CS2 PCS3 CS3 PCMO WAIT PCM1 CLKO PCM2 HLDAK PCM3 HLDRQ PCM4 PCM5 PCS4 PCS5 PCS6 PCS7 PCTO WRO PCT1 WR1 PCT2 PCT4 RD PCT5 PCT6 ASTB PCT7 GND GND PDLO ADO PDL1 AD1 P
13. J3 Evaluation Board HardwareUser s Manual 4 3 7 RESET 1 RESET overview When the time of power on or SW4 are pushed reset starts a board It is a RESET signal at the MINICUBE or FL PR4 use and MINICUBE2 use time and composition differs A reset signal block diagram is shown below FJ3 SJ3 MINICUBE FL PR4 MINICUBE2 connection Reset signal block diagram flow of a reset signal MINICUBE2 V850FJ3 SJ3 FL PR4 MINICUBE2 connector 2 205 FL PR4 1 GND P30 TXDO 2 RESout F P31 RXDO 3 SI RXD 4 VDD 5 SO TXD 6 VPP 7 SCK 8 H S MINICUBE 1 P62 9 CLK Resistance 10 VDE eae ipd M DDI 11 VDD2 DCK 12 FLMDI 3 DMS 13 RFU i DDO 14 FLMDO i DRST 15 RESin 16 NC i RESET MINICUBE 1 f i 3 D Connection apparatus Short pin Select MINICUBE2 2 3 MINICUBE 1 2 B RESET FL PR4 1 2 B MNICUBE FL PR4 and Nothing a 4 MINICUBE2 are promised on exclusion use respectively RESET signal is communalized Figure 4 3 7 19 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 2 RESET signal setting JP7 A setup of a RESET signal changes with apparatus connected JP7 performs a setup JP7 1 2 3 1 2 short circuit Normal use During connecting FL PR4 During connecting MINICUBE default 2 3 short circuit During connecting MINICUBE2 Table 4 3 7 2
14. LIN transceiver LIN1 Between CPU LIN transceiver NSLP JPX10 LIN1 Between LIN transceiver LIN connector Table 4 3 3 5 16 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 4 Expansion connectors J5 J6 It is the connector used in case an optional CAN add in board etc is connected As standard it is not mounted Expansion connectors table Signal name Function used on a Board Signal name Function used on a Board 8bit DIP SW P98 SOB1 A8 P10 INTP9 P912 SCKB2 A12 P99 SCKB1 A9 N i P01 8bit DIP SW P11 INTP10 P913 INTP4 A13 P910 SIB2 A10 O PO4 INTP1 POS INTPO Push SWI INTPO P32 ASCKAO 8bit DIP SW P914 INTP5 A14 P911 SOB2 A11 P35 8bit DIP SW P915 INTP6 A15 50 50 P41 SOBO Flash PRO4 PCMO WAIT P40 SIBO Flash PRO4 PCS1 CS1 P42 SCKBO Flash PRO4 P36 IETXO P50 KRO 8bit DIP SW PCS2 CS2 P53 KR3 DDO N Wire 7 P51 KR1 8bit DIP SW PCS3 _CS3 P54 KR4 DCK N Wire PCT5 8bit DIP SW P52 KR2 DDI N Wire P73 ANI3 P55 KR5 DMS N Wire PCT7 8bit DIP SW P90 TXDA1 A0 P72 ANI2 P95 A5 P91 RXDA1 A1 P6O INTP11 P61 INTP12 Expansion CAN Expansion CAN P96 A6 P70 ANIO P92 A2 P71 ANI
15. MINICUBE2 Table 4 3 12 2 In case FL PR4 and MINICUBE are used a JP7 short pin is set to the 1 2 side and it is set as the course of dashed and dotted line FL PR4 and a dotted line MINICUBE Refer to Figure 4 3 7 In case MINICUBE2 is used a JP7 short pin is set to the 2 3 side and it is set as the course of solid line MINICUBE2 Please use a JP7 short pin for the 1 2 side at the time of real operation setting it up when you do not use a debugger 24 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual MINICUBE and FL PR4 MINICUBE2 connection block diagram FJ3 SJ3 MINICUBE FL PR4 MINICUBE2 connection MINICUEE2 Self program function usg Txp GND Communication control signal block diagram C POW SI RXD V850ES FJ3 5 VDD SO TXD P30 TXDO VPP P31 RXDO SCK H S CLK VDE VDD2 FLMD1 RFU 1 FLMDO 14 DDI RESin 15 DCK NC 16 DMS DDO MINICUBE and FL PR4 are premised on exclusion use DRST RESET and FLMD 0 signal are communalized En N P62 RESET MINICUBE GND A1 GND A2 P62 GND Normal mode LO GND A4 If HI Self programming mode GND A5 GND A6 DDI A7 DCK 8 DMS AQ DDO DRST RESET FLMDO GND GND GND GND GND GND GND GND GND GND PORTO PORT1 VDD
16. S FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 Configuration The following figure shows the physical placement and the outside of the major components on the CEB V850ES FJ3 SJ3 evaluation CPU board The various components are described below hd TUR 1PXI 0000 0000 Ea dH SEES L2 210 910 OD JEFE JPXID JPNS mondo SEE m P errr rrr 1 eoecgcecoeoseo a act 8 PERCE Im 26 Bs B yi 2t cup pet p RES E C o E Jae Figure 4 3 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 1 Power supply 1 Power supply part Although premised fundamental on use in 12V input from the attached AC DC adaptor it is possible to also make it operate by the power supply supply from a USB port Notes As for the USB port power supply supply capability is restricted to 500mA by specification When you operate this board in a USB port please use consumption current by 500mA or less moreover since 5V are supplied from a USB port A LIN I F function cannot be used A block diagram is shown below Power Supply 12V LIN 0 LIN 1 Peripheral device Expansion connectors CPU CPU Peripheral Pull up resistance Figure 4 3 1 1 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 2 Power supply connector CN8 Please use DC jack sid
17. SUB 32 768 KHz V850ES SJ3 Operating CLK direct mode 4 MHz PLL mode 32 MHz Oscillator MAIN 4 MHz SUB 32 768 KHz The crystal for MAIN clocks is socket mounted A through hole for each signal line check is around CPU Two rows of half pitch Expansion connector 30 pin 2 54 pitch x 2 Flash PRO4 connector 16 pin x 1 MINICUBE connector 26 pin x 1 CAN I F connector 9 pin D SUB female x 2 LIN I F connector 3 pin x 2 PUSH SW x 3 RESET NMI INTO DIP SW 8 bit x 1 Development environment setting FL PR4 MINICUBE MINICUBE2 UART setting USB FL PR4 MINICUBE2 CAN termination resistance setting LIN master slave switching Power LED 5 V Green 7 segment LED x 12 V 5 V 43 8 V GND AC adapter DC 12 V input With regulator IC 5 V FJ3 3 3V SJ3 output CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 2 Block Diagram Whole block diagram 850ES FJ 3 starter kit whole block diagram Ki 9 gt n o 2 lt Ki 9 gt 9 o 2 lt o d D DIPSW8 bit 7seg8 bit RESET NMI INTPO Power supply 12V Figure 4 2 The above figure is the case where V850ES FJ3 is mounted In this case CPU power supply voltage is set to 5V Moreover when V850ES SJ3 is mounted CPU power supply voltage is set to 3 3V Since a voltage setup is set up at the time of shipment especially a visitor does not need to be conscious of it CEB V850E
18. UBE which is a target CPU debugger Signal No B1 GND B3 GND B4 GND GND GND GND GND GND GND DRST PORTO RESET PORT1 FLMDO Table 4 3 13 VDD 27 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 14 The connector for FL PR4 MINICUBE2 CN5 It is a connector for connecting MINICUBE2 which is a target CPU debugger Moreover it is as common as the connection connector of FL PR4 which is a FLASH write in tool with a built in CPU V850ES FJ3 GND GND RESET RESET SI RxD P40 SIBO or P31 RXDDO VDD EVDD SO TxD P41 SOBO or P30 TXDDO VPP N C SCK P42 SCKBO H S PCMO 1 2 3 4 5 6 7 8 9 CLK N C VDE N C VDD2 N C FLMD1 N C RFU 1 N C FLMDO FLMDO RESETin N C N C N C Table 4 3 14 The RESETin of a No 15 pin is the reset signal passed to MINICUBE2 It is not used at the time of FL PR4 connection 28 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 15 The connector for CPU I O pins check The through hole for checking each terminal of CPU is arranged around a CPU chip The column from which the CPU pin number is is not pulled out to the connector for a check Each signal name has indicated the thing of FJ3 Signal name 1 GND 2
19. ace LIN interface N wire connector etc The CEB V850ES SJ3 features an NEC Electronics made 32 bit single chip microcontroller V850ES SJ3 Other devices are the same as CEB V850 ES FJ3 This board is designed so that the CPU pins can be provided outside the board by connecting an optional add in board The MINICUBE or the MINICUBE2 can be used as debugging environment The FL PR4 FlashPro4 hereafter FL PR4 made by Naito Densei Machida Mfg Co Ltd is required for writing programs Besides FL PR4 FP LITE and MINICUBE2 can be written in The MINICUBE the MINICUBE2 the FL PR4 are not included with this evaluation kit 3 Document The following documents are included as PDF files CEB V850ES FJ3 SJ3 Evaluation Board Hardware User s Manual CEB V850ES FJ3 Evaluation Board Circuit Diagrams CEB V850ES FJ3 Evaluation Board Parts List CEB V850ES SJ3 Evaluation Board Circuit Diagrams CEB V850ES SJ3 Evaluation Board Parts List V850ES FJ3 Hardware Preliminary User s Manual V850ES SJ3 Hardware Preliminary User s Manual CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 1 Hardware Specifications The specifications of the CEB V850ES FJ3 SJ3 Starter s Kit Evaluation Board are shown below CPU Check pin e External connectors SW Jumpers LED e Check pin e Power supply V850ES FJ3 x 1 or V850ES SJ3 V850ES FJ3 Operating CLK direct mode 6 MHz PLL mode 48 MHz Oscillator MAIN 6 MHz
20. ck diagram P65 CTXD2 P 66 CRXD2 CAN CAN termination CAN transceiver voltage connect B60 connector m ati ng connector IC open enable connector V850ES FJ3 05 J6 P67 CTXD3 P 68 CRXD3 P61 J3 J4 CAN CAN termination CAN transceiver voltage connect open enable Connector CAN expansion board Evaluation CPU board Figure 5 2 35 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 5 3 Board size 65 00 Expansion connector 30 10 00 ka J3 10 00 CAN connector CAN2 9pin DSUB CAN circuit CAN 2 CAN 3 90 00 CAN connector CAN3 9pin DSUB Expansion connector 30pin Figure 5 3 36 5 4 External connectors CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual Table of Connection connectors J3 J4 Usage Type with CAN Usage Type with CAN No Signal Name Expansion Board No signal Name Expansion Board 1 POO N C 1 P98 SOB1 A8 N C 2 P10 INTP9 N C 2 P912 SCKB2 A12 N C 3 P01 N C 3 P99 SCKB1 A9 N C 4 P11 INTP10 4 P913 INTP4 A13 N C 5 POS INTPO 5 P910 SIB2 A10 N C 6 P32 ASCKAO 6 P914 INTP5 A14 N C 7 PO4 INTP1 7 P911 SOB2 A11 N C 8 P35 8 P915 INTP6 A15 N C 50 50 P41 SOBO WAIT P40 SIBO PCS1 CS1 N C P42 SCKBO P36 IETXO N C
21. e it is soldered directly crystal is unexchangeable 21 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 11 USB 1 USB overview USB connection is made using the UART interface of CPU USB UART interface device FT232R is mounted and USB is changed into UART The USB section block diagram is shown below FJ3 SJ3 USB connection C POW V850FJ3 SJ3 FT232R P30 TXDO RXD VCC P31 RXDO TXD USBN RTS USBP CTS NBUSEN Supplement Power supply Figure 4 3 11 22 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 2 USB setting With a flash write in circuit since P31 RXDO is common please set a jumper JP8 to the 1 2 side and perform USB communication JP8 1 2 3 CPU 1 1 2 short circuit TXD of USB connects default 2 3 short circuit TXD of CN5 connects Table 4 3 11 2 3 The check of USB cable insertion and extraction The insertion and extraction state of a USB cable can be checked by checking the level of P69 P69 input Lo USB cable connecting Hi USB cable un connecting Table 4 3 11 3 Refer to the user s manual etc for a setup of P69 4 About driver software It is downloadable from the homepage of Future Technology Devices International Corp 5 USB bus power VBUS which is the bus power of USB is set DIODE OR to 5V power supply of this board When making it operate with this board simple substance it can operate only by
22. e of an attached AC adaptor for a power supply connector CN8 connecting The power supply to supply is as follows AC adaptor NP12 US1210 Akizuki Denshi Corp Input voltage range 100 240 50 60 Hz Output voltage DC12V Current 1Amax Suitable connector Type A 5 5 Polarity GND a GND Figure 4 3 1 2 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 3 2 CAN I F 1 CAN I F overview Two CAN interfaces are mounted as standard A block diagram is shown below CAN transceiver Open setting TJA 1050 jumper JPX2 4 CTXDn TXD CAN H Open setting Terminator jumper Common change jumper JPX1 3 mode filter JP1 2 CRXDn RXD CAN L D SUB 9 pin female V850ES FJ3 SJ3 Figure 4 3 2 1 10 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 2 CAN I F connector CN1 CN2 CANO is assigned to CN1 and is assigned to CN2 respectively Since the connector on a substrate mounts Dsub9 pin female the connector by the side of a cable should use Dsub9 pin male at the time of cable creation Pin distribution table is shown below CAN I F connector pin distribution table CN1 CANO CN2 CAN1 2 3 GND GND 4 N C N C 5 Coupling with capacitor and fed to GND Coupling with capacitor and fed to GND 6 N C N C 7 CAN H1 CAN H2 8 c 212 212 Table 4 3 2 2 Connector part n
23. ea 80KB x3FFF000H x3FECOO00H x3FEBFFFH Built in RAM area 60KB x3FF0000H Prohibition of use of Prohibition of use x3FEFOOOH Prohibition of use ener x3FECO00H x1000000H xOFFFFFFH External memory area 8MB CS3 x0800000H 7 4MB CS2 x0400000H xO3FFFFFH External memory area 2MB External memory x01FFFFFH x0200000H CS1 1MB x01FFFFFH x0100000H 50 Built k us area x0000000H x0000000H Figure 4 4 2 32 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 5 Notes at the time of user circuitry In adding and connecting a user circuit at an evaluation board please consider the following notes to the design and manufacture which cannot receive influence of a noise etc in reference easily Moreover there are restrictions matters such as drive current in each terminal Please refer to these notes and a correspondence CPU user s manual and use it within rating 4 5 1 Consumption current The total combined consumption current of this board and expansion boards must be 0 3 A or less due to connector performance factors When the current exceeding 0 3A is required a heat sink is needed for U13 Please attach the optimal heat sink after having a heat design carried out or contact to our company in that case If the current more than 0 3A is passed without a heat sink U13 generates heat and there is danger such as a burn and a fire M
24. i sete creme iced cet x eese d chee 24 4 3 13 The connector for MINICUBE CN6 enne nnne 27 4 3 14 The connector for FL PR4 MINICUBE2 5 0 28 4 3 15 The connector for CPU I O pins check een nnne nnns 29 4 4 Mermnotry map rie ite reco ce pat e e hp ate 31 4 5 Notes at the time of user circuitry 33 4 5 1 Consumption ipic ete Bot o RR Hiper 33 4 5 2 l O sigrials unte eU eb I t IB e e eddie 33 4 6 jumper setup at the time of shipment U een nmee nennen netten nnne nnne 34 5 CAN exparsion board esata enna n Hee iid e co e Ley va pe 35 5 1 SPeCiHiCAtiONS EE 35 5 2 Block diagram ug nid eene enean 35 5 3 Boatd SIZ6 2 tt e out i dte edt n eate tees eerte 36 5 4 u u e ph e Da RN ERE a eR ees 37 5 5 Evaluation boarditmatlng e ERU REB pr bI Mos bd n eletto see 38 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 1 Overview This manual prescribes a CEB V850ES FJ3 evaluation board and a CEB V850ES SJ3 evaluation board CEB V850ES FJ3 SJ3 is called below about two kinds of evaluation boards 2 Evaluation CPU Board CEB V850ES FJ3 SJ3 The CEB V850ES FJ3 features an NEC Electronics made 32 bit single chip microcontroller V850ES FJ3 USB interface 7 segment LED CAN interf
25. oreover power supply supply stops by the shutdown function which U13 has The supplied AC adapter is rated for 12 V 0 5 A or higher but the rating may differ depending on the shipment lot 4 5 2 I O signals Each signal line currently outputted to J3 and J4 is outputted to the connector after pulling up by 47kQ Pay attention to pattern damage pattern bridge etc and implement measures as needed such as removing mounted parts For the specifications of each pin and the electrical specifications refer to the correspondence CPU user s manual 33 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 4 6 A jumper setup at the time of shipment A setup of the jumper at the time of shipment is as in the following tables No Sue mon 1 2 OPEN EN 3 4 OPEN CANO no terminator CAN1no terminator JP3 LINO master JP4 LINO master JP5 LIN1 master JP6 1 2 SHORT LIN1 master JP7 1 2 SHORT Reset normal use JP8 1 2 SHORT RXDO USB UART use Table 4 6 34 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 5 CAN expansion board This product is a board for CAN interface expansion developed for the CEB V850ES FJ2 As standard it is not attached 5 1 Specifications The CAN expansion board which expands the number of CAN channels by 2 channels is used connected to the J5 and J6 connectors of the CEB V850ES FJ3 5 2 Block diagram CAN expansion board blo
26. umber XM3B 0922 112 OMRON Corp CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual 3 CAN transceiver TJA1050T made by Philips Corp are mounted in this board as a CAN transceiver Refer to the applicable data sheet for the details of a device Connection of CPU and a CAN transceiver is shown below CANO connection CTXDO P33 TXD Transmitting data CRXDO P34 RXD Receiving data VREF VREF CAN H CAN L PCM4 Power supply 5Vsupply Table 4 3 2 3 1 connection TJA1050T Signal Name CTXD1 P360 TXD Transmitting data CRXD1 P37 RXD Receiving data VREF VRE CAN H CAN L CAN 5 RS RS VCC GND Power supply 5Vsupply Table 4 3 2 3 2 4 CAN signal terminus setup A CAN signal terminus value is set up by JP1 and JP2 JP1 corresponds to CANO and JP2 correspond to respectively JP1 2 4 2 OO 3 1 Terminator value common to JP1 and JP2 open Infinite default 1 2 short circuit 1200 1 2 3 4 short circuit 600 others Prohibition of a setup Table 4 3 2 4 CEB V850ES FJ3 SJ3 Evaluation Board HardwareUser s Manual b About JPX1 JPX4 Although the pattern connects between 1 2 and between 3 4 of JPX1 JPX4 a signal is separable by cutting the pattern on the back side soldering side of each jumper As standard the following jumper is un mounting JPX1 3 JPX2 4 4 2 4 2 OO OO 3 1
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