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MCS® 51 Microcontroller Family User`s Manual

1. 00000000 SCON SBUF C1CAPMO 1 2 4 C1MOD 00000000 X0000000 X0000000 X0000000 X0000000 X0000000 0000 P1 AD1 ACON 00000000 00000000 XX000000 TCON TMOD TLO TL1 TH0 TH1 00000000 00000000 00000000 00000000 00000000 00000000 P0 SP DPL DPH AD0 11111111 00000111 00000000 00000000 00000000 00 0000 Found in the 8051 core see 8051 Hardware Description for explanations these SFRs See description of PCON SFR Bit PCON 4 is not affected by reset X F8 FF FO F7 E8 EF 7 08 DF DO 07 B8 BF B7 AB AF AO A7 98 OF 90 97 88 8F 80 87 6 5 intel User software should not write 1 5 to these unimple mented locations since they may be used in future MCS 51 products to invoke new features In that case the reset or inactive values of the new bits will always be 0 and their active values will be 1 The functions of the SFRs outlined below More information on the use of specific SFRs for each periph eral is included in the description of that peripheral Accumulator ACC is the Accumulator register The mnemonics for Accumulator Specific instructions however refer to the Accumulator simply as B Register The B register is used during multiply and divide operation
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3. ee 1 0 BIT POSITION rey 5 22 COMMAND RESPONSE FINAL RESPONSE 270427 17 COMMAND RESPONSE Identifies the type of command response POLL FINAL Identifies frame as being a polling request from the master station or the last in a series of frames from the master or secondary 1 1 If bits 1 0 1 1 the frame is identified as an unnumbered format type NONSEQUENCED FORMAT 270427 18 Figure 3 7 SDLC Control Field 7 29 intel 83C152 HARDWARE DESCRIPTION Following the informational control field comes the formation to be transferred In the supervisory format bits 1 0 0 1 bits 3 2 de termine which mode is being used When the mode is OO it indicates that the receive line of the station that sent the supervisory frame 15 enabled and ready to accept frames When the mode is Ol it indicates that previously a received frame was rejected The value in the receive count identifies which frame s need to be retransmit ted The standard commands are BITS 7 5 3 2 Command Disconnect DISC Response optional UP Function descriptor in information field CFGR Unnumbered Information UI Set initialization mode SIM When the mode is 10 the sending station is indicating that its receiver is not ready to accept frames Mode 11 is an illegal mode in SDLC proto
4. 270653 23 Figure 26 Reset Timing 5 37 ntel 8XC51FX HARDWARE DESCRIPTION While the RST pin is high the port pins ALE and PSEN are weakly pulled high After RST is pulled low it will take 1 to 2 machine cycles for ALE and PSEN to start clocking For this reason other devices can not be synchronized to the internal timings of the 8XC51FX Driving the ALE and PSEN pins to 0 while reset 15 active could cause the device to go into an indetermi nate state The internal reset algorithm redefines all the SFRs Ta ble 1 lists the SFRs and their reset values The internal RAM is not affected by reset On power up the RAM content is indeterminate 9 1 Power On Reset For CHMOS devices when is turned on an auto matic reset can be obtained by connecting the RST pin to VCC through a 1 uF capacitor Figure 27 The CHMOS devices do not require an external resistor like the HMOS devices because they have an internal pull down on the RST pin When power is turned on the circuit holds the RST pin high for an amount of time that depends on the capaci tor value and the rate at which it charges To ensure a valid reset the RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles Figure 27 Power on Reset Circuitry On power up should rise within approximately ten milliseconds The oscillator start up time will de pend on the oscillator frequency
5. 5 51 ARCHITECTURAL OVERVIEW Internal Data Memory is mapped in Figure 6 The memory space 15 shown divided into three blocks which are generally referred to as the Lower 128 the Upper 128 and SFR space Internal Data Memory addresses are always one byte wide which implies an address space of only 256 bytes However the addressing modes for internal RAM can in fact accommodate 384 bytes using a simple trick Direct addresses higher than 7FH access one memory space and indirect addresses higher than 7FH access a different memory space Thus Figure 6 shows the Up per 128 and SFR space occupying the same block of addresses through FFH although they are physi cally separate entities BIT ADDRESSABLE SPACE BIT ADDRESSES 0 7F RO R RESET VALUE OF STACK POINTER 270251 7 Figure 7 The Lower 128 Bytes of Internal RAM The Lower 128 bytes of RAM are present in all MCS 51 devices as mapped in Figure 7 The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as RO through R7 Two bits in the Program Status Word PSW select which register bank is in use This allows more efficient use of code space since register instructions are shorter than instructions that use direct addressing NO BIT ADDRESSABLE SPACES AVAILABLE AS STACK SPACE IN DEVICES WITH 256 BYTES RAM NOT IMPLEMENTED IN 8051 270251 8 Figure 8 The Upper 128 Bytes of Internal RAM
6. Timer 0 overflow flag TCON 6 TR1 Timer 1 run control bit TCON 7 TF1 Timer 1 overflow flag TDN Transmit Done flag see TSTAT TEN Transmit Enable bit see TSTAT TFNF Transmit FIFO Not Full flag see TSTAT TFIFO 85H TFIFO is a 3 byte FIFO that contains the transmission data for the GSC THO 08CH Timer 0 High byte contains the high byte for timer counter 0 ntel 08DH Timer 1 High byte contains the high byte for timer counter 1 TI Transmit Interrupt see SCON TLO 08AH Timer Low byte contains the low byte for timer counter 0 TL1 O8BH Timer 1 Low byte contains the low byte for timer counter 1 TM Transfer Mode see DCONO TMOD 089H 7 6 5 4 3 2 1 0 Cure ort wr wo aere ort wi TMOD 0 MO Mode selector bit for Timer 0 TMOD 1 M1 Mode selector bit for Timer O TMOD 2 C T Timer Counter selector bit for Timer 0 TMOD 3 GATE Gating Mode bit for Timer 0 TMOD 4 Mode selector bit for Timer 1 TMOD 5 M1 Mode selector bit for Timer 1 TMOD 6 C T Timer Counter selector bit for Timer 1 TMOD 7 GATE Gating Mode bit for Timer 1 TSTAT 008 Transmit Status Register 7 6 5 4 3 2 1 0 UR TSTAT 0 DMA DMA Select If set indicates that DMA channels are used to service the GSC FIFO s and GSC interrupts occur on TDN and RDN and also en ables UR to become set If cleared indicates that the GSC i
7. PX1H PTOH PXOH PCA interrupt priority high bit Timer 2 interrupt priority high bit Serial Port interrupt priority high bit Timer 1 interrupt priority high bit External interrupt 1 priority high bit Timer 0 interrupt priority high bit External interrupt priority high bit 4 11 intel Table 7 Priority Level Bit Values HE p ex ___ POWER DOWN MODE The 8 5 can exit Power Down with either hard ware reset or external interrupt Reset redefines all the SFRs but does not change the on chip RAM An exter nal interrupt allows both the SFRs except PD in PCON and the on chip RAM to retain their values 270783 5 Figure 6 Interrupt Sources To properly terminate Power Down the reset or exter nal interrupt should not be applied before is re stored to its normal operating level and must be held active long enough for the oscillator to restart and sta bilize normally less than 10 msec 4 12 8XC52 54 58 HARDWARE DESCRIPTION With an external interrupt INTO or INT1 must be en abled and configured as level sensitive before entering Power Down Holding the pin low restarts the oscilla tor and bringing the pin back high completes the exit After the RETI instruction is executed in the interrupt service routine the next instruction will be the one fol lowing the instruction tbat put the device in Power Down POWER OFF FLAG The Power Off Flag POF
8. X oscillator frequency Set ting the ECOMn bit in the mode register CCAPMn enables the comparator function PCA TIMER COUNTER 87C51GB HARDWARE DESCRIPTION For the Software Timer mode the MATn bit also needs to be set When a match occurs between the PCA timer and the compare registers a match signal is generated and the module s event flag CCFn is set An interrupt is then flagged if the ECCFn bit is set The inter rupt is generated only if it has been properly enabled Software must clear the event flag before the next inter rupt will be flagged During the interrupt routine a new 16 bit compare val ue can be written to the compare registers CCAPnH and CCAPnL Notice however that a write to CCAPnL clears the ECOMn bit which temporarily dis ables the comparator function while these registers are being updated so an invalid match does not occur write to CCAPnH sets the ECOMn bit and re enables the comparator For this reason user software should write to CCAPnL first then CCAPnH INTERRUPT CCAPMn MODE REGISTER 270897 22 Figure 20 PCA 16 Bit Comparator Mode Software Timer 6 29 intel 87C51GB HARDWARE DESCRIPTION 7 5 High Speed Output Mode The High Speed Output HSO mode toggles a CEXn pin when a match occurs between the PCA timer and a pre loaded value in a module s compare registers For this mode the TOGn bit needs to be set in addition to the ECOMn and bits in
9. PD DL BIT ADDRESSABLE 270427 3 Figure 2 2 Special Function Registers intel 83C152 HARDWARE DESCRIPTION Data Memory Map bits BIT ADDRESSES PO TCON P1 SCON P2 IE P3 IP P4 IEN1 PSW TSTAT A RSTAT B IPN1 Figure 2 3B Bit Addresses 7 9 intel 83C152 HARDWARE DESCRIPTION Byte SYMBOLIC NAME BIT MAP Address MSB LSB pos m4 mz Po mo BM ova AE once mom arne HABEN_ pred Jr reste Pomas Figure 2 3 Addresses 2 1 3 PROGRAM MEMORY The 83C152 contains 8K of ROM program memory and the 80C152 uses only external program memory Figure 2 4 shows the program memory locations and where they reside The user is allowed a maximum of EXTERNAL 64K of program memory In the 83C152 program memory fetches beyond 8K automatically access exter nal program memory When program memory is exter nally addressed all of the Port 2 pins emit the address Since all of Port 2 is affected by the address unused address pins cannot be used as normal I O ports even if less than 64K of memory is being accessed EXTERNAL IF EA 0 INTERNAL IF EA 1 0000H 270427 4 Figure 2 4 Program Memory intel 83C152 HARDWARE DESCRIPTION 2 2 Interrupt Structure interrupts and IPN1 F8
10. VILLLLLLELLLLL LLLI LL ELLE RECS a SNO J l l l l III LLI LI LLLA NOACK LTCOT TEN esl PXO 270427 2 83C152 HARDWARE DESCRIPTION 2 1 2 1 Bit Addressable Memory The C152 has several memory spaces in which the bits are directly addressed by their location The directly addressable bits and their symbolic names are shown in Figure 2 3A 2 3B and 2 3C Bit addresses O to 7FH reside in on board user data RAM in byte addresses 20H to 2FH see Figure 2 3A Bit addresses 80H to OFFH reside in the SFR memory space but not every SFR is bit addressable see Figure 2 3B The addressable bits are scattered throughout the SFRs The addressable bits occur every eighth SFR ad dress starting at 80H and occupy the entire byte Most of the bits that are addressable in the SFRs have been given symbolic names These names will often be ferred to in this or other documentation on the C152 Most assemblers also allow the use of the symbolic names when writing in assembly language These names are shown in Figure 2 3C ZA wr INTO RXD EXO tap Txt DEN GTXD GRXD Mt MO C T Mi Tri Ti ro TRO mi to SMOD ARB REQ GAREN XRCLK
11. 4 gi els ni pip P1 P2 p1 2 1 2 1 P2 DATA SAMPLED FLOAT PCH OR PCH OR R DPH OR P2 SFR OUT P2 SFR Figure 6 External Data Memory Read Cycle STATE 6 STATE 1 STATE 2 STATE 3 P1 P2 2 2 1 2 2 1 2 2 Figure 7 External Data Memory Write Cycle 6 12 270897 9 ntel 87C51GB HARDWARE DESCRIPTION Fetches from external Program Memory always use a 16 bit address Accesses to external Data Memory can use either 16 bit address MOVX DPTR or an 8 bit address MOVX Ri Whenever a 16 bit address is used the high byte of the address comes out on Port 2 where it is held for the duration of the read or write cycle The Port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1s This occurs when the MOVX G DPTR instruction is executed During this time the Port 2 latch the Special Function Regis ter does not have to contain 1s and the contents of the Port 2 SFR are not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the Port 2 SFR will reappear in the next cycle If an 8 bit address is being used MOVX Ri the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle In this case Port 2 pins c
12. O 0 1 0 1 GMOD 7 XTCLK External Transmit Clock If set an external 1X clock is used for the transmitter If cleared the internal baud rate generator provides the ntel 83C152 HARDWARE DESCRIPTION transmit clock The input clock is applied to P1 3 TxC The user software is responsible for setting or clearing this flag External receive clock is enabled by setting PCON 3 GO DMA Go bit see DCONO GRxD GSC Receive Data input an alternate function of one of the port 1 pins P1 0 This pin is used as the receive input for the GSC P1 0 must be programmed to a 1 for this function to operate GSC Global Serial Channel A high level multi pro tocol serial communication controller added to the 80C51BH core to accomplish high speed transfers of packetized serial data GTxD GSC Transmit Data output an alternate func tion of one of the port 1 pins P1 1 This pin is used as the transmit output for the GSC P1 1 must be pro grammed to a 1 for this function to operate HBAEN Hardware Based Acknowledge Enable see RSTAT HLDA Hold Acknowledge an alternate function of one of the port 1 pins P1 6 This pin is used to per form the HOLD ACKNOWLEDGE function for DMA transfers HLDA can be an input or an output depending on the configuration of the DMA channels P1 6 must be programmed to a 1 for this function to operate HOLD Hold an alternate function of one of the port 1 pins P
13. Po SMOD Double baud rate bit If Timer 1 is used to generate baud rate and SMOD 1 the baud rate is doubled when the Serial Port is used in modes 1 2 or 3 Not implemented reserved for future use Not implemented reserved for future use Not implemented reserved for future use General purpose flag bit GFO General purpose flag bit PD Power Down bit Setting this bit activates Power Down operation in the 80C51BH Available only in CHMOS IDL Idle Mode bit Setting this bit activates Idle Mode operation in the 80C51BH Available only in CHMOS If 1s are written to PD and IDL at the same time PD takes precedence User software should not write 1s to reserved bits These bits may be used in future MCS 51 products to invoke new features in that case the reset or inactive value of the new bit will be O and its active value will be 1 2 11 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET INTERRUPTS In order to use any of the interrupts in the MCS 51 the following three steps must be taken 1 Set the EA enable all bit in the IE register to 1 2 Set the corresponding individual interrupt enable bit in the IE register to 1 3 Begin the interrupt service routine at the corresponding Vector Address of that interrupt See Table below Interrupt Vector Source Address IE0 TF1 RI amp TI TF2 amp EXF2 In addition for external interrupts pins
14. Raw transmit or receive mode Almost all the options available from Table 3 1 be implemented with the proper software to perform the functions that are necessary for the options selected In Table 3 1 a judgment has been made by the authors on which options are practical and which are not What this means is that in Table 3 1 N should be inter preted as meaning that the option is either not practical when implemented with user software or that it cannot be done is used when that function is one of several that can be implemented with the GSC without additional user software The GSC is targeted to operate at bit rates up to 2 4 MBps using the external clock options and up to 2 MBps using the internal baud rate generator internal data formatting and on chip clock recovery The baud rate generator allows most standard rates to be achieved These standards include the proposed IEEE802 3 LAN standard 1 0MBps and the stan dard 1 544MBps The baud rate is derived from the crystal frequency This makes crystal selection impor tant when determining the frequency and accuracy of the baud rate The user needs to be aware that after reset the GSC is in CSMA CD mode IFS 256 bit times and a bit time equals 8 oscillator periods The GSC will remain in this mode until the interframe space expires If the user changes to SDLC mode or the parameters used in CSMA CD these changes will not take effect
15. 00000000 XXXXXXXX XXXXXXXX 7 00000000 CCAPOL CCAP1L CCAP2L CCAPSL CCAP4L EF 00000000 XXXXXXXX 7 00000000 1 2 4 00X00000 1 00 000 0000000 0000000 0000000 X0000000 0000000 PSW 00000000 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 00000000 00 00000000 00000000 00000000 00000000 IP SADEN X0000000 00000000 P3 IPH 11111111 X0000000 IE SADDR 00000000 00000000 p2 11111111 SCON SBUF 00000000 XXXXXXXX P1 11111111 TCON TMOD TLO TL1 THO TH1 00000000 00000000 00000000 00000000 00000000 00000000 PO SP DPL DPH PCON 87 11111111 00000111 00000000 00000000 00XX0000 Found in the 8051 core See 8051 Hardware Description for explanations of these SFRs See description of PCON SFR Bit PCON 4 is not affected by reset Undefined F8 FF E8 08 DF 00 07 C7 B8 BF BO B7 A8 AF 7 98 OF 90 97 88 8F 5 5 8XC51FX HARDWARE DESCRIPTION Table 3 PSW Program Status Word Register Address ODOH Bit Addressable Bit Reset Value 0000 0000B cv ao m ss ev gt 7 6 5 4 3 2 1 0 Function Carry flag Auxili
16. Enables the DMA done interrupt for Channel 1 IEN1 5 EGSTE Enables the GSC transmit error in terrupt IFS 0A4H Interframe Space determines the number of bit times separating transmitted frames in CSMA CD and SDLC IP 0B8H 7 6 5 4 3 2 1 9 12 ers Pa Allows the user software two levels of prioritization to be assigned to each of the interrupts in IE 1 assigns the corresponding interrupt in IE a higher interrupt than an interrupt with a corresponding 0 IP 0 PXO Assigns the priority of external interrupt INTO IP 1 PTO Assigns the priority of Timer O interrupt TO ntel 83 152 HARDWARE DESCRIPTION IP 2 PX1 Assigns the priority of external interrupt INTI IP 3 PT1 Assigns the priority of Timer 1 interrupt T1 IP 4 PS Assigns the priority of the LSC interrupt SBUF IPN1 OF8H 7 6 5 4 3 2 1 o paste poma pasty PGSRV Allows the user software two levels of prioritization to be assigned to each of the interrupts in IEN1 1 as signs the corresponding interrupt in IEN1 a higher in terrupt than an interrupt with a corresponding O IPN1 0 PGSR V Assigns the priority of GSC receive valid interrupt 1 PGSRE Assigns the priority of GSC error receive interrupt IPN1 2 PDMAO Assigns the priority of DMA done interrupt for Channel 0 IPN1 3 PGSTV Assigns the priority of GSC trans
17. Mode 0 0 Normal 0 1 Raw Transmit 1 0 Raw Receive 1 1 Alternate Backoff In raw receive mode the receiver operates as normal except that all the bytes following the BOF are loaded into the receive FIFO including the CRC The trans mitter operates as normal In raw transmit mode the transmit output is internally connected to the receiver input The internal connec tion is not at the actual port pin but inside the port latch All data transmitted is done without a preamble flag or zero bit insertion and without appending a CRC The receiver operates as normal Zero bit dele tion is performed In alternate backoff mode the standard backoff process is modified so the the backoff is delayed until the end of the IFS This should help to prevent collisions con stantly happening because the IFS time is usually larger than the slot time GMOD 7 XTCLK External Transmit Clock If set an external 1X clock is used for the transmitter If cleared the internal baud rate generator provides the transmit clock The input clock is applied to P1 3 XC The user software is responsible for setting or clearing this flag External receive clock is enabled by setting PCON 3 IFS 0A4H Interframe Spacing Determines the number of bit times separating transmitted frames in CSMA CD and SDLC A bit time is equal to 1 baud rate Only even interframe space periods can be used The number written into this register is divided by two and
18. P Samos atso ertrnal exouionisdeabied Programmed U Unprogrammed Any other combination of Lock Bits is not defined 8XC51FX Hardware Description HARDWARE DESCRIPTION OF THE 8XC51FX CONTENTS PAGE CONTENTS PAGE 1 0 INTRODUCTION 2 0 MEMORY 2 1 Program Memory 2 2 Data Memory 3 0 SPECIAL FUNCTION REGISTERS 4 0 PORT STRUCTURES AND OPERATION POWER SAVING MODES OPERATION 5 1 intel 8XC51FX HARDWARE DESCRIPTION 1 0 INTRODUCTION The 8XC51FX is a highly integrated 8 bit microcon troller based on the MCS 51 architecture As a member of the MCS 51 family the 8XC51FX is optimized for control applications Its key feature is the programma ble counter array PCA which is capable of measuring and generating pulse information on five 1 pins Also included are an enhanced serial port for multi proces sor communications an up down timer counter and a program lock scheme for the on chip program memory Since the 8XC51FX products are CHMOS they have two software selectable reduced power modes Idle Mode and Power Down Mode The 8XC51FX uses the standard 8051 instruction set and is pin for pin compatible with the existing MCS 51 family of products This document presents a comprehensive description of the on chip hardware features of the 8XC51FX It be gins with a discussion of the on chip memory and then discusses each of the peripherals listed below Please note that 8X
19. Priority bit 0 assigns low priority Position IP 7 Function reserved reserved IP 6 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 ceived simultaneously an internal polling sequence de termines which request is serviced Thus within each priority level there is a second priority structure deter mined by the polling sequence as follows Source Priority Within Level IEO highest TFO IE1 TF1 RI TF2 EXF2 gt lowest Note that the priority within level structure is only used to resolve simultaneous requests of the same priori ty level The IP register contains a number of unimplemented bits IP 7 and IP 6 are vacant in the 8052s and in the 8051s these and IP 5 are vacant User software should not write 1s to these bit positions since they may be used in future MCS 51 products How Interrupts Are The interrupt flags are sampled at 5592 of every ma chine cycle The samples are polled during the follow ing machine cycle The 8052 s Timer 2 interrupt cycle is different as described in the Response Time Section If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appro priate service routine provided this hardware generat ed LCALL is not blocked by any of the following con IP 5 Timer 2 interrupt priority bit Serial Port interrupt priority bit
20. Two Program Memory Lock Schemes The 8751BH 8752BH and 87C51 use the faster 8751BH 8752BH and 87C51 contain two Program Quick Pulse programming algorithm These de Memory locking schemes Encrypted Verify and Lock vices program at VPP 12 75V using a series of Bits twenty five 100 us PROG pulses per byte programmed This results in total programming time of Encryption Array Within the EPROM is an array of mately 26 seconds for the 8752BH 8 Kbytes and encryption bytes that are initially unprogrammed all 13 seconds for the 87C51 4 Kbytes 1 5 The user can program the array to encrypt the code bytes during EPROM verification The verifica Detailed procedures for programming and verifying tion procedure sequentially XNORs each code byte each device are given in the data sheets with one of the key bytes When the last key byte in the array is reached the verify routine starts over with the first byte of the array for the next code byte If the key Exposure to Light bytes are unprogrammed the XNOR process leaves the code byte unchanged With the key bytes programmed It is good practice to cover the EPROM window with the code bytes are encrypted and can be read correctly an opaque label when the device is in operation This is only if the key bytes are known in their proper order not so much to protect the EPROM array from inad Table 6 lists the number of encryption bytes available vertent erasure
21. ntel 83 152 HARDWARE DESCRIPTION RFIFO Receive FIFO RFIFO is 3 byte buffer that is loaded each time the GSC receiver has a byte of data Associated with RFIFO is a pointer that is automatically updated with each read of the FIFO A read of RFIFO fetches the oldest data in the FIFO RSTAT Receive Status Register 7 6 5 4 3 2 1 0 Figure 3 16 RSTAT RSTAT 0 HABEN Hardware Based Acknowledge Enable If set enables the hardware based acknowl edge feature The user software is responsible for setting or clearing this flag RSTAT 1 GREN Receiver Enable When set the receiver is enabled to accept incoming frames The user must clear RFIFO with software before enabling the receiver RFIFO is cleared by reading the contents of RFIFO until 0 After each read of RFIFO it takes one machine cycle for the status of RFNE to be updated Setting GREN also clears RDN CRCE AE and RCABT GREN is cleared by hardware at the end of a reception or if any receive errors are detected The user software is responsible for setting this flag and the GSC or user software can clear it The status of GREN has no effect on whether the receiver detects a collision in CSMA CD mode as the receiver input circuitry al ways monitors the receive pin RSTAT 2 Receive FIFO Not Empty set indicates that the receive FIFO contain
22. read from a reserved bit is indeterminate 6 2 Capture Compare Modules Each of the five compare capture modules has six pos sible functions it can perform 16 bit Capture positive edge triggered 16 bit Capture negative edge triggered 16 bit Capture both positive and negative edge triggered 16 bit Software Timer 16 bit High Speed Output 8 bit Pulse Width Modulator In addition module 4 can be used as a Watchdog Tim er The modules can be programmed in any combina tion of the different modes Each module has a mode register called CCAPMn n 0 1 2 3 or 4 to select which function it will perform The CCAPMn register is shown in Table 12 Note the ECCFn bit which enables the PCA interrupt 5 22 when a module s event flag is set The event flags CCFn are located in the CCON register and get set when a capture event software timer or high speed output event occurs for a given module Table 13 shows the combinations of bits in the CCAPMn register that are valid and have a defined function Invalid combinations will produce undefined results Each module also has a pair of 8 bit compare capture registers CCAPnH and CCAPnL associated with it These registers store the time when a capture event oc curred or when a compare event should occur For the PWM mode the high byte regiser CCAPnH controls the duty cycle of the waveform The next five sections describe each of the compare capture modes in de
23. 270251 2 Figure 2 MCS 51 Memory Structure CHMOS Devices Functionally the CHMOS devices designated with in the middle of the device name are all fully compatible with the 8051 but being CMOS draw less current than an HMOS counterpart To further exploit the power savings available in CMOS circuitry two re duced power modes are added Software invoked Idle Mode during which the CPU is turned off while the RAM and other on chip peripherals continue operating In this mode cur rent draw is reduced to about 15 of the current drawn when the device is fully active Software invoked Power Down Mode during which all activities suspended on chip RAM continues to hold its data In this mode the device typically draws less than 10 pA Although the 80C51BH is functionally compatible with its HMOS counterpart specific differences between the two types of devices must be considered in the design of an application circuit if one wishes to ensure complete interchangeability between the HMOS and CHMOS devices These considerations are discussed in the Ap plication 252 Designing with the 80C51BH For more information on the individual devices and features listed in Table 1 refer to the Hardware De scriptions and Data Sheets of the specific device MEMORY ORGANIZATION IN MCS 51 DEVICES Logical Separation of Program and Data Memory All MCS 51 devices have
24. 270252 30 3 34 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 5 6 STATE 3 Wapsi 1 P2 P1 2 p1 2 1 2 p1 P2 2 1 2 2 270252 31 Figure 38 External Data Memory Write Cycle STATE 5 STATE 6 STATE 1 STATE 2 STATE 3 STATE 4 STATE 5 P1 2 2 2 2 1 2 1 2 1 2 1 2 P1 P2 P3 P1 P2 INPUTS SAMPLED RST RST MOV PORT SRC OLD DATA NEW DATA MODE 0 Figure 39 Port Operation 270252 32 3 35 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 ADDITIONAL REFERENCES The following application notes and articles found in the Embedded Applications handbook Order Number 270648 1 AP 125 Designing Microcontroller Systems for Electrically Noisy Environments 2 AP 155 Oscillators for Microcontrollers 3 AP 252 Designing with the 80C51BH 4 AR 517 Using the 8051 Microcontroller with Resonant Transducers 8XC52 54 58 Hardware Description 8XC52 54 58 CONTENTS PAGE HARDWARE DESCRIPTION AUTO RELOAD Up or Down Counter 8 52 54 58 HARDWARE DESCRIPTION INTRODUCTION The 8 52 54 58 is a highly integrated 8 bit micro controller based on the MCS 51 architecture The key features are an enhanced serial port for multi processor communications
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26. All six ports in the 8 51 are bidirectional Each consists of a latch Special Function Register PO through P5 output driver and an input buffer All the ports except for Port 0 have Schmitt Trigger inputs The output drivers of Ports 0 and 2 and the input buff ers of Port 0 are used in accesses to external memory In this application Port O outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the Port 2 pins continue to emit the P2 SFR content All the Port 1 Port 3 Port 4 and most of Port 5 pins are multi functional They are not only port pins but also serve the functions of various special features as shown in Table 3 ADDR DATA READ LATCH 270897 2 A Port 0 Bit 87C51GB HARDWARE DESCRIPTION 4 1 Configurations Functional diagrams of a bit latch and I O buffer in each of the four ports are shown in Figure 2 The bit latch one bit in the port s SFR is represented as a Type D flip flop which clocks in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read a port
27. DIV AB will leave 13 in the Accumulator or 00001101B and the value 17 11H 00010001B in B since 251 13 X 18 17 Carry and OV will both be cleared 1 4 reso 199 DIV 15 Bro A 2 42 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DJNZ lt byte gt lt rel addr gt Function Decrement and Jump if Not Zero Description DJNZ decrements the location indicated by 1 and branches to the address indicated by the second operand if the resulting value is not zero An original value of 00H will underflow to OFFH No flags are affected The branch destination would be computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Internal RAM locations 40H 50H and 60H contain the values O1H 70H and 15H respec tively The instruction sequence DJNZ 40H LABEL__1 DJNZ SOH LABEL 2 DJNZ 60H LABEL 3 will cause a jump to the instruction at label LABEL 2 with the values and 15H in the three RAM locations The first jump was not taken because the result was zero This instruction provides a simple way of executing a pro
28. Figure 18 PCA 16 Bit Comparator Mode Software Timer and High Speed Output 5 25 intel 6 7 Pulse Width Modulator Mode Any or all of the five PCA modules can be pro grammed to be a Pulse Width Modulator output can be used to convert digital data to an analog signal by simple external circuitry The frequency of the PWM depends on the clock sources for the PCA timer With a 16 MHz crystal the maximum frequency of the PWM waveform is 15 6 KHz 0 1 2 or 4 Don t 8XC51FX HARDWARE DESCRIPTION generates 8 bit PWMs by comparing the low byte of the PCA timer CL with the low byte of the module s compare registers CCAPnL Refer to Figure 20 When CL lt CCAPnL the output is low When CL CCAPnL the output is high Tbe value in CCAPnL controls the duty cycle of the waveform To change the value in CCAPnL without output glitches the user must write to the high byte register CCAPnH This value is then shifted by hardware into CCAPnL when CL rolls over from OFFH to which corresponds to the next period of the output REGISTER x Don t Care CCAPMn MODE REGISTER 270653 17 Figure 20 PCA 8 Bit PWM Mode 5 26 DUTY CYCLE CCAPnH 100 00 8XC51FX HARDWARE DESCRIPTION OUTPUT WAVEFORM 270653 18 Figure 21 CCAPnH Varies Duty Cycle CCAPnH can contain any integer from 0 to 255 to vary the duty cycle from a 10096 to 0 496 see
29. XRL direct lt direct A 2 74 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XRL direct data Bytes 3 Cycles 2 Encoding 0011 immediate data Operation XRL direct lt direct data 2 75 8051 8052 and 80051 Hardware Description 8051 8052 and 80 51 Hardware Description CONTENTS PAGE CONTENTS PAGE PORT STRUCTURES AND OPERATION POWER SAVING MODES OF OPERATION 3 1 intel 8051 8052 AND 80C51 HARDWARE DESCRIPTION INTRODUCTION This chapter presents a comprehensive description of the on chip hardware features of the 51 micro controllers Included in this description are The port drivers and how they function both as ports and for Ports 0 and 2 in bus operations The Timer Counters The Serial Interface The Interrupt System Reset The Reduced Power Modes in the CHMOS devices The EPROM versions of the 8051 8052AH and 80C51BH The devices under consideration are listed in Table 1 it becomes unwieldy to be constantly referring to each of these devices by their individual names we will adopt a convention of referring to them generically as 8051s and 8052s unless a specific member of the group is being referred to in which case it will be specifically named The 8051s include the 8051 80C51BH and their ROMIess and versions 80525 the 8052 8032AH and 8752BH Figu
30. er PCON 4 GAREN GSC Auxiliary Receiver Enable Bit This bit needs to be set to a 1 to enable the recep tion of back to back SDLC frames A back to back SDLC frame is when the EOF and BOF is shared be tween two sequential frames intended for the same sta tion on the link If GAREN contains a 0 then the ceiver will be disabled upon reception of the EOF and by the time user software re enables the receiver the first bit s may have already passed in the case of back to back frames Setting GAREN to a 1 prevents the receiver from being disabled by the EOF but GREN will be cleared and can be checked by user software to determine that an EOF has been received GAREN has no effect if the GSC is in CSMA CD mode PRBS Pseudo Random Binary Sequence This register contains a pseudo random number to be used in the CSMA CD backoff algorithm The number is generated by using a feedback shift register clocked by the CPU phase clocks Writing all ones to the PRBS will freeze the value at all ones Writing any other value to it will restart the PRBS generator The PRBS is ini tialized to all zero s during RESET A read of location OEAH will not necessarily give the seed used in the backoff algorithm because the PRBS counters are clocked by internal CPU phase clocks This means the contents of the PRBS may have been altered between the time when the seed was generated and before a READ has been internally executed 7 45
31. 0 RCAP2H 8052 RCAP2L 8052 SCON Ek PCON HMOS PCON CHMOS 270252 21 Figure 26 Power on Reset Circuit 3 27 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 POWER ON RESET For HMOS devices when is turned on an automat ic reset can be obtained by connecting the RST pin to through 10 uF capacitor and to Vss through an 8 2 resistor Figure 26 The CHMOS devices do not require this resistor although its presence does no harm In fact for CHMOS devices the external resistor can be removed because they have an internal pulldown on the RST pin The capacitor value could then be re duced to 1 pF When power is turned on the circuit holds the RST pin high for an amount of time that depends on the capaci tor value and the rate at which it charges To ensure a valid reset the RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles On power up Vcc should rise within approximately ten milliseconds The oscillator start up time will de pend on the oscillator frequency For a 10 MHz crystal the start up time is typically 1 ms For a 1 MHz crystal the start up time is typically 10 ms With the given circuit reducing quickly to 0 caus es the RST pin voltage to momentarily fall below OV However this voltage is internally limited and will not harm the device NOTE The port pins will be in a rando
32. 11100010B with the carry unaffected Bytes 1 Cycles 1 Encoding 0000 0011 Operation RR 1 n 0 6 AO Function Rotate Accumulator Right through Carry flag Description eight bits the Accumulator and the carry flag are together rotated one bit to the right Bit 0 moves into the carry flag the original value of the carry flag moves into the bit 7 position No other flags are affected Example The Accumulator holds the value 0C5H 11000101B the carry is zero The instruction RRC A leaves the Accumulator holding the value 62 01100010B with the carry set Bytes 1 Cycles 1 Encoding 0001 0011 Operation RRC An 1 n 0 6 7 2 67 intel SETB lt bit gt Function Description Example SETB C Bytes Cycles Encoding Operation SETB bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Set Bit SETB sets the indicated bit to one SETB can operate on the carry flag or any directly addressable bit No other flags are affected The carry flag is cleared Output Port 1 has been written with the value 34H 00110100B The instructions SETB C SETB P1 0 will leave the carry set to 1 and change the data output on Port 1 to 35H 00110101B 1101 0011 SETB 1 2 1 mams SETB bit 1 2 68
33. 2 samples is allowed Thus sample sequences such as 11110000 00001111 and 111100000 000001111 are val id Sequences of the form 111100000 000000XXX are interpreted as collisions For these kinds of sequences the GSC recognizes the collision to have occurred within 1 5 8 to 1 3 4 bit times after the previous 1 to O transition Unexpected 1 to 0 Transition If the line is at a logic 1 during the first half of a bit cell then it is expected to make a 1 to O transition at the midpoint of the bit cell If the transition is missed it is assumed that this bit cell is the first half of an EOF flag 1 0 1 0 1 1 270427 14 Figure 3 3 Manchester Encoding 7 23 intel line idle for two bit times One bit time later which marks the midpoint of the next bit cell if there is still no 1 to 0 transition a valid EOF is assumed and the line idle bit LNI in TSTAT gets set However if the assumed EOF flag is interrupted by a 1 10 0 transition in the bit time following the first miss ing transition a collision is assumed In that case the GSC hardware recognizes the collision to have oc curred within 1 2 to 5 8 bit time after the unexpected transition 3 2 6 RESOLUTION OF COLLISIONS How the GSC responds to a detected collision depends on what it was doing at the time the collision was de tected What it might be doing is either transmitting or receiving a frame or it might be inactive GSC Inact
34. 84H Contains the Protocol bit PR the Preamble Length PL1 0 CRC Type CT Address Length AL Mode select M1 0 and External Trans mit Clock TXC This register is used for GSC opera tion only 0C8H Interrupt enable register for DMA and GSC interrupts IFS OA4H Determines the number of bit times sepa rating transmitted frames OF8H Interrupt priority register DMA and GSC interrupts MYSLOT 0F5H Contains the Jamming mode bit DCJ the Deterministic Collision Resolution Algo rithm bit DCR and the DCR slot address for the GSC P4 Contains the memory image of Port 4 PRBS 0E4H Contains a pseudo random number to be used in CSMA CD backoff algorithms May be read or written to by user software RFIFO 4 RFIFO is used to access 3 byte FIFO that contains the receive data from the GSC RSTAT OE8H Contains the Hardware Based Ac knowledge Enable bit HABEN Global Receive En able bit GREN Receive FIFO Not Empty bit Receive Done bit RDN CRC Error bit Alignment Error bit AE Receiver sion Abort detect bit RCABT and the Overrun bit OVR used with both DMA and GSC SARLO 0A2H Contains the low byte of the source address for DMA transfers SARHO 0A3H Contains the high byte of the source address for DMA transfers SARL 0B2H Same as SARLO but for Chan 1
35. DPTR AB AB A A Rn A Ri A data direct A direct data A direct A Ri A data direct A direct data A Rn A direct A Ri A data direct A direct data MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 10 8051 Instruction Set Summary Continued Increment Data Pointer Multiply A amp B Divide B Decimal Adjust Accumulator AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive OR register to Accumulator Exclusive OR direct byte to Accumulator Exclusive OR indirect RAM to Accumulator Exclusive OR immediate data to Accumulator Exclusive OR Accumulator to direct byte Exclusive OR immediate data to direct byte Clear Accumulator Complement Accumulator MOV MOV MOV MOV 2 22 Mnemonic SWAP A DATA TRANSFER A direct A Ri A data Rn data direct Rn direct direct direct Ri direct data Oscillator Description Period Byte LOGICAL OPERATIONS Continued Rotate Accumulator Left
36. Figure 18 Serial Port Mode 1 TCLK RCLK and Timer 2 are Present in the 8052 8032 Only Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit 3 19 times are synchronized to the divide by 16 counter not to the write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse oc curs one bit time after that intel As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10 divide by 16 rollover after write to SBUF Reception is initiated by a detected 1 10 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a tr
37. Finally for a master to communicate with both slaves at once the address must have bit 1 1 and bit 2 O Notice however that bit 3 is a don t care for both slaves This allows two different addresses to select both slaves 1111 0001 or 1111 0101 If a third slave was added that required its bit 3 O then the latter address could be used to communicate with Slave 1 and 2 but not Slave 3 The master can also communicate with all slaves at once with the Broadcast Address It is formed from the logical OR of the SADDR and SADEN registers with 6 36 zeros defined as don t cares The don t cares also allow flexibility in defining the Broadcast Address but in most applications a Broadcast Address will be OFFH The feature works the same way in the 8 bit mode Mode 1 as in the 9 bit modes except that the stop bit takes the place of the 9th data bit If SM2 is set the RI flag is set only if the received byte matches the Given or Broadcast Address and is terminated by a valid stop bit Setting the SM2 bit has no effect in Mode 0 On reset the SADDR and SADEN registers are initial ized to which defines the Given and Broadcast Addresses as XXXX XXXX all don t cares This as sures the 8XC51GB serial port to be backwards com patibility with other MCS 51 products which do not implement Automatic Addressing 8 4 Baud Rates The baud rate in Mode O is fixed Mode 0 Baud Rate cesar resume The baud rate in Mode 2
38. PORT 3 PORT 4 PORT 5 PORT 6 POWER CONTROL GSC PSEUDO RANDOM SEQUENCE PROGRAM STATUS WORD GSC RECEIVE BUFFER RECEIVE STATUS DMA amp GSC DMA SOURCE ADDR 0 LOW DMA SOURCE ADDR 0 HIGH DMA SOURCE ADDR 1 LOW DMA SOURCE ADDR 1 HIGH LOCAL SERIAL CHANNEL LSC BUFFER LOCAL SERIAL CHANNEL LSC CONTROL GSC SLOT TIME STACK POINTER GSC TRANSMIT COLLISION COUNTER TIMER CONTROL GSC TRANSMIT BUFFER TIMER 0 HIGH TIMER 1 HIGH TIMER 0 LOW TIMER 1 LOW TIMER MODE TRANSMIT STATUS DMA amp GSC intel TFIFO 85H is used to access 3 byte FIFO that contains the transmission data for the GSC TSTAT OD8H Contains the DMA Service bit Transmit Enable bit TEN Transmit Not Full bit Transmit Done bit TDN Transmit Collision Detect bit TCDT Underrun bit UR No Acknowledge bit NOACK and the Re ceive Data Line bit LND This register is used with both DMA and GSC The general purpose flag bits and GF1 that exist on the 80C51BH are no longer available on the C152 GFO has been renamed GFIEN GSC Flag Idle En able and is used to enable idle fill flags Also GF1 has been renamed XRCLK External Receive Clock En able and is used to enable the receiver to be clocked externally 2 1 2 DATA MEMORY Internal data memory consists of 256 bytes as shown in Figure 2 1 The first 128 bytes are addressed exactly like an 80C51BH using di
39. The serial port can be programmed such that when the stop bit is received the serial port interrupt will be acti vated only if the received byte is an address byte RB8 1 This feature is enabled by setting the SM2 bit in SCON A way to use this feature in multiprocessor sys tems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an ad dress byte which identifies the target slave Remember an address byte has its 9th bit set to 1 whereas a data byte has its 9th bit set to 0 the slave processors should have their SM2 bits set to 1 so they will only be interrupted by an address byte In fact the 8XC51GB has an Automatic Address Recognition feature which allows only the addressed slave to be interrupted That is the address comparison occurs in hardware not soft ware On the 8051 serial port an address byte inter rupts all slaves for an address comparison The addressed slave then clears its SM2 bit and pre pares to receive the data bytes that will be coming The other slaves are unaffected by these data bytes They are still waiting to be addressed since their SM2 bits are all set ntel 87C51GB HARDWARE DESCRIPTION 8 3 Automatic Address Recognition Automatic Address Recognition reduces the CPU time required to service the serial port Since the CPU is only interrupted when it receives its own address the software overhead to compare addre
40. Timer 1 interrupt priority bit IP 4 IP 3 IP 2 External interrupt 1 priority bit IP 1 Timer 0 interrupt priority bit IP 0 External interrupt O priority bit User software should never write 1s to unimplemented bits since they may be used in future MCS 51 products Figure 23 IP Interrupt Priority Register If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are re INTERRUPTS ARE POLLED INTERRUPT INTERRUPT GOES LATCHED ACTIVE ditions 1 An interrupt of equal or higher priority level is al ready in progress The current polling cycle is not the final cycle in the execution of the instruction in progress The instruction in progress is RETI or any write to the IE or IP registers 2 3 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condi tion 2 ensures that the instruction in progress will be INTERRUPT ROUTINE 270252 20 This is the fastest possible response when C2 is the final cycle of instruction other than RETI an access to IE or Figure 24 Interrupt Response Timing Diagram 3 24 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 completed before vectoring to any service routine Con dition 3 ensures that if the instruction in progress is RETI or any access to IE or IP then at least one more in
41. Upon reset the DCEN bit is set to 0 so that Timer 2 will default to count up When DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin TIMER 2 INTERRUPT 270897 14 Figure 12 Timer 2 Capture Table 8 T2MOD 2 Control Register Address Not Bit Addressable Bit Symbol Function 2 DECN Not implemented reserved for future use Timer 2 Output Enable bit Down Count Enable bit When set this allows Timer 2 to be configured as an up down counter Reset Value XXXX XX00B i 1 1 7 6 5 4 3 2 1 0 software should not write 15 to reserved bits These bits may used future 8051 family products to new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate 6 18 intel In the auto reload mode with DCEN 0 there are two options selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow The overflow also caus es the timer registers to be reloaded with the 16 bit value in RCAP2H and RCAP2L The values in RCAP2H and RCAP2L are preset by software If 2 1 16 bit reload can be triggered either by an overflow or by a 1 10 0 transition at external input T2EX This transition also sets the EXF2 bit Either the TF
42. array is not available without the Lock Bit Program code verification is performed as usual except that each code byte comes out exclusive NOR ed XNOR with one of the key bytes Therefore to read the ROM EPROM code the user has to know the encryp tion key bytes in their proper sequence Unprogrammed bytes have the value OFFH If the En cryption Array is left unprogrammed all the key bytes have the value OFFH Since any code byte XNOR ed intel with leaves the byte unchanged leaving the En cryption Array unprogrammed in effect bypasses the encryption feature Program Lock Bits Also included in the Program Lock scheme are Lock Bits which can be enabled to provide varying degrees of protection Table 9 lists the Lock Bits and their corresponding influence on the mi crocontroller Refer to Table 8 for the Lock Bits avail able on the various products The user is responsible for programming the Lock Bits on EPROM devices On ROM devices LB1 is automatically set by the factory when the encryption array is submitted The Lock Bit is not available without the encryption array on ROM devices Erasing the EPROM also erases the Encryption Array and the Lock returning the part to full functionali ty Table 8 Program Protection Lock Bits Encrypt Array LB1 LB1 LB1 LB1 LB2 LB3 LB1 182 LB3 LB1 LB2 LB3 8XC52 54 58 HARDWARE DESCRIPTION ONCE MODE The ON Circuit Emulation ONCE mode facilita
43. cycle is not the final cycle in the execution of the instruction in progress 3 The instruction in progress is RETI or any write to the IE or IP registers Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condi tion 2 ensures that the instruction in progress will be completed before vectoring to any service routine Con dition 3 ensures that if the instruction in progress is RETI or any write to IE or IP then at least one more instruction will be executed before any interrupt is vec tored to The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle If the interrupt flag for a level sensitive external interrupt is active but not being responded to for one of the above conditions and is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every poll ing cycle is new The polling cycle LCALL sequence is illustrated in the Interrupt Response Timing Diagram Note that if an interrupt of a higher priority level goes active prior to 5 2 of the machine cycle labeled C3 in the diagram then in accordance with the above rules it will be vectored to during C5 and C6 without any in struction of the lower priority routine having been exe cute
44. event the pin had a 1 and lost it to a glitch INPUT DATA READ PORT PIN 270653 5 CHMOS Configuration pFET 1 is turned on for 2 osc periods after Q makes a 0 10 1 transition During this time pFET 1 also turns on pFET 3 through the inverter to form a latch which holds the 1 pFET 2 is also on Port 2 is similar except that it holds the strong pullup on while emitting 1s that are address bits See text Accessing External Memory Figure 4 Ports 1 and 3 Internal Pullup Configurations 5 9 ntel 8XC51FX HARDWARE DESCRIPTION 4 3 Port Loading and Interfacing The output buffers of Ports 1 2 and 3 can each sink 1 6 m at 0 45 These port pins can be driven by open collector and open drain outputs although 0 to 1 transitions will not be fast since there is little current pulling the pin up An input 0 turns off pullup pFET3 leaving only the very weak pullup pFET2 to drive the transition In external bus mode Port 0 output buffers can each sink 3 2 at 0 45 V However as port pins they require external pullups to be able to drive any inputs See the latest revision of the data sheet for design in information 4 4 Read Modify Write Feature Some instructions that read a port read the latch and others read the pin Which ones do which The instruc tions that read the latch rather than the pin are the ones that read a value possibly change it and then rewrite it to the latch These are called
45. internal bus in response to a read pin signal from the CPU Some instructions that read a port activate the read latch signal and others activate the read pin signal See the Read Modify Write Feature section As shown in Figure 2 the output drivers of Ports O and 2 are switchable to an internal ADDRESS and AD DRESS DATA bus by an internal CONTROL signal for use in external memory accesses During external memory accesses the P2 SFR remains unchanged but the PO SFR gets 1s written to it Table 4 Alternate Port Functions Port Pin P0 0 ADO P0 7 AD7 P1 0 T2 1 1 2 P1 2 ECI 1 3 1 4 1 1 5 2 1 6 P1 7 CEX4 2 0 8 P2 7 A15 P3 0 RXD P3 1 TXD P3 2 INTO P3 3 INT P3 4 TO P3 5 T1 P3 6 WR P3 7 RD Alternate Function Multiplexed Byte of Address Data for External Memory Timer 2 External Clock Input Clock Out Timer 2 Reload Capture Direction Control PCA External Clock Input PCA Module 0 Capture Input Compare PWM Output PCA Module 1 Capture Input Compare PWM Output PCA Module 2 Capture Input Compare PWM Output PCA Module 3 Capture Input Compare PWM Output PCA Module 4 Capture Input Compare PWM Output High Byte of Address for External Memory Serial Port Input Serial Port Output External Interrupt 0 External Interrupt 1 Timer 0 External Clock Input Timer 1 External Clock Input Write Strobe for External Memory Read
46. it cannot be re entered until at least one instruction of the interrupt ed program is executed One way to use this feature for single stop operation is to program one of the external interrupts say INTO to be level activated The service routine for the interrupt will terminate with the follow ing code JNB P3 2 Here Till INTO Goes High JB P3 Wait Here Till it Goes Low RETI Go Back and Execute One Instruction Now if the INTO pin which is also the P3 2 pin is held normally low the CPU will go right into the External Interrupt 0 routine and stay there until INTO is pulsed from low to high to low Then it will execute RETI 20 back to the task program execute one instruction and immediately re enter the External Interrupt O rou tine to await the next pulsing of P3 2 One step of the task program is executed each time P3 2 is pulsed 12 OSC PERIODS 55 56 51 52 3 54 55 56 51 52 53 54 55 56 51 52 3 4 _ Cy INTERNAL RESET SIGNAL SAMPLE RST SAMPLE RST The reset input is the RST pin which is the input to Schmitt Trigger reset is accomplished by holding the RST pin high for at least two machine cycles 24 oscillator periods while the oscillator is running The CPU responds by generating an internal reset with the timing shown in Figure 25 The external reset signal is asynchronous to the internal clock The RST
47. located at PCON 4 is set by hardware when rises from 0 to approximately 5V POF can also be set or cleared by software This allows the user to distinguish between a cold start reset and warm start reset A cold start reset is one that is coincident with being turned on to the device after it was turned off A warm start reset occurs while is still applied to the device and could be generated for example by an exit from Power Down Immediately after reset the user s software can check the status of the POF bit POF 1 would indicate a cold start The software then clears POF and com mences its tasks 0 immediately after reset would indicate a warm start must remain above for POF to retain a 0 Program Memory Lock In some microcontroller applications t is desirable that the Program Memory be secure from software piracy The 8 5 has varying degrees of program protection depending on the device Table 8 outlines the lock schemes available for each device Encryption Array Within the EPROM ROM is an ar ray of encryption bytes that are initially unprogrammed all 1 5 For EPROM devices the user can program the encryption array to encrypt the program code bytes during EPROM verification For ROM devices the user submits the encryption array to be programmed by the factory If an encryption array is submitted LB1 will also be programmed by the factory The encryption
48. not reduced before Power Down is invoked If the Os cillator Fail Detect circuitry is not disabled before en tering powerdown the part will reset itself see Section 11 0 Oscillator Fail Detect Table 28 shows the status of external pins during Power Down mode Table 28 Status of the External Pins during Power Down Mode Program Ports Memory 3 4 5 Internal Data Data Data Data External Float Data Data Data The 8XC51GB can exit Power Down with either a hardware reset or external interrupt Reset redefines most of the SFRs but does not change the on chip RAM external interrupt allows both the SFRs and the on chip RAM to retain their values To properly terminate Power Down the reset or exter nal interrupt should not be executed before is re stored to its normal operating level and must be held active long enough for the oscillator to restart and sta bilize normally less than 10 ms With an external interrupt INTO or must be en abled and configured as level sensitive Holding the pin low restarts the oscillator and bringing the pin back high completes the exit After the RETI instruction is executed in the interrupt service routine the next in struction will be the one following the instruction that put the device in Power Down 14 3 Power Off Flag The Power Off Flag POF located at PCON 4 is set by hardware when rises from to 5V POF can also be set or cleare
49. operand are listed in Table 3 Thus the ANL lt byte gt instruction may take any of the forms ANL direct addressing ANL A R1 indirect addressing ANL A R6 register addressing ANL A 53H immediate constant of the logical instructions that are Accumulator specific execute in lus using 12 MHz clock The others take 2 ps Note that Boolean operations can be performed on any byte in the lower 128 internal Data Memory space or the SFR space using direct addressing without having to use the Accumulator The XRL lt byte gt data in struction for example offers a quick and easy way to invert port bits as in XRL If the operation is in response to interrupt not using the Accumulator saves the time and effort to stack it in the service routine The Rotate instructions RL A RLC A etc shift the Accumulator 1 bit to the left or right For a left rota tion the MSB rolls into the LSB position For a right rotation the LSB rolis into the MSB position 5 51 ARCHITECTURAL OVERVIEW The SWAP A instruction interchanges the high and low nibbles within the Accumulator This is a useful operation in manipulations For example if the Accumulator contains a binary number which is known to be less than 100 it can be quickly converted to BCD by the following code MOV 10 DIV AB SWAP A ADD Dividing the number by 10 leaves the tens digit in the low nibble of the
50. oscillator frequency 5 21 8XC51FX HARDWARE DESCRIPTION Table 11 CCON PCA Counter Control Register Address 0D8H Bit Addressable Bit Function CF Reset Value 00X0 00008 on ocra core core cor 56 7 6 5 4 3 2 1 0 PCA Counter Overflow flag Set by hardware when the counter rolls over CF flags an interrupt if bit ECF in CMOD is set CF may be set by either hardware or software but can only be cleared by software CR by software to turn the PCA counter off CCF4 cleared by software CCF3 cleared by software CCF2 cleared by software CCF1 cleared by software CCF0 cleared by software NOTE PCA Counter Run control bit Set by software to turn the PCA counter on Must be cleared Not implemented reserved for future use PCA Module 4 interrupt flag Set by hardware when a match or capture occurs Must be PCA Module 3 interrupt flag Set by hardware when a match or capture occurs Must be PCA Module 2 interrupt flag Set by hardware when a match or capture occurs Must be PCA Module 1 interrupt flag Set by hardware when a match or capture occurs Must be PCA Module 0 interrupt flag Set by hardware when a match or capture occurs Must be User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value
51. read modify write in structions Listed below are the read modify write in structions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL logical e g ANL ORL logical e g ORL P2 XRL logical EX OR e g XRL P3 JBC if bit 1 and clear bit e g JBC 1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 STATE 1 STATE 2 STATE 3 STATE 4 P1 2 1 2 2 P 2 DJNZ decrement and jump if not zero e g DJNZ P3 LABEL MOV move carry bit to bit Y of Port X CLR PX Y clear bit Y of Port X SETB PX Y set bit Y of Port X It is not obvious that the last three instructions in this list are read modify write instructions but they are They read the port byte all 8 bits modify the addressed bit then write the new byte back to the latch The reason that read modify write instructions are di rected to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor and interpret it as a 0 Reading the latch rather than the pi
52. 1 and associated timings for trans mit receive intel HARDWARE DESCRIPTION OF THE 8051 8052 80 51 RXD P3 0 ALT OUTPUT FUNCTION TXD P3 1 ALT OUTPUT FUNCTION RXCLOCK RI RECEIVE START 441111110 RXD P3 0 ALT INPUT FUNCTION 8051 INTERNAL BUS 333253 54 2002 523304 9690 6 323334 96 00 e s musa 3182833433 96 828254 96 96 ALE WRITE senn 3672 SHIFT Our 2 X PL 6 TRANSMIT RXD DATA TXD SHIFT CLOCK 3 1 5691 WRITE SCON CLEAR RI Bohn te J pacai e SHIFT n n n f n RECEIVE RXD DATA 020 001 002 93 poe gt _ TXD SHIFT CLOCK Figure 17 Serial Port Mode 0 270252 15 3 18 intel TIMER 1 OVERFLOW TIMER 2 OVERFLOW START TXCLOCK RXCLOCK RI RX CONTROL START DETECTOR TX WRITE TO SBUF HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 8051 INTERNAL BUS es ZERO DETECTOR SHIFT pata TX CONTROL SEND LOAD SBUF SHIFT 1FFH I 8051 INTERNAL BUS SEND DATA 1 1 TRANSMIT SHIFT 1 1 1 wwo X X I 02 X 01 Y D X Ds pa sroPBT _ YY J STARTBIT 316 RESET STOP BIT RECEIVE N SHIFT 270252 16
53. 1 if SM2 0 8 is the stop bit that was received In mode 0 RB8 is not used TI SCON 1 Transmit interrupt flag Set by hardware at the end of the 8th bit time in mode O or at the beginning of the stop bit in the other modes Must be cleared by software RI SCON 0 Receive interrupt flag Set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes except see SM2 Must be cleared by software Description Baud Rate SHIFT REGISTER Fosc 12 8 Bit UART Variable 9 Bit UART Fosc 64 OR Fosc 32 9 Bit UART Variable SERIAL PORT SET UP Table 9 SM2 VARIATION Single Processor Environment SM2 0 Multiprocessor Environment SM2 1 GENERATING BAUD RATES Serial Port in Mode 0 Mode 0 has a fixed baud rate which is 1 12 of the oscillator frequency To run the serial port in this mode none of the Timer Counters need to be set up Only the SCON register needs to be defined Osc Freq Baud Rate au e T Serial Port in Mode 1 Mode 1 has a variable baud rate The baud rate can be generated by either Timer 1 or Timer 2 8052 only 2 19 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET USING TIMER COUNTER 1 TO GENERATE BAUD RATES For this purpose Timer 1 is used in mode 2 Auto Reload Refer to Timer Setup section of this chapter K x Oscillator Freq Baud Rate 222 12x 256 THI If SMOD 0 then K If SMOD 1 then K 1
54. 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on 2 if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX Start stop control for Timer 2 A logic 1 starts the timer Timer or counter select Timer 2 0 Internal timer OSC 12 or OSC 2 in baud rate generator mode 1 External event counter falling edge triggered Capture Reload flag When set captures will occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow CAPTURE MODE 16 bit timer or counter which upon overflow sets bit TF2 in T2CON
55. 36 through 39 show when the various strobe and port signals are clocked internally The figures do not show rise and fall times of the signals nor do they show propagation delays between the XTAL signal and events at other pins Rise and fall times are dependent on the external load ing that each pin must drive They are often taken to be something in the neighborhood of 10 nsec measured between 0 8V and 2 0V Propagation delays are different for different pins For a given pin they vary with pin loading temperature VCC and manufacturing lot If the XTAL waveform is taken as the timing reference prop delays may vary from 25 to 125 nsec The AC Timings section of the data sheets do not refer ence any timing to the XTAL waveform Rather they relate the critical edges of control and input signals to each other The timings published in the data sheets include the effects of propagation delays under the specified test conditions intel HARDWARE DESCRIPTION OF THE 8051 8052 80 51 2 3 4 1 2 P1 p2 P1 2 2 1 2 2 p 2 2 p 2 270252 29 Figure 36 External Program Memory Fetches 6 DUE STATE 4 STATE 5 P1 P2 p1 2 1 22 1 2 1 2 2 pi 2 P2 OR OR B Figure 37 External Data Memory Read Cycle
56. 5 AR6 AR bit addr code addr code addr 1 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 As A 2 25 intel 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 11 Instruction Opcodes in Hexadecimal Order Continued Hex Number Hex Number Mnemonic Operands Mnemonic Operands Code ofBytes Code of Bytes 1 A RO 1 SUBB 1 1 A R1 1 5088 A R2 1 A RO 1 SUBB A R3 1 A R1 1 SUBB 1 A R2 1 SUBB AR5 1 A R3 1 SUBB A R6 1 1 5088 7 1 5 2 ORL C bit addr 1 A R6 2 AJMP code addr 1 7 2 C bit 2 code addr 1 INC DPTR 2 code addr 1 MUL AB 2 C bit addr 1 2 Ro data addr 2 data 2 R1 data 3 data addr data 2 MOV Ro data addr 2 GRO data 2 MOV R1 data addr 2 R1 data 2 MOV Re data addr 2 RO data 2 MOV R3 data addr 2 R1 data 2 MOV R4 data addr 2 R2 data 2 MOV R5 data addr 2 83 4 data 2 MOV R6 data addr 2 4 data 2 MOV R7 data addr 2 R5 data 2 ANL C bit addr 2 R6 data 2 ACALL code addr 2 R7 data 2 CPL bit addr 2 code addr 1 CPL 2 addr 2 C bit addr 3 CJNE A data addr code addr 1 A GA PC 3 CJNE RO data cod
57. 51 products IDLE MODE An instruction that sets causes that to be the last instruction executed before going into the Idle mode In the Idle mode the internal clock signal is gated off to the CPU but not to the Interrupt Timer and Serial Port functions The CPU status is preserved in its entirety the Stack Pointer Program Counter Program Status Word Accumulator and all other reg isters maintain their data during Idle The port pins hold the logical states they had at the time Idle was activated ALE and PSEN hold at logic high levels There two ways to terminate the Idle Activation of any enabled interrupt will cause PCON O to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruc tion to be executed will be the one following the in struction that put the device into Idle 270252 22 Figure 27 Idle and Power Down Hardware 3 28 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 MSB LSB Gro PD o Position PCON 7 Symbol Name and Function Double Baud rate bit When set to a 1 and Timer 1 is used to generate baud rate and the Serial Port is used in modes 1 2 or 3 Reserved Reserved Reserved Generai purpose flag bit General purpose flag bit Power Down bit Setting this bit activates power down operation Idle mode bit Setting this bit activates idle mode operation 1s
58. 8XC152 as listed below Pin GSC data input pin GSC data output pin GSC enable signal for an external driver GSC input pin for external transmit clock GSC input for external receive clock hold input output hold acknowledge input output 10 17 Port 2 Port 2 is an 8 bit bi directional port with internal pullups Port 2 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current on the data sheet because of the internal pullups Port 2 emits the high order address byte during fetches from external Program Memory if EBEN is pulled low During accesses to external Data Memory that use 16 bit addresses MOVX DPTR and DMA operations Port 2 emits the high order address byte in these applications it uses strong internal pullups when emitting 1s During accesses to external Data Memory that use 8 bit addresses Ri Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high order address bits during program verification Port 3 Port 3 is 8 bit bi directional 1 port with internal pullups Port pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are external
59. Accumulator and the ones digit in the B register The SWAP and ADD instructions move the tens digit to the high nibble of the Accumulator and the ones digit to the low nibble Data Transfers INTERNAL RAM Table 4 shows the menu of instructions that are avail able for moving data around within the internal memo ry spaces and the addressing modes that can be used with each one With a 12 MHz clock all of these in structions execute in either 1 or 2 ps The MOV lt dest gt src instruction allows data to be transferred between any two internal RAM or SFR locations without going through the Accumulator Re member the Upper 128 byes of data RAM can be ac cessed only by indirect addressing and SFR space only by direct addressing Note that in all MCS 51 devices the stack resides in on chip RAM and grows upwards The PUSH instruc tion first increments the Stack Pointer SP then copies the byte into the stack PUSH and POP use only direct addressing to identify the byte being saved or restored Table 4 A List of the 51 Data Transfer Instructions that Access Internal Data Memory Space Cee MOV det A lt de gt a 2 J X x x 1 x 16 bit immediateconstant x 2 gt x PP Mov x 12 X 1 1 12 Addressing Modes Execution X
60. CPL C CPL bit JC rel JNC rel JB bit rel J bit rel bit rel IE S 2 __2 2 2 NB BC how easily internal be moved to a port pin MOV MOV C FLAG P1 0 C In this example FLAG is the name of any addressable bit in the Lower 128 or SFR space An I O line the LSB of Port 1 in this case is set or cleared depending on whether the flag bit is 1 or O The Carry bit in the PSW is used as the single bit Accu mulator of the Boolean processor Bit instructions that refer to the Carry bit as C assemble as Carry specific instructions CLR etc The Carry bit also a direct address since it resides in the PSW register which is bit addressable Note that the Boolean instruction set includes ANL and ORL operations but not the XRL Exclusive OR operation An XRL operation is simple to implement in software Suppose for example it is required to form the Exclusive OR of two bits C bit XRL bit2 The software to do that could be as follows MOV C bit1 JNB bit2 OVER CPL OVER continue First bit is moved to the Carry If bit2 0 then C now contains the correct result That is bit XRL bit2 bit if bit2 0 On the other hand if bit2 1C now contains the complement of the correct result It need only be inverted CPL C to complete the opera tion This code uses the JNB instruction one of a series of bit test ins
61. Counters Mode 3 is different The four operating modes are described in the following text MODE 0 Either Timer in Mode 0 is an 8 bit Counter with a divide by 32 prescaler This 13 bit timer is MCS 48 compatible Figure 7 shows the Mode 0 operation as it applies to Timer 1 In this mode the Timer register is configured as a 13 Bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TF1 The counted input is enabled to the Timer when 1 and either GATE Oor INTI 1 Setting 1 allows the Timer to be controlled by external input INT1 to facilitate pulse width measurements TR1 is a control bit in the Special Function Register TCON Figure 8 GATE is in TMOD The 13 Bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are inde terminate and should be ignored Setting the run flag 1 does not clear the registers Mode 0 operation 15 the same for Timer 0 as for Timer 1 Substitute TRO and INTO for the correspond ing Timer 1 signals in Figure 7 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 MODE 1 Mode 1 is the same as Mode 0 except that the Timer register is being run with all 16 bits LSB Timer 0 Timer 1 Gating control when set Timer Counter x is enabled only while INTx pin is high and control pin is set When cleared Timer x is enabled
62. Figure 21 7 0 SERIAL INTERFACE The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both ac cessed through Special Function Register SBUF Actu ally SBUF is two separate registers a transmit buffer and a receive buffer Writing to SBUF loads the trans mit register and reading SBUF accesses a physically separate receive register The serial port control and status register is the Special Function Register SCON shown in Table 14 This reg ister contains the mode selection bits SMO and 5 the SM2 bit for the multiprocessor modes see Multi processor Communications section tbe Receive En able bit REN the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits TI and RI The serial port can operate in 4 modes Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted re ceived 8 data bits LSB first The baud rate is fixed at 1 12 the oscillator frequency Mode 1 10 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first
63. Figure 35 Reset 6 49 When power is turned on the circuit holds the RESET pin high for an amount of time that depends on the capacitor value and the rate at which it charges To ensure a valid reset the RESET pin must be held low long enough to allow the oscillator to start up plus two machine cycles On power up should rise within approximately ten milliseconds The oscillator start up time will de pend on the oscillator frequency For a 10 MHz crystal the start up time is typically 1 ms For a 1 MHz crystal the start up time is typically 10 ms Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location This is because the SFRs spe cifically the Program Counter may not get properly initialized 14 0 POWER SAVING MODES For applications where power consumption is critical the 8XC51GB provides two power reducing modes of operation Idle and Power Down The input through which backup power is supplied during these opera tions is Vcc The Idle and Power Down modes are activated by setting bits IDL and PD respectively in the SFR PCON Table 26 Figure 36 shows the Idle and Power Down circuitry In the Idle mode IDL 1 the oscillator continues to run and the Interrupt Serial Port PCA and Timer blocks continue to be clocked but the clock signal is gated off to the CPU In Power Down PD 1 the oscillator
64. Figure 4 14 4 5 Summary of DMA Control Bits DCONn DAS IDA sas isa pone Go DAS specifies the Destination Address Space If DAS 0 the destination is in External Data Memory If DAS 1 and IDA 0 the destination is a Special hold holda if ARB O AND REQ 0 return 1 if SARn if ARB if REQ XRAM OR DARn XRAM HLDA HULDA else return return 1 end hold_holda Function Register SFR If DAS 1 and IDA 1 the destination is in Internal Data RAM IDA Increment Destination Address If IDA 1 the destination address is automatically incremented after each byte transfer If IDA 0 it is not SAS specifies the Source Address Space If SAS 0 the source is in Externa Data Memory If SAS 1 and ISA 0 the source is an SFR If SAS 1 and ISA 1 the source is Internal Data RAM ISA Increment Source Address If ISA 1 the source address is automatically incremented after each byte transfer If ISA 0 it is not DM Demand Mode If DM 1 the DMA Channel operates in Demand Mode In Demand Mode the DMA is initiated either by an external signal or by a Serial Port flag depending on the value of the TM bit If DM 0 the DMA is requested by setting the GO bit in software TM Transfer Mode If DM 1 then TM selects whether a DMA is initiated by an external signal TM or by a Serial Port flag TM 0 If DM 0 then TM selects whether the
65. INTO and INT1 3 2 and P3 3 must be set to 1 and depending on whether the interrupt is to be level or transition activated bits ITO or IT1 in the TCON register may need to be set to 1 ITx O level activated ITx 1 transition activated IE INTERRUPT ENABLE REGISTER BIT ADDRESSABLE If the bit is 0 the corresponding interrupt is disabled If the bit is 1 the corresponding interrupt is enabled IE 7 Disables all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit IE 6 implemented reserved for future use ET2 IE 5 Enable or disable the Timer 2 overflow or capture interrupt 8052 only ES 4 Enable or disable the serial port interrupt ETI JE 3 X Enable or disable the Timer 1 overflow interrupt EX1 IE 2 Enable or disable External Interrupt 1 ETO IE Enable or disable the Timer overflow interrupt EX0 Enable or disable External Interrupt 0 User software should not write 15 to reserved bits These bits may be used in future MCS 51 products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 2 12 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1 R
66. If SMODO 0 then accesses to 7 are to SMO If SMODO 1 then accesses to 7 are to FE Automatic Address Recognition Automatic Address Recognition reduces the CPU time required to service the serial port Since the CPU is only interrupted when it receives its own address the software overhead to compare addresses is eliminated With this feature en abled in one of the 9 bit modes the Receive Interrupt RD flag will only get set when the received byte corre sponds to either a Given or Broadcast address NOTE 05 FREQ IS DIVIDED BY 2 12 T2 PIN TRANSITION DETECTION 8XC52 54 58 HARDWARE DESCRIPTION TIMER 1 OVERFLOW 1 SMOD1 INTERRUPT Figure 5 Timer 2 in Baud Rate Generator Mode A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an ad dress byte which identifies the target slave Remember an address byte has its 9th bit set to 1 whereas a data byte has its 9th bit set to O All the slave processors should have their SM2 bits set to 1 so they will only be interrupted by an address byte The Automatic Address Recognition feature allows only the addressed slave to be interrupted In this mode the address comparison occurs in hardware not software On the 80C51 serial port an address byte interrupts al slaves for an address comparison The a
67. If the interrupt was level activated then the external requesting source is what controls the request flag rather than the on chip hardware The ex ternal interrupts are enabled through bits EXO and in the IE register and EX2 EX3 EX4 5 and EX6 in the IEA register Since the external interrupt pins are sampled once each machine cycle an input high or low should hold for at least 12 oscillator periods to ensure sampling If the 6 42 external interrupt is transition activated the external source has to hold the request pin high for at least one cycle and then hold it low for at least one cycle to ensure that the transition is seen so that interrupt re quest flag IEx will be set IEx will be automatically cleared by the CPU when the service routine is called If external interrupt INTO or INTI is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt serv ice routine is completed or else another interrupt will be generated ntel 12 2 Timer Interrupts Timer 0 and Timer 1 interrupts are generated by and TF1 in register TCON which are set by a rollover in their respective Timer Counter registers the excep tion is Timer 0 in Mode 3 When a timer interrupt 15 generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to These tim
68. It is not obvious that the last three instructions in this list are read modify write instructions but they are 1 STATE 2 STATE 3 STATE 4 STATE 5 STATE 6 STATE 1 They read the port byte all 8 bits modify the addressed bit then write the new byte back to the latch The reason that read modify write instructions are di rected to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor and interpret it as a O Reading the latch rather than the pin will return the correct value of 1 4 5 Accessing External Memory Accesses to external memory are of two types accesses to external Program Memory and accesses to external Data Memory Accesses to external Program Memory use signal PSEN program store enable as the read Strobe Accesses to external Data Memory use RD or WR alternate functions of P3 7 and P3 6 to strobe the memory Refer to Figures 5 through 7 STATE 2 2 1 2 2 1 22 2 270897 7 Figure 5 External Program Memory Fetches 6 11 87C51GB HARDWARE DESCRIPTION p1 2 P1 2 Pt 2 2
69. M1 Mode selector bit NOTE 1 MO Mode selector bit NOTE 1 NOTE 1 Operating Mode 0 13 bit Timer MCS 48 compatibie 16 bit Timer Counter 1 2 8 bit Auto Reload Timer Counter 3 Timer O TLO is an 8 bit Timer Counter controlled by the standard Timer O control bits THO is an 8 bit Timer and is controlled by Timer 1 control bits 3 Timer 1 Timer Counter 1 stopped intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TIMER SET UP Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes It is assumed that only one timer is being used at a time If it is desired to run Timers 0 and 1 simultaneously in any mode the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 Tables 5 and 6 For example if it is desired to run Timer 0 in mode 1 GATE external control and Timer 1 in mode 2 COUNTER then the value that must be loaded into TMOD is 69H 09H from Table 3 ORed with 60H from Table 6 Moreover it is assumed that the user at this point is not ready to turn the timers on and will do that at a different point in the program by setting bit TRx Gn TCON to 1 TIMER COUNTER 0 As a Timer Table 3 TIMER 0 FUNCTION INTERNAL CONTROL NOTE 1 EXTERNAL CONTROL NOTE 2 13 bit Timer 16 bit Timer 8 bit Auto Reload two 8 bit Timers As a Counter Table 4 COUNTER 0 FUNCTION INTERNAL CONTRO
70. NOR ed XNOR with intel one of the key bytes Therefore to read the ROM EPROM code the user has to know the encryp tion key bytes in their proper sequence Unprogrammed bytes have the value OFFH If the En cryption Array is left unprogrammed all the key bytes have the value OFFH Since any code byte XNOR ed with OFFH leaves the byte unchanged leaving the En cryption Array unprogrammed in effect bypasses the encryption feature When using the encryption array feature one impor tant factor should be considered If a code byte has the value OFFH verifying the byte will produce the encryp tion byte value If a large block gt 64 bytes of code is left unprogrammed a verification routine will display the encryption array contents For this reason all un used code bytes should be programmed with some val ue other than OFFH and not all of them the same val ue This will ensure maximum program protection Program Lock Bits Also included in the Program Lock scheme are Lock Bits which can be enabled to provide varying degrees of protection Table 25 lists the Lock Bits and their corresponding influence on the mi crocontroller Refer to Table 24 for the Lock Bits avail able on the various products The user is responsible for programming the Lock Bits on EPROM devices On ROM devices LB1 is automatically set by the factory when the encryption array is submitted The Lock Bit is not available without the encryption array o
71. Operation MUL A 7 o lt A X 8 15 8 Function Operation Description Execution continues at the following instruction Other than the PC no registers or flags are affected Example It is desired to produce a low going output pulse on bit 7 of Port 2 lasting exactly 5 cycles simple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be inserted This may be done assuming no interrupts are enabled with the instruction sequence CLR 2 7 SETB 27 1 Cycles 1 Encoding 000010000 Operation 1 intel 1 MCS9 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ORL lt dest byte gt lt src byte gt Function Logical OR for byte variables Description ORL performs the bitwise logical OR operation between the indicated variables storing the results in the destination byte No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the Accumulator holds 11000011B and RO holds 55H 01010101B
72. PC In the latter case the PC is incremented to the address of the following instruction before being added with the Accumulator otherwise the base register is not al tered Sixteen bit addition is performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected Example value between 0 and 3 is in the Accumulator The following instructions will translate the value in the Accumulator to one of four values defined by the DB define byte directive REL PC MOVC A A PC RET DB 66H DB 7TTH DB 88H DB 99H If the subroutine is called with the Accumulator equal to O1H it will return with 77H in the Accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the Accumulator instead MOVC DPTR Bytes 1 Cycles Encoding Operation MOVC A DPTR MOVC A A PC Bytes Cycles 2 Operation MOVC lt 1 PC 2 57 MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET intel MOVX lt dest byte gt lt src byte gt Function Description Example Move External The MOVX instructions transfer data between the Accumulator and a byte of external data memory hence the X appended to MOV There are two types of instructions differing i
73. PSW 7 CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ALU OPERANDS PSW 6 AUXILIARY CARRY FLAG RECEIVES CARRY OUT FROM 1 OF ADDITION OPERANDS 5 GENERAL PURPOSE STATUS FLAG PSW 4 REGISTER BANK SELECT BIT 1 MCS 51 ARCHITECTURAL OVERVIEW PSW 0 PARITY OF ACCUMULATOR SET BY HARDWARE TO 1 IF IT 5 000 NUMBER OF 15 OTHERWISE IT tS RESET TO 0 PSW 1 USER DEFINABLE FLAG PSW 2 OVERFLOW FLAG SET BY ARITHMETIC OPERATIONS PSW 5 REGISTER BANK SELECT BIT O 270251 10 Figure 10 PSW Program Status Word Register MCS 51 Devices The next 16 bytes above the register banks form a block of bit addressable memory space The MCS 51 instruc tion set includes a wide selection of single bit instruc tions and the 128 bits in this area can be directly ad dressed by these instructions The bit addresses in this area are 00H through 7FH All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing The Upper 128 Figure 8 can only be accessed by indirect addressing The Upper 128 bytes of RAM are not implemented in the 8051 but are in the devices with 256 bytes of RAM See Table 1 Figure 9 gives a brief look at the Special Function Reg ister SFR space SFRs include the Port latches tim ers peripheral controls etc These registers can only be accessed by direct addressing In general all MCS 51 microcontrollers have the same SFRs as the 8051 and at the
74. PX4 PX4H External interrupt 4 interrupt priority bits External interrupt 3 interrupt priority bits PX2 PX2H External interrupt 2 interrupt priority bits PC1 PC1H PCA1 interrupt priority bits PSEP PSEPH Serial Expansion Port interrupt priority bits NOTE User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate 6 46 intel 87C51GB HARDWARE DESCRIPTION Table 24 Interrupt Polling Sequence 1 Highest 2 15 Lowest Note that the priority within level structure is used to resolve simultaneous requests of the same prior ity level 12 7 Interrupt Processing The interrupt flags are sampled at S5P2 of every ma chine cycle The samples are polled during the follow ing machine The Timer 2 overflow interrupt 15 slightly different as described in the Interrupt Re sponse Time section If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority level is al ready in progress 2 The current polling
75. Port 0 latch the Special Function Regis ter thus obliterating the information in the Port 0 SFR Also a MOV PO instruction must not take place during external memory accesses If the user writes to Port 0 during an external memory fetch the incoming code byte is corrupted Therefore do not write to Port O if external program memory is used External Program Memory is accessed under two con ditions 1 Whenever signal is active or 2 Whenever the program counter PC contains an ad dress greater than 1FFFH 8K for the 8XCSIFA or 3FFFH 16K for the 8 51 or 7FFFH 32K for the 87C51FC This requires that the ROMless versions have wired to Vss enable the lower 8K 16K or 32K program bytes to be fetched from external memory When the CPU is executing out of external Program Memory all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose I O During external program fetches they output the high byte of the PC with the Port 2 drivers using the strong pullups to emit bits that are 15 5 12 5 0 TIMERS COUNTERS The C51FX has three 16 bit Timer Counters Timer 0 Timer 1 and Timer 2 Each consists of two 8 bit regis ters THx and TLx x 0 1 and 2 All three can be configured to operate either as timers or event counters In the Timer function the TLx register is incremented every machine cycle Thus one can think of it as count ing machine cycles Since a ma
76. Program Memory can be accessed with indexed addressing and it can only be read This addressing mode is intended for reading look up tables in Program Memory A 16 bit base register either DPTR or the Program Counter points to the base of the table and the Accumulator is set up with the table entry number address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer Another type of indexed addressing is used in the case jump instruction In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data Arithmetic Instructions The menu of arithmetic instructions is listed in Table 2 The table indicates the addressing modes that can be used with each instruction to access the byte oper and For example the ADD A lt byte gt instruction can be written as ADD A 7FH direct addressing ADD A GRO indirect addressing ADD A R7 register addressing ADD A 127 immediate constant The execution times listed in Table 2 assume a 12 MHz clock frequency All of the arithmetic instructions exe cute 1 us except the INC DPTR instruction which takes 2 js and the Multiply and Divide instructions which take 4 ps Note that any byte in the internal Data Memory space can be incremented or decremented without going through the Accumulator One of the INC instructions operates on the 16 bit Data Pointer The Dat
77. RAM location 20H holds the value 75H 01110101B The instruction XCH A GRO will leave RAM location 20H holding the values 3FH 00111111B and 75H 01110101B in the accumulator 1 1 XCH Rn 2 1 XCH A direct 1 1 Ri 2 72 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XCHD A Ri Function Exchange Digit Description XCHD exchanges the low order nibble of the Accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the internal RAM location indirectly addressed by the specified register The high order nibbles bits 7 4 of each register are not affected No flags are affi Example contains the address 20H The Accumulator holds the value 36H 00110110B Internal RAM location 20H holds the value 75H 01110101B The instruction XCHD A RO will leave RAM location 20H holding the value 76H 01110110B and 35H 00110101B in the Accumulator Bytes 1 Cycles 1 Operation XCHD Ris o XRL lt dest byte gt lt src byte gt Function Logical Exclusive OR for byte variables Description XRL performs the bitwise logical Exclusive OR operation between the indicated variables storing the results in the destination No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate
78. Since the hardware does not clear an event flag when the inter rupt is vectored to the flag must be cleared in software CCAPMn MODE REGISTER In the interrupt service routine the 16 bit capture value must be saved in RAM before the next capture event occurs A subsequent capture on the same CEXn pin will write over the first capture value in CCAPnH and CCAPnL 6 4 16 Bit Software Timer Mode In the compare mode the 16 bit value of the PCA tim er is compared with a 16 bit value pre loaded in the module s compare registers CCAPnH CCAPnL The comparison occurs three times per machine cycle in order to recognize the fastest possible clock input i e x oscillator frequency Setting the ECOMRn bit in the mode register CCAPMn enables the comparator function as shown in Figure 18 For the Software Timer mode the MATn bit also needs to be set When a match occurs between the PCA timer and the compare registers a match signal is generated and the module s event flag CCFn is set An interrupt is then flagged if the bit is set The inter rupt is generated only if it has been properly enabled Software must clear the event flag before the next inter rupt will be flagged INTERRUPT PCA TIMER COUNTER 270653 14 Figure 17 PCA 16 Bit Capture Mode 5 24 intel 8XC51FX HARDWARE DESCRIPTION During the interrupt routine new 16 bit compare val ue can be written to the compare registers CCA
79. TO 00 TRANSITION 0 CL lt CCAPnL REGISTER 270897 25 Figure 23 8 Bit PWM 6 32 intel CCAPnH can contain any integer from 0 to 255 to vary the duty cycle from a 100 to 0 4 A 096 duty cycle can be obtained by writing directly to the port pin with the CLR bit instruction To calculate the CCAPnH val ue for a given duty cycle use the following equation CCAPnH 256 1 Duty Cycle where CCAPnH is an 8 bit integer and Duty Cycle is expressed as a fraction See Figure 24 8 0 SERIAL PORT The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from DUTY CYCLE CCAPnH 1007 00 87C51GB HARDWARE DESCRIPTION the receive register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed through Special Function Register SBUF Ac tually SBUF is two separate registers a transmit buffer and a receive buffer Writing to SBUF loads the trans mit register and reading SBUF accesses a physically separate receive register The serial port control and status register is the Special Function Register SCON Table 17 This register con tains the mode selection bits
80. This bit can then be used to generate In the capture mode there are two options selected by an interrupt If EXEN2 1 Timer 2 still does the bit EXEN2 T2CON If EXEN2 0 Timer 2 is a above but with the added feature that a 1 10 0 tran TIMER 2 INTERRUPT 270653 9 Figure 12 Timer 2 in Capture Mode 5 16 8XC51FX HARDWARE DESCRIPTION intel sition at external input T2EX causes the current value in the Timer 2 registers TH2 and TL2 to be captured into registers RCAP2H and RCAP2L respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set The EXF2 bit like TF2 can generate an interrupt The capture mode is illustrated in Figure 12 AUTO RELOAD MODE UP OR DOWN COUNTER Timer 2 can be programmed to count up down when configured in its 16 bit auto reload mode This feature is invoked by a bit named DCEN Down Counter En able located in the SFR TZMOD see Table 9 Upon reset the DCEN bit is set to O so that Timer 2 will defauit to count up When DCEN is set Timer 2 can count up or down depending on the value of the 2 pin Figure 13 shows Timer 2 automatically counting up when DCEN 0 In this mode there two options selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 counts up to OFFFFH and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16 bit value in RCAP2H and RCAP2L The values in 2 and RCAP2
81. Transfer from External Memory to Internal Memory aa OSC PERIODS n 72 OSC PERIODS ALE N N 2222 22 22 oma cvete eri hcm 270427 32 Figure 4 5 DMA Transfer from External Memory to External Memory 4 3 1 REQUESTER MODE The Requester Mode is selected by setting the control bit REQ which resides in PCON In that mode when the C152 wants to do a DMA to External Data Memo ry it first generates a Hold Request signal HLD and waits for Hold Acknowledge signal HLDA before commencing the DMA operation Note that program execution continues while HLDA is awaited The DMA is not begun until a logical 0 is detected at the HLDA pin Then once the DMA has begun it goes to completion regardless of the logic level at HLDA The protocol is activated only for DMAs not for pro gram fetches or MOVX operations and only for to or from External Data Memory If the data destination and source are both internal to the C152 the HLD HLDA protocol is not used The HLD output is an alternate function of port pin P1 5 and the HLDA input is an alternate function of port pin P1 6 7 51 4 3 2 ARBITER MODE For DMAs that are to be driven by some device other than the C152 a different version of the Hold Hold Acknowledge protocol is available In this version the device which is to drive the DMA sends a Hold Re quest signal HLD to the C152 If the C152 is current ly performin
82. Watchdog These circuits are used in applications that are subject to electrical noise power glitches electrostatic discharges etc or where high reliability is required The Watchdog Timer function is only available on PCA module 4 In this mode every time the count in the PCA timer matches the value stored in module 4 s compare registers an internal reset is generated See Figure 19 The bit that selects this mode is WDTE in the CMOD register Module 4 must be set up in either compare mode as a Software Timer or High Speed Out put When the PCA Watchdog Timer times out it resets the chip just like a hardware reset except that it does not drive the reset pin high To hold off the reset the user has three options 1 periodically change the compare value so it will never match the PCA timer 2 periodically change the PCA timer value so it will never match the compare value 3 disable the Watchdog by clearing the WDTE bit before a match occurs and then later re enable it The first two options are more reliable because the Watchdog Timer is never disabled as in option 3 The second option is not recommended if other PCA mod ules are being used since this timer is the time base for all five modules Thus in most applications the first solution is the best option If a Watchdog Timer is not needed module 4 can still be used in other modes CCAPMn MODE REGISTER n 0 1 2 3 or 4 x Don t Care 270653 15
83. When a ce CRYSTAL FREQUENCY in MHz ramic resonator is used C1 and C2 are normally select 270252 34 ed to be of somewhat higher values typically 47 The manufacturer of the ceramic resonator should be Figure 31 ESR vs Frequency consulted for recommendations on the values of these capacitors 3 31 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Frequency tolerance and temperature range are deter mined by the system requirements A more in depth discussion of crystal specifications ce ramic resonators and the selection of values for C1 and C2 can be found in Application Note 155 tors for Microcontrollers which is included in the Embedded Applications Handbook To drive the HMOS parts with an external clock source apply the external clock signal to XTAL2 and ground XTALI as shown in Figure 32 A pullup resis tor may be used to increase noise margin but is op tional if VOH of the driving gate exceeds the VIH MIN specification of XTAL2 270252 25 Figure 32 Driving the HMOS MCS 51 Parts with an External Clock Source CHMOS Versions The on chip oscillator circuitry for the 80C51BH Shown in Figure 33 consists of a single stage linear inverter intended for use as a crystal controlled posi tive reactance oscillator in the same manner as the HMOS parts However there are some important dif ferences One difference is that the 80C51BH is able to turn off
84. X gt j ntel MCS 51 ARCHITECTURAL OVERVIEW but the stack itself is accessed by indirect addressing using the SP register This means the stack can go into the Upper 128 if they are implemented but not into SFR space In devices that do not implement the Upper 128 if the SP points to the Upper 128 PUSHed bytes are lost and POPped bytes are indeterminate The Data Transfer instructions include 16 bit MOV that can be used to initialize the Data Pointer DPTR for look up tables in Program Memory or for 16 bit external Data Memory accesses The A byte instruction causes the Accumu lator and addressed byte to exchange data The XCHD A GRi instruction is similar but only the low nibbles are involved in the exchange To see how XCH and XCHD can be used to facilitate data manipulations consider first the problem of shift ing an 8 digit BCD number two digits to the right Fig ure 11 shows how this can be done using direct 5 and for comparison how it can be done using XCH instructions To aid in understanding how the code works the contents of the registers that are holding the BCD number and the content of the Accumulator are shown alongside each instruction to indicate their status after the instruction has been executed MOV MOV MOV MOV MOV A 2EH 2EH 2DH 2DH 2CH 2CH 2BH 2BH 0 12 a Using direct MOVs 14 bytes 9 us CLR XCH XCH A A 2BH A 2CH
85. a float state and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored after a normal reset is applied THE ON CHIP OSCILLATORS HMOS Versions The on chip oscillator circuitry for the HMOS HMOS I and HMOS II members of the MCS 51 fam ily is a single stage linear inverter Figure 29 intended for use as a crystal controlled positive reactance oscil lator Figure 30 In this application the crystal is oper ated in its fundamental response mode as an inductive reactance in parallel resonance with capacitance exter nal to the crystal intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 23 Figure 29 On Chip Oscillator Circuitry in the HMOS Versions of the MCS 51 Family In general crystals used with these devices typically have the following specifications ESR Equivalent Series Resistance see Figure 31 Shunt Capacitance 7 0 pF max Load Capacitance 30 pF 3 pF Drive Level 1mwW 270252 24 Figure 30 Using the HMOS On Chip Oscillator ESR OHMS The crystal specifications and capacitance values C1 and C2 in Figure 30 are not critical 30 pF can be used in these positions at any frequency with good quality crystals ceramic resonator can be used in place of 4 8 12 16 the crystal in cost sensitive applications
86. addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins Example If the Accumulator holds 11000011B and register 0 holds OAAH 10101010B then the instruction XRL A RO will leave the Accumulator holding the value 69H 01101001B When the destination is a directly addressed byte this instruction can complement combina tions of bits in any RAM location or hardware register The pattern of bits to be complement ed is then determined by a mask byte either a constant contained in the instruction or a variable computed in the Accumulator at run time The instruction XRL 1 00110001 will complement bits 5 4 and O of output Port 1 2 78 intel XRL A Rn Bytes Cycles Encoding Operation A direct Bytes Cycles Encoding Operation XRL 8 Bytes Cycles Encoding Operation XRL A data Bytes Cycles Encoding Operation direct A Bytes Cycles Encoding Operation 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 XRL Rn 2 1 0110 0101 direct address XRL A direct 1 1 XRL Ri 2 1 0100 XRL lt A data 2 1
87. an internal polling sequence de termines which request is serviced Thus within each priority level there is a second priority structure deter mined by the polling sequence shown in Table 19 Note that the priority within level structure is only used to resolve simultaneous requests of the same priori ty level Table 19 Interrupt Priority within Level Polling Sequence INTO Timer 0 INTI Timer 1 PCA Serial Port Timer 2 Highest 1 2 3 4 5 6 7 Lowest 8XC51FX Interrupt Priority Structure In the 8XC51FX a second Interrupt Priority register IPH has been added increasing the number of priori ty levels to four Table 20 shows this second register The added register becomes the MSB of the priority select bits and the existing IP register acts as the LSB This scheme maintains compatibility with the rest of the MCS 51 family Table 21 shows the bit values and priority levels associated with each combination 8XC51FX HARDWARE DESCRIPTION Table 21 Priority Level Bit Values Bits IPHx interrupt Priority Level How Interrupts are Handled 9 The interrupt flags are sampled at 5 2 of every ma chine cycle The samples are polled during the follow ing machine cycle The Timer 2 interrupt cycle is slightly different as described in the Response Time section If one of the flags was in a set condition at 5 2 of the preceding cycle the polling cycle will find
88. an internal reset is generated see Figure 22 The bit that selects this mode is WDTE in the CMOD register Module 4 must be set up in either compare mode as a Software Timer or High Speed Output INTERRUPT CCAPMn MODE REGISTER 270897 23 Figure 21 PCA 16 Bit Comparator Mode High Speed Output 87C51GB HARDWARE DESCRIPTION t CCAP4L PCA TIMER COUNTER 4 MODE REGISTER 270897 24 Figure 22 Watchdog Timer Mode To hold off the reset the user has three options 1 periodically change the compare value so it will nev er match the PCA timer 2 periodically change the PCA timer value so it will never match the compare value 3 disable the Watchdog by clearing the WDTE bit be fore a match occurs and then later re enable it The first two options are more reliable because the Watchdog Timer is never disabled as in option 3 The second option is not recommended if other PCA mod ules are being used since this timer is the time base for all five modules Thus in most applications the first solution is the best option The watchdog routine should not be part of an inter rupt service routine Why Because if the program 6 31 counter goes astray and gets stuck in an infinite loop interrupts will still be serviced and the watchdog will not reset the controller Thus the purpose of the watch dog would be defeated Instead call this subroutine from the main program within 655
89. and DEN be comes inactive at the end of a reset then Reset will have to be held low for a minimum of four machine cycles 2 4 Ports 4 5 and 6 Ports 4 5 and 6 operation is identical to Ports 1 3 on the 80C51BH The description of port operation can be found in the 8051 52 Hardware Description Chapter of the Intel Embedded Controller Handbook Ports 5 and 6 exist only on the JB and JD version of the C152 and can either function as standard I O ports or can be configured so that program memory fetches are per formed with these two ports To configure ports 5 and 6 as standard 1 0 ports EBEN is tied to a logic low When in this configuration ports 5 and 6 operation is identical to that of port 4 except they are not bit ad dressable To configure ports 5 and 6 to fetch program memory EBEN is tied to a logic high When using ports 5 and 6 to fetch the program memory the signal EPSEN is used to enable the external memory device instead of PSEN Regardless of which ports are used to fetch program memory all data memory fetches occur over ports 0 and 2 The 80C152JB and 80C152JD available as ROMless devices only ALE is still used to latch the address in all configurations Table 2 1 sum izes the control signals and how the ports may be used 2 5 Timer Counters The 80C51BH and C152 have the same pair of 16 bit general purpose timer counters The user should refer 83C152 HARDWARE DESCRIPTION to the I
90. and must be held active long enough for the oscillator to restart and sta bilize normally less than 10 msec With an external interrupt INTO or INT must be en abled and configured as level sensitive Holding the pin low restarts the oscillator and bringing the pin back high completes the exit After the RETI instruction is executed in the interrupt service routine the next in struction will be the one following the instruction that put the device in Power Down 10 3 Power Off Flag The Power Off Flag POF located at PCON 4 is set by hardware when rises from O to 5 Volts POF can also be set or cleared by software This allows the user to distinguish between a cold start reset and a warm start reset A cold start reset is one that is coincident with being turned on to the device after it was turned off A 5 40 8XC51FX HARDWARE DESCRIPTION warm start reset occurs while Vcc is still applied to the device and could be generated for example by a Watchdog Timer or an exit from Power Down Immediately after reset the user s software can check the status of the POF bit POF 1 would indicate a cold start The software then clears POF and com mences its tasks POF 0 immediately after reset would indicate a warm start must remain above 3 volts for POF to retain 0 11 0 EPROM VERSIONS The 8XC51FX uses the Improved Quick Pulse pro ing algorithm These devices program at V
91. are written to PD and IDL at the same time PD takes precedence The reset value of PCON is 0XXX0000 In the HMOS devices the PCON register only contains SMOD The other four bits are implemented only in the CHMOS devices User software should never write 13 to unimplemented bits since they may be used in future MCS 51 products 6 5 4 PCON 3 PCON 2 PCON 0 Figure 28 PCON Power Control Register The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal oper ation or during 14 For example an instruction that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits The other way of terminating the Idle mode is with a hardware reset Since the clock oscillator is still run ning the hardware reset needs to be held active for only two machine cycles 24 oscillator periods to complete the reset The signal at the RST pin clears the IDL bit directly and asynchronously At this time the CPU resumes program execution from where it left off that is at the instruction following the one that invoked the Idle Mode As shown in Figure 25 two or three machine cycles of program execution may take place before the internal reset algorithm takes control On chip hard ware inhibits access to the internal RAM during this time but access to the port pins is not
92. be different This is accomplished by using Timer 2 for the receiver or transmitter and using Timer 1 for the other function Setting RCLK and or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 5 The baud rate generator mode is similar to the auto re load mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in Modes 1 and 3 are determined by Timer 2 s overflow rate as follows Timer 2 Overflow Rate Modes 1 and 3 Baud Rates 16 intel 8XC52 54 58 HARDWARE DESCRIPTION The Timer can be configured for either timer or counter operation In most applications it is config ured for timer operation CP T2 0 The timer operation is different for Timer 2 when it s being used as a baud rate generator Normally as a timer it incre ments every machine cycle thus at 1 the oscillator frequency As a baud rate generator however it incre ments every state time thus at the oscillator fre quency The baud rate formula is given below Modes 1 _ Oscillator Frequency Baud Rate 32 x 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of RCAP2H and RCAP2L taken as 16 bit unsigned in teger Timer 2 as a baud rate generator is shown in Figure 5 This figure is valid only if RCLK or TCLK 1 in T2CON Note that a rollover in TH2 does n
93. bit EXEN2 in T2CON If EXEN2 0 then Timer 2 is a 16 bit timer or counter which upon overflowing sets bit TF2 the Timer 2 overflow bit which can be used to generate an interrupt If EXEN2 1 then Timer 2 still does the above but with the added feature that 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and 2 to be captured into registers RCAP2L and RCAP2H respectively RCAP2L and RCAP2H are new Special Function Registers in the 8052 In addition the transition at 2 causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt The Capture Mode is illustrated in Figure 12 In the auto reload mode there are again two options which are selected by bit EXEN2 in T2CON If 2 0 then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2L and RCAP2H which are preset by software If EXEN2 then Timer 2 still does the above but with the 3 13 added feature that 1 10 0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2 The auto reload mode is illustrated in Figure 13 The baud rate generator mode is selected by RCLK 1 and or TCLK 1 will be described in conjunc tion with the serial port SERIAL INTERFACE The serial port is full duplex meaning it can transmit and receive simultaneously It is also rece
94. bit mode Mode 1 as in the 9 bit modes except that the stop bit takes the place of the 9th data bit If SM2 is set the RI flag is set only if the received byte matches the Given or Broadcast Address and is terminated by a valid stop bit Setting the SM2 bit has no effect in Mode O The master can selectively communicate with groups of slaves by using the Given Address Addressing all slaves at once is possible with the Broadcast Address These addresses are defined for each slave by two Spe cial Function Registers SADDR and SADEN A slave s individual address is specified in SADDR SADEN is a mask byte that defines don t cares to form the Given Address These don t cares allow flexibility in the user defined protocol to address one or more slaves at a time The following is an example of how the user could define Given Addresses to selectively ad dress different slaves Slave 1 SADDR 1111 0001 SADEN 1111 1010 GIVEN 1111 0 Slave 2 SADDR 1111 0011 SADEN 1111 1001 GIVEN 1111 OXX1 8XC51FX HARDWARE DESCRIPTION Table 14 SCON Serial Port Control Register Address 98H Bit Addressable Bit SMODO 0 1 Function Reset Value 0000 0000B Svo re sw sm2 REN Ri 6 5 4 3 2 1 0 Framing Error bit This bit is set by the receiver when an invalid stop bit is detected The FE bit is not cleared by valid frames but should be cleared by software The SMODO bit
95. bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate 6 27 intel 87 510 HARDWARE DESCRIPTION Table 15 Module Modes Register eeowe oaemcaee ware roam pwwn ecere Module Function x Px fx o X iesteastrebyagesivesdpe Lx x X fiet capuo bya nogetve edgo tiger on OB x x 9 x Jesteswewawasenencn i o x Ex o x x o emmm x 3 s lt X Don t Care INTERRUPT TIMER COUNTER CCAPMn MODE REGISTER 270897 21 Figure 19 PCA 16 Bit Capture Mode The external input pins CEXO through sam In the interrupt service routine the 16 bit capture value pled for a transition When a valid transition is detected must be saved in RAM before the next capture event positive and or negative edge hardware loads the occurs subsequent capture on the same CEXn pin 16 bit value of the PCA timer CH CL into the mod will write over the first capture value in CCAPnH and ule s capture registers CCAPnH CCAPnL The re CCAPnL sulting value in the capture registers reflects the PCA timer
96. block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 0 and 2 Either SM2 0 or the received Sth data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into and the first 8 data bits go into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to O transition at the RXD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI INTERRUPTS The 8051 provides 5 interrupt sources The 8052 pro vides 6 These are shown in Figure 21 The External Interrupts INTO and can each be either level activated or transition activated depending on bits ITO and IT1 in Register TCON The flags that actually generate these interrupts are bits and in TCON When an external interrupt is generated the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt 270252 19 Figure 21 MCS 51 Interrupt Sources was transition activated If the interrupt was level acti vated then the external requesting source is what con trols the request flag rather than the on chip hardware The Time
97. but to protect the and other on on the various products chip logic Allowing light to impinge on the silicon die while the device is operating can cause logical malfunc When using the encryption array one important factor tion should be considered If a code byte has the value 3 29 intel verifying the byte will produce the encryption byte value If a large block of code is left unpro grammed a verification routine will display the encryp tion array contents For this reason all unused code bytes should be programmed with some value other than and not all of them the same value This will ensure maximum program protection Program Lock Bits Also included in the Program Lock scheme are Lock Bits which can be enabled to provide varying degrees of protection Table 5 lists the Lock Bits and their corresponding effect on the micro controller Refer to Table 6 for the Lock Bits available on the various products Erasing the EPROM also erases the Encryption Array and the Lock Bits returning the part to full functionali ty Table 5 Program Lock Bits and their Features Program Lock Bits Protection Type No program lock features enabled Code verify will still be encrypted by the encryption array if programmed MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset and further programming
98. cleared enabling the requester s DMA to pro ceed the arbiter has no way to stop the requester s DMA in progress At this point de activating HLDA will have no effect on the requester s use of the bus Only the requester itself can stop the DMA in progress and when it does it de activates both DMXRQ and HLD If the DMA is in alternate cycles mode then each time a DMA cycle is completed DMXRQ goes to 0 thus de activating HLD Once HLD has been de activated it can t be re asserted till after HLDA has been seen to go high through flip flop Q1A Thus every time the DMA is suspended to allow an instruction cycle to pro ceed the requester gives up the bus and must renew the request and receive another acknowledge before an other DMA cycle to XRAM can proceed Obviously in this case the alternate cycles mode may consist of single DMA cycles separated by any number of instruc tion cycles depending on how long it takes the request er to regain the bus A channel 1 DMA in progress will always be overrid den by a request of any kind from channel 0 If a channel 1 to XRAM is in progress and is over ridden by a channel 0 DMA which does not require the bus DMXRQ will go to 0 during the channel DMA thus de activating HLD Again the requester must re new its request for the bus and must receive a new 1 10 0 transition in before channel 1 can continue its DMA to XRAM 4 4 DMA Arbitration
99. data transfers are to be in bursts TM 1 or in alternate cycles TM 0 DONE indicates the completion of a DMA operation and flags an interrupt It is set to 1 by on chip hardware when BCRn 0 and is cleared to 0 by on chip hard ware when the interrupt is vectored to It can also be set or cleared by software 1 return 1 0 return 1 Figure 4 14 Hold Hold Acknowledge Logic as a Pseudo HLL Function intel 83C152 HARDWARE DESCRIPTION GO is the enable bit for the DMA Channel itself The DMA Channel is inactive if GO 0 PCON canen XRCLK GFIEN PDN IDL ARB enables the DMA logic to detect HLD and gener ate HL DA After it has activated HLDA the C152 will not begin a new DMA to or from External Data Mem ory as long as HLD is seen to be active This logic is disabled when ARB 0 and enabled when ARB 1 enables the logic to generate and tect HLDA before performing a DMA to or from Ex ternal Data Memory After it has activated HLD the C152 will not begin the DMA until HLDA is seen to be active This logic is disabled when REQ 0 and en abled when REQ 1 5 0 INTERRUPT STRUCTURE The 8XC152 retains all five interrupts of the 80C51BH Six new interrupts are added the 8X C152 to support its GSC and the DMA features They are as listed be low and the flags that generate them are shown in Fig ure 5 1 GSCRV GSC Receive Valid GSCR
100. depends on the value of bit SMOD1 in Special Function Register PCON If SMOD1 0 which is the value on reset the baud rate is 1 64 the oscillator frequency If SMODI 1 the baud rate is 1 32 the oscillator frequency Mode 2 Baud Rate 2 SMOD1 x The baud rates and 3 determined by the Timer 1 overflow rate by Timer 2 overflow rate or by both one for transmit and the other for receive 8 5 Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as fol lows Modes 1 and 3 Timer 1 Overflow Rate Baud Rate 2 SMOD1 x 32 Figure 28 shows how commonly used Baud Rates may be generated The Timer 1 interrupt should be disabled in this application Timer 1 can be configured for either timer or counter operation and in any of its 3 running modes In most applications it is configured for timer operation in the auto reload mode high intel 87C51GB HARDWARE DESCRIPTION nibble of TMOD 0010B In this case the baud rate 8 6 Timer 2 to Generate Baud Rates is given by the formula iat Timer 2 is selected as the baud rate generator by setting Modes 1 and3 _ gt suopi x 9398 Frequency TCLK and or RCLK in T2CON Note that the baud Baud Rate 32 x 12 x 256 TH1 rates for transmit and receive can be simultaneously different Setting R
101. devices 7 16 intel 2 8 Power Down and Idle Both of these operations function identically as in the 80C51BH Application Note 252 Designing with the 80C51BH gives an excellent explanation on the use of the reduced power consumption modes Some of the items not covered in AP 252 are the considerations that are applicable when using the GSC or DMA in con junction with the power saving modes The GSC continues to operate in Idle as long as the interrupts are enabled The interrupts need to be en abled so that the CPU can service the FIFO s In order to properly terminate a reception or transmission the C152 must not be in idle when the EOF is transmitted or received After servicing the GSC user software will need to again invoke the Idle command as the CPU does not automatically re enter the Idle mode after servicing the interrupts The GSC does not operate while in Power Down so the steps required prior to entering Power Down become more complicated The sequence when entering Power Down and the status of the I O is of major importance in preventing damage to the C152 or other components in the system Since the only way to exit Power Down is with a Reset several problem areas become very sig nificant Some of the problems that merit careful con sideration are cases where the Power Down occurs dur ing the middle of a transmission and the possibility that other stations are not or cannot enter this same mode The stat
102. emit PO and P2 SFR data External Data Memory is involved the Port 0 and Port 2 pins are used as the address data bus 83C152 HARDWARE DESCRIPTION and RD and or WR signals are generated as needed in the same manner as in the execution of a MOVX DPTR instruction 4 3 Hold Hold Acknowledge Two operating modes of Hold Hold Acknowledge log ic are available and either or neither may be invoked by software In one mode the C152 generates a Hold Request signal and awaits a Hold Acknowledge re sponse before commencing a DMA that involves exter nal RAM This is called the Requester Mode In the other mode the C152 accepts a Hold Request signal from an external device and generates a Hold Acknowledge signal in response to indicate to the re questing device that the C152 will not commence a DMA to or from external RAM while the Hold Re quest is active This is called the Arbiter mode 2 OSC PERIODS 270427 29 Figure 4 2 Transfer from Internal Memory to Internal Memory E OSC PERIODS ALE X PO INST DARLn DATA OUT AANST 2 Se were RESUME PROGRAM CYCLE EXECUTION 270427 30 Figure 4 3 Transfer from Internai Memory to External Memory 7 50 83 152 HARDWARE DESCRIPTION OSC PERIODS CLOW A n ZA A I RESUME PROGRAM 270427 31 Figure 4 4 DMA
103. flag Set by hardware when external interrupt edge detected Cleared when interrupt processed Interrupt 1 Type contro bit Set Cleared by software to specify falling level triggered external interrupts Interrupt O Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed Interrupt O Type control bit Set cleared by software to specify falling level triggered external interrupts Figure 8 TCON Timer Counter Control Register MODE 2 Mode 2 configures the Timer register as an 8 bit Coun ter TL1 with automatic reload as shown in Figure 9 Overflow from TL1 not only sets TF1 but also reloads with the contents of which is preset by soft ware The reload leaves TH1 unchanged Mode 2 operation is the same for Timer Counter 0 MODE 3 Timer 1 in Mode 3 simply holds its count The effect is the same as setting 0 3 11 Timer 0 in Mode 3 establishes TLO and THO as two separate counters The logic for Mode 3 on Timer 0 is shown in Figure 10 TLO uses the Timer 0 control bits C T GATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter With Timer O in Mode 3 an 8051 can look like it has three Timer Counters and
104. flag is set The instruction sequence ADDC A R3 DA A will first perform a standard twos complement binary addition resulting in the value OBEH 10111110 in the Accumulator The carry and auxiliary carry flags will be cleared The Decimal Adjust instruction will then alter the Accumulator to the value 24H 00100100 indicating the packed BCD digits of the decimal number 24 the low order two digits of the decimal sum of 56 67 and the carry in The carry flag will be set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum 56 67 and 1 is 124 BCD variables can be incremented or decremented by adding 01H or 99H If the Accumulator initially holds 30H representing the digits of 30 decimal then the instruction sequence ADD A 99H DA A will leave the carry set and 29H in the Accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 1 DA contents of Accumulator are BCD IF Aso gt 9 1 THEN A3 9 lt A3 9 6 AND IF A gt 9 v KO 11 THEN 7 4 lt 6 2 40 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DEC byte Function Decrement Description variable indicated is decremented by 1 An original value of 00H will underflow to OFFH No flags are affected Four operand addressing modes are allowed accumulator register direct or register indirect Note When th
105. for address matching during GSC opera tion OD5H Selects don t care bits to be used with ADRO AMSK1 OESH Selects don t care bits to be used with BAUD 94H Contains the programmable value for the baud rate generator for the GSC The baud rate will equal fosc BAUD 1 X 8 BCRLO Contains the low byte of a count down counter that determines when the DMA access for Channel 0 is complete BCRHO 0E3H Contains the high byte for count down counter for Channel 0 BCRLI 2 Same as except for DMA Channel 1 BCRHI 0F3H Same as BCRHO except for DMA Channel 1 BKOFF 0C4H An 8 bit count down timer used with the CSMA CD resolution algorithm DARLO 0C2H Contains the low byte of the destina tion address for DMA Channel 0 DARHO 0C3H Contains the high byte of the desti nation address for DMA Channel 0 DARL 0D2H Same as DARLO except for DMA Channel 1 DARHI 0D3H Same as DARHO except for DMA Channel 1 DCONO 92H Contains the Destination Address Space bit DAS Increment Destination Address bit 7 5 83C152 HARDWARE DESCRIPTION IDA Source Address Space bit SAS Increment Source Address bit ISA DMA Channel Mode bit DM Transfer Mode bit TM Done bit DONE and the GO bit GO DCONO is used to control DMA Channel 0 DCONI 93H Same as DCONO except this is for Channel 1 GMOD
106. function All five modules plus the timer overflow share one interrupt vector The timer counter and compare capture modules Share Port 1 pins for external I O These pins are listed below If the port pin is not used for the PCA it can Still be used for standard I O PCA Component External i O Pin 16 bit Counter 16 bit Module 0 P1 2 ECI P1 3 CEXO 1 4 CEX1 P1 5 CEX2 P1 6 P1 7 CEX4 16 bit Module 1 16 bit Module 2 16 bit Module 3 16 bit Module 4 7 1 PCA Timer Counter The has a free running 16 bit timer counter con sisting of registers CH and CL the high and low bytes of the count value These two registers can be read or written to at any time Reading the PCA timer as a full 16 bit value simultaneously requires using one of the modules in the capture mode and toggling a port pin in software TO PCA MODULES 0 4 CL INTERRUPT ENABLE Figure 18 PCA Timer Counter 6 24 intel 87C51GB HARDWARE DESCRIPTION The clock input can be selected from the following four modes Oscillator frequency 12 The PCA timer increments once per machine cycle With a 16 MHz crystal the timer increments every 750 ns Oscillator frequency 4 The PCA timer increments three times per machine cycle With 16 MHz crystal the timer increments External input The PCA timer increments when a 1 to O transition is detected on the ECI pin P1 2 The ma
107. if SM2 1 then Rt will not be activated if a valid stop bit was not received In Mode 0 SM2 should be 0 enables serial Set by software to enable reception Clear by software to disable reception TB8 istheSth data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired in Modes 2 and 3 is the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used is transmit interrupt fiag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software is receive interrupt flag Set by hardware at the end of the Bth bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see 5 2 Must be cleared by software Figure 14 SCON Serial Port Control Register Baud Rates The baud rate in Mode 0 is fixed Mode 0 Baud Rate Oscillator Frequency The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON If SMOD 0 which is the value on reset the baud rate 1 4 the oscillator frequency If SMOD 1 the baud rate is the oscillator frequency 3 15 2SMOD Mode 2 Baud Rate X Oscillator Frequency In tbe 8051 the baud rates in Modes 1 and 3 are deter mined by the Timer 1 overflow rate In the 8052 these baud r
108. in its current state slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct addressing is allowed for the source operand Example Set the carry flag if and only if P1 0 1 ACC 7 1 and 0 MOV 1 0 LOAD CARRY WITH INPUT PIN STATE ANL 7 AND CARRY WITH ACCUM 7 ANL C OV AND WITH INVERSE OF OVERFLOW FLAG ANL Bytes 2 Cycles 2 Encoding bit address Operation ANL C A bit ANL C bit Bytes Cycles 2 Encoding Operation ANL lt Q A 1 bit intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CJNE lt dest byte gt lt src byte gt rel Function Description Example CJNE A direct rel Bytes Cycles Encoding Operation Compare and Jump if Not Equal CJNE compares the magnitudes of the first two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction The carry flag is set if the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt otherwise the carry is cleared Neither operand is affected The first two operands allow four addressing mode co
109. interrupt vectors two ex ternal interrupts INTO and three timer inter rupts Timers 0 1 and 2 and the serial port interrupt These interrupts are all shown in Figure 6 Timer 2 Interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and that bit will have to be cleared in software The Timer 0 and Timer 1 flags and are set at S5P2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows Interrupt Priority Structure A second Interrupt Priority register IPH has been added increasing the number of priority levels to four Table 6 shows this second register The added register becomes the MSB of the priority select bits and the existing IP register acts as the LSB This scheme main tains compatibility with the rest of the MCS 51 family Table 7 shows the bit values and priority levels associ ated with each combination Table 6 IPH Interrupt Priority High Register IPH Address 7 Bit Symbol Reset Value X000 0000 7 6 5 4 3 2 1 0 Function Not Implemented reserved for future use PPCH PT2H PSH
110. is frozen Symbol SMOD1 SMODO PD IDL NOTE 87C51GB HARDWARE DESCRIPTION Table 26 PCON Power Control Register Address 87H Reset Value 00 00008 Not Bit Addressable swop swopo Por Gro PD ot 7 6 5 4 3 2 1 0 Bit Function Double Baud rate bit When set to a 1 and Timer 1 is used to generate baud rates and the Serial Port is used in modes 1 2 or 3 When set Read Write accesses to SCON 7 to the FE bit When clear Read Write accesses to SCON 7 are to the SMO bit Not implemented reserved for future use Power Off Flag Set by hardware on the rising edge of Vcc Set or cleared by software This flag allows detection of a power failure caused reset must remain above 3V to retain this bit General purpose flag bit General purpose flag bit Power Down bit Setting this bit activates Power Down operation Idle mode bit Setting this bit activates idle modes operation If 1s are written to PD and IDL at the same time PD takes precedence User software should not write 1s to unimplemented bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate Figure 36 Idle and Power Down Hardware 6 50 ntel 14 1 Idle Mode An instruction that sets the IDL bit causes that to
111. is possible to examine some other registers or conditions such as the current byte count to determine when to stop the DMA transfers to TFIFO but this is not recommended as a way to service the DMA and GSC when transmit ting because frequent reading of the DMA registers will cause the effective DMA transfer rate to slow down When using the DMA channels initialization of the GSC would be exactly the same as normal except that 1 this informs the GSC that the DMA channels are going to be used to service the GSC Although only TSTAT is written to both the receiver and transmitter use this same DMA bit The interrupts EGSTE 1 5 GSC transmit error EGSTV IEN1 3 GSC transmit valid EGSRE IEN1 1 GSC receive error and EGSRV IENI 0 GSC receive valid need to be enabled The DMA inter rupts are normally not used when servicing the GSC with the DMA channels To ensure that the DMA in terrupts are not responded to is a function of the user software and should be checked by the software to make sure they are not enabled Priority for these inter rupts can also be set at this time Whether to use high or low priority needs to be decided by the user When responding to the GSC interrupts if a buffer is being used to store the GSC information then the DMA reg isters used for the buffer will probably need updating After this initialization all that needs to be done when the GSC is actually going to b
112. is still low the GO bit is cleared the DONE bit is set and the DMA ceases If the exter nal interrupt is enabled it will be serviced If the interrupt pin is pulled up before BCRn reaches 0000H then the DMA ceases but the GO bit is still 1 and the DONE bit is still 0 An external interrupt is not generated in this case since in level activated mode pulling the pin to a logical 1 clears the interrupt flag If the interrupt pin is then pulled low again DMA trans fers will continue from where they were previously stopped The timing for the DMA Cycle in the transition acti vated mode or for the first DMA Cycle in the level ac tivated mode is as follows If the 1 to O transition is intel detected before the final machine cycle of the instruc tion in progress then the DMA commences as soon as the instruction in progress is completed Otherwise one more instruction will be executed before the DMA starts No instruction is executed during any DMA Cy cle 4 2 Timing Diagrams Timing diagrams for single byte DMA transfers are Shown in Figures 4 2 through 4 5 for four kinds of DMA Cycles internal memory to internal memory in ternal memory to external memory external memory to internal memory and external memory to external memory In each case we assume the C152 is executing out of external program memory If the C152 is execut ing out of internal program memory then PSEN is in active and the Port 0 and Port 2 pins
113. mit valid interrupt IPN1 4 1 Assigns the priority of DMA done interrupt for Channel 1 IPN1 5 PGSTE Assigns the priority of GSC trans mit error interrupt ISA Increment Source Address see DCONO LNI Line Idle see TSTAT LSC Local Serial Channel The asynchronous serial port found on all MCS 51 devices Uses start stop bits and can transfer only 1 byte at a time MO One of two GSC mode bits see TMOD 1 One of two GSC mode bits see TMOD MYSLOT OFSH 7 6 5 4 3 2 1 0 Dcu ocr sas saa sas saz s sao 7 67 Determines which type of Jam is used which backoff algorithm is used and the DCR slot address for the GSC MYSLOT 0 1 2 3 4 5 0 1 2 3 4 5 These bits deter mine which slot address is assigned to the C152 when using deterministic backoff during CSMA CD opera tions on the GSC Maximum slots available is 63 An address of 00H prevents that station from participating in the backoff process MYSLOT 6 DCR Determines which collision reso lution algorithm is used If set to a 1 then the determi nistic backoff is used If cleared then a random slot assignment is used MYSLOT 7 DCJ Determines the type of Jam used during CSMA CD operation when a collision occurs If set to a 1 then a low D C level is used as the jam signal If cleared then CRC is used as the jam signal The jam is applied for a length of time equal to the CRC length NOACK No Acknowled
114. must be set to enable access to the FE bit Serial Port Mode Bit 0 SMODO must 0 to access bit SMO Serial Port Mode Bit 1 SMO SM1 0 0 0 1 1 0 1 1 Mode 0 1 2 3 Description shift register 8 bit UART 9 bit UART 9 bit UART Baud Rate Fosc 12 variable Fosc 64 or Fosc 32 variable Enables the Automatic Address Recognition feature in Modes 2 or 3 If SM2 1 then RI will not be set unless the received 9th data bit RB8 is 1 indicating an address and the received byte is a Given or Broadcast Address In Mode 1 if SM2 1 then RI will not be activated unless a valid stop bit was received and the received byte is a Given or Broadcast Address Mode 0 SM2 should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The Sth data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In modes 2 and 3 the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see 5 2 Must be cleared b
115. new transmis sion begins by setting TEN and loading TFIFO The minimum amount of time available to initiate a retrans mission would be one interframe space period after the line is sensed as being idle As the number of stations approach 256 the probability of a successful transmission decreases rapidly If there 7 43 more than 256 stations involved in the collision there would be no resolution since at least two of the stations will always have the same backoff interval se lected All the stations monitor the link as long as that station is active even if not attempting to transmit This is to ensure that each station always defers the minimum amount of time before attempting a transmission and so that addresses are recognized However the collision detect circuitry operates slightly differently In normal back off mode a transmitting station always monitors the link while transmitting If a collision is detected one or more of the transmitting stations apply the jam signal and all transmitting stations enter the back off algorithm The receiving stations also con stantly monitor for a collision but do not take part in the resolution phase This allows a station to try to transmit in the middle of a resolution period This in turn may or may not cause another collision If the new station trying to transmit on the link does so during an unused slot time then there will probably not be a colli sion If trying to transmi
116. no CRC Error neither CRCE nor AE will get set If there is a CRC Error and no Alignment Error the CRCE bit will get set but not the AE bit If there is both CRC Error and an Align ment Error the AE bit will get set but not the CRCE bit Thus in CSMA CD mode the and AE bits are mutually exclusive The Receive Abort flag gets set if an incom ing frame was interrupted after received data had al ready passed to the Receive FIFO In SDLC mode this can happen if a line idle condition is detected before an EOF flag is In CSMA CD mode it can happen if there is a collision In either case the CPU will have to re initialize whatever pointers and counters it might have been using The Overrun Error flag OVR gets set if the GSC Re ceiver is ready to push a newly received byte onto the Receive FIFO but the FIFO is full Up to 7 dribble bits can be received after the EOF without causing an error condition ntel 6 0 GLOSSARY ADRO 1 2 3 95H 0A5H OBSH 5 Address Match Registers 0 1 2 3 The contents of these SFRs are compared against the address bits from the serial data on the GSC If the address matches the SFR then the C152 accepts that frame If in 8 bit addressing mode a match with any of the four registers will trigger acceptance In 16 bit addressing mode a match with ADR1 ADRO or ADR3 ADR2 will be accepted Ad dress length is determined by GMOD AL AE Alignment Error see
117. occurrence of 5 consecu tive 1s and the receiver automatically removes a zero after receiving 5 consecutive 1s All the necessary steps required for implementing bit stuffing and stripping are incorporated into the GSC hardware This makes the operation transparent to the user About tbe only time this operation becomes apparent to the user is if the actual data on the transmission medium is being moni tored by a device that is not aware of the automatic insertion of Os The bit stuffing stripping guarantees that there will be at least one transition every 6 bit times while the line is active 83 152 HARDWARE DESCRIPTION 3 3 5 SENDING ABORT CHARACTER An abort character is one of the exceptions to the rule that disallows more than 5 consecutive 1s The abort character consists of any occurrence of seven or more consecutive ones The simplest way for the C152 to send an abort character is to clear the TEN bit This causes the output to be disabled which in turn forces it to a constant high state The delay necessary to insure that the link is high for seven bit times is a task that needs to be handled by user software Other methods of sending an abort character are using the IFS register or using the Raw Transmit mode Using IFS still entails clearing the TEN bit but TEN can be immediately re enabled The next message will not begin until the IFS expires The IFS begins timing out as soon as DEN goes high which identifies the end o
118. of operation VCC can be 51 devices will present a substantial barrier against reduced to as low as 2V Care must be taken however gal readout of protected software to ensure that VCC is not reduced before the Power Down mode is invoked and that VCC is restored to its normal operating level before Power Down mode 15 One Lock Bit Scheme on 8751H terminated The reset that terminates Power Down also frees the oscillator The reset should not be activated The 8751H contams s lock bit which once pro before VCC is restored to its normal operating level grammed denies electrical access by any external and must be held active long enough to allow the oscil means to the on chip Program Memory The effect of lator to restart and stabilize normally less than 10 this lock bit is that while it is programmed the internal msec Program Memory can not be read out the device can not further programmed and it not execute ternal Program Memory Erasing the EPROM array deactivates the lock bit and restores the device s full EPROM VERSIONS functionality It can then be re programmed The EPROM versions of these devices are listed in Ta ble 4 The 8751H programs at VPP 21V using one The procedure for programming the lock bit is detailed 50 msec PROG pulse per byte programmed This the 8751H data sheet sults in a total programming time 4K bytes of approx imately 4 minutes
119. of the CRC is a pass fail flag The pass fail flag only operates during reception CRC is considered as passing when the the CRC gener ator has 11000111 00000100 11011010 01111011B as a remainder after all of the data including the CRC checksum from the transmitting station has been cy cled through the CRC generator The preamble BOF and EOF are not included as part of the CRC algo rithm An interrupt is available that will interrupt the CPU if the CRC of the receiver is invalid The user can enable the CRC to be passed to the CPU by placing the receiver in the raw receive mode This method of calculating the CRC is compatible with IEEE 802 3 EOF The End Of Frame indicates when the transmis sion is completed The end flag in CSMA CD consists of an idle condition An idle condition is assumed when there is no transitions and the link remains high for 2 or more bit times 83 152 HARDWARE DESCRIPTION PL PERL PU PERL eto 270427 8 Figure 3 2 CRC Generator 3 2 3 INTERFRAME SPACE The interframe space is the amount of time that trans mission is delayed after the link is sensed as being idle and is used to separate transmitted frames In alternate backoff mode the interframe space may also be includ ed in the determination of when retransmissions may actually begin The C152 allows programmabie inter frame spaces of even numbers of bit times from 2 to 256 The hardware enforces the interframe space in SDLC mo
120. pin is sampled during State 5 Phase 2 of every machine cycle The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin that is for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin While the RST pin is high ALE and PSEN are weakly pulled high After RST is pulled low it will take 1 to 2 machine cycles for ALE and PSEN to start clocking For this reason other devices can not be synchronized to the internal timings of the 8051 Driving the ALE and PSEN pins to O while reset is active could cause the device to go into an indetermi nate state The internal reset algorithm writes Os to all the SFRs except the port latches the Stack Pointer and SBUF The port latches are initialized to FFH the Stack Pointer to 07H and SBUF is indeterminate Table 3 lists the SFRs and their reset values The internal RAM is not affected by reset On power up the RAM content is indeterminate Y Y Y Y Y Y M jon jocos j LI 5 11 OSC PERIODS 19 OSC PERIODS 270252 33 Figure 25 Reset Timing 3 26 intel Table 3 Reset Values of the SFRs U B _ OH __ Ek ______ mM _ PO P3 FFH TOD ___ OOH TH 00H TL1 2 8052 __7 2 8052
121. register Table 14 selects the input trigger positive and or negative transition for module n Refer to Fig ure 19 Table 15 shows the combinations of bits in the CCAPMn register that are valid and have a defined function Invalid combinations will produce undefined results Table 14 CCAPMn PCA Modules Compare Capture Registers CCAPMn Address CCAPMO n 0 4 CCAPM1 ODBH CCAPM2 ODCH ODDH CCAPM4 ODEH Not Bit Addressable Bit Symbol Function Not implemented reserved for future use Reset Value X000 00008 Toan ECCFn 7 6 5 4 3 2 1 0 ECOMn Enable Comparator ECOMn 1 enables the comparator function CAPPn Capture Positive CAPPn 1 enables positive edge capture CAPNn Capture Negative CAPNn 1 enables negative edge capture MATn Match When 1 match of the counter with this module s compare capture register causes the CCFn bit in CCON to be set flagging an interrupt TOGn register causes the CEXn pin to toggle PWMn modulated output Toggle When TOGn 1 a match of the counter with this module s compare capture Pulse Width Modulation Mode PWMn 1 enables the CEXn pin to be used as a pulse width ECCFn Enable CCF interrupt Enables compare capture flag CCFn in the CCON register to generate an interrupt NOTE User software should not write 1s to reserved bits These
122. request of higher priority level is serviced If requests of the same priority level are received simultaneously an internal polling se quence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence shown in Table 24 intel 87C51GB HARDWARE DESCRIPTION Table 23 Interrupt Priority Registers Address OB8H Reset Value X000 00008 Bit Addressable _ ec 2 Ps Pro Pxo Address OB6H Reset Value 0000 0000B Not Bit Addressable PAD 6 Px5 Px3 2 PC1 PSEP Address 0B7H Reset Value 000 00008 Not Bit Addressable pron Address 5 Reset Value 0000 00008 Not Bit Addressable PADH PXaH 2 0 Lowest 0 1 1 Highest Symbol Function Not Implemented reserved for future use PPC PPCH PCA interrupt priority bits PT2 PT2H Timer 2 interrupt priority bits PS PSH Serial Port interrupt priority bits PT1 PT1H Timer 1 interrupt priority bits PX1 PX1H External interrupt 1 interrupt priority bits PTO PTOH Timer 0 interrupt priority bits PXO PXOH External interrupt 0 interrupt priority bits PAD PADH A D converter interrupt priority bits PX6 PX6H External interrupt 6 interrupt priority bits PX5 PX5H External interrupt 5 interrupt priority bits
123. same addresses in SFR space However enhance ments to the 8051 have additional SFRs that are not present in the 8051 nor perhaps in other proliferations of the family REGISTER MAPPED PORTS ADDRESSES THAT END OH OR 8H ARE ALSO BIT ADDRESSABLE PORT PINS ACCUMULATOR 5 270251 9 Figure 9 SFR Space Sixteen addresses in SFR space are both byte and bit addressable The bit addressable SFRs are those whose address ends in 0008 The bit addresses in this area 80H through FFH THE MCS 51 INSTRUCTION SET All members of the MCS 51 family execute the same instruction set The MCS 51 instruction set is opti mized for 8 bit control applications It provides a vari ety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data struc tures The instruction set provides extensive support for one bit variables as a separate data type allowing direct bit manipulation in control and logic systems that re quire Boolean processing An overview of the MCS 51 instruction set is presented below with a brief description of how certain instruc tions might be used References to the assembler in this discussion are to Intel s MCS 51 Macro Assembler ASMS1 More detailed information on the instruction can be found in the MCS 5 Macro Assembler Us er s Guide Order No 9800937 for ISIS Systems Order No 122752 for DOS Systems Program Status Word T
124. separate address spaces for Program and Data Memory as shown in Figure 2 The logical separation of Program and Data Memory allows the Data Memory to be accessed by 8 bit addresses which can be more quickly stored and manipulated by an 8 bit CPU Nevertheless 16 bit Data Memory ad dresses can also be generated through the DPTR regis ter Program Memory can only be read not written to There can be up to 64K bytes of Program Memory In the ROM and EPROM versions of these devices the lowest 4K 8K or 16K bytes of Program Memory are provided on chip Refer to Table 1 for the amount of on chip ROM or EPROM on each device In the ROMliess versions all Program Memory is external The read strobe for external Program Memory is the signal PSEN Program Store Enable intel MCS 51 ARCHITECTURAL OVERVIEW Data Memory occupies a separate address space from Program Memory Up to 64K bytes of external RAM can be addressed in the external Data Memory space The CPU generates read and write signals RD and WR as needed during external Data Memory accesses External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program Data memory Program Memory Figure 3 shows a map of the lower part of the Program Memory After reset the CPU begins execution from location 0000H As show
125. the byte being written or read Port 2 outputs the high byte of the externa memory address when the address is 16 bits wide Otherwise the Port 2 pins continue to emit the P2 SFR content All the Port 3 pins and in the 8052 two Port 1 pins are multifunctional They are not only port pins but also serve the functions of various special features as listed on the following page intel HARDWARE DESCRIPTION OF THE 8051 8052 80C51 Port Pin Alternate Function 1 0 2 Timer Counter 2 external input P1 1 T2EX Timer Counter 2 Capture Reload trigger P3 0 RXD serial input port P3 1 TXD serial output port P3 2 INTO external interrupt P3 3 INT1 external interrupt P3 4 TO Timer Counter 0 external input P3 5 T1 Timer Counter 1 external input P3 6 WR external Data Memory write strobe P3 7 RD externa Data Memory read strobe P1 0 and P1 1 serve these alternate functions only on the 8052 The alternate functions can only be activated if the cor responding bit latch in the port SFR contains a 1 Oth erwise the port pin is stuck at 0 1 0 Configurations Figure 4 shows a functional diagram of a typical bit latch and I O buffer in each of the four ports The bit latch one bit in the port s SFR is represented as a Type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal b
126. the CCAPMn mode register By setting or clearing the pin in software the user can select whether the CEXn pin will change from a logical O to a logical 1 or vice versa The user also has the option of flagging an interrupt when a match event occurs by setting the ECCFn bit See Figure 21 The HSO mode is more accurate than toggling port pins in software because the toggle occurs before branching to an interrupt That is interrupt latency will not effect the accuracy of the output In fact the interrupt is optional Only if the user wants to change the time for the next toggle is it necessary to update the compare registers Otherwise the next toggle will occur when the PCA timer rolls over and rnatches the last compare value Without any CPU intervention the fastest waveform the can generate with the HSO mode is a 30 5 Hz signal at 16 MHz 7 6 Watchdog Timer Mode A Watchdog Timer is a circuit that automatically in vokes a reset unless the system being watched sends regular hold off signals to the Watchdog These circuits are used in applications that are subject to electrical noise power glitches electrostatic discharges etc or where high reliability is required The Watchdog Timer function is only available on PCA Module 4 If a Watchdog Timer is not needed Module 4 can still be used in other modes As a Watchdog timer every time the count in the PCA timer matches the value stored in module 4 s compare registers
127. the baud rate The baud rate in Mode 3 is vari able you can use Timer 1 and or Timer 2 to generate baud rates See Figure 27 00 o1 02 05 04 05 oe 07 06 Data Byte Stort Bit Stop Bit Ninth Doto Bit 270897 29 Figure 27 3 Data Frame 8 1 Framing Error Detection Framing Error Detection allows the serial port to check for valid stop bits in modes 1 2 or 3 missing stop bit can be caused for example by noise on the serial lines or transmission by two CPUs simultaneously If a stop bit is missing a Framing Error bit FE is set The FE bit can be checked in software after each recep tion to detect communication errors Once set the FE bit must be cleared in software A valid stop bit will not clear FE The FE bit is located in SCON and shares the same bit address as SMO Control bit SMODO in the reg ister determines whether the SMO or FE bit is accessed If SMODO 0 then accesses to 7 to SMO If SMODO 1 then accesses to SCON 7 are to FE 8 2 Multiprocessor Communications Modes 2 and 3 provide a 9 bit mode to facilitate multi processor communication The 9th bit allows the con troller to distinguish between address and data bytes The 9th bit is set to 1 for address and set to 0 for data bytes When receiving the 9th bit goes into RB8 in SCON When transmitting the ninth bit TB8 is set or cleared in software
128. the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle Timer 0 and Timer 1 have four operating modes Mode 0 13 bit timer Mode 1 16 bit timer Mode 2 8 bit auto reload timer Mode 3 Timer 0 as two separate 8 bit timers Also its possible to use Timer 1 to generate baud rates Timer 2 has three modes of operation Timer 2 Capture Timer 2 Auto Reload up or down counting and Timer 2 as a Baud Rate Generator 5 1 Timer 0 and Timer 1 The Timer Counter function is selected by control bits Tx in TMOD Table 4 These two Timer Coun ters have four operating modes which are selected by bit pairs M1x MOx also in TMOD Mode 0 Mode 1 and Mode 2 are the same for both Timer Counters Mode 3 operation is different for the two timers intel 87C51GB HARDWARE DESCRIPTION Table 4 TMOD Timer Counter Mode Control Register Address 89H Reset Value 0000 0000B Not Bit Addressable TIMER 1 TIMER 0 GATE GATE 7 6 5 4 3 2 1 0 Bit Function Gating control when set Timer Counter 0 or 1 is enabled only while INTO or INT 1 pin is high and TRO or TR1 control pin is set When cleared Timer 0 or 1 is enabled whenever TRO or TR1 control bit is set Timer or Counter Selector Clear for Timer operation input from internal system clock Set for Counter operation input from TO or T1 inp
129. the use of the DMA channels with the GSC will be covered The DMA channels can be configured by user software so that the GSC data transfers are serviced by the DMA controller Since there are two DMA channels one channel can be used to service the receiver and one channel can be used to service the transmitter In using the DMA channels the CPU is relieved of much of the time required to do the basic servicing of the GSC buff ers The types of servicing that the DMA channels can provide are loading of the transmit FIFO removing data from the receive FIFO notification of the CPU when the transmission or reception has ended and re Sponse to certain error conditions When using the ntel 83C152 HARDWARE DESCRIPTION DMA channels the source or destination of the data intended for serial transmission can be internal data memory external data memory or any of the SFRs The only tasks required after initialization of the DMA and GSC registers are enabling the proper interrupts and informing the DMA controller when to start After the DMA channels are started all that is required of the CPU is to respond to error conditions or wait until the end of transmission Initialization of the DMA channels requires setting up the control source and destination address registers On the DMA channel servicing the receiver the con trol register needs to be loaded as follows DCONn 2 0 this sets the transfer mode so that response is
130. timer operation C__T2 0 The Timer opera tion is different for Timer 2 when it s being used as a baud rate generator Normally as a timer it increments every machine cycle 1 12 the oscillator frequency As a baud rate generator however it increments every state time 3 the oscillator frequency The baud rate formula is given below Modes 1 and3 _ Oscillator Frequency Baud Rate 32 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of RCAP2H and RCAP2L taken as a 16 bit unsigned in teger Timer 2 as a baud rate generator is valid only if RCLK and or TCLK 1 in T2CON Note that a rollover in does not set TF2 and will not generate an inter rupt Therefore the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Note too that if 2 is set a 1 10 0 tran sition on the 2 pin will set EXF2 but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate generator T2EX can be used as an extra external interrupt if desired SEPE SEPREN CLKPOL Table 18 lists commonly used baud rates and how they can be obtained from Timer 2 It should be noted that when Timer 2 is running TR2 1 in timer function in the baud rate generator mode one should not try to read or write TH2 or TL2 Under these conditions the Timer is being incremented every state time and the results of a read or
131. to 2 MBPS with on chip clock recovery and 2 4 MBPS using the external clock options In applications using the serial channel the GSC implements the Data Link Layer and Physical Link Layer as described in the ISO reference model for open systems interconnection The GSC is designed to meet the requirements of a wide range of serial communications applications and is optimized to implement Carrier Sense Multi Access with Collision Detection CSMA CD and Synchro nous Data Link Control SDLC protocols The GSC architecture is also designed to provide flexibility in de fining non standard protocols This provides the ability to retrofit new products into older serial technologies as well as the development of proprietary interconnect schemes for serial backplane environments The versatility of the GSC is demonstrated by the wide range of choices available to the user The various modes of operation are summarized in Table 3 1 In subsequent sections each available choice of operation will be explained in detail In using Table 3 1 the parameters listed vertically on the left hand side represent an option that is selected X The parameters listed horizontally along the top of the table are all the parameters that could theoreti cally be selected Y The symbol at the junction of both X and Y determines the applicability of the option Y Note that not all combinations are backwards compati ble For example Manchester encodin
132. transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse oc curs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift regis ter Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeroes This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after write to SBUF Reception is initiated by a detected 1 10 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is imme diately reset and 1FFH is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not O the receive circuits are reset and the unit goes back to looking for another 1 to O transition If the start bit proves valid it is shifted into the input shift r
133. until the interframe space expires A requirement for the inter frame space timer to begin is that the receiver be in an idle state This makes it possible for the GSC to be in some other mode than the user intends for a significant amount of time after reset To prevent unwanted GSC errors from occurring the user should not enable the GSC or the GSC interrupts for 170 machine cycles 256 8 12 after LNI bit is set 3 2 CSMA CD Operation 3 2 1 CSMA CD OVERVIEW CSMA CD operates by sensing the transmission line for a carrier which indicates link activity At the end of link activity a station must wait a period of time called the deference period before transmission may begin The deference period is also known as the interframe space The interframe space is explained in Section 3 2 3 With this type of operation there is always the possibil ity of a collision occurring after the deference period due to line delays If a collision is detected after trans mission is started a jamming mechanism is used to en sure that all stations monitoring the line are aware of the collision resolution algorithm is then executed to 7 20 resolve the contention There are three different modes of collision resolution made available to the user on the C152 Re transmission is attempted when a resolution algorithm indicates that a station s opportunity has ar rived Normally in CSMA CD re transmission slot assign ments are intend
134. will need to be cleared If DMA servicing is being used the point ers must also be reinitialized It should be noted that a collision should never occur after the BOF flag in a well designed system since the system slot time will likely be less than the preamble length The occurrence of such a situation is normally due to a station on the link that is not adhering to proper CSMA CD protocol is not using the same timings as the rest of the network A collision occurring during the preamble or BOF flag is the normal type of collision that is expected When this type of collision occurs the GSC automatically handles the retransmission attempts for as many as eight tries If on the eighth attempt a collision occurs intel 83C152 HARDWARE DESCRIPTION the transmitter is disabled although the jam and back off are performed If enabled the CPU is then inter rupted The user software should then determine what action to take The possibilities range from just report ing the error and aborting transmission to reinitializing the serial channel registers and attempt retransmission If less than eight attempts are desired TCDCNT can be loaded with some value which will reduce the number of collisions possible before TCDCNT overflows The value loaded should consist of all Is as the least signifi cant bits e g 7 solid block of 15 is sug gested because TCDCNT is used as a mask when gen erating the random slot n
135. with an address that depends on the source of the interrupt being vectored to as shown be low Vector Source Address IEO 0003H 000BH IE1 0013 TF1 001BH RI TI 0023H TF2 EXF2 0028 Execution proceeds from that location until the RETI instruction is encountered The RETI instruction in forms the processor that this interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted program continues from where it left off Note that a simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress 3 25 External Interrupts The external sources can be programmed to be level ac tivated or transition activated by setting or clearing bit or ITO in Register TCON If ITx 0 external interrupt x is triggered by a detected low at the INTx pin If ITx 1 external interrupt x is edge triggered In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx then requests the interrupt Since the external interrupt pins are sampled once each machine cycle an input high or low should hold for at least 12 oscillator periods to ensure sampling If the external interrupt is transition activated the external source has t
136. 0 CPS1 50 Selected Input Internal clock 12 Internal clock Fosc 4 Timer O overflow External clock at ECI P1 2 pin max rate 8 ECF PCA Enable Counter Overflow interrupt ECF 1 enables CF bit in CCON to generate an interrupt 0 disables that function of CF NOTE User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate Fosc oscillator frequency 6 25 87C51GB HARDWARE DESCRIPTION Table 13 CCON PCA Counter Control Register Address 0D8H Bit Addressable Bit Function CF Reset Value 00X0 00008 on core 7 6 5 4 3 2 1 0 Counter Overflow flag Set hardware when the counter rolis over CF flags interrupt if bit ECF in CMOD is set CF may be set by either hardware or software but can only be cleared by software CR by software to turn the PCA counter off CCF4 cleared by software CCF3 cleared by software CCF2 cleared by software CCF1 cleared by software CCF0 cleared by software NOTE PCA Counter Run control bit Set by software to turn the PCA counter on Must be cleared Not implemented reserved for future use Module 4 interrupt flag S
137. 0 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off Timer 0 overflow Flag Set by hardware on Timer Counter 0 overflow Cleared by hardware when processor vectors to interrupt routine TRO IE1 Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off interrupt 1 flag Set by hardware when external interrupt 1 edge is detected transmitted or level activated Cleared when interrupt processed only if transition activated IT1 IEO Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupt 1 Interrupt 0 flag Set by hardware when external interrupt 0 edge is detected transmitted or level activated Cleared when interrupt processed only if transition activated ITO triggered external interrupt O CONTROL interrupt 0 Type control bit Set cleared by software to specify falling edge low level INTERRUPT OVERFLOW Figure 9 Timer Counter 0 1 in Mode 1 16 Bit Counter MODE 3 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate counters The logic for Mode 3 on Timer O is shown in Figure 11 TLO uses the Timer 0 control bits C T TRO INTO and THO is locked into 5 14 a timer function counting machine cycles and takes over the use of TR1 and from Timer 1 Thus THO now cont
138. 0 and is used to re enable trans mission At that time transmission can proceed subject of course to IFS enforcement unless shifting a 1 into TCDCNT from the right caused a 1 to shift out from the MSB of TCDCNT or the collision was detected after TFIFO had been ac cessed by the transmit hardware 83C152 HARDWARE DESCRIPTION MYSLOT 270427 38 Figure 3 5 Backoff Timer Logic In either of these cases the transmitter is disabled TEN 0 and the Transmit Error TCDT is set The automatic restart is canceled Where the Normal and Alternate Random backoff al gorithms differ is that in Normal Random backoff the BKOFF timer starts counting down as soon as a line idle condition is detected whereas in Alternate Ran dom backoff the BKOFF timer doesn t start counting down till the IFS expires The Alternate Random mode was designed for net works in which the slot time is less than the IFS the randomly assigned backoff time for a given transmitter happens to be 0 then it is free to transmit as soon as the IFS ends If the slot time is shorter than the IFS Nor mal Random mode would nearly guarantee that if there s a first collision there will be a second collision The situation is avoided in Alternate Random mode since the BKOFF countdown doesn t start till the IFS is over The unit of count to the BKOFF timer is the slot time The slot time is measured in bit times and is deter mine
139. 0022050 Lo 3 A oo TE NI Raw ___1 1 1 sore ________ elo 7 18 intel 83C152 HARDWARE DESCRIPTION Table 3 1 Continued AVAILABLE OPTIONS gt SELECTED FUNCTION DATA ENCODING MANCHESTER NAZI NRZ FLAGS 01111110 11 IDLE 16 BIT CCITT 32 BIT AUTODIN II DUPLEX HALF FULL ACKNOWLEDGEMENTINONE O o o o o HARDWARE USER DEFINED Ernu ae a 3 6 C S 2 4 R X N S D N AVAILABLE B B M L M I OPTIO T T R R NORMALLY PREFERRED N N X N A A A D L L ADDRESS RECOGNITION NONE 8 BIT 16 BIT COLLISION RESOLUTION NORMAL ALTERNATE DETERMINISTIC PREAMBLE NONE 8 BIT 32 BIT 64 BIT JAM D C CRC CLOCKING EXTERNAL INTERNAL CONTROL CPU DMA wem bb DEDE E rawtransmT ____ 1 2 PN 1 1 o sw _____ suc _____ 7 19 83 152 HARDWARE DESCRIPTION intel Note 1 Programmable
140. 0B3H Same as SARHI but for DMA Chan nel 1 SLOTTM Determines the length of the slot time in CSMA CD TCDCNT 0D4H Contains the number of collisions in the current frame if using CSMA CD GSC N N N N N N O N N N N N N N N N N N N N N N O N O N N N N N N N N O O N 83C152 HARDWARE DESCRIPTION ADR1 ADR2 ADR3 AMSKO AMSK1 B BAUD BCRLO BCRHO BCRL1 BCRH1 BKOFF DARLO DARHO DARL1 DARH1 DCONO DCON1 DPH DPL GMOD IEN1 IFS IP IPN1 MYSLOT PO P1 P2 P3 P4 P5 P6 PCON PRBS PSW RFIFO RSTAT SARLO SARHO SARL1 SARH1 SBUF SCON SLOTTM SP TCDCNT TCON TFIFO THO TH1 TLO TL1 TMOD TSTAT 7 6 ACCUMULATOR GSC MATCH ADDRESS 0 GSC MATCH ADDRESS 1 GSC MATCH ADDRESS 2 GSC MATCH ADDRESS 3 GSC ADDRESS MASK 0 GSC ADDRESS MASK 1 B REGISTER GSC BAUD RATE DMA BYTE COUNT 0 LOW DMA BYTE COUNT 0 HIGH DMA BYTE COUNT 1 LOW DMA BYTE COUNT 1 HIGH GSC BACKOFF TIMER DMA DESTINATION ADDR 0 LOW DMA DESTINATION ADDR 0 HIGH DMA DESTINATION ADDR 1 LOW DMA DESTINATION ADDR 1 HIGH CONTROL 0 CONTROL 1 DATA HIGH DATA POINTER LOW GSC MODE INTERRUPT ENABLE REGISTER 0 INTERRUPT ENABLE REGISTER 1 GSC INTERFRAME SPACING INTERRUPT PRIORITY REGISTER 0 INTERRUPT PRIORITY REGISTER 1 GSC SLOT ADDRESS PORT 0 PORT 1 PORT 2
141. 1 Software Serial Port Implemented with the 7 425 Small DC Motor Control 8 The appropriate data sheet rec DRM a 87C51GB Hardware 6 Description 87 51 Hardware Description CONTENTS PAGE CONTENTS 1 0 INTRODUCTION TO THE 8XC51GB 2 0 MEMORY ORGANIZATION 2 1 Reading the 2 2 Data Memory pare Capture Modules 3 0 SPECIAL FUNCTION REGISTERS 8 1 Framing Error Detection 8 2 Multiprocessor Communications 8 3 Automatic Address Recognition 5 0 TIMER COUNTERS 8 4 Baud Rates 5 1 Timer 0 and Timer 1 8 5 Timer 1 to Generate Baud Timer 2 Capture Mode Timer 2 Auto Reload Mode eception 10 0 WATCHDOG 10 1 Using the WDT 18 e DOT During Power Down and 6 3 A D Trigger Mode 6 4 A D Input Modes 6 Using the A D with Fewer than 8 rower DOW 61 5 CONTENTS 12 0 INTERRUPTS 14 0 POWER SAVING MODES 12 1 External Interrupts 14 1 Idle Mode 12 2 Timer Interrupts 14 2 Power Down Mode 12 3 PCA Interrupt 14 3 Power Off Flag 12 4 Serial Port Interrupt 15 0 EPROM OTP PROGRAMMING 12 5 Interrupt Enable 15 1 Program Memory Lock Program Lock Bits 16 0 ONCE MODE 6 2 intel 87C51GB HARDWARE DESCRIPTION 1 0 INTRODUCTION TO THE 8XC51GB The 8XC51GB is a highly integrated 8 bit microcon troller based the MCS 51 architecture As a mem ber of the MCS 51
142. 1 Encoding 111110101 direct address Operation direct lt direct Rn Bytes 2 2 Encoding direct address Operation MOV direct Rn MOV direct direct Bytes 3 Cycles 2 Encoding 1000 0101 dir addr src dir addr dest Operation MOV direct direct MOV direct GRi Bytes 2 Cycles 2 KEPE TM Operation MOV direct Ri MOV direct data Bytes 3 Cycles 2 Encoding 0111 direct address immediate data Operation MOV direct lt data 2 54 intel Ri A Bytes Cycles Encoding Operation MOV Ri direct Bytes Cycles Encoding Operation Ri data Bytes Cycles Encoding Operation MCS 51 PROGRAMMER 5 GUIDE AND INSTRUCTION SET 1 1 MOV Ri 2 2 MOV direct 2 1 o111 o01tij MOV RD data MOV lt dest bit gt lt src bit gt Function Description Example Move bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand One of the operands must be the carry flag the other may be any directly addressable bit No other register or flag is affected The carry flag is originally set The data present at input Port 3 is 11000101B The data previously written to output Port 1 is 35H 00110101B MOV P1 3 C MOV 3 3 MOV 12 will leave the carry
143. 1 The diodes D1 and D2 which act as clamps to and Vss are parasitic to the Rr FETs The crystal specifications and capacitance values C1 and C2 in Figure 39 are not critical 30 pF can be used in these positions at any frequency with good quality crystals In general crystals used with these devices typically have the following specifications ESR Equivalent Series Resistance CO shunt capacitance 7 0 pF maximum CL load capacitance 30 pF 3 pF Drive Level 1MW 270897 37 270897 38 Figure 38 Using the CHMOS On Chip Oscillator 6 53 87C51GB HARDWARE DESCRIPTION o vi u 4 8 12 CRYSTAL FREQUENCY in MHz 270897 39 16 Figure 39 ESR Frequency Frequency tolerance and temperature range are deter mined by the system requirements ceramic resonator can be used in place of the crystal in cost sensitive applications When a ceramic resona tor is used and C2 are normally selected as higher values typically 47 pF The manufacturer of the ceram ic resonator should be consulted for recommendations on the values of these capacitors A more in depth discussion of crystal specifications ce ramic resonators and the selection of values for C1 and C2 can be found in Application Note AP 155 tors for Microcontrollers in the Embedded Control Applications handbook drive the CHMOS parts with external clock source apply the external clock sign
144. 1 5 This is used to perform the HOLD function for DMA transfers HOLD can be an input or an output depending on the configuration of the DMA channels P1 5 must be programmed to a 1 for this function to operate IDA Increment Destination Address see DCONO IE 7 6 5 4 3 2 1 0 Interrupt Enable SFR used to individually enable the Timer and Local Serial Channel interrupts Also con tains the global enable bit which must be set to a 1 to enable any interrupt to be automatically recognized by the CPU IE 0 EX0 Enables the external interrupt INTO P3 2 IE 1 ETO Enables the Timer 0 interrupt 7 66 IE 2 EX1 Enables the external interrupt INT on 3 3 Enables the Timer 1 interrupt 4 ES Enables the Local Serial Channel interrupt IE 7 EA The global interrupt enable bit This bit must be set to a 1 for any other interrupt to be enabled 0C8H 76 5 4 3 2 1 0 Interrupt enable register and GSC interrupts A 1 in any bit position enables that interrupt IEN1 0 EGSRV Enables the GSC valid receive in terrupt IENI 1 EGSRE Enables the GSC receive error in terrupt IEN1 2 EDMAO Enables the DMA done interrupt for Channel 0 IEN1 3 EGSTV Enables the GSC valid transmit in terrupt IEN1 4
145. 1 and ISA 1 the internal source is in the 256 byte data RAM In any case if ISA 1 the source address is automati cally incremented after each byte transfer If ISA 0 it is not The functions of these four control bits are summarized below pas IDA Destination Auto Increment External RAM External RAM y SFR no Internal RAM CIL mr External RAM External RAM SFR Internal RAM intel 83C152 HARDWARE DESCRIPTION There are four modes in which the DMA channel can operate These are selected by the bits DM and TM Demand Mode and Transfer Mode in DCONn TM OperatingMode Alternate Cycles Mode Burst Mode Serial Port Demand Mode External Demand Mode The operating modes are described below 4 1 1 ALTERNATE CYCLE MODE In Alternate Cycles Mode the DMA is initiated by set ting the GO bit in DCONn Following the instruction that set the GO bit one more instruction is executed and then the first data byte is transferred from the source address to the destination address Then another instruction is executed and then another byte of data is transferred and so on in this manner Each time a data byte is transferred BCRn Byte Count Register for DMA Channel n is decremented When it reaches 0000H on chip hardware clears the GO bit and sets the DONE bit and the DMA ceases The DONE bit flags an interrupt 4 1 2 BURST MODE Burst Mode differs from Alternate
146. 2 SMOD is the PCON register Most of the time the user knows the baud rate and needs to know the reload value for TH1 Therefore the equation to calculate TH1 can be written as K x Osc Freq 256 Ties 384 x baud rate must be an integer value Rounding off to the nearest integer may not produce the desired baud rate In this case the user may have to choose another crystal frequency Since the PCON register is not bit addressable one way to set the bit is logical ORing the PCON register ie ORL PCON 80H The address of PCON is 87H USING TIMER COUNTER 2 TO GENERATE BAUD RATES For this purpose Timer 2 must be used in the baud rate generating mode Refer to Timer 2 Setup Table in this chapter If Timer 2 is being clocked through pin T2 P1 0 the baud rate is Bai Fia 2 Fists 16 And if it is being clocked internally the baud rate is Osc Freq o Baud Rate 57 65536 RCAP2H RCAP2D To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as Osc Freq RCAP2H RCAP2L 65536 32x Baud Rate SERIAL PORT iN MODE 2 The baud rate is fixed in this mode and is 15 or of the oscillator frequency depending on the value of the SMOD bit in the PCON register In this mode none of the Timers are used and the clock comes from the internal phase 2 clock SMOD 1 Baud Rate 7 4 Osc Freq SMOD 0 Baud Rate Osc Freq To set th
147. 2 HARDWARE DESCRIPTION 7 6 POSITIONS RECEPTION SENDING SEQUENCE FNAL SEQUENCE 270427 15 RECEPTION SEQUENCE The sequence expected in the SENDING SEQUENCE portion of the control byte in the next received frame This also confirms correct reception of up to seven frames prior to the sequence given POLL FINAL Identifies the frame as being a polling request from the master station or the last in a series of frames from the master or secondary SENDING SEQUENCE Identifies the sequence of the frame being transmitted 0 If bit 0 0 the frame is identified as informational format type INFORMATION FORMAT gt gt cm gt GP 45 CP 4D P gt gt d gt gt PosmoNs 7 6 5 4 3 2 1 0 RECEPTION x SEQUENCE 270427 16 RECEPTION SEQUENCE Expected sequence of frame for next reception POLL FINAL Identifies frame as being a polling request from the master station or the last a series of frames from the master or secondary MODE Identifies whether receiver is ready 00 not ready 10 or a frame was rejected 01 The rejected frame is identified by the reception sequence 0 1 If bits 1 0 0 1 the frame is identified as a supervisory format type SUPERVISORY FORMAT n a D D Gb 9 5 Bo
148. 2 or EXF2 bit can generate the Timer 2 inter rupt if it is enabled Figure 13 shows timer 2 automati cally counting up when DCEN 0 87C51GB HARDWARE DESCRIPTION Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 14 In this mode the T2EX pin controls the direction of count logic 1 at T2EX makes Timer 2 count up The timer will overflow at OFFFFH and set the TF2 bit which can then generate an interrupt if it is enabled This overflow also causes the 16 bit value in RCAP2H and RCAP2L to be re loaded into the timer registers TH2 and TL2 respec tively logic 0 at 2 makes Timer 2 count down Now the timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L The under RCAP2H RCAP2L 270897 15 D RCAP2H RCAP2L UP COUNTING RELOAD VALUE 2 PIN 270897 16 Figure 14 2 Auto Reload Mode 1 6 19 intel flow sets the TF2 bit and causes OFFFFH to be reload ed into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows This bit can be used as a 17th bit of resolu tion if desired In this operating mode EXF2 does not generate an interrupt 5 3 Programmable Clock Out The 87C51GB has new feature 5096 duty cycle clock can be programmed to come out on P1 0 This pin besides being a regular I O pin has two alternate functions It can be programmed 1 to input the exter
149. 20 b Using XCHs 9 bytes 5 us Figure 11 Shifting a BCD Number Two Digits to the Right After the routine has been executed the Accumulator contains the two digits that were shifted out on the right Doing the routine with direct MOVs uses 14 code bytes and 9 ps of execution time assuming a 12 MHz clock The same operation with XCHs uses less code and executes almost twice as fast right shift by an odd number of digits a one digit shift must be executed Figure 12 shows a sample of code that will right shift a BCD number one digit us ing the XCHD instruction Again the contents of the registers holding the number and of the Accumulator are shown alongside each instruction MOV R1 2EH MOV 2DH loop for R1 2EH LOOP MOV A R1 XCHD A eRO SWAP A MOV R1 A DEC DEC CJNE R1 2AH LOOP loop for R1 2DH loop for R1 2CH loop for R1 2BH 00 00 23 08101123145167 01 CLR o 01 zs 4s er 00 A 2AH 00101123145167 08 Figure 12 Shifting a BCD Number One Digit to the Right First pointers R1 and RO are set up to point to the two bytes containing the last four BCD digits Then a loop is executed which leaves the last byte location 2EH holding the last two digits of the shifted number The pointers are decremented and the loop is repeated for location 2DH The CJNE instruction Compare and Jump if Not Equal is a loop control tha
150. 26 7 2 Compare Capture Modules Each of the five compare capture modules has six pos sible functions it can perform 16 bit Capture positive edge triggered 16 bit Capture negative edge triggered 16 bit Capture both positive and negative edge triggered 16 bit Software Timer 16 bit High Speed Output 8 bit Pulse Width Modulator In addition module 4 can be used as a Watchdog Tim er The modules can be programmed in any combina tion of the different modes intel 87C51GB HARDWARE DESCRIPTION Each module has a mode register called CCAPMn n O 1 2 3 or 4 to select which function it will perform The ECCFn bit enables the PCA interrupt when a module s event flag is set The event flags are located in the CCON register and get set when a capture event software timer or high speed output event occurs for a given module Each module also has a pair of 8 bit compare capture registers CCAPnH and CCAPnL associated with it These registers store the time when a capture event curred or when a compare event should occur For the mode the high byte register CCAPnH controls the duty cycle of the waveform 7 3 PCA Capture Mode Both positive and negative transitions can trigger a cap ture with the PCA This gives the PCA the flexibility to measure periods pulse widths duty cycles and phase differences on up to five separate inputs Setting the CAPPn and or CAPNn bits in the CCAPMn mode
151. 3 3 In Manchester encoding the value of the bit is determined by the transition in the middle of the bit time a positive transition is decod ed as 1 and a negative transition is decoded as a 0 The Address and Info bytes are transmitted LSB first The CRC is transmitted MSB first If the external 1X clock feature is chosen the transmis sion mode is always NRZ see Section 3 5 11 Using CSMA CD with the external clock option is not sup ported because the data needs reformatting from NRZ to Manchester for the receiver to be able to detect code violations and collisions 3 2 5 COLLISION DETECTION The GSC hardware detects collisions by detecting Man chester waveform violations at its GRXD pin Three kinds of waveform violations are detected a missing O to 1 transition where one was expected 1 to O tran sition where none was expected and a waveform that stays low or high for too short a time Jitter Tolerance A valid Manchester waveform must have a transition at the midpoint of any bit cell and may have a transition at the edge of any bit cell Therefore transitions will nominally be separated by either 1 2 bit time or 1 bit time The GSC samples the GRXD pin at the rate of 8 x the bit rate The sequence of samples for the received bit sequence 001 would nominally be samples 11110000 0000 1111 bit value 0 1 E lt bit cell gt lt bit cell gt lt bit cell gt 1111 0000 sa
152. 36 counts of the PCA timer 7 7 Pulse Width Modulator Mode Any or all of the five PCA modules can be pro grammed to be a Pulse Width Modulator The PWM output can be used to convert digital data to an analog signal by simple external circuitry The frequency of the PWM depends on the clock source for the PCA timer With a 16 MHz crystal the maximum frequency of the PWM waveform is 15 6 KHz Table 16 shows the vari ous frequencies that are possible intel 87C51GB HARDWARE DESCRIPTION Table 16 PWM Frequencies PWMF saq 1 4 11 8 2 15 6 KHz 0 Overflow 8 bit 15 5 Hz 20 3 Hz 16 bit 0 06 Hz 0 08 Hz 8 bit Auto Reload 3 9 KHz to 15 3 Hz 5 2 KHz to 20 3 Hz External Input Max 5 9 KHz 7 8 KHz For this mode the ECOMn bit and the PWMn bits in The value in CCAPnL controls the duty cycle of the the CCAPMn mode register need to be set The PCA waveform To change the value in CCAPnL without generates 8 bit PWMs by comparing the low byte of the output glitches the user must write to the high byte PCA timer CL with the low byte of the module s register CCAPnH This value is then shifted by hard compare registers CCAPnL When CL lt CCAPnL ware into CCAPnL when CL rolls over from OFFH to the output is low When CL gt CCAPnL the output is which corresponds to the next period of the out high Refer to Figure 23 put CL MADE FF
153. 7 5 11 986 MHZ 0 0 2 110 6 MHZ 0 0 2 110 12 MHZ 0 0 1 Figure 15 Timer 1 Generated Used Baud Rates Using Timer 2 to Generate Baud Rates 11 Note then the baud rates for transmit and receive can be simultaneously different Setting RCLK and or In the 8052 Timer 2 is selected as the baud rate genera TCLK puts Timer 2 into its baud rate generator mode tor by setting TCLK and or RCLK in Y2CON Figure as shown in Figure 16 NOTE OSC FREQ IS DIVIDED BY 2 NOT 12 270252 14 Figure 16 Timer 2 in Baud Rate Generator Mode 3 16 intel The baud rate generator mode is similar to the auto re load mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software Now the baud rates in Modes 1 and 3 are determined by Timer 2 s overflow rate as follows Timer 2 Overflow Rate 16 The Timer can be configured for either timer or counter operation In the most typical applications it is configured for timer operation C T2 0 Tim er operation is a little different for Timer 2 when it s being used as a baud rate generator Normally as a timer it would increment every machine cycle thus at the oscillator frequency As a baud rate generator however it increments every state time thus at 7 the oscillator frequency In that case the baud rate is given by the formula Modes 1 3 Baud Rat
154. 83C152 Hardware Description _ ___ 5 5 51 Family 1 Microcontrollers Architectural Overview MCS 51 FAMILY OF CONTENTS PAGE MICROCONTROLLERS ARCHITECTURAL OVERVIEW 1 1 intel MCS 51 ARCHITECTURAL OVERVIEW INTRODUCTION The 8051 is the original member of the MCS 51 family and is the core for all MCS 51 devices The features of the 8051 core are e 8 bit CPU optimized for control applications Extensive Boolean processing single bit logic capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on chip Program Memory 128 bytes of on chip Data RAM 32 bidirectional and individually addressable I O lines Two 16 bit timer counters Full duplex UART 6 source 5 vector interrupt structure with two priority levels On chip clock oscillator The basic architectural structure of this 8051 core is shown in Figure 1 EXTERNAL INTERRUPTS INTERRUPT 128 BYTES ae CONTROL RAM BUS I SERIAL CONTROL E 41 0 PORTS 2 _ ADDRESS 1 5 270251 1 Figure 1 Block Diagram of the 8051 Core MCS 51 ARCHITECTURAL OVERVIEW 9 952 410 85728 02921 25 85108 029121 410 9 ____ 7918 WOH 72108 e 0291 952 WOHdlO 8 29128 L 2 ee 029121 92 408 e
155. 89H Not Bit Addressable TIMER 1 Bit Function Reset Value 0000 00008 TIMER 0 m cate m Mo 7 6 5 4 3 2 1 0 Gating control when set Timer Counter 0 1 is enabled only while INTO INT1 is high and TR0 or TR1 control pin is set When cleared Timer 0 or 1 is enabled whenever TR0 or TR1 control bit is set Timer or Counter Selector Clear for Timer operation internal system clock Set for Counter operation input from TO T1 input pin Operating Mode 8 bit Timer Counter THx with TLx as 5 bit prescaler 16 bit Timer Counter THx and TLx are cascaded there is no prescaler 8 bit auto reload Timer Counter THx holds a value which is to be reloaded into TLx each time it overflows Timer 0 TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits Timer 1 Timer Counter stopped INTERRUPT OVERFLOW 270653 6 Figure 8 Timer Counter 0 1 0 13 Bit Counter 5 13 8XC51FX HARDWARE DESCRIPTION Table 6 TCON Timer Counter Control Register Address 88H Bit Addressable Bit Symbol Function TF1 Reset Value 0000 00008 o m eo 7 6 5 4 3 2 1 0 Timer 1 overflow Flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 TF
156. 9 KBPS There certain requirements that the external clock will need to meet These requirements are specified in the data sheet For a description of the use of the GSC with external clock please read Section 3 5 11 3 5 5 INITIALIZATION Initialization can be broken down into two major com ponents 1 initialization of the component so that its serial port is capable of proper communication and 2 initialization of the system or a station so that intelligi ble communication can take place Most of the initialization of the component has already been discussed in the previous sections Those items not covered are the parameters required for the component to effectively communicate with other components These types of issues are common to both system and component initialization and will be covered in the fol lowing text 7 37 Initialization of the system can be broken down into several steps First are the assumptions of each net work station The first assumption is that the type of data encoding to be used is predetermined for the system and that each station will adhere to the same basic rules defining that encoding The second assumption is that the basic protocol and line discipline is predetermined and known This means that all stations are using CSMA CD or SDLC or whatever and that all stations are either full or half duplex The third assumption is that the baud rate is preset for the whole system Although
157. A External Clock input P1 3 CEXO PCA Module 0 Capture Input Compare PWM Output P1 4 CEX1 PCA Module 1 Capture Input Compare PWM Output P1 5 CEX2 PCA Module 2 Capture Input Compare PWM Output 1 6 Module Capture Input Compare PWM Output P1 7 CEX4 PCA Module 4 Capture Input Compare PWM Output P2 0 AB P2 7 A15 High Byte of Address for External Memory P3 0 RXD Serial Port input P3 1 TXD Serial Port Output P3 2 INTO External Interrupt O P3 3 INT1 External Interrupt 1 P3 4 TO Timer 0 External Clock Input P3 5 T1 Timer 1 External Clock Input P3 6 WR Write Strobe for External Memory P3 7 RD Read Strobe for External Memory P4 0 SEPCLK Clock Source for SEP P4 1 SEPDAT Data for SEP P4 2 ECI1 PCA1 External Clock Input P4 3 C1EXO PCA1 Module 0 Capture Input Compare PWM Output P4 4 C1EX1 PCA1 Module 1 Capture Input Compare PWM Output P4 5 C1EX2 PCA1 Module 2 Capture Input Compare PWM Output P4 6 C1EX3 1 Module 3 Capture Input Compare PWM Output P4 7 C1EX4 P5 2 INT2 PCA1 Module 4 Capture Input Compare PWM Output External Interrupt 2 P5 3 INT3 External Interrupt 3 P5 4 INT4 External Interrupt 4 P5 5 INT5 External Interrupt 5 P5 6 INT6 External Interrupt 6 NOTE The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1 Otherwise the port pin will not go high intel 4 0 PORTS
158. AD NEXT OPCODE AGAIN READ NEXT OPCODE AGAIN NO FETCH ACCESS EXTERNAL MEMORY 270251 15 Figure 15 State Sequences in 59 51 Devices 1 18 intel states and phases for various kinds of instructions Nor mally two program fetches are generated during each machine cycle even if the instruction being executed doesn t require it If the instruction being executed doesn t need more code bytes the CPU simply ignores the extra fetch and the Program Counter is not incre mented Execution of a one cycle instruction Figure 15 and B begins during State 1 of the machine cycle when the opcode is latched into the Instruction Register A sec ond fetch occurs during S4 of the same machine cycle Execution is complete at the end of State 6 of this ma chine cycle The MOVX instructions take two machine cycles to execute No program fetch is generated during the sec ond cycle of a instruction This is the only time program fetches are skipped The fetch execute se quence for MOVX instructions is shown in Figure 15 D 5 51 ARCHITECTURAL OVERVIEW The fetch execute sequences are the same whether the Program Memory is internal or external to the chip Execution times do not depend on whether the Pro gram Memory is internal or external Figure 16 shows the signals and timing involved in pro gram fetches when the Program Memory is external If Program Memory is external then the Program Memo ry re
159. AND INSTRUCTION SET Logical OR for bit variables Set the carry flag if the Boolean value is a logical 1 leave the carry its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Set the carry flag if and only if P1 0 1 ACC 7 1 OV 0 MOV 1 0 LOAD CARRY WITH INPUT PIN 10 ORL 7 CARRY WITH THE ACC 7 ORL CARRY WITH THE INVERSE OF 2 2 0111 0010 ORL V bit 2 2 ORL v bit 2 63 intel 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET POP direct Function Pop from stack Description contents of the internal RAM location addressed by the Stack Pointer is read and the Stack Pointer is decremented by one The value read is then transferred to the directly ad dressed byte indicated No flags are affected Example Stack Pointer originally contains the value 32H and internal RAM locations through 32H contain the values 20H 23H and 01H respectively The instruction sequence POP DPH POP DPL will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H At this point the instruction POP SP will leave the Stack Pointer set to 20H Note that in this special case the Stack Po
160. ARDWARE DESCRIPTION DOWN COUNTING RELOAD VALUE FFH INTERRUPT RCAP2H RCAP2L COUNTING RELOAD VALUE T2EX PIN 270653 11 Figure 14 Timer 2 Auto Reload Mode DCEN 1 1 TH2 8 Bits MA T20E T2MOD 1 Timer 2 Interrupt 270653 35 Figure 15 Timer 2 in Clock Out Mode intel 8XC51FX HARDWARE DESCRIPTION 16 BITS EACH MODULE 0 P1 5 CEXO MODULE 1 LA P1 4 CEX1 PCA TIMER COUNTER MODULE 2 DJ 1 5 2 1 6 MODULE 4 1 7 Figure 15a Programmable Counter Array 270653 12 The timer counter and compare capture modules gram of this timer The clock input can be selected share Port 1 pins for external I O These pins are listed from the following four modes below If the port pin is not used for the PCA it can Oscillator frequency 12 still be used for standard 1 O The CL register is incremented at S5P2 of every machine cycle With a 16 MHz crystal the timer PCA Component External 1 Pin increments every 750 nanoseconds 16 bit Counter P1 2 ECI frequency 4 Module The CL register is incremented at 51 2 S3P2 and 16 bit Module 1 P1 4 1 S5P2 of every machine cycle With a 16 MHz crys 16 bit Module 2 P1 5 CEX2 tal the timer increments every 250 nanoseconds 16 bit Module 3 P1 6 CEX3 Timer overflows 16 bit Module 4 P1 7 Th
161. BB A data Bytes Cycles Encoding Operation SWAP A Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 SUBB C direct 1 1 SUBB O 2 1 SUBB A data Swap nibbles within the Accumulator SWAP A interchanges the low and high order nibbles four bit fields of the Accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are affected Accumulator hoids the value 5 110001018 The instruction SWAP A leaves the Accumulator holding the value 5CH 01011100B 1 1 1 0100 SWAP 3 0 A74 2 71 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XCH A lt byte gt Function Description Example Bytes Cycles Encoding Operation A direct Bytes Cycles Encoding Operation Bytes Cycles Encoding Operation Exchange Accumulator with byte variable XCH loads the Accumulator with the contents of the indicated variable at the same time writing the original Accumulator contents to the indicated variable The source destination operand can use register direct or register indirect addressing RO contains the address 20H The Accumulator holds the value 3FH 00111111B Internal
162. BM documents which go into detail on the SDLC protocol and its use The control field is eight bits wide and the format is determined by bits O and 1 If bit O is a zero then the frame is an informational frame If bit O is a one and bit 1 a zero then it is a supervisory frame and if bit 0 is a one and bit 1 a one then the frame is an unnumbered frame In an informational frame bits 3 2 1 contain the se quence count of the frame being sent Bit 4 is the P F Poll Final bit If bit 4 equals 1 and originates from the primary then the secondary station is expected to initiate a transmission If bit 4 equals 1 and originates from a secondary station then the frame is the final frame in a transmission Bits 7 6 5 contain the sequence count a station expects on the next transmission to it The sequence count can vary from 000 to 1118 The count then starts over again at 0008 after the value 111B is incremented The acknowledgement is recognized by the receiving station when it decodes bits 7 6 5 of an incoming frame The station sending the transmission is acknowledging the frames received up to the count represented in bits 7 6 5 sequence count 1 With this method up to seven se quential frames may be transmitted prior to an ac knowledgement being received If eight frames were al lowed to pass before an acknowledgement the sequence count would roll over and this would negate the pur pose of the sequence numbers intel 83C15
163. Baud Rato 1256 THD _ 32 x 12 x 256 TH1 One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled and configuring the Timer to run as 16 bit timer high nibble of TMOD 0001B and using the Timer 1 interrupt to do a 16 bit software reload Table 15 lists various commonly used baud rates and how they can be obtained from Timer 1 7 6 Using Timer 2 to Generate Baud Rates Timer 2 is selected as the baud rate generator by setting TCLK and or RCLK in T2CON Table 7 Note that the baud rates for transmit and receive can be simulta neously different Setting RCLK and or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 23 The baud rate generator mode is similar to the auto re load mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software Table 15 Timer 1 Generated ae e Used Baud Rates 110 12 MHz 5 30 Baud Rate Value Mode 0 1 MHz 12 MHz Mode 2 Max 375K 12 MHz Modes 1 3 62 5K 12 MHz 19 2K 11 059 MHz 9 6K 11 059 MHz 4 8K 11 059 MHz 2 4K 11 059 MHz 1 2K 11 059 MHz 137 5 11 986 MHz 110 6 MHz O O O O O O gt x O O O O O O O O x x lt N N N N N N N N gt lt intel 8XC51FX HARDWARE DESCRIPTION The baud rates in Modes 1 and 3 are determined by Timer 2 5 overflow rate as foll
164. C relative offset IF Rn data THEN 1 C 0 ELSE CJNE Ri data rel Bytes 3 Cycles 2 Encoding 10110111 immediate data Operation 3 IF Ri lt gt data THEN relative offset IF Ri lt data THEN 1 C 0 ELSE 2 36 intel CLR A Function Description Example Bytes Cycles Encoding Operation CLR bit Function Description Example CLR C Bytes Cycles Encoding Operation CLR bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Clear Accumulator The Accumulator is cleared all bits set on zero No flags are affected The Accumulator contains 5CH 01011100B The instruction CLR A will leave the Accumulator set to 000000008 1 1 CLR 0 Clear bit The indicated bit is cleared reset to zero No other flags are affected CLR can operate on the carry flag or any directly addressable bit Port 1 has previously been written with SDH 01011101 The instruction CLR 12 will leave the port set to 59H 01011001B 1100 0011 CLR 0 2 1 CLR bit 0 2 37 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CPL A Function Complement Accumulator Description Each bit of the Accumulator is logically complemented one s complement Bits which previ ously contain
165. C With external clock the bit stuffing stripping is still active with SDLC protocol 3 5 12 Determining Receiver Errors It is possible that several receiver error bits will be set in response to a single cause The multiple errors that can occur are AE and CRCE may both be set when an alignment error occurs due to a bad CRC caused by the mis aligned frame RCABT AE and CRCE may be set when an abort Occurs OVR AE and CRCE may be set when a overrun oc curs In order to determine the correct cause of the error a specific order should be followed when examining the error bits This order is 1 OVR 2 RCBAT 3 AE 4 CRCE 3 5 13 Addressing There are four 8 bit address registers ADRO ADRI ADR2 ADR3 and two 8 bit address mask registers AMSKO AMSK1 in the C152 These function with the GSC receiver only The transmitted address is treat ed like any other data The address is transmitted under Software control by placing the address byte s at the proper location usually first in the sequence of bytes to be output in the outgoing packet The C152 can have up to four different 8 bit addresses or two different 16 bit addresses assigned to each sta tion When using 16 bit addressing ADRO ADR1 form one address and ADR2 ADR3 form the second ad dress If the receiver is enabled it looks for a matching address after every BOF flag is detected As the data is received if the 8th or 16th bit does not match t
166. C51FX does not include the 80C51FA and 83C51FA Therefore these devices do not have some of the features found on the 8 51 These features are programmable clock out four level interrupt priority structure enhanced program lock scheme and asynchronous port reset e Four 8 Bit Bidirectional Parallel Ports Three 16 Bit Timer Counters with One Up Down Timer Counter Clock Out Programmable Counter Array with Compare Capture Software Timer High Speed Output Pulse Width Modulator Watchdog Timer Full Duplex Programmable Serial Port with Framing Error Detection Automatic Address Recognition Interrupt Structure with Seven Interrupt Sources Four Priority Levels Power Saving Modes Idle Mode Power Down Mode Table 1 summarizes the product names and memory differences of the various 8XC51FX products currently available Throughout this document the products will generally be referred to as the C51FX 5 3 Table 1 C51FX Family of Microcontrollers ROM EPROM ROMlIess Device Version Version 83C51FA BOCS1FA 256 870518 51 256 256 2 0 MEMORY ORGANIZATION All MCS 51 devices have a separate address space for Program and Data Memory Up to 64 Kbytes each of external Program and Data Memory can be addressed 2 1 Program Memory If the EA pin is connected to Vss all program fetches
167. CLK and or TCLK puts Timer 2 One can achieve very low baud rates with Timer 1 by into its baud rate generator mode as shown in Figure leaving the Timer 1 interrupt enabled and configuring 29 the Timer to run as a 16 bit timer high nibble of TMOD 0001B and using the Timer 1 interrupt to do a 16 bit software reload Baud Rate F meme T ee Reload Value X Mode 0 Max 1 MHz 12 MHz X X X Mode 2 Max 375K 12 MHz 1 X X Modes 1 amp 3 62 5K 12 MHz 1 0 2 19 2K 11 059 MHz 1 0 2 9 6K 11 059 MHz 0 0 2 4 8K 11 059 MHz 0 0 2 2 4K 11 059 MHz 0 0 2 1 2K 11 059 MHz 0 0 2 137 5 11 986 MHz 0 0 2 110 6 MHz 0 0 2 110 12 MHz 0 0 1 Figure 28 Timer 1 Generated Used Baud Rates NOTE OSC FREQ 15 DIVIOED BY 2 NOT 12 Cam AVAILABILITY OF ADOITIONAL EXTERNAL INTERRUPT 270897 30 Figure 29 Timer 2 in Baud Rate Generator Mode 6 37 intel 87C51GB HARDWARE DESCRIPTION The baud rate generator mode is similar to the auto re load mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in Modes 1 and 3 are determined by Timer 275 overflow rate as follows Modes 1 and 3 _ Timer 2 Overflow Rate Baud Rates e Timer 2 can be configured for either timer or coun ter operation In most applications it is configured for
168. Cycles mode only in that once the data transfer has begun program execu tion is entirely suspended until BCRn reaches 0000H indicating that all data bytes that were to be transferred have been transferred The interrupt control hardware remains active during the DMA so interrupt flags may get set but since program execution is suspended the interrupts will not be serviced while the DMA is in progress 4 1 3 SERIAL PORT DEMAND MODE In this mode the DMA can be used to service the Local Serial Channel LSC or the Global Serial Channel GSC In Serial Port Demand Mode the DMA is initiated by any of the following conditions if the GO bit is set Source Address SBUF RI 1 Destination Address SBUF 1 Source Address RFIFO 1 Destination Address TFIFO AND 1 Each time one of the above conditions is met one DMA Cycle is executed that is one data byte is trans ferred from the source address to the destination ad 7 49 dress On chip hardware then clears the flag RI TI RFNE that initiated the DMA and decre ments BCRn Note that since the flag that initiated the DMA is cleared it will not generate an interrupt unless DMA servicing is held off or the byte count equals 0 DMA servicing may be held off when alternate cycle is being used or by the status of the HOLD HLDA logic In these situations the interrupt for the LSC may occur before the DMA c
169. E GSC Receive Error GSCTV GSC Transmit Valid GSCTE GSC Transmit Error DMAO DMA Channel 0 Done Channel 1 Done As shown in Figure 5 1 the Receive Valid interrupt can be signaled either by the RFNE flag Receive FIFO Not Empty or by the RDN flag Receive Done Which one of these flags causes the interrupt depends on the setting of the DMA bit in the SFR named TSTAT 0 means the hardware 15 not config ured to service the GSC so the CPU will service it in software in response to the Receive FIFO not being empty In that case generates the Receive Valid interrupt DMA 1 means the hardware is configured to service the GSC in which case the CPU need not be interrupted till the receive is complete In that case RDN generates the Receive Valid interrupt Similarly the Transmit Valid interrupt can be signaled either by the TFNF flag Transmit FIFO Not Full or by the TDN flag Transmit Done depending on whether the DMA bit is O or 1 Note that setting the DMA bit does not itself configure the DMA channels to service the GSC That job must be done by software writes to the DMA registers The bit only selects whether the GSCRV and GSCTYV interrupts are flagged by a FIFO needing serv ice or by an operation done signal The Receive and Transmit Error interrupt flags are generated by the logical OR of a number of error condi tions which are described i
170. EDGE Hardware Based Acknowledge HBA is a data link packet acknowledging scheme that the user software can enable with CSMA CD protocol It is not an op tion with SDLC protocol however In general HBA can give improved system response time and increased effective transmission rates over ac knowledge schemes implemented in higher layers of the network architecture Another benefit is the possibility of early release of the transmit buffer as soon as the acknowledge is received The acknowledge consists of a preamble followed by an idle condition A receiving station with HABEN en abled will send an acknowledge only if the incoming address is unique to the receiving station and if the frame is determined to be correct with no errors For the acknowledge to be sent TEN must be set For the transmitting station to recognize the acknowledge GREN must be set zero as the LSB of the address indicates that the address is unique and not a group or broadcast address Errors can be caused by collisions incorrect CRC misalignment or FIFO overflow The receiver sends the acknowledge as soon as the line is sensed to be idle The user must program the interframe space and the preamble length such that the acknowl edge is completed before IFS expires This is normally done by programming IFS larger than the preamble 83C152 HARDWARE DESCRIPTION A transmitting station with HABEN enabled expects an acknowledge It must receive one prior to t
171. For 10 MHz crystal the start up time is typically 1 msec For a 1 MHz crystal the start up time is typically 10 msec With the given circuit reducing quickly to 0 caus es the RST pin voltage to momentarily fall below OV However this voltage is internally limited and will not harm the device 5 38 Note that the port pins will be in a random state until the oscillator has started and the internal reset algorithm has written 1s to them Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location This is because the SFRs spe cifically the Program Counter may not get properly 10 0 POWER SAVING MODES OPERATION For applications where power consumption is critical the C51FX provides two power reducing modes of op eration Idle and Power Down The input through which backup power is supplied during these opera tions is Vcc Figure 28 shows the internal circuitry which implements these features In the Idie mode IDL 1 the oscillator continues to run and the In terrupt Serial Port PCA and Timer blocks continue to be clocked but the clock signal is gated off to the CPU In Power Down PD 1 the oscillator is fro zen The Idle and Power Down modes are activated by setting bits in Special Function Register PCON Table 23 10 1 Idle Mode An instruction that sets causes that to be the last instruction executed before going
172. GTXD pin is pulled to a logic O for the duration of the jam If the node is AC coupled to the network then AC jam must be selected In this case the GSC takes the CRC it has calculated thus far in the transmission inverts each bit and transmits the inverted CRC The selection of DC or AC jam is made by setting or clear ing the DCJ bit which resides in the SFR named MYSLOT When the jam signal is completed the 8X C152 goes into an idle state Presumeably other stations on the network are also generating their own jam signals after which they too go into an idle state When the 8XC152 detects the idle state at its own GRXD pin the backoff sequence begins There three software selectable collision resolution algorithms in the 8XC152 The selection is made by writing values to 3 bits Normal Random Alternate Random Deterministic M1 and MO reside in GMOD DCR is in MYSLOT In the Normal Random algorithm the GSC backs off for a random number of slot times and then decides whether to restart the transmission The backoff time begins as soon as a line idle condition is detected The Alternate Random algorithm is the same as the Normal Random except the backoff time doesn t start until an IFS has transpired 7 25 In the Deterministic algorithm the GSC backs off to await its pre determined turn Random Backoff In either of the random algorithms the first thing that happens after a col
173. H setting the priority For an explanation on how the priority of interrupts affects The C152 retains all five interrupts of the 80C51BH In their operation please refer to the MCS 51 Architecture addition six new interrupts have been added for total Hardware Chapters the Intel Embedded Con of 11 available interrupts Two SFRs have been added troller Handbook A detailed description on how the to the C152 for control of the new interrupts These interrupts function is the MCS 51 Architectural added SFRs are IEN1 C8H for enabling the Overview IEN1 FUNCTIONS under CPU control and EGSTE is enabied This interrupt is invoked if TFNF is set when the GSC is under CPU control EDMAO IEN1 2 DMA CHANNEL REQUEST 0 The interrupt service routine at will be invoked when DCONO 1 DONE is set and is enabled is invoked if RFNE is set when the GSC is under CPU control 7 RESERVED and do not exist on chip service routine is invoked if NOACK TCDT or UR is set when and EGSTV is enabled This interrupt service routine is em 033H GSC RECEIVE ERROR The interrupt service routine at 33H and EGSRV is enabled This interrupt service routine is RESERVED and do not exist on chip EGSTE 04 GSC TRANSMIT ERROR The interrupt service routine at the GSC is under DMA control and EGSTE is enabled EDMA1 IEN1 4 CHANNEL REQUEST 1 interrupt se
174. H Bytes 1 Cycles 2 Encoding 0010 0010 Operation RET 15 8 SP SP SP 1 PC7 9 lt SP SP SP 1 RETI Function Return from interrupt Description RETI pops the high and low order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed The Stack Pointer is left decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Program execution continues at the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower or same level interrupt had been pending when the RETI instruction is executed that one instruction will be executed before the pending interrupt is processed Example Stack Pointer originally contains the value OBH An interrupt was detected during the instruction ending at location 0122H Internal RAM locations OAH and OBH contain the values 23H and 01H respectively The instruction RETI will leave the Stack Pointer equal to and return program execution to location 0123H Bytes Cycles 2 Encoding 0011 0010 Operation RETI 15 8 SP SP SP 1 PC7 9 lt SP SP SP 1 2 65 intel Function Description Example Bytes Cycles Encoding
175. I and TI in register SCON Neither of these flags is cleared by hardware when the service routine is vectored to The service routine will normally have to determine whether it was RI or TI that generated the interrupt and the bit will have to be cleared in soft ware The serial port interrupt is enabled by bit ES in the IE register 12 5 Interrupt Enable Each of these interrupt sources can be individually en abled or disabled by setting or clearing a bit in the Interrupt Enable IE and registers as shown Table 22 Note that IE also contains a global disable bit EA If EA is set 1 the interrupts are individually enabled or disabled by their corresponding bits in IE and If EA is clear 0 all interrupts are disabled Figure 33 shows the interrupt control system 87C51GB HARDWARE DESCRIPTION intel asamsrss eouenbes L 551 Figure 33 Interrupt Control System 6 87C51GB HARDWARE DESCRIPTION Table 22 Interrupt Enable Registers Address Bit Addressable Reset Value 0000 0000B Bit 7 6 5 4 Address OA7H Not Bit Addressable Bit 6 5 4 LEAD Exe exs exa exs EC 7 3 2 1 0 Reset Value 0000 00008 3 2 1 0 Enable bit 1 enables the interrupt Enable bit 0 disables the interrupt Symbol Function Global disable bit If EA 0 all Interrupts are disabled
176. INT1 No level Yes trans TIMER 1 TF1 Yes SERIAL PORT RI TI No TIMER 2 TF2 EXF2 No PCA CF CCFn n 0 4 No Execution proceeds from that location until the RETI instruction is encountered The RETI instruction in forms the processor that this interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted program continues from where it left off Note that a simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking interrupt was still in progress Note that the starting addresses of consecutive inter rupt service routines are only 8 bytes apart That means if consecutive interrupts are being used IEO and TFO for example and 1 and if the first interrupt routine is more than 7 bytes long then that routine will have to execute a jump to some other memory location where the service routine can be completed without overlapping the starting address of the next interrupt routine LONG CALL TO INTERRUPT VECTOR ADDRESS INTERRUPT ROUTINE 270653 22 This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or write IE or IP Figure 25 interrupt Response Timing Diagram 5 36 intel 8XC51FX HARDWARE DESCRIPTION 8 7 Response Time The 0 and IN
177. If EA 1 each Interrupt can be individually enabled or disabled by setting or clearing its enable bit PCA interrupt enable bit Timer 2 interrupt enable bit Serial Port interrupt enable bit Timer 1 interrupt enable bit External interrupt 1 enable bit Timer 0 interrupt enable bit External interrupt 0 enable bit A D converter interrupt enable bit External interrupt 6 enable bit External interrupt 5 enable bit External interrupt 4 enable bit External interrupt 3 enable bit External interrupt 2 enable bit 1 interrupt enable bit Serial Expansion Port interrupt enable bit 12 6 Interrupt Priorities Each interrupt source on the 8XC51GB can be individ ually programmed to one of four priority levels by set ting or clearing the bits in the Interrupt Priority and IPA registers and the Interrupt Priority High IPH and IPAH registers See Table 23 The IPH reg isters have the same bit map as the IP registers with an H added to each bit s name This gives each interrupt source two bits for setting the priority levels The LSB of the Priority Select Bits is in the IP SFR and the MSB is in the IPH SFR A low priority interrupt can itself be interrupted by a higher priority interrupt but not by another interrupt of the same priority The highest priority interrupt can not be interrupted by any other interrupt source If two or more requests of different priority levels are received simultaneously the
178. L NOTE 1 EXTERNAL CONTROL NOTE 2 13 bit Timer 16 bit Timer 8 bit Auto Reload one 8 bit Counter NOTES 1 The Timer is turned ON OFF by setting clearing bit TRO in the software 2 The Timer is turned ON OFF by the 1 to 0 transition on INTO P3 2 when TRO 1 hardware control 2 15 intel 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TIMER COUNTER 1 Asa Counter NOTES Table 5 TIMER 1 FUNCTION INTERNAL CONTROL NOTE 1 13 bit Timer 16 bit Timer 8 bit Auto Reload does not run Table 6 COUNTER 1 FUNCTION INTERNAL CONTROL 13 bit Timer 16 bit Timer 8 bit Auto Reload not available EXTERNAL CONTROL NOTE 2 EXTERNAL CONTROL NOTE 2 1 The Timer is turned ON OFF by setting clearing bit TR1 in the software 2 The Timer is turned ON OFF by the 1 to 0 transition 1 P3 3 when TR1 1 hardware control 2 16 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET T2CON TIMER COUNTER 2 CONTROL REGISTER BIT ADDRESSABLE 8052 Only TF2 EXF2 RCLK TLCK EXEN2 C T2 CP RL2 T2CON 7 T2CON 6 T2CON 5 T2CON 4 T2CON 3 T2CON 2 T2CON 1 T2CON 0 Timer 2 overflow flag set by hardware and cleared by software TF2 cannot be set when either 1 CLK 1 Timer 2 external set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When Ti
179. L are preset by software If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 140 0 transition at external input T2EX This tran sition also sets the EXF2 bit Either the TF2 or EXF2 bit can generate the Timer 2 interrupt if it is enabled Table 9 T2MOD Timer 2 Mode Control Register T2MOD Address OC9H Not Bit Addressable Bit Symbol Function Reset Value XXXX XX00B l 7 6 5 4 3 2 1 0 Not implemented reserved for future use T20E Timer 2 Output Enable bit Down Count Enable bit When set this allows Timer 2 to be configured as an up down counter User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate UR E I RCAP2H RCAP2L Figure 13 Timer 2 Auto Reload Mode DCEN 0 5 17 intel 8XC51FX HARDWARE DESCRIPTION Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 14 In this mode the T2EX pin controls the direction of count A logic 1 at 2 makes Timer 2 count up The timer will overflow at OFFFFH and set the TF2 bit which can then generate an interrupt if it is enabled This overflow also causes a the 16 bit value in 2 and RCAP2L to be re loaded int
180. M2 bit in SCON A way to use this feature in multiprocessor sys tems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an ad dress byte which identifies the target slave Remember an address byte has its 9th bit set to 1 whereas a data 5 28 byte has its 9th bit set to 0 the slave processors should have their SM2 bits set to 1 so they will only be interrupted by an address byte In fact the C51FX has an Automatic Address Recognition feature which al lows only the addressed slave to be interrupted That is the address comparison occurs in hardware not soft ware On the 8051 serial port an address byte inter rupts all slaves for an address comparison The addressed slave s software then clears its SM2 bit and prepares to receive the data bytes that will be com ing The other slaves are unaffected by these data bytes They are still waiting to be addressed since their SM2 bits are all set 7 3 Automatic Address Recognition Automatic Address Recognition reduces the CPU time required to service the serial port Since the CPU is only interrupted when it receives its own address the software overhead to compare addresses is eliminated With this feature enabled in one of the 9 bit modes the Receive Interrupt RI flag will only get set when the received byte corresponds to either a Given or Broad cast address The feature works the same way in the 8
181. MORY SPACE REGISTER BANK 3 REGISTER BANK 2 REGISTER BANK 1 REGISTER BANK O 000 USER DATA MEMORY SPACE 270427 1 NOTE User data memory above 80H must be addressed indirectly Using direct addressing above 80H accesses the Special Function Registers Figure 2 1 Data Memory Map 7 7 intel External data memory is accessed like an 80C51BH with instructions Addresses up to 64K may be accessed when using the Data Pointer DPTR When accessing external data memory with the DPTR the address appears on Port 0 and 2 When using the DPTR if less than 64K of external data memory is used the address is emitted on all sixteen pins This means that when using the DPTR the pins of Port 2 not used for addresses cannot be used for general pur pose I O An alternative to using 16 bit addresses with the DPTR is to use RO or R1 to address the external data memory When using the registers to address ex ternal data memory the address range is limited to 256 bytes However software manipulation of Port 2 pins as normal I O allows this 256 bytes restriction to be expanded via bank switching When using RO or R1 as data pointers Port 2 pins that are not used for ad dressing can be used as general purpose I O IPGSTE PDMA1IPGSTY POMAO PGSRE PGSRV LLL LL LLL LLLI MYSLOT DCJ DCR SAS SAS SA2 SAO D ull l L l l ee LLLI LLL LL LL LLL Es
182. MP is generic mnemonic which can be used if the program mer does not care which way the jump is encoded The SJMP instruction encodes the destination address as a relative offset as described above The instruction is 2 bytes long consisting of the opcode and the relative offset byte The jump distance is limited to a range of 128 to 4 127 bytes relative to the instruction follow ing the SJMP The LJMP instruction encodes the destination address as a 16 bit constant The instruction is 3 bytes long consisting of the opcode and two address bytes The destination address can be anywhere in the 64K Pro gram Memory space The AJMP instruction encodes the destination address as an 11 bit constant The instruction is 2 bytes long consisting of the opcode which itself contains 3 of the 11 address bits followed by another byte containing the low 8 bits of the destination address When the instruc tion is executed these 11 bits are simply substituted for the low 11 bits in the PC The high 5 bits stay the same Hence the destination has to be within the same 2K block as the instruction following the AJMP In all cases the programmer specifies the destination address to the assembler in the same way as a label or as a 16 bit constant The assembler will put the destina tion address into the correct format for the given in struction If the format required by the instruction will not support the distance to the specified destinat
183. NT will still be ANDed with PRBS and the result loaded into BKOFF In order to insure that all stations have the same value loaded into BKOFF which determines the first slot number to occur the PRBS should be loaded with OFFH the PRBS will maintain this value until either the 8 152 is reset or the user writes some other value into PRBS After BKOFF is loaded it begins counting down slot times as soon as the IFS ends Slot times are defined by the user the same way as before by loading SLOTTM with the number of bit times per slot intel When BKOFF equals the slot assignment as defined in MYSLOT the signal MYSLOT in Fig ure 3 5 is asserted for one slot time during which the GSC can restart its transmission While BKOFF is counting down if any activity is de tected at the GRXD pin the countdown is frozen until the activity ends a line idle condition is detected and an IFS transpires Then the countdown resumes from where it left off If a collision is detected at the GRXD while BKOFF is counting down the collision resolution algo rithm is restarted from the beginning In effect the GSC owns its assigned slot number but with one exception Nobody owns slot number O Therefore if the GSC is assigned slot number 0 then when BKOFF 0 this station and any other station that has something to say at this time will have an equal chance to take the line 3 2 7 HARDWARE BASED ACKNOWL
184. O or ADR3 ADR2 will be accepted Addressing mode is determined in GMOD AL AMSKO 1 0D5H 0E5H Address Match Mask 0 1 Identifies which bits in ADRO 1 are don t care bits Writing a one to a bit in AMSKO 1 masks out that corresponding bit in ADDRO 1 BAUD 94H GSC Baud Rate Generator Contains the value of the programmable baud rate The data rate will equal frequency of the oscillator BAUD 1 X 8 Writing to BAUD actually stores the value in a reload register The reload register contents are copied into the BAUD register when the Baud register decre ments to 00H Reading BAUD yields the current timer value A read during GSC operation will give a value that may not be current because the timer could decre ment between the time it is read by the CPU and by the time the value is loaded into its destination BKOFF Backoff Timer The backoff timer is an eight bit count down timer with a clock period equal to one slot time The backoff time is used in the CSMA CD collision resolution algorithm The user software may read the timer but the value may be inval id as the timer is clocked asynchronously to the CPU Writing to OCAH will have no effect GMOD 84H 7 6 5 4 3 2 1 0 XTCLK AL PL1 PR Figure 3 14 GMOD GMOD 0 PR Protocol If set SDLC protocols with NRZI encoding and SDLC flags are used If cleared CSMA CD link access with Manchester encoding is us
185. ODULE 1 P1 4 CEX1 PCA TIMER COUNTER MODULE 2 P1 5 CEX2 MODULE 3 1 6 5 MODULE 4 1 7 4 270897 19 Figure 17 Block Diagram 6 23 intel 87C51GB HARDWARE DESCRIPTION 4 There has been one additional bit added to CICON to allow both PCAs to be enabled simultaneously The bit is called CRE and occupies bit position 5 of Its bit address is OEDH When is set both CR and must be set to enable Each PCA consists of a 16 bit timer counter and five 16 bit compare capture modules as shown in Figure 17 The PCA timer counter serves as a common time base for the five modules and is the only timer which can service the PCA Its clock input can be pro grammed to count any one of the following signals Oscillator frequency 12 Oscillator frequency 4 Timer 0 overflow External input on ECI P1 2 The compare capture modules can be programmed in any one of the following modes rising and or falling edge capture software timer high speed output pulse width modulator Module 4 can also be programmed as a watchdog timer 51 CPSO FOSC 12 FOSC 4 TIMER 0 OVERFLOW EXTERNAL INPUT o 1 9 1 CONTROL CIDL PROCESSOR IN IDLE MODE CH 8 BITS 8 BITS When the compare capture modules are programmed in the capture mode software timer or high speed out put mode an interrupt can be generated whenever the module executes its
186. Operation RLC A Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Rotate Accumulator Left The eight bits in the Accumulator are rotated one bit to the left Bit 7 is rotated into tbe bit O position No flags are affected The Accumulator holds the value OCSH 11000101B The instruction RL A leaves the Accumulator holding the value 8BH 10001011B with the carry unaffected 1 RL 1 lt 0 6 0 7 Rotate Accumulator Left through the Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit 0 position No other flags are affected The Accumulator holds the value 0C5H 11000101B and the carry is zero The instruction RLC A leaves the Accumulator holding the value 8BH 10001010B with the carry set 1 1 0011 0011 RLC An 1 lt 0 6 A0 lt C C A7 2 66 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET RR A Function Rotate Accumulator Right Description eight bits in the Accumulator are rotated one bit to the right Bit O is rotated into the bit 7 position No flags are affected Example Accumulator holds the value 5 11000101 The instruction RR A leaves the Accumulator holding the value OE2H
187. Overview MCS 5 Programmers Guide Instruction Set and the Hardware Description of the 80C51 in the Embedded Microcontrollers and Proces sors Handbook Order 270645 PIN DESCRIPTION The 8 5 pin out is the same as the 80 51 The only difference is the alternate function of pins P1 0 and P1 1 P1 0 is the external clock input for Timer 2 P1 1 is the Reload Capture Direction Control for Timer 2 DATA MEMORY The 8XC5X implements 256 bytes of on chip RAM The upper 128 bytes occupy a parallel address space to the Special Function Registers That means they have the same addresses but they are physically separate from SFR space When an instruction accesses an internal location above address 7FH the CPU knows whether the access is to the upper 128 bytes of RAM or the SFR space by the addressing mode used in the instruction Instructions that use direct addressing access SFR space For exam ple MOV data Direct Addressing accesses the SFR at location OAOH which is P2 In structions that use indirect addressing access the upper 128 bytes of RAM For example MOV RO data Indirect Addressing where RO contains OAOH accesses the data byte at ad dress OAOH rather than P2 whose address is Note that stack operations are examples of indirect ad dressing so the upper 128 bytes of data RAM are avail able as stack space SPECIAL FUNCTION REGISTERS A map of the on chip memory area called t
188. P2L In the Clock Out mode Timer 2 roll overs will not gen erate an interrupt This is similar to when Timer 2 is used as a baud rate generator It is possible to use Tim er 2 as a baud rate generator and a clock generator simultaneously Note however that the baud rate and Clock out frequencies cannot be determined indepen dently of one another since they both use the values in RCAP2H and RCAP2L 6 0 PROGRAMMABLE COUNTER ARRAY The Programmable Counter Array PCA consists of a 16 bit timer counter and five 16 bit compare capture modules as shown in Figure 15a The PCA timer coun ter serves as a common time base for the five modules and is the only timer which can service the PCA Its clock input can be programmed to count any one of the following signals oscillator frequency 12 oscillator frequency 4 Timer O overflow external input on ECI 1 2 Each compare capture module can be programmed in any one of the following modes rising and or falling edge capture software timer high speed output pulse width modulator Module 4 can also be programmed as a watchdog tim er When the compare capture modules are programmed in the capture mode software timer or high speed out put mode an interrupt can be generated when the mod ule executes its function All five modules plus the timer overflow share one interrupt vector more about this in the PCA Interrupt section intel 8XC51FX H
189. P2L are the Capture Re each of the 6 interrupt sources in the IP register The load registers for Timer 2 in 16 bit capture mode or 16 IPH register allows four priorities bit auto reload mode Serial Port Registers Registers SADDR and SA TIMER 2 DEN are used to define the Given and the Broadcast addresses for the Automatic Address Recognition fea Timer 2 is a 16 bit Timer Counter which can operate ture either as a timer or an event counter This is selectable by bit C T2 in the SFR T2CON Table 3 It has three 4 4 intel operating modes capture auto reload up or down counting and baud rate generator The modes are se lected by bits in T2CON as shown in Table 4 Timer 2 consists of two 8 bit registers TH2 and TL2 In the Timer function the TL2 register is incremented every machine cycle Thus one can think of it as count ing machine cycles Since a machine cycle consists of 12 oscillator periods the count rate is 1 of the oscillator frequency 8XC52 54 58 HARDWARE DESCRIPTION ternal input pin T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes 2 machine cycles 24 oscillator periods to recognize 1 to O transition the maximum count rate i
190. P2L as shown in this equation Oscillator Frequency Clock Out Frequency 17 65536 RCAP2H RCAP2L In the clock out mode Timer 2 roll overs will not gen erate an interrupt This is similar to when Timer 2 is used as a baud rate generator It is possible to use Tim er 2 as a baud rate generator and a clock generator simultaneously Note however that the baud rate and clock out frequencies can not be determined indepen dently from one another since they both use RCAP2H and RCAP2L UART UART the 8XC5X operates identically to the UART in the 80 51 except for the following enhance ments For a complete understanding of the 8XC5X UART please refer to the description in the 80C51 Hardware Description chapter in the Embedded Mi crocontrollers and Processors Handbook Framing Error Detection Framing Error Detection allows the serial port to check for valid stop bits in modes 1 2 or 3 A missing stop bit can be caused for example by noise on the serial lines or transmission by two CPUs simultaneously If a stop bit is missing a Framing Error bit FE is set The FE bit can be checked in software after each recep tion to detect communication errors Once set the FE bit must be cleared in software A valid stop bit will not clear FE The FE bit is located in SCON and shares the same bit address as SMO Control bit SMODO in the PCON reg ister location PCON 6 determines whether the SMO or FE bit is accessed
191. PnH and CCAPnL Notice however that a write to CCAPnL clears the ECOMn bit which temporarily dis ables the comparator function while these registers are being updated so an invalid match does not occur A write to CCAPnH sets the ECOMn bit and re enables the comparator For this reason user software should write to CCAPnL first then CCAPnH 6 5 High Speed Output Mode The High Speed Output HSO mode toggles a CEXn pin when a match occurs between the PCA timer and a pre loaded value in a module s compare registers For this mode the TOGn bit needs to be set in addition to the ECOMn and bits as seen in Figure 18 setting or clearing the pin in software the user can select whether the CEXn pin will change from a logical O to a logical 1 or vice versa The user also has the option of flagging an interrupt when a match event oc curs by setting the ECCFn bit The HSO mode is more accurate than toggling port pins in software because the toggle occurs before branching to an interrupt That is interrupt latency will not effect the accuracy of the output If the user does not change the compare registers in an interrupt routine the next toggle will occur when the PCA timer rolls over and matches the last compare value 6 6 Watchdog Timer Mode Watchdog Timer is a circuit that automatically in vokes a reset unless the system being watched sends CCAPnH CCAPnL PCA TIMER COUNTER regular hold off signals to the
192. RDWARE DESCRIPTION 6 6 A D in Power Down Table 11 PCA and PCA1 SFRs The A D on the 8XC51GB contains circuitry that lim its the amount of current dissipated during Power Down mode to leakage current only For this circuitry to function properly AVggr should be tied to during power down The Ipp specification in the data Sheet includes the current for the entire chip While AVreF is tied to during Power Down the voltage may be reduced to the minimum voltage as shown in the data sheet 7 0 PROGRAMMABLE COUNTER ARRAY Programmable Counter Arrays PCAs provide more timing capabilities with less CPU intervention than the standard timer counters Their advantages include re duced software overhead and improved accuracy For example a PCA can provide better resolution than Timers 0 1 and 2 because the clock rate can be three times faster A PCA can also perform many tasks that these hardware timers cannot i e measure phase differences between signals or generate PWMs The 8 51 has two PCAs called PCA and The following text and figures address only PCA but are also applicable to PCA1 with the following excep tions 1 Module 4 does not support the Watchdog Timer 2 the SFRs and bits have 1s added to their names see Table 11 3 Port 4 is the interface for PCAT P4 2 4 3 4 4 CIEX2 P4 5 1 2 4 6 C1EX3 P4 7 CIEX4 16 BITS EACH M
193. RSTAT AL Address Length see GMOD OD5H 0 5 Address Match Mask 0 1 Identifies which bits in ADRO 1 are don t care bits Setting a bit to 1 in AMSKO 1 identifies the corre sponding bit in ADDRO I as not to be examined when comparing addresses BAUD 94H Contains the programmable value for the baud rate generator for the GSC The baud rate will equal fosc BAUD 1 X 8 OE2H OF2H Byte Count Register Low 0 1 Contains the lower byte of the byte count Used during DMA transfers to identify to the DMA chan nels when the transfer is complete 1 Byte Count Register High 0 1 Contains the upper byte of the byte count BKOFF 0C4H Backoff Timer The backoff timer is an eight bit count down timer with a clock period equal to one slot time The backoff time is used in the CSMA CD collision resolution algorithm BOF Beginning of Frame flag A term commonly used when dealing with packetized data Signifies the beginning of a frame CRC Cyclic Redundancy Check An error checking routine that mathematically manipulates a value depen dent on the incoming data The purpose is to identify when a frame has been received in error CRCE CRC Error see RSTAT CSMA CD Stands for Carrier Sense Multiple Ac cess with Collision Detection CT CRC Type see GMOD DARLO 1 0C2H 0D2H Destination Address Reg ister Low 0 1 Contains the lo
194. Rotate Accumulator Left through the Carry Rotate Accumulator Right Rotate Accumulator Right through the Carry Swap nibbles within the Accumuiator Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM All mnemonics copyrighted Intel Corporation 1980 intel Mnemonic MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 10 8051 Instruction Set Summary Continued Description Byte Period DATA TRANSFER Continued MOM Ri direct Ri data DPTR data16 A A DPTR A A PC A Ri A DPTR direct direct A Rn Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16 bit constant Move Code byte relative to DPTR to Acc Move Code byte relative to PC to Acc Move External RAM 8 bit to Acc Move External RAM 16 bit addr to Acc Move Acc to External RAM 8 bit addr Move Acc to External RAM 16 bit addr Push direct byte onto stack Pop direct byte from Stack Exchange register with Accum
195. SCRIPTION Mode 1 10 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in SCON The baud rate in Mode 1 is vari able you can use either Timer 1 to generate baud rates and or Timer 2 to generate baud rates Figure 25 shows the mode 1 Data Frame 00 02 05 04 05 06 D7 Data Byte Stort Stop Bit 270897 27 Figure 25 1 Data Frame 2 11 bits transmitted through ceived through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On re ceive the 9th data bit goes into RB8 in SCON while the stop bit is ignored The validity of the stop bit can be checked with Framing Error Detection The baud rate is programmable to either 1 32 or 1 64 the oscilla tor frequency See Figure 26 01 02 05 04 os 06 07 pe Data Byte EM Stort Bit Stop Bit Ninth Data Bit 270897 28 Figure 26 Mode 2 Data Frame Mode 3 11 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 in all respects except
196. SFR at location which is P2 In structions that use indirect addressing access the upper 128 bytes of data RAM For example MOV GRO data where RO contains accesses the data byte at ad dress rather than P2 whose address is Note that stack operations are examples of indirect ad dressing so the upper 128 bytes of data RAM are avail able as stack space 3 0 SPECIAL FUNCTION REGISTERS A map of the on chip memory area called the SFR Special Function Register space is shown in Table 2 Note that not all of the addresses are occupied Unoc cupied addresses are not implemented on the chip Read accesses to these addresses will in general return random data and write accesses will have no effect intel 8XC51FX HARDWARE DESCRIPTION User software should not write 15 to these unimple The functions of the SFRs are outlined below More mented locations since they may be used in future information on the use of specific SFRs for each periph MCS 51 products to invoke new features In that case eral is included in the description of that peripheral the reset or inactive values of the new bits will always be 0 and their active values will be 1 Accumulator ACC is the Accumulator register The mnemonics for Accumulator Specific instructions however refer to the Accumulator simply as A Table 2 SFR Mapping and Reset Values CH 2
197. SMO and SM1 the SM2 bit for the multiprocessor modes the Receive Enable bit REN the 9th data bit for transmit and receive TB8 and and the serial port interrupt bits TI and RI OUTPUT WAVEFORM 270897 26 Figure 24 CCAPnH Varies Duty Cycle 6 33 intel 87C51GB HARDWARE DESCRIPTION Table 17 SCON Serial Port Control Register SCON Address 98H Reset Value 0000 00008 Bit Addressable SMo FE SM sm2 REN RI 7 6 5 4 3 Bit 2 1 0 SMOD0 0 1 Symbol Function FE Framing Error bit This bit is set by the receiver when an invalid stop bit is detected The FE bit is not cleared by valid frames but should be cleared by software The SMODO bit must be set to enable access to the FE bit Serial Port Mode Bit 0 SMODO must 0 to access SMO Serial Port Mode Bit 1 SMO SM1 Mode Description Baud Rate 0 0 0 shift register Fosc 12 0 1 1 8 bit UART variable 1 0 0 9 bit UART 64 or Fosc 32 1 1 3 9 bit UART variable Enables the Automatic Address Recognition feature in Modes 2 or 3 If SM2 1 then RI will not be set unless the received byte is a Given or Broadcast Address In Mode 1 if SM2 1 then RI will not be activated unless a valid stop bit was received and the received byte is a Given or Broadcast Address Mode 0 SM2 should be 0 Enables serial reception Set by software to enable reception Cleared by software to disable reception The 9th data bit tha
198. SPECIAL FUNCTION REGISTERS Table 1 contains a list of all the SFRs and their addresses Comparing Table 1 and Figure 5 shows that all of the SFRs that are byte and bit addressable are located on the first column of the diagram in Figure 5 Table 1 Accumulator B Register Program Status Word Stack Pointer Data Pointer 2 Bytes Low Byte High Byte Port 0 Port 1 Port 2 Port3 Interrupt Priority Control Interrupt Enable Control Timer Counter Mode Control Timer Counter Control Timer Counter 2 Control Timer Counter 0 High Byte Timer Counter 0 Low Byte Timer Counter 1 High Byte Timer Counter 1 Low Byte Timer Counter 2 High Byte Timer Counter 2 Low Byte T C 2 Capture Reg High Byte T C 2 Capture Reg Low Byte Serial Control Serial Data Buffer Power Control Bit addressable 8052 only intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET WHAT DO THE SFRs CONTAIN JUST AFTER POWER ON OR A RESET Table 2 lists the contents of each SFR after power on or a hardware reset Table 2 Contents of the SFRs after reset Register Value in Binary 00000000 00000000 00000000 000001 11 00000000 00000000 11111111 11111111 11111111 11111111 8051 XXX00000 8052 XX000000 8051 0 00000 8052 0X000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 indeterminate HMOS OXXXXXXX CHMOS 0XXX0000 X U
199. ST RST MOV PORT SRC OLD DATA NEW DATA SERIAL PORT SHIFT CLOCK MODE 0 270653 33 Figure 3 Port Operation the change requires a 0 10 1 transition in Ports 1 2 and 3 an additional pullup is turned on during S1P1 and S1P2 of the cycle in which the transition occurs This is done to increase the transition speed The extra pullup can source about 100 times the current that the normal pullup can The internal pullups are field effect transistors not linear resistors The pull up arrange ments are shown in Figure 4 The pullup consists of three pFETs Note that an n channel FET nFET is turned on when a logical 1 is applied to its gate and is turned off when a logical 0 is applied to its gate p channel FET pFET is the opposite it is on when its gate sees a O and off when its gate sees a 1 2 OSC PERIODS c FROM PORT LATCH pFET 1 in is the transistor that is turned on for 2 oscil lator periods after O to 1 transition in the port latch 1 at the port pin turns on pFET3 a weak pull up through the invertor This invertor and pFET form a latch which hold the 1 If the pin is emitting a 1 a negative glitch on the pin from some external source can turn off pFET3 causing the pin to go into a float state pFET2 is a very weak pullup which is on whenever the nFET is off in tradi tional CMOS style It s only about 110 the strength of pFET3 Its function is to restore a 1 to the pin in the
200. Strobe for External Memory Port 0 ADDR DATA INT BUS 270653 2 8XC51FX HARDWARE DESCRIPTION B Port 1 or Port 3 Bit ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL PULL UP ALTERNATE INPUT FUNCTION C Port 2 Bit Figure 4 for details of the internal pullup INTERNAL PULL UP Figure 2 C51FX Port Bit Latches and I O Buffers Also shown in Figure 2 is that if a P1 or P3 latch contains a 1 then the output level is controlled by the signal labeled alternate output function The actual pin level is always available to the pin s alternate input function if any Ports 1 2 and 3 have internal pullups Port 0 has open drain outputs Each 1 line can be independently used as an input an output Ports 0 and 2 may not be used as general purpose I O when being used as the AD DRESS DATA BUS To be used as an input the port bit latch must contain a 1 which turns off the output driver FET On Ports 1 2 and 3 the pin is pulled high by the internal pullup but can be pulled low by an external source Port 0 differs from the other ports in not having inter nal pullups The pullup FET in the PO output driver see Figure 2 is used only when the Port is emitting 1s during external memory accesses Otherwise the pullup FET is off Consequently PO lines that are being used as output port lines are open drain Writing a 1 to the bit latch leaves both output FETs off which f
201. T indicates that 7 consec utive ones were detected prior to the end flag but after data has been loaded into the receive FIFO AE may also be set The setting of this flag is controlled by the GSC RSTAT 7 OVR Overrun If set indicates that the receive FIFO was full and new shift register data was written into it AE and or CRCE may also be set The setting of this flag is controlled by the GSC and it is cleared by user software SLOTTM Slot Time Determines the length of the slot time used in CSMA CD A slot time equals SLOTTM X 1 baud rate A read of SLOTTM will give the value of the slot time timer but the value may be invalid as the timer is clocked asynchronously to the CPU Loading SLOTTM with 0 results in 256 bit times TCDCNT 0D4H Transmit Collision Detect Count Contains the number of collisions that have occurred if probabilistic CSMA CD is used The user software must clear this register before transmitting a new frame so that the GSC backoff hardware can accurately dis tinguish a new frame from a retransmit attempt In deterministic backoff mode TCDCNT is used to hold the maximum number of slots TFIFO 85H GSC Transmit FIFO TFIFO isa 3 byte buffer with an associated pointer that is automati cally updated for each write by user software Writing a byte to TFIFO loads the data into the next available location in the transmit FIFO Setting TEN clears the transmit FIFO so the transmit FIFO
202. T pin which has a Schmitt Trigger input reset is accomplished by holding the RESET pin low for at least two machine cycles 24 oscillator periods On the 8XCSIGB reset is asyn chronous to the CPU clock This means that the oscil lator does not have to be running for the I O pins to be in their reset condition However has to be within the specified operating conditions Once Reset has reached a high level the 8XC51GB may remain in its reset state for up to 5 machine cycles This is caused by the OFD circuitry While the RESET pin is low the port pins ALE and PSEN are weakly pulled high After RESET is pulled high it will take up to 5 machine cycles for ALE and PSEN to start clocking For this reason other devices can not be synchronized to the internal timings of the 8XCS1GB Driving the ALE and PSEN pins to O while reset is active could cause the device to go into an indetermi nate state The internal reset algorithm redefines most of the SFRs Refer to individual SFRs for their reset values The internal RAM is not affected by reset On power up the RAM content is indeterminate 13 1 Power On Reset For CHMOS devices when is turned on an auto matic reset can be obtained by connecting the RESET pin to Vss through a 1 uF capacitor The CHMOS devices do not require an external resistor like the HMOS devices because they have an internal pullup on the RESET pin Figure 35 shows this 270897 35
203. TI levels inverted and latched into the Interrupt Flags and IE1 at S5P2 of every machine cycle Similarly the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at S5P2 The values are not actually polled by the circuitry until the next machine cycle The Timer 0 and Timer 1 flags and TF1 are set at S5P2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the re quested service routine will be the next instruction to be executed The call itself takes two cycles Thus a mini mum of three complete machine cycles elapses between activation of an external interrupt request and the be ginning of execution of the service routine s first in struction Figure 25 shows interrupt response timing longer response time would result if the request is blocked by one of the 3 previously listed conditions If an interrupt of equal or higher priority level is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long
204. The Arbitration described in this section is not arbitration between two devices wanting to access a shared RAM but on chip arbitration between the two DMA channels on the 8XC152 The 8XC152 provides two DMA channels either of which may be called into operation at any time in re sponse to real time conditions in the application circuit Since DMA cycle always uses the 8X C152 s internal bus and there s only one internal bus only one DMA channel can be serviced during a single DMA cycle Executing program instructions also requires the inter bus so program execution will also be suspended in order for a DMA to take place ARBITRATION 2 270427 42 Figure 4 11 Internal Bus Usage 7 55 intel 83C152 HARDWARE DESCRIPTION Figure 4 11 shows the three tasks to which the internal bus of the 8XC152 can be dedicated In this figure Instruction Cycle means the complete execution of a single instruction whether it takes 1 2 or 4 machine cycles Cycle means the transfer of a single data byte from source to destination whether it takes 1 or 2 machine cycles Each time a DMA Cycle or an Instruc tion Cycle is executed on chip arbitration logic deter mines which type of cycle is to be executed next Note that when an instruction is executed if the in struction wrote to a DMA register defined in Figure 4 1 but excluding then another instruction is executed without further arbitration T
205. a Pointer is used to generate 16 bit addresses for external memory so being able to increment it in one 16 bit operation is a useful feature The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16 bit product into the concatenated B and Accumulator registers 1 10 5 51 ARCHITECTURAL OVERVIEW Table 2 List of the MCS 51 Arithmetic Instructions operation Execution ma mm Tei 40 ases X X ak ss wes lt ve gt X x x L Nc DPR Data Poimerony 2 DEG A oec eves me we i xlxlxl DV AB A Int A B 4 Decimal Adis The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8 bit quotient in the Accumulator and the 8 bit remainder in the B register Oddly enough DIV AB finds less use in arithmetic divide routines than in radix conversions and grammable shift operations An example of the use of DIV AB in a radix conversion will be given later In shift operations dividing a number by 2 shifts its n completes the shift in 4 us and leaves the B register holding the bits that were shifted out The DA A instruction is for BCD arithmetic opera tions In BCD arithmetic ADD and ADDC instruc tions should always be followed by a DA A operation to ensure that the result is
206. ables it Bit Function Global disable bit If EA 0 all Interrupts are disabled If EA 1 each Interrupt can be individually enabled or disabled by setting or clearing its enable bit PCA interrupt enable bit Timer 2 interrupt enable bit Serial Port interrupt enable bit Timer 1 interrupt enable bit External interrupt 1 enable bit Timer 0 interrupt enable bit External interrupt 0 enable bit Table 18 Interrupt Priority Registers Address 0B8H Reset Value X000 0000B Bit Addressable rpc Ps err Pro 7 6 5 4 3 2 1 0 Priority Bit 1 assigns high priority Priority Bit 0 assigns low priority Bit Function Not implemented reserved for future use PCA interrupt priority bit Timer 2 interrupt priority bit Serial Port interrupt priority bit Timer 1 interrupt priority bit External interrupt 1 priority bit Timer O interrupt priority bit External interrupt 0 priority bit User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate ntel If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are re ceived simultaneously
207. acti vate the read latch signal and others activate the read pin signal Those that read the latch are the Read Modify Write instructions The output drivers of Ports 0 and 2 switchable to an internal ADDRESS and ADDRESS DATA bus by an internal control signal for use in external memory ac cesses During external memory accesses the P2 SFR ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL PULL UP ALTERNATE INPUT FUNCTION 270897 3 B Port 1 3 4 or 5 Bit 270897 4 C Port 2 Bit See Figure 4 for details of the internal pullup Figure 2 8XC51GB Port Bit Latches and I O Buffers intel 87C51GB HARDWARE DESCRIPTION remains unchanged but the PO SFR gets 1s written to it If a P1 through P5 latch contains a 1 then the output level is controlled by the signal labeled alternate out put function The pin level is always available to the pin s alternate input function if any Ports 1 through 5 have internal pullups Port O has open drain outputs Each I O line can be independently used as an input or an output Ports 0 and 2 may not be used as general purpose I O when being used as the ADDRESS DATA BUS To be used as an input the port bit latch must contain a 1 which turns off the output driver FET On Ports 1 through 5 the pin is pulled high by the internal pullup but can be pulled low by an external source P1 P2 P4 and P5 reset to a low state While in reset these pins ca
208. ad strobe PSEN is normally activated twice per machine cycle as shown in Figure 16 A If an access to external Data Memory occurs as shown in Figure 16 B two PSENs are skipped because the address and data bus are being used for the Data Mem Ory access Note that a Data Memory bus cycle takes twice as much time as a Program Memory bus cycle Figure 16 shows the relative timing of the addresses being emitted at Ports 0 and 2 and of ALE and PSEN ALE is used to latch the low address byte from PO into the address latch ONE MACHINE CYCLE ONE MACHINE CYCLE Doc To S ALE PSEN RD 1 j WITHOUT MOVX 1 1 I I 1 P2PCHOUTX PCHOUT PCHOUT PCHOUT X PCHOUT X PCHOUT I I I 1 A 4 pci our VALID VALID pct our VALID VALIO 0 08 gt G5 our CYCLE CYCLE2 552221222 I PSEN RD I P2PCHOUTX PCHOUT X DPHOUTORP20UT PCHOUT X PCHOUT LLL B WITH A MOVX EET UN UE Lec L ADDR OUT VALID VALID t PCL OUT VALID 270251 16 Figure 16 Bus Cycles in 5 51 Devices Executing from External Program Memory ntel MCS 51 ARCHITECTURAL OVERVIEW When the CPU is executing from internal Program Memory PSEN is not activated and program address es are not emitted However ALE continues to be acti vated twice per machine cycle and so is availabl
209. addressing the instruction specifies a register which contains the address of the operand Both inter nal and external RAM can be indirectly addressed The address register for 8 bit addresses can be RO or of the selected register bank or the Stack Pointer The address register for 16 bit addresses can only be the 16 bit data pointer register DPTR REGISTER INSTRUCTIONS The register banks containing registers RO through R7 can be accessed by certain instructions which carry a 3 bit register specification within the opcode of the in struction Instructions that access the registers this way are code efficient since this mode eliminates an address byte When the instruction is executed one of the eight registers in the selected bank is accessed One of four banks is selected at execution time by the two bank select bits in the PSW REGISTER SPECIFIC INSTRUCTIONS Some instructions are specific to a certain register For example some instructions always operate on the Ac cumulator or Data Pointer etc so no address byte is needed to point to it The opcode itself does that In structions that refer to the Accumlator as A assemble as accumulator specific opcodes IMMEDIATE CONSTANTS The value of a constant can follow the opcode in Pro gram Memory For example A 100 loads the Accumulator with the decimal number 100 The same number could be specified in hex digits as 64H INDEXED ADDRESSING Only
210. ag is one six is added to the Accumulator producing the proper BCD digit in the low order nibble This internal addition would set the carry flag if a carry out of the low order four bit field propagat ed through all high order bits but it would not clear the carry flag otherwise If the carry flag is now set or if the four high order bits now exceed nine 1010xxxx 111xxxx these high order bits are incremented by six producing the proper BCD digit in the high order nibble Again this would set the carry flag if there was a carry out of the high order bits but wouldn t clear the carry The carry flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected of this occurs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 06H 60H or 66H to the Accumulator depending on initial Accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the Accumulator to BCD nota tion nor does apply to decimal subtraction 2 39 intel Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET The Accumulator holds the value 56H 01010110B representing the packed BCD digits of the decimal number 56 Register 3 contains the value 67H 01100111B representing the packed BCD digits of the decimal number 67 The carry
211. al to XTAL1 and leave XTAL2 floating Refer to the External Clock Source diagram This is an important difference from the HMOS parts With HMOS the external clock source is applied to XTAL2 and XTALI is grounded See Figure 40 External Oscillator Signal CMOS Gate There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide by two flip flop However minimum and maximum high and low times specified in the data sheets must be observed Refer to the External Clock Specifications for this information An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback ca pacitance Once the external signal meets the and specifications the capacitance will not exceed 20 pF 18 0 CPU TIMING The internal clock generator defines the sequence of states that make up a machine cycle A machine cycle consists of 6 states numbered S1 through S6 Each state time lasts for two oscillator periods Thus a ma chine cycle takes 12 oscillator periods or 1 us if the oscillator frequency is 12 MHz Each state is then di vided into a Phase 1 and Phase 2 half Rise and fall times are dependent on the external load ing that each pin must drive They are approximately 10 ns measured between 0 8 and 2 0V Propagation delays are different for different pin
212. also in BCD Note that DA A will not convert a binary number to BCD The DA A operation produces a meaningful result only as the second step in the addition of two BCD bytes bits to the right Using DIV AB to perform the division Table 3 List of the MCS 51 Logical Instructions iL Dir ind Reg mm Time as ANL lt byte gt A bte ye ANDA X 1 ANC bye daa lt byte gt bye AND X 2 be A lt byie gt ORA x T bye daa lt byte gt bye OR d X 2 lt byte gt X XAL bye da lt byte gt bye XOR ema X A Accumulator only CPL A Accumulator only Rotate ACC Left 1 bit Accumulator only Rotate Right 1 bit Accumulator only RRC A Rotate Right through Carry Accumulator only RLC A Rotate Left through Carry Accumulator only Swap Nbolesin A Accumulator only intel Logical Instructions Table 3 shows the list of MCS 51 logical instructions The instructions that perform Boolean operations AND OR Exclusive OR NOT on bytes perform the operation on a bit by bit basis That is if the Accumu lator contains 001101018 and lt byte gt contains 01010011B then ANL lt byte gt will leave the Accumulator holding 00010001 The addressing modes that can be used to access the lt byte gt
213. amble length protocol select and enables the external clocking of the transmit data GMOD 0 PR Protocol If set SDLC protocols with NRZI encoding zero bit insertion and SDLC flags are used If cleared CSMA CD link access with Manches ter encoding is used GMOD 1 2 PLO 1 Preamble length PL1 PLO LENGTH BITS 0 0 0 0 1 8 1 0 32 1 1 64 The length includes the two bit Begin Of frame flag CSMA CD but does not include the SDLC flag In SDLC mode the BOF is SDLC flag otherwise it is two consecutive ones Zero length is not compatible in CSMA CD mode GMOD 3 CRC Type If set 32 bit AUTODIN II 32 is used If cleared 16 bit CRC CCITT is used GMOD 4 AL Address Length If set 16 bit ad dressing is used If cleared 8 bit addressing is used In 8 bit mode a match with any of the 4 address registers will allow that frame to be accepted ADRO ADRI ADR2 ADR3 Don t Care bits may be masked in ADRO and ADR1 with AMSKO and AMSK1 In 16 bit mode addresses are matched against ADRI ADRO or ADR3 ADR2 Again Don t Care bits in ADR1 ADRO can be masked in AM SK1 AMSKO A received address of all ones will al ways be recognized in any mode GMOD 5 6 1 Mode Select Two test modes an optional alternate backoff mode or normal back off can be enabled with these two bits Mode Normal Raw Transmit Raw Receive Alternate Backoff
214. an 8052 like it has four When Timer O is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate generator or in fact in any application not requiring an interrupt intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 INTERRUPT 270252 10 Figure 9 Timer Counter 1 Mode 2 8 Bit Auto Reload 1 121osc INTERRUPT CONTROL INTERRUPT 270252 11 Figure 10 Timer Counter 0 Mode 3 Two 8 Bit Counters Timer 2 Table 2 Timer 2 Operating Modes s Made 16 bit Auto Reload 16 bit Capture Baud Rate Generator off Timer 2 is a 16 bit Timer Counter which is present only in the 8052 Like Timers 0 and 1 can operate either as a timer or as an event counter This is selected by bit C T2 in the Special Function Register 2 Figure 11 It has three operating modes capture auto load and baud rate generator which se lected by bits in 2 as shown in Table 2 3 12 intel MSB HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 LSB Tre amp x2 exene me Symbol TF2 Position T2CON 7 Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 EXF2 T2CON 6 Timer 2 external flag set when either a capture or rel
215. an be used to page the external data mem ory In either case the low byte of the address is time multi plexed with the data byte on Port 0 The ADDRESS DATA signal drives both FETs in the Port 0 output buffers Thus in external bus mode the Port 0 pins are not open drain outputs and do not require external pullups The ALE Address Latch Enable signal should be used to capture the address byte into an ex ternal latch The address byte is valid at the negative transition of ALE Then in a write cycle the data byte to be written appears on Port O just before WR is acti vated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at Port 0 just before the read strobe RD is deactivated During any access to external memory the CPU writes OFFH to the Port 0 latch the Special Function Regis ter thus obliterating the information in the Port O SFR Also a MOV PO instruction must not take place during external memory accesses If the user writes to Port 0 during an external memory fetch the incoming code byte is corrupted Therefore do not write to Port O if external program memory is used External Program Memory is accessed under two con ditions 1 Whenever signal EA is high or 2 Whenever the program counter PC contains an ad dress greater than 1FFFH 8K This requires that the ROMless versions have EA wired to Vss to enable the lower 8K of program bytes to be fetched from e
216. an clear the RI or TI flag This is because the LSC is serviced according to the status of and TI whether or not the DMA channels are being used for the transferring of data The GSC does not use RFNE or flags when using the channels so these do not need to be disabled When using the DMA channels to service the LSC it is recommended that the interrupts RI and TI be disabled If the dec remented BCRn is O000H on chip hardware then clears the GO bit and sets the DONE bit The DONE bit flags an interrupt 4 1 4 EXTERNAL DEMAND MODE In External Demand Mode the DMA is initiated by one of the External Interrupt pins provided the GO bit is set INTO initiates a Channel 0 DMA and initiates a Channel 1 DMA If the external interrupt is configured to be transition activated then each 1 to 0 transition at the interrupt pin sets the corresponding external interrupt flag and generates one DMA Cycle Then BCRn is decrement ed No more DMA Cycles take place until another 1 to 0 transition is seen at the external interrupt pin If the decremented BCRn 0000H on chip hardware clears the GO bit and sets the DONE bit If the exter nal interrupt is enabled it will be serviced If the external interrupt is configured to be level acti vated then DMA Cycles commence when the interrupt pin is pulled low and continue for as long as the pin is held low and BCRn is not 0000H If BCRn reaches 0 while the interrupt pin
217. and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is variable Mode 2 11 bits are transmitted through TXD or ceived through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 Refer to Figure 22 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in SCON while the stop bit is ignored The validity of the stop bit can be checked with Framing Error Detec tion The baud rate is programmable to either 15 or 1 64 the oscillator frequency had CP CP C C CC CP CO DATA BYTE STOP NINTH DATA Modes 2 end 3 only 270653 19 Figure 22 Data Frame Modes 1 2 and 3 ntel 8XC51FX HARDWARE DESCRIPTION Mode 3 11 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 in all respects except the baud rate The baud rate in Mode 3 is vari able all four modes transmission is initiated by any in struction that uses SBUF as a destination register Re ception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 For more detailed informatio
218. and an up down timer counter As this product is CHMOS it has two software selectable reduced power modes Idle Mode and Power Down Mode Being a member of the MCS 51 family the 8X C52 54 58 is optimized for control applications This document presents a comprehensive description of the on chip hardware features of the 8 52 54 58 as they differ from the 80C51BH It begins by describing how the I O functions are different and then discusses each of the peripherals as follows 256 Bytes On Chip RAM Special Function Registers SFR Timer 2 Capture Timer Counter Up Down Timer Counter Baud Rate Generator Full Duplex Programmable Serial Interface with Framing Error Detection Automatic Address Recognition 6 Interrupt Sources Enhanced Power Down Mode Power Off Flag ONCE Mode The 8XC52 54 58 uses the standard 8051 instruction set and is pin for pin compatible with the existing MCS 51 family of products Table 1 sumrnarizes the product names and memory differences of the various 8XC52 54 58 products currently available Through out this document the products will generally be re ferred to as the 8X CSX Table 1 8XC52 54 58 Microcontrollers ROM EPROM ROMIess ROM EPROM Device Version Version Bytes Bytes 80C52 87052 8K 16K 32K 80C58 87C58 For a description of the features that are the same as the 80C51 the reader should refer to the MCS 51 Ar chitectural
219. and auxiliary carry flags are set respectively if there is a carry out from bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occured OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or imme diate Example Accumulator holds 11000011B and register 0 holds 10101010B with the carry flag set The instruction ADDC 0 will leave 6EH 01101110B in the Accumulator with AC cleared and both the Carry flag and OV set to 2 30 intel ADDC A Rn Bytes Cycles Encoding Operation ADDC A direct Bytes Cycles Encoding Operation ADDC A GRi Bytes Cycles Encoding Operation ADDC A data Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 0011 ADDC 2 1 ADDC O direct 1 1 ADDC lt R 2 1 0011 immediate data ADDC data 2 31 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET AJMP 11 Function Absolute Ju
220. and if the instruction in progress is RETI I 12 OSC PERIODS or write to or the additional wait time cannot be more than 5 cycles a maximum of one or more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL Thus in a single interrupt system the response time is always more than 3 cycles and less than 9 cycles 9 0 RESET The reset input is the RST pin which has a Schmitt Trigger input A reset is accomplished by holding the RST pin high for at least two machine cycles 24 oscil lator periods while the oscillator is running The CPU responds by generating an internal reset with the tim ing shown in Figure 26 The external reset signal is asynchronous to the internal clock The RST pin is sampled during State 5 Phase 2 of every machine cycle ALE and PSEN will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin that is for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin The port pins are driven to their reset state as soon as a valid high is detected on the RST pin regardless of whether the clock is running 55 56 1 52 55 54 ss 56 1 52 55 se 55 56 1 52 53 54 RST Y Y Y Y Y Y s Ye Yep Yep a 11 OSC PERIODS 19 OSC PERIODS
221. ansition is detected the divide by 16 counter is imme diately reset and 1FFH is written into the input shift register Resetting the divide by 16 counter aligns its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16155 At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not O the receive circuits are reset and the unit goes back to look ing for another 1 to 0 transition This is to provide re jection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit regis ter it flags the RX Control block to do one last shift load SBUF and and set RI The signal to load SBUF and RBS and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 0 and 2 Either SM2 0 or the received stop bit 1 either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes i
222. are directed to external memory On the 83C51FA or 87C51FA if the EA pin is connected to Vcc then program fetches to addresses O000H through 1FFFH are directed to internal ROM and fetches to addresses 2000H through FFFFH are to external memory On the 83C51FB or 87C51FB if EA is connected to VCC program fetches to addresses 0000H through 3FFFH are directed to internal ROM and fetches to addresses 4000H through FFFFH are to external mem ory On the 83 51 or 87C51FC if EA is connected to program fetches to addresses 0000H through are directed to internal ROM or EPROM and fetches to addresses 8000H through FFFFH are to ex ternal memory 2 2 Data Memory The C51FX implements 256 bytes of on chip data RAM The upper 128 bytes occupy a parallel address space to the Special Function Registers That means they have the same addresses but are physically sepa rate from SFR space When an instruction accesses an internal location above address 7FH the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction Instruc tions that use direct addressing access SFR space For example MOV OAOH data O PO 18 RAM ADDR REGISTER TIMING INSTRUCTION REGISTER 1 0 1 7 7 8XC51FX HARDWARE DESCRIPTION 2 0 2 7 2 DRIVERS Figure 1 8XC51FX Functional Block Diagram accesses the
223. are not impiemented on the chip Read accesses to these addresses will in general return random data and write accesses will have no effect User software should not write Is to these unimple mented locations since they may be used in future MCS 51 products to invoke new features In that case the reset or inactive values of the new bits will always be 0 and their active values will be 1 The functions of the SFRs are outlined below ACCUMULATOR ACC is the Accumulator register The mnemonics for Accumulator Specific instructions however refer to the Accumulator simply as A B REGISTER The B register is used during multiply and divide oper ations For other instructions it can be treated as anoth er scratch pad register PROGRAM STATUS WORD The PSW register contains program status information as detailed in Figure 3 STACK POINTER The Stack Pointer Register is 8 bits wide It is incre mented before data is stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the Stack Pointer is initialized to 07H after a reset This causes the stack to begin at location 08H DATA POINTER The Data Pointer DPTR consists of a high byte DPH and a low byte DPL Its intended function is 3 5 to hold a 16 bit address It may be manipulated as a 16 bit register or as two independent 8 bit registers PORTS 0 TO 3 P1 P2 and P3 are the SFR latches of Ports 0 1 2 and 3 respect
224. ared Alternate Cycle Transfers are used if DMA is in the Block Mode or Local Serial channel GSC inter rupts are used to initiate a transfer if in Demand Mode DCON 3 DM DMA Channel Mode When set Demand Mode is used and when cleared Block Mode is used DCON 4 ISA Increment Source Address When set the source address registers are automatically incre mented during each transfer When cleared the source address registers are not incremented DCON 5 SAS Source Address Space When set the source of data for the DMA transfers is internal data memory if autoincrement is also set If autoincrement is not set but SAS is then the source for data will be one of the Special Function Registers When SAS is cleared the source for data is external data memory DCON 6 IDA Increment Destination Address Space When set destination address registers are in cremented once after each byte is transferred When cleared the destination address registers are not auto matically incremented intel 83C152 HARDWARE DESCRIPTION DCON 7 DAS Destination Address Space When set destination of data to be transferred is internal data memory if autoincrement mode is also set If autoincre ment is not set the destinationwill be one of the Special Function Registers When DAS is cleared then the des tination is external data memory DCR Deterministic Resolution see MYSLOT DEN An alternate function of one of the por
225. ary Carry flag For BCD Operations Flag O Available to the user for general purposes Register bank select bit 1 Register bank select bit 0 RS1 RSO 0 0 0 1 1 0 1 1 Overflow flag User definable flag Bank 0 Bank 1 Bank 2 Bank 3 Working Register Bank and Address 00H 07H 08H 0FH 10H 17H 18H 1FH Parity flag Set cleared by hardware each instruction cycle to indicate an odd even number of bits in the Accumulator i e even parity B Register The B register is used during multiply and divide operations For other instructions it can be treat ed as another scratch pad register Stack Pointer The Stack Pointer Register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions The stack may reside anywhere in on chip RAM On reset the Stack Pointer is initialized to 07H causing the stack to begin at loca tion 08H Data Pointer The Data Pointer DPTR consists of a high byte DPH and a low byte DPL Its intended function is to hold a 16 bit address but it may be ma nipulated as a 16 bit register or as two independent 8 bit registers Program Status Word The PSW register contains pro gram status information as detailed in Table 3 Ports 0 to 3 Registers PO P1 P2 and P3 are the SFR latches of Port 0 Port 1 Port 2 and Port 3 respective ly Timer Registers Register pairs THO TLO TL 1 and 2 TL2 the 16 bit count r
226. ates can be determined by Timer 1 or by Timer 2 or by both one for transmit and the other for re ceive intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Using Timer 1 to Generate Baud Rates mode high nibble of TMOD 0010B In that case the baud rate is given by the formula When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Modes1 3 25 Oscillator Frequency 1 overflow rate and the value of SMOD as fol Baud Rate 7 712 256 Modes 1 3 5 One can achieve very low baud rates with Timer 1 by Baud Rate X Timer 1 Overflow Rate leaving the Timer 1 interrupt enabled and configuring the Timer to run as a 16 bit timer high nibble of TMOD 0001B and using the Timer 1 interrupt to The Timer 1 interrupt should be disabled in this appli do a 16 bit software reload cation The Timer itself can be configured for either timer or counter operation and in any of its 3 Figure 15 lists various commonly used baud rates and running modes In the most typical applications it is how they can be obtained from Timer 1 configured for timer operation in the auto reload Baud Rate Reloa ENGEL Mode 0 Max 1 MHZ 12 MHZ X Mode 2 Max 375K 12 MHZ 1 x X Modes 1 3 62 5K 12 MHZ 1 0 2 19 2K 11 059 MHZ 1 0 2 9 6K 11 059 MHZ 0 0 2 4 8K 11 059 MHZ 0 0 2 2 4K 11 059 MHZ 0 0 2 1 2K 11 059 MHZ 0 0 2 13
227. ations 7EH and 7FH holding respective ly and 41H INC A Bytes 1 Cycles Encoding Operation INC A A 1 2 44 intel INC INC INC Rn Bytes Cycles Encoding Operation direct Bytes Cycles Encoding Operation Ri Bytes Cycles Encoding Operation INC DPTR Function Description Example Bytes Cycles Encoding Operation 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 INC lt Rn 1 2 1 INC direct lt direct 1 direct address 1 1 INC Ri Ri 1 Increment Data Pointer Increment the 16 bit data pointer by 1 16 bit increment modulo 216 is performed an overflow of the low order byte of the data pointer DPL from OFFH to 00H will increment the high order byte DPH No flags are affected This is the only 16 bit register which can be incremented Registers DPH and DPL contain 12H and OFEH respectively The instruction sequence INC DPIR INC DPTR INC DPTR will change DPH and DPL to 13H and 01H 1 2 INC DPTR DPTR 1 2 45 intel MCSe 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JB bit rel Function Jump if Bit set Description the indicated bit is one jump to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte t
228. ations of lock bits may produce indetermi nate results and should not be used 16 0 ONCE MODE The ONCE ON Circuit Emulation mode facilitates testing and debugging of systems using the 8XC51GB without having to remove the device from the circuit The ONCE mode is invoked by 1 Pulling ALE low while the device is in reset and PSEN is high 2 Holding ALE low as RST is deactivated While the device is in ONCE mode the Port 0 pins go into a float state and the other port pins ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored after a valid reset is ap plied 17 0 ON CHIP OSCILLATOR The on chip oscillator for the CHMOS devices consists of a single stage linear inverter intended for use as a intel 87C51GB HARDWARE DESCRIPTION crystal controlled positive reactance oscillator In this application the crystal is operating in its fundamental response mode as an inductive reactance in parallel res onance with capacitance external to the crystal Figure 37 shows the on chip oscillator circuitry The oscillator on the CHMOS devices can be turned off under software control by settmg the PD bit in the PCON register Figure 38 The feedback resistor Rf shown in the figure consists of parallel and p channel 5 controlled by the PD bit such that Rr is opened when PD
229. be the last instruction executed before going into the Idle mode In the Idle mode the internal clock signal is gated off to the CPU but not to the Interrupt Timer and Serial Port functions The PCA and PCA1 timers can be programmed either to pause or continue operat ing during Idle with the CIIDL bit in CIMOD The CPU status is preserved in its entirety the Stack Pointer Program Counter Program Status Word Accumulator and all other registers maintain their data during Idle The port pins hold the logical states they had at the time Idle was activated ALE and PSEN hold at logic high levels Refer to Table 27 Table 27 Status of the External Pins during idie Mode Program Ports esos PSE to re rea Internal Data Data Data Data External Float Data Address Data There are two ways to terminate the Idle Mode Activa tion of any enabled interrupt will cause the IDL bit to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle The flag bits GFO and GF1 in can be used to give an indication if an interrupt occurred during nor mal operation or during Idle For example an instruc tion that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bi
230. bit time to get from the GRXD pin to the bit decoder The bit decoder strips off the preamble BOF bits and the first bit after BOF is shift ed into a serial strip buffer The length of the strip buffer is equal to the number of bits in the selected CRC It is within this buffer that address recognition takes place If the address is recognized as one for which reception should proceed then when the first address bit exits the strip buffer it is shifted into an 8 bit shift register When the shift register is full its content is transferred to RFIFO That is the event that deter mines whether a collision sets RCABT or not GSC Transmitting If the GSC is in the process of transmitting a frame at the time the collision is detected it will in every case execute its jam backoff procedure Its reponse beyond that depends on whether the first byte of the frame has been transferred from TFIFO to the output shift regis ter yet or not That transfer takes place at the beginning of the first bit of the BOF that is 2 bit times before the end of the preamble BOF sequence If the transfer from TFIFO hasn t occurred yet the GSC hardware will try again to gain access to the line after its backoff time has expired Up to 8 automatic restarts can be attempted If the 8th restart is interrupt ed by yet another collision the transmitter is disabled TEN 0 and the Transmit Error Interrupt flag TCDT is set If the transfer from TFIFO occurs befo
231. byte is not affected No other register or flag is affected This is by far the most flexible operation Fifteen combinations of source and destination addressing modes are allowed Internal RAM location 30H holds 40H The value of RAM location 40H is 10H The data present at input port 1 is 11001010B MOV MOV MOV MOV MOV MOV R0 430H 0 lt 30H A GRO A lt 40H RLA Rl lt 40H lt 10H R1 P1 40H lt P2 P1 P2 leaves the value 30H in register 0 40H in both the Accumulator and register 1 10H in register B and OCAH 11001010B both in RAM location 40H and output on port 2 2 1 0101 direct address MOV direct MOV A ACC is not a valid instruction 2 52 intel MOV A Ri Bytes Cycles Encoding Operation MOV A data Bytes Cycles Encoding Operation MOV Rn A Bytes Cycles Encoding Operation MOV Rn direct Bytes Cycles Encoding Operation Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 MOV A Ri 2 1 0111 0100 immediate data MOV data 1 1 MOV Rn A 2 2 MOV Rn direct 2 1 MOV Rn lt data immediate data 2 53 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOV direct A Bytes 2 Cycles
232. cation for the LSC SCON 098H 7 6 5 4 3 2 1 0 smo sm2 REN TI RI SCON 0 Receive Interrupt flag SCON 1 TI Transmit Interrupt flag SCON 2 8 Receive Bit 8 contains the ninth bit that was received in Modes 2 and 3 or the stop bit in Mode 1 if SM20 Not used in Mode 0 SCON 3 TB8 Transmit Bit 8 the ninth bit to be transmitted in Modes 2 and 3 SCON 4 REN Receiver Enable enables reception for the LSC 5 SM2 Enables the multiprocessor communi cation feature in Modes 2 and 3 for the LSC SCON 6 SM1 LSC mode specifier 7 SM2 LSC mode specifier SDLC Stands for Synchronous Data Link Communi cation and is a protocol developed by IBM SLOTTM Determines the length of the slot time in CSMA CD SP 081H Stack Pointer an eight bit pointer register used during a PUSH POP CALL RET or RETI TCDCNT 0D4H Contains the number of collisions in the current frame if using probabilistic CSMA CD and contains the maximum number of slots in the de terministic mode TCDT Transmit Collision Detect see TSTAT TCON 088H 7 6 5 4 3 2 1 0 TR TRO w1 wo 0 ITO Interrupt 0 mode control bit TCON 1 External interrupt 0 edge TCON 2 IT1 Interrupt 1 mode control bit TCON 3 IE1 External interrupt 1 edge flag TCONA TRO Timer 0 run control bit CON 5
233. cept That It Holds The Strong Pullup On While Emitting 1s That Are Address Bits See Text Accessing External Memory In the CHMOS versions the pullup consists of three pFETs It should be noted that an n channel FET nFET is turned on when a logical 1 is applied to its gate and is turned off when a logical 0 is applied to its gate A p channel FET pFET is the opposite it is on when its gate sees a O and off when its gate sees a 1 Figure 5 is the transistor that is turned on for 2 oscillator periods after O to 1 transition in the port latch While it s on it turns on pFET3 a weak pull up through the inverter This inverter and pFET form a latch which hold the 1 Note that if the pin is emitting a 1 a negative glitch on the pin from some external source can turn off pFET3 causing the pin to go into a float state pFET2 is a very weak pullup which is on whenever the nFET is off in traditional CMOS style It s only about the strength of pFET3 Its function is to restore a to the pin in the event the pin had a 1 and lost it to a glitch Port Loading and Interfacing The output buffers of Ports 1 2 and 3 can each drive 4 LS TTL inputs These ports on HMOS versions can be driven in a normal manner by any TTL or NMOS cir cuit Both HMOS and CHMOS pins can be driven by open collector and open drain outputs but note that 0 to 1 transitions will not be fast In the HMOS device if the pin is driven b
234. chine cycle consists of 12 oscillator periods the count rate is 1 12 of the oscilla tor frequency In the Counter function the register is incremented in response to a 1 10 0 transition at its corresponding ex ternal input 0 or T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes 2 machine cycles 24 oscillator periods to recognize a 1 10 0 transition the maximum count rate is of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle In addition to the Timer or Counter selection Timer 0 and Timer 1 have four operating modes from which to select Modes 0 3 Timer 2 has three modes of opera tion Capture Auto Reload and Baud Rate Generator 5 1 Timer 0 and Timer 1 The Timer or Counter function is selected by control bits C T in the Special Function Register TMOD Ta ble 5 These two Timer Counters have four operating modes which are selected by bit pairs M1 MO in TMOD Modes 0 1 and 2 the same for both Tim er Counters Mode 3 operation is different f
235. cleared and change Port 1 to 39H 00111001B 2 55 intel C bit Cycles Encoding Operation MOV bit C Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 C lt tit 2 2 1001 bit address MOV bit MOV OPTR data16 Function Description Example Bytes Cycles Encoding Operation Load Data Pointer with a 16 bit constant The Data Pointer is loaded with the 16 bit constant indicated The 16 bit constant is loaded into the second and third bytes of the instruction The second byte DPH is the high order byte while the third byte DPL hoids the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once The instruction MOV DPTR 1234H will load the value 1234H into the Data Pointer DPH will hold 12H and DPL will hold 34H 3 2 0000 immed data15 8 immed data7 0 MOV PTR lt datajs 0 DPH DPL lt f data 5 3 O data7 9 2 56 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET A A lt base reg gt Function Move Code byte Description The instructions load the Accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned eight bit Accumu lator contents and the contents of a sixteen bit base register which may be either the Data Pointer or the
236. cles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 3 2 0000 JBC PO PO 3 IF bit 1 THEN bit 0 PO rel Jump if Carry is set If the carry flag is set branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the twice No flags are affected The carry flag is cleared The instruction sequence JC LABELI CPL C JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 2 2 JC PO PO 2 IF O 1 THEN PO 2 47 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JMP A DPTR Function Description Example Bytes Encoding Operation Jump indirect Add the eight bit unsigned contents of the Accumulator with the sixteen bit data pointer and load the resulting sum to the program counter This will be the address for subsequent instruc tion fetches Sixteen bit addition is performed modulo 216 a carry out from the low order eight bits propagates through the higher order bits Neither the Accumulator nor the Data Pointer is altered No flags are affected An even number from to 6 is in the Accumulator The following sequence o
237. col Bits 7 6 5 represent the value of the sequence the sta tion expects when the next transfer occurs for that sta tion There is no information following the control field when the supervisory format is used In the unnumbered format bits 1 0 1 1 bits 7 6 5 3 2 notice bit 4 is missing indicate commands from the primary to secondary stations or requests of second ary stations to the primary Identification in information field XID 1 1 0 O Test pattern in information field TEST The standard responses are BITS 7 6 5 3 2 Command 0 0 0 Unnumbered information UI 0 0 0 0 1 Request for initialization RIM 0 0 0 1 1 Station in disconnected mode DM 1 000 1 Invalid frame received 0 1 1 0 0 Unnumbered acknowledgement UA 1 1 1 1 1 Signalloss of input BCN 1 1 0 0 1 Function descriptor in information field CFGR 0 1 0 0 O Station wants to disconnect RD 1 0 1 1 1 Identification in information field XID 1 1 1 O 0 Test pattern in information field TEST 7 30 intel 83C152 HARDWARE DESCRIPTION In an unnumbered frame information of variable length may follow the control field if UI is used or information of fixed length may follow if 5 used As stated earlier the user software is responsible for the proper management of the control field This portion of the frame is passed to from the GSC FIFOs as basic informational type data INFO This is the information fiel
238. comes out exclusive NOR ed XNOR with one of the key bytes Therefore to read the ROM code the user has to know the 64 key bytes in their proper sequence Unprogrammed bytes have the value OFFH So if the Encryption Array is left unprogrammed all the key bytes have the value OFFH Since any code byte XNORed with OFFH leaves the byte unchanged leav ing the Encryption Array unprogrammed in effect by passes the encryption feature PROGRAM LOCK BITS Also included in the Program Lock scheme are three Lock Bits which can be programmed to disable certain functions as shown in Table 29 obtain maximum security of the on board program and data all 3 Lock Bits and the Encyption Array must be programmed Erasing the EPROM also erases the Encryption Array and the Lock Bits returning the part to full functionali ty 6 52 Table 29 EPROM OTP Lock Bits Program Lock Bits LB1 LB2 LB3 No Program Lock features enabled Code Verify will still be encrypted by the Encryption Array MOVC instructions executed from external program memory are disabled from fetching code bytes from Logic Enabled internal memory A is sampled and latched on reset and further programming of EPROM is disabled as above but Verify is also disabled option available on EPROM only Same as above and all external program execution is inhibited and internal cannot be read externally NOTE All other combin
239. cost sensitive applications When a ceramic resona tor is used C1 and C2 are normally selected as higher values typically 47 pF The manufacturer of the ceram ic resonator should be consulted for recommendations on the values of these capacitors A more in depth discussion of crystal specifications ce ramic resonators and the selection of values for C1 and C2 can be found in Application Note AP 155 tors for Microcontrollers in the Embedded Applica tions handbook To drive the CHMOS parts with an external clock source apply the external clock signal to and leave XTAL2 floating as shown in Figure 31 This is an important difference from the HMOS parts With HMOS the external clock source is applied to XTAL2 and XTAL is grounded An external oscillator may encounter as much as a 100 pF load at when it starts up This is due to interaction between the amplifier and its feedback ca pacitance Once the external signal meets the and specifications the capacitance will not exceed 20 pF 270653 26 Figure 29 On Chip Oscillator Circuitry 5 42 8xC51FX XTAL2 OSCILLATOR SIGNAL CMOS GATE Vss Figure 31 Driving the CHMOS Parts with an External Clock Source 15 0 CPU TIMING The internal clock generator defines the sequence of states that make up a machine cycle machine cycle consists of 6 states numbered S1 through S6 Each state time lasts for two oscillator per
240. counter Figure 24 Interrupt Sources intel 8 1 External Interrupts External Interrupts INTO and INT can each be either level activated or transition activated depending on bits ITO and in register TCON If ITx 0 exter nal interrupt x is triggered by a detected low at the pin If ITx 1 external interrupt x is negative edge triggered The flags that actually generate these interrupts are bits IEO and IE1 in TCON These flags are cleared by hardware when the service routine is vectored to only if the interrupt was transition activat ed If the interrupt was level activated then the exter nal requesting source is what controls the request flag rather than the on chip hardware Since the external interrupt pins are sampled once each machine cycle an input high or low should hold for at least 12 oscillator periods to ensure sampling If the external interrupt is transition activated the external source has to hold the request pin high for at least one cycle and then hold it low for at least one cycle to ensure that the transition is seen so that interrupt re quest flag IEx will be set IEx will be automatically cleared by the CPU when the service routine is called If external interrupt INTO INTI is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt serv ice routine is co
241. ction with preamble the addresses 00 00 and 55 55 H should not be assigned to any C152 as the preamble following the idle fill flags will be interpreted as an address intel 3 4 User Defined Protocols The explanation on the implementation of user defined protocols would go beyond the scope of this manual but examining Table 3 1 should give the reader a con solidated list of most of the possibilities In this manual any deviation from the documents that cover the imple mentation of CSMA CD SDLC are considered user defined protocols Examples of this would be the use of SDLC with the 32 bit CRC selected with hardware based acknowledge 83C152 HARDWARE DESCRIPTION 3 5 Using the GSC 3 5 1 LINE DISCIPLINE Line discipline is how the management of the transfer of data over the physical medium is controlled Two types of line discipline will be discussed in this section full duplex and half duplex Point to Point Network SECONDARY PRIMARY 270427 21 Multi Drop Network PRIMARY SECONDARY SECONDARY SECONDARY Ring Network PRIMARY SECONDARY SECONDARY Figure 3 10 SDLC Networks 7 34 270427 23 ntel 83C152 HARDWARE DESCRIPTION Full duplex is the simultaneous transmission and recep tion of data Full duplex uses anywhere from two to four wires At least one wire is needed for transmission and one wire for reception Usually there will also be a ground refer
242. ctions in this list are read modify write instructions but they are They read the port byte all 8 bits modify the addressed bit then write the new byte back to the latch The reason that read modify write instructions are di rected to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor and interpret it as a O Reading the latch rather than the pin will return the correct value of 1 ACCESSING EXTERNAL MEMORY Accesses to external memory are of two types accesses to external Program Memory and accesses to external Data Memory Accesses to external Program Memory use signal PSEN program store enable as the read strobe Accesses to external Data Memory use RD or WR alternate functions of P3 7 and P3 6 to strobe the memory Refer to Figures 36 through 38 in the Internal Timing section Fetches from external Program Memory always use a 16 bit address Accesses to external Data Memory can use either a 16 bit address MOVX GDPTR or an 8 bit address MOVX 3 9 Whenever a 16 bit address is used the high byte of the address comes out on Port 2 where it is held for the duration of the read or write cycle Note that the Por
243. d This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or write IE or IP Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the ap propriate servicing routine The hardware generated LCALL pushes the contents of the Program Counter onto the stack but it does not save the PSW and re loads the PC with an address that depends on the source of the interrupt being vectored to Table 25 shows the interrupt vector addresses Table 25 Interrupt Vector Addresses Interrupt Interrupt Cleared Vector Source Request Bits Hardware Address INTO No level 0003H Yes trans 000BH INT1 IE1 No level Yes trans 2 2 No O02BH CF CCFn n 0 AlF CF1 C1CCFn n 0 4 sc N 2 ves oossH 0058H Pinta oo63H Pints amp Yes ooeBh mre Yes 0094 6 47 intel 87C51GB HARDWARE DESCRIPTION Execution proceeds from that location until the RETI instruction is encountered The RETI instruction in forms the processor that this interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted program continues from where it left off Note that a simple RET instruction would also have returned execution to the
244. d for bit 7 and clears C otherwise If C was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the carry is subtracted from the Accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or imme diate The Accumulator holds OC9H 11001001B register 2 holds 54H 01010100B and the carry flag is set The instruction SUBB A R2 will leave the value 74H 01110100B in the accumulator with the carry flag and AC cleared but OV set Notice that OC9H minus 54H is 75H The difference between this and the above result is due to the carry borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR C instruction SUBB Rn 2 70 intel SUBB A direct Bytes Encoding Operation SUBB A Ri Bytes Cycles Encoding Operation SU
245. d period could be used but would allow some frames to be missed When a GSC transmitter has a new message to send it will first sense the link If activity is detected transmis sion will be deferred to allow the frame in progress to complete When link activity ceases the station contin ues deferring for one interframe space period As mentioned earlier the interframe space is used dur ing the collision resolution period as well as during nor mal transmission The backoff method selected affects how the deference period is handled during normal transmission If normal backoff mode is selected the interframe space timer is reset if activity occurs during approximately the first half of the interframe space If alternate backoff or deterministic backoff is selected the timer is not reset In all cases when the interframe Space timer expires transmission may begin regardless if there is activity on the link or not Although the C152 resets the interframe space timer if activity is de tected during the first one half of the interframe space this is not necessarily true of all CSMA CD systems IEEE 802 3 recommends that the interframe space be reset if activity is detected during the first two thirds or less of the interframe space ntel 83C152 HARDWARE DESCRIPTION 3 2 4 CSMA CD DATA ENCODING Manchester encoding decoding is automatically select ed when the user software selects CSMA CD transmis sion mode See Figure
246. d and contains the data that one device on the link wishes to transmit to another device It can be of any length the user wishes but must be a multiple of 8 bits It is possible that some frames may contain no information field The informa tion field is identified to the receiving stations by the preceding control field and the following CRC The GSC determines where the last of the information field is by passing the bits through the CRC generator When the last bit or EOF is received the bits that re main constitute the CRC CRC The Cyclic Redundancy Check CRC is an er ror checking sequence commonly used in serial com munications The C152 offers two types of CRC algo rithms a 16 bit and a 32 bit The 32 bit algorithm is normally used in CSMA CD applications and is de scribed in section 3 2 2 In most SDLC applications 16 bit CRC is used and the hardware configuration that supports 16 bit CRC is shown in Figure 3 8 The gener ating polynomial that the CRC generator uses with the 16 bit CRC is G X X16 X12 X5 1 The way the CRC operates is that as a bit is received it is XOR d with bit 15 of the current CRC and placed in temporary storage The result of XOR ing bit 15 with the received bit is then XOR d with bit 4 and bit 11 as the CRC is shifted one position to the right The bit in temporary storage is shifted into position 0 The required CRC length for SDLC is 16 bits The CRC is automatically stripped f
247. d by CPU write to the register SLOTTM The slot time clock is a 1 byte downcounter which starts its countdown from the value written to SLOTTM It is decremented each bit time when a backoff is in prog ress and when it gets to 1 it generates one tick in the slot time clock The next state after 1 is the reload value which was written to SLOTTM If 0 is the value writ ten to SLOTTM the slot time clock will equal 256 bit times CPU write to SLOTTM accesses the reload register A CPU read of SLOTTM accesses the downcounter In 7 26 most protocols the slot period must be equal to or greater than the longest round trip propagation time plus the jam time Deterministic Backoff In the Deterministic backoff mode the GSC is assigned in software a slot number The slot assignment is writ ten to the low 6 bits of the register MYSLOT This same register also contains in the 2 high bit positions the control bits DCJ and DCR Slot assignments therefore can run from 0 to 63 It will turn out that the higher the slot assignment the sooner the GSC will get to restart its transmission in the event of a collision The highest slot assignment in the network is written by each station s software into its TCDCNT register Normally the highest slot assignment is just the total number of stations that are going to participate in the backoff algorithm In deterministic backoff mode a collision will not cause 1 to be shifted into TCDC
248. d by software This allows the user to distinguish between a cold start reset and a warm start reset cold start reset is one that is coincident with being turned on to the device after it was turned off A warm start reset occurs while is still applied to the device and could be generated for example by a Watchdog Timer or an exit from Power Down 87C51GB HARDWARE DESCRIPTION Immediately after reset the user s software can check the status of the POF bit POF 1 would indicate a cold start The software then clears POF and com mences its tasks POF 0 immediately after reset would indicate a warm start must remain above for POF to retain a 0 15 0 EPROM OTP PROGRAMMING The 8XC51GB uses the fast Quick Pulse Program ming algorithm The devices program at Vpp 12 75V and 5 0V using a series of five 100 us PROG pulses per byte programmed 15 1 Program Memory Lock In some microcontroller applications it is desirable that the Program Memory be secure from software piracy The 8XC51GB has a three level program lock feature which protects the code of the on chip EPROM OTP or ROM Within the EPROM OTP ROM are 64 bytes of En cryption Array that are initially unprogrammed all is The user can program the Encryption Array to encrypt the program code bytes during EPROM OTP ROM verification The verification procedure is per formed as usual except that each code byte
249. d by the GSC TSTAT 7 LND Line Idle If set indicates the re ceive line is idle In SDLC protocol it is set if 15 consec utive ones are received In CSMA CD protocol line idle is set if GR X D remains high for approximately 1 6 bit times LNI is cleared after a transition on GR XD The status of this flag is controlled by the GSC 7 47 3 8 Serial Backplane vs Network Environment The C152 GSC port is intended to fulfill the needs of both serial backplane environment and the serial com munication network environment The serial backplane is where typically only processor to processor commu nications take place within a self contained box The communication usually only encompasses those items which are necessary to accomplish the dedicated task for the box In these types of applications there may not be a need for line drivers as the distance between the transmitter and receiver is relatively short The net work environment however usually requires transmis sion of data over large distances and requires drivers and or repeaters to ensure the data is received on both ends 4 0 DMA Operation The C152 contains DMA Direct Memory Accessing logic to perform high speed data transfers between any two of Internal Data RAM Internal SFRs External Data RAM If external RAM is involved the Port 2 and Port 0 pins are used as the address data bus and RD and WR signals are generated as required Hardware is also implement
250. d understanding of the memory space and how it is used in the operation of MCS 51 products is essen tial All the enhancements on the C152 are implement ed by accessing Special Function Registers SFRs added data memory or added program memory 1 d 04 119 014 3430 1visu 1081N05 259 0 43151938 315934 SS34gQ0vY 83C152 HARDWARE DESCRIPTION 03151939 SS3400Y 33430 593 Sagara 2 1408 0 1804 1408 Ltd 0 Zd 04 004 0 vd Figure 1 1 Block Diagram 4 7 intel 2 1 1 SPECIAL FUNCTION REGISTERS SFRs The following list contains all the SFRs their names and function of the SFRs of the 80C51BH tained and for a detailed explanation of their operation please refer to the chapter Hardware Description of the 8051 and 8052 that is found in the Embedded Controller Handbook An overview of the new SFRSs is found in Section 2 1 1 1 with a detailed explanation in Section 3 7 Section 4 5 and 6 0 2 1 1 1 New SFRs The following descriptions are quick overviews of the new SFRs and not intended to give a complete under standing of their use The reader should refer to the detailed explanation in Section 3 for the GSC SFRs and Section 4 for the DMA SFRs ADR 0 1 2 3 95H 0A5H 0B5H OCSH Contains the four bytes
251. ddressed slave then clears its SM2 bit and pre pares to receive the data bytes that will be coming other slaves are unaffected by these data bytes as they are still waiting to receive an address byte The feature works the same way in the 8 bit mode Mode 1 as in the 9 bit modes except that the stop bit takes the place of the 9th data bit If SM2 is set the RI flag is set only if the received byte matches the Given or Broadcast Address and is terminated by a valid stop bit Setting the SM2 bit has no effect on Mode 0 The master can selectively communicate with groups of slaves by using the Given Address Addressing all slaves at once is possible with the Broadcast Address These addresses are defined for each slave by two Spe cial Function Registers SADDR and SADEN 4 10 slave s individual address is specified in SADDR SADEN is a mask byte that defines don t care bits to form the Given Address These don t cares allow flexi bility in the user defined protocol to address one or more slaves at a time The following is an example of how the user could define Given Addresses to selective ly address different slaves Slave 1 SADDR 1111 0001 SADEN 1111 1010 GIVEN 1111 0X0X Slave 2 SADDR 1111 0011 SADEN 1111 1001 GIVEN 1111 0XX1 The SADEN bits are selected such that each slave can be addressed separately Notice that bit O LSB is a don t care for Slave 1 s Given Address but bit 0 1 for Slave 2 T
252. de as well as in CSMA CD mode The period of the interframe space is determined by the contents of IFS IFS is an SFR that is programmable from O to 254 The interframe space is measured in bit times The value in IFS multiplied by the bit time equals the interframe space unless IFS equals 0 If IFS does equal 0 then the interframe space will equal 256 bit times One of the considerations when loading the IFS is that only even numbers LSB must be 0 can be used because only the 7 most significant bits are loaded into IFS The LSB is controlled by the GSC and deter mines which half of the IFS is currently being used In some modes the interframe space timer is re triggered if activity is detected during the first half of the period The GSC determines which half of the interframe space is currently being used by examining the LSB A one indicates the first half and zero indicates the second half of the IFS After reset IFS is 0 which delays the first transmission for both SDLC and CSMA CD by 256 bit times after reset a bit time equals 8 oscillator clock periods 7 22 In most applications the period of the interframe space will be equal to or greater than the amount of time needed to turn around the received frame The turn around period is the amount of time that is needed by user software to complete the handling of a received frame and be prepared to receive the next frame An interframe space smaller than the required turn aroun
253. e Modes 1 3 Baud Rate Oscillator Frequency 32x 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of RCAP2H and RCAP2L taken as a 16 bit unsigned in teger Timer 2 as a baud rate generator is shown in Figure 16 This Figure is valid only if RCLK TCLK 1 in T2CON Note that a rollover in TH2 does not set TF2 and will not generate an interrupt Therefore the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Note too that if 2 is set a 1 0 0 transition T2EX will set EXF2 but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate generator 2 can be used as an extra external interrupt if desired It should be noted that when Timer 2 is running TR2 1 in timer function in the baud rate generator mode one should not try to read or write TH2 or TL2 Under these conditions the Timer is being incremented every state time and the results of a read or write may not be accurate The RCAP registers may be read but shouldn t be written to because a write might overlap a reload and cause write and or reload errors Turn the Timer off clear TR2 before accessing the Timer 2 or RCAP registers in this case More About Mode 0 Serial data enters and exits through RXD TXD out puts the shift clock 8 bits are transmitted received 8 data bits LSB first The baud rate is fixed at the osc
254. e information field CRC The Cyclic Redundancy Check CRC is an er ror checking algorithm commonly used in serial com munications The C152 offers two types of CRC algo rithms a 16 bit and a 32 bit The 16 bit algorithm is normally used in the SDLC mode and will be described in the SDLC section In CSMA CD applications either 7 21 algorithm can used but IEEE 802 3 uses 32 bit CRC The generation polynomial the C152 uses with the 32 bit CRC is G X X32 X26 X23 X22 X16 X12 Xil X10 X8 X7 X5 X4 2 X 1 The CRC generator as shown in Figure 3 2 operates by taking each bit as it is received and XOR ing it with bit 31 of the current CRC This result is then placed in temporary storage The result of XOR ing bit 31 with the received bit is then XOR d with bits 0 1 3 4 6 7 9 10 11 15 21 22 25 as the CRC is shifted right one position When the CRC is shifted right the temporary storage space holding the result of XOR ing bit 31 and the incoming bit is shifted into position 0 The whole process is then repeated with the next incoming or out going bit The user has no access to the CRC generator or the bits which constitute the CRC while in CSMA CD On transmission the CRC is automatically appended to the data being sent and on reception the CRC bits are not normally loaded into the receive FIFO Instead they are automatically stripped The only indication the user has for the status
255. e CL register is incremented at S5P2 of the ma chine cycle when Timer 0 overflows This mode al d lows a pro able input frequency to the PCA 6 1 PCA 16 Bit Timer Counter po d RE External input The PCA has a free running 16 bit timer counter con The CL register is incremented at the first one of wipe of the count value These two registers read or Jet eH written to at any time Figure 16 shows a block dia pled at S1P2 S3P2 and S5P2 of every machine cy cle The maximum input frequency in this mode is oscillator frequency 8 MODULES 0 4 FOSC 12 eed CH jue ed OVERFLOW 8 BITS 8 BITS EXTERNAL D spa CONTROL INTERRUPT ENABLE PROCESSOR IDLE MODE Figure 16 PCA Timer Counter 5 20 intel 8XC51FX HARDWARE DESCRIPTION CH is incremented after two oscillator periods when The CCON register shown in Table 11 contains two CL overflows more bits which associated with the timer counter The CF bit gets set by hardware when the The mode register CMOD contains the Count Pulse counter overflows and the CR bit is set or cleared to Select bits CPS1 and CPSO to specify the clock input turn the counter on or off The other five bits in this CMOD is shown in Table 10 This register also con register are the event flags for the compare capture tains the bit which enables the PCA counter over modules and
256. e Interrupt Priori ty to High 0 Priority to Low 1 GSC Transmit Valid Interrupt Priority to High 0 Priority to Low 1 DMA Channel 0 Done Interrupt Priori ty to High _0 Priority to Low 1 GSC Receive Error Interrupt Priority to High 0 Priority to Low 1 GSC Receive Valid Interrupt Priority to High 0 Priority to Low tou PDMAI PGSTV PDMAO PGSRE PGSRV Note that these registers all have unimplemented bits If these bits are read they will return unpredict able values If they are written to the value written goes nowhere It is recommended that user software should never write 15 to unimplemented bits in MCS 51 devices Fu ture versions of the device may have new bits installed in these locations If so their reset value will be 0 Old software that writes 15 to newly implemented bits may unexpectedly invoke new features The MCS 51 interrupt structure provides hardware support for only two priority levels High and Low With as many interrupt sources as the 8XC152 has it may be helpful to know how to augment the priority structure in software Any number of priority levels can be implemented in software by saving and redefining the interrupt enable registers within the interrupt serv ice routines The technique is described in the 51 Architectural Overview chapter in this handbook ntel 5 1 GSC Transmitter Error Conditions The GSC Transmitter section reports three kinds of err
257. e SEP interrupt and the serial port in terrupt Figure 32 shows the interrupt sources of the bits that generate interrupts can be set or cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be canceled in software 12 1 External Interrupts External Interrupts INTO and INTI can each be either level activated or negative edge triggered depending on bits ITO and in register TCON If ITx 0 exter nal interrupt x is triggered by a detected low at the INTx pin If ITx 1 external interrupt x is negative edge triggered INT2 and INT3 can each be either negative or positive edge triggered depending on bits 112 and IT3 in regis ter EXICON If ITx 0 external interrupt x is nega tive edge triggered If ITx 1 external interrupt x is positive edge triggered INT4 INT5 and INT6 are positive edge triggered only 6 41 270897 32 Figure 32 Interrupt Sources 87C51GB HARDWARE DESCRIPTION Table 21 EXICON External Interrupt Control Register EXICON Address 6 7 6 Function Bit EXICON Symbol 5 IE5 IE6 is detected IE5 is detected IE4 is detected IE3 is detected IE2 is detected IT3 4 IE4 Reset Value X000 0000B Not Bit Addressable 1 0 IT3 IT2 3 IE3 2 IE2 Not implemented reserved for future use Interrupt 6 Edge flag This bit is
258. e SMOD bit ORL 80 The address of PCON is 87H SERIAL PORT IN MODE 3 The baud rate in mode 3 is variable and sets up exactly the same as in mode 1 2 20 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MCS 51 INSTRUCTION SET Table 10 8051 Instruction Set Summary Oscillator Int t R Time Refer to Hard De nterrupt Response Time er to ware scription Chapter Instructions that Affect Flag Settings 1 Instruction Instruction Flag Mnemonic Description Byte ARITHMETIC OPERATIONS ADD A Rn Add register to Accumulator ADD A direct Add direct byte to Accumulator ADD A Ri Add indirect to Accumulator ADD A data Addimmediate data to Accumulator ADDC A Rn Add register to Accumulator with Carry ADDC Add direct byte to Accumulator with Carry ADDC A Ri Add indirect RAM to Accumulator with Carry A data Add immediate data to Acc with Carry A Rn Subtract Register from Acc with borrow A direct Subtract direct byte from Acc with borrow A GRi Subtract indirect RAM from ACC with borrow A data Subtract immediate data from Acc with borrow Increment Accumulator increment register increment direct byte increment direct RAM Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM All mnemonics copyrighted Intel Corporation 1980 2 gt X ANL C bit ANL C bit ORL ORL C bit MOV C bit
259. e addr 1 AB 3 CJNE R1 data code addr 3 data addr data addr 3 CJNE RO data code addr 2 data addr R0 3 CJNE 1 data code addr 2 data addr R1 3 Re data code addr 2 data addr RO 3 CJNE data code addr 2 data addr R1 3 CJNE R4 data code addr 2 data addr R2 3 CJNE R5 data code addr 2 data addr R3 3 CJNE R6 data code addr 2 data addr R4 3 CJNE R7 data code addr 2 data addr R5 2 PUSH data addr 2 data R6 2 AJMP code addr 2 data addr R7 2 CLR bit addr 3 DPTR data 1 CLR 2 code addr 1 SWAP A 2 bit addr C 2 XCH A data addr 1 A A DPTR 1 XCH 2 A s data 1 XCH A GR1 2 A data addr 1 XCH A RO 1 A RO 1 XCH 1 1 1 A R2 1 A RO 1 2 26 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 11 Instruction Opcodes in Hexadecimal Order Continued Number of Bytes Hex Number Code Bytes Mnemonic Mnemonic Operands data addr code addr A GRO A R1 RO code addr R1 code addr R2 code addr R3 code addr R4 code addr R5 code addr R6 code addr R7 code addr A DPTR code addr A RO A R1 A A data addr data addr A eRO A GR1 A R2 A R3 A R4 A R5 A R6 A R7 A 1 1 1 1 1 1 1 1 2 1 2 1 2 1 1 1 1 1 3 1 1 1 1 2 2 1 2 1 2 1 2 2 2 1 2 1 2 1 2 1 1 1 2 1 1 1 1 1 1 1 2 1 2 27 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET INSTRUCTION DEFINITIONS ACALL addr11 Function Abs
260. e as a clock output signal Note however that one ALE is skipped during the execution of the MOVX instruction Interrupt Structure The 8051 core provides 5 interrupt sources 2 external interrupts 2 timer interrupts and the serial port inter rupt What follows is an overview of the interrupt structure for the 8051 Other MCS 51 devices have ad ditional interrupt sources and vectors as shown in Ta ble 1 Refer to the appropriate chapters on other devic es for further information on their interrupts INTERRUPT ENABLES Each of the interrupt sources can be individually en abled or disabled by setting or clearing a bit in the SFR MSB LSB eA es er eo exo Enable bit 1 enables the interrupt Enable bit 0 disables it Symbol Position EA IE 7 Function disables all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit reserved reserved Serial Port Interrupt enabie bit Timer 1 Overflow Interrupt enable bit External Interrupt 1 enable bit ETO Timer 0 Overflow Interrupt enable bit EX0 External interrupt 0 enable bit These reserved bits are used in other MCS 51 devices ES ET1 EX1 Figure 17 IE Interrupt Enable Register in the 8051 1 20 named IE Interrupt Enable This register also con tains a global disable bit which can be cleared to dis able all i
261. e capability of receiving group addresses If desired the user software can mask off all the bits of the address This type of masking puts the GSC in a promiscuous mode so that all addresses are received 7 28 CONTROL The control field is used for initialization of the system identifying the sequence of a frame to identify if the message is complete to tell secondary stations if a response is expected and acknowledgement of previously sent frames The user software is responsi ble for insertion of the control field as the GSC hard ware has no provisions for the management of this field The interpretation and formation of the control field must also be handled by user software The infor mation following the control field is typically used for information transfer error reporting and various other functions These functions are accomplished by the for mat of the control field There are three formats avail able The types of formats are Informational Supervi sory or Unnumbered Figure 3 7 shows the various for mat types and how to identify them Since the user software is responsible for the implemen tation of the control field what follows is a simple ex planation on the control field and its functions For a complete understanding and proper implementation of SDLC the user should refer to the IBM document GA27 3093 2 IBM Synchronous Data Link Control General Information Within that document is another list of I
262. e inactive and in fact if they re not going to be used at all their pins are avail able as extra I O lines More about that later LOOKUP TABLES Table 6 shows the two instructions that are available for reading lookup tables in Program Memory Since these instructions access only Program Memory the lookup tables can only be read not updated The mne monic is MOVC for move constant If the table access is to external Program Memory then the read strobe is PSEN Tabie 6 The 5 51 Lookup Table Read Instructions A A DPTR Read Memory at A A A PC Read Pgm Memory at A PC The first MOVC instruction in Table 6 can accommo date a table of up to 256 entries numbered 0 through 255 The number of the desired entry is loaded into the Accumulator and the Data Pointer is set up to point to beginning of the table Then MOVC A DPTR copies the desired table entry into the Accumulator The other MOVC instruction works the same way ex cept the Program Counter PC is used as the table base and the table is accessed through a subroutine First the number of the desired entry is loaded into the Accumulator and the subroutine is called MOV CALL __ NUMBER TABLE The subroutine TABLE would look like this TABLE MOVC A A PC RET The table itself immediately follows the RET return instruction in Program Memory Th
263. e of the GSC pins becomes critical and the GSC status will need to be saved before power down is entered There will also need to be some meth od of identifying to the CPU that the following Reset is probably not a cold start and that other stations on the link may have already been initialized The DMA circuitry stops operation in both Idle and Power Down modes Since operation is stopped in both modes the process should be similar in each case Spe cific steps that need to be taken include notification to other devices that DMA operation is about to cease for a particular station or network proper withdrawal from DMA operation and saving the status of the channels Again the status of the I O pins dur ing Power Down needs careful consideration to avoid damage to the C152 or other components Port 4 returns to its input state which is high level using weak pullup devices 7 17 83C152 HARDWARE DESCRIPTION 2 9 Local Serial Channel The Local Serial Channel LSC is the name given to the UART that exists on all MCS 51 devices The LSC s function and operation is exactly the same as on the 80C51BH For a description on the use of the LSC refer to the 8051 52 Hardware Description Chapter in the Intel Embedded Controller Handbook under Serial Interface 3 0 GLOBAL SERIAL CHANNEL 3 1 Introduction The Global Serial Channel GSC is a multi protocol high performance serial interface targeted for data rates up
264. e used is load the byte count set up the source addresses for the DMA chan nel servicing the transmitter set up the destination ad dresses for the DMA channel servicing the receiver and start the DMA transfer The GSC enable bits should be set first and then the GO bits for the DMA This initiates the data transfers ntel 83C152 HARDWARE DESCRIPTION This simplifies the maintenance of the GSC and can make the implementation of an external buffer for packetized information automatic An external buffer can be used as the source of data for transmission or the destination of data from the receiv er In this arrangement the message size is limited to the RAM size or 64K whichever is smaller By using an external buffer the data can be accessed by other devices which may want access to the serial data The amount of time required for the external data moves will also decrease Under CPU control a command would take 24 oscillator periods to complete Under DMA control external to internal or internal to external data moves take only 12 oscillator periods 3 5 4 BAUD RATE The GSC baud rate is determined by the contents of the SFR BAUD the external clock The formula used to determine the baud rate when using the internal clock is fosc BAUD 1 8 For example if a 12 MHz oscillator is used the baud rate can vary from 12 000 000 0 1 8 1 5 MBPS to 12 000 000 255 1 8 5 85
265. eatures In that case the reset or inactive value of the new bit will be O and its active value will be 1 The value read from a reserved bit is indeterminate 5 39 ntel internal reset algorithm takes control On chip hard ware inhibits access to the internal RAM during this time but access to the port pins is not inhibited To eliminate the possibility of unexpected outputs at the port pins the instruction following the one that invokes Idle should not be one that writes to a port pin or to external Data RAM 10 2 Power Down Mode An instruction that sets PCON 1 causes that to be the last instruction executed before going into the Power Down mode this mode the on chip oscillator is stopped With the clock frozen functions stopped but the on chip RAM and Special Function Registers are held The port pins output the values held by their respective SFRs and ALE and PSEN output lows In Power Down can be reduced to as low as 2V Care must be taken however to ensure that is not reduced before Power Down is invoked The C51FX can exit Power Down with either hard ware reset or external interrupt Reset redefines all the SFRs but does not change the on chip RAM An exter nal interrupt allows both the SFRs and the on chip RAM to retain their values To properly terminate Power Down the reset or exter nal interrupt should not be executed before is restored to its normal operating level
266. ed The user software is responsible for setting or clearing this flag GMOD 1 2 PLO 1 Preamble length PL1 PLO LENGTH BITS 0 0 0 0 1 8 1 0 32 1 1 64 7 44 The length includes the two bit Begin Frame flag in CSMA CD but does not include the SDLC flag In SDLC mode the BOF is an SDLC flag otherwise it is two consecutive ones Zero length is not compatible in CSMA CD mode The user software is responsible for setting or clearing these bits GMOD 3 CRC Type If set 32 bit AUTODIN 32 is used If cleared 16 bit CRC CCITT is used The user software is responsible for setting or clearing this flag GMOD AL Address Length If set 16 bit ad dressing is used If cleared 8 bit addressing is used In 8 bit mode a match with any of the 4 address registers will be accepted ADRO ADRI ADR2 ADR3 Don t Care bits may be masked ADRO and 1 with AMSKO and AMSK1 In 16 bit mode addresses are matched against ADRI ADRO ADR3 ADR2 Again Don t Care bits in ADR1 ADRO can be masked in 1 A received address of all ones will always be recognized in any mode The user software is responsible for setting or clearing this flag GMOD 5 6 Mode Select Two test modes an optional alternate backoff mode or normal back off can be enabled with these two bits The user soft ware is responsible for setting or clearing the mode bits M1
267. ed a one are changed to a zero and vice versa No flags are affected Example Accumulator contains 5 01011100B The instruction CPL A will leave the Accumulator set to 10100011B Bytes 1 Cycles 1 Encoding 1111 0100 Operation CPL 71 CPL bit Function Complement bit Description bit variable specified is complemented A bit which had been a one is changed to zero and vice versa No other flags are affected CLR can operate on the carry or any directly address able bit Note When this instruction is used to modify an output pin the value used as the original data will be read from the output data latch not the input pin Example 1 has previously been written with 5BH 01011101B The instruction sequence CPL Pl CPL 1 2 will leave the port set to 5 01011011 Bytes 1 Cycles 1 Encoding 1011 0011 Operation CPL intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CPL bit Bytes 2 Cycles 1 Encoding bit address Operation CPL bit lt 71 bit DA A Function Decimal adjust Accumulator for Addition Description DA A adjusts the eight bit value in the Accumulator resulting from the earlier addition of two variables each in packed BCD format producing two four bit digits Any ADD or ADDC instruction may have been used to perform the addition If Accumulator bits 3 0 are greater than nine xxxx1010 xxxx1111 or if the AC fl
268. ed to be random This method gives all stations an equal opportunity to utilize the serial com munication link but also leaves the possibility of anoth er collision due to two stations having the same slot assignment There is an option on the C152 which al lows all the stations to have their slot assignments pre viously determined by user software This pre assign ment of slots is called the deterministic resolution mode This method allows resolution after the first col lision and ensures the access of the link to each station during the resolution Deterministic resolution can be advantageous when the link is being heavily used and collisions are frequently occurring and in real time ap plications where determinism is required Deterministic resolution may also be desirable if it is known before hand that a certain station s communication needs to be prioritized over those of other stations if it is involved in a collision 3 2 2 CSMA CD FRAME FORMAT The frame format in CSMA CD consists of a pream ble Beginning of Frame flag BOF address field in formation field CRC and End of Frame flag EOF as shown in Figure 3 1 Figure 3 1 Typical CSMA CD Frame PREAMBLE The preamble is a series of alternating 15 and Os The length of the preamble is programmable to be 0 8 32 or 64 bits The purpose of the preamble is to allow all the receivers to synchronize to the same clock edges and identifies to the other stations on line t
269. ed to generate a Hold Re quest signal and await a Hold Acknowledge response before commencing a that involves external RAM Alternatively the Hold Hold Acknowledge hardware can be programmed to accept a Hold Request signal from an external device and generate Hold Acknowl edge signal in response to indicate to the requesting device that the C152 will not commence a DMA to or from external RAM while the Hold Request is active 4 1 DMA with the 80C152 The C152 contains two identical general purpose 8 bit channels with 16 bit addressability DMAO and DMA transfers can be executed by either chan nel independent of the other but only by one channel at a time During the time that a DMA transfer is being executed program execution is suspended A DMA transfer takes one machine cycle 12 oscillator CHANNEL 0 DARHO DARLO DESTINATION ADDRESS SOURCE ADDRESS BCRHO BCRLO BYTE COUNT DMAO CONTROL 83C152 HARDWARE DESCRIPTION DMA CHANNEL 1 DESTINATION ADDRESS SOURCE ADDRESS U BYTE COUNT DMA1 CONTROL new bits control Hold Hold Acknowledge logic 270427 28 Figure 4 1 Registers periods byte transferred except when the destina tion and source are both in External Data RAM In that case the transfer takes two machine cycles per byte The term DMA Cycle will be used to mean the transfer of a sing
270. ee machine cycles data may continue to be transmitted for up to 4 machine cycles after Reset is first applied ALE Address Latch Enable output signal for latching the low byte of the address during accesses to external memory In normal operation ALE is emitted at a constant rate of 1 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory While in Reset ALE remains at a constant high level PSEN Program Store Enable is the Read strobe to External Program Memory When the 8XC152 is executing from external program memory PSEN is active low When the device is executing code from External Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to External Data Memory While in Reset PSEN remains at a constant high level Access enable EA must be externally pulled low in order to enable the 8XC152 to fetch code from External Program Memory locations 0000H to OFFFH EA must be connected to for internal program execution XTAL 1 Input to the inverting oscillator amplifier and input to the internal clock generating circuits Port 5 Port 5 is an 8 bit bi directional 1 port with internal 5 Port 5 pins that have 1s written to them are pulled high by the internal pu
271. egative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX Start Stop control for Timer 2 TR2 1 starts the timer Timer or counter select for Timer 2 C T2 0 for timer function C T2 1 for external event counter falling edge triggered Capture Reload select CP RL2 1 causes captures to occur on negative transitions at T2EX if EXEN2 1 CP RL2 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at 2 when EXEN2 1 When either RCLK TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow 8 52 54 58 HARDWARE DESCRIPTION Table 4 Timer 2 Operating Modes CAPTURE MODE In the capture mode there are two options selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 16 bit timer or counter which upon overflow sets bit TF2 in T2CON This bit can then be used to generate an interrupt If 2 1 Timer 2 still does the above but with the added feature that a 1 to O tran sition at external input T2EX causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set The EXF2 bit like TF2 can generate an interrupt The capture mode is illustrated in Figure 1 AUTO RELOAD Up or Down Counter Timer 2 can be programmed to count up or down when configured in i
272. egister and reception of the rest of the frame will pro intel n HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 8051 INTERNAL BUS KEEKE PHASE 2 CLOCK tosc MODE 2 SMOD 1 SERIAL INTERRUPT SMOD 0 SMOD IS AX CLOCK RX CONTROL INPUT SHIFT REG 9 BITS LOAD N SBUF y Y ix 8051 INTERNAL BUS LOCK 1 f 1 1 1 WRITE TO SBUF 86 DATA Esim aS SHIFT R fil 1 A 1 1 TRANSMIT TXD SIT J STOP RX 16 RESET RECEIVE 270252 17 Figure 19 Serial Port Mode 2 3 21 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 8051 INTERNAL BUS TIMER 1 TIMER 2 OVERFLOW OVERFLOW 8051 INTERNAL BUS TX LOC WRITE TO SBUF roc o Ao 11 01 41 A A h _ R k _ 1 __ pong S1P1 4 fl 1 TRANSMIT SHIFT Txo STOP 1I STOP BIT GEN RX 16 RESET CLOCK gir DETECTOR STOP RECEIVE SAMPLE TIMES AM BIT SH RI J 525 f 270252 18 Figure 20 Serial Port Mode 3 and Timer 2 are Present the 8052 8032 Only 3 22 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in Modes 2 and 3 is a 9 bit register it flags the RX Control
273. egister SCON while the stop bit is ignored The baud rate is programmable to either or the oscillator frequency Mode 3 11 bits are transmitted through TXD or re ceived through a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 all respects except the baud rate The baud rate in Mode 3 is vari able In all four modes transmission is initiated by any in struction that uses SBUF as a destination register Re ception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 3 14 Multiprocessor Communications Modes 2 and 3 have a special provision for multipro cessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an ad dress byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An addre
274. egisters for Timer Counters 0 1 and 2 respectively Control and status bits are contained in registers TCON and TMOD for Timers 0 and 1 and in registers T2CON and T2MOD for Timer 2 The register pair RCAP2H RCAP2L are the capture reload registers for Timer 2 in 16 bit capture mode or 16 bit auto reload mode Programmable Counter Array PCA Registers The 16 bit PCA timer counter consists of registers CH and CL Registers CCON and CMOD contain the control and status bits for the The CCAPMn n 0 1 2 3 or 4 registers control the mode for each of the five PCA modules The register pairs CCAPnH CCAPnL are the 16 bit compare capture registers for each PCA module Serial Port Registers The Serial Data Buffer SBUF is actually two separate registers a transmit buffer and a receive buffer register When data is moved to SBUF it goes to the transmit buffer where it is held for serial transmission Moving a byte to SBUF initiates the transmission When data is moved from SBUF it comes from the receive buffer Register SCON contains the control and status bits for the Serial Port Registers SADDR and SADEN are used to define the Given and the Broadcast addresses for the Automatic Address Recognition feature Interrupt Registers The individual interrupt enable bits are in the IE register Two priorities can be set for each of the 7 interrupts in the IP register Power Control Register PCON controls the Power Reduc
275. emember that while an interrupt service is in progress it cannot be interrupted by a lower or same level interrupt PRIORITY WITHIN LEVEL Priority within level is only to resolve simultaneous requests of the same priority level From high to low interrupt sources are listed below IEO TF0 IE1 RI or TI TF2 or EXF2 IP INTERRUPT PRIORITY REGISTER BIT ADDRESSABLE If the bit is 0 the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a higher priority IP 7 Not implemented reserved for future use IP 6 Not implemented reserved for future use PT2 IP 5 Defines the Timer 2 interrupt priority level 8052 only PS IP 4 Defines the Serial Port interrupt priority level 3 Defines the Timer 1 interrupt priority level 2 Defines External Interrupt 1 priority level 1 Defines the Timer 0 interrupt priority level PXO 0 Defines the External Interrupt 0 priority level User software should not write 1s to reserved bits These bits may be used in future MCS 51 products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 2 13 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TCON TIMER COUNTER CONTROL REGISTER BIT ADDRESSABLE TCON 7 Timer 1 overflow flag Set by hardware when the Timer Counter 1 overflows Cleared by hard ware as processor vecto
276. en the actual transmit ted waveform and the exact calculated value s In NRZI data jitter would be how much the actual wave form exceeds or falls short of one calculated bit time A bit time equals 1 baud rate If using Manchester encod ing there can be two transitions during one bit time as shown in Figure 3 11 This causes a second parameter to be considered when trying to figure out the complete data jitter amount This other parameter is the half bit jitter The half bit jitter is comprised of the difference in time that the half bit transition actually occurs and the calculated value Jitter is important because if the tran sition occurs too soon it is considered noise and if the transition occurs too late then either the bit is missed or a collision is assumed LOGICAL VALUE MANCHESTER ENCODING RECEIVED DATA RECEIVED DATA Figure 3 11 3 5 9 Transmit Waveforms The GSC is capable of three types of data encoding Manchester NRZI and NRZ Figure 3 12 shows ex amples of all three types of data encoding 3 5 10 Receiver Clock Recovery The receiver is always monitored at eight times the baud rate frequency except when an external clock is used When using an external clock the receiver is load ed during the clock cycle In CSMA CD mode the receiver synchronizes to the transmitted data during the preamble If a pulse is de tected as being too short it is assumed to be noise or a collision If a pulse is to
277. ence on each signal if the distance from station to station is relatively long Full duplex opera tion in the C152 requires that both the receive and the transmit portion of the GSC are functioning at the same time Since both the transmitter and receiver are operating two CRC generators are also needed The C152 handles this problem by having one 32 bit CRC generator and one 16 bit CRC generator When sup porting full duplex operation the 32 bit CRC generator is modified to work as a 16 bit CRC generator When ever the 16 bit CRC is selected the GSC automatically enters the full duplex mode Half duplex with 16 bit CRC is discussed in the following paragraph Half duplex is the alternate transmission and reception of data over a single common wire Only one or two wires are needed in half duplex systems One wire is needed for the signal and if the distance to be covered is long there will also be a wire for the ground reference In half duplex mode only the receiver or transmitter can operate at one time When the receiver or transmit ter operates is determined by user software but typical ly the receiver will always be enabled unless the GSC is transmitting When using the C152 in half duplex and the receiver is connected to the transmitter it is possible that a station will receive its own transmission This can occur if a broadcast address is sent the address mask register s are filled with all 15 or the address being sent
278. er interrupts are enabled by bits ETO and in the IE register Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared in software The Timer 2 interrupt is enabled by the ET2 bit in the IE register 12 3 PCA Interrupt The interrupts are generated by the logical OR of five event flags CCFn CICFn and the PCA timer overflow flag CF CF1 in the registers CCON and 1 None of these flags are cleared by hardware when the service routine is vectored to Normally the service routine will have to determine which bit flagged the interrupt and clear that bit in software This allows the user to define the priority of servicing each PCA module 6 43 87C51GB HARDWARE DESCRIPTION The PCA interrupt is enabled by bit EC in the IE regis ter The interrupt is enabled by bit in the IEA register In addition the CF CF1 flag and each of the CCFn C1CFn flags must also be individually enabled by bits ECF ECF1 and ECCFn ECICFn in registers CMOD CIMOD and CCAPMn respectively in order for that flag to be able to cause an interrupt 12 4 Serial Port Interrupt The serial port interrupt is generated by the logical OR of bits R
279. er of slots that are most appropriate for a particu lar application The PRBS register must be set to all ones This disables the PRBS by freezing it s contents at The backoff timer 15 used to count down the number of slots based on the slot timer value setting the period of one slot The user software is responsible for setting or clearing this flag MYSLOT 7 DCJ D C Jam When set selects D C type jam when clear selects A C type jam The user software is responsible for setting or clearing this flag 83C152 HARDWARE DESCRIPTION mo 087 7 6 5 4 3 2 1 0 Swoc ee nec eanEN acuario PCON contains bits for power control LSC control control and GSC control The bits used for the GSC are PCON 2 PCON 3 and 4 PCON 2 GFIEN GSC Flag Idle Enable Setting GFIEN to a 1 caused idle flags to be generated between transmitted frames in SDLC mode SDLC idle flags consist of 01111110 flags creating the sequence 01111110011111110 011111110 A possible side effect of enabling GFIEN is that the maximum possible latency from writing to TFIFO until the first bit is transmitted increased from approximately 2 bit times to around 8 bit times GFIEN has no effect with CSMA CD PCON 3 XRCLK GSC External Receive Clock En able Writing a 1 to XRCLK enables an external clock to be applied to pin 5 Port 1 4 The external clock is used to determine when bits are loaded into the receiv
280. eramic resonator between the XTALI and XTAL2 pins of the microcontroller and capacitors to ground as shown in Figure 13 270251 14 5 Figure 14 Using External 1 17 intel MCS 51 ARCHITECTURAL OVERVIEW Examples of how to drive the clock with an external oscillator are shown in Figure 14 Note that in the HMOS devices 8051 etc the signal at the XTAL2 pin actually drives the internal clock generator In the CHMOS devices 80C51BH etc the signal at the pin drives the internal clock generator If only one pin is going to be driven with the external oscillator signal make sure it is the right pin The internal clock generator defines the sequence of states that make up the MCS 51 machine cycle 1 P1 P2 S2 P2 53 m 54 1 2 P2 OSC XTAL2 P2 READ NEXT OPCODE DISCARD READ NEXT OPCODE DISCARD READ NEXT OPCODE DISCARD D MOVX 1 byte 2 Machine Cycles A machine cycle consists of a sequence of 6 states numbered S1 through S6 Each state time lasts for two oscillator periods Thus a machine cycle takes 12 oscil lator periods or 1 ps if the oscillator frequency is 12 MHz Each state is divided into a Phase 1 half and a Phase 2 half Figure 15 shows the fetch execute sequences in 1 P P2 54 55 P1 P2 1 P2 5 2 1 READ NEXT OPCODE AGAIN RE
281. errupt source is individually enabled or disabled by setting or clearing its enable bit IE 6 reserved IE 5 Timer 2 interrupt enable bit IE 4 Serial Port interrupt enable bit IE 3 Timer 1 interrupt enable bit IE 2 External interrupt 1 enable bit Timer 0 interrupt enable bit 0 External interrupt 0 enable bit User software should never write 1s to unimplemented bits since they may be used in future MCS 51 products Figure 22 IE Interrupt Enable Register intel Each of these interrupt sources can be individually en abled or disabled by setting or clearing a bit in Special Function Register Figure 22 IE contains also global disable bit EA which disables all interrupts at once Note in Figure 22 that bit position IE 6 is unimple mented In the 8051s bit position IE 5 is also unimple mented User software should not write 1s to these bit positions since they may be used in future MCS 51 products Priority Level Structure Each interrupt source can also be individually pro grammed to one of two priority levels by setting or clearing a bit in Special Function Register IP Figure 23 A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low pri ority interrupt high priority interrupt can t be inter rupted by any other interrupt source MSB LSB es er Pro exo Priority bit 1 assigns high priority
282. et by hardware when a match or capture occurs Must PCA Module 3 interrupt flag Set by hardware when a match or capture occurs Must be PCA Module 2 interrupt flag Set by hardware when a match or capture occurs Must be PCA Module 1 interrupt flag Set by hardware when a match or capture occurs Must be PCA Module 0 interrupt flag Set by hardware when a match or capture occurs Must be User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate READING THE PCA TIMER Some applications may require that the full 16 bit PCA timer value be read simultaneously Since the timer consists of two 8 bit registers CH CL it would nor mally take two MOV instructions to read the whole timer value An invalid read could occur if the registers rolled over in between the execution of the two MOVs However with the PCA Capture Mode the 16 bit timer value can be loaded into the capture registers by tog gling a port pin For example configure Module O to capture falling edges and initialize P1 3 to be high Then when the user wants to read the PCA timer clear P1 3 and the full 16 bit timer value will be saved in the capture registers It s still optional whether the user wants to generate an interrupt with the capture 6
283. et size In these cases the servicing of the DMA and or GSC would be in response to the DMA Done flag when the byte count reaches zero In some cases the buffer size is not the limiting factor and the packet lengths will be unknown In these cases it would be desirable to eliminate the function of the Done flag To effectively disable the Done flag for the DMA channel servicing the receiver the byte count Should be set to some number larger than any packet 7 36 that will be received up to 64K If not using the Done flag then GSC servicing would be driven by the receive Done RDN flag and or interrupt RDN is set when the EOF is detected When using the flag should also be checked to insure that all the data has been emptied out of the receive FIFO The byte count register is used for all transmissions and this means that all packets going out will have to be of the same length or the length of the packet to be sent will have to be known prior to the start of transmission When using the DMA channels to service the GSC transmitter there is no practical way to disable the Done flag This is because the transmit done flag TDN is set when the transmit FIFO is empty and the last message bit has been transmitted But when using the DMA channel to service the transmitter loads to the TFIFO continue to occur until the byte count reaches 0 This makes it impossible to use TDN as a flag to stop the DMA transfers to TFIFO It
284. eturn random data Special Function Register space is shown in Table 1 and write accesses will have no effect Table 1 SFR Mapping and Reset Values Special Function Registers SFRs include the Port P5 CH CCAPOH CCAP1H CCAP2H CCAP3H 00000000 00000000 XXXXXXXX XXXXXXXX AD7 SEPSTAT 00000000 00000000 XXXXX000 C1CON CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L 00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX ACC AD6 SEPDAT 00000000 00000000 1 2 4 00X00000 00XXX000 X0000000 X0000000 X0000000 X0000000 X0000000 PSW AD5 SEPCON 00000000 00000000 XX000000 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 00000000 00 00000000 00000000 00000000 00000000 P4 AD4 EXICON ACMP 00000000 00000000 X0000000 00000000 SADEN C1CAPOH C1CAP1H C1CAP2H CH1 X0000000 00000000 XXXXXXXX XXXXXXXX 00000000 P3 AD3 IPAH IPA IPH 11111111 00000000 00000000 00000000 X0000000 SADDR C1CAPOL C1CAP1L C1CAP2L C1CAP3L C1CAP4L CL1 00000000 00000000 XXXXXXXX 00000000 2 5 WDTRST IEA 00000000 00000000
285. f instructions will branch to one of four AJMP instructions in a jump table starting at JMP__TBL MOV JMP JMP__TBL AJMP AJMP AJMP AJMP DPTR JMP__TBL A DPTR LABELO LABEL LABEL2 LABEL3 If the Accumulator equals 04H when starting this sequence execution will jump to label LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address 1 2 JMP DPTR 2 48 intel JNB bit el Function Description Example Bytes Cycles Encoding Operation JNC rel Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Jump if Bit Not set If the indicated bit is a zero branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010B The Accumulator holds 56H 01010110B The instruction sequence JNB Pi 3LABELI JNB ACC 3 LABEL2 will cause program execution to continue at the instruction at label LABEL2 3 2 0000 JNB PC PO 3 IF bi 0 THEN PC rel Jump if Carry not set If the carry flag is a zero branch to the address indica
286. f transmission This also requires that IFS contain a value equal to or great er than 8 This method may have the undesirable effect that DEN goes high and disables the external drivers The other alternative is to switch to Raw Transmit mode Then writing OFFH to TFIFO would generate a bigh output for 8 bit times This method would leave DEN active during the transmission of the abort char acter When the receiver detects seven or more consecutive 1s and data has been loaded into the receive FIFO the RCABT flag is set in RSTAT and that frame is ig nored If no data has been loaded into the receive FIFO there are no abort flags set and that frame is just ignored retransmitted frame may immediately fol low an abort character provided the proper flags are used 270427 20 Figure 3 9 NRZI Encoding ntel 83 152 HARDWARE DESCRIPTION 3 3 6 LINE IDLE If 15 or more consecutive 15 are detected by the receiv er the Line Idle bit LNI in TSTAT is set The seven 15 from the abort character may be included when sens ing for a line idle condition The same methods used for sending the Abort character can be used for creating the Idle condition However the values would need to be changed to reflect 15 bit times instead of seven bit times 3 3 7 ACKNOWLEDGEMENT Acknowledgment in SDLC is an implied acknowledge and is contained in the control field Part of the control frame is the sequence number of the next expected f
287. family the 8XC51GB is optimized for control applications Its key features are an analog to digital converter and two programmable counter rays PCA capable of measuring and generating pulse information on ten I O pins Also included are an en hanced serial port for multi processor communications a serial expansion port hardware watchdog timer os cillator fail detection an up down timer counter and a program lock scheme for the on chip program memory Since the 8XC51GB is CHMOS it has two software selectable reduced power modes Idle Mode and Power Down Mode The 8XC51GB used the standard 8051 instruction set and is functionally compatible with the existing MCS 51 family of products This document presents comprehensive description of the on chip hardware features of the 8XCSIGB It be gins with a discussion of how the memory is organized followed by the instruction set and then discusses each of the peripherals listed below Six 8 bit Bidirectional Parallel Ports Three 16 bit Timer Counters with One Up Down Timer Counter Programmable Clock Output Analog to Digital Converter with 8 channels 8 bit resolution compare mode Two Programmable Counter Arrays with Compare Capture Software Timer High Speed Output Pulse Width Modulator Watchdog Timer PCA only Full Duplex Programmable Serial Port with Framing Error Detection Automatic Address Recognition Serial Expansion Port fo
288. fter executing the instruction LCALL SUBRTN at location 0123H the Stack Pointer will contain 09H internal RAM locations 08H and 09H will contain 26H and 01H and the PC will contain 1234H Bytes 3 Cycles 2 Encoding 0001 0010 addr15 addr8 addr7 addr0 Operation LCALL 3 SP lt SP 1 SP lt PC7 9 SP lt SP 1 SP 5 8 lt 5 0 LJMP addr16 Function Long Jump Description LJMP causes an unconditional branch to the indicated address by loading the high order and low order bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the full 64K program memory address space No flags are affected Example label is assigned to the instruction at program memory location 1234H The instruction LJMP JMPADR at location 0123H will load the program counter with 1234H Bytes 3 Cycles 2 Encoding 0000 0010 addri5 addre addr7 addro Operation LIMP PC lt 5 2 51 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOV lt dest byte gt lt src byte gt Function Description Example MOV Bytes Cycles Encoding Operation MOV A direct Bytes Cycles Encoding Operation Move byte variable The byte variable indicated by the second operand is copied into the location specified by the first operand The source
289. fy Write Instructions Some instructions that read a port read the latch and others read the pin Which ones do which The instruc tions that read the latch rather than the pin are the ones that read a value possibly change it and then rewrite it to the latch These are called read modify write instructions Listed on the following page are the read modify write instructions When the destination INPUT lt DATA READ PORT PIN 270897 6 NOTE CHMOS Configuration pFET 1 is turned on for 2 osc periods after mades a 0 10 1 transition During this time pFET 1 also turns on pFET 3 through the inverter to form a latch which holds the 1 pFET 2 is also on Port 2 is similar except that it holds the strong pullup on while emitting 1s that are address bits See text Accessing External Memory Figure 4 Ports 1 3 4 and 5 Internal Pullup Configuration 6 10 ntel 87C51GB HARDWARE DESCRIPTION operand is a port or a port bit these instructions read the latch rather than the pin ANL logical AND e g ANL P1 ORL logical OR e g ORL P2 A XRL logical EX OR e g XRL P3 A JBC jump if bit 1 and clear bit e g JBC P1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 DJNZ decrement and jump if not zero e g DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of Port X CLR PX Y clear bit Y of Port X SETBPX Y set bit Y of Port X
290. g a DMA to or from External Data Memo ry it will complete this DMA before responding to the Hold Request When the C152 responds to the Hold Request it does so by activating a Hold Acknowledge signal This indicates that the C152 will not commence a new DMA to or from External Data Memory while HLD remains active Note that in the Arbiter Mode the C152 does not sus pend program execution at all even if it is executing from external program memory It does not surrender use of its own bus The Hold Request input HLD is at P1 5 The Hold Acknowledge output HLDA is at P1 6 This version of the Hold Hold Acknowledge feature is se lected by setting the control bit ARB in PCON The functions of the ARB and REQ bits in PCON then are Hold Hold Acknowledge Logic 0 0 Disabled 0 1 C152 generates detects 1 0 152 detects HLD generates HLDA 1 1 Invalid 4 3 3 USING THE HOLD HOLD ACKNOWLEDGE The HOLD HOLDA logic only affects tion with external RAM and doesn t affect other opera tions with external R AM such as MOVX instruction Figure 4 6 shows a system in which two 83C152s are sharing a global this system both executing from internal ROM Neither CPU uses the bus except to access the shared and such access 83C152 HARDWARE DESCRIPTION es are done only through DMA operations not by instructio
291. g requires half duplex but half duplex does not require Manchester encoding intel 83C152 HARDWARE DESCRIPTION Table 3 1 dm ENCODING NITION BACKOFF AMBLE NAZI SDLC NIX N NRZ EXT CLIQ Es el T1 IDLE 16 BIT CCITT 32 BIT AUTODIN II amp CKNOWLEDGEMENTNONE O O JO O 1 9 HARDWARE x USER DEFINED otojojojo 1 ojo ojojo ojo x N NjO o 1 ojo ojo N NOT AVAILABLE M OPTIONA NORMALLY PREFERRED mr Q 4 mx on r m zum r Zzm omroz z O ic Um mo T E R M I N l s T I c mr mzoz ADDRESS RECOGNITION NONE ALL 8 BIT 16 BIT COLLISION RESOLUTION NORMAL ALTERNATE DETERMINISTIC INTERNAL 04215 21011215 210 0
292. gister bank select control bits 1 amp 0 Set cleared by software to determine working register bank see Note Symbol Position PSW 2 PSW 1 PSW 0 Name and Significance Overflow User definable flag Parity flag Set cleared by hardware each instruction cycle to indicate an odd even number of bits in the Accumulator i e even parity NOTE The contents of RS1 RS0 enable the working register banks as follows 0 0 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 00H 07H 08H OFH 10H 17H 18H 1FH Figure 3 PSW Program Status Word Register ADDR DATA CONTROL ce READ LATCH INT BUS 270252 2 Port 0 Bit READ LATCH 270252 4 C Port 2 Bit INTERNAL 270252 3 Port 1 Bit ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL PULL UP ALTERNATE INPUT FUNCTION 270252 5 D Port 3 Bit Figure 4 8051 Port Bit Latches and 1 0 Buffers See Figure 5 for details of the internal pullup PORT STRUCTURES AND OPERATION four ports in the 8051 are bidirectional Each con sists of a latch Special Function Registers PO through P3 an output driver and an input buffer The output drivers of Ports and 2 and the input buff ers of Port 0 are used in accesses to external memory In this application Port O outputs the low byte of the 3 6 external memory address time multiplexed with
293. gment error bit see TSTAT NRZI Non Return to Zero inverted a type of data encoding where 0 is represented by a change in the level of the serial link A 1 is represented by no change OVR Overrun error bit see RSTAT PR Protocol select bit see PCON 87H 7 6 5 4 3 2 1 0 Swce wne nea snevpcudaren Po iou PCON 0 IDL Idle bit used to place the C152 into the idle power saving mode PCON 1 PD Power Down bit used to place the C152 into the power down power saving mode PCON 2 GFIEN GSC Flag Idle Enable bit when set enables idle flags 01111110 to be generated be tween transmitted frames in SDLC mode PCON 3 XRCLK External Receive Clock bit used to enable an external clock to be used for only the re ceiver portion of the GSC PCON 4 GAREN GSC Auxiliary Receive Enable bit used to enable the GSC to receive back to back SDLC frames This bit has no effect in CSMA CD mode intel 5 Requester mode bit set to a 1 when C152 is to be operated as the requester station during DMA transfers PCON 6 ARB Arbiter mode bit set to 1 when C152 is to be operated as the arbiter during DMA transfers PCON 7 SMOD LSC mode bit used to double the baud rate on the LSC Priority bit DMA Channel 0 interrupt see Priority bit DMA Channel 1 interrupt see IPNI PGSRE Priority bit for GSC Receive Error interrupt
294. gram loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPL P1 7 DJNZ R2 TOGGLE will toggle P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse will last three machine cycles two for DJNZ and one to alter the pin DJNZ Rn rel Bytes 2 Cycles 2 Encoding 1105 Operation DJNZ PC PO 2 Rn 1 IF Rn gt Oor Rn lt 0 THEN lt rel intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DJNZ direct re Bytes 3 Cycles 2 Encoding direct address Operation DJNZ 2 direct lt direct 1 IF direct gt 0 or direct lt 0 THEN rel INC byte Function Increment Description INC increments the indicated variable by 1 An original value of OFFH will overflow to No flags are affected Three addressing modes are allowed register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins Example Register 0 contains 7EH 011111110B Internal RAM locations and 7FH contain OFFH and 40H respectively The instruction sequence INC GRO INC RO INC GRO will leave register O set to 7FH and internal RAM loc
295. h PCA module 4 The WDT does not drive the Reset pin 10 1 Using the WDT Since the WDT is automatically enabled while the processor is running the user only needs to be con cerned with servicing it The 14 bit counter overflows when it reaches 16383 The WDT increments once every machine cycle This means tbe user must reset the WDT at least every 16383 machine cycles If the user does not wish to use the functionality of the WDT in an application a timer interrupt can be used to reset the WDT To reset the WDT the user must write OTEH and OEIH to WDTRST WDTRST is a write only register The WDT count cannot be read or written Using a timer interrupt is not recommended in applications that make use of the WDT because inter 6 40 87C51GB HARDWARE DESCRIPTION rupts may still be serviced even after a software upset To make the best use of the WDT it should be serviced in those sections of code that will periodically be exe cuted within the time required to prevent a WDT reset 10 2 edd During Power Down and e In Power Down mode the oscillator stops which means the WDT also stops While in Power Down the user does not need to service the WDT There are two meth ods of exiting Power Down by a reset or via a level activated external interrupt which is enabled prior to entering Power Down If Power Down is exited with reset servicing of the WDT should occur as it normally does whenever the 8 51 is reset Ex
296. hat there is activity indicating the link is being used For these reasons zero preamble length is not compati ble with standard CSMA CD protocols When using CSMA CD the BOF is considered part of the pream ble compared to SDLC where the BOF is not part of the preamble This means that if zero preamble length were to be used in CSMA CD mode BOF would be generated It is strongly recommended that zero pream ble length never be used in CSMA CD mode If the preamble contains two consecutive Os the preamble is considered invalid If the C152 detects an invalid pre amble the frame is ignored BOF In CSMA CD the Beginning Of Frame is a part of the preamble and consists of two sequential 1s The purpose of the BOF is to identify the end of the pream ble and indicate to the receiver s that the address will immediately follow intel 83C152 HARDWARE DESCRIPTION ADDRESS The address field is used to identify which messages are intended for which stations The user must assign addresses to each destination and source How the addresses are assigned how they are main tained and how each transmitter is made aware of which addresses are available is an issue that is left to the user Some suggestions are discussed in Section 3 5 5 Generally each address is unique to each station but there are special cases where this is not true In these special cases a message is intended for more than one station These multi targeted me
297. he address recognition circuitry the rest of the frame is ignored and the search continues for another flag If the address does match the address recognition circuitry the address and all subsequent data is passed into the receive FIFO until the EOF flag or an error occurs The address is not stripped and is also passed to RFIFO The address masking registers AMSKO and AMSK1 work in conjunction with ADRO and ADR respective ly to identify don t care bits 1 in any position in the AMSKn register makes the respective bit in the ADR n register irrelevant These combinations can then be used for form group addresses If the masking regis ters are filled with all 1s the C152 will receive all pack ets which is called the promiscuous mode If 16 bit addressing is used AMSKO AMSK1 form one 16 bit address mask 83C152 HARDWARE DESCRIPTION CSMA CD Clock Recovery IDEAL WAVEFORM E 5 z a z a ACTUAL WAVEFORM RECOVERED BIT STREAM CLOCK Figure 3 13A Clock Recovery IDEAL WAVEFORM B 5 2 amp z a ACTUAL WAVEFORM RECOVERED BIT STREAM CLOCK Figure 3 13B Clock Recovery 7 41 ntel 83 152 HARDWARE DESCRIPTION 3 6 GSC Operation 3 6 1 Determining Line Discipline In norma operation the GSC uses full or half duplex operation When using 32 bit CRC GMOD 3 1 operation can only be half duplex If using a 16 bit CRC GMOD 3 0 full duplex is selected by de fault Whe
298. he Program Status Word PSW contains several Status bits that reflect the current state of the CPU The PSW shown in Figure 10 resides in SFR space It con tains the Carry bit the Auxiliary Carry for BCD oper ations the two register bank select bits the Overflow flag a Parity bit and two user definable status flags The Carry bit other than serving the functions of a Carry bit in arithmetic operations also serves as the Accumulator for a number of Boolean operations intel MCS 51 ARCHITECTURAL OVERVIEW The bits RSO and RS1 are used to select one of the four register banks shown in Figure 7 A number of instruc tions refer to these RAM locations as RO through R7 The selection of which of the four banks is being re ferred to is made on the basis of the bits RSO and RS1 at execution time The Parity bit reflects the number of 1s in the Accumu lator P 1 if the Accumulator contains an odd num ber of 1s and P 0 if the Accumulator contains an even number of 1s Thus the number of 1s in the Accu mulator plus P is always even Two bits in the PSW are uncommitted and may be used as general purpose status flags Addressing Modes The addressing modes in the MCS 51 instruction set are as follows DIRECT ADDRESSING In direct addressing the operand is specified by an 8 bit address field in the instruction Only internal Data RAM and SFRs can be directly addressed INDIRECT ADDRESSING In indirect
299. he Special Function Register SFR space is shown in Table 2 Note that not all of the addresses are occupied Unoc cupied addresses may not be implemented on the chip Read accesses to these addresses will in general return random data and write accesses will have an indetermi nate effect User software should not write 1s to these unlisted lo cations since they may be used in future 51 ucts to invoke new features In that case the reset or inactive values of the new bits will always be 0 Order Number 270783 004 intel 8XC52 54 58 HARDWARE DESCRIPTION Table 2 8XC5X SFR Map and Reset Values B 00000000 ACC 00000000 PSW 00000000 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 00000000 XXXXXX00 00000000 00000000 00000000 00000000 SADEN IPH 11111111 X0000000 IE SADDR 00000000 00000000 P2 11111111 0B7H 7 SCON SBUF P1 88H TCON TMOD TLO TL1 THO TH1 00000000 00000000 00000000 00000000 00000000 00000000 SP DPL DPH PCON 87H 11111111 00000111 00000000 00000000 00000000 Timer Registers Control and status bits are contained Interrupt Registers The individual interrupt enable in registers 2 and T2MOD for Timer 2 The reg bits are in the IE register Two priorities can be set for ister pair RCAP2H RCA
300. he end of the interframe space or else an error is assumed and the NOACK bit is set Setting of the TDN bit is also delayed until the end of the interframe space Collisions detected during the interframe space wil also cause to be set If the user software has enabled servicing of the GSC an interrupt is generated when TDN is set TDN will be set at the end of the interframe space if a hard ware based acknowledge is required and received If the GSC is serviced by the CPU the user must time out the 7 27 interframe space and then check TDN before disabling the transmitter or transmit error interrupts NOACK will generate a transmit error interrupt if the transmit ter and interrupts are enabled during the interframe space 3 3 SDLC Operation 3 3 1 SDLC OVERVIEW SDLC is a communication protocol developed by IBM and widely used in industry It is based on a primary secondary architecture and requires that each second ary station have a unique address The secondary sta tions can only communicate to the primary station and then only when the primary station allows communi cation to take place This eliminates the possibility of contention on the serial line caused by the secondary station s trying to transmit simultaneously In the C152 SDLC can be configured to work in either full or half duplex When adhering to strict SDLC pro tocol full duplex is required Full duplex is selected whenever a 16 b
301. he hardware reset needs to be held active for only program execution from where it left off that is at the two machine cycles 24 oscillator periods to complete instruction following the one that invoked the Idle the reset Mode As shown in Figure 26 two or three machine cycles of program execution may take place before the Figure 28 Idle and Power Down Hardware Tabie 23 PCON Power Control Register Address 87H Reset Value 00XX 0000B Not Bit Addressable smopi smopo Por ar Po OL Bit 7 6 5 4 3 2 1 0 Symbol Function SMOD1 Double Baud rate bit When set to a 1 and Timer 1 is used to generate baud rates and the Serial Port is used in modes 1 2 or 3 SMODO When set Read Write accesses to SCON 7 are to the FE bit When clear Read Write accesses to SCON 7 to the SMO bit Not implemented reserved for future use Power Off Flag Set by hardware on the rising edge of Set or cleared by software This flag allows detection of a power failure caused reset must remain above 3V to retain this bit General purpose flag bit General purpose flag bit Power Down bit Setting this bit activates Power Down operation Idle mode bit Setting this bit activates idle modes operation If 1s are written to PD and IDL at the same time PD takes precedence NOTE User software should not write 1s to unimplemented bits These bits may be used in future 8051 family products to invoke new f
302. he logical OR of bits RI and TI in register SCON Neither of these flags is cleared by hardware when the service routine is vectored to The service routine will normally have to determine whether it was RI or TI that generated the interrupt and the bit will have to be cleared in soft ware 8 5 Interrupt Enable Each of these interrupt sources can be individually en abled or disabled by setting or clearing a bit in the Interrupt Enable IE register See Table 17 Note that IE also contains a global disable bit EA If EA is set 1 the interrupts are individually enabled or dis abled by their corresponding bits in IE If EA is clear 0 all interrupts are disabled 8 6 Priority Level Structure Each interrupt source can also be individually pro grammed to one of two priority levels by setting or clearing a bit in the Interrupt Priority IP register shown in Table 18 A low priority interrupt can itself be interrupted by a higher priority interrupt but not by another low priority interrupt high priority inter rupt cannot be interrupted by any other interrupt source Symbol EA Symbol 2 1 1 8XC51FX HARDWARE DESCRIPTION Table 17 IE Interrupt Enable Register Address 0A8H Reset Value 0000 00008 Bit Addressable EA Es Exi Ero 7 6 5 4 3 2 1 0 Enable Bit 1 enables the interrupt Enable Bit 0 dis
303. he receive functions can be tested In Raw Receive the transmitter should be externally connected to the receiver To do this a port pin should be used to enable an external device to connect the two pins together In Raw Receive mode the receiver acts as normal except that all bytes following the BOF are loaded into the receive FIFO including the CRC Also address recognition is not active but needs to be per formed in software If SDLC is selected as the protocol zero bit deletion is still enabled The transmitter still operates as normal and in this mode most of the trans mitter functions and an external transceiver can be test ed This is also the only way that the CRC can be read by the CPU but the CRC error bit will not be set 3 5 7 EXTERNAL DRIVER INTERFACE A signal is provided from the C152 to enable transmit ter drivers for the serial link This is provided for sys tems that require more than what the GSC ports are capable of delivering The voltage and currents that the GSC is capable of providing are the same levels as those for normal port operation The signal used to enable the external drivers is DEN No similar signal is needed for the receiver DEN is active one bit time before transmission begins In CSMA CD DEN remains active for two bit times after the CRC is transmitted In SDLC DEN remains active until the last bit of the EOF is transmitted 3 5 8 JITTER RECEIVE Data jitter is the difference betwe
304. herefore a sin gle write or a series of writes to registers will prevent a DMA from taking place and will continue to prevent a DMA from taking place until at least one instruction is executed which does not write to any DMA register The logic that determines whether the next cycle will be a DMAO cycle cycle or an Instruction Cycle is shown in Figure 4 12 as a pseudo HLL function The statements in Figure 4 12 are executed sequentially un less an condition is satisfied in which case the cor responding return is executed and the remainder of the function is not The return value of 0 1 or 2 is passed to the arbitration logic block in Figure 4 11 to determine which exit path from the block is used arbitration logic if GOO 1 AND mode_logic 0 if 601 1 AND mode logic 1 else return 2 end arbitration logic The return value is based on the condition of the GO bit for each channel and on the value returned by an other function named mode Jogic The algorithm for mode logic is the same for both channels The function is shown in Figure 4 13 as a pseudo HLL function mode logic n where n 0 when the func tion is invoked for DMA channel 0 and n 1 when it s invoked for DMA channel 1 The value returned by this function is either O or 1 and will be passed on to the DMA arbitration logic in Figure 4 12 Note that the arbitration logic as shown in Figure 4 12 always g
305. hus to selectively communicate with just Slave 1 the master must send an address with bit 0 0 e g 1111 0000 Similarly bit 1 0 for Slave 1 but is a don t care for Slave 2 Now to communicate with just Slave 2 an ad dress with bit 1 1 must be used e g 1111 0111 intel 8XC52 54 58 HARDWARE DESCRIPTION Finally for a master to communicate with both slaves at once the address must have bit 0 1 and bit 1 0 Notice however that bit 2 15 don t care for both slaves This allows two different addresses to select both slaves 1111 0001 or 1111 0101 If a third slave was added that required its bit 2 0 then the latter address could be used to communicate with Slave 1 and 2 but not Slave 3 The master can also communicate with all slaves at once with the Broadcast Address It is formed from the logical OR of the SADDR and SADEN registers with zeroes defined as don t cares The don t cares also al low flexibility in defining the Broadcast Address but in most applications a Broadcast Address will be OFFH SADDR and SADEN are located at address OA9H and OB9H respectively On reset the SADDR and SADEN registers are initialized to which defines the Given and Broadcast Addresses as X XXX XXXX all don t cares This assures the serial port to be backwards compatible with other MCS 51 prod ucts which do not implement automatic address recog nition INTERRUPTS The 8 5 has a total of 6
306. if there are more than eight collisions TSTAT 5 UR Underrun If set indicates that in DMA mode the last bit was shifted out of the transmit register and that the DMA byte count did not equal zero When an underrun occurs the transmitter halts without sending the CRC or the end flag TSTAT 6 NOACK No Acknowledge If set indi cates that no acknowledge was received for the previous frame Will be set only if HBAEN is set and no ac knowledge is received prior to the end of the IFS NOACK 5 not set following a broadcast or a multi cast packet TSTAT 7 LNI Line Idle If set ndicates the re ceive line is idle In SDLC protocol it is set if 15 consec utive ones are received In CSMA CD protocol line idle is set GR X D remains high for approximately 1 6 bit times LNI is cleared after a transition on GR XD TxC External Clock input for GSC transmitter UR Underrun flag see TSTAT XRCLK External GSC Receive Clock Enable bit see PCON XTCLK External GSC Transmit Clock Enable bit see GMOD
307. igure 18 IP Interrupt Priority Register in the 8051 IE REGISTER 1 o oo INDIVIDUAL ENABLES DISABLE MCS 51 ARCHITECTURAL OVERVIEW HIGH PRIORITY IP REGISTER INTERRUPT INTERRUPT POLLING SEQUENCE LOW PRIORITY INTERRUPT 270251 17 Figure 19 8051 Interrupt Control System In operation all the interrupt flags are latched into the interrupt control system during State 5 of every ma chine cycle The samples are polled during the follow ing machine cycle If the flag for an enabled interrupt is found to be set 1 the interrupt system generates an LCALL to the appropriate location in Program Memo ry unless some other condition blocks the interrupt Several conditions can block an interrupt among them that an interrupt of equal or higher priority level is already in progress The hardware generated LCALL causes the contents of the Program Counter to be pushed onto the stack and reloads the PC with the beginning address of the service routine As previously noted Figure 3 the service rou tine for each interrupt begins at a fixed location Only the Program Counter is automatically pushed onto the stack not the PSW or any other register Hav ing only the PC be automatically saved allows the pro grammer to decide how much time to spend saving which other registers This enhances the interrupt re sponse time albeit at the expense of increasing the pro grammer s burden of responsibility As a
308. illator frequency Figure 17 shows a simplified functional diagram of the serial port in Mode 0 and associated timing 3 17 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission The internal timing is such that one full machine cycle will elapse between write to SBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during S3 54 and S5 of every machine cycle and high during S6 SI and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift register are shifted to the right one position As data bits shift out to the right zeroes come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initial ly loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX Control block to do one last shift and tben deactivate SEND and set TI Both of these actions occur at S1P1 of the 10th machine cycle after write to SBUF Reception is initiated by
309. imer Counter 2 Control Register Address Bit Addressable Bi Function Reset Value 0000 00008 Tre ExF2 TOLK ExEN2 C T2 2 7 6 5 4 3 2 1 0 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 Timer 2 external set when either capture reload is caused negative transition 2 and EXEN2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 Receive clock fiag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX Start stop control for Timer 2 A logic 1 starts the timer Timer or counter select Timer 2 0 Internal timer OSC 12 or OSC 2 in baud rate gene
310. inhibited To eliminate the possibility of unexpected outputs at the port pins the instruction following the one that invokes Idle should not be one that writes to a port pin or to externa Data RAM POWER DOWN MODE An instruction that sets PCON 1 causes that to be the last instruction executed before going into the Power Down mode In the Power Down mode the on chip oscillator is stopped With the clock frozen all func intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Tabie 4 EPROM Versions of the 8051 and 8052 Device EPROM EPROM Time Required to Name Version Bytes Program Entire E um 8051AH 8751H 8751BH 210V 1275V 4minutes eros i275v tions stopped but the and Special Function Registers are held The port pins output the Program Memory LOCKS values held by their respective SFRs ALE and PSEN In some microcontroller applications it is desirable that output lows the Program Memory be secure from software piracy Intel has responded to this need by implementing a The only exit from Power Down for the 80C51 is a Program Memory locking scheme in some of the MCS hardware reset Reset redefines all the SFRs but does 51 devices While it is impossible for anyone to guaran not change the on chip RAM tee absolute security against all levels of technological sophistication the Program Memory locks in the MCS In the Power Down mode
311. intel MCS 51 MICROCONTROLLER FAMILY USER S MANUAL ORDER NO 272383 002 FEBRUARY 1994 Intel Corporation makes warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein intel retains the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation Intel Corporation and intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Other brands and names are the property of their respective owners Additional copies of this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 c INTEL CORPORATION 1993 MCS 51 MICROCONTROLLER FAMILY USER S MANUAL CONTENTS PAGE CHAPTER 1 MCS 51 Family of Microcontrollers Architectural Overview CHAPTER 2 MCS 51 Programmer s Guide and Instruction Set CHAPTER 3 8051 8052 and 80C51 Hardware Description CHAPTER 4 8XC52 54 58 Hardware Description CHAPTER 5 8XC51FX Hardware Description CHAPTER 6 87C51GB Hardware Description CHAPTER 7
312. intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SJMP rel Function Description Example Bytes Cycles Encoding Operation Short Jump Program control branches unconditionally to the address indicated The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it The label RELADR is assigned to an instruction at program memory location 0123H The instruction 5 RELADR will assemble into location 0100H After the instruction is executed the PC wil contain the value 0123H Note Under the above conditions the instruction following SJMP will be at 102H Therefore the displacement byte of the instruction will be the relative offset 0123H 0102H 21H Put another way an SJMP with a displacement of OFEH would be a one instruction infinite loop 2 2 SJMP 2 2 69 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SUBB A lt src byte gt Function Description Example SUBB Bytes Cycles Encoding Operation Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the Accumulator leaving the result in the Accumulator SUBB sets the carry borrow flag if a borrow is neede
313. inter was decremented to 2FH before being loaded with the value popped 20H Bytes 2 Cycles 2 Encoding 0000 Operation POP direct lt 5 SP SP 1 PUSH direct Function Push onto stack Description Stack Pointer is incremented by one The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer Otherwise no flags are affect ed Example entering an interrupt routine the Stack Pointer contains 09H The Data Pointer holds the value 0123H The instruction sequence PUSH DPL PUSH DPH will leave the Stack Pointer set to OBH and store 23H and O1H in internal RAM locations OAH and OBH respectively Bytes 2 Cycles 2 Encoding 0000 Operation PUSH SP SP 1 SP direct intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET RET Function Return from subroutine Description pops the high and low order bytes of the PC successively from the stack decrementing the Stack Pointer by two Program execution continues at the resulting address generally the instruction immediately following an ACALL or LCALL No flags are affected Example The Stack Pointer originally contains the value OBH Internal RAM locations OAH and OBH contain the values 23H and O1H respectively The instruction RET will leave the Stack Pointer equal to the value 09H Program execution will continue at location 0123
314. interrupt 0 edge is detected transmitted or level activated Cleared when interrupt processed only if transition activated Interrupt 0 Type control bit Set cleared by software to specify falling edge low level triggered external interrupt 0 INTERRUPT CONTROL Figure 9 Timer Counter 0 or 1 in Mode 1 16 Bit Counter 6 15 intel 87C51GB HARDWARE DESCRIPTION allows the Timer to be controlled by external input pin to facilitate pulse width measurements TRx and TFx are control bits in the SRF TCON The GATEx bits are in TMOD There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 MODE 2 Mode 2 configures the Timer register as an 8 bit Coun ter TLx with automatic reload as shown in Figure 10 Overflow from TLx not only sets TFx but also reloads TLx with the contents of THx which is preset by soft ware The reload leaves THx unchanged The counted input is enabled to the timer when or TR1 1 and either GATEx 0 or INTx pin 1 CONTROL Setting GATEx 1 allows the Timer to be controlled by external input INTx pin to facilitate pulse width measurements TRx and TFx are control bits in the SFR TCON The bits are in TMOD There are two different GATE bits one for Timer 1 7 and one for Timer 0 TMOD 3 MODE 3 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in Mode 3 es
315. interrupted program but it would have 1 the interrupt control system thinking interrupt was still in progress The starting addresses of consecutive interrupt service routines are only 8 bytes apart That means if consecu tive interrupts are being used and for exam ple and 1 and if the first interrupt routine is more than 7 bytes long then that routine will bave to execute a jump to some other memory location where the service routine can be completed without overlap ping the starting address of the next interrupt routine 12 8 Interrupt Response Time The INTO and levels are inverted and latched into the Interrupt Flags and IE1 at 55 2 of every machine cycle The level of interrupts 2 through 6 are also latched into the appropriate flags 2 in S5P2 Similarly the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at S5P2 The values are not actually polled by the circuitry until the next machine cycle INTERRUPT INTERRUPT GOES LATCHED ACTIVE The Timer 0 and Timer 1 flags and TF1 are set at S5P2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polied in the same cycle in which the timer overflows If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the re quested service routine wil
316. into the Idle mode In the Idle mode the internal clock signal is gated off to the CPU but not to the Interrupt Timer and Serial Port functions The PCA can be pro grammed either to pause or continue operating during Idle refer to the PCA section for more details The CPU status is preserved in its entirety the Stack Point er Program Counter Program Status Word Accumu lator and all other registers maintain their data during Idle The port pins hold the states they had at the time Idle was activated ALE and PSEN hold at logic high levels There two ways to terminate the Idle Mode Activa tion of any enabled interrupt will cause PCON O to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle The flag bits and GF1 can be used to give an indication if an interrupt occurred during normal oper ation or during Idle For example an instruction that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits intel 8XC51FX HARDWARE DESCRIPTION The other way of terminating the Idle mode is with a The signal at the RST pin clears the IDL bit directly hardware reset Since the clock oscillator is still run and asynchronously At this time the CPU resumes ning t
317. iods Thus a ma chine cycle takes 12 oscillator periods or 1 microsecond if the oscillator frequency is 12 MHz Each state is then divided into a Phase 1 and Phase 2 balf Rise and fall times are dependent on the external load ing that each pin must drive They are approximately 10 nsec measured between 0 8V and 2 0V Propagation delays are different for different pins For a given pin they vary with pin loading temperature and manufacturing lot If the XTAL1 waveform 15 taken as the timing reference propagation delays may vary from 25 to 125 nsec The AC Timings section of the data sheets do not refer ence any timing to the XTAL1 waveform Rather they relate the critical edges of control and input signals to 5 43 8XC51FX HARDWARE DESCRIPTION ESR in OHMS 4 8 12 CRYSTAL FREQUENCY In MHz 270653 29 16 Figure 32 ESR vs Frequency each other The timings published in the data sheets include the effects of propagation delays under the specified test condition ADDITIONAL REFERENCES The following application notes provide supplemental information to this document and can be found in the Embedded Applications handbook 1 AP 125 Designing Microcontroller Systems for Electrically Noisy Environments 2 AP 155 Oscillators for Microcontrollers 3 AP 252 Designing with the 80C51BH 4 AP 410 Enhanced Serial Port on the 83 51 5 415 83C51FA FB PCA Cookbook 6 AB 4
318. ion ad dress a Destination out of range message is written into the List file The JMP A DPTR instruction supports case jumps The destination address is computed at execu tion time as the sum of the 16 bit DPTR register and the Accumulator Typically DPTR is set up with the address of a jump table and the Accumulator is given an index to the table In a 5 way branch for example an integer O through 4 is loaded into the Accumulator The code to be executed might be as follows MOV DPTR JUMP TABLE MOV A JINDEX NUMBER RL A JMP DPTR The RL instruction converts the index number 0 through 4 to an even number on the range 0 through 8 because each entry in the jump table is 2 bytes long JUMP TABLE AJMP CASE 0 AJMP CASE 1 AJMP CASE 2 AJMP CASE 3 AJMP CASE 4 Table 8 shows a single CALL addr instruction but there two of them LCALL and ACALL which differ in the format in which the subroutine address is given to the CPU CALL is a generic mnemonic which can be used if the programmer does not care which way the address is encoded The LCALL instruction uses the 16 bit address format and the subroutine can be anywhere in the 64K Pro gram Memory space The ACALL instruction uses the 11 bit format and the subroutine must be in the same 2K block as the instruction following the ACALL In any case the programmer specifies the subroutine address to the assembler in the same way as a
319. ion is not in progress When 8 bits have been received SEPREN will be cleared by hardware Once the trans mission or reception is complete SEPIF will be set SEPIF remains set until cleared by software SEPIF is also the source of the SEP interrupt Data is transmit ted and received MSB first If the user attempts to read or write the SEPDATA register or write to the SEPCON register while the SEP is transmitting or receiving an error bit is set The SEPFWR bit is set if the action occurred while the SEP was transmitting The SEPFRD bit is set if the action occurred while the SEP was receiving There is no in terrupt associated with these error bits The bit remains set until cleared by software The attempted read or write of the register is ignored The reception of trans mission that was in progress will not be affected 10 0 HARDWARE WATCHDOG TIMER The hardware WatchDog Timer WDT resets the 8XC51GB when it overflows The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset The WDT consists of a 14 bit counter and the WatchDog Timer ReSeT WDTRST SFR The WDT is always enabled and in crements while the oscillator is running There is no way to disable the WDT This means that the user must still service the WDT while testing or debugging an application The WDT is loaded with O when the 8XC51GB exits reset The WDT described in this sec tion is not the Watchdog Timer associated wit
320. is initialized into the system it sends out a message containing its assumed address The format of the message should be such that any station decoding the address recognizes it as a request for initialization If that address is already used the receiving station returns a message with its own ad dress stating that the address in question is already tak en The initializing station then picks another address When the initializing station sends its inquiry for the address check a timer is also started If the timer ex pires before the inquiry is responded to then that sta tion assumes the address chosen is okay ntel 83C152 HARDWARE DESCRIPTION In the second procedure an initializing station asks for an address assignment from the system This requires that some station on the link take care of the task of maintaining a record of which addresses are used This station will be called station 1 When the initializing station called station 2 gets on the link it sends out a message with a broadcast address The format of the message should be such that all other stations on the link recognize it as a request for address assignment Part of the message from station 2 is a random number generated by the station requesting the address Sta tion 2 then examines all received messages for this ran dom number The random number could be the address of the received message or could be within the informa tion section of a broadcast f
321. is instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Register 0 contains 7FH 01111111B Internal RAM locations and 7FH contain 00H and 40H respectively The instruction sequence DEC GRO DEC RO DEC GRO will leave register 0 set to 7EH and internal RAM locations and set to OFFH and 3FH DEC A Bytes 1 Cycles 1 Operation DEC 1 DEC Rn Bytes 1 Cycles 1 Operation DEC Rn lt Rn 1 2 41 intel DEC direct Bytes Cycles Encoding Operation DEC Bytes Cycles Encoding Operation DIV AB Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET to DEC direct direct 1 1 1 DEC RD 1 Divide DIV AB divides the unsigned eight bit integer in the Accumulator by the unsigned eight bit integer in register B The Accumulator receives the integer part of the quotient register B receives the integer remainder The carry and OV flags will be cleared Exception if B had originally contained the values returned in the Accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case The Accumulator contains 251 OFBH or 11111011B and B contains 18 12H or 00010010B The instruction
322. is type of table can have up to 255 entries numbered 1 through 255 Num ber 0 can not be used because at the time the MOVC instruction is executed the PC contains the address of the RET instruction An entry numbered 0 would be the RET opcode itself Boolean Instructions MCS 51 devices contain a complete Boolean single bit processor The internal RAM contains 128 addressable bits and the SFR space can support up to 128 other addressable bits of the port lines are bit address able and each one can be treated as a separate single bit port The instructions that access these bits are not just conditional branches but a complete menu of move set clear complement OR and AND instruc tions These kinds of bit operations are not easily ob tained in other architectures with any amount of byte oriented software 5 51 ARCHITECTURAL OVERVIEW Table 7 A List of the MCS 51 Boolean Instructions Mnemonic Operation Tino ue AN C CAND DR 2 ANL C AND NOT bt 2 _ C C ORbt 2 cst C 2 om Joz 1 Mov wc Mec i c w meo 31 SETB bit C 2 Jump if bit 1 The instruction set for the Boolean processor is shown in Table 7 All bit accesses are by direct addressing Bit addresses through 7FH are in the Lower 128 and bit addresses 80H through FFH are in SFR space
323. it CRC is selected At the end of a valid reset the 16 bit CRC is selected To select half duplex with a 16 bit CRC the receiver must be turned off by user software before transmission The receiver is turned off by clearing the GREN bit RSTAT 1 The receiver needs to be turned off because the address that is transmitted is the address of the secondary station s receiver If not turned off the receiver could mistake the outgoing message as being intended for itself When 32 bit CRCs are used half duplex is the only method available for transmission intel 83C152 HARDWARE DESCRIPTION 3 3 2 SDLC Frame Format The format of an SDLC frame is shown in Figure 3 6 The frame consists of a Beginning of Frame flag Ad dress field Control Field Information field optional a CRC and the End of Frame flag BOF ADDRESS CONTROL meo cnc Figure 3 6 Typical SDLC Frame BOF The begin of frame flag for SDLC is 01111110 It is only one of two possible combinations that have six consecutive ones in SDLC The other possibility is an abort character which consists of eight or more consec utive ones This is because SDLC utilizes a process called bit stuffing Bit stuffing is the insertion of a O as the next bit every time a sequence of five consecutive 1s is detected The receiver automatically removes a O af ter every consecutive group of five ones This removal of the O bit is referred to as bit stripping Bit stuffing is di
324. it and the interrupt system will generate an LCALL to the appropriate service routine provided this hard ware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority level is al ready in progress 2 The current polling cycle is not the final cycle in the execution of the instruction in progress 3 The instruction in progress is RETI or any write to the IE or IP registers Tabie 20 IPH Interrupt Priority High Register IPH Address 0B7H Not Bit Addressable Bit 7 6 Function Not implemented reserved for future PCA interrupt priority high bit Timer 2 interrupt priority high bit Serial Port interrupt priority high bit Timer 1 interrupt priority high bit External interrupt 1 priority high bit Timer 0 interrupt priority high bit External interrupt priority high bit 4 use 5 35 Reset Value X000 0000 2 PSH Prin PxtH Pron 5 3 0 2 1 intel 8XC51FX HARDWARE DESCRIPTION Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condi tion 2 ensures that the instruction in progress will be completed before vectoring to any service routine Con dition 3 ensures that if the instruction in progress is RETI or any write to IE or IP then at least one more instruction will be executed before any interrupt is vec tored to The polling cycle is repeated
325. iting Power Down with an interrupt is significantly different The interrupt is held low which brings the device out of Power Down and starts the oscillator The user must hold the interrupt low long enough for the oscillator to stabilize When the interrupt is brought high the inter rupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high It is suggested that the WDT be reset during the interrupt service routine for the interrupt used to exit Power Down To ensure that the WDT does not overflow within a few states of exiting of powerdown it is best to reset the WDT just before entering powerdown In Idle mode the oscillator continues to run To pre vent the WDT from resetting the 8 51 while in Idie the user should always set up a timer that will periodically exit Idle service the WDT and re enter Idle mode 11 0 OSCILLATOR FAIL DETECT The Oscillator Fail Detect OFD circuitry keeps the 8XC51GB in reset when the oscillator speed is below the OFD trigger frequency The OFD trigger frequency is shown in the data sheet as a minimum and maxi mum If the oscillator frequency is below the minimum the device is held in reset If the oscillator frequency is greater than the maximum the device will not be held in reset If the frequency is between the minimum and maximum it is indeterminate whether the device will be held in re
326. itional pullup is turned on during S1P1 and S1P2 of the cycle in which the transition occurs This is done to increase the transition speed The extra pullup can source about 100 times tbe current that the normal pullup can It should be noted that the internal pullups are field effect transistors not linear resistors The pull up arrangements are shown in Figure 5 In HMOS versions of the 8051 the fixed part of the pullup is a depletion mode transistor with the gate wired to the source This transistor will allow the pin to source about 0 25 mA when shorted to ground In parallel with the fixed pullup is an enhancement mode transistor which is activated during 1 whenever the port bit does 0 to 1 transition During this interval if the port pin is shorted to ground this extra transistor will allow the pin to source an additional 30 mA 2 OSC PERIODS HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 6 A HMOS Configuration The enhancement mode transistor is turned on for 2 osc periods after Q makes a 0 to 1 transition 2 OSC PERIODS INPUT PORT PIN 270252 7 B CHMOS Configuration pFET 1 is turned on for 2 osc periods after Q makes a 0 to 1 transition During this time pFET 1 also turns on pFET 3 through the inverter to form a latch which holds the 1 pFET 2 is also on Figure 5 Ports 1 And 3 HMOS And CHMOS Internal Pullup Contigurations Port 2 is Similar Ex
327. its oscillator under software control by writing a 1 to the PD bit in PCON Another difference is that in the 80 5 the internal clocking circuitry is driven by the signal at XTAL1 whereas in the HMOS versions it is by the signal at XTAL2 The feedback resistor Ry in Figure 33 consists of paral leled n and p channel FETs controlled by the PD bit such that Rr is opened when PD 1 The diodes D1 and D2 which act as clamps to VCC and VSS are parasitic to the FETs The oscillator can be used with the same external com ponents as the HMOS versions as shown in Figure 34 Typically C2 30 pF when the feedback ele ment is a quartz crystal and C1 C2 47 pF whena ceramic resonator is used To drive the CHMOS parts with an external clock source apply the external clock signal to XTAL1 and leave XTAL2 float as shown in Figure 35 270252 26 Figure 33 On Chip Oscillator Circuitry in the CHMOS Versions of the MCS 51 Family intel 270252 28 Figure 35 Driving the CHMOS MCS 51 Parts with External Source The reason for this change from the way the HMOS part is driven can be seen by comparing Figures 29 and 33 In the HMOS devices the internal timing circuits are driven by the signal at XTAL2 In the CHMOS devices the internal timing circuits are driven by the signal at XTAL 1 3 33 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 27 INTERNAL TIMING Figures
328. ive The collision is detected whether the GSC is active or not If the GSC is neither transmitting nor receiving at the time the collision is detected it takes no action un less user software has selected the Deterministic Colli sion Resolution DCR algorithm If DCR has been selected the GSC will participate in the resolution al gorithm GSC Receiving If the GSC is already in the process of receiving a frame at the time the collision is detected its response de pends on whether the first byte of the frame has been transferred into RFIFO yet or not If that hasn t oc curred the GSC simply aborts the reception but takes no other action unless DCR has been selected If DCR has been selected the GSC participates in the resolu tion algorithm If the reception has already progressed to the point where a byte has been transferred to RFIFO by the time the collision is detected the receiver is disabled Receiving a Frame first byte not in RFIFO yet Receiving a Frame first byte already in RFIFO What the GSC was doing Transmitting a Frame first Execute jam backoff byte still in TFIFO Restart if collision count lt 8 Transmitting a Frame first Execute jam backoff byte already taken from TFIFO Set TCDT clear TEN 830152 HARDWARE DESCRIPTION GREN 0 and the Receive Error Interrupt flag RCABT is set If DCR has been selected the GSC participates in the resolution algorithm Incoming bits take 1 2
329. ive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The Serial port receive and transmit registers are both ac cessed at Special Function Register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register HARDWARE DESCRIPTION OF THE 8051 8052 80 51 270252 12 Figure 12 Timer 2 in Capture The serial port can operate in 4 modes Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted re ceived 8 data bits LSB first The baud rate is fixed at 1 12 the oscillator frequency Mode 1 10 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is variable Mode 2 11 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On re ceive the 9th data bit goes into RB8 in Special Functon R
330. ively SERIAL DATA BUFFER The Serial Data Buffer is actually two separate regis ters a transmit buffer and a receive buffer register When data is moved to SBUF it goes to the transmit buffer where it is held for serial transmission Moving a byte to SBUF is what initiates the transmission When data is moved from SBUF it comes from the receive buffer TIMER REGISTERS Register pairs THO TLO and TH2 TL2 are the 16 bit Counting registers for Timer Coun ters 0 1 and 2 respectively CAPTURE REGISTERS The register pair RCAP2H RCAP2L the Cap ture registers for the Timer 2 Capture Mode In this mode in response to a transition at the 80525 T2EX 2 and TL2 are copied into RCAP2H and RCAP2L Timer 2 also has 16 bit auto reload mode and RCAP2H and RCAP2L hold the reload value for this mode More about Timer 2 s features in a later section CONTROL REGISTERS Special Function Registers IP IE TMOD TCON T2CON SCON and PCON contain control and status bits for the interrupt system the Timer Counters and the serial port They are described in later sections MSB HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 LSB L cv ac ns ov and Significance Carry flag Auxiliary Carry flag For BCD operations Position PSW 7 PSW 6 Symbol FO PSW 5 Flag 0 Available to the user for general purposes Re
331. ives precedence to channel 0 over channel 1 If is set and mode logic 0 returns a 1 then a cycle is called without further reference to the situation in channel 1 That is not to say DMAI Cy cle will be interrupted once it has begun Once a cycle has begun be it an Instruction Cycle or Cycle it will be completed without interruption The statements in mode logic n Figure 4 13 are ex ecuted sequentially until an if condition based on the DMA mode programmed into DCONn is satisfied For example if the channel is configured to Burst mode then the first if condition is satisfied so the turn 1 expression is executed and the remainder of the function is not 1 return 0 1 return 1 Figure 4 12 Arbitration Logic 7 56 intel 83C152 HARDWARE DESCRIPTION mode_logic n if DCONn indicates burst_mode return 1 if DCONn indicates extern demand mode if demand flag 1 return 1 else return 0 if DCONn indicates SP_demand mode if SARn SBUF AND RI 1 return 1 if DARn SBUF AND TI 1 return 1 if SARn RFIFO AND RFNE 1 return 1 if DARn TFIFO AND 1 AND previous cycle instruction_cycle return 1 else return 0 if DCONn indicates alt cycles mode 12 DCONm indicates alt_cycles_mode OR GOm 0 if previous cycle instruction_cycle return 1 else return 0 J if previous cycle in
332. j Vec Swpyvotag 0005 24 3592 vss Omwtgoud ____ 27 30 0 0 is 8 bit open drain bi directional I O port As an output port each 25 28 34 37 pin can sink 8 LS TTL inputs 0 pins that have 15 written to them float and NOTES that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to 1 N C pins on PLCC package may be connected to internal die and should not be used in customer applications 2 It is recommended that both Pin and Pin 33 be grounded for PLCC devices external program memory if EBEN is pulled low During accesses to external Data Memory Port 0 always emits the low order address byte and serves as the multiplexed data bus In these applications it uses strong internal pullups when emitting 15 Port 0 also outputs the code bytes during program verification External pullups are required during program verification 7 14 intel 83C152 HARDWARE DESCRIPTION PIN DESCRIPTION Continued Port 1 Port 1 is an 8 bit bidirectional port with internal pullups Port 1 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current on the data sheet because of the internal pullups Port 1 also serves the functions of various special features of the
333. l RAM Ports 1 and 2 are used for normal I O Registers O and 1 contain 12H and 34H Location 34H of the external RAM holds the value 56H The instruction sequence MOVX A GRI MOVX copies the value 56H into both the Accumulator and external RAM location 12H 2 58 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET A GRi Bytes 1 2 Encoding 1110 001i Operation gt 1 8 A DPTR 5 Encoding 111010000 Operation MOVX 3 gt 1 8 MOVX Bytes Encoding 1111 Operation B RD lt A MOVX DPTR A Bytes 1 Cycles 2 Encoding Operation DPTR lt 2 59 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MUL Function Multiply Description MUL AB multiplies the unsigned eight bit integers in the Accumulator and register B The low order byte of the sixteen bit product is left in the Accumulator and the high order byte in If the product is greater than 255 the overflow flag is set otherwise it is cleared The carry flag is always cleared Example Originally the Accumulator holds the value 80 50H Register B holds the value 160 OAOH The instruction MUL AB will give the product 12 800 3200H so B is changed to 32H 00110010B and the Accumula tor is cleared The overflow flag is set carry is cleared Bytes 1 Cycles 4
334. l be the next instruction to be executed The call itself takes two cycles Thus a mini mum of three complete machine cycles elapses between activation of an external interrupt request and the be ginning of execution of the service routine s first in struction See Figure 34 A longer response time would result if the request is blocked by one of the 3 conditions discussed in the In terrupt Processing section If an interrupt of equal or higher priority level is already in progress the addition al wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instruc tions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or write to IE or IP the additional wait time cannot be more than 5 cycles a maximum of one or more cycles to complete the in struction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus in a single interrupt system the response time is always more than 3 cycles and less than 9 cycles INTERRUPT ROUTINE VECTOR ADDRESS 270897 34 This is the fastest possible response when C2 is the final cycle of an instruction other than RET or write IE or IP Figure 34 Interrupt Response Timing Diagram 87C51GB HARDWARE DESCRIPTION 13 0 RESET The reset input is the RESE
335. l memory accesses Otherwise the pullup FET is off Consequent ly PO lines that are being used as output port lines are open drain Writing a 1 to the bit latch leaves both output FETs off so the pin floats In that condition it can be used a high impedance input Because Ports 1 2 and 3 have fixed internal pullups they are sometimes called quasi bidirectional ports When configured as inputs they pull high and will source current IIL in the data sheets when externally pulled low Port 0 on the other hand is considered true bidirectional because when configured as an in put it floats All the port latches in the 8051 have 1s written to them by the reset function If a 0 is subsequently written to a port latch it can be reconfigured as an input by writing a to it Writing to a Port In the execution of an instruction that changes the val ue in a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction How ever port latches are in fact sampled by their output buffers only during Phase 1 of any clock period Dur ing Phase 2 the output buffer holds the value it saw during the previous Phase 1 Consequently the new value in the port latch won t actually appear at the output pin until the next Phase 1 which will be at 51 1 of the next machine cycle See Figure 39 in the Internal Timing section If the change requires a 0 to 1 transition in Port 1 2 or 3 an add
336. label or as a 16 bit constant The assembler will put the address into the correct format for the given instructions Subroutines should end with a RET instruction which returns execution to the instruction following the CALL RETI is used to return from an interrupt service rou tine The only difference between RET and RETI is that RETI tells the interrupt control system that the interrupt in progress is done there is no interrupt in progress at the time RETI is executed then the RETI is functionally identical to RET Table 9 shows the list of conditional jumps available to the MCS 51 user All of these jumps specify the desti nation address by the relative offset method and so are limited to a jump distance of 128 to 127 bytes from the instruction following the conditional jump instruc tion Important to note however the user specifies to the assembler the actual destination address the same way as the other jumps as a label or a 16 bit constant intel MCS 51 ARCHITECTURAL OVERVIEW Table 9 Conditional Jumps in MCS 51 Devices Addressing Modes Execution JZ rel Jump if A 0 Accumulator only sss JNZ rel Accumulator only 2 DJNZ byte rel Decrement andjumpitnotzero x x 2 CINE A bye e JumpifA bye x x 2 CINE lt byte gt datarel bye data x x 2 There is no Zero bit in the PSW JZ and JNZ inst
337. ld be ignored Setting the run flag TRx does not clear these registers MODE 1 Mode 1 is the same as Mode 0 except that the Timer register uses all 16 bits In this mode and TLx are cascaded there is no prescaler Refer to Figure 9 As the count rolls over from all 1s to all Os it sets the timer interrupt flag TFO or TF1 The counted input is enabled to the timer when TRO or TR1 1 and either GATEx 0 or INTx pin 1 Setting GATEx 1 Table 5 TCON Timer Counter Control Register Address 88H Bit Addressable TR tro TRO 11 rri igo 7 6 5 4 3 2 1 0 Bit Symbol Function Reset 0000 0000B TF1 Timer 1 overflow Flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TFO Timer 0 overflow Flag Set by hardware on Timer Counter 0 overflow Cleared by hardware when processor vectors to interrupt routine TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off IE1 Interrupt 1 flag Set by hardware when external interrupt 1 edge is detected transmitted or level activated Cleared when interrupt processed only if transition activated IT1 Interrupt 1 Type control bit Set cleared by software to specifiy falling edge low level triggered external interrupt 1 IEO Interrupt 0 flag Set by hardware when external
338. le data byte whether it takes 1 or 2 machine cycles Associated with each channel are seven SFRs shown in Figure 4 1 SARLn and SARHn holds the low and high bytes of the source address Taken together they form a 16 bit Source Address Register DARLn and DARHn hold the low and high bytes of the destination address and together form the Destination Address Register BCRL and BCRHn hold the low and high bytes of the number of bytes to be transferred and together form the Byte Count Register DCONn contains control and flag bits Two bits in DCONn are used to specify the physical destination of the data transfer These bits are DAS Destination Address Space and IDA Increment Des tination Address If DAS 0 the destination is in data memory external to the C152 If DAS 1 the destination is internal to the C152 If DAS 1 and IDA 0 the internal destination is a Special Function Register SFR If DAS 1 and IDA 1 the inter nal destination is in the 256 byte data RAM In any case if IDA 1 the destination address is automatically incremented after each byte transfer If IDA 0 it is not 7 48 Two other bits in DCONn specify the physical source of the data to be transferred These are SAS Source Address Space and ISA Increment Source Address If SAS 0 the source is in data memory external to the C152 If SAS 1 the source is internal If SAS 1 and ISA 0 the internal source is an SFR If SAS
339. led through the register SEPCON SEPDAT contains data for the Serial Expansion Port and SEPSTAT is used to monitor its status Interrupt Registers The individual interrupt enable bits are in the IE and IEA registers One of four priori ty levels can be selected for each interrupt using the IP IPA and registers The EXICON register controls the selection of the activation polarity for ex ternal interrupts two and three Analog to Digital Converter Registers The results of A D conversions are placed in registers AD0 AD1 87C51GB HARDWARE DESCRIPTION channels 0 through 7 respectively The register ACMP contains the results of the A D comparison feature ACON is the control register for A D conversions Power Control Register PCON controls the Power Re duction Modes Idle and Power Down Oscillator Fail Detect Register The OSCR register is used both to monitor the status of the OFD circuitry and to disable the feature Watchdog Timer Register The WatchDog Timer ReSeT WDTRST register is used to keep the watch dog timer from periodically resetting the part AD2 AD3 AD5 AD6 and AD7 for analog Table 3 Alternate Port Functions O Alternate Function P0 0 ADO PO 7 AD7 Multiplexed Byte of Address Data for external memory P1 0 T2 Timer 2 External Clock input Clockout 1 1 2 Timer 2 Reload Capture Direction Control P1 2 ECI PC
340. lision is detected is that a 1 gets shifted into the TCDCNT Transmit Collision Detect Count register from the right Thus if the software cleared TCDCNT before telling the GSC to transmit then TCDCNT keeps track of how many times the transmission had to be aborted because of collisions TCDCNT 00000000 first attempt 00000001 first collision 00000011 second collision 00000111 third collision 00001111 fourth collision 11111111 After TCDCNT gets a 1 shifted into it the logical AND of TCDCNT and PRBS is loaded into a count down timer named BKOFF PRBS is the name of an SFR which contains the output of a pseudo random binary sequence generator Its function is to provide a random number for use in the backoff algorithm Thus on the first collision BKOFF gets loaded random ly with either 00000000 or 00000001 If there is a sec ond collision it gets loaded with the random selection of 00000000 00000001 00000010 or 00000011 On the third collision there will be a random selection among 8 possible numbers On the fourth among 16 etc Figure 3 5 shows the logical arrangement of PRBS TCDCNT and BKOFF BKOFF starts counting down from its preload value counting slot times At any time the current value in BKOFF can be read by the CPU but CPU writes to BKOFF have no effect While BKOFF is counting down if its current value is not 0 transmission is dis abled The output signal BKOFF 0 is asserted when BKOFF reaches
341. llups and in that state can be used as inputs As inputs Port 5 pins that are externally being pulled low will source current ly the data sheet because of the internal pullups Port 5 is also the multiplexed low order address and data bus during accesses to external program memory if EBEN is pulled high In this application it uses strong pullups when emitting 1s Port 6 Port 6 is an 8 bit bi directional port with internal pullups Port 6 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 6 pins that are externally pulled low will source current lj on the data sheet because of the internal pullups Port 6 emits the high order address byte during fetches from external Program Memory if EBEN is pulled high In this application it uses strong pullups when emitting 1s EBEN E Bus Enable input that designates whether program memory fetches take place via Ports O and 2 or Ports 5 and 6 Table 2 1 shows how the ports are used in conjunction with EBEN EPSEN E bus Program Store Enable is the Read strobe to external program memory when EBEN is high Table 2 1 shows when EPSEN is used relative to PSEN depending on the status of EBEN and EA NOTES 1 N C pins on PLCC package may be connected to internal die and should not be used in customer applications 2 It is recommended that both Pin 3 and Pin 33 be grounded for PLCC
342. loaded in the most significant seven bits Complete interframe space is obtained by counting this seven bit number down to zero twice A user software read of this register will give a value where the seven most sig nificant bits gives the current count value and the least significant bit shows a one for the first count down and a zero for the second count The value read may not be valid as the timer is clocked in periods not necessarily associated with the CPU read of IFS Loading this reg ister with zero results in 256 bit times MYSLOT Slot Address Register 7 6 5 4 3 2 1 0 sas sat Figure 3 15 MYSLOT MYSLOT 0 1 2 3 4 5 Slot Address The ad dress bits choose 1 of 64 slot addresses Address 63 has the highest priority and address 1 has the lowest value of zero will prevent a station from transmitting during the collision resolution period by waiting until all the possible slot times have elapsed The user soft ware normally initializes this address in the operating software MYSLOT 6 DCR Deterministic Collision Resotu tion Algorithm When set the alternate collision reso lution algorithm is selected Retriggering of the IFS on reappearance of the carrier is also disabled When using this feature Alternate Backoff Mode must be selected and several other registers must be initialized User software must initialize TCDCNT with the maximum numb
343. loats the pin and allows it to be used as a high impedance input Because Ports 1 through 3 have fixed internal pullups they are sometimes call quasi bidirectional ports 5 8 When configured as inputs they pull high and will source current JIL in the data sheets when externally pulled low Port 0 on the other hand is considered true bidirectional because it floats when configured as an input All the port latches have 1s written to them by the reset function If a 0 is subsequently written to port latch it can be reconfigured as an input by writing a 1 to it 4 2 Writing to a Port In the execution of an instruction that changes the value in a port latch the new value arrives at the latch during State 6 Phase 2 of the final cycle of the instruc tion However port latches are in fact sampled by their output buffers only during Phase 1 of any clock period During Phase 2 the output buffer holds the value it saw during the previous Phase 1 Consequently the new value in the port latch won t actually appear at the output pin until the next Phase 1 which will be at S1P1 of the next machine cycle Refer to Figure 3 For more information on internal timings refer to the CPU Tim ing section 6XC51FX HARDWARE DESCRIPTION STATE 5 STATE 6 STATE 1 STATE 2 wis sia kh STATE 5 p1 P2 22 2 2 22 pi 2 p2 P 2 P1 P2 P3 INPUTS SAMPLED R
344. ly being pulled low will source current on the data sheet because of the pullups Port 3 also serves the functions of various special features of the MCS 51 Family as listed below Pim Name _ Serial input line Serial output line External interrupt O External interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe Port 4 Port 4 is 8 bit bi directional I O port with internal pullups Port 4 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 4 pins that are externally being pulled low will source current on the data sheet because of the internal pullups In addition Port 4 also receives the low order address bytes during program verification NOTES 1 N C pins on PLCC package may be connected to internal die and should not be used in customer applications 2 It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices 7 15 intel 83C152 HARDWARE DESCRIPTION PIN DESCRIPTION Continued RST Reset input A logic low this pin for three machine cycles while the oscillator is running resets the device An internal pullup resistor permits a power on reset to be generated using only an external capacitor to Vss Although the GSC recognizes the reset after thr
345. m Status Word PSW select which register bank is in use This allows more efficient use of code space since register instruc tions are shorter than instructions that use direct ad dressing 6 4 When an instruction accesses an internal location above address 7FH the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction Instruc tions that use direct addressing access SFR space For example MOV OAOH data accesses the SFR at location which is P2 In structions that use indirect addressing access the upper 128 bytes of data RAM For example MOV GRO data intel 87C51GB HARDWARE DESCRIPTION where R0 contains 0A0H accesses the data byte at ad latches timers peripheral controls etc These registers dress rather than P2 whose address is can only be accessed by direct addressing Sixteen ad Note that stack operations are examples of indirect ad dresses in SFR space are both byte and bit addressable dressing so the upper 128 bytes of data RAM are avail The bit addressable SFRs are those whose address ends able as stack space in 0008 The bit addresses in this area are 80H through OFFH 3 0 SPECIAL FUNCTION REGISTERS Not all of the addresses are occupied Unoccupied ad dresses are not implemented on the chip Read accesses A map of the on chip memory area called by the SFR to these addresses will in general r
346. m state until the oscillator has started and the internal reset algorithm has written 15 to them Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location This is because the SFRs spe cifically the Program Counter may not get properly initialized POWER SAVING MODES OF OPERATION For applications where power consumption is critical the CHMOS version provides power reduced modes of operation as a standard feature The power down mode in HMOS devices is no longer a standard feature and is being phased out CHMOS Power Reduction Modes CHMOS versions have two power reducing modes Idle and Power Down The input through which back up power is supplied during these operations is VCC Figure 27 shows the internal circuitry which imple ments these features In the Idle mode IDL 1 the oscillator continues to run and the Interrupt Serial Port and Timer blocks continue to be clocked but the intel clock signal is gated off to the CPU In Power Down PD 1 the oscillator is frozen The Idle and Power Down modes are activated by setting bits in Special Function Register PCON The address of this register is 87H Figure 26 details its contents In the HMOS devices the PCON register only contains SMOD The other four bits are implemented only in the CHMOS devices User software should never write 1 to unimplemented bits since they may be used in future MCS
347. matches the sending stations address through the use of the address masking registers The receiver must be disabled by the user while transmitting if any of these conditions will occur unless the user wants a station to receive its own transmission The receiver is disabled by clearing GREN and GAREN if used Half duplex operation in the C152 is supported with either 16 bit or 32 bit CRCs Whenever a 32 bit CRC is selected only half duplex operation can be sup ported by the GSC It is possible to simulate full duplex operation with a 32 bit CRC but this would require that the CRC be performed with software Calculating the CRC with the CPU would greatly reduce the data rates that could be used with the GSC Whenever a 16 bit CRC is selected full duplex operation is automati cally chosen and the GSC must be reconfigured if half duplex operation is preferred 3 5 2 PLANNING FOR NETWORK CHANGES AND EXPANSIONS complete explanation on how to plan for network expansion will not be covered in this manual as there are far too many possibilities that would need to be discussed But there are several areas that will have major impact when allowing for changes in the system In cases where there will never be any changes allowed 7 35 expansion plans become a mute issue However it is strongly suggested that there always be some allowance for future modifications Some of the general areas that will impact the overall scheme on how
348. mbinations the Accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant The Accumulator contains 34H Register 7 contains 56H The first instruction in the se quence Brey ee des R7 60H NOT_ EQ JC REQ LOW R7 sets the carry flag and branches to the instruction at label NOT By testing the carry flag this instruction determines whether R7 is greater or less than 60H If the data being presented to Port 1 is also 34H then the instruction WAIT A P1 WAIT clears the carry flag and continues with the next instruction in sequence since the Accumula tor does equal the data read from P1 If some other value was being input on P1 the program will loop at this point until the P1 data changes to 34H 3 2 10110101 PC 3 IF A lt gt direct THEN PC PC relative offset IF A lt direct 2 35 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CJNE A data rei Bytes 3 Cycles 2 Encoding 1011 immediate data Operation PO PO 3 IF A lt gt data THEN relative offset IF A lt data THEN lt 1 ELSE C 0 Rn data rel Bytes 3 Cycles 2 Encoding 1011 1 immediate data Operation PC 3 lt gt data PC P
349. mer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software Receive clock flag When set causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 amp 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 amp 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable flag When set allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port 2 0 causes Timer 2 to ignore events at T2EX Software START STOP control for Timer 2 A logic 1 starts the Timer Timer or Counter select 0 Internal Timer 1 External Event Counter falling edge triggered Capture Reload flag When set captures will occur on negative transitions at 2 if EXEN2 1 When cleared Auto Reloads will occur either with Timer 2 overflows or negative transitions at 2 when 2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the Timer is forced to Auto Reload on Timer 2 overflow intel MCS9 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TIMER COUNTER 2 SET UP Except for the baud rate generator mode the values given for T2CON do not include the setting of the TR2 bit Therefore bit TR2 m
350. mp Description AJMP transfers program execution to the indicated address which is formed at run time by concatenating the high order five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP Example label is at program memory location 0123H The instruction JMPADR is at location 0345H and will load the PC with 0123H Bytes 2 Cycles 2 Encoding 10 0001 a7 a6 a5 a4 a2 a1 Operation AJMP PC 2 page address ANL lt dest byte gt lt src byte gt Function Logical AND for byte variables Description ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Ifthe Accumulator holds 11000011B and register 0 h
351. mpleted or else another interrupt will be generated 8 2 Timer interrupts Timer O and Timer 1 Interrupts are generated by TFO and TF 1 in register TCON which set by a rollover in their respective Timer Counter registers except see Timer 0 in Mode 3 When a timer interrupt is generat ed the flag that generated it is cleared by the on chip hardware when the service routine is vectored to Timer 2 Interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared in software 5 33 8XC51FX HARDWARE DESCRIPTION 8 3 PCA Interrupt The PCA interrupt is generated by the logical OR of CF CCFO CCF1 2 CCF3 and CCF4 in register CCON None of these flags is cleared by hardware when the service routine is vectored to Normally the service routine will have to determine which bit flagged the interrupt and clear that bit in software The PCA interrupt is enabled by bit EC in the Interrupt Enable register see Table 16 In addition the CF flag and each of the CCFn flags must also be enabled by bits ECF and ECCFm in registers CMOD and CCAPMn respectively in order for that flag to be able to cause an interrupt 8 4 Serial Port Interrupt The serial port interrupt is generated by t
352. mpling system allows a jitter tolerance of 1 sample for transitions that are 1 2 bit time apart and 2 samples for transitions that are 1 bit time apart 1 1 MANCHESTER 1 Narrow Pulses A valid Manchester waveform must stay high or low for at least a half bit time nominally 4 sample times Jitter tolerance allows a waveform which stays high or low for 3 sample times to also be considered valid A sample sequence which shows a second transition only 1 or 2 sampie times after the previous transition is con sidered to be the result of a collision Thus sample sequences such as 0000110000 and 111101111 are inter preted as collisions The GSC hardware recognizes the collision to have oc curred within 3 8 to 1 2 bit time following the second transition Missing 0 1 Transition 0 to 1 transition is expected to occur at the center of any bit cell that begins with 0 If the previous 1 0 transition occurred at the bit cell edge a jitter tolerance of 1 sample is allowed Sample sequences such as 1111 00001111 and 1111 000001111 are valid where 7 indicates a bit cell edge Sequences of the form 1111 000000X XX are interpreted as collisions For these kinds of sequences the GSC recognizes the collision to have occurred within 1 to 1 1 8 bit times after the previous 1 10 0 transition If the previous 1 10 0 transition occurred at the center of the previous bit cell a jitter tolerance of
353. n whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type the contents of or 1 in the current register bank provide eight bit address multiplexed with data on Eight bits are sufficient for external 1 0 expansion decoding or for a relatively small RAM array For somewhat larger arrays any output port pins can be used to output higher order address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instruction the Data Pointer generates a sixteen bit address P2 outputs the high order eight address bits the contents of DPH while P0 multiplexes the low order eight bits DPL with data The P2 Special Function Register retains its previous con tents while the P2 output buffers are emitting the contents of DPH This form is faster and more efficient when accessing very large data arrays up to 64K bytes since no additional instructions are needed to set up the output ports It is possible in some situations to mix the two MOVX types large RAM array with its high order address lines driven by P2 can be addressed via the Data Pointer or with code to output high order address bits to P2 followed by a instruction using An external 256 byte RAM using multiplexed address data lines e g an Intel 8155 RAM I O Timer is connected to the 8051 Port 0 Port 3 provides control lines for the externa
354. n ROM devices Erasing the EPROM also erases the Encryption Array and the Lock Bits returning the part to full functionali ty 8XC51FX HARDWARE DESCRIPTION Table 24 C51FX Program Protection Device LockBits Encrypt Array _83051FA None Noe 13 0 ONCETM MODE The ONCE ON Circuit Emulation mode facilitates testing and debugging of systems using the CSIFX without having to remove the device from the circuit The ONCE mode is invoked by 1 Pulling ALE low while the device is in reset and PSEN is high 2 Holding ALE low as RST is deactivated While the device is in ONCE mode the Port 0 pins go into a float state and the other port pins ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored after a valid reset is ap plied Table 25 Lock Bits Program Lock Bits M M P Programmed U Unprogrammed Any other combination of the Lock Bits is not defined Protection Type U U U No program lock features enabled Code verity wili still be encrypted by the encryption array if programmed instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset and further programming of the EPROM is disabled a P P U Sameas2al
355. n Regis ters SFRs These enhancements include a high speed multi protocol serial communication interface two channels for DMA transfers HOLD HLDA bus con trol a fifth L O port expanded data memory and ex panded program memory In addition to a standard UART referred to here as Local Serial Channel LSC the 83C152 has an on board multi protocol communication controller called the Global Serial Channel GSC The GSC interface supports SDLC CSMA CD user definable protocols and a subset of HDLC protocols The GSC capabilities include address recognition collision resolution CRC generation flag generation automatic retransmission and a hardware based acknowledge feature This high speed serial channel is capable of implementing the Data Link Layer and the Physical Link Layer as shown in the OSI open systems communication model This model can be found in the document Reference Model for Open Systems Interconnection Architecture JSO TC97 SC16 N309 The DMA circuitry consists of two 8 bit chan nels with 16 bit addressability The control signals Read RD Write WR hold and hold acknowledge HOLD HLDA are used to access external memory The DMA channels are capable of addressing up to 64K bytes 16 bits The destination or source address can be automatically incremented The lower 8 bits of the address are multiplexed on the data bus Port 0 and the upper eight bits of address will be on Port 2 Data is tra
356. n Section 3 6 5 Each interrupt is assigned a fixed location in Program Memory and the interrupt causes the CPU to jump to that location All the interrupt flags are sampled at 55 2 of every machine cycle and then the samples sequentially polled during the next machine cycle If more than one interrupt of the same priority is active the one that is highest in the polling sequence is serv iced first The interrupts and their fixed locations in Program Memory are listed below in the order of their polling sequence RFNE 0 nore GSCRV RDN 1 270427 43 CRCE AE a OVR 270427 44 pa 0 GSCTV TDN 1 270427 45 270427 46 DONE 1 777 270427 47 DONE DCON1 1 270427 48 Figure 5 1 Six New Interrupts the 8 152 External Interrupt 0 GSC Receive Valid Timer 0 Overflow GSC Receive Error Channel 0 Done External Interrupt 1 GSC Transmit Valid DMA Channel 1 Done Timer 1 Overflow GSC Transmit Error UART Transmit Receive Note that the locations of the basic 8051 interrupts are the same as in the rest of the MCS 51 Family And relative to each other they retain their same positions in the polling sequence The locations of the new interrupts all follow the loca tions of the basic 8051 interrupts in Program Memory but they are interleaved with them in the polling se quence To support the new i
357. n in Figure 3 each interrupt is assigned a fixed location in Program Memory The interrupt causes the CPU to jump to that location where it commences exe cution of the service routine External Interrupt 0 for example is assigned to location 0003H If External In terrupt 0 is going to be used its service routine must begin at location 0003H If the interrupt is not going to be used its service location is available as general pur pose Program Memory 0033H 0028H 0023H INTERRUPT LOCATIONS 001BH 8 BYTES 0013H 0008H 0003H 0000H 270251 3 Figure 3 MCS 51 Program Memory The interrupt service locations are spaced at 8 byte in tervals 0003H for External Interrupt 0 000BH for Timer 0 0013H for External Interrupt 1 001BH for Timer 1 etc If an interrupt service routine is short enough as is often the case in control applications it can reside entirely within that 8 byte interval Longer service routines can use a jump instruction to skip over subsequent interrupt locations if other interrupts are in use The lowest 4K or 8K or 16K bytes of Program Mem ory can be either in the on chip ROM or in an external ROM This selection is made by strapping the EA Ex ternal Access pin to either Vcc or Vss In the 4K byte ROM devices if the E pin is strapped to then program fetches to addresses 0000H through 0FFFH are directed to the internal ROM Pro gram fetches to addresses 1000H thro
358. n on each serial port mode refer to the Hardware Description of the 8051 8052 and 80C51 7 1 Framing Error Detection Framing Error Detection allows the serial port to check for valid stop bits in modes 1 2 3 missing stop bit can be caused for example by noise on the serial lines or transmission by two CPUs simultaneously If a stop bit is missing a Framing Error bit FE is set The FE bit can be checked in software after each recep tion to detect communication errors Once set the FE bit must be cleared in software A valid stop bit will not clear FE The FE bit is located in SCON and shares the same bit address as SMO Control bit SMODO in the PCON reg ister location PCON 6 determines whether the SMO or FE bit is accessed If SMODO 0 then accesses to SCON 7 to SMO If SMODO 1 then accesses to SCON 7 are to FE 7 2 Multiprocessor Communications Modes 2 and 3 provide a 9 bit mode to facilitate multi processor comunication The 9th bit allows the control ler to distinguish between address and data bytes The 9th bit is set to 1 for address bytes and set 0 for data bytes When receiving the 9th bit goes into RB8 in SCON When transmitting 8 is set or cleared in software The serial port can be programmed such that when the stop bit is received the serial port interrupt will be acti vated only if the received byte is an address byte RB8 1 This feature is enabled by setting the S
359. n sequence The AIF flag is set upon completion of the channel 7 conversion AIF will flag an interrupt if the A D interrupt is enabled Once a conversion cy cle is completed a new cycle begins starting with the lowest channel If the user wishes each channel to be converted only once the ACE bit should be cleared Clearing ACE stops all A D conversion activity If a new A D cycle begins the result of the previous con version will be overwritten In external mode the A D conversions begin when a falling edge is detected at the TRIGIN pin There is no edge detector on the TRIGIN pin is it sampled once every machine cycle A negative edge is recognized when TRIGIN is high in one machine cycle and low in the next For this reason TRIGIN should be held high for at least one machine cycle and low for one machine cycle Once the falling 6 22 edge is detected the A D conversions begin on the next machine cycle and complete when channel 7 is convert ed After channel 7 is converted AIF is set and the conversions halt until another trigger is detected while 1 External triggers are ignored while conver sion cycle is in progress 6 4 A D Input Modes The 8XC51GB two input modes Scan mode and Select mode Clearing AIM places the 8XC51GB Scan mode In Scan mode the analog conversions occur in the sequence ACHO ACH1 2 ACH3 ACH4 ACHS ACH6 and 7 The result of each analog conversion is placed i
360. n set this bit allows Timer 2 to be configured up down counter Bit OVERFLOW N T T TIMER 2 LRCAP2H INTERRUPT 270783 2 LJ LA Y TIMER 2 T T INTERRUPT RCAP2H RCAPZL UP COUNTING RELOAD VALUE COUNT DIRECTION 1 UP 2 270783 3 Figure 3 2 Auto Reload Mode DCEN 1 4 7 8 52 54 58 HARDWARE DESCRIPTION 20 T2MOD 1 Timer 2 Interrupt 270783 6 Figure 4 Timer 2 in Ciock Out Mode Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 3 In this mode the T2EX pin controls the direction of count logic 1 at T2EX makes Timer 2 count up The timer will overflow at and set the TF2 bit This overflow also causes the 16 bit value in RCAP2H and RCAP2L to be re loaded into the timer registers TH2 and TL2 respec tively A logic 0 at T2EX makes Timer 2 count down Now the timer underflows when 2 and TL2 equal the values stored in RCAP2H and RCAP2L The under flow sets the TF2 bit and causes OFFFFH to be reload ed into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows This bit can be used as a 17th bit of resolu tion if desired In this operating mode EXF2 does not flag an interrupt BAUD RATE GENERATOR Timer 2 is selected as the baud rate generator by setting TCLK and or RCLK in T2CON Table 3 Note that the baud rates for transmit and receive can
361. n sink large amounts of current If these ports are to be used as inputs and externally driven high while in reset the user should be aware of possible contention simple solution is to use open collector interfaces with these port pins or to buffer the inputs Port 0 differs from the other ports in not having inter nal pullups The pullup FET in the PO output driver is used only when the port is emitting 1s during external memory accesses Otherwise the pullup FET is off Consequently PO lines that are being used as output ees STATE 6 p1 P2 STATE 1 p1 2 P1 P2 2 1 2 1 1 2 2 port lines are open drain Writing a 1 to the bit latch leaves both output FETs off which floats the pin and allows it to be used as a high impedance input Because Ports 1 through 5 have fixed internal pullups they are sometimes called quasi bidirectional ports When configured as inputs they pull high and will source current in the data sheets when externally pulled low Port 0 on the other hand is considered true bidirectional because it floats when configured as an input The latches for ports 0 and 3 have 1s written to them by the reset function If a 0 is subsequently written to a port latch it can be reconfigured as an input by writing a 1 to it 4 2 Writing to a Port In the execution of an instruction that changes the val ue in a port latch the new value ar
362. n the corresponding analog result register ADO ADI AD2 AD3 AD4 ADS AD6 and AD7 Setting AIM activates Select mode In Select mode one of the lower 4 analog inputs is con verted four times After the first four conversions are complete the cycle continues with ACH4 through ACHT The results of the first four conversion are placed in the lower four result registers ADO through AD3 The rest of the conversions are placed in their matching result register ACSO and ACSI determine which analog inputs are used as shown in Table 10 Table 10 A D Channel Selection Selected Channel 6 5 Using the A D with Fewer than 8 Inputs There are several options for a user who wishes to con vert fewer than eight analog input channels If time is not critical the user can simply wait for the A D inter rupt to be generated by the AIF bit after channel 7 is converted and can ignore the results for unused chan nels If a user needs to know the results of a conversion immediately after it occurs a timer should be used to generate an interrupt The amount of time required for each A D conversion is specified in the 8XC51GB data Sheet The user could also periodically poll the result registers provided he or she is looking only for a change in the analog voltage Using the Select mode see above does not reduce the time required for a con version cycle but will convert a given channel more frequently intel 87C51GB HA
363. n using 16 bit CRC the receiver can be turned off while transmitting RSTAT 1 0 and the transmitter can be turned off during reception TSTAT 1 0 This simulates half duplex operation when using a 16 bit CRC Normally HDLC uses a 16 bit CRC so half duplex is determined by turning off the receiver or transmitter This is so that the receiver will not detect its own ad dress as transmission takes place This also needs to be done when using CSMA CD with a 16 bit CRC for the same reason 3 6 2 CPU DMA CONTROL OF THE GSC The data for transmission or reception can be handled by either the CPU TSTAT 0 0 or DMA controller TSTAT 0 1 This allows the user two sets of flags to control the FIFO Associated with these flags are interrupts which may be enabled by the user software Either one or both sets of flags may be used at the same time In CPU control mode the flags RFNE TFNF are gen erated by the condition of the receive or transmit FI FO s After loading a byte into the transmit FIFO there is a one machine cycle latency until the TFNF flag is updated Because of this latency the status of TFNF should not be checked immediately following the instruction to load the transmit FIFO If using the interrupts to service the transmit FIFO the one ma chine cycle of latency must be considered if the TFNF flag is checked prior to leaving the subroutine When using the CPU for control transmission normal ly is initiated b
364. n will return the correct value of 1 4 5 Accessing External Memory Accesses to external memory are of two types accesses to external Program Memory and accesses to external Data Memory Accesses to external Program Memory use signal PSEN program store enable as the read strobe Accesses to external Data Memory use RD or WR alternate functions of P3 7 and P3 6 to strobe the memory Refer to Figures 5 through 7 Fetches from external Program Memory always use a 16 bit address Accesses to external Data Memory can use either a 16 bit address MOVX DPTR or 8 bit address MOVX Ri STATE 5 P P2 STATE 6 P2 STATE 1 pi P2 STATE 2 P P2 270653 30 Figure 5 External Program Memory Fetches 5 10 intel 8XC51FX HARDWARE DESCRIPTION iren ivi STATE 3 bare 1 2 2 p1 2 2 22 2 Pil 2 PCL OUT PROGRAM MEMORY IS EXTERNAL DPL OR Ri Figure 6 External Data Memory Read Cycle STATE 4 STATE 5 STATE 6 sor STATE 3 ir dd p1 p2 p2 p1 1 2 1 2 2 pil 2 p 2 Figure 7 External Data Memory Write Cycle 5 11 ntel 8XC51FX HARDWARE DESCRIPTION Whenever a 16 bit address is used the high byte of the address comes out on Port 2 where it is held for the duration of the read or write cycle The Po
365. nal clock for Timer Counter 2 or 2 to output a 5096 duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency Figure 15 shows Timer 2 in clock out mode 87C51GB HARDWARE DESCRIPTION configure the Timer Counter 2 as a clock generator bit 2 in T2CON must be cleared and bit T2OE in T2MOD must be set Bit TR2 in T2CON also must be set to start the timer Clock Out frequency depends on the oscillator fre quency and the reload value of Timer 2 capture regis ters RCAP2H RCAP2L as shown in this equation Clock Out Oscillator Frequency Frequency 4 x 65536 RCAP2H RCAP2L In the Clock Out mode Timer 2 roll overs will not generate an interrupt This is similar to when it is used as a baud rate generator It is possible to use Timer 2 as baud rate generator and a clock generator simulta neously Note however that the baud rate and the clock out frequency will be the same TL2 1 8 Bits Wing T20E T2MOD 1 TIMER 2 INTERRUPT 270897 17 Figure 15 Timer 2 Mode 6 20 ntel 87C51GB HARDWARE DESCRIPTION 6 0 A D CONVERTER The A D converter on the 8XC51GB consists of 8 analog inputs ACH0 ACH7 an external trigger in put separate analog voltage supplies AVss and AVggr comparison reference input COMPREF and internal circuitry The internal cir cuitry includes an 8 channel multiplexer a 256 element
366. ndefined Bit Addressable 8052 only intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ScoN j EINE NEN NEDAE C _ 7 TCON TH Po p Figure 5 Bit Addressable 8 Bytes 2 10 FF EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 87 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Those SFRs that have their bits assigned for various functions are listed in this section A brief description of each bit is provided for quick reference For more detailed information refer to the Architecture Chapter of this book PSW PROGRAM STATUS WORD BIT ADDRESSABLE Lo sc ov gt PSW 7 Carry Flag 25 PSW 6 Auxiliary Carry Flag FO PSW 5 Flag 0 available to the user for general purpose 51 PSW 4 Register Bank selector bit 1 SEE NOTE 1 RSO PSW 3 Register Bank selector bit 0 SEE NOTE 1 PSW 2 Overflow Flag PSW 1 User definable flag P PSW 0 Parity Set cleared by hardware each instruction cycle to indicate odd even number of P bits in the accumulator NOTE 1 The value presented by 50 and 851 selects the corresponding register bank __ RS Register Bank 00H 07H 08H 0FH 10H 17H 18H 1FH PCON POWER CONTROL REGISTER NOT BIT ADDRESSABLE smop
367. ne by the master polling the secondary stations to see if they have a need to access the serial line This should prevent any collisions from occurring provided each secondary station has its own unique address This arrangement also partially determines the types of networks supported Normal SDLC networks consist of point to point multi drop or ring configurations and the C152 supports all of these However some SDLC processors support an au tomatic one bit delay at each node that is not supported by the C152 In a Loop Mode configuration is is necessary that the transmission be delayed from the re ception of the frames from the upstream station before passing the message to the downstream station This delay is necessary so that a station can decode its own address before the message is passed on The various networks are shown in Figure 3 10 3 3 9 HDLC SDLC COMPARISON HDLC High level Data Link Control is a standard adopted by the International Standards Organization ISO The HDLC standard is defined in the ISO docu ment 150 6159 HDLC unbalanced classes of dures IBM developed the SDLC protocol as a subset of HDLC SDLC conforms to HDLC protocol require ments but is more restrictive SDLC contains a more precise definition on the modes of operation Some of the major differences between SDLC and HDLC are SDLC HDLC Unbalanced primary Balanced secondary peer to peer Modulo 8 no extensions M
368. ns One CPU is programmed to be the Arbiter and the other to be the Requester The ALE Switch selects which ALE signal will be directed to the address latch The Arbiter s ALE is selected if HLDA is high and the Requester s ALE is selected if HLDA is low ALE REQ IF ALBA 0 270427 34 Figure 4 7 ALE Switch Select The ALE Switch logic can be implemented by a single 74 0 as shown in Figure 4 7 270427 33 Figure 4 6 Two 83C 152s Sharing External RAM 7 52 intel 83C152 HARDWARE DESCRIPTION 4 3 4 INTERNAL LOGIC OF THE ARBITER The internal logic of the arbiter is shown in Figure 4 8 In operation an input low at HLD sets Q2 if the arbi ter s internal signal DMXRQ is low DMXRQ is the arbiter s to XRAM Request Setting Q2 acti vates HLDA through Q3 Q2 being set also disables any DMAs to XRAM that the arbiter might decide to do during the requester s DMA Figure 4 9 shows the minimum response time 4 to 7 CPU oscillator periods between a transition at the HLD input and the response at HLDA HLD input P1 5 When the arbiter wants to DMA the XRAM it first activates DMXRQ This signal prevents Q2 from being set if it is not already set An output low from Q2 en ables the arbiter to carry out its DMA to XRAM and maintains an output high at HLDA When the arbiter completes its DMA the signal DMXRQ goes to O which enables Q2 to accept signals from the HLD inpu
369. nsmitted over an 8 bit address data bus Up to 64K bytes of data may be transmitted for each DMA activa tion The new I O port P4 functions the same as Ports 1 3 found on the 80C5IBH Internal memory has been doubled in the 83C152 Data memory has been expanded to 256 bytes and internal program memory has been expanded to 8K bytes There are also some specific differences between the 83C152 and the 80C51BH The first is that the number ing system between the 83C152 and the 80C51BH is slightly different The 83C152 and the 80C51BH are factory masked ROM devices The 80C152 and the 80C31BH are ROMless devices which require the 7 8 use of external program memory The second difference is that RESET is active low in the 83C152 and active high in the 80 51 This is very important to design ers who may currently be using the 80C51BH and plan ning to use the 83C152 or are planning on using both devices on the same board The third difference is that GFO and general purpose flags in PCON have been renamed GFIEN and XRCLK GFIEN enables idle flags to be generated in SDLC mode and XRCLK enables the receiver to be externally clocked of the previously unused bits are now being used and inter rupt vectors have been added to support the new en hancements Programmers using old code generated for the 80C51BH will have to examine their programs to ensure that new bits are properly loaded and that the new interrupt vect
370. ntel Embedded Controller Handbook which de Scribes the timer counters and their use The user should bear in mind when reading the Intel Embedded Controller Handbook that the C152 does not have the third event timer named Timer 2 which is in the 8052 2 6 Package The 83C152 is packaged in a 48 pin DIP and a 68 lead PLCC This differs from the 40 pin DIP and 44 pin PLCC of the 80 51 The larger package is required to accommodate the extra 8 bit I O port P4 Figures 2 5A 2 5B and 2 5C show the packages and the pin names GRXD DEN RXC wn 10 11 38 80C152JA JC 83C152JA JC 15 14 A13 412 11 10 49 48 A D7 A D6 A D5 A D4 270427 5 Figure 2 5A DIP Pin Out Table 2 1 Program Memory Fetches Active Addresses 0 0FFFFH BMC Addresses 0 OFFFFH Inactive Active Active Inactive Invalid Combination Addresses 0 1FFFH Addresses z 2000H intel 83C152 HARDWARE DESCRIPTION view 80 152 8 80C152JA JC 80C152JD 83C152JA JC XTAL1 32 Figure 2 5B PLCC Pin Out Figure 2 5C PLCC Pin Out 2 7 Pin Description The pin description for the 80C51BH also applies to the C152 and is listed below Changes have been made to the descriptions as they apply to the C152 PIN DESCRIPTION Pine ee ption Dip PLCCOD 48 2
371. nterrupt Flag 9 1 Programmable Modes and Clock Options The four programmable modes determine the inactive level of the clock pin and which edge of the clock is used for transmission or reception These four modes are shown in Figure 31 Table 19 shows how the modes are determined SEPMODEO SEPMODE2 DATA SAMPLED DATA OUTPUT SEPMODE3 CU MALL LLL LL 87C51GB HARDWARE DESCRIPTION Table 19 Determination of SEP Modes CLKPOL SEP Mode zs SEPMODE1 SEPMODE2 SEPMODES The four clock options determine the rate at which data is shifted out of or into the SEP All four rates are fractions of the oscillator frequency Table 20 shows the various rates that can be selected for the SEP Table 20 SEP Data Rates SEPS SEPSO DataRate cs PLP LL U U U LT E EPL LLU ULL CLOCK m CLOCK CLOCK DATA SAMPLED DATA OUTPUT 07 X 25 X D3 o2 X or X 9 Cannot be used for receive mode 270897 31 Figure 31 SEP Modes 6 39 ntel 9 2 SEP Transmission or Reception To transmit or receive a byte the user should initialize the SEP mode CLKPOL and clock frequen cy SEPS1 and SEPSO and enable the SEP SEPE transmission then occurs if the user loads data into SEPDATA A reception occurs if the user sets SEPREN while SEPDATA is empty and a transmis s
372. nterrupts a second Interrupt En able register and a second Interrupt Priority register are implemented in bit addressable SFR space The two In terrupt Enable registers in the 8XC152 are as follows 7 6 5 4 3 2 1 0 te es Ext Ero exo Address of in SFR space OA8H bit addressable 76 5 4 3 2 1 0 ev Address pF IE1 in SFR space able OC8H bit address The bits in IE are unchanged from the standard 8051 IE register The bits in IEN1 are as follows EGSTE 1 Enable GSC Transmit Error Interrupt 0 Disable EDMAI 1 Enable DMA Channel 1 Done Interrupt 0 Disable EGSTV 1 Enable GSC Transmit Valid Interrupt 0 Disable EDMAO 1 Enable DMA Channel 0 Done Interrupt 0 Disable EGSRE 1 Enable GSC Receive Error Interrupt 0 Disable EGSRV 1 Enable GSC Receive Valid Interrupt 0 Disable 7 61 83 152 HARDWARE DESCRIPTION The two Interrupt Priority registers in the 8XC152 are as follows 7 6 5 4 3 2 1 0 iP Ps Prt Address of IP in SFR space bit addressable 76 5 4 3 2 1 0 IPN1JPGSTE POMAt PGSTV POMAdPGSRE PGSRY Address of IPN1 in SFR space OF8H bit address able The bits in IP are unchanged from the standard 8051 IP register The bits in IPN1 are as follows PGSTE 1 GSC Transmit Error Interrupt Priority to High 0 Priority to Low 1 DMA Channel 1 Don
373. nterrupts at once Figure 17 shows the IE reg ister for the 8051 INTERRUPT PRIORITIES Each interrupt source can also be individually pro grammed to one of two priority levels by setting or clearing a bit in the SFR named IP Interrupt Priority Figure 18 shows the IP register in the 8051 low priority interrupt can be interrupted by a high priority interrupt but not by another low priority inter rupt A high priority interrupt can t be interrupted by any other interrupt source If two interrupt requests of different priority levels are received simultaneously the request of higher priority level is serviced If interrupt requests of the same priori ty level are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence Figure 19 shows for the 8051 how the IE and IP regis ters and the polling sequence work to determine which if any interrupt will be serviced MSB LSB es eri exi Pro exo Priority 1 assigns high priority Priority bit 0 assigns low priority iti Function reserved reserved reserved Seriat Port interrupt priority bit Timer 1 interrupt priority bit External Interrupt 1 priority bit Timer 0 interrupt priority bit External Interrupt 0 priority bit IP 2 IP 1 IP 0 These reserved bits are used in other MCS 51 devices F
374. nto RB8 the 8 data bits go into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for 1 10 0 transition in RXD More About Modes 2 and 3 Eleven bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On trans 3 20 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 mit the 9th data bit TB8 can be assigned the value of 0 or 1 On receive the 9th data bit goes into RB8 in SCON The baud rate is programmable to either or the oscillator frequency in Mode 2 Mode 3 may have a variable baud rate generated from either Timer 1 or 2 depending on the state of TCLK and RCLK Figures 19 and 20 show a functional diagram of the serial port in Modes 2 and 3 The receive portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission com mences at 1 1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SBUF signal The
375. o hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag IEx will be set IEx will be automatically cleared by the CPU when the service routine is called If the external interrupt is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deacti vate the request before the interrupt service routine is completed or else another interrupt will be generated Response Time The INTO and INTI levels are inverted and latched into the interrupt flags and 1 at S5P2 of every machine cycle Similarly the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at S5P2 The values are not actually polled by the circuitry until the next machine cycle The Timer 0 and Timer 1 flags and TF1 are set at 5 2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the re quested service routine will be the next instruction to be executed The call itself takes two cycles Thus a mini mum of three complete machine cycles elapse between activation of an external interr
376. o long it is assumed to be a collision or an idle condition In SDLC the synchronization takes place during the BOF flag In addition pulses less than four sample pe riods are ignored and assumed to be noise This sets a lower limit on the pulse size of received zeros 7 39 83C152 HARDWARE DESCRIPTION 270427 24 Jitter In CSMA CD the preamble consists of alternating 1s and Os Consequently the preamble looks like the waveform in Figure 3 13A and 3 13B 3 5 11 External Clocking To select external clocking the user is given three choices External clocking can be used with the trans mitter with the receiver or with both To select exter nal clocking for the transmitter XTCLK GMOD 7 has to be set to a 1 To select external clocking for the receiver XRCLK PCON 3 has to be set to a 1 Set ting both bits to 1 forces external clocking for tbe re ceiver and transmitter The minimum frequency the GSC can be externally clocked at is 0 Hz D C The external transmit clock is applied to pin 4 TXC P1 3 The external receive clock is applied to pin 5 RXC P1 4 To enable the external clock function on the port pin that pin has to be set to a 1 in the appro priate SFR P1 83 152 HARDWARE DESCRIPTION 270427 25 Figure 3 12 Transmit Waveforms Whenever the external clock option is used the format of the transmitted and received data is restricted to encoding and the protocol is restricted to SDL
377. o the PC after incrementing the PC to the first byte of the next instruction bit tested is not modified No flags are affected Example The data present at input port 1 is 110010108 The Accumulator holds 56 01010110B The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label LABEL2 Bytes 3 Cycles 2 Encoding 0010 0000 Operation JB lt PC 3 IF bit 1 THEN PO PO rel JBC bit rel Function Jump if Bit is set and Clear bit Description If the indicated bit is one branch to the address indicated otherwise proceed with the next instruction The bit will not be cleared if it is already a zero The branch destination is comput ed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original data will be read from the output data latch not the input pin Example The Accumulator holds 56H 01010110B The instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 will cause program execution to continue at the instruction identified by the label LABEL2 with the Accumulator modified to 52H 010100108 intel Bytes Encoding Operation JC rel Function Description Example Bytes Cy
378. o the next if condition testing DARn against SBUF and against 1 The same considerations regarding SAS and ISA in the SARn test are now applied to DAS and IDA in the DAR test If SFR space isn t selected no Serial Port buffer is being addressed Note that if DMA channel n is configured to Alternate Cycles mode the logic must examine the other DCON register DCONm to determine if the other channel is also configured to Alternate Cycles mode and whether its GO bit is set In Figure 4 13 the symbol DCONn refers to the DCON register for this channel and DCONm refers to the other channel A careful examination of the logic in Figure 4 13 will reveal some idiosyncracies that the user should be aware of First the logic allows sequential DMA cycles to be generated to service RFIFO but not to service TFIFO This idiosyncracy is due to internal timing conflicts and results in each individual DMA cycle to TFIFO having to be immediately preceded by an In struction cycle The logic disallows that there be two DMaAs to TFIFO in a row If the user is unaware of this idiosyncracy it can cause problems in situations where one DMA channel is serv icing TFIFO and the other is configured to a complete ly different mode of operation 83 152 HARDWARE DESCRIPTION For example consider the situation where channel 0 is configured to service TFIFO and channel 1 is config ured to Alternate Cycles mode Then DMAs to TFIFO will always o
379. o the timer registers TH2 and TL2 respec tively logic 0 at 2 makes Timer 2 count down Now the timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L The under flow sets the TF2 bit and causes OFFFFH to be reload ed into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows This bit can be used as a 17th bit of resolu tion if desired In this operating mode EXF2 does not generate an interrupt BAUD RATE GENERATOR MODE The baud rate generator mode is selected by setting the RCLK and or TCLK bits in T2CON Timer 2 in this mode will be described in conjunction with the serial port PROGRAMMABLE CLOCK OUT 50 duty cycle clock can be programmed to come out on P1 0 This pin besides being a regular I O pin has two alternate functions It can be programmed 1 to input the external clock for Timer Counter 2 or 2 to output a 50 duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency To configure the Timer Counter 2 as a clock generator bit C T2 in 2 must be cleared and bit T2OE in T2MOD must be set Bit TR2 T2CON 2 also must be set to start the timer see Table 6 for operating modes 5 18 The Clock out frequency depends on the oscillator fre quency and the reload value of Timer 2 capture regis ters RCAP2H RCAP2L as shown in this equation Clock out Frequency Oscillator Frequency 4 X 65536 RCAP2H RCA
380. oad is caused by a negative transition on 2 and 2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3 0 causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX Start stop control for Timer 2 A logic 1 starts the timer Timer or counter select Timer 2 0 internal timer OSC 12 1 External event counter falling edge triggered Capture Reload flag When set captures will occur on negative transitions at 2 if 2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at 2 when EXEN2 1 When either RCLK 10r TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Figure 11 T2CON Timer Counter 2 Control Register In the Capture Mode there are two options which are selected by
381. od Description Jump indirect relative to the DPTR Jump if Accumulator is Zero Jump if Accumulator is Not Zero Compare direct byte to Acc and Jump if Not Equal Compare immediate to Acc and Jump if Not Equal Byte Mnemonic CJNE Ri data rel DJNZ DJNZ direct rel Description PROGRAM BRANCHING Continued CJNE Rn data rel Compare immediate to register and Jump if Not Equal Compare immediate to indirect and Jump if Not Equal Decrement register and Jump if Not Zero Decrement direct byte and Jump if Not Zero No Operation Byte 1 Oscillator Period mnemonics copyrighted Intel Corporation 1980 2 24 I MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 11 Instruction Opcodes in Hexadecimal Order Hex Number Hex Number Code Bytes Mnemonic Operands Code of Bytes Mnemonic Operands code addr code addr A A data addr data addr A data addr data data A data addr A RO A R1 A RO A R2 A R3 A R4 A R5 6 A R7 code addr code addr data addr A data addr data A A data addr A RO A R1 A RO A R1 A R2 A R5 A R6 code addr code addr data data addr data data A data addr bit addr code addr code addr code addr A A data addr bit addr code addr code addr A A data A data addr A RO A GR1 AR1 AR2 A R3
382. odulo 128 up to 127 allowed up to 7 out outstanding frames standing frames before before acknowledge acknowledge is required is required 8 bit addressing only Extended addressing Byte aligned data Variable size of data The C152 does not support HDLC implementation re quiring data alignment other than byte alignment The user will find that many of the protocol parameters are programmable in the C152 which allows easy imple mentation of proprietary or standard HDLC network User software needs to implement the control field functions 3 3 10 USING A PREAMBLE IN SDLC When transmitting a preamble in SDLC mode the user should be aware that the pattern of 10101010 is output NRZI encoding is used in SDLC when the in ternal baud rate generator is the clock source and this means that a transition will occur every two bit times when 0 is transmitted This compares with some oth er SDLC devices most of which transmit the pattern 00000000 which will cause a transition every bit time Our past experience has shown that the C152 pre amble does not cause a problem with most other devic es This is because the preamble is used only to define the relative bit time boundaries within some variation allowed by the receiving station and the C152 pream ble fulfills this function The C152 does not have any problems with receiving a preamble consisting of all Os One note of caution however If idle fill flags are used in conjun
383. of the EPROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled P Programmed U Unprogrammed Any other combination of the Lock Bits is not defined Table 6 Program Protection Lock Bits Encrypt Array 87518 LB1 82 LB1 LB2 LB1 LB2 LB3 8752BH 87 51 3 30 HARDWARE DESCRIPTION OF THE 8051 8052 80 51 When Lock 1 is programmed the logic level at the EA pin is sampled and latched during reset If the de vice is powered up without a reset the latch initializes to a random value and holds that value until reset is activated It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly ROM PROTECTION The 8051AHP and 80C51BHP are ROM Protected versions of the 8051AH and 80C51BH respectively To incorporate this Protection Feature program verifica tion has been disabled and external memory accesses have been limited to 4K Refer to the data sheets on these parts for more information ONCETM Mode The ONCE on circuit emulation mode facilitates testing and debugging of systems using the device with out the device having to be removed from the circuit The ONCE mode is invoked by 1 Pull ALE low while the device is in reset and PSEN is high 2 Hold ALE low as RST is deactivated While the device is in ONCE mode the Port 0 pins go into
384. olds 55H 01010101B then the instruction ANL A RO will leave 41H 01000001B in the Accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run time The instruction ANL 1 01110011 will clear bits 7 3 and 2 of output port 1 2 32 intel ANL A Rn Bytes Cycles Encoding Operation ANL A direct Bytes Cycles Encoding Operation ANL A Ri Bytes Cycles Encoding Operation ANL A data Bytes Cycles Encoding Operation ANL direct A Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 ANL 2 1 ANL A A direct 1 1 o101 0110 ANL A 2 1 ANL A f data 2 1 ANL direct direct A 2 33 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ANL direct 4 data Bytes 3 Cycles 2 Encoding immediate data Operation ANL direct lt direct data ANL C lt src bit gt Function Logical AND for bit variables Description If the Boolean value of the source bit is a logical then clear the carry flag otherwise leave the carry flag
385. olute Call Description ACALL unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction then pushes the 16 bit result onto the stack low order byte first and increments the Stack Pointer twice The destination address is obtained by successively concatenating the five high order bits of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2K block of the program memory as the first byte of the instruction following ACALL No flags are affected Initially SP equals 07H The label SUBRTN is at program memory location 0345 H After executing the instruction ACALL SUBRTN at location 0123H SP will contain 09H internal RAM locations 08H and 09H will contain 25H and 01H respectively and the PC will contain 0345H Bytes 2 Cycles 2 Encoding 10 a9 81 000 1 a7 a6 a5 a4 a2 a1 Operation ACALL PC PO 2 SP SP 1 SP PC7 9 SP SP 1 SP 15 8 10 0 page address 2 28 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ADD A lt src byte gt Function Description Example ADD A Rn Bytes Cycles Encoding Operation ADD A direct Bytes Cycles Encoding Operation Add ADD adds the byte variable indicated to the Acc
386. ontroller intel Program Memory addresses are always 16 bits wide even though the actual amount of Program Memory used may be less than 64K bytes External program execution sacrifices two of the 8 bit ports and P2 to the function of addressing the Program Memory Data Memory The right half of Figure 2 shows the internal and exter nal Data Memory spaces available to the MCS 51 user Figure 5 shows a hardware configuration for accessing up to 2K bytes of external RAM The CPU in this case is executing from internal ROM Port O serves as a multiplexed address data bus to the RAM and 3 lines of Port 2 are being used to page the RAM The CPU generates RD and WR signals as needed during exter nal RAM accesses 270251 5 Figure 5 Accessing External Data Memory If the Program Memory is Internal the Other Bits of P2 are Available as I O There can be up to 64K bytes of externa Data Memo ry External Data Memory addresses can be either 1 or 2 bytes wide One byte addresses are often used in con junction with one or more other I O lines to page the RAM as shown in Figure 5 Two byte addresses can also be used in which case the high address byte is emitted at Port 2 ACCESSIBLE BY DIRECT ADDRESSING ACCESSIBLE UPPER BY INDIRECT ADORESSING N ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING REGISTERS STACK POINTER ACCUMULATOR ETC 270251 6 Figure 6 Internal Data Memory
387. or Zero If all bits of the Accumulator are zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative dis placement in the second instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally contains 01H The instruction sequence JZ LABELI DEC A JZ LABEL2 will change the Accumulator to and cause program execution to continue at the instruc tion identified by the label LABEL2 2 2 2110 5000 JZ lt PO 2 IF A 0 THEN PO PO rel 2 50 intel LCALL addr16 MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Function Long call Description LCALL calls a subroutine located at the indicated address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first incrementing the Stack Pointer by two The high order and low order bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64K byte program memory address space No flags are affected Example Initially the Stack Pointer equals 07H The label SUBRTN is assigned to program memory location 1234H A
388. or conditions TCDT Transmitter Collision Detector UR Underrun in Transmit FIFO NOACK No Acknowledge These bits reside in the TSTAT register User software can read them but only the GSC hardware can write to them The GSC hardware will set them in response to the various error conditions that they represent When user software sets the TEN bit the GSC hardware will at that time clear these flags This is the only way these flags can be cleared The logical OR of these three bits flags the GSC Trans mit Error interrupt GSCTE and clears the TEN bit as shown in Figure 5 2 Thus any detected error condi tion aborts the transmission No CRC bits are transmit ted In SDLC mode no EOF flag is generated In CSMA CD mode an EOF is generated by default since the GTXD pin is pulled to a logic 1 and held there TRANSMIT EOF 830152 HARDWARE DESCRIPTION The TCDT bit can get set only if the GSC is configured to CSMA CD mode In that case the GSC hardware sets TCDT when a collision is detected during a trans mission and the collision was detected after TFIFO has been accessed Also the GSC hardware sets TCDT when a detected collision causes the TCDCNT register to overflow The UR bit can get set only if the DMA bit in TSTAT is set The DMA bit being set informs the GSC hard ware that TFIFO is being serviced by DMA In that case if the GSC goes to fetch another byte from TFIFO and finds it empty and the byte count
389. or the two timers MODE 0 Either Timer 0 or Timer 1 in Mode 0 is an 8 bit Coun ter with a divide by 32 prescaler Figure 8 shows the Mode 0 operation for either timer In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFx The counted input is enabled to the Timer when TRx 1 and either GATE O or INTx 1 Setting 1 allows the Timer to be controlled by external input INTx to facilitate pulse width measurements TRx and TFx are intel control bits in SFR TCON Table 6 The GATE bit is in TMOD There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 The 13 bit register consists of all 8 bits of THx and the lower 5 bits of TLx The upper 3 bits of TLx are inde terminate and should be ignored Setting the run flag TRx does not clear these registers MODE 1 Mode 1 is the same as Mode 0 except that the Timer register uses all 16 bits Refer to Figure 9 In this mode THx and TLx are cascaded there is no prescaler 8XC51FX HARDWARE DESCRIPTION MODE 2 Mode 2 configures the Timer register as an 8 bit Coun ter TLx with automatic reload as shown in Figure 10 Overflow from TLx not only sets TFx but also reloads TLx with the contents of THx which is preset by soft ware The reload leaves THx unchanged Table 5 TMOD Timer Counter Mode Control Register Address
390. or two bit times If the CRC is correct while in CSMA CD mode AE is not set and any mis alignment is assumed to be caused by dribble bits as the line went idle In SDLC mode AE is set if a non byte aligned flag is received CRCE may also be set The setting of this flag is controlled by the GSC intel 83C152 HARDWARE DESCRIPTION RSTAT 6 Receiver Collision Abort Detect If set indicates that collision was detected after data had been loaded into the receive FIFO in CSMA CD mode In SDLC mode RCABT indicates that 7 consec utive ones were detected prior to the end flag but after data has been loaded into the receive FIFO AE may also be set if RCABT is set 7 OVR Overrun If set indicates that the receive FIFO was full and new shift register data was written into it It is cleared by user software AE and or CRCE may also be set if OVR is set SARHO 0A3H Source Address Register High 0 contains the high byte of the source address for DMA Channel 0 SARHI 0B3H Source Address Register High 1 contains the high byte of the source address for DMA Channel 1 SARLO 0A2H Source Address Register Low 0 con tains the low byte of the source address for DMA Channel 0 SARLI 0B2H Source Address Register Low 1 con tains the low byte of the source address for DMA Channel 1 SAS Source Address Space bit see DCONO SBUF 099H Serial Buffer both the receive and transmit SFR lo
391. ors will not interfere with their pro gram Throughout the rest of this manual the 80C152 and the 83C152 will be referred to generically as the C152 The C152 is based on the 80C51BH architecture and utilizes the same 80C51BH instruction set Figure 1 1 is a block diagram of the C152 Readers are urged to compare this block diagram with the 80C51BH block diagram There have been no new instructions added All the new features and peripherals are supported by an extension of the Special Function Registers SFRs Very little of the information pertaining specifically to the 80C51BH core will be discussed in this chapter The detailed information on such functions as the in struction set port operation timer counters etc can be found in the MCS 51 Architecture chapter in the Intel Embedded Controller Handbook Knowledge of the 80C51BH is required to fully understand this man ual and the operation of the C152 To gain a basic un derstanding on the operation of the 80CSIBH the reader should familiarize himself with the entire MCS 51 chapter of the Embedded Controller Handbook Another source of information that the reader may find helpful is Intel s LAN Components User s Manual or der number 230814 Inside are descriptions of various protocols application examples and application notes dealing with different serial communication environ ments 2 0 COMPARISON OF 80C152 AND 80C51BH FEATURES 2 1 Memory Space A goo
392. ot set TF2 and will not generate an interrupt Note too that if 2 is set 1 10 0 transition in T2EX will set EXF2 but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate generator T2EX can be used as an extra external interrupt if desired It should be noted that when Timer 2 is running TR2 1 in timer function in the baud rate generator mode one should not try to read or write TH2 or TL2 Under these conditions the Timer is being incremented every state time and the results of a read or write may not be accurate The RCAP2 registers may be read but shouldn t be written to because a write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 registers PROGRAMMABLE CLOCK OUT A 50 duty cycle clock can be programmed to come out on P1 0 This pin besides being a regular I O pin has two alternate functions It can be programmed 1 to input the external clock for Timer Counter 2 or 2 to output a 50 duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency configure the Timer Counter 2 as a clock generator bit C T2 T2CON 1 must be cleared and bit T2OE T2MOD 1 must be set Bit TR2 T2CON 2 starts and stops the timer The Clock Out frequency depends on the oscillator fre quency and the reload value of Timer 2 capture regis ters RCAP2H TCA
393. ot try to read or write TH2 or TL2 Under these conditions the Timer is being incremented every state time and the results of a read or write may not be accurate The RCAP2 registers may be read but shouldn t be written to because a write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or 2 registers Table 16 lists commonly used baud rates and how they can be obtained from Timer 2 Table 16 Timer 2 Generated Used Baud Rates RCAP2H RCAP2L FF FF Osc Freq 270653 20 Figure 23 Timer 2 in Baud Rate Generator Mode 5 31 intel 8XC51FX HARDWARE DESCRIPTION 8 0 INTERRUPTS The C51FX has a total of 7 interrupt vectors two ex ternal interrupts INTO and INTI three timer inter rupts Timers 0 1 and 2 the interrupt and the serial port interrupt These interrupts are all shown in Figure 24 All of the bits that generate interrupts can be set cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be cancelled in software Each of these interrupts will be briefly described fol lowed by a discussion of the interrupt enable bits and the interrupt priority levels INTERRUPT SOURCES TF2 EXF2 See exceptions when Timer 2 is used as baud rate generator or an up down
394. ows Timer 2 Overflow Rate 1 and Baud Rates 16 The Timer can be configured for either timer or counter operation In most applications it is config ured for timer operation C T2 0 The Timer operation is different for Timer 2 when it s being used as a baud rate generator Normally as a timer it incre ments every machine cycle 1 12 the oscillator frequen Cy a baud rate generator however it increments every state time 7 the oscillator frequency The baud rate formula is given below Modes 1 and 3 _ Oscillator Frequency BaudRate 32 x 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer Timer 2 as a baud rate generator is shown in Figure 23 This figure is valid only if RCLK and or TCLK 1 in T2CON Note that a in TH2 does not set TF2 and will not generate an interrupt Therefore the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Note too that if 2 is set 1 to O transition in T2EX will set EXF2 but wil not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use NOTE OSC FREQ BY 2 NOT 12 as a baud rate generator T2EX can be used as an extra external interrupt if desired It should be noted that when Timer 2 is running TR2 in timer function in the baud rate generator mode one should n
395. pp 12 75 and Voc 5 0V using a series of five 100 PROG pulses per byte programmed This sults in a total programming time of approximately 5 seconds for the 87C51FA s 8 Kbytes 10 seconds for the 87 51 5 16 Kbytes and 20 seconds for the 87CS1FC s 32 Kbytes Exposure to Light The EPROM window must be cov ered with an opaque label when the device is in opera tion This is not so much to protect the EPROM array from inadvertent erasure but to protect the RAM and other on chip logic Allowing light to impinge on the silicon die while the device is operating can cause logi cal malfunction 12 0 PROGRAM MEMORY LOCK In some microcontroller applications it is desirable that the Program Memory be secure from software pi racy The C51FX has varying degrees of program pro tection depending on the device Table 24 outlines the lock schemes available for each device Encryption Array Within the EPROM ROM is an ar ray of encryption bytes that are initially unprogrammed all I s For EPROM devices the user can program the encryption array to encrypt the program code bytes during EPROM verification For ROM devices the user submits the encryption array to be programmed by the factory If an encryption array is submitted LB1 will also be programmed by the factory The encryption array is not available without the Lock Bit Program code verification is performed as usual except that each code byte comes out exclusive
396. r the ROMless devices all program fetches must be to external memory If the EA pin is connected to Voc then program fetches greater than 8K are to external addresses for the 8XC51GB products On the 87C51GB with EA connected to Vcc program fetches to addresses 0000H through 1FFFH are to in ternal ROM and fetches to addresses 2000H through FFFFH are to external memory 2 2 Data Memory The 8XC51GB implements 256 bytes of on chip data RAM The memory space is divided into three blocks RAM ADOR REGISTER INSTRUCTION REGISTER PORT 1 PORT 5 DRIVERS 1 0 1 7 5 0 5 7 87C51GB HARDWARE DESCRIPTION 2 0 2 7 T L 1 1 i 1 TL HHDH 4 PORT DRIVERS DRIVERS 4 0 4 7 P3 0 P3 7 270897 1 Figure 1 87C51GB Block Diagram which are generally referred to as the Lower 128 the Upper 128 and SFR space The Upper 128 bytes occu py a parallel address space to the Special Function Reg isters That means they have the same addresses but they are physically separate from SFR space The Lower 128 bytes of RAM are present in all MCS 51 devices All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as RO through R7 Two bits in the Progra
397. r 0 and Timer 1 Interrupts are generated by and TF1 which are set by a rollover in their re spective Timer Counter registers except see Timer O in Mode 3 When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to The Serial Port Interrupt is generated by the logical OR of RI and TI Neither of these flags is cleared by hard ware when the service routine is vectored to In fact the service routine will normally have to determine whether it was RI or TI that generated the interrupt and the bit will have to be cleared in software In the 8052 the Timer 2 Interrupt is generated by the logical OR of TF2 and EXF2 Neither of these flags is cleared by hardware when the service routine is vec tored to In fact the service routine may have to deter mine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared in soft ware All of the bits that generate interrupts can be set or cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be canceled in software MSB LSB es ers exi exo Enable Bit 1 enables the interrupt Enable Bit 0 disables it Symbol Position EA 1E 7 Function disables all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each int
398. rame All the stations ex cept station 1 on the link should ignore the initializa tion request Station 1 upon receiving the initialization request assigns an address and returns it to station 2 Station 1 will be required to format the message in such manner so that all stations on the link recognize it as a response to initialization This means that all stations except station 2 ignore the return message 3 5 6 TEST MODES There are two test modes associated with the GSC that are made available to the user The test modes are named Raw Receive and Raw Transmit The test modes are selected by the proper setting of the two mode bits in GMOD GMOD 5 GMOD 6 If M1 M0 0 1 then Raw Transmit is se lected If M1 MO 1 0 then Raw Receive is enabled The 32 bit CRC cannot be used in any of the test modes or else CRC errors will occur In Raw Transmit the transmit output is internally con nected to the Receiver input This is intended to be used as a local loop back test mode so that all data written to the transmitter will be returned by the re ceiver Raw Transmit can also be used to transmit user data If Raw Transmit is used in this way the data is emitted with no preamble flag address CRC and no bit insertion The data is still encoded with whatever format is selected Manchester with CSMA CD NRZI with SDLC or as NRZ if external clocks are used The receiver still operates as normal and in this mode most of t
399. rame This sequence number is called the Receive Count In transmitting the Receive Count the receiver is in fact acknowledging all the previous frames prior to the count that was transmitted This allows for the transmission of up to seven frames before acknowl edge is required back to the transmitter The limitation of seven frames is necessary because the Receive Count in the control field is limited to three binary digits This means that if an eighth transmission occurred this would cause the next Receive Count to repeat the first count that still is waiting for an acknowledge This would defeat the purpose of the acknowledgement The processing and general maintenance of the sequence count must be done by the user software The Hard ware Based Acknowledge option that is provided in the C152 is not compatible with standard SDLC protocol 3 3 8 PRIMARY SECONDARY STATIONS All SDLC networks are based upon a primary second ary station relationship There can be only one primary station in a network and all the other stations are con sidered secondary All communication is between the primary and secondary station Secondary station to secondary station direct communication is prohibited If there is a need for secondary to secondary communi cation the user software will have to make allowances for the master to act as an intermediary Secondary stations are allowed use of the serial line only when the master permits them This is do
400. rator mode 1 External event counter falling edge triggered Capture Reload flag When set captures will occur on negative transition at T2EX if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at 2 when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow 6 17 ntel 87C51GB HARDWARE DESCRIPTION The T2 Pin has another alternate function on the 87C51GB It can be configured as a Programmable Clock Out TIMER 2 CAPTURE MODE In the capture mode there are two options selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 isa 16 bit timer on counter which upon overflow sets bit TF2 in T2CON This bit can then be used to generate an interrupt If EXEN2 1 Timer 2 still does the above but with the added feature that a 1 to O tran sition at external input T2EX causes the current value in the Timer 2 registers TH2 and TL2 to be captured into registers RCAP2H and RCAP2L respectively In TRANSITION addition the transition at T2EX causes bit EXF2 T2CON to be set The EXF2 bit like TF2 can generate an interrupt Figure 12 illustrates this TIMER 2 AUTO RELOAD UP OR DOWN COUNTER Timer 2 can be programmed to count up or down when configured in its 16 bit auto reload mode This feature is invoked by a bit named DCEN Down Counter En able located in the SFR T2MOD see Table 8
401. rdware based ac knowledge is for The other two ways the NOACK bit can get set are to guard against the possibility that the transmitting station might mistake an unrelated trans mission or transmission fragment for an acknowledge signal 5 2 GSC Receiver Error Conditions The GSC Receiver section reports four kinds of error conditions CRC Error AE Alignment Error RCABT Receive Abort OVR Overrun in Receive FIFO These bits reside in the RSTAT register User software can read them but only the GSC hardware can write to them The GSC hardware will set them in response to the various error conditions that they represent When user software sets the GREN bit the GSC hardware will at that time clear these flags This is the only way these flags can be cleared 7 63 The logical OR of these four bits flags the GSC Receive Error interrupt GSCRE and clears the GREN bit as shown in Figure 5 3 Note in this figure that any error condition will prevent RDN from being set CRC Error means the CRC generator did not come to its correct value after calculating the CRC of the message plus received CRC An Alignment Error means the number of bits received between the BOF and EOF was not a multiple of 8 In SDLC mode the CRCE bit gets set at the end of any frame in which there is a CRC Error and the AE bit gets set at the end of any frame in which there is an Alignment Error In CSMA CD mode if there is
402. re 1 shows a functional block diagram of the 8051s and 8052s Table 1 The MCS 51 Family of Microcontrollers 8051AH 8052AH 80C51BH 8031AH 8032AH 80C31BH 8751H 8751BH 8752BH 87C51 Special Function Registers Device ROMless EPROM ROM 6 bit Name Version Version a HMOS A map of the on chip memory area called SFR Special Function Register space is shown in Figure 2 SFRs marked by parentheses are resident in the 8052s but not in the 8051s intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 EGISTER lt lt 1 i PCON THz acara saur ik INTERRUPT SERIAL PORT AND TIMER BLOCKS INSTRUCTION REGISTER 10 17 270252 1 Figure 1 MCS 51 Architectural Block Diagram HARDWARE DESCRIPTION OF THE 8051 8052 80 51 FO F7 E8 EF EO E7 08 Do 07 88 7 AQ A7 98 9F s jJ _ T s TMOD 4 THO TH Po SP pH I X PON 8 Figure 2 Indicates Resident 80525 not 80515 Note that not all of the addresses are occupied cupied addresses
403. re a collision is detected the transmitter is disabled TEN 0 and the TCDT flag is set The response of the GSC to detected collisions is sum marized in Figure 3 4 None unless DCR 1 1 begin DCR countdown None unless DCR 1 If DCR 1 begin DCR countdown Set RCABT clear GREN If DCR 1 begin DCR countdown Figure 3 4 Response to a Detected Collision References to DCR and the DCR Countdown Have to Do with the Deterministic Collision Resolution Algorithm ntel 83C152 HARDWARE DESCRIPTION Jam The jam signal is generated by any 8XC152 that is in volved in transmitting a frame at the time a collision is detected at its GRXD pin This is to ensure that if one transmitting station detects a collision all the other sta tions on the network will also detect a collision If a transmitting 8XC152 detects a collision during the preamble BOF part of the frame that it is trying to transmit it will complete the preamble BOF and then begin the signal in the first bit time after BOF If the collision is detected later in the frame the jam sig nal will begin in the next bit time after the collision was detected The jam signal lasts for the same number of bit times as the selected CRC length either 16 or 32 bit times The 8XC152 provides two types of jam signals that can be selected by user software If the node is DC coupled to the network the DC jam can be selected In this case the
404. re before enabling the receiver RFIFO is cleared by reading the contents of RFIFO until RFNE 0 After each read of RFIFO it takes one machine cycle for the status of RFNE to be updated Setting GREN also clears RDN CRCE AE and RCABT GREN is cleared by hardware at the end of a reception or if any receive errors are detected The status of GREN has no effect on whether the receiver detects a collision in CSMA CD mode as the receiver input circuitry always monitors the receive pin RSTAT 2 RFNE Receive FIFO Not Empty If set indicates that the receive FIFO contains data The re ceive FIFO is a three byte buffer into which the receive data is loaded A CPU read of the FIFO retrieves the oldest data and automatically updates the FIFO point ers Setting GREN to a one will clear the receive FIFO The status of this flag is controlled by the GSC This bit is cleared if user software empties receive FIFO RSTAT 3 RDN Receive Done If set indicates the successful completion of a receiver operation Will not be set if a CRC alignment abort or FIFO overrun error occurred RSTAT 4 CRCE CRC Error If set indicates that a properly aligned frame was received with a mismatched CRC RSTAT 5 AE Alignment Error In CSMA CD mode AE is set if the receiver shift register an internal serial to parallel converter is not full and the CRC is bad when an EOF is detected In the EOF is a line idle condition see LND f
405. rect addressing 83 152 HARDWARE DESCRIPTION The addresses of the second 128 bytes of data memory happen to overlap the SFR addresses The SFRs and their memory locations are shown in Figure 2 2 This means that internal data memory spaces have the same address as the SFR address However each type of memory is addressed differently To access data memo ry above 80H indirect addressing or the chan nels must be used To access the SFRs direct address ing is used When direct addressing is used the address is the source or destination e g MOV A 10H moves the contents of location 10H into the accumulator When indirect addressing is used the address of the destination or source exists within another register e g MOV A GRO This instruction moves the contents of the memory location addressed by RO into the accumu lator Directly addressing the locations 80H to OFFH will access the SFRs Another form of indirect address ing is with the use of Stack Pointer Operations If the Stack Pointer contains an address and PUSH or POP instruction is executed indirect addressing is actually used Directly accessing an unused SFR address will give undefined results Physically there are separate SFR memory and data memory spaces allocated on the chip Since there are separate spaces the SFRs do not diminish the available data memory space OVERLAPPING MEMORY ADORESSES SPECIAL FUNCTION REGISTER SPACE BIT ADDRESSABLE ME
406. register of the channel servicing TFIFO is not zero it sets the UR bit If the DMA hardware is not being used to service TFIFO the UR bit cannot get set If the DMA bit is 0 then when the GSC finds TFIFO empty it assumes that the transmission of data is complete and the trans mission of CRC bits can begin The NOACK bit is functional only in CSMA CD mode and only when the HABEN bit in RSTAT is set The HABEN bit turns on the Hardware Based Ac knowledge feature as described in Section 3 2 6 If this feature is not invoked the NOACK bit will stay at 0 270427 49 Figure 5 2 Transmit Error Flags Logic for Clearing TEN Setting 7 62 OVR GREN RECEIVED 83C152 HARDWARE DESCRIPTION 270427 50 Figure 5 3 Receive Error Flag Logic for Clearing GREN setting RDN If the bit gets set it means the GSC has com pleted a transmission and was expecting to receive a hardware based acknowledge from the receiver of the message but did not receive the acknowledge or at least did not receive it cleanly There are three ways the bit can get set 1 The acknowledge signal an unattached preamble was not received before the IFS was completed 2 collision was detected during the IFS 3 The line was active during the last bit time of the IFS The first condition is an obvious reason for setting the bit since that s what the ha
407. resistive ladder a comparator sample and hold capaci tor successive approximation register A D trigger control a comparison result register and 8 A D result registers as shown in the A D block diagram Figure 16 AVREF must be held within the tolerances stated on the 8XC51GB data sheet The accuracy of the A D cannot be improved for instance by tying AVgrr to the voltage on 6 1 A D Special Function Registers The A D has 10 SFRs associated with it The SFRs are shown in Table 9 ADO RESULT 1 AD6 RESULT ps wa ua am 1 AD7 RESULT Table 9 A D SFRs LSB pore E 084H OF4H MSB LSB CON AIF ACS1 50 AIM 097H MSB LSE cup CMP 1 2 3 4 5 6 AD0 through AD7 contain the results of the 8 analog conversion Each SFR is updated as each conversion is complete starting with the lowest channel and ending with channel 7 ACMP is the comparison result register ACMP is or ganized differently than all the other SFRs in that CMPO occupies the MSB the LSB CMPO TRIGIN Trigger CONVERSION ENABLE i SCAN SELECT AIM AVss 270897 18 Figure 16 A D Block Diagram 6 21 intel 87C51GB HARDWARE DESCRIPTION through CMP7 correspond to analog inputs 0 th
408. resses as XX XX all don t cares This assures the C51FX serial port to be back wards compatibility with other MCS 51 products which do not implement Automatic Addressing 7 4 Baud Rates The baud rate in Mode 0 is fixed Mode 0 Baud Rate S Sen The baud rate in Mode 2 depends on the value of bit SMOD1 in Special Function Register PCON If SMOD1 0 which is the value on reset the baud rate is the oscillator frequency If SMOD 1 the baud rate is the oscillator frequency Oscillator Frequency Mode 2 Baud Rate 25 001 x The rates in Modes and 3 determined by the Timer 1 overflow rate or by Timer 2 overflow rate or by both one for transmit and the other for receive 7 5 Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD1 as fol lows 8XC51FX HARDWARE DESCRIPTION Modes 1 and 3 _ x 1779 1 Overflow Rate Baud Rate 2708 32 The Timer 1 interrupt should be disabled in this appli cation The Timer itself can be configured for either timer or counter operation and in any of its 3 running modes In most applications it is configured for timer operation in the auto reload mode high nibbie of TMOD 0010B In this case the baud rate is given by the formula Modes 1 and 3 _ 2SMOD1 x Oscillator Frequency
409. ressing MOV data addr or by indirect addressing MOV Ri Figure 3 shows the 8051 and the 8052 Data Memory organization 2 4 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 270249 3 Figure 3a The 8051 Data Memory 270249 4 Figure 3b The 8052 Data Memory 2 5 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET INDIRECT ADDRESS AREA Note that in Figure 3b the SFRs and the indirect address RAM have the same addresses 8 Neverthe 1655 they are two separate areas and are accessed two different ways For example the instruction MOV 80H OAAH writes OAAH to Port 0 which is one of the SFRs and the instruction MOV 80 R0 0BBH writes OBBH in location 80H of the data Thus after execution of both of the above instructions Port 0 will contain OAAH and location 80 of the RAM will contain OBBH Note that the stack operations are examples of indirect addressing so the upper 128 bytes of data RAM are available as stack space in those devices which implement 256 bytes of internal RAM DIRECT AND INDIRECT ADDRESS AREA The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments as listed below and shown in Figure 4 1 Register Banks 0 3 Locations O through 1FH 32 bytes ASM 51 and the device after reset default to register bank 0 To use the other register banks the user must select them in the software refer
410. result many interrupt functions that are typical in control applica tions toggling a port pin for example or reloading a timer or unloading a serial buffer can often be com 1 21 pleted in less time than it takes other architectures to commence them SIMULATING A THIRD PRIORITY LEVEL IN SOFTWARE Some applications require more than the two priority levels that are provided by on chip hardware in MCS 51 devices In these cases relatively simple soft ware can be written to produce the same effect as a third priority level First interrupts that are to have higher priority than 1 are assigned to priority 1 in the IP Interrupt Priority register The service routines for priority 1 interrupts that are supposed to be interruptible by priority 2 interrupts are written to include the following code PUSH IE MOV MASK CALL LABEL 12224443 LABEL RETI intel MCS 51 ARCHITECTURAL OVERVIEW As soon as any priority 1 interrupt is acknowledged the IE Interrupt Enable register is re defined so as to disable all but priority 2 interrupts Then a CALL to LABEL executes the RETI instruction which clears the priority 1 interrupt in progress flip flop At this point any priority 1 interrupt that is enabled can be serviced but only priority 2 interrupts are enabled POPping IE restores the original enable byte Then a no
411. rives at the latch during State 6 Phase 2 of the final cycle of the instruc tion However port latches are sampled by their output buffers only during Phase 1 of any clock period Dur ing Phase 2 the output buffer holds the value it saw during the previous Phase 1 Consequently the new value in the port latch won t actually appear at the output pin until the next Phase 1 which will be at 1 1 of the next machine cycle Refer to Figure 3 STATE 2 STATE 3 STATE 4 STATE 5 PO P1 P2 4 5 P1 P2 P4 PS INPUTS SAMPLED RST hide MOV PORT SRC OLD DATA NEW DATA Figure 3 Port Operation SERIAL PORT SHIFT CLOCK MOOE 0 intel 87C51GB HARDWARE DESCRIPTION For more information on internal timings refer to the CPU Timing section If the change requires a O to 1 transition in Ports 1 through 5 an additional pullup is turned on during and 51 2 of the cycle in which the transition occurs This is done to increase the transition speed The extra pullup can source about 100 times the cur rent that the normal pullup can The internal pullups are field effect transistors not linear resistors The pull up arrangements are shown in Figure 4 The pullup consists of three pFETs Note that an n channel FET nFET is turned on when a logical 1 is applied to its gate and is turned off when a logical 0 is applied to its gate p channel FET pFET is the opposite it is on when it
412. rmal RET rather than another RETT is used to terminate the service routine The additional software adds 10 ps at 12 MHz to priority 1 interrupts 1 22 ADDITIONAL REFERENCES The following application notes are found in the Em bedded Control Applications handbook Order Num ber 270648 1 69 An Introduction to the Intel 5 51 Sin gle Chip Microcomputer Family 2 AP 70 Using the Intel MCS 51 Boolean Process ing Capabilities 5 51 5 Guide Instruction Set MCS 51 PROGRAMMER S CONTENTS GUIDE AND INSTRUCTION SET WHAT DO THE SFRs CONTAIN JUST AFTER POWER ON OR RESET PSW PROGRAM STATUS WORD BIT ADDRESSABLE PCON POWER CONTROL REGISTER NOT BIT ADDRESSABLE INTERRUPTS IE INTERRUPT ENABLE REGISTER BIT ADDRESSABLE ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS PRIORITY WITHIN LEVEL IP INTERRUPT PRIORITY REGISTER BIT ADDRESSABLE TCON TIMER COUNTER CONTROL REGISTER BIT ADDRESSABLE TMOD TIMER COUNTER MODE CONTROL REGISTER NOT BIT ADDRESSABLE TIMER SET UP TIMER COUNTER 0 TIMER COUNTER 1 T2CON TIMER COUNTER 2 CONTROL REGISTER BIT ADDRESSABLE TIMER COUNTER 2 SET UP SCON SERIAL PORT CONTROL REGISTER BIT ADDRESSABLE 2 1 5 PAGE CONTENTS PAGE SERIAL PORT SET UP USING TIMER COUNTER 2 TO GENERATE BAUD RATES GENERATING BAUD RATES Serial Portin Mode 6 SERIAL PORT IN MODE 2 Serial Po
413. rols the Timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When Timer O is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate generator or in any applica tion not requiring an interrupt intel 8XC51FX HARDWARE DESCRIPTION CONTROL OVERFLOW INTERRUPT RELOAD INTERRUPT OVERFLOW INTERRUPT Figure 11 Timer Counter 0 Mode 3 Two 8 Bit Counters 5 2 Timer 2 Timer 2 a 16 bit Timer Counter which can operate either as a timer or as an event counter This is selected by bit C T2 in the Special Function Register 2 Table 8 It has three operating modes capture auto reload up or down counting and baud rate generator The modes are selected by bits in 2 as shown in Table 7 5 15 Table 7 Timer 2 Operating Modes 16 Bit Auto Reload 16 Bit Capture Baud Rate Generator Clock Out on P1 0 Timer Off intel 8XC51FX HARDWARE DESCRIPTION Table 8 T2CON Timer Counter 2 Control Register Address 0C8H Reset Value 0000 00008 Bit Addressable 7 6 5 4 3 2 1 0 Function Bit Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and 2 1 When Timer
414. rom the frame and not passed on to the CPU The last 16 bits are then run though the CRC generator to insure that the correct remainder is left The remainder that is checked for is 001110100001111B 1DOF Hex If there is a mis match an error is generated The user software has the option of enabling this interrupt so the CPU is notified 270427 19 Figure 3 8 16 Bit CRC 7 31 intel EOF The End Of Frame EOF indicates when the transmission is complete The EOF is identified by the end flag An end flag consists of the bit pattern 01111110 The EOF can also serve as the BOF for the next frame 3 3 3 DATA ENCODING The transmission of data in SDLC mode is done via NRZI encoding as shown in Figure 3 9 NRZI encod ing transmits data by changing the state of the output whenever 0 is being transmitted Whenever a 1 is transmitted the state of the output remains the same as the previous bit and remains valid for the entire bit time When SDLC mode is selected it automatically enables the NRZI encoding on the transmit line and NRZI decoding on the receive line The Address and Info bytes are transmitted LSB first The CRC is trans mitted MSB first 3 3 4 BIT STUFFING STRIPPING In SDLC mode one of the primary rules of the protocol is that in any normal data transmission there will never be an occurrence of more than 5 consecutive 1s The GSC takes care of this housekeeping chore by automat ically inserting a O after every
415. rough 7 CMPn is set to 1 if the analog input is greater than COMPREF CMPn is cleared if the analog input is less than or equal to COMPREF ACON is the A D control register and contains the A D Interrupt Flag AIF A D Conversion Enable ACE A D Channel Select ACSO and 1 A D Input Mode AIM and A D Trigger Mode ATM 6 2 A D Comparison Mode The A D Comparison mode is always active while the A D converter is enabled The Comparison mode is used to compare each analog input against an external reference voltage applied to COMPREF Whenever the A D converter is triggered each bit in ACMP is updat ed as each analog conversion is completed starting with channel O up to channel 7 regardless of whether Select or Scan mode is invoked The comparison mode can provide a quicker greater than less than sion than can be performed with software and it is more code efficient It can also be used to convert the analog inputs into digital inputs with a variable threshold If the comparison mode is not used COMPREF should be tied to Vcc or Vss 6 3 A D Trigger Mode The analog converter can be triggered either internally or externally To enable internal trigger mode ATM should be cleared When in internal trigger mode A D conversions begin in the machine cycle which follows the setting of the ACE bit The lowest channel see A D Input Modes below is converted first followed by all the other chan nels i
416. rs to the interrupt service routine TRI TCON 6 Timer 1 run control bit Set cleared by software to turn Timer Counter 1 ON OFF TCON 5 Timer 0 overflow Set by hardware when the Timer Counter 0 overflows Cleared by hard ware as processor vectors to the service routine TRO 4 Timer 0 run control bit Set cleared by software to turn Timer Counter 0 ON OFF IEI TCON 3 External Interrupt 1 edge flag Set by hardware when External Interrupt edge is detected Cleared by hardware when interrupt is processed IT1 TCON 2 Interrupt 1 type control bit Set cleared by software to specify falling edge low level triggered External Interrupt IEO TCON 1 External Interrupt 0 edge flag Set by hardware when External Interrupt edge detected Cleared by hardware when interrupt is processed ITO TCON 0 Interrupt 0 type control bit Set cleared by software to specify failing edge low level triggered External Interrupt TMOD TIMER COUNTER MODE CONTROL REGISTER NOT BIT ADDRESSABLE m Mo m Wo CIS FD NEC A l te is TIMER 1 TIMER 0 When TRx is set and GATE 1 TIMER COUNTERx will run only while INTx pin is high hardware control When GATE 0 TIMER COUNTERx will run only while TRx 1 software control C T Timer or Counter selector Cleared for Timer operation input from internal system clock Set for Coun ter operation input from Tx input pin
417. rt 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1s This occurs when the MOVX DPTR instruction is executed During this time the Port 2 latch the Special Function Regis ter does not have to contain 1s and the contents of the Port 2 SFR are not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the Port 2 SFR will reappear in the next cycle If an 8 bit address is being used MOVX Ri the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle In this case Port 2 pins can be used to page the external data mem In either case the low byte of the address is time multi plexed with the data byte on Port 0 The ADDRESS DATA signal drives both FETs in the Port 0 output buffers Thus in external bus mode the Port 0 pins are not open drain outputs and do not require external pullups The ALE Address Latch Enable signal should be used to capture the address byte into an ex ternal latch The address byte is valid at the negative transition of ALE Then in a write cycle the data byte to be written appears on Port 0 just before WR is acti vated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at Port 0 just before the read strobe RD is deactivated During any access to external memory the CPU writes OFFH to the
418. rt in Mode 1 SERIAL PORT IN MODE 3 USING TIMER COUNTER 1 TO 59 51 INSTRUCTION SET GENERATE BAUD RATES INSTRUCTION DEFINITIONS 2 2 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET The information presented in this chapter is collected from the MCS 51 Architectural Overview and the Hardware Description of the 8051 8052 and 80C51 chapters of this book The material has been selected and rearranged to form a quick and convenient reference for the programmers of the MCS 51 This guide pertains specifically to the 8051 8052 and 80C51 MEMORY ORGANIZATION PROGRAM MEMORY The 8051 has separate address spaces for Program Memory and Data Memory The Program Memory can be up to 64K bytes long The lower 4K 8K for the 8052 may reside on chip Figure 1 shows a map of the 8051 program memory and Figure 2 shows a map of the 8052 program memory 270249 1 Figure 1 The 8051 Program Memory intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 270249 2 Figure 2 The 8052 Program Memory Data Memory The 8051 can address up to 64K bytes of Data Memory external to the chip The MOVX instruction is used to access the external data memory Refer to the MCS 51 Instruction Set in this chapter for detailed description of instructions The 8051 has 128 bytes of on chip RAM 256 bytes in the 8052 plus a number of Special Function Registers SFRs The lower 128 bytes of RAM can be accessed either by direct add
419. ructions test the Accumulator data for that condi tion e MCS 51 HMOS OR CHMOS The DJNZ instruction Decrement and Jump if Not QUARTZ CRYSTAL Zero is for loop control To execute a loop N times load counter byte with N and terminate loop with a DJNZ to the beginning of the loop as shown below for N 10 MOV COUNTER 10 LOOP begin loop end loop DJNZ COUNTER LOOP continue The CJNE instruction Compare and Jump if Not Equal can also be used for loop control as in Figure 12 Two bytes are specified in the operand field of the in struction The jump is executed only if the two bytes are not equal In the example of Figure 12 the two 270251 12 bytes were the data in R1 and the constant 2AH The A CHMOS initial data in R1 was 2EH Every time the loop was executed R1 was decremented and the looping was to continue until the R1 data reached 2 Another application of this instruction is in greater than less than comparisons The two bytes in the op erand field are taken as unsigned integers If the first is less than the second then the Carry bit is set 1 If the first is greater than or equal to the second then the Carry bit is cleared 270251 13 5 TIMING All 5 51 microcontrollers have an on chip oscillator which can be used if desired as the clock source for the CPU To use the on chip oscillator connect a crystal or c
420. rvice routine at 53H is invoked when DCON1 1 DONE is set and EDMA1 is enabled invoked if TDN is set when the GSC is under DMA control and is invoked if CRCE OVR RCABT or AE is set when the GSC is under CPU or DMA control and EGSRE is enabled EGSRV IEN1 0 invoked if RDN is set when the GSC is under DMA control and EGSRV is enabled IPN1 is used the same way the current 80C51BH interrupt priority register IP is By assigning a 1 to the 4BH is invoked if NOACK or TCDT is set when the GSC is EGSTV IEN1 3 043H GSC TRANSMIT VALID The interrupt service routine at 43H EGSTV is enabled GSC RECEIVE VALID The interrupt service routine at 2BH appropriate bit that interrupt has a higher priority than interrupt with a 0 assigned to it in the priority register The new interrupt priority register IPN1 contents are C ema ema GECTRANSMTVAUD C rese GSCRECENEERNOR Nto GSCRECENEVAID 7 11 intel 83C152 HARDWARE DESCRIPTION The eleven interrupts are sampled in the following order when assigned the same priority level in the IP and IPN1 registers Priority Priority interrupt Interrupt Priority Symbolic Symbolic Symbolic Symbolic Sequence Address Name Address Name 1 FIRST 2 3 4 5 6 7 8 9 10 11 LAST 2 3 Reset RESET performs the same operations in both the 80C51BH and the C152 and those conditions that exist at
421. s of the oscillator frequency To ensure that a given level is sampled at least once before it changes it Should be held for at least one full machine cycle In the Counter function the register is incremented in response to a 1 10 0 transition at its corresponding ex Table 3 T2ZCON Timer Counter 2 Control Register T2CON Address Bit Addressable EXF2 RCLK TCLK EXEN2 CP T2 CP RL2 7 6 5 4 3 2 1 0 Symbol TF2 Reset Value 0000 00008 Bit Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 Timer 2 external flag set when either a capture or reload is caused by a negative transition on 2 and EXEN2 1 When Timer 2 interrupt is enabled 2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 Receive clock enable When set causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock EXF2 Transmit clock enable When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable When set allows a capture or reload to occur as a result of a n
422. s For a given pin they vary with pin loading temperature and manufacturing lot If the XTAL1 waveform is taken as the timing reference propagation delays may vary from 25 ns to 125 ns The AC Timings section of the data sheets do not refer ence any timing to the XTAL1 waveform Rather they relate the critical edges of control and input signals to each other The timings published in the data sheets include the effects of propagation delays under the specified test condition 8 5168 XTAL2 XTAL1 270897 40 Figure 40 Driving the CHMOS Devices with an External Clock Sources wn 83C152 Hardware 7 Description 83 152 HARDWARE CONTENTS PAGE DESCRIPTION o INTRODUCTION 2 0 COMPARISON OF 80C152 AND 80C51BH FEATURES 2 4 Ports 4 5 and 6 2 5 Timers Counters 3 8 Serial Backplane vs Networ Environment 4 0 DMA OPERATION 4 1 DMA with the 80C152 5 1 GSC Transmitter Error Conditions 7 1 intel 83C152 HARDWARE DESCRIPTION 1 0 INTRODUCTION The 83C152 Universal Communications Controller is an 8 bit microcontroller designed for the intelligent management of peripheral systems or components The 83C152 is a derivative of the 80C51BH and retains the same functionality The 83C152 is fabricated on the same CHMOS process as the 80C51BH What makes the 83C152 different is that it has added func tions and peripherals to the basic 80C51BH architec ture that are supported by new Special Functio
423. s For other instructions it can be treat ed as another scratch pad register Stack Pointer The Stack Pointer Register is 8 bits wide Jt is incremented before data is stored during PUSH and CALL executions The stack may reside anywhere in on chip RAM On reset the Stack Pointer is initialized to 07H causing the stack to begin at loca tion 08H Data Pointer The Data Pointer DPTR consists of a high byte DPH and a low byte DPL Its intended function is to hold a 16 bit address but it may be ma nipulated as a 16 bit register or as two independent 8 bit registers Program Status Word The PSW register contains pro gram status information as detailed in Table 2 87C51GB HARDWARE DESCRIPTION Ports 0 to 5 Registers PO P1 P2 P3 P4 and P5 are the SFR latches of Ports 0 through 5 respectively Timer Registers Register pairs THO TLO 1 TL 1 and TH2 TL2 are the 16 bit count registers for Timer Counters 0 1 and 2 respectively Control and status bits are contained in registers TCON and TMOD for Timers 0 and 1 and in registers T2CON and T2MOD for Timer 2 The register pair RCAP2H RCAP2L are the capture reload registers for Timer 2 in 16 bit capture mode or 16 bit auto reload mode Programmable Counter Array and 1 Regis ters The 16 bit PCA and PCA timer counters consist of register CH CH1 and CL CL1 Registers CCON 1 and contain the control and status bit
424. s data The re ceive FIFO is a three byte buffer into which the receive data is loaded A CPU read of the FIFO retrieves the oldest data and automatically updates the FIFO point ers Setting GREN to a one will clear the receive FIFO The status of this flag is controlled by the GSC It is cleared if user empties receive FIFO RSTAT 3 RDN Receive Done If set indicates the successful completion of a receiver operation Will not be set if CRC alignment abort or FIFO overrun error occurred The status of this flag is controlled by the GSC RSTAT 4 CRC Error If set indicates that properly aligned frame was received with a mismatched CRC The status of this flag is controlled by the GSC RSTAT 5 AE Alignment Error In CSMA CD mode AE is set if the receiver shift register an internal serial to parallel converter is not full and the CRC is bad when an EOF is detected In CSMA CD the EOF is a line idle condition see LNI for two bit times If the CRC is correct while in CSMA CD mode AE is not set and any mis alignment is assumed to be caused by dribble bits as the line went idle In SDLC mode AE is set if a non byte aligned flag is received CRCE may also be set The setting of this flag is controlled by the GSC 7 46 RSTAT 6 RCABT Receiver Collision Abort Detect If set indicates that a collision was detected after data had been loaded into the receive FIFO CSMA CD mode In SDLC mode RCAB
425. s for the PCA and The 0 1 2 3 or 4 and the 1 registers control the mode for each of the five PCA and the five PCA1 modules The register pairs CCAPnH CCAPnL and CICAPnH CICAPnL are the 16 bit compare capture registers for each PCA and 1 module Serial Port Registers The Serial Data Buffer SBUF is actually two separate registers a transmit buffer and a receive buffer register When data is moved to SBUF it comes from the receive buffer Register SCON contains the control and status bits for the Serial Port Registers SADDR and SADEN are used to define the Given and the Broadcast addresses for the Automatic Address Recognition feature Table 2 PSW Program Status Word Register Address Bit Addressable Bit 6 5 Function Carry flag Auxiliary Carry flag For BCD Operations Flag 0 Available to the user for general purposes Register bank select bit 1 Register bank select bit 0 851 RSO Reset Value 0000 0000B cv ac 7 4 3 2 1 0 Working Register Bank and Address Bank 0 Bank 1 Bank 2 Bank 3 00 07 08H OFH 10H 17H 18H 1FH Overflow flag User definable flag Parity flag Set cleared by hardware each instruction cycle to indicate an odd even number of one bits in the Accumulator i e even parity intel Serial Expansion Port Registers The Serial Expansion Port is control
426. s gate sees a 0 and off when its gate sees a 1 pFET 1 is the transistor that is turned on for 2 oscilla tor periods after a O to 1 transition in the port latch A 1 at the port pin turns on pFET3 a weak pullup through the inverter This inverter and pFET form a latch which hold the 1 If the pin is emitting a 1 a negative glitch on the pin from some external source can turn off pFET2 causing the pin to go into a float state pFET2 is a very weak pullup which is on whenever the nFET is off in tradi tional CMOS style It s only about the strength of 2 Its function is to restore a 1 to the pin in the event the pin had a 1 and lost it to a glitch 2 OSC PERIODS Qo FROM PORT LATCH 4 3 Port Loading and Interfacing The output buffers of Ports 1 through 5 can each sink at least the amount of current specified by Vor in the data sheet These port pins can be driven by open col lector and open drain outputs although 0 1 tran sitions will not be fast since there is little current pull ing the up An input 0 turns off pullup pFET2 leaving only the very weak pullup pFET 2 to drive the transition In external bus mode Port 0 output buffers can each sink the amount of current specified at the test condi tions for VOL in the data sheet However as port pins they require external pullups to be able to drive any inputs See the latest revision of the data sheet for design in information 4 4 Read Modi
427. s obliterating whatever information the Port 0 SFR may have been holding If the user writes to Port O during an externa memory fetch the incoming code byte is corrupted Therefore do not write to Port 0 if external program memory is used External Program Memory is accessed under two con ditions 1 Whenever signal is active or 2 Whenever the program counter PC contains a number that is larger than OFFFH 1FFFH for the 8052 This requires that the ROMless versions have EA wired low to enable the lower 4K 8K for the 8032 program bytes to be fetched from external memory When the CPU is executing out of external Program Memory all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose I O During external program fetches they output the high byte of the PC During this time the Port 2 drivers use the strong pullups to emit PC bits that are 1s TIMER COUNTERS The 8051 has two 16 bit Timer Counter registers Tim er 0 and Timer 1 The 8052 has these two plus one intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 more Timer 2 three be configured to operate either as timers or event counters In the Timer function the register is incremented every machine cycle Thus one can think of it as count ing machine cycles Since a machine cycle consists of 12 oscillator periods the count rate is 1 of the oscillator frequency In the Counter f
428. s operating in it normal mode and interrupts oc cur on and RFNE For more information on DMA servicing please refer to the DMA section on serial demand mode 4 2 2 3 TSTAT 1 TEN Transmit Enable When set causes TDN UR TCDT and NOACK flags to be reset and the TFIFO cleared The transmitter will clear TEN af 7 70 83C152 HARDWARE DESCRIPTION ter successful transmission a collision during the data CRC or end flag cleared during a transmission the GSC transmit pin goes to a steady state high level This is the method used to send an abort character in SDLC Also DEN is forced to a high level The end of transmission occurs whenever the TFIFO is emptied TSTAT 2 TFNF Transmit FIFO not full When set indicates that new data may be written into the transmit FIFO The transmit FIFO is a three byte buff er that loads the transmit shift register with data TSTAT 3 TDN Transmit Done When set indi cates the successful completion of a frame transmission If HBAEN is set TDN will not be set until the end of the IFS following the transmitted message so that the acknowledge can be checked If an acknowledge is ex pected and not received TDN is not set An acknowl edge is not expected following a broadcast or multi cast packet TSTAT 4 TCDT Transmit Collision Detect If set indicates that the transmitter halted due to a collision It is set if a collision occurs during the data or CRC or
429. scussed in Section 3 3 4 All the procedures required for bit stuffing and bit stripping are automatically han dled by the GSC In standard SDLC protocol the BOF signals the start of a frame and is limited to 8 bits in length Since there is no preamble in SDLC the BOF is considered an entire separate field and marks the beginning of the frame The BOF also serves as the clock synchronization mechanism and the reference point for determining the position of the address and control fields ADDRESS The address field is used to identify which stations the message is intended for Each secondary station must have a unique address The primary sta tion must then be made aware of which addresses are assigned to each station The address length is specified as 8 bits in standard SDLC protocols but it is expand able to 16 bits in the C152 User software can further expand the number of address bits but the automatic address recognition feature works on a maximum of 16 bits In SDLC the addresses are normally unique for each station However there are several classes of messages that are intended for more than one station These mes sages are called broadcast and group addressed frames An address consisting of all 1s will always be automati cally received by the GSC this is defined as the broad cast address in SDLC A group address is an address that is common to more than one station The GSC provides address masking bits to provide th
430. see IPN1 Priority bit for GSC Receive Valid interrupt see IPNI PGSTE Priority bit for GSC Transmit Error inter rupt see IPN1 PGSTV Priority bit for GSC Transmit Valid inter rupt see PLO One of two bits that determines the Preamble Length see GMOD One of two bits that determines the Preamble Length see GMOD PRBS OE4H Pseudo Random Binary Sequence gen erates the pseudo random number to be used in CSMA CD backoff algorithms PS Priority bit for the LSC service interrupt see IP Priority bit for Timer 0 interrupt see IP PT1 Priority bit for Timer 1 interrupt see IP PXO Priority bit for External interrupt O see IP Priority bit for External interrupt 1 see IP GSC Receiver Abort error bit see RSTAT RDN GSC Receiver Done bit see RSTAT GREN GSC Receiver Enable bit see RSTAT RFNE GSC Receive FIFO Not Empty bit see RSTAT 83C152 HARDWARE DESCRIPTION RI LSC Receive Interrupt bit see SCON RFIFO 4 RFIFO is a 3 byte FIFO that contains the receive data from the GSC RSTAT OE8H Receive Status Register 7 6 5 4 3 2 1 0 OvR RCABT AE CRCE RDN RFNE GREN HABEN RSTAT 0 HBAEN Hardware Based Acknowledge Enable If set enables the hardware based acknowl edge feature RSTAT 1 GREN Receiver Enable When set the receiver is enabled to accept incoming frames The user must clear RFIFO with softwa
431. set by hardware when an external interrupt edge Interrupt 5 Edge flag This bit is set by hardware when an external interrupt edge Interrupt 4 Edge flag This bit is set by hardware when an external interrupt edge Interrupt 3 Edge flag This bit is set by hardware when an external interrupt edge Interrupt 2 Edge flag This bit is set by hardware when an external interrupt edge Interrupt 3 Type control bit This bit is set or cleared by software to control whether INT3 is positive or negative transition activated When ITS is high IE3 is set by a positive transition on pin INT3 When is low IE3 is set by a negative transition on pin INT3 Interrupt 2 Type control bit This bit is set or cleared by software to control whether INT2 is positive or negative transition activated When IT2 is high 22 is set by a positive transition on pin INT2 When IT2 is low IE2 is set by a negative transition on pin INT2 Using software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from reserved bit is indeterminate The flags that actually generate the interrupts are bits IE1 in TCON IE2 IES and IE6 in EXICON These flags are cleared by hardware when the service routine is vectored to if the interrupt was transition activated
432. set or not The OFD is automatically enabled when the device comes out of reset or when Power Down is exited with a reset or an interrupt The OFD is intended to function only in situations where there is a gross failure of the oscillator such as a intel 87C51GB HARDWARE DESCRIPTION broken crystal To fulfill this need the OFD trigger fre quency is significantly below the normal operating fre quency The OFD will not reset the 8XC51GB if the oscillator frequency should change to another point within the operating range 11 1 OFD During Power Down In Power Down the 8XC51GB oscillator stops in or der to conserve power To prevent the 8 51 from immediately resetting itself out of power down the OFD must be disabled prior to setting the PD bit Writ ing the sequence 01EH to the OSCillatoR OSCR SFR turns the OFD off Once disabled the OFD can only be re enabled by a reset or exit from Power Down with an interrupt The status of the OFD whether on or off can be determined by reading OSCR The LSB indicates the status of the OFD The upper 7 bits of OSCR will always be 1s when read If OSCR OFFH the OFD is enabled If OSCR OFEH the OFD is disabled 12 0 INTERRUPTS The 8XC51GB has a total of 15 interrupt vectors seven external interrupts INTO INT1 INT2 INT3 INT4 5 and INTO three timer interrupts Timers 0 1 and 2 two interrupts PCAO and 1 the A D interrupt th
433. should not be written to prior to setting TEN If TEN is already set transmission begins as soon as data is written to TFI FO TSTAT 008 Transmit Status Register 7 6 5 4 3 2 1 0 Lint NoACK UR TEN Figure 3 17 5 DMA DMA Select If set indicates that channels used to service the GSC FIFO s and GSC interrupts occur and and also ables UR to become set If cleared indicates that the GSC is operating in its normal mode and interrupts occur on TENF and RENE For more information on DMA servicing please refer to the DMA section on DMA serial demand mode 4 2 2 3 The user software is responsible for setting or clearing this flag ntel 83C152 HARDWARE DESCRIPTION TSTAT 1 TEN Transmit Enable When set causes TDN UR TCDT and NOACK flag to be reset and the TFIFO cleared The transmitter will clear TEN af ter a successful transmission a collision during the data CRC or end flag The user software is responsible for setting but the GSC or user software may clear this flag If cleared during a transmission the GSC transmit pin goes to a steady state high level This is the method used to send an abort character in SDLC Also DEN is forced to a high level The end of transmission occurs whenever the TFIFO is emptied TSTAT 2 TFNF Transmit FIFO not full When set indicates that new data may be written into the
434. sovertyisdisabled a P P P Sameas3 also extemal execution is disabled intel 8XC51FX HARDWARE DESCRIPTION 14 0 ON CHIP OSCILLATOR The on chip oscillator for the CHMOS devices shown in Figure 29 consists of a single stage linear inverter intended for use as a crystal controlled positive reac tance oscillator In this application the crystal is operat ing in its fundamental response mode as an inductive reactance in parallel resonance with capacitance exter nal to the crystal Figure 30 The oscillator on the CHMOS devices can be turned off under software control by setting the PD bit in the PCON register The feedback resistor Rr in Figure 29 consists of paralleled n and p channe FETs controlled by the PD bit such that Rf is opened when PD 1 The diodes D1 and D2 which act as clamps to Vss are parasitic to the Rr FETs The crystal specifications and capacitance values C1 and C2 in Figure 30 are not critical 30 pF can be used in these positions at any frequency with good quality crystals In general crystals used with these devices typically have the following specifications ESR Equivalent Series Resistance see Figure 32 shunt capacitance load capacitance Drive Level 7 0 pF maximum 30 pF 3 pF 1 MW Frequency tolerance and temperature range are deter mined by the system requirements ceramic resonator can be used in place of the crystal in
435. ss byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be com ing The slaves that weren t being addressed leave their 25 set and go on about their business ignoring the coming data bytes SM2 has no effect in Mode 0 and in Mode 1 can be used to check the validity of the stop bit In Mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received Serial Port Control Register The serial port control and status register is the Special Function Register SCON shown in Figure 14 This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and 8 and the serial port interrupt bits TI and RI intel HARDWARE DESCRIPTION OF THE 8051 8052 80 51 270252 13 Figure 13 Timer 2 in Auto Reload Mode MSB 58 smo Sw sm2 REN Where SM0 SM1 specify the serial port mode as follows SMO SM1 Mode Description Baud Rate O shifttregister 105 12 1 BbtUART variable 2 bit UART fosc 64 or 32 3 9 bit UART variable enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then will not be activated if the received 9th data bit RB8 is O In Mode 1
436. ssages are called broadcast multicast group addresses broadcast address consisting of all 1s will always be received by all stations multicast group address usually is indi cated by using a las the first address bit The user can choose to mask off all or selective bits of the address so that the GSC receives all messages or multicast group messages The address length is programmable to be 8 or 16 bits An address consisting of all 1s will always be received by the GSC on the C152 The address bits are always passed from the GSC to the CPU With user software the address can be extended beyond 16 bits but the automatic address recognition will only work on a maximum of 16 bits User software will have to resolve any remaining address bits INFO This is the information field and contains the data that one device on the link wishes to transmit to another device It can be of any length the user wishes but needs to be in multiples of 8 bits This is because multiples of 8 bits are used to transfer data into or out of the GSC FIFOs The information field is delineated from the rest of the components of the frame by the preceding address field and the following CRC The receiver determines the position of the end of the infor mation field by passing the bytes through a temporary storage space When the EOF is received the bytes in temporary storage are the CRC and the last bit re ceived previous to the CRC constitute the end of th
437. sses is eliminated Automatic address recognition is enabled by setting the SM2 bit in SCON With this feature enabled in one of the 9 bit modes the Receive Interrupt RI flag will only get set when the received byte corresponds to ei ther a Given or Broadcast address The master can selectively communicate with groups of slaves by using the Given Address Addressing all slaves at once is possible with the Broadcast Address These addresses are defined for each slave by two Spe cial Function Registers SADDR and SADEN A slave s individual address is specified in SADDR SADEN is a mask byte that defines don t cares to form the Given Address These don t cares allow flexibility in the user defined protocol to address one or more slaves at a time The following is an example of how the user could define Given Addresses to selectively ad dress different slaves Slave 1 SADDR 1111 0001 SADEN 1111 1010 GIVEN 1111 0 0 Slave 2 SADDR 1111 0011 SADEN 1111 1001 GIVEN 1111 0XX1 The SADEN bytes are selected such that each slave can be addressed separately Notice that bit 1 LSB is a don t care for Slave 1 5 Given Address but bit 1 1 for Slave 2 Thus to selectively communicate with just Slave 1 the master must send an address with bit 1 0 e g 1111 0000 Similarly bit 2 O for Slave 1 but is a don t care for Slave 2 Now to communicate with just Slave 2 an address with bit 2 1 must be used e g 1111 0111
438. ster T marn Toon ________ 3 X iestessretraposbee sige on X x o iestessre tva negatee doo ager on D px o Ese x X Don t Care 5 23 8XC51FX HARDWARE DESCRIPTION 6 3 16 Bit Capture Mode Both positive and negative transitions can trigger ture with the This gives the the flexibility to measure periods pulse widths duty cycles and phase differences on up to five separate inputs Setting the CAPPn and or CAPNn in the CCAPMn mode register select the input trigger positive and or negative tran sition for module n Refer to Figure 17 The external input pins CEXO through CEX4 are sam pled for a transition When a valid transition is detected positive and or negative edge hardware loads the 16 bit value of the PCA timer CH CL into the mod ule s capture registers CCAPnH CCAPnL The re sulting value in the capture registers reflects the PCA timer value at the time a transition was detected on the CEXn pin Upon a capture the module s event flag CCFn in CCON is set and an interrupt is flagged if the ECCFn bit in the mode register CCAPMn is set The in terrupt will then be generated if it is enabled
439. struction cycle previous dma cycle NOT DMAn return 1 return 0 end mode logic n Figure 4 13 DMA Mode Logic 7 57 intel If the channel is configured to External Demand mode then the first if condition is not satisfied but the second one is In that case the block of statements following that if condition and delimited is executed if the demand flag for channel 0 and IE1 for chan nel 1 is set the return 1 expression is executed and the remainder of the function is not If the demand flag is not set the return 0 expression is executed and the remainder of the function is not If the channel is configured to Serial Port Demand mode the source and destination addresses SARn and DARmn have to be checked to see which Serial Port buffer is being addressed and whether its demand flag is set SARn refers to the 16 bit source address for this chan nel Note that the condition SARn SBUF cannot be true unless the SAS and ISA bits in DCONn are configured to select SFR space If SARn is numeri cally equal to the address of SBUF 99H and SAS and ISA are configured to select internal RAM rather than SFR space then SARn refers to location 99H in the upper 128 of internal RAM not to SBUF If the test for SARn SBUF is true and if the flag RI is set mode logic n returns as 1 and the remainder of the function is not executed Otherwise execution proceeds t
440. struction will be executed before any interrupt is vec tored to The polling cycle is repeated with each machine cycle and the values polled are the values that were present at SSP2 of the previous machine cycle Note then that if an interrupt flag is active but not being responded to for one of the above conditions and is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle is new The polling cycle LCALL sequence is illustrated in Figure 24 Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 24 then in accordance with the above rules it will be vectored to during C5 and C6 without any in struction of the lower priority routine having been exe cuted Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the ap propriate servicing routine In some cases it also clears the flag that generated the interrupt and in other cases it doesn t It never clears the Serial Port or Timer 2 flags This has to be done in the user s software clears an external interrupt or IE1 only if it was transition activated hardware generated LCALL pushes the contents of the Program Counter onto the stack but it does not save the PSW and re loads the PC
441. t again Inhibit Arbiter s DMA to XRAM HLDA Output 1 6 270427 39 Figure 4 8 internal Logic of the Arbiter 7 53 HLDA Input 1 6 83 152 HARDWARE DESCRIPTION HLD Input N 1 CPU Ose Periods HHHHHHHHHHHHHHHHHHH Clock 1 I t Clock 2 4 HUDA Output i 1 I t 2 Osc 4032 Periods Periods 270427 40 Figure 4 9 Minimum HLD HLDA Response Time Inhibit Requester s DMA to XRAM HLD Output P1 5 270427 41 Figure 4 10 Internal Logic of the Requester Clock 1 and Clock 2 are Shown in Figure 4 9 7 54 intel 83C152 HARDWARE DESCRIPTION 4 3 5 Internal Logic of the Requester The internal logic of the requester is shown in Figure 4 10 Initially the requester s internal signal DMXRQ to XRAM Request is at 0 so Q2 is set and the HLD output is high As long as Q2 stays set the re quester is inhibited from starting any DMA to XRAM When the requester wants to DMA the XRAM it first activates DMXRQ This signal enables Q2 to be cleared but doesn t clear it and if HLDA is high also acti vates the HLD output 1 to 0 transition from HLDA can now clear Q2 which will enable the requester to commence its DMA to XRAM Q2 being low also maintains an output low at HLD When the DMA is completed DMXRQ goes to 0 which sets Q2 and de activates HLD Only DMXRQ going to 0 can set Q2 That means once Q2 gets
442. t 1 pins P1 2 Its purpose is to enable external drivers when the GSC is transmitting data This function is always active when using the GSC and if P1 2 is programmed to a DM DMA Mode see DCONO DMA Direct Memory Access mode see TSTAT DONE done bit see DCONO DPH Data Pointer High an SFR that contains the high order byte of a general purpose pointer called the data pointer DPTR DPL Data Pointer Low an SFR that contains the low order byte of the data pointer EDMAO Enable DMA Channel O interrupt see Enable DMA Channel 1 interrupt see IENI EGSRE Enable GSC Receive Error interrupt see IEN1 EGSRV Enable GSC Receive Valid interrupt see EGSTE Enable GSC Transmit Error interrupt see EGSTV Enable GSC Transmit Valid interrupt see IENI EOF A general term used in serial communications EOF stands for End Of Frame and signifies when the last bits of data are transmitted when using packetized data ES Enable LSC Service interrupt see IE Enable Timer 0 interrupt see IE Enable Timer 1 interrupt see IE Enable External interrupt 0 see IE Enable External interrupt 1 see IE 7 65 GMOD 84H 7 6 5 4 3 2 1 0 Drew wo ac Pr mo Pn The bits in this SFR perform most of the configuration on the type of data transfers to be used with the GSC Determines the mode address length pre
443. t 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1s This is during the execution of a MOVX DPTR instruction During this time the Port 2 latch the Special Function Register does not have to contain 1s and the contents of the Port 2 SFR not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the Port 2 SFR will reappear in the next cycle If an 8 bit address is being used MOVX GRi the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle This will facili tate paging In any case the low byte of the address is time multi plexed with the data byte on Port 0 The ADDR signal drives both FETs in the Port 0 output buffers Thus in this application the Port O pins are not open drain outputs and do not require externa pull ups Signal ALE Address Latch Enable should be used to capture the address byte into an external latch The address byte is valid at the negative transition of ALE Then in a write cycle the data byte to be written appears on Port 0 just before WR is activated and re mains there until after WR is deactivated a read cycle the incoming byte is accepted at Port 0 just be fore the read strobe is deactivated During any access to external memory the CPU writes OFFH to the Port 0 latch the Special Function Regis ter thu
444. t during a used slot time then there will probably be a collision The actions the re ceiver does take when detecting a collision is to just stop receiving data if data has not been loaded into RFIFO or to stop reception clear receiver enable REN and set the receiver abort flag RCABT RSTAT 6 If deterministic resolution is used the transmitting sta tions go through pretty much the same process as in normal back off except that the slots are predeter mined All the receivers go through the back off algo rithm and may only transmit during their assigned slot 3 6 4 SUCCESSFUL ENDING OF TRANSMISSIONS AND RECEPTIONS In both CSMA CD and SDLC modes the TDN bit is set and TEN cleared at the end of a successful trans mission The end of the transmission occurs when the TFIFO is empty and the last byte has been transmitted In CSMA CD the user should clear the TCDCNT reg ister after successful transmission At the end of a successful reception the bit is set and GREN is cleared The end of reception occurs when the EOF flag is detected by the GSC hardware 83 152 HARDWARE DESCRIPTION 3 7 Register Descriptions ADRO0 1 2 3 95H 0A5H OBSH OC5H Address Match Registers 0 1 2 3 Contains the address match values which determines which data will be accepted as valid In 8 bit addressing mode a match with any of the four registers will trigger acceptance In 16 bit address ing mode a match with ADR1 ADR
445. t will be de scribed later The loop 15 executed from LOOP to for R1 2EH 2DH 2CH and 2BH At that point the digit that was originally shifted out on the right has propagated to location 2AH Since that location should be left with Os the lost digit is moved to the Accumulator intel MCS 51 ARCHITECTURAL OVERVIEW EXTERNAL RAM Table 5 shows a list of the Data Transfer instructions that access external Data Memory Only indirect ad dressing can be used The choice is whether to use a one byte address Ri where Ri can be either RO or R1 of the selected register bank or two byte address DPTR The disadvantage to using 16 bit addresses if only a few K bytes of external RAM are involved is that 16 bit addresses use all 8 bits of Port 2 as address bus On the other hand 8 bit addresses allow one to address a few K bytes of RAM as shown in Figure 5 without having to sacrifice all of Port 2 All of these instructions execute in 2 ps with a 12 MHz clock Table 5 A List of the MCS 51 Data Transfer Instructions that Access External Data Memory Space s SES ECILTCNE NEN nomena prima EN Note that in all external Data RAM accesses the Ac cumulator is always either the destination or source of the data The read and write strobes to external RAM are acti vated only during the execution of a instruc tion Normally these signals ar
446. t will be transmitted in Modes 2 and 3 Set or clear by software as desired In modes 2 and 3 the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software NOTE SMODO is located at PCONG Fosc oscillator frequency The serial port can operate in 4 modes In all four modes transmission is initiated by any in 0 Shift Register fr struction that uses SBUF as a destination register Re t fixed frequency ception is initiated in Mode 0 by the condition RI 0 Mode 1 8 Bit UART variable frequency and REN 1 Reception is initiated in the other Mode 2 9 Bit UART fixed frequency modes by the incoming start bit if REN 1 Mode 3 9 Bit UART variable fi ES Mode 0 Serial data enters and exits through RXD The baud rate i odes is fixed and in others i TXD outputs the shift clock 8 bits are transmitted re generated by Timer lor Timer 2 6 data bits LSB first The baud rate is fixed at 1 12 the oscillator frequency 87C51GB HARDWARE DE
447. tablishes TLO and THO as two separate counters TLO uses the Timer O control bits C T0 GATEO TRO THO is locked into a INTERRUPT 270897 12 INTERRUPT OVERFLOW INTERRUPT 270897 13 Figure 11 Timer Counter 0 Mode 3 Two 8 Bit Counters 6 16 intel timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus TH0 now controls the Timer 1 interrupt The logic for Mode 3 on Timer 0 is shown in Figure 11 3 15 provided for applications requiring an extra 8 bit or counter When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate generator or in applica tion not requiring an interrupt 5 2 Timer 2 Timer 2 is a 16 bit Timer Counter which can operate either as a timer or as an event counter This is selected by bit C T2 in the SFR T2CON Table 7 It has the following three operating modes Timer 2 Capture 87C51GB HARDWARE DESCRIPTION Timer 2 Auto Reload up or down counting and Timer 2 as a Baud Rate Generator The modes are also selected by bits in T2CON as Shown in Table 6 Table 6 Timer 2 Operating Modes RCLK 2 2 2 Mode 0 0 1 test Auto Reload 16 Bit Capture Baud Rate Generator Clock Out on P1 0 Timer Oft Present only on the 87C51FC Table 7 T2CON T
448. tail intel 8XC51FX HARDWARE DESCRIPTION Table 12 CCAPMn PCA Modules Compare Capture Registers CCAPMn Address ODAH Reset Value X000 00008 n 0 4 CCAPM1 ODBH CCAPM2 ODCH CCAPM3 ODDH ODEH Not Bit Addressable __ __ cAPPn caPNn TOGn PWMn ECCFn 7 6 5 4 3 2 1 0 Symbol Function Bit Not implemented reserved for future use ECOMn Enable Comparator ECOMn 1 enables the comparator function CAPPn Capture Positive CAPPn 1 enables positive edge capture CAPNn Capture Negative 1 enables negative edge capture MATn Match When MATn 1 match of the counter with this module s compare capture register causes the CCFn bit in CCON to be set flagging an interrupt TOGn Toggle When TOGn 1 a match of the PCA counter with this module s compare capture register causes the CEXn pin to toggle PWMn Pulse Width Modulation Mode PWMn 1 enables the CEXn pin to be used as a pulse width modulated output ECCFn Enable CCF interrupt Enables compare capture flag CCFn in the CCON register to generate an interrupt NOTE User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate Table 13 PCA Module Modes CCAPMn Regi
449. ted otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified The carry flag is set The instruction sequence JNC LABEL CPL C JNC LABEL2 will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2 2 2 JNC lt 2 IF 0 lt 2 49 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JNZ rel Function Description Example Bytes Cycles Encoding Operation JZ Jump if Accumulator Not Zero If any bit of the Accumulator is a one branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative dis placement in the second instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally holds 00H The instruction sequence JNZ LABELI INC A JNZ LABEL2 will set the Accumulator to 01H and continue at label LABEL2 2 2 0111 0000 JNZ PC lt PC 2 IF 0 address rel Function Description Example Bytes Cycles Encoding Operation Jump if Accumulat
450. ter the DMAO cycle channel 0 must wait for an Instruction cycle before it can access TFIFO again Channel 1 being in Burst mode doesn t have that restriction and is therefore granted a DMA 1 cycle After the first DMA1 cycle channel 0 is still waiting for an Instruction cycle and channel 1 still does not have that restriction There follows another DMA1 cycle intel 83C152 HARDWARE DESCRIPTION The result is that in this particular case channel 0 has to wait until channel 1 completes its Burst mode DMA and then has to wait for an Instruction cycle to be gen erated before it can continue its own DMA to TFIFO The delay in servicing TFIFO can cause an Underflow condition in the GSC transmission The delay will not occur if channel 1 is configured to Alternate Cycles mode since channel 0 would then see the Instruction cycles it needs to complete its logic re quirements for asserting its request 4 4 1 DMA Arbitration with Hold Hold Ack The Hold Hold Acknowledge feature is invoked by set ting either the ARB or REQ bit in PCON Their effect is to add the requirements of the Hold Hold Ack pro tocol to mode logic This amounts to replacing ev ery expression return 1 in Figure 4 13 with the ex pression return hld hida logic where hld hida logic is a function which returns 1 if the Hold Hold Ack protocol is satisfied and returns 0 oth erwise A suitable definition for logic is shown in
451. tes testing and debugging of systems using the 5 without having to remove the device from the circuit The ONCE mode is invoked by either 1 Pulling ALE low while the device is in reset and PSEN is high 2 Holding ALE low as RESET is deactivated While the device is in ONCE mode the Port 0 pins go into a float state and the other port pins ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored after a valid reset is ap plied ADDITIONAL REFERENCES The following application notes provide supplemental information to this document and can be found in the Embedded Applications handbook Order No 270648 AP 125 Designing Microcontroller Systems for Electrically Noisy Environments 2 AP 155 Oscillators for Microcontrollers 3 AP 252 Designing with the 80C51BH 4 AP 410 Enhanced Serial Port on the 83C51FA Table 9 Lock Bits Lock Bits Protection Type B1 482 183 U U No program lock features enabled Code verify will still be encrypted by the encryption array if programmed MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset and further programming of the EPROM is disabled 3 P P U Sameas2alsovertyisdisabled ___ gt
452. the interrupt for RDN to determine when a frame is com pleted In DMA mode the interrupts are generated by the in ternal transmit receive done TDN RDN condi tions When the CPU responds to TDN or RDN checks are performed to see if the transmit underrun error has occurred The underrun condition is only checked when using the DMA channels Upon power up the CPU mode is initialized General DMA control is covered in Section 4 0 DMA control of the GSC is covered in Section 3 5 4 If DMA is to be used for serving the GSC it must be configured into the serial channel demand mode and the DMA bit in TSTAT has to be set 3 6 3 COLLISIONS AND BACKOFF The actions that are taken by the GSC if a collision Occurs while transmitting depend on where the colli sion occurs If a collision occurs in CSMA CD mode following the preamble and BOF flag the TCDT flag is set and the transmit hardware completes a jam When this type of collision occurs there will be no automatic retry at transmission After the jam control is returned to the CPU and user software must then initiate what ever actions are necessary for a proper recovery The possibility that data might have been loaded into or from the GSC deserves special consideration If these fragments of a message have been passed on to other devices user software may have to perform some exten sive error handling or notif cation Before starting a new message the transmit and receive FIFOs
453. the baud rate could probably be determined by the mi croprocessor just by monitoring the link it will make it much simpler if the baud rate is known in advance One of the first things that will be required during sys tem initialization is the assignment of unique addresses for each station In a two station only environment this is not necessary and can be ignored However keep in mind that all systems should be constructed for easy future expansions Therefore even in only a two station system addresses should be assigned There are three basic ways in which addresses can be assigned The first and most common is preassigned addresses that are loaded into the station by the user This could be done with a DIP switch through a keyboard The sec ond method of assigning addresses is to randomly as sign an address and then check for its uniqueness throughout the system and the third method is to make an inquiry to the system for the assignment of a unique address Once the method of address assignment is determined the method should become part of the specifications for the system to which all additions will have to adhere This then is the final assumption The negotiation process may not be clear for some readers The following two procedures are given as a guideline for dynamic address assignment In the first procedure a station assumes a random ad dress and then checks for its uniqueness throughout the system As a station
454. the condition REN 1 and R1 0 At S6P2 of the next machine cycle the RX Control unit writes the bits 11111110 to the receive shift register and in the next clock phase activates RE CEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shift ed to the left one position The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bits come in from the right 1s shift out to the left When the 0 that was initially loaded into the right most position arrives at the leftmost position in the shift register it flags the RX Control block to do one last Shift and load SBUF At SIP1 of the 10th machine cycle after the write to SCON that cleared RI RE CEIVE is cleared and RI is set More About Mode 1 Ten bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB SCON In the 8051 the baud rate is determined by the Timer 1 overflow rate In the 8052 it is deter mined either by the Timer 1 overflow rate or the Timer 2 overflow rate or both one for transmit and the other for receive Figure 18 shows a simplified functional diagram of the seria port in Mode
455. the end of a valid RESET are MYSLOT INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE 00H 0000H X0000000B 0XX00000B XX000000B 00H XXX00000B XX000000B 00000000B 0XXX0000B 00H OOH INDETERMINATE 000000008 INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE 00H 00H 07H INDETERMINATE 00H INDETERMINATE 00H 00H 00H 00H XX0001008 0000H intel The same conditions apply for both the 80C51BH and C152 for a correct reset pulse or power on reset ex cept that Reset is active low on the C152 Please refer to the 8051 52 Hardware Description Chapter of the Intel Embedded Controller Handbook for an explana tion on how to provide a proper power on reset Since Reset is active low on the C152 the resistor should be tied to VCC and the capacitor should be tied to VSS Because the clocking on part of the GSC circuitry is independent of the processor clock data may still be transmitted and DEN active for some time after reset is applied The transmission may continue for a maxi mum of four machine cycles after reset is first pulled low Although Reset has to be held low for only three machine cycles to be recognized by the GSC hardware all of the GSC circuitry may not be reset until four machine cycles have passed If it is important in the user application that all transmission
456. then the in struction ORL will leave the Accumulator holding the value 0D7H 11010111B When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be either a constant data value in the instruction or a variable computed in the Accumulator at run time The instruction ORL 1 00110010 will set bits 5 4 and of output Port 1 ORL Bytes 1 Cycles 1 encoding Operation ORL 2 61 intel ORL Bytes Cycles Encoding Operation ORL A Ri Bytes Cycles Encoding Operation ORL A data Bytes Cycles Encoding Operation ORL direct A Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 ORL V direct 1 1 ORL V Ri 2 1 ORL A A V data 2 1 ORL direct lt direct V A ORL direct data Bytes Cycles Encoding Operation 3 2 ORL direct direct V data 2 62 immediate data intel ORL C lt src bit gt Function Description Example ORL C bit Bytes Cycles Encoding Operation ORL C bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE
457. tion Modes Idle and Power Down Modes intel 8XC51FX HARDWARE DESCRIPTION 4 0 PORT STRUCTURES AND OPERATION All four ports in the C51FX are bidirectional Each consists of a latch Special Function Registers PO through P3 an output driver and an input buffer The output drivers of Ports 0 and 2 and the input buff ers of Port 0 are used in accesses to external memory In this application Port 0 outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the Port 2 pins continue to emit the P2 SFR content All the Port 1 and Port 3 pins are multifunctional They are not only port pins but also serve the functions of various special features as listed in Table 4 The alternate functions can only be activated if the cor responding bit latch in the port SFR contains a 1 Oth erwise the port pin is stuck at O 4 1 1 O Configurations Figure 2 shows a functional diagram of a typical bit latch and I O buffer in each of the four ports The bit latch one bit in the port s SFR is represented as a Type D flip flop which clocks in a value from the in ternal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the
458. to GSC interrupts and put the DMA control in alternate cycle mode DCONn 3 1 this enables the demand mode DCONnA 0 this clears the automatic increment option for the source address and DCONn 5 1 this defines the source as SFR The DMA channel servicing the receiver also needs its source address register to contain the address of RFIFO SARHN XXH SARLN channel servicing the transmitter the control register needs to be loaded as follows DCONn 2 0 DCONn 3 1 DCONn 6 0 this clears the automatic increment option for the destination address and DCONn 7 1 this sets the destination as SFR The channel serving the transmitter also requires that its destination address register contains the address of TFIFO DARHN XXH DARLN 85H Assuming that DCONO would be serving the receiver and the trans mitter DCONO would be loaded with 1010 0 and DCON 1 would be loaded with 10 10 The contents of SARHO and DARHI do not have any im pact when using internal SFRs as the source or destina tion When using the DMA channels to service the GSC the byte count registers will also need to be initialized The Done flag for the DMA channel servicing the re ceiver should be used if fixed packet lengths only are being transmitted or to insure that memory is not over written by long received data packets Overwriting of data can occur when using a smaller buffer than the pack
459. to incorporate future changes to the system are 1 Communication of the change to all the stations or the primary station 2 Maximum distance for communication This will af fect the drivers used and the slot time 3 More stations may be on the line at one time This may impact the interframe space or the collision resolu tion used 4 If using CSMA CD without deterministic resolu tion any increase in network size will have a negative impact on the average throughput of the network and lower the efficiency The user will have to give careful consideration when deciding how large a system can ultimately be and still maintain adequate performance 3 5 3 DMA SERVICING OF GSC CHANNELS There are two sources that can be used to control the GSC The first is CPU control and the second is DMA control CPU control is used when user software takes care of the tasks such as loading the TFIFO reading the RFI FO checking the status flags and general tracking of the transmission process the number of tasks grow and higher data transfer rates are used the overhead required by the CPU becomes the dominant consump tion of time Eventually a point is reached where the CPU is spending 100 of its time responding to the needs of the GSC An alternative is to have the DMA channels control the GSC A detailed explanation on the general use of the DMA channels is covered in Section 4 In this section only those details required for
460. to the MCS 51 Micro Assembler User s Guide Each register bank contains 8 one byte registers O through 7 Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is the first register RO of the second register bank Thus in order to use more than one register bank the SP should be intialized to a different location of the RAM where it is not used for data storage ie higher part of the RAM 2 Bit Addressable Area 16 bytes have been assigned for this segment 20H 2FH Each one of the 128 bits of this segment can be directly addressed 0 7FH The bits can be referred to in two ways both of which are acceptable by the ASM 51 One way is to refer to their addresses 0 7FH The other way is with reference to bytes 20H to Thus bits 0 7 can also be referred to as bits 20 0 20 7 and bits 8 FH are the same as 21 0 21 7 and so on Each of the 16 bytes in this segment can also be addressed as a byte 3 Scratch Pad Area Bytes 30H through 7FH are available to the user as data RAM However if the stack pointer has been initialized to this area enough number of bytes should be left aside to prevent SP data destruction 2 6 intel 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Figure 4 shows the different segments of the on chip RAM 270249 5 Figure 4 128 Bytes of RAM Direct and Indirect Addressable intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET
461. transmit FIFO The transmit FIFO is a three byte buff er that loads the transmit shift register with data The status of this flag is controlled by the GSC TSTAT 3 TDN Transmit Done When set indi cates the successful completion of a frame transmission If HABEN is set TDN will not be set until the end of the IFS following the transmitted message so that the acknowledge can be checked If an acknowledge is ex pected and not received TDN is not set An acknowl edge is not expected following a broadcast or multi cast packet The status of this flag is controlled by the GSC TSTAT 4 TCDT Transmit Collision Detect If set indicates that the transmitter halted due to a collision It is set if a collision occurs during the data or CRC or if there are more than eight collisions The status of this flag is controlled by the GSC TSTAT 5 UR Underrun If set indicates that in DMA mode the last bit was shifted out of the transmit register and that the byte count did not equal zero When an underrun occurs the transmitter halts without sending the CRC or the end flag The status of this flag is controlled by the GSC TSTAT 6 NOACK No Acknowledge If set indi cates that no acknowledge was received for the previous frame Will be set only if HABEN is set and no ac knowledge is received prior to the end of the IFS NOACK is not set following broadcast or a multi cast packet The status of this flag is controlle
462. tructions which execute a jump if the ad dressed bit is set JC JB JBC or if the addressed bit is not set JNC JNB In the above case bit2 is being tested and if bit2 0 the CPL C instruction is jumped over JBC executes the jump if the addressed bit is set and also clears the bit Thus a flag can be tested and cleared in one operation the PSW bits are directly addressable so the Parity bit or the general purpose flags for example are also available to the bit test instructions RELATIVE OFFSET The destination address for these jumps is specified to the assembler by a label or by an actual address in Program Memory However the destination address assembles to a relative offset byte This is a signed two s complement offset byte which is added to the PC in two s complement arithmetic if the jump is exe cuted The range of the jump is therefore 128 to 127 gram Memory bytes relative to the first byte following the instruction MCS 51 ARCHITECTURAL OVERVIEW Jump Instructions Table 8 shows the list of unconditional jumps Table 8 Unconditional Jumps in MCS 51 Devices add JMP A DPTR Jump to CALL addr Call subroutine ataddr 2 RET Rewntomssrwwne 2 moe Nooperation 1 The Table lists a single JMP addr instruction but in fact there are three SJMP LJMP and AJMP which differ in the format of the destination address J
463. ts The other way of terminating the Idle mode is with a hardware reset Since the clock oscillator is still run ning the hardware reset needs to be held active for only two machine cycles 24 oscillator periods to complete the reset The signal at the RESET pin clears the IDL bit directly and asynchronously At this time the CPU resumes program execution from where it left off that is at the instruction following the one that invoked the Idle Mode As shown in the Reset Timing diagram two or three machine cycles of program execution may take place before the internal reset algorithm takes control On chip hardware inhibits access to the internal RAM during this time but access to the port pins is not inhib ited To eliminate the possibility of unexpected outputs at the port pins the instruction following the one that invokes Idle should not be one that writes to a port pin or to external Data RAM 6 51 87C51GB HARDWARE DESCRIPTION 14 2 Power Down Mode An instruction that sets the PD bit causes that to be the last instruction executed before going into the Power Down mode In this mode the on chip oscillator is stopped With the clock frozen all functions are stopped but the on chip RAM and Special Function Registers are held The port pins output the values held by their respective SFRs and ALE and PSEN output lows In Power Down can be reduced to as low as 2V Care must be taken however to ensure that is
464. ts 16 bit auto reload mode This feature TRANSITION 12 1 eit Capture X Baud Rate Generator E __ x OH k is invoked by a bit named DCEN Down Counter En able located in the SFR T2MOD see Table 5 Upon reset the DCEN bit is set to O so that Timer 2 will default to count up When DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin Figure 2 shows Timer 2 automatically counting up when DCEN 0 In this mode there are two options selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 counts up to OFFFFH and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16 bit value in RCAP2H and RCAP2L The values in RCAP2H and RCAP2L are preset by software If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 1 10 0 transition at external input T2EX This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can generate an interrupt if enabled TIMER 2 INTERRUPT 270783 1 Figure 1 Timer 2 in Capture Mode intel 8XC52 54 58 HARDWARE DESCRIPTION Table 5 T2MOD Timer 2 Mode Control Register T2MOD Address Reset Value XXXX XX00B Not Bit Addressable L2 ss n po cc e 7 6 5 4 3 2 1 0 Symbol Function Not implemented reserved for future use T20E Timer 2 Output Enable bit Whe
465. ugh FFFFH are directed to external ROM In the 8K byte ROM devices Vcc selects ad dresses 0000H through to be internal and ad dresses 2000H through FFFFH to be external In the 16K byte ROM devices EA selects ad dresses OOOOH through 3FFFH to be internal and ad dresses 4000H through FFFFH to be external If the EA pin is strapped to Vss then all program fetches are directed to external ROM The ROMless parts must have this pin externally strapped to Vss to enable them to execute properly The read strobe to external ROM PSEN is used for all external program fetches PSEN is not activated for in ternal program fetches 270251 4 Figure 4 Executing from External Program Memory The hardware configuration for external program exe cution is shown in Figure 4 Note that 16 I O lines Ports O and 2 are dedicated to bus functions during external Program Memory fetches Port 0 PO in Figure 4 serves as a multiplexed address data bus It emits the low byte of the Program Counter PCL as an ad dress and then goes into a float state awaiting the arriv of the code byte from the Program Memory During the time that the low byte of the Program Counter is valid on PO the signal ALE Address Latch Enabie clocks this byte into an address latch Meanwhile Port 2 P2 in Figure 4 emits the high byte of the Program Counter PCH Then PSEN strobes the EPROM and the code byte is read into the microc
466. ulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low order Digit indirect RAM with Acc Oscillator Mnemonic CLR C CLR bit SETB SETB bit CPL C CPL bit ANL C bit ANL C bit ORL C bit ORL C bit MOV J8 bit rel JNB bit rel JBC bit rel ACALL addrii LCALL 16 RET RETI AJMP 1 LJMP addr16 SJMP rel 2 23 Oscillator Description Byte BOOLEAN VARIABLE MANIPULATION Clear Carry Clear direct bit Set Carry Set direct bit Complement direct bit AND direct bit to CARRY AND complement of direct bit to Carry OR direct bit to Carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry not set Jump if direct Bit is set Jump if direct Bit is Not set Jump if direct Bit is set amp clear bit PROGRAM BRANCHING Absolute Subroutine Call Long Subroutine Call Return from Subroutine Return from interrupt Absolute Jump Long Jump Short Jump relative addr All mnemonics copyrighted Intel Corporation 1980 intel PROGRAM BRANCHING Continued JMP JZ Mnemonic A DPTR A direct rel A data rel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 10 8051 Instruction Set Summary Continued Oscillator Peri
467. umber assignment The TCDCNT register operates by shifting the contents one bit position to the left as each collision is detected As each shift occurs a 1 is loaded into the LSB When TCDCNT overflows GSC operation stops and the CPU is notified by the setting of the TCDT bit which can flag an interrupt The amount of time that the GSC has before it must be ready to retransmit after a collision is determined by the mode which is selected The mode is determined GMOD 5 and GMOD 6 If MO and equal 0 0 normal backoff then the minimum period before retransmission will be either the interframe space or the backoff period whichever is longer If MO and M1 equal 1 1 alternate backoff then the minimum period before retransmission will be the interframe space plus the backoff period Both of these are shown in Figure 3 4 Alternate backoff must be enabled if us ing deterministic resolution If the GSC is not ready to retransmit by the time its assigned slot becomes avail able the slot time is lost and the station must wait until the collision resolution time period has passed Instead of waiting for the collision resolution to pass the transmission could be aborted The decision to abort is usually dependent on the number of stations on the link and how many collisions have already oc curred The number of collisions can be obtained by examining the register TCDCNT The abort is normal ly implemented by clearing TEN The
468. umulator leaving the result in the Accumula tor The carry and auxiliary carry flags are set respectively if there is a carry out from bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occured OV 15 set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number pro duced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or imme diate The Accumulator holds 0C3H 11000011B and register 0 holds 10101010B The instruction ADD A R0 will leave 6DH 01101101B in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1 1 1 52191111 ADD lt Rn 2 1 0010 lt direct direct address 2 29 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ADD A Ri Bytes 1 Cycles 1 Operation ADD A RD ADD A data Bytes 2 Cycles 1 Encoding 0010 0100 Operation ADD data ADDC A lt sre byte gt Function Add with Carry Description ADDC simultaneously adds the byte variable indicated the carry flag and the Accumulator contents leaving the result in the Accumulator The carry
469. unction the register is incremented in response to a 1 10 0 transition at its corresponding external input pin TO T1 or in the 8052 T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incre mented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes 2 machine cycles 24 oscillator periods to recognize a 1 to O transition the maximum count rate is 1 4 of the oscillator fre quency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle In addition to the Timer or Counter selection Timer 0 and Timer 1 have four operating modes from which to select Timer 2 in the 8052 has three modes of operation Capture Auto Reload and baud rate generator Timer 0 and Timer 1 These Timer Counters are present in both the 8051 and the 8052 The Timer or Counter function is select ed by control bits C T in the Special Function Register TMOD Figure 6 These two Timer Counters have MSB cate w four operating modes which are selected by bit pairs M1 MO in TMOD Modes 0 1 and 2 are the same for both Timer
470. upt request and the be ginning of execution of the first instruction of the serv ice routine Figure 24 shows interrupt response timings A longer response time would result if the request is blocked by one of the 3 previously listed conditions If an interrupt of equal or higher priority level is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 HARDWARE DESCRIPTION OF THE 8051 8052 80 51 intel cycles long and if the instruction in progress is RETI or an access to IE or IP the additional wait time can not be more than 5 cycles a maximum of one more to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is DIV Thus in a single interrupt system the response time is always more than 3 cycles and less than 9 cycles SINGLE STEP OPERATION The 8051 interrupt structure allows single step execu tion with very little software overhead As previously noted an interrupt request will not be responded to while an interrupt of equal priority level is still in prog 55 nor will it be responded to after until at least one other instruction has been executed Thus once an interrupt routine has been entered
471. ur programmable modes four selectable frequencies Hardware Watchdog Timer Reset asynchronous active low Oscillator Fail Detection Interrupt Structure with 15 interrupt sources Four priority levels Power Saving Modes Idle Mode Power Down Mode The table below summarizes the product names of the various 8XC51GB products currently available Throughout this document the products will generally be referred to as the 8XC51GB Figure 1 shows func tional block diagram of the 8XC51GB ROM OTP Device Version Bytes 8705188 8705108 8005168 256 2 0 MEMORY ORGANIZATION All MCS 51 devices have a separate address space for Program Memory and Data Memory The logical sepa ration of Program and Data Memory allows the Data Memory to be accessed by 8 bit addresses which can be more quickly stored and manipulated by an 8 bit CPU Nevertheless 16 bit Data Memory addresses can also be generated through the DPTR register Up to 64 Kbytes each of external Program and Data Memory can be addressed Version 2 1 Program Memory Program Memory can only be read not written to There can be up to 64 Kbytes of Program Memory The read strobe for external Program Memory is the signal PSEN Program Store Enable is not acti vated for internal program fetches If the EA External Access pin is connected to Vss all program fetches are directed to external memory Fo
472. us in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read a port acti vate the read latch signal and others activate the read pin signal More about that later As shown in Figure 4 the output drivers of Ports 0 and 2 are switchable to an internal ADDR and ADDR DATA bus by an internal CONTROL signal for use in external memory accesses During external memory ac cesses the P2 SFR remains unchanged but the PO SFR gets 1s written to it Also shown in Figure 4 is that if a P3 bit latch contains a 1 then the output level is controlled by the signal labeled alternate output function The actual P3 X pin level is always available to the pin s alternate input function if any Ports 1 2 and 3 have internal pullups Port 0 has open drain outputs Each I O line can be independently used as an input or an output Ports 0 and 2 may not be used as general purpose when being used as the ADDR DATA BUS To be used as an input the port bit latch must contain a 1 which turns off the output driver FET Then for Ports 1 2 and 3 the pin is pulled high by the internal pullup but can be pulled low by an external source Port 0 differs in not having internal pullups The pullup FET in the PO output driver see Figure 4 is used only when the Port is emitting 1s during externa
473. ust be set separately to turn the Timer on As a Timer Tabie 7 INTERNAL EXTERNAL CONTROL CONTROL NOTE 1 NOTE 2 16 bit Auto Reload 16 bit Capture BAUD rate generator receive amp transmit same baud rate receive only transmit only As a Counter Table 8 INTERNAL EXTERNAL CONTROL CONTROL NOTE 1 NOTE 2 16 bit Auto Reload 02H OAH 16 bit Capture 03H 5 1 Capture Reload occurs only Timer Counter overflow 2 Capture Reload occurs on Timer Counter overflow and 1 to 0 transition on 2 P1 1 pin except when Timer 2 is used in the baud rate generating mode 2 18 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SCON SERIAL PORT CONTROL REGISTER BIT ADDRESSABLE sm sm2 ren mae m m SMO SCON 7 Serial Port mode specifier NOTE 1 SM1 SCON 6 Serial Port mode specifier NOTE 1 SM2 SCON 5 Enables the multiprocessor communication feature in modes 2 amp 3 In mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 See Table 9 SCON 4 Set Cleared by software to Enable Disable reception TB8 SCON 3 The 9th bit that will be transmitted in modes 2 amp 3 Set Cleared by software RB8 2 In modes 2 amp 3 is the 9th data bit that was received In mode
474. ut pin Operating Mode 8 bit Timer Counter THx with TLx as 5 bit prescaler 16 bit Timer Counter and TLx are cascaded there is no prescaler 8 bit auto reload Timer Counter THx holds a value which is to be reloaded into TLx each time it overfiows Timer 0 TLO is 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is 8 bit timer only controlled by Timer 1 control bits Timer 1 Timer Counter stopped MODE 0 As the count rolls over from all 1s to all Os it sets the timer interrupt flag TFO or TF1 The counted input is Either Timer 0 or Timer 1 in Mode O is an 8 bit counter enabled to the timer when TRO or TR1 1 and either with a divide by 32 prescaler In this mode the Timer GATEx 0 or INTx pin 1 Setting GATEx 1 register is configured as a 13 bit register Figure 8 allows the Timer to be controlled by external input shows the Mode 0 operation for either timer INTx pin to facilitate pulse width measurements INTERRUPT CONTROL OVERFLOW 270897 10 Figure 8 Timer Counter 0 1 in Mode 0 13 Bit Counter 6 14 intel 87C51GB HARDWARE DESCRIPTION TRx and TFx are control bits in the SFR TCON The GATEx bits are in TMOD There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 The 13 bit register consists of all 8 bits of THx and the lower 5 bits of TLx The upper 3 bits of TLx are inde terminate and shou
475. value at the time a transition was detected on the The time it takes to service this interrupt routine deter CEXn pin mines the resolution of back to back events with the same PCA module To store two 8 bit registers and Upon a capture the module s event flag CCFn in clear the event flags takes at least 9 machine cycles CCON is set and an interrupt is flagged if the ECCFn That includes the call to the interrupt routine At bit in the mode register CCAPMn is set The in 12 MHz this routine would take less than 10 How terrupt will then be generated if it is enabled Since the ever depending on the frequency and interrupt latency hardware does not clear an event flag when the inter the resolution will vary with each application rupt is vectored to the flag must be cleared in software 6 28 intel 7 4 Software Timer Mode In most applications a software timer is used to trigger interrupt routines which must occur at periodic inter vals The user preloads a 16 bit value in a module s compare registers When a match occurs between this compare value and the PCA timer value an event flag is set and an interrupt can then be generated In the compare mode the 16 bit value of the timer is compared with a 16 bit value pre loaded in the module s compare registers CCAPnH CCAPnL as seen in Figure 20 The comparison occurs three times per machine cycle in order to recognize the fastest pos sible clock input
476. verride the alternate cycles of channel 1 If TFIFO needs more than 1 byte it will receive them in precendence over channel 1 but each DMA to TFIFO must be preceded by an Instruction cycle The sequence of cycles might be cycle Instruction cycle 1 cycle during which gets set Instruction cycle DMAO cycle Instruction cycle cycle as a result of which gets cleared Instruction cycle cycle Instruction cycle cycle Instruction cycle 7 58 The requirement that TFIFO be preceded by an Instruction cycle can result in the normal prece dence of channel 0 over channel 1 being thwarted Con sider for example the situation where channel 0 is con figured to service TFIFO and is in the process of doing so and channel 1 decides it wants to do a Burst mode DMA The sequence of events might be Instruction cycle sets GO bit in DCON1 Instruction cycle during which gets set DMAO cycle cycle DMA cycle DMA cycle DMAI cycle completes channel 1 burst Instruction cycle cycle Instruction cycle This sequence begins with two Instruction cycles The first one accesses DMA register 1 and there fore is followed by another Instruction cycle which presumably does not access DMA register After the second Instruction cycle both channels are ready to generate DMA cycles and channel 0 of course takes precedence Af
477. wer byte of the destina tions address when performing DMA transfers DARHO 1 0D3H Destination Address Reg ister Low 0 1 Contains the upper byte of the destina tions address when performing DMA transfers 7 64 83C152 HARDWARE DESCRIPTION DAS Destination Address Space see DCON DCJ D C Jam see MYSLOT DCONO 1 092H 093H 7 6 5 4 3 2 1 0 Das sas isa DONE The DCON registers control the operation of the channels by determining the source of data to be trans ferred the destination of the data to be transfer and the various modes of operation DCON 0 GO Enables DMA Transfer When set it enables channel If block mode is set then DMA transfer starts as soon as possible under CPU control If demand mode is set then DMA transfer starts when a demand is asserted and recognized DCON 1 DONE DMA Transfer is Complete When set the DMA transfer is complete It is set when BCR equals 0 and is automatically reset when the DMA vectors to its interrupt routine If DMA inter rupt is disabled and the user software executes a jump on the DONE bit then the user software must also reset the done bit If DONE is not set then the DMA transfer is not complete DCON 2 TM Transfer Mode When set DMA burst transfers are used if the DMA channel is config ured in block mode or external interrupts are used to initiate a transfer if in Demand Mode When TM is cle
478. whenever control bit is set Timer or Counter Selector cleared for Timer operation input from internal system clock Set for Counter operation input from Tx input Operating Mode Timer Counter THx with TLx as 5 bit prescaler 16 bit Timer Counter and TLx cascaded there is 8 bit auto reload Timer Counter holds value which is to be reloaded into each time it overflows Timer 0 TLO is an 8 bit Timer Counter controlled by the standard Timer 0 contro bits THO is an 8 bit timer only controlled by Timer 1 control bits Timer 1 Timer Counter 1 stopped Figure 6 TMOD Timer Counter Mode Control Register 3 10 HARDWARE DESCRIPTION OF THE 8051 8052 80 51 INTERRUPT CONTROL 270252 9 Figure 7 Timer Counter 1 Mode 0 13 Bit Counter MSB LSB rer Tm m Name and Significance Timer 1 overflow Flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine Timer 1 Run control bit Set cleared by software to tum Timer Counter on otf Timer 0 overflow Flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine Timer 0 Run control bit Set cleared by software to turn Timer Counter on off Symbol Position Name and Significance Interrupt 1 Edge
479. will be discussed in the next section flow to generate the PCA interrupt In addition the user has the option of turning off the PCA timer during Idle Mode by setting the Counter Idle bit CIDL The Watchdog Timer Enable bit WDTE will be discussed in a later section Table 10 CMOD PCA Counter Mode Register CMOD Address 0D9H Reset Value 00 X000B Not Bit Addressable om wore T ceso amp 7 6 5 4 3 2 1 0 Function Bit Counter Idle control CIDL 0 programs the PCA Counter to continue functioning during Mode CIDL 1 programs it to be gated off during idle Watchdog Timer Enable WDTE 0 disables Watchdog Timer function Module 4 WDTE 1 enables it Not implemented reserved for future use PCA Count Pulse Select bit 1 Count Pulse Select bit 0 CPS1 50 Selected Input 0 0 Internal clock Fosc 12 0 1 Internal clock Fosc 4 1 0 Timer 0 overflow 1 1 External clock at ECI P1 2 pin max rate Fosc 8 ECF PCA Enable Counter Overflow interrupt ECF 1 enables CF bit in CCON to generate an interrupt ECF 0 disables that function of CF NOTE User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate Fosc
480. with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle If the interrupt flag for a level sensitive external interrupt is active but not being responded to for one of the above conditions and is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every poll ing cycle is new The polling cycle LCALL sequence is illustrated in Figure 25 Note that if an interrupt of a higher priority level goes active prior to 55 2 of the machine cycle labeled in Figure 25 then in accordance with the above rules it will be vectored to during C5 and C6 without any in struction of the lower priority routine having been exe cuted Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the ap propriate servicing routine The hardware generated LCALL pushes the contents of the Program Counter onto the stack but it does not save the PSW and re loads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 22 INTERRUPTS ARE POLLED INTERRUPT INTERRUPT sors ACTIVE LATCHED Table 22 Interrupt Vector Address Interrupt Interrupt Cleared by Vector Source T Hardware Address No level Yes trans TIMER 0 Yes
481. write may not be accurate The RCAP2 registers may be read but shouldn t be written to because a write might overlap reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 registers Table 18 Timer 2 Generated Baud Rates Baud Rate RCAP2H RCAP2L 9 0 SERIAL EXPANSION PORT The Serial Expansion Port SEP allows a wide variety of serially hosted peripherals to be connected to the 8XC51GB The SEP has four programmable modes and four clock options There is a single bi directional data pin P4 1 and a clock output pin P4 0 Data transfers consist of 8 clocks with 8 bits of data received or transmitted When not transmitting or receiving the data and clock pins are inactive There are 3 SFRs asso ciated with the SEP as shown in Figure 30 LSB SEPSO SEPCON 0D7H CLKPH SEPS1 LSB CSB SEPDAT 0E7H LSB SEPFWR SEPFRD SEPIF SEPSTAT OF7H Figure 30 SEP SFRs intel None of the SEP SFRs are bit addressable However the individual bits of SEPSTAT and SEPCON are sig nificant and have symbolic names associated with them as shown The meaning of these bits are SEP Enable bit SEPREN SEP Receive ENable CLKPOL POLarity CLKPH CLocK PHase SEPSI SEP Speed select 1 SEP Speed select 0 SEPFWR SEP Fault during WRite SEPFRD SEP Fault during ReaD SEPIF SEP I
482. x x x O O x x x O x x x x x x gt x O SETBC D Note that operations on SFR byte address 208 or bit addresses 209 215 the PSW or bits in the PSW will also affect flag settings Note on instruction set and addressing modes Rn Register R7 RO of the currently se lected Register Bank direct 8 bit internal data location s address This could be an Internal Data RAM location 0 127 a SFR i e I O port control register status register etc 128 255 Ri 8 bit internal data RAM location 0 255 addressed indirectly through reg ister R1 or RO data 8 bit constant included in instruction data 16 16 bit constant included in instruction addr 16 16 bit destination address Used by LCALL amp LJMP A branch be anywhere within the 64K byte Pro gram Memory address space 11 bit destination address Used by ACALL amp AJMP The branch will be within the same 2K byte page of pro gram memory as the first byte of the following instruction Signed two s complement 8 bit offset byte Used by SJMP and all condition jumps Range 128 to 127 bytes relative to first byte of the fol lowing instruction Direct Addressed bit in Internal Data RAM or Special Function Register 2 21 intel ARITHMETIC OPERATIONS Continued INC MUL DIV DA LOGICAL OPERATIONS ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL
483. ximum input frequency in this mode is oscillator frequency 8 The mode register CMOD Table 12 contains the Count Pulse Select bits CPS1 and CPSO to specify the clock input This register also contains the ECF bit which enables the PCA counter overflow to generate the PCA interrupt In addition the user has the option of turning off the PCA timer during Idle Mode by set ting the Counter Idle bit This can further re duce power consumption by an additional 30 every 250 ns The CCON Table 13 register contains two more bits which are associated with the PCA timer counter The CF bit gets set by hardware when the counter over flows and the CR bit is set or cleared to turn the coun ter on or off Timer 0 overflows The timer increments whenever Timer O over flows This mode allows a programmable input fre quency to the PCA Table 12 CMOD PCA Counter Mode Register CMOD Address OD9H Reset Value 00 000 Not Bit Addressable wore ces 7 6 5 4 3 2 1 0 Symbol Function CIDL Bit Counter Idle control CIDL 0 programs the Counter to continue functioning during idle Mode CIDL 1 prograrns it to be gated off during idle Watchdog Timer Enable WDTE 0 disables Watchdog Timer function on PCA Module 4 WDTE 1 enables it WDTE Not implemented reserved for future use PCA Count Pulse Select bit 1 PCA Count Pulse Select bit
484. xternal memory When the CPU is executing out of external Program Memory all 8 bits of Port 2 are dedicated to an output 6 13 function and may not be used for general purpose I O During external program fetches they output the high byte of the PC with the Port 2 drivers using the strong pullups to emit bits that are 1s 5 0 TIMER COUNTERS The 8XC51GB has three 16 bit Timer Counters Tim er 0 Timer 1 and Timer 2 Each consists of two 8 bit registers THx and TLx with x 0 1 or 2 All three can be configured to operate either as timers or event counters In the Timer function the TLx register is incremented every machine cycle Thus you can think of it as count ing machine cycles Since a machine cycle consists of 12 oscillator periods the count rate is 1 12 of the oscillator frequency In the Counter function the register is incremented in response to a 1 10 0 transition at its corresponding ex ternal input pin TO Ti or T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes 2 machine cycles 24 oscillator periods to recognize a 1 10 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of
485. y an open collector output 0 to 1 transition will have to be driven by the relatively weak depletion mode FET in Figure 5 A In the CHMOS device an input O turns off pullup pFET3 leaving only the very weak pullup to drive the transition In external bus mode Port 0 output buffers can each drive 8 LS TTL inputs As port pins they require exter nal pullups to drive any inputs intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 Read Modify Write Feature Some instructions that read a port read the latch and others read the pin Which ones do which The instruc tions that read the latch rather than the pin are the ones that read a value possibly change it and then rewrite it to the latch These are called read modify write in structions The instructions listed below are read mod ify write instructions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL logical AND e g ANL ORL logical OR e g ORL P2 XRL logical EX OR e g XRL P3 A JBC jump if bit 1 and clear bit e g JBC 1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 DJNZ decrement and jump if not zero e g DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of Port X CLR PX Y clear bit Y of Port X SETBPX Y set bit Y of Port X It is not obvious that the last three instru
486. y setting the TEN bit TSTAT 1 and then writing to TFIFO TEN must be set before load ing the transmit FIFO as setting TEN clears the trans mit FIFO TCDCNT should also be checked by user software and cleared if a collision occurred on a prior transmission To enable the receiver GREN RSTAT 1 is set After GREN is set the GSC begins to look for a valid BOF After detecting a valid BOF the GSC attempts to match the received address byte s against the address match registers When a match occurs the frame is loaded into the GSC Due to the CRC strip hardware there is a 40 or 24 bit time delay following the BOF until the first data byte is loaded into RFIFO if the 32 or 16 bit CRC is chosen If the end of frame is detected before data is loaded into the receive FIFO the receiver ignores that frame 7 42 If the receiver detects a collision during reception in CSMA CD mode and if any bytes have been loaded into the receive FIFO the RCABT flag is set The GSC hardware then halts reception and resets GREN The user Software needs to filter any collision fragment data which may have been received If the collision occurred prior to the data being loaded into RFIFO the CPU is not notified and the receiver is left enabled At the end of a reception the RDN bit is set and GREN is cleared In HABEN mode this causes an acknowledgement to be transmitted if the frame did not have a broadcast or multi cast address The user software can enable
487. y software NOTE SMODO is located at Fosc oscillator frequency The SADEN byte are selected such that each slave can be addressed separately Notice that bit 1 LSB is a don t care for Slave 1 Given Address but bit 1 1 for Slave 2 Thus to selectively communicate with just Slave 1 the master must send an address with bit 1 O e g 1111 0000 Similarly bit 2 0 for Slave 1 but is a don t care for Slave 2 Now to communicate with just Slave 2 an ad dress with bit 2 1 must be used e g 1111 0111 Finally for a master to communicate with both slaves at once the address must have bit 1 1 and bit 2 0 5 29 Notice however that bit 3 is a don t care for both slaves This allows two different addresses to select both slaves 1111 0001 or 1111 0101 If a third slave was added that required its bit 3 0 then the latter address could be used to communicate with Slave 1 and 2 but not Slave 3 The master can also communicate with all slaves at once with the Broadcast Address It is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t cares The don t cares also allow intel flexibility in defining the Broadcast Address but in most applications a Broadcast Address will be SADDR and SADEN are located at address A9H and B9H respectively On reset the SADDR and SADEN registers are initialized to which defines the Given and Broadcast Add

MCS® 51 Microcontroller Family User`s Manual

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MCS&reg; 51 Microcontroller Family User`s Manual

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MCS® 51 Microcontroller Family User`s Manual