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1. 33301 LOW OC 2 3 302 HIGH LOC ONE 2 3 31 TRANSMIT CHARACTER COUNT REGISTER TCCR 23311 Low LOC 0xN3C 23312 HIGH LOC OXN3D 2332 TIME CONSTANT REGISTER TCIR ENE E sete 23321 fo 200 OLD DE 23322 HIGH LOC OIE E CHAPTER 3 PCI INTERFACE vessssssssssssssosssssssssscscssssssssssessssssunssssssnsonsscscesescscssssesesesusususssnsensnsssesesescasasaeesesesessnsanusssnsansnesenseee 34 30 PCLINTERFACE REOISTERS ttt ttt 3 1 PCI CONFIGURATION REGISTERS TABLE 3 1 1 PCI CONFIGURATION REGISTERS 311 PCI CONFIGURATION ID REGISTER OFFSET 0X00 RESET 0 908010 5 3 12 PCI 35 313 PCI STATUS REGISTER OFFSET 0X06 RESET 0 0280 35 314 PCI REVISION ID REGISTER OFFSET NO 36 3 1 5 PCI CLASS CODE REGISTER OFFSET 0X09 0B RESET 0X068000 236 316 PCI CACHE LINE SIZE REGISTER OFFSET RESET 0X00 36 317 PCI LATENCY TIMER REGISTER OFFSET RESET 0X00 2 36 3 1 8 PCI HEADER TYPE REGISTER OFFSET RESET OO 36 3 1 9 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL RUNTIME DMA REGISTERS OFFSET 0 010 RESET OXOO0000000 TRA 36 3 1 10 PCI BASE ADDRESS REGISTER FOR I O ACCESS TO LOCAL RUNTIME DMA REGISTERS OFFSET 0X14 RESET 0X00000001 n nn
2. PCI interface is compliant with the 5V 33MHz PCI Specification 2 1 The PCI9080 provides dual DMA controllers for fast data transfers to and from the on board FIFOs Fast DMA burst accesses provide for a maximum burst throughput of 132MB s to the PCI interface To reduce CPU overhead during DMA transfers the controller also implements Chained Scatter Gather DMA as well as Demand Mode DMA Since many features of the PCI9080 are not utilized in this design it is beyond the scope of this document to duplicate the PCI9080 User s Manual Only those features which will clarify areas specific to the PCI PMC HPDI32 are detailed here Please refer to the PCI9080 User s Manual See Related Publications for more detailed information Note that the BIOS configuration and software driver will handle most of the PCI9080 interface Unless the user is writing a device driver the details of the PCI interface Chapter 2 may be skipped 31 CONFIGURATION REGISTERS The PCI device configuration for the PCI PMC HPDI322 is fully PCI 2 1 compliant Table 3 1 1 contains a list of the PCI configuration registers present in the PCI9080 An on board configuration serial EEPROM initializes many of these registers TABLE 3 1 1 PCI CONFIGURATION REGISTERS Local Offset PCI Local Register Name Value after Addr Writable Reset Device ID Vendor ID 0x908010B5 Y Status Command 0 02800017 Class Code Revision ID 0x0680003 0x0C 15 0 BIST Unused
3. DMA Clear Count Mode Unused DMA Channel 0 Interrupt Select A routes the DMA Channel 0 interrupt to the PCI interrupt Note This bit should always be set to 1 D31 18 Reserved 3 4 2 DMA CHANNEL 0 PCI ADDRESS REGISTER PCI 0x84 D31 0 PCI Address Register 3 4 5 DMA CHANNEL 0 LOCAL ADDRESS REGISTER PCI 0x88 D31 0 Local Address Register Note Should be set to Local FIFO offset 0x18 3 4 4 DMA CHANNEL 0 TRANSFER SIZE BYTES REGISTER PCI 0x8C D22 0 DMA Transfer Size D31 23 Reserved 3 4 5 CHANNEL 0 DESCRIPTOR POINTER REGISTER PCI 0x90 3 5 DO Descriptor Location A indicates PCI address space Note This bit should always be set to 1 if Chained DMA enabled DI End of Chain D2 Interrupt after Terminal Count D3 Direction of transfer A indicates transfers from local bus to PCI bus Read Receive FIFO A 0 indicates transfers from local bus to PCI bus Write Transmit FIFO D31 4 Next Descriptor Address 3 4 6 DMACHANNEL 0 COMMAND STATUS REGISTER PCI 0 8 DO Channel 0 Enable D1 Channel 0 Control D2 Channel 0 Abort D3 Clear Interrupt D4 Channel 0 Done D7 5 Reserved 3 4 7 DMAARBITRATION REGISTER PCI 0XAC Same as Mode Arbitration Register MARBR PCI 0x08 See Section 2 2 2 3 48 THRESHOLD REGISTER PCI 0XB0 D3 0 DMA Channel 0 PCI to Local Almost Full COPLAF 07 4 Channel 0 Local to PCI Almost Empty COLPAE D11 8 MA C
4. indicates PCI9080 has signaled a target abort Writing a 1 to this bit clears the bit D12 Received Target Abort A indicates PCI9080 has received a target abort Writing a 1 to this bit clears the bit D13 Master Abort A indicates the PCI9080 has generated a master abort signal Writing a 1 to this bit clears the bit D14 Signal System Error indicates the PCI9080 has reported a system error on the SERR signal Writing a 1 to this bit clears the bit 015 Detected Parity Error A indicates the PCI9080 has detected a PCI bus parity error even if parity error handling is disabled the Parity Error Response bit in the Command Register is clear One of three conditions can cause this bit to be set 1 PCI9080 detected a parity error during a PCI address phase 2 PCI9080 detected a data parity error when it was the target of a write 3 PCI9080 detected a data parity error when performing a master read Writing a 1 to this bit clears the bit 3 1 4 PCI REVISION ID REGISTER OFFSET 0X08 D7 0 Revision ID The silicon revision of the PCI9080 3 1 5 PCI CLASS CODE REGISTER OFFSET 0X09 0B RESET 0X068000 D7 0 Register level programming interface 0x00 Queue Ports at 0x40 and 0x44 0x01 Queue Ports at 0x40 and Ox44 Int Status and Int Mask at 0x30 and 0x34 D15 8 Sub class Code 0x80 Other bridge device D23 16 Base Class Code 0x06 Bridge Device 3 1 6 PCI
5. 100 010 110 001 101 011 111 D3 D4 6 654 000 100 010 110 001 101 011 Demand Mode DMA Channel 0 Request Encoder Request DMA on Serial Channel 1 Rx FIFO Almost Full Hold until Serial Channel 1 Rx FIFO Almost Empty Request DMA on Serial Channel 1 Tx FIFO Almost Empty Hold until Serial Channel 1 Tx FIFO Almost Full Request DMA on Serial Channel 2 Rx FIFO Almost Full Hold until Serial Channel 2 Rx FIFO Almost Empty Request DMA on Serial Channel 2 Tx FIFO Almost Empty Hold until Serial Channel 2 Tx FIFO Almost Full Request DMA on Serial Channel 3 Rx FIFO Almost Full Hold until Serial Channel 3 Rx FIFO Almost Empty Request DMA on Serial Channel 3 Tx FIFO Almost Empty Hold until Serial Channel 3 Rx FIFO Almost Empty Request DMA on Serial Channel 4 Rx FIFO Almost Full Hold until Serial Channel 4 Rx FIFO Almost Empty Request DMA on Serial Channel 4 Tx FIFO Almost Empty Hold until Serial Channel 4 Rx FIFO Almost Empty Reserved Demand Mode DMA Channel Request Encoder Request DMA on Serial Channel 1 Rx FIFO Almost Full Hold until Serial Channel 1 Rx FIFO Almost Empty Request DMA on Serial Channel 1 Tx FIFO Almost Empty Hold until Serial Channel 1 Tx FIFO Almost Full Request DMA on Serial Channel 2 Rx FIFO Almost Full Hold until Serial Channel 2 Rx FIFO Almost Empty Request DMA on Serial Channel 2 Tx FIFO Almost Empty Hold until Serial Channel 2 Tx FIFO Almost Full Req
6. 11 Both Edges 2 3 18 TxX RX DATA REGISTER RDR TDR 2 3 18 1 Low LOC 0xN20 RW Tx Rx D7 0 HIGH LOC 0xN21 RW Tx Rx D7 0 2 3 19 RECEIVER MODE REGISTER RMR 2 3 19 1 1 D5 D6 7 Low LOC 0 22 Rx Enable encoded as follows 00 Disable Immediately 01 Disable After Reception 10 Enable Without Auto Enables 11 Enable With Auto Enables Rx Character Length encoded as follows 000 8 Bits 001 1 Bits 010 2 Bits 011 3 Bits 100 4 Bits 101 5 Bits 110 6 Bits 111 7 Bits RW Rx Parity Enable Rx Parity Sense encoded as follows 00 Even 01 Odd 10 Space 11 Mark 2 3 19 2 D1 D2 D3 4 HIGH LOC 0 23 RW RW RW 00 01 10 11 000 001 010 011 100 101 110 111 Queue Abort Rx CRC Enable Rx CRC Preset Value Rx CRC Polynomial encoded as follows 16 32 Reserved Rx Data Decoding encoded as follows NRZ NRZB NRZI Mark NRZI Space Biphase Mark Biphase Space Biphase Level Diff Biphase Level 2 3 20 RECEIVE COMMAND STATUS REGISTER RCSR 2 3 20 1 D0 Di D2 D3 D4 D5 D6 D7 2 3 20 2 D1 D2 D3 D4 7 Low LOC 0 24 RO RW RW RO RW RW RW RW Rx Character Available Rx Overrun Parity Error Frame Abort CRC Framing Error Rx CV EOT EOF Rx Break Abort Rx Idle Exited Hunt HIGH LOC 0xN25 RO RO RO RO WO 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
7. 2 3 4 2 D2 D3 D4 D5 D6 D7 010 2 bits 011 3 bits 100 4 bits 101 5 bits 110 6 bits 111 7 bits Reserved RO Loop Sending RO On Loop HiGH LOC 0XN05 DPLL Adjust Sync Edge encoded as follows 00 Both Edges 01 Rising Edge Only 10 Falling Edge Only 11 Adjust Sync Inhibit RW Clocks Missed Latched Unlatch RW Clocks Missed Latched Unlatch RW DPLL in Sync Quick Sync WO RCC FIFO Clear RO RCC FIFO Valid RO RCC FIFO Overflow 2 3 5 CHANNEL CONTROL REGISTER CCR 2 3 5 1 D0 4 D5 D6 7 2 3 5 2 D6 7 Low LOC 0xN06 Reserved Wait for Rx DMA Trigger Rx Status Block Transfer encoded as follows D6 being the LSB 00 No Status Block 01 One word Status Block 10 Two word Status Block 11 Reserved HIGH LOC 0 07 Tx Preamble Pattern encoded as follows 00 All Zeros 01 All Ones 10 Alternating amp 0 11 Alternating 0 amp 1 Tx Preamble Length encoded as follows 00 8 bits 01 16 bits 10 32 bits 11 64 bits Tx Flag Preamble Tx Status Block Transfer encoded as follows 19 2 3 6 2 3 7 2 3 8 2 3 9 00 No Status Block 01 One word Status Block 10 Two word Status Block 11 Reserved PRIMARY RESERVED REGISTER RESERVED 2 3 61 Low LOC 0xN08 00 07 RW Reserved 2 3 6 2 HIGH LOC 0xN09 00 07 RW Reserved SECONDARY RESERVED REGISTER RESERVED 2 371 Low LOC 0xNA 00 07 RW Reserved 2 3 75 HiGH LOC 0xNB 00 07 RW Reserved TEST MODE DATA REGISTE
8. 3 1 11 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRESS SPACE 37 OFFSET 0X18 RESET 0 00000000 3 1 12 PCI SUBSYSTEM DEVICE VENDOR ID REGISTER OFFSET 0X2C RESET 0X908010B5 3 1 13 PCI INTERRUPT LINE REGISTER OFFSET RESET 0X00 3 1 14 PCI INTERRUPT PIN REGISTER OFFSET RESET 0 01 3 1 15 PCI MIN REGISTER OFFSET RESET 0 00 sie ies E 3 1 16 PCIMAX LAT REGISTER OFFSET OX3F RESET O0XO00 esses eene tenente tenente tenente entente 32 LOCALCONFIGURATION 5 5 TABLE 3 2 1 LOCAL CONFIGURATION REGISTERS eene tenete tenente tense te tenere te tenete te 321 LOCAL ADDRESS SPACE 0 RANGE REGISTER FOR PCI TO LOCAL 39 PCI 0X00 RESET 0 322 MODE ARBITRATION REGISTER PCI 0X08 323 ENDIAN DESCRIPTOR REGISTER PCI 3 24 LOCAL ADDRESS SPACE 0 EXPANSION ROM BUS REGION DESCRIPTOR REGISTER PCLOXIS RESET 04003014 2 IS 3 3 RUNTIME REGISTERS EE TABLE 3 3 1 RUNTIME REGISTERS rect ie Lee eiere et Eee esI eee eee ta Eee tuto 3 3 1 INTERRUPT CONTROL STATUS PCI 0X68 RESET 0X00000000 3 3 SERIAL EEPROM CONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER
9. PCI 0 KW AIR KE 41 333 PCI PERMANENT CONFIGURATION ID REGISTER PCI 0X70 RESET 0 10859080 42 334 PCI PERMANENT REVISION ID REGISTER PCI 0X74 enne tenerent nennt tenni nennen 34 LOCALDMA REGISTERS REA RIEN ERNST ENTER TABLE 3 4 1 DMA REGISTERS necerte oee ER Ee 341 DMA CHANNEL 0 MODE REGISTER PCI 0X80 342 DMA CHANNEL 0 PCI ADDRESS REGISTER PCI 0 84 343 DMA CHANNEL 0 LOCAL ADDRESS REGISTER PCI 0X88 344 DMA CHANNEL TRANSFER SIZE BYTES REGISTER PCI 0 8 345 CHANNEL 0 DESCRIPTOR POINTER REGISTER 90 3 46 DMA CHANNEL 0 COMMAND STATUS REGISTER PCI OXA8 3 4 7 DMA ARBITRATION REGISTER PCI OXAC 348 DMA THRESHOLD REGISTER PCI Sie 3 5 MESSAGING QUEUE REGISTERS renani n a EN O R N EE E E TENN REIWEN ENTENTE 45 40 4 1 42 43 44 45 CHAPTER 5 HARDWARE CONFIGURATION 47 5 0 THE ON BOARD MASTER amp TRANSMIT RECEIVE CLOCKS sese 47 5 1 EEPROM JUMPER eee 47 5 2 CABLE INTERFACE CONNECTIONS TABLE 5 2 1 USER CABLE PIN OUT 5 3 BOARD LAYOUT we e ies 2 48 FIGURE 54 1 BOARD LAYO
10. 1011 Short Frame CV Polarity Residue Code 0 Residue code 1 Residue Code 2 Receive Command encoded as follows D12 being the LSB Null command Reserved Preset CRC Enter Hunt Mode Reserved Select FIFO Status Select FIFO Interrupt Level Select FIFO Request Level Reserved Reserved Reserved Reserved 2 3 21 2 3 22 2 3 23 2 3 24 1100 Reserved 1110 Reserved 1111 Reserved D6 RO First Byte in Error D7 RO Second Byte in Error RECEIVE INTERRUPT CONTROL REGISTER RICR 2 3 21 1 Low LOC 0xN26 DO RW TCOR Read Count TC RW Rx Overrun INTERRUPT ARMED 02 RW Parity Error Frame Abort INTERRUPT ARMED D3 RW Status on Words D4 RW Rx CV EOT EOF INTERRUPT ARMED 05 RW Rx Break Abort INTERRUPT ARMED D6 RW Rx Idle INTERRUPT ARMED D7 RW Exited Hunt INTERRUPT ARMED 2 3 21 2 HIGH LOC 0xN27 D0 7 RW Rx FIFO Control and Status Fill Interrupt DMA Level RECEIVE SYNC REGISTER RSR 2 3 22 1 Low LOC 0xN28 D0 7 RW RSYN 0 7 2 3 22 2 HIGH LOC 0xN29 0 7 RW RSYN 15 8 RECEIVE COUNT LIMIT REGISTER RCLR 2 3 23 Low LOC 0xN2A D0 7 RW RCL 7 0 2 3 23 2 HIGH LOC 0xN2B D0 7 RW RCL 15 8 RECEIVE CHARACTER COUNT REGISTER RCCR 2 3 24 1 Low LOC 0xN2C 00 7 7 0 2 3 24 2 HIGH LOC 0xN2D D0 7 RO RCC15 8 2 3 25 TIME CONSTANT 0 REGISTER 2 3 25 1 Low LOC 0xN2E D0 7 RW TC07 0 2 3 25 2 HIGH LOC 0xN2F D0 7 RW TO015 8 2 3 26 TRANSMIT MODE REGISTER TMR 2 3 26 Low
11. 1110 Select FIFO Interrupt Level 0111 Select FIFO Request Level 1000 Send Frame Message 1001 Send Abort 1010 Reserved 1011 Reserved 1100 Reset DLE Inhibit 1101 Set DLE Inhibit 1110 Reset EOF EOM 1111 Set EOF EOM 2 3 28 TRANSMIT INTERRUPT CONTROL REGISTER 2 3 29 2 3 30 2 3 31 2 3 32 2 3 28 1 DO D1 D2 D3 Low LOC 0xN36 RW RW RW RW RW RW RW RW TC1R Read Count TC Tx Overrun INTERRUPT ARMED Wait for Send Command Tx CRC Sent INTERRUPT ARMED Tx EOF EOT Sent INTERRUPT ARMED Tx Abort Sent INTERRUPT ARMED Tx Idle Sent INTERRUPT ARMED Tx Preamble Sent INTERRUPT ARMED HIGH LOC 0XN37 RW Tx FIFO Control and Status Fill Interrupt DMA Level TRANSMIT SYNC REGISTER TSR 2 3 29 1 D0 7 2 3 29 2 0 7 Low LOC 0xN38 RW TSYN 7 0 HIGH LOC 0 39 RW TSYN 15 8 TRANSMIT COUNT LIMIT REGISTER TCLR 2 3 30 1 0 7 2 3 30 2 0 7 Low LOC 0xN3A RW TCL 7 0 HIGH LOC 0XN3B RW TCL 15 8 TRANSMIT CHARACTER COUNT REGISTER TCCR 2 3 31 1 0 7 2 3 31 2 0 7 Low LOC 0xN3C RO TCC 7 0 HIGH LOC 0XN3D RO TCC 15 8 TIME CONSTANT 1 REGISTER TC1R 2 3 32 1 Low LOC 0xN3E 0 7 2 3 32 2 D7 0 RW 7 0 HIGH LOC 0XN3F RW 15 8 CHAPTER 3 PCI INTERFACE 3 0 PCI INTERFACE REGISTERS A PCI9080 I O Accelerator from PLX Technology handles the PCI Interface
12. D4 D5 D6 D7 Low LOC 0xN1C RW RW RW RW RO RW RO RW HIGH RO RW RO RW RO RW RO RW BRGO ZC Latched Unlatch ZC Latched Unlatch DPLL SYNC Latched Unlatch RCC Overflow Latched Unlatch CTS CTS Latched Unlatch DCD DCD Latched Unlatch LOC 0xN1D TxREQ TxREQ Latched Unlatch RxREQ RxREQ Latched Unlatch TxC TxC Latched Unlatch RxC RxC Latched Unlatch 2 3 17 STATUS INTERRUPT CONTROL REGISTER SICR 2 3 17 1 DO D1 D2 D3 D4 5 2 3 17 2 Low LOC OxN1E RW RW RW RW RW 00 01 10 11 00 01 10 11 HIGH RW 01 10 11 RW ZC INTERRUPT ENABLE ZC INTERRUPT ENABLE DPLL SYNC INTERRUPT ENABLE RCC Overflow INTERRUPT ENABLE CTS Interrupts encoded as follows D4 being the LSB Disabled Rising Edge Only Falling Edge Only Both Edges DCD Interrupts encoded as follows D6 being the LSB Disabled Rising Edge Only Falling Edge Only Both Edges LOC 0xNIF TxREQ Interrupts encoded as follows Disabled Rising Edge Only Falling Edge Only Both Edges RxREQ Interrupts encoded as follows 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges RW TxC Interrupts encoded as follows D12 being the LSB 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges RW RxC Interrupts encoded as follows D14 being the LSB 00 Disabled 01 Rising Edge Only 10 Falling Edge Only
13. almost full flag will be asserted when the FIFO has Total FIFO size in bytes 0x10 bytes in it For the standard 32Kbyte FIFO an almost full value of 0x10 will cause the almost full flag to be asserted when the FIFO has 32752 bytes of data 32768 16 or 0x8000 0x10 The values placed in the FIFO almost registers are programmed to the FIFO chips whenever a FIFO reset is performed the proper steps to program these values are e Program the respective FIFO almost register s Perform a FIFO reset of the respective FIFO The value in the almost register is now programmed into the FIFO chips Please note if the FIFO almost registers are left at a value of 0x0 during a FIFO reset the almost flags will be set to the FIFO chip manufacturer default of 7 bytes from empty and 7 bytes from full PCI DMA 44 4 5 4 6 The PCI DMA functionality allows data to be transferred to from host memory from to 510478 onboard FIFO buffers with the least amount of CPU overhead PLX Technology PCI9080 interface chip used on SIO4 cards handles all PCI DMA functions Due to the lack of interrupt sources needed by some device drivers demand mode DMA transfers are not fully supported by the 5104 at this time ZILOG Z16C30 DMA While not a true DMA in the technical sense the Zilog DMA function does provide a means for data transfer mostly transparent to the user to from the Z16C30 serial controller chips from to the S
14. 2 HIGH LOC 0XN05 23 5 CHANNEL CONTROL REGISTER CCR 23 5 1 Low LOC 0XN00 2 3 5 2 HIGH LOC 0XNO7 23 6 23 6 1 Low LOC 0XNO08 2 3 6 2 HIGH LOC 2 3 7 2 3 7 1 Low LOC OXNA 2 3 7 2 HIGH LOC OXNB 2 3 8 TEST MODE DATA REGISTER TMDR 2 3 8 1 Low LOC 2 3 8 2 HIGH LOC OXN1A 2 3 9 2 3 9 1 Low LOC OXNE 2 3 9 2 HIGH LOC OXNOF 2 3 10 CLOCK MODE CONTROL REGISTER CMCR Low LOC 0xN10 HIGH LOC 0 11 2 3 11 HARDWARE CONFIGURATION REGISTER HCR 2 3 10 1 2 3 10 2 23111 Low LOC 0XN12 23 12 HIGH LOC 0XN13 2 3 12 INTERRUPT VECTO 23121 LOW LOC OXN14 23 122 HIGH LOC OXN2A 2 3 13 I O CONTROL REGISTER 23131 LOW LOC OXNIO 23 132 HIGH LOC OXNI7 2 3 14 INTERRUPT CONTR TEST MODE CONTROL REGISTER TMCR R REGISTER IVR OL REGISTER ICR 2 3 14 1 2 3 14 2 2 3 15 1 2 3 15 2 2 3 16 1 2 3 16 2 2 3 17 1 2 3 17 2 2 3 18 1 2 3 18 2 Low LOC OXN18 HIGH LOC OXNI9 2 3 15 DAISY CHAIN CONTROL REGISTER Low LOC OXN1A HIGH RW LOC OXNIB 2 3 16 MISCELLANEOUS INTERRUPT STATUS REGISTER MISR Low LOC 0XNIC HIGH LOC OXNID 2 3 17 STATUS INTERRUPT CONTROL REGISTER SICR LOW LOC OXNI1E HIGH LOC OXNIF 2318 TX RX DATA REGISTER RDR TDR Low LOC 0xN20 HIGH LOC OXN21 2 3 10 RECEIVER MODE REGISTER RMR 233984 TONN ee 23192 HIGH LOC 2
15. Header Type Latency Timer Cache Line Size 0x00002008 Local 7 0 PCI Base Addr 2 for Local Addr Space 0 2 0 00000000 PCI Base Addr 3 for Local Addr Space PCIBAR3 Unused 0 00000000 Subsystem ID Subsystem Vendor ID 0x90802400 PCI Base Address to Local Expansion ROM Unused 0x00000000 Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x00000100 Local Note The Local Base Address for the PCI Configuration registers in Local Address Space is 0xC0000000 However there should be no need for the user to access the PCI Configuration registers through Local Address Space PCI Base Addr 1 for I O Mapped Local Runtime DMA Registers 0x00000001 PCIBAR1 Y Y Y Y PCI Base Addr 0 for Memory Mapped Local Runtime DMA 0x00000000 Registers PCIBARO Y Y 3 1 1 PCI CONFIGURATION ID REGISTER OFFSET 0X00 RESET 0X908010B5 D15 0 Vendor ID 0x10B5 PLX Technology D31 16 Device ID 0x9080 PCI9080 3 1 2 PCI DO Space A 1 allows the device to respond to I O space accesses D1 Memory Space 1 allows the device to respond to memory space accesses D2 PCI Master Enable A 47 allows the device to behave as a PCI bus master Note This bit must be set for the PCI 9080 to perform DMA cycles D3 Special Cycle Not Supported D4 Memory Write Invalidate enables memory write invalidate 05 VGA Palette Snoop Not Supported D6 Parity Error Response A 0 indicates t
16. cable will load the cable Writing a 1 to this bit will turn on the receivers for the Channel 1 upper portion of the cable The signals that are turned on are the Channel 1 RxD and Channel 1 DCD on the upper portion of the cable This will cause these signals on the cable to go from a tri state condition to a loaded condition D5 Enable the Channel 1 Receivers for the Lower portion of the cable will load the cable Writing a 1 to this bit will turn on the receivers for the Channel 1 lower portion of the cable The signals that are turned on are the Channel 1 RxD and Channel 1 DCD on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to a loaded condition D6 Reserved D7 Reset Zilog for Channel 1 2 Pulsed Writing 1 to this bit will cause the channel 1 2 Zilog Z16C30 USC to be reset This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Note After power up and after any reset to this component the next access to channel 1 or channel 2 USC must be a write of 0x00 to offset 0x00 of channel 1 USC D8 Channel 1 Tx FIFO Empty TRUE 0 D9 Channel 1 Tx FIFO Almost Empty TRUE 0 D10 Channel 1 Tx FIFO Almost Full TRUE 0 D11 Channel 1 Tx FIFO Full TRUE 0 D12 Channel Rx FIFO Empty TRUE 0 D13 Channel 1 Rx FIFO Almost Empty TRUE 0 D14 Channel Rx FIFO Almost Full TRUE 0 D15
17. in this register is used to watch the Rx data as it is being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to the interrupt logic An actual interrupt to the host will only occur if this interrupt source is enable in the interrupt control register 2 1 23 CHANNEL 4 SYNC DETECT LOC 0 5 00 7 Channel 4 Sync Detected Data The data in this register is used to watch the Rx data as itis being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to the interrupt logic An 14 actual interrupt to host will only occur if this interrupt source is enable in the interrupt control register 2 1 24 INTERRUPT CONTROL LOC 0x60 DO Enable Channel 1 Interrupt on Sync Detected D1 Enable Channel 1 Interrupt on Tx FIFO Almost Empty D2 Enable Channel 1 Interrupt on Rx FIFO Almost Full D3 Enable Channel Interrupt on USC Request Interrupt D4 Enable Channel 2 Interrupt on Sync Detected D5 Enable Channel 2 Interrupt on Tx FIFO Almost Empty D6 Enable Channel 2 Interrupt on Rx FIFO Almost Full D7 Enable Channel 2 Interrupt on USC Request D8 Enable Channel 3 Interrupt on Sync Detected D9 Enable Channel 3 Interrupt on Tx FIFO Almost Empty D10 Enable Channel 3 Interrupt on Rx FIFO Almost Full D11 Enable Channel 3 Interrupt on USC Request Interrupt D12 Ena
18. means the Almost Empty Almost Full flags should be set to a value of at least 8 Chaining Enable indicates chaining mode is enabled For chaining mode the DMA source address destination address and byte count are loaded from memory in PCI Space Done Interrupt Enable A enables interrupt when DMA done Note If DMA clear count mode is enabled the interrupt won t occur until the byte count is cleared Local Addressing Mode indicates local addresses LA 31 2 to be held constant Note This bit should always be set to 1 no address increment Demand Mode Enable A causes the DMA controller to operate in Demand Mode In Demand Mode the DMA controller transfers data when its DREQ input is asserted The DMA controller transfers Lwords 32bits of data This may result in multiple transfers for an 8 or 16 bit bus Write and Invalidate Mode for DMA Transfers When set to 1 PCI 9080 performs Write and Invalidate cycles to the PCI bus PCI 9080 supports Write and Invalidate sizes of 8 or 16 Lwords The size is specified in the PCI Cache Line Size Register If a size other than 8 or 16 is specified PCI 9080 performs write transfers rather than Write and Invalidate transfers Transfers must start and end at the Cache Line Boundaries DMA EOT End of Transfer Enable Unused Stop Data Transfer Mode A 0 sends a BLAST to terminate DMA transfer Note This bit should always be set to 0
19. www generalstandards com The information in this document is subject to change without notice General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent right of any rights of others General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No parts of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation This user s manual provides information on the register level programming of the PMC SIO4 board Information required for customized software development This manual assumes that the u
20. 3 20 RECEIVE COMMAND STATUS REGISTER RCSR EINE ere VE 28 23201 TON OG AUGE 28 23202 Hich OG OR NOD ee 28 2 3 21 RECEIVE INTERRUPT CONTROL REGISTER ORICR U n n a 292117 LOW XDOCOSNO 23212 HIGH LOC DAR 2 3 22 RECEIVE SYNC REGISTER RSR 23221 LOW LOC 0xN29 23222 HIGH LOC ON 2 323 RECEIVE COUNT LIMIT REGISTER RCLR 23521 LOW 23232 NE 2 3 24 RECEIVE CHARACTER COUNT REGISTER RCCR 29 23241 Low LOC 0XN2C 29 23242 HIGH LOC OXN2D 29 2325 TIME CONSTANT 0 REGISTER TCOR a Sec vev 30 2 3 251 LOW OD SD 30 23252 HIGH 2 M 30 2326 TRANSMIT MODE REGISTER TMR 30 288017 NNN 30 2 4262 HIGH LOC OXN33 e 30 2327 TRANSMIT COMMAND STATUS REGISTER TCSR 2 31 23271 LOW 4 31 53972 MEN bine m E 31 2 328 TRANSMIT INTERRUPT CONTROL REGISTER TICR 32 23281 LOW DO 23282 HIGH RE tre hd erento 2329 TRANSMIT SYNC REGISTER TSR es 23291 LOW LOC 0XN38 2 4292 HIGH 39 see E 2 3 30 TRANSMIT COUNT LIMIT REGISTER TCLR
21. 3 TX ALMOST LOC 0x30 m ge en Vi CHANNEL 3 Er e EE CHANNEL 3 ALMOST LOC NE CHANNEL CONTROL STATUS LOCH CHANNEL 4 TX ALMOST Ne CHANNEL 4 RX ALMOST LOC 0 44 CHANNEL 4 FIFO LOC 0x49 CHANNEL 4 CONTROL STATUS LOC 0 4 E CHANNEL 1 SYNC DETECT LOC OX SOR t D CHANNEL 2 SYNC DETECT LOC DSD EE CHANNEL 3 SYNC DETECT LOC SSN e RR CR e e pti ate CHANNEL 4 SYNC DETECT LOC Nat INTERRUPT CONTROL LOC 0X60 INTERRUPT STATUS LOC 0X64 SERIALCONTROLLER REGISTERS M m ux t USC REGISTERS ttt ttt titt ttt ttt ttt ttt ttt ttt ttt CHANNEL 1 USC LOC 0X100 TO DD EE CHANNEL 2 USC LOC 0X200 TO OX27E CHANNEL 3 USC LOC 0X300 0X37E EN beet ar e let CHANNEL 4 USC LOC 0X400 TO 0 47 CHANNEL COMMAND ADDRESS REGISTER CCAR LOW LOC oer T m E TOC DONDE de toe LL MD MM MEL M AD EUR ALTI A CU 16 CHANNEL MODE REGISTER CMR ttt ttt ttt ttt ttt ttt 17 2 3 3 1 Low LOC 0xN02 CHANNEL COMMAND STATUS REGISTER CCSR PRIMARY RESERVED REGISTER RESERVED SECONDARY RESERVED REGISTER RESERVED 23 32 HIGH LOC 0XN03 234 23 4 1 Low LOC OXNO04 2 3 4
22. 34 LOCAL DMA REGISTERS The Local DMA registers are used to setup the DMA transfers to and from the on board FIFOs Since the PCI PMC HPDI22 is half duplex data is only transferred in one direction at a time only DMA Channel 0 is used TABLE 3 4 1 DMA REGISTERS CFG Offset PCI Local Register Name Value after Addr Ad Writable Reset 0 80 1 dr 0x80 0x100 8 0x90 0 94 DMA Channel 0 PCI Address Register DMA Channel 0 Transfer Byte Count Register DMA Channel 0 Descriptor Pointer Register DMA Channel 1 Mode Register Unused 0 00000003 0 124 0 128 DMA Channel Local Address Register Unused 0 00000000 DMA Channel 1 Transfer Byte Count Register Unused 0x00000000 DMA Channel Descriptor Pointer Register Unused 0x00000000 D DMA Channel 0 Command Status Register rit 3 4 1 DMA CHANNEL 0 MODE REGISTER PCI 0x80 D1 0 Local Bus Width 00 8 bit DMA transfer width 01 16 bit DMA transfer width 10 11 32 bit DMA transfer width D5 2 Internal Wait States Unused D6 Ready Input Enable Note This bit should always be set to 1 Ready Input Enabled D7 Bterm Input Enable Unused Note This bit should always be set to 0 BTERM Disabled 08 Local Burst Enable D10 D11 D12 D13 D14 D15 D16 D17 Note If Burst enabled the user must ensure FIFO will not become empty read or full write during the burst access For Demand Mode DMA this
23. C The Zilog ZI6C30s Transmit FIFO Buffers Receive FIFO Buffers Control Logic DC PMC PMC Bus Interface 12 1 3 14 1 5 1 6 1 1 8 BOARD CONTROL REGISTER The board control register will provide configuration for the PMC DMA request priorities BOARD STATUS REGISTER The board status register will provide status of the board for future expansion SYNC WORD SELECTION REGISTERS The sync word selection registers are used to provide an interrupt upon the reception of a particular character on a particular channel The character is software programmable DATA RECEPTION Data is received into the Zilog Z16C30 After the data is received the software may retrieve the data from the Z16C30 or have the data buffered into the main Rx FIFOs and retrieved by the software at a later time depending on how the Z16C30 has been initialized DATA TRANSMISSION Data is placed into the Zilog Z16C30 or buffered into the main Tx FIFOs depending on how the Z16C30 has been initialized The Zilog can transmit and receive in any of several serial protocols Asynchronous External Sync Isochronous Asynchronous with Code Violations Monosynchronous Bisynchronous HDLC SDLC Plus many more ERROR DETECTION By utilizing the features of the Z16C30 various forms of error detection are built into the board The following are some of the methods of error detection available e Parity error detection err
24. CACHE LINE SIZE REGISTER OFFSET 0X0C RESET 0x00 D7 0 System cache line size in units of 32 bit words 3 1 7 PCI LATENCY TIMER REGISTER OFFSET 0X0D RESET 0 00 D7 0 PCILatency Timer Units of PCI bus clocks the amount of time the PCI9080 as a bus master can burst data on the PCI bus 3 1 8 PCI HEADER TYPE REGISTER OFFSET 0XOE RESET 0x00 D6 0 Configuration Layout Type 0 D7 Header Type 0 3 1 9 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL RUNTIME DMA REGISTERS OFFSET 0x010 RESET 0 00000000 D0 Memory Space Indicator A 0 indicates register maps into Memory space Note Hardcoded to 0 D2 1 Location of Register 00 Locate anywhere in 32 bit memory address space Note Hardcoded to 0 D3 Prefetchable Note Hardcoded to 0 D7 4 Memory Base Address Default Size 256 bytes Note Hardcoded to 0 D31 8 Memory Base Address Memory base address for access to Local Runtime and DMA registers Note is Memory Mapped Base Address of PCI9080 Registers 3 1 10 PCI BASE ADDRESS REGISTER FOR I O ACCESS TO LOCAL RUNTIME DMA REGISTERS OFFSET 0x14 RESET 0x00000001 DO Memory Space Indicator A indicates the register maps into I O space Note Hardcoded to 1 Reserved D7 2 Base Address Default Size 256 bytes Note Hardcoded to 0 D31 8 I O Base Address Base Address for I O access to Local Runtime and DMA Registers Note PCIBARI is I O Mapped Base Address of P
25. CI9080 Registers 3 1 11 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRESS SPACE 0 OFFSET 0X18 RESET 0x00000000 DO Memory Space Indicator A 0 indicates register maps into Memory space Specified in Local Address Space 0 Range Register LASORR D2 1 Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space Specified in Local Address Space 0 Range Register LASORR D3 Prefetchable A 0 indicates reads are not prefetchable Specified in Local Address Space 0 Range Register LASORR D31 4 Memory Base Address Memory base address for access to Local Address Space 0 3 1 12 PCI SUBSYSTEM DEVICE VENDOR ID REGISTER OFFSET 0X2C RESET 0X908010B5 D15 0 Subsystem Vendor ID 0x10B5 PLX Technology D31 16 Subsystem Device ID 0x2400 General Standards Corporation HPDI32 3 1 13 PCI INTERRUPT LINE REGISTER OFFSET 0X3C RESET 0x00 07 0 Interrupt Line Routing Value Indicates which input of the system interrupt controller s to which the interrupt line of the device is connected 3 1 14 PCI INTERRUPT PIN REGISTER OFFSET 0X3D RESET 0X01 07 0 Interrupt Pin register Indicates which interrupt pin the device uses O1 INTA Note PCI 9080 supports only one PCI interrupt pin INTA 3 1 15 PCI MIN_GNT REGISTER OFFSET 0X3E RESET 0x00 D7 0 Minimum Grant Specifies the minimum burst period the device needs assuming clock rate of 33 MHz V
26. Channel 1 Rx FIFO Full TRUE 0 FIFO status flags are active low indicators of current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates 8 that it is not true There only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows OxC 1100 Almost Empty and Empty xD 1101 Almost Empty but not Empty xF 1111 In between Almost Empty and Almost Full OxB 1011 Almost Full but not full 0x3 0011 Almost Full and Full 2 1 8 CHANNEL 2 TX ALMOST LOC 0x20 D7 0 Channel 2 Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel D0 15 Used for the Almost Empty Flag D16 31 Used for the Almost Full Flag 2 1 9 CHANNEL 2 RX ALMOST LOC 0x24 00 7 Channel 2 Rx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel 00 15 Used for the Almost Empty Flag D16 31 Used for the Almost Full Flag 2 1 10 CHANNEL 2 FIFO LOC 0x28 D0 7 Channel 2 FIFO Data The FIFOs are setup in a way that the Rx FIFO and the Tx FIFO are located at the same address A write to this address will be directed toward the Tx FIFO and a read from this address will be directed toward the Rx FIFO 2 1 11 CHANNEL 2 CONTROL STATUS LOC 0x2C DO Reset Channel 2 Tx FIFO Pulsed Writ
27. IO4 s onboard FIFO buffers While in transmit mode the Zilog DMA provides a mechanism by which each byte transferred to the 510475 onboard transmit FIFO buffer will automatically be read out by the Z16C30 chip and sent out to the cable This operation will continue as long as the transmit FIFO buffer has data in it While in receive mode the Zilog DMA provides a mechanism by which each byte read from the cable by the Z16C30 chip will be automatically transferred to 510475 onboard receive FIFO buffer This operation will continue as long as the receive FIFO buffer is not full INTERRUPTS The 5104 is capable of generating a number of interrupts to the host CPU which may be utilized by the application code or device driver to perform various operations Interrupt sources may include but are not limited to receive FIFO buffer almost empty sync word detection and Zilog Z16C30 serial controller chip interrupts Upper Lower Connector Naming Convention Since all the cable transceivers are bidirectional the serial Data and Clock signals can be transmitted or received on two separate IO connector pins The naming convention Upper and Lower is used in order to differentiate between these two pins with identical function Typically one pin is used for receive data and the other pin is used for transmit Separate controls for the transmitter receiver enables allow the user flexibility to monitor the transmit line or perform a sta
28. LOC 0XN32 D0 1 Tx Enable encoded as follows DO being the LSB 00 Disable Immediately 01 Disable After Transmission 10 Enable Without Auto Enables 11 Enable With Auto Enables D2 4 Tx Character Length encoded as follows 000 8 Bits 001 1 Bit 010 2 Bits 011 3 Bits 100 4 Bits 101 5 Bits 110 6 Bits 111 7 Bits 05 RW Tx Parity Enable D6 7 Tx Parity Sense encoded as follows 00 Even 01 10 Space 11 Mark 2 3 26 2 HIGH LOC 0xN33 DO RW Tx CRC EOF EOM D1 RW Tx CRC Enable D2 RW Tx CRC on Preset Value D3 4 Polynomial Tx CRC encoded as follows 00 CRC CCITT 01 16 10 32 11 05 7 Tx Data Encoding encoded as follows 000 NRZ 001 010 011 100 101 110 111 NRZB NRZI Mark NRZI Space Biphase Mark Biphase S pace Biphase Level Diff Biphase Level 2 3 27 TRANSMIT COMMAND STATUS REGISTER TCSR 2 3 27 1 DO D1 D2 D3 D4 D5 D3 D4 7 Low LOC 0xN34 RO RW RO RW RW RW RW RW Tx Buffer Empty Tx Underrun All Sent Tx CRC Sent Tx EOF EOT Sent Tx Abort Sent Tx Idle Sent Tx Preamble Sent HIGH LOC 0xN35 Tx Idle Line Condition 000 SYNC Flag Normal 001 Alternating amp 0 010 All Zeros O11 All Ones 100 Reserved 101 Alternating Mark amp Space 110 Space 111 Mark RW TxWait on Underrun WO Transmit Command 0000 Null Command 0001 Reserved 0010 Preset CRC 0011 Reserved 0100 Reserved 0101 Select FIFO Status
29. Output Channel X Upper CTS DCD RS422 485 Transceiver CMOSInput Channel X Lower CTS DCD RS422 485 CMOSOutput Input Output Channel X Lower CTS DCD RS422 485 Transceiver Cable Connector The direction of the CTS DCD transceivers follows the data transceivers l e if channel X data is configured to transmit on the upper portion of the cable the CTS DCD signal on the upper portion of the cable will also be configured as an output One work around to enable receiving CTS DCD signals while data is configured as an output would be to wire a cable such that the CTS DCD lines are connected to the lower cable portion thus data would be transmitted on the upper cable portion but the 5104 can receive the CTS DCD signal FIGURE 5 4 4 SIO4 CTS DCD ROUTING CHAPTER 6 ORDERING OPTIONS 6 0 ORDERING INFORMATION Since the SIO4 is designed to fit a variety of high speed serial interface needs there are several options that must be specified when ordering the SIO4 board Please consult our sales department with your application requirements to decide on the correct ordering options 6 0 1 CABLE INTERFACE RS485 422 Interface THE RS485 RS422 INTERFACE PROVIDES FOR CLOCK SPEEDS UP TO 26MHZ THIS IS THE STANDARD INTERFACE OPTION RS232 Interface THE RS232 INTERFACE PROVIDES FOR CLOCK SPEEDS UP TO 1MHZ THIS IS THE STANDARD INTERFACE OPTION 6 0 2 FIFO SIZE The SIO4 can accept FIFOs with depths ranging from 512 byt
30. PMC SIO4 User Manual General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail techsupport generalstandards com PMC SIO4 Documentation History 8 9 10 11 12 October 24 1997 combined PMC SIO4 documentation with the latest VME SIO4 documentation November 19 1997 edited Register map amp inserted Zilog data book information into publication section amp deleted non pertinent information out of Chapter 1 December 1 1997 edited bit map and bit descriptions edited section numbering and edited table of contents December 2 1997 edited Chapter 3 hardware configurations April 17 1998 Updated bit map April 20 24 1998 Drew description of clock jumper configurations April 24 1998 Inserted PLX PCI Register maps into Chapter2 moved Local Registers to Chapter 3 updated section numbering and TOC May 1 released Manual revision N R Updated Register Map Table 3 0 1 page 53 August 98 Corrected errors January 02 Corrected errors May 30 2002 Added Programming Section corrected errors Copyright 1998 General Standards Corp Additional copies of this manual or other General Standards Corporation literature may be obtained from General Standards Corporation 8302A Whitesburg Drive Huntsville Alabama 35802 Telephone 256 880 8787 Fax 256 880 8788 Company URL
31. R TMDR 2 3 81 Low LOC 0xNC 00 07 RW TestData7 0 2 3 8 2 HIGH LOC 0xN1A D0 D7 RW Test Data 7 0 TEST MODE CONTROL REGISTER TMCR 2 3 9 1 Low LOC 0xNE D0 4 Test Register Address encoded as follows 00000 Null Address 00001 High Byte of Shifters 00010 CRC Byte 0 00011 CRC Byte I 00100 Rx FIFO Write 00101 Clock Multiplexer Outputs 00110 CTROand Counters 0011 Clock Multiplexer Inputs 01000 DPLL State 01001 Low Byte of Shifters 01010 CRC Byte 2 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 HIGH RW CRC Byte 3 Tx FIFO Read Reserved I O and Device Status Latches Internal Daisy Chain Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 4044H 4044H 4044H 4044H 4044H 4044H 4044H 4044H Reserved LOC OXxNOF Reserved 2 3 10 CLOCK MODE CONTROL REGISTER CMCR 2 3 10 1 D0 2 Low LOC 0 10 RW 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 Receive Clock Source encoded as follows Disabled RxC Pin TxC Pin DPLL Output BRGO Output Output CTRO Output CTR1 Output Transmit Clock Source encoded as follows Disabled RxC Pin TxC Pin DPLL Output BRGO Output Output CTRO Output 2 3 10 2 111 RW 00 01 10 11 Output DPLL Clock Source encode
32. STER IVR 2 3 12 1 Low LOC 0 14 RW IV 7 0 HIGH LOC 0XN2A RO Modified Vector encoded as follows 000 None 001 Device Status 010 Status 011 Transmit Data 100 Transmit Status 101 Receive Data 110 Receive Status 111 Not Used D12 15 RO IV 7 4 2 3 13 I O CONTROL REGISTER IOCR 2 3 13 1 0 2 Low LOC 0 16 RxC Pin Control encoded as follows 000 Input Pin 001 Rx Clock Output 010 Rx Byte Clock Output 011 SYNC Output 100 BRGO Output 03 05 2 3 13 2 20 11 02 03 101 Output 110 CTRO Output 111 DPLL Rx Output TxC Pin Control encoded as follows 000 Input Pin 001 Tx Clock Output 010 Tx Byte Clock Output 011 Tx Complete Output 100 BRGO Output 101 Output 110 Output 111 DPLL Tx Output TxD Pin Control encoded as follows 00 Tx Data Output 01 3 State Output 10 Output 0 11 Output 1 HIGH LOC 0XN17 RxREQ Pin Control encoded as follows 00 Input pin 01 Rx DMA Request Output 10 Output 0 11 Output 1 TxREQ Pin Control encoded as follows 00 Input pin 01 Tx DMA Request Output 10 Output 0 11 Output 1 DCD Pin Control encoded as follows 00 DCD Input 01 DCD SYNC Input 10 Output 0 1 Output 1 CTS Pin Control encoded as follows 00 CTS Input 01 CTS Input 10 Output 0 11 Output 1 2 3 14 INTERRUPT CONTROL REGISTER ICR 2 3 14 1 DO D1 D2 D3 D4 DS D6 7 Low LOC 0xN18 RW Device Stat
33. UCTION 1 1 10 1 1 FIGURE 1 1 1 FUNCTIONAL DESCRIPTION 1 2 13 14 15 1 6 17 1 8 20 INTRODUCTIONS t er er ret tee d A EE DIE 1 BUNC TIONAL DESCRIPTIONS ee reborn ee etre sedie eee 1 BOARD CONTROL BOARD STATUS REGISTER REGISTER MAP e tree am a e RON PUN RR RO OE 4 TABLE 2 0 1 PMC SIO4 REGISTER ADDRESS MAb 4 2 1 2 1 0 2 1 2 2 14 2 1 5 2 1 6 2 1 7 2 1 8 2 1 9 2 1 10 2 1 11 2 1 12 2 1 13 2 1 14 2 1 15 2 1 16 2 1 17 2 1 18 2 1 19 2 1 20 2 1 21 2 1 22 2 1 23 2 1 24 2 1 25 23 2 3 1 2 3 1 1 2 3 1 2 2 3 1 3 2 3 14 2 3 2 2 3 2 1 23 22 2 33 BIT MAP FOR LOCAL SPACE REGISTERS eerte ttt ttt ttt ttt tot 5 FIRMWARE REVISION LOG GOD p pe e e A S REN EPA ERE CLOCK CONTROL LOC CHANNEL 1 TX ALMOST LOC 0 10 CHANNEL 1 RX ALMOST LOC 0x14 en 42 CHANNEL 1 FIFO LOC 0X18 CHANNEL I CONTROL STATUS LOOS 7 CHANNEL ANGSTEN Ne CHANNEL 2 RX ALMOST LOC CHANNEL 2 FIFO LOC 0X28 CHANNEL 2 CONTROL STATUS 0 2 CHANNEL
34. UT sne 48 54 THE ZILOG CLOCK SELECT JUMPERS J3 J4 III 48 FIGURE 5 4 2 CLOCK JUMPERS ROUTING DATA ROUTING n treten tenente nain nnn 50 FIGURE 5 4 4 SIO4 CTS DCD e LE KLEER 50 CHAPTER 6 ORDERING OPTIONS 2 to tones enun 51 6 0 6 0 1 6 0 2 6 0 3 6 1 ORDERING INFORM ATION petite teret ett ta een eres ege VES ee Ree a Y tede E Ree RENE hene 51 GABLE INTERFACE dec RETREAT usss 51 cob cou tsk hsp D ER 51 RHOD RR 51 CUSTOM APPLICATIONS 51 VII CHAPTER 1 INTRODUCTION 10 INTRODUCTION The 5104 interface card is capable of transmitting and receiving serial data generating interrupts and also provides loop back testing This card provides the following specific functionalities PMC Bus Interface Interrupt functionality FIFOs are provided for data transmit and for data receive to increase the size of the receive buffers User interface signal connections are provided via connectors on the front panel 1 1 FUNCTIONAL DESCRIPTION As shown in the functional block diagram see Figure 1 1 1 this board includes the following PMC Bus Slave Interface RS 485 422 Differential Cable Transceivers 2 Universal Serial Controllers US
35. able This will cause this signal on the cable to go from a tri state condition to a driven state D10 Channel 3 Enable Receive Upper CIk o Writing 1 to this bit will turn on receiver for Channel 3 Rx clock on upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a loaded condition D11 Channel 3 Enable Receive Lower CIk Writing 1 to this bit will turn on the receiver for the Channel 3 Rx clock on the lower portion of the cable This will cause this signal on the cable to go from a tri state condition to loaded condition D12 Channel 4 Enable Drive Upper Writing a 1 to this bit will turn on the transmitter for the Channel 4 Tx on the upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a driven state D13 Channel 4 Enable Drive Lower Writing 1 to this bit will turn on the transmitter for the Channel 4 Tx CIk on the lower portion of the cable This will cause this signal on the cable to go from a tri state condition to a driven state D14 Channel 4 Enable Receive Upper CIk Writing 1 to this bit will turn on the receiver for the Channel 4 Rx clock on the upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a loaded condition D15 Channel 4 Enable Receive Lower CIk Writing a 1 to this bit will turn on the receiv
36. alue is in 250 nsec increments A 0 indicates no stringent requirement 3 1 16 REGISTER OFFSET 0X3F RESET 0x00 07 0 Maximum Latency Specifies the maximum burst period the device needs assuming a clock rate of 33 MHz Value is in 250 nsec increments A 0 indicates no stringent requirement 32 LOCAL CONFIGURATION REGISTERS The Local Configuration registers give information on the Local side implementation Since Local Expansion ROM Local Address Space 1 and Direct Master accesses are not implemented on PCI PMC HPDI32 the descriptions of these registers have been omitted Most of the Local Configuration Registers are preloaded from the configuration Serial EEPROM at system reset TABLE 3 2 1 LOCAL CONFIGURATION REGISTERS Register Name Value after Writable Reset Range for PCI to Local Address Space 0 OxFFFFF000 Y Local Base Address Remap for PCI to Local Address Space 0 0x00000000 Unused Mode Arbitration Register 0x00000000 Big Little Endian Descriptor 0x00000000 2 gt 511521092 Range for PCI to Local Expansion ROM Unused 0x00000000 Local Base Address Re map for PCI to Local Expansion ROM 0x00000000 and BREQo control Unused Local Bus Region Descriptions for PCI Local Accesses 0x00000000 Range for Direct Master to PCI Unused 0 00000000 Local Base Address for Direct Master to PCI Memory Unused 0 00000000 R Local Base Addre
37. annel 00 15 Used for the Almost Empty Flag D16 31 Used for the Almost Full Flag 2 1 14 CHANNEL 3 ALMOST LOC 0x38 D0 7 Channel 3 FIFO Data The FIFOs are setup in way that the Rx FIFO and the Tx FIFO are located at the same address write to this address will be directed toward the Tx FIFO and read from this address will be directed toward the Rx FIFO 2 1 15 CHANNEL 3 CONTROL STATUS LOC DO Di D2 D3 D5 Reset Channel 3 Tx FIFO Pulsed Writing a 1 to this bit will cause the channel 3 Tx FIFOs to be reset If the channel 3 Tx Almost register is not a value of 0x00000000 then this will also cause the channel 3 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit 15 a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Reset Channel 3 Rx FIFO Pulsed Writing a 17 to this bit will cause the channel 3 Rx FIFOs to be reset If the channel 3 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 3 Rx FIFOs almost flags to be programmed After setting this bit to a 1 itis the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to re
38. ble The signals that are turned on are the Channel 3 RxD and Channel 3 DCD on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to loaded condition Reserved Reset Zilog for Channel 3 4 Pulsed Writing 1 to this bit will cause the channel 3 4 Zilog Z16C30 USC to be reset This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Note that after power up and after any reset to this component the next access to channel 3 or channel 4 USC must be a write of 0x00 to offset 0x00 of channel 3 USC Channel 3 Tx FIFO Empty TRUE 0 Channel 3 Tx FIFO Almost Empty TRUE 0 Channel 3 Tx FIFO Almost Full TRUE 0 Channel 3 Tx FIFO Full TRUE 0 Channel 3 Rx FIFO Empty TRUE 0 Channel 3 Rx FIFO Almost Empty TRUE 0 Channel 3 Rx FIFO Almost Full TRUE 0 Channel 3 Rx FIFO Full TRUE 0 The FIFO status flags are active low indicators of the current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates that it is not true There are only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows OxC 1100 OxD 1101 OxF 1111 OxB 1011 0 3 0011 Almost Empty and Empty Almost Empty but not Empty In between Almost Empty and Almost Full Almost Fu
39. ble Channel 4 Interrupt on Sync Detected D13 Enable Channel 4 Interrupt on Tx FIFO Almost Empty D14 Enable Channel 4 Interrupt on Rx FIFO Almost Full D15 Enable Channel 4 Interrupt on USC Request Interrupt Note T in any of these positions will enable corresponding interrupt source to perform PMC interrupt 0 in any of these positions will disable the corresponding interrupt source from performing PMC interrupt 2 1 25 INTERRUPT STATUS LOC 0x64 DO Status on Channel 1 Interrupt for Sync Detected Di Status on Channel 1 Interrupt for Tx FIFO Almost Empty D2 Status on Channel 1 Interrupt for Rx FIFO Almost Full D3 Status on Channel 1 Interrupt for USC Request Interrupt D4 Status on Channel 2 Interrupt for Sync Detected D5 Status on Channel 2 Interrupt for Tx FIFO Almost Empty D6 Status on Channel 2 Interrupt for Rx FIFO Almost Full D7 Status on Channel 2 Interrupt for USC Request D8 Status on Channel 3 Interrupt for Sync Detected D9 Status on Channel 3 Interrupt for Tx FIFO Almost Empty D10 Status on Channel 3 Interrupt for Rx FIFO Almost Full D11 Status on Channel 3 Interrupt for USC Request Interrupt D12 Status on Channel 4 Interrupt for Sync Detected D13 Status on Channel 4 Interrupt for Tx FIFO Almost Empty D14 Status on Channel 4 Interrupt for Rx FIFO Almost Full D15 Status on Channel 4 Interrupt for USC Request Interrupt Note 1 in any of these positions will indicate that the corresponding source
40. cable to go from a tri state condition to a loaded condition D4 Channel 2 Enable Drive Upper Writing a 1 to this bit will turn on the transmitter for the Channel 2 Tx on the upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a driven state D5 Channel 2 Enable Drive Lower Clk Writing 1 to this bit will turn on the transmitter for the Channel 2 Tx Clk on the lower portion of the cable This will cause this signal on the cable to go from a tri state condition to a driven state D6 Channel 2 Enable Receive Upper Clk Writing a 1 to this bit will turn on the receiver for the Channel 2 Rx clock on the upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a loaded condition D7 Channel 2 Enable Receive Lower Clk Writing a 1 to this bit will turn on the receiver for the Channel 2 Rx clock on the lower portion of the cable This will cause this signal on the cable to go from a tri state condition to a loaded condition D8 Channel 3 Enable Drive Upper Clk Writing a 1 to this bit will turn on the transmitter for the Channel 3 Tx on the upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a driven state D9 Channel 3 Enable Drive Lower Writing a 1 to this bit will turn on the transmitter for the Channel 3 Tx Clk on the lower portion of the c
41. d as follows BRGO Output Output RxC Pin TxC Pin HIGH LOC 0XN11 BRGO Clock Source encoded as follows 00 01 10 1 CTRO Output CTR1 Output RxC Pin TxC Pin Clock Source encoded as follows 00 01 10 1 CTRO Output Output RxC Pin TxC Pin CRTO Clock Source encoded as follows 00 01 10 11 BRGO Output Output RxC Pin TxC Pin Clock Source encoded as follows 00 01 10 11 Disabled Disabled RxC Pin TxC Pin 2 3 11 HARDWARE CONFIGURATION REGISTER 2 3 11 1 D1 DO D2 3 D5 D6 7 Low LOC 0xN12 RW RW BRGO Enable BRGO Single Cycle Continuous Rx ACK Pin Control encoded as follows 00 01 10 11 3 State Output Rx Acknowledge Input Output 0 Output 1 BRGI Enable BRGI Single Cycle Continuous Tx ACK Pin Control encoded as follows 00 01 10 3 State Output Tx Acknowledge Input Output 0 2 3 11 2 D DI 02 03 D5 D6 7 1 Output 1 HIGH LOC 0 13 DPLL Mode encoded as follows 00 Disabled 01 NRZ NRZI 10 Biphase Mark Space 11 Biphase Level DPLL Clock Rate encoded as follows 00 32x Clock Mode 01 16x Clock Mode 10 8x Clock Mode 11 Reserved RW Accept Code Violations RW Rate Match DPLL CTRO CTRO Clock Rate encoded as follows 00 32x Clock Mode 01 16 10 8x Clock Mode 11 4x Clock Mode 2 3 12 INTERRUPT VECTOR REGI
42. e 0 Burst Enable D25 Extra Long Load from Serial Enable D26 Expansion ROM Space Burst Enable Unused D27 Direct Slave PCI Write Mode D28 31 PCI Target Retry Delay Clocks 3 3 REGISTERS The Runtime registers consist of mailbox registers doorbell registers and a general purpose control register The mailbox and doorbell registers serve no purpose on the PCIIPMC HPDI22 TABLE 3 3 1 RUNTIME REGISTERS Register Name Value after Writable Reset Mailbox Register 3 Unused Y Y Y Y 40 E EARS 0x40 4 0x60 Ox7C 3 3 1 INTERRUPT CONTROL STATUS PCI 0X68 RESET 0x00000000 DO D1 D2 D3 D7 4 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D31 28 Enable Local bus LSERR Unused Enable Local bus LSERR on a PCI parity error Unused Generate PCI Bus SERR Mailbox Interrupt Enable Unused Reserved PCI Interrupt Enable PCI Doorbell Interrupt Enable Unused PCI Abort Interrupt Enable PCI Local Interrupt Enable Local Interrupt must be enabled for USC FIFO interrupts Retry Abort Enable Unused PCI Doorbell Interrupt Status PCI Abort Interrupt Status PCI Local Interrupt Status Local Interrupt Output Enable Local Doorbell Interrupt Enable Unused Local DMA Channel 0 Interrupt Enable Local DMA Channel Interrupt Enable Local Doorbell Interrupt Status DMA Chann
43. el 0 Interrupt Status DMA Channel Interrupt Status BIST Interrupt Status A 0 indicates a Direct Master was bus master during a Master or Target abort A 0 indicates that DMA CHO was bus master during a Master or Target abort A 0 indicates that DMA was bus master during a Master or Target abort A 0 indicates that a Target A bort was generated by the PCI9080 after 256 consecutive Master retries to a Target PCI Mailbox 3 0 Write Status 3 3 2 SERIAL EEPROM CONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER PCI 0X6C RESET 0X0X001767E D3 0 D7 4 D11 8 D15 12 D16 D17 D23 18 D24 D25 D26 D27 D28 D29 D30 D31 PCI Read Command Code for DMA PCI Write Command Code for DMA PCI Memory Read Command Code for Direct Master Unused PCI Memory Write Command Code for Direct Master Unused General Purpose Output Unused General Purpose Input Unused Reserved Serial EEPROM clock for Local or PCI bus reads or writes to Serial EEPROM Serial EEPROM chip select Write bit to serial EEPROM Read serial EEPROM data bit Serial EEPROM present Reload Configuration Registers PCI Adapter Software Reset Local Init Status A l indicates Local initialization done 3 3 3 PCI PERMANENT CONFIGURATION ID REGISTER PCI 0X70 RESET 0X10B59080 D15 0 Permanent Vendor ID 0x10B5 D31 16 Permanent Device ID 0x9080 3 3 4 PCI PERMANENT REVISION ID REGISTER PCI 0x74 D7 0 Permanent Revision ID
44. er for the Channel 4 Rx clock on the lower portion of the cable This will cause this signal on the cable to go from a tri state condition to loaded condition 2 1 4 CHANNEL 1 TXALMOST LOC 0x10 00 31 Channel I Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel 0 15 Used for the Almost Empty Flag D16 31 Used for the Almost Full Flag 2 1 5 CHANNEL 1 RX ALMOST LOC 0x14 00 31 Channel Rx Almost Data The data in this register is used for programming the Almost Flags of the Rx FIFOs for this channel D0 15 Used for the Almost Empty Flag D16 31 Used for the Almost Full Flag 2 1 6 CHANNEL 1 FIFO LOC 0x18 D0 7 Channel FIFO Data The FIFOs are setup in a way that the Rx FIFO and the Tx FIFO are located at the same address A write to this address will be directed toward the Tx FIFO and a read from this address will be directed toward the Rx FIFO D8 31 Reserved 2 1 7 CHANNEL 1 CONTROL STATUS LOC 0x1C DO Reset Channel Tx FIFO Pulsed Writing 1 to this bit will cause channel 1 Tx FIFOs to be reset If the channel 1 Tx Almost register is not a value of 0x00000000 then this will also cause the channel 1 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse th
45. erefore it is not necessary for software to return to clear this bit it will clear itself DI Reset Channel 1 Rx FIFO Pulsed Writing a 1 to this bit will cause the channel 1 Rx FIFOs to be reset If the channel 1 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 1 Rx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself D2 Enable the Channel 1 Transmitters for the Upper portion of the cable will drive the cable Writing a 1 to this bit will turn on the transmitters for the Channel 1 upper portion of the cable The signals that are turned on are the Channel 1 TxD and Channel 1 CTS on the upper portion of the cable This will cause these signals on the cable to go from a tri state condition to a driven state D3 Enable the Channel 1 Transmitters for the Lower portion of the cable will drive the Cable Writing a 1 to this bit will turn on the transmitters for the Channel 1 lower portion signals that are turned on are the Channel 1 TxD and Channel 1 CTS on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to a driven state D4 Enable the Channel 1 Receivers for the Upper portion of the
46. erved 01101 Load Rx Character Count 01110 Load Tx Character Count 01111 Reserved 10000 Load TCO 10001 Load TC1 10010 Load amp 10011 Select Serial Data LSB First 10100 Select Serial Data MSB First 10101 Select Straight Memory Data 10110 Select Swapped Memory Data 10111 Reserved 11000 Rx Purge 11001 Reserved 11010 Reserved 11011 Reserved 11100 Reserved 11101 Reserved 11110 Reserved 11111 Reserved Selected upon reset 2 3 3 CHANNEL MODE REGISTER CMR 2 3 3 1 Low LOC 0 02 00 03 WO Receiver Mode encoded as follows 04 07 2 3 3 2 D4 7 0000 Asynchronous 0001 External Synchronous 0010 Isochronous 0011 Asynchronous with CV 0100 Monosync 0101 Bisync 010 HDLC 0111 Transparent Bisync 1000 1001 802 3 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Rx Submode 3 0 HIGH LOC 0xN03 Transmitter Mode encoded as follows 0000 Asynchronous 0001 Reserved 0010 Isochronous 0011 Asynchronous with CV 0100 0101 Bisync 010 HDLC 0111 Transparent Bisync 1000 1001 802 3 1010 Reserved 1011 Reserved 1100 Slaved Monosync 1101 Reserved 1110 HDLC Loop 1111 Reserved Tx Submode 3 0 2 3 4 CHANNEL COMMAND STATUS REGISTER CCSR 2 3 4 1 D0 Di D2 4 Low LOC 0 04 RO RxACK RO TxACK HDLC Tx Last Character Length encoded as follows 000 8 bits 001 1 bit 18 D5 D6 D7
47. es to 32k bytes Larger FIFO depth is important for faster interfaces to reduce the risk of software overhead Standard configuration of the SIO4 contains 32k byte deep FIFOs 6 0 3 INTERFACE CABLE General Standards Corporation can provide an interface cable for the SIO4 board This cable is twisted pair for increased noise immunity Several standard cable lengths are offered or the cable length can be custom ordered to the user s needs Versions of the cable are available with connectors on both ends or the cable may be ordered with a single connector to allow the user to adapt the other end for a specific application Please consult factory for more information on cabling options and pricing 61 CUSTOM APPLICATIONS Although the 5104 board provides extensive flexibility to accommodate most user applications custom interfaces exist which may not exactly conform to the SIO4 interface standard General Standards Corporation has worked with many customers to provide customized versions based on the HPDI32 board Please consult our sales department with your specifications to inquire about a custom application PMC SIO4 User Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787
48. hannel 0 Local to PCI Almost Full COLPAF D15 12 DMA Channel 0 PCI to Local Almost Empty COPLAE D19 16 DMA Channel 1 PCI to Local Almost Full CIPLAF Unused D23 20 DMA Channel 1 Local to PCI Almost Empty CILPAE Unused D27 24 DMA Channel 1 PCI to Local Almost Full CILPAF Unused D31 28 DMA Channel 1 PCI to Local Almost Empty CIPLAE Unused D D D D D D MESSAGING QUEUE REGISTERS Messaging queue registers not used on the PCI PMC HPDI32 44 CHAPTER 4 PROGRAMMING 4 0 4 1 4 2 4 3 INTRODUCTION This section was written for the user who is attempting to write his her own device driver or would just like a better understanding of how the 5104 family of cards operates Some of the operations listed in this section may be performed by or differently from the same operation when using a General Standards provided device driver Please see the device driver documentation for specific differences RESETS Each serial communication channel of the SIO4 provides three reset sources a transmit FIFO buffer reset a receive FIFO buffer reset and a Zilog Z16C30 reset Please note that performing a FIFO buffer reset while data is present in that FIFO will cause the data to be lost Also note since each Zilog Z16C30 chip contains two serial channels performing a Zilog reset to either channel will reset the entire chip For instance performing a Zilog reset on either channel 1 or channel 2 will reset the entire Z
49. has either performed a PMC interrupt or that the source for the interrupt is currently active thus could perform a PMC interrupt if enabled in the interrupt control register Whether or not the interrupt was performed depends on the interrupt control register If the corresponding bit in the interrupt control register is a 0 then the source has not performed a interrupt and is only indicating the current status of that source If the corresponding bit in the interrupt 15 control register is 1 then source has performed a PMC interrupt and has latched itself Writing a 1 to the respective bit in the interrupt status register clears the interrupt status bit A second interrupt will not occur until after that status bit has been cleared The interrupts are not queued hence each potential interrupt should be observed when identifying the source and clearing the status register Failure to do so could prevent any other interrupts from occurring SERIAL CONTROLLER REGISTERS IMPORTANT Write to Loc 0x100 and Loc 0x300 after every reset to confirm the USC address system Contact your local Zilog Representative for Data books and User manuals in reference to the Z16C30 USC Universal Serial Controller for a more detailed description of the following registers It is the advice of the design engineer of this product that both books should be obtained by any persons desiring to design using this product See Related Publicati
50. hat a parity error is ignored and operation continues A indicates that parity checking is enabled D7 Wait Cycle Control Controls whether the device does address data stepping A 0 indicates the device never does address data stepping Note Hardcoded to 0 D8 SERR Enable A allows the device to drive SERR line D9 Fast Back to Back Enable Indicates what type of fast back to back transfers a Master can perform on the bus A indicates fast back to back transfers can occur to any agent on the bus A 0 indicates fast back to back transfers can only occur to the same agent as the previous cycle D15 10 Reserved 3 1 3 PCI STATUS REGISTER OFFSET 0X06 RESET 0 0280 D5 0 D6 D8 D10 9 D11 Reserved User Definable Features Supported A indicates UDF are supported Note User Definable Features are Not Implemented Fast Back to Back Capable indicates the adapter can accept fast back to back transactions Master Data Parity Error Detected 1 indicates the following three conditions are met 1 PCI9080 asserted PERR itself or observed PERR asserted 2 PCI9080 was bus master for the operation in which the error occurred 3 Parity Error Response bit in the Command Register is set Writing a 1 to this bit clears the bit DEVSEL Timing Indicates timing for DEVSEL assertion A value of 01 indicates a medium decode Note Hardcode to 01 Target Abort A
51. ilog chip clearing all registers for both channel 1 and channel 2 Likewise performing a Zilog reset of either channel 3 or channel 4 will reset the second Zilog chip and clear all the registers for channel 3 and channel 4 FIFO ALMOST FLAGS The FIFO buffer chips utilized on the SIO4 provide a means by which the user can determine the approximate amount of data in the FIFO This mechanism is called FIFO almost full and FIFO almost empty flags and these are programmable by the user Each serial communication channel provides two 32 bit registers for setting these values a TX FIFO Almost Register and an RX FIFO Almost Register Each of these registers if further broken up into two 16 bit portions where the value in the upper 16 bits D16 D31 is used to program the almost full FIFO flag and the value in the lower 16 bits DO D15 is used to program the FIFO almost empty flag The almost flags current status may be read from the respective channel s Control Status register These FIFO status bits are updated every 33 nanoseconds Each value in the corresponding portion of the almost register represents the number of bytes from each respective end of the FIFO Meaning a value of 0x00100010 in the FIFO almost register means that the FIFO almost flags will be programmed to trigger at a point 0x10 bytes from each end of the FIFO This means that the almost empty flag will be asserted when the FIFO has 0x10 1 bytes in it whereas the
52. in the same manner substituting the following parts Jumpers J4 for Channel 3 and J7 for Channel 4 Clock Selection 20 MHz F actory Jumper Field S ITXC Pin Installed L E Pin O Oscillator Ber ED 19 Zilog ChannelX Receive Clock 21 6C30 BO Serial Controller So Os 1 channel only shown Channel X Transmit Clock Channel X Upper Clock Channel X Upper Tx RX Clock CMOS Input CMOS Output RS422 485 Input Output R5422 485 Transceiver CMOS Input CMOS Output Channel X Lower T3wRX Clock RS422 485 Input Output Channel X Lower Tx RX Clock R5422 485 Transceiver Cable Connector Figure 5 4 2 Clock Jumpers Routing IRxData Pin ITxData Pin Zilog Z16C30 Serial Controller 1 channel only shown Channel X Receive Data Channel X Transmit Data Channel X Upper TxD RXD RS422 485 Input Output Channel X Upper TxD RxD CMOS Input CMOS Output R5422 485 Transceiver Channel X Lower TxD RxD RS422 485 Input Output Channel X Lower TxD RxD CMOS Input CMOS Output RS422 485 Transceiver Cable Connector Figure 5 4 2 Data Routing 49 FIGURE 5 4 2 CLOCK JUMPERS ROUTING DATA ROUTING DCD Pin CTSPin Zilog Z16C30 SerialController 1channelonly Channel X DCD Signal Channel X CTS Signal CMOSInput npu Outpul Ghannel XUpperCTS DCD CMOSOutput Input
53. ing a 1 to this bit will cause the channel 2 Tx FIFOs to be reset If the channel 2 Tx Almost register is not a value of 0x00000000 then this will also cause the channel 2 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Reset Channel 2 Rx FIFO Pulsed Writing a 1 to this bit will cause the channel 2 Rx FIFOs to be reset If the channel 2 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 2 Rx FIFOs almost flags to be programmed After setting this bit to a 1 itis the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself D2 Enable the Channel 2 Transmitters for the Upper portion of the cable will drive the cable Writing 1 to this bit will turn on the transmitters for the Channel 2 upper portion of the cable The signals that are turned on are the Channel 2 TxD and Channel 2 CTS on the D3 D5 D7 D8 D10 D11 D12 D13 D14 D15 upper portion of the cable This will cause these signals on the cable to go from a tri state c
54. l turn on the receivers for the Channel 4 upper portion of the cable The signals that are turned on are the Channel 4 RxD and Channel 4 DCD on the upper portion of the cable This will cause these signals on the cable to go from a tri state condition to a loaded condition Enable the Channel 4 Receivers for the Lower portion of the cable will load the cable Writing a 1 to this bit will turn on the receivers for the Channel 4 lower portion of the cable The signals that are turned on are the Channel 4 RxD and Channel 4 DCD on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to a loaded condition Reserved Reset Zilog for Channel 3 4 Pulsed Writing 1 to this bit will cause the channel 3 4 Zilog Z16C30 USC to be reset This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Note After power up and after any reset to this component the next access to channel 3 or channel 4 USC must be a write of 0x00 to offset 0x00 of channel 3 USC Channel 4 Tx FIFO Empty TRUE 0 Channel 4 Tx FIFO Almost Empty TRUE 0 010 Channel 4 Tx FIFO Almost Full TRUE 0 D11 Channel 4 Tx FIFO Full TRUE 0 D12 Channel 4 Rx FIFO Empty TRUE 0 D13 Channel 4 Rx FIFO Almost Empty TRUE 0 D14 Channel 4 Rx FIFO Almost Full TRUE 0 D15 Channel 4 Rx FIFO Full TRUE 0 The FIFO status flags are active l
55. ll but not full Almost Full and Full 2 1 16 CHANNEL4 ALMOST LOC 0x40 D0 31 0 15 Channel 4 Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel is used for the Almost Empty Flag D16 31 is used for the Almost Full Flag 2 1 17 CHANNEL 4 Rx ALMOST LOC 0x44 00 31 Channel 4 Rx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel is used for the Almost Empty Flag D16 31 is used for the Almost Full Flag 0 15 2 1 18 CHANNEL 4 FIFO LOC 0x48 D0 7 Channel 4 FIFO Data The FIFOs set in way that the Rx FIFO and Tx FIFO are located at same address A write to this address will be directed toward the Tx FIFO and a read from this address will be directed toward the Rx FIFO 2 1 19 CHANNEL 4 CONTROL STATUS LOC 0x4C DO D1 D2 D3 D5 D7 D8 D9 Reset Channel 4 Tx FIFO Pulsed Writing a 1 to this bit will cause the channel 4 Tx FIFOs to be reset If the channel 4 Tx Almost register is not a value of 0x00000000 then this will also cause the channel 4 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it
56. ndalone loop back test This also allows two SIO4 boards to be connected directly or two channels to be connected directly using standard cabling options by simply configuring the transmitter and receiver pins correctly Figure 5 4 2 shows the overall operation for the Upper Lower Clock and Data signals The clock enables are controlled fromthe GSC Clock Control Register Section 2 1 2 and the data signals are enabled in the GSC Channel Control Status Registers starting at Section 2 1 5 Even though the clock and data lines have separate enables they will typically be set the same For example if you want to transmit on the Channel 1 Upper signals and receive on the Channel 1 Lower signals the Upper Tx Clock and Upper Tx Data will be enabled for transmit and the Lower Rx Clock and Lower Rx Data should be enabled for receive CHAPTER 5 HARDWARE CONFIGURATION 5 0 5 1 5 2 THE ON BOARD MASTER amp TRANSMIT RECEIVE CLOCKS The oscillator U1 is used for generating a transmit receive clock It is factory installed at 20 MHz and may be changed to accommodate different baud rates Any standard 8 or 14 pin dip oscillator will fit into the socket of Ul EEPROM JUMPER J12 The jumper J12 is a 2x3 header These jumpers are used for manufacturer uses only It should not be necessary for any users of the PMC SIO4 to perform any operations involving these jumpers CABLE INTERFACE CONNECTIONS There is a 68 pin DSUB user I O interface c
57. ondition to a driven state Enable the Channel 2 Transmitters for the Lower portion of the cable will drive the Cable Writing a 1 to this bit will turn on the transmitters for the Channel 2 lower portion of the cable The signals that are turned on are the Channel 2 TxD and Channel 2 CTS on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to a driven state Enable the Channel 2 Receivers for the Upper portion of the cable will load the cable Writing a 1 to this bit will turn on the receivers for the Channel 2 upper portion of the cable The signals that are turned on are the Channel 2 RxD and Channel 2 DCD on the upper portion of the cable This will cause these signals on the cable to go from a tri state condition to a loaded condition Enable the Channel 2 Receivers for the Lower portion of the cable will load the cable Writing a 1 to this bit will turn on the receivers for the Channel 2 lower portion of the cable The signals that are turned on are the Channel 2 RxD and Channel 2 DCD on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to a loaded condition Reserved Reset Zilog for Channel 1 2 Pulsed Writing a 1 to this bit will cause the channel 1 2 Zilog Z16C30 USC to be reset This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear it
58. onnector PLUG mounted soldered to the front edge of the board Ref Des PA2 for row A amp PB2 for row B The part number is PSOE 068PI SRI TG manufacturer Robinsen Nugent The mating part number is PSOE68 S TG This cable is used for all 4 channels See Table 4 2 1 below for pin out TABLE 5 2 1 USER CABLE PIN OUT Channel 1 Lwr Cable TX RX Clk 6 Channel Lwr Cable TX RX Cik 40 Channel I Cable TXD RXD 18 Channel Upr Cable TXD RXD 42 Channel I Cable CTS DCD 9 Channel 3 Upr Cable CTS DCD 45 Noconneet 6 Noconmect 0 No connect No connect 53 BOARD LAYOUT The following figure is a drawing of the physical components of the PMC SIO4 Altera Flex Zilog EPF6016QC208 3 Z16C3010VSC PLX Zilog PCI9080 Z16C3010VSC FIGURE 5 4 1 BOARD LAYOUT 54 THE ZILOG CLOCK SELECT JUMPERS J3 J4 J7 amp 18 The purpose of these jumpers is to select where the Zilog clock comes from or goes to If the Zilog clock uses the on board transmit receive clock or the cable clock then the jumpers should be installed If the Zilog is going to generate an output clock to the cable then some of the jumpers should not be installed The Zilog Clock Select Jumpers are 2x8 the pin out is shown below there are individual jumpers for each channel see Figure 4 3 1 below for a graphical description of how Channels amp 2 are configured 48 Note Channels 3 amp 4 are implemented
59. ons section of this document for address of Zilog Note In the following register addresses n stands for Channel Number 2 3 1 USC REGISTERS 2 3 1 1 CHANNEL 1 USC LOC 0x100 0 17 0 7 Channel I USC Data Zilog Data Bus See Serial Controller Registers 2 3 1 2 CHANNEL 2 USC LOC 0 200 0 27 D0 7 Channel 2 USC Data Zilog Data Bus See Serial Controller Registers 2 3 1 3 CHANNEL3 USC LOC 0x300 0x37E 0 7 Channel USC Data Zilog Data Bus See Serial Controller Registers 2 3 1 4 CHANNEL 4 USC LOC 0x400 TO 0x47E 0 7 Channel 4 USC Data Zilog Data Bus See Serial Controller Registers 2 3 2 CHANNEL COMMAND ADDRESS REGISTER CCAR Same format for Channels 0 3 USC Control Registers 2 3 2 1 Low LOC 0xN00 D0 WO Upper Lower Byte Select 01 05 WO Address 4 0 D6 WO Byte Word Access D7 WO DMA Continue The contents of this register should always be set to 0x00 for this product 2 3 2 2 HIGH LOC 0 01 00 01 WO Mode Control encoded as follows D9 D8 0 0 Normal Operation 0 1 Auto Echo 1 0 External Local Loop back 1 1 Internal Local Loop back D2 Channel Reset D3 7 WO Channel Command encoded as follows D11 as the LSB 00000 Null Command 00001 Reserved 00010 Reset Highest IUS 00011 Trigger Channel Load DMA 00101 Trigger Rx DMA 00110 Trigger Tx DMA 00111 Trigger Rx amp Tx DMA 00100 Reserved 00100 Rx FIFO Purge 00101Tx FIFO Purge 01011 Rx amp Tx FIFO Purge 01100 Res
60. or detection Tx underrun INTERRUPTS Interrupts will be provided for the following conditions e DMA Complete N Sync word detected Tx FIFO almost empty Rx FIFO almost full Exited Hunt IdleRcvd Break Abort RxBound Abort ParityError RxOverrun Plus many others Q CHAPTER 2 LOCAL SPACE REGISTERS 2 0 REGISTER MAP TABLE 2 0 1 PMC SIO4 REGISTER ADDRESS MAP Address after Programming RW 0x04 RW 0x08 LA N N 0x10 0x14 0x18 3 LA N e N i LA N e N Go NIN LA 5 Ox R 0400 D8 see Zilog see Zilog 0x200 Reference Data Book 040 0 8 RO read only WO write only RW read write capability BD Bit Dependent LA 5 We N Q Q D S We N P 99 N LA 5 Go Go Go NINN LA N R R R R LA N E D D D D D D D D D D D D32 D D D D D D D D D D D RW RW RW RW RW RW RW RW W W W W W W W W W W W 99 5 A 2 1 BITMAP FOR LOCAL SPACE REGISTERS When writing to the registers all reserved bits should be set to 0 for future compatibility In addition the value read from a reserved bit will be indeterminate 2 1 0 FIRMWARE REVISION LOC 0x00 D0 31 0 00000000 Original Revision Board Control loc 0x04 D2 0 210 000
61. ow indicators of the current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates that it is not true There are only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows OxC 1100 Almost Empty and Empty OxD 1101 Almost Empty but not Empty OxF 1111 In between Almost Empty and Almost Full OxB 1011 Almost Full but not full 0x3 0011 Almost Full and Full 2 1 20 CHANNEL 1 SYNC DETECT LOC 0x50 D0 7 Channel Sync Detected Data The data in this register is used to watch the Rx data as it is being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to the interrupt logic An actual interrupt to the host will only occur if this interrupt source is enable in the interrupt control register 2 1 21 CHANNEL 2 SYNC DETECT LOC 0x54 00 7 Channel 2 Sync Detected Data The data in this register is used to watch the Rx data as it is being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to the interrupt logic Anactual interrupt to the host will only occur if this interrupt source is enable in the interrupt control register 2 1 22 CHANNEL 3 SYNC DETECT LOC 0X58 00 7 Channel 3 Sync Detected Data The data
62. self Note that after power up and after any reset to this component the next access to channel 1 or channel 2 USC must be a write of 0 00 to offset 0x00 of channel 1 USC Channel 2 Tx FIFO Empty TRUE 0 Channel 2 Tx FIFO Almost Empty TRUE 0 Channel 2 Tx FIFO Almost Full TRUE 0 Channel 2 Tx FIFO Full TRUE 0 Channel 2 Rx FIFO Empty TRUE 0 Channel 2 Rx FIFO Almost Empty TRUE 0 Channel 2 Rx FIFO Almost Full TRUE 0 Channel 2 Rx FIFO Full TRUE 0 The FIFO status flags are active low indicators of the current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates that it is not true There are only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows OxC 1100 Almost Empty and Empty xD 1101 Almost Empty but not Empty OxF 1111 In between Almost Empty and Almost Full OxB 1011 Almost Full but not full 0x3 0011 Almost Full and Full 2 1 12 CHANNEL 3 TXALMOST LOC 0x30 D0 31 Channel 3 Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel 00 15 Used for the Almost Empty Flag 10 D16 31 Used for the Almost Full Flag 2 1 13 CHANNEL 3 RX ALMOST LOC 0x34 D0 31 Channel 3 Rx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this ch
63. ser is familiar with the PCI bus interface specification In an effort to avoid redundancy this manual relies on data books other manuals and specifications as indicated in the related publication section RELATED PUBLICATIONS EIA Standard for the RS 422A Interface EIA order number EIA RS 422A Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC Sponsored by the Bus Architecture Standards Committee of the IEEE Computer Society P1386 1 Draft 2 0 April 4 1995 Sponsor Ballot Draft For questions or comments regarding this draft please contact either the chair or draft editor of this proposed standard Wayne Fisher PMC Chair 2001 Logic Drive San Jose CA 95124 3456 USA Ph 408 369 6250 Fax 408 371 3382 Em wfisher fci com Dave Moore PMC Draft Editor Digital Equipment Corporation 146 Main Street MLO11 4 U32 Maynard MA 01754 2571 USA Ph 408 493 2257 Fax 408 493 0652 E mail moore eng pko dec com PCI Local Bus Specification Revision 2 1 June 1 1995 Questions regarding the PCI specification should be forwarded to PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX Zilog User s Manual and Product Specifications Databook for the Z16C30 USC requests should be forwarded to ZILOG Inc 210 East Hacienda Ave Campbell CA 95008 6600 408 370 8000 TABLE OF CONTENTS CHAPTER 1 INTROD
64. ss for Direct Master to PCI Memory IO CFG 0x00000000 Unused PCI Base Address Re map for Direct Master to PCI Unused 0 00000000 PCI Configuration Address Register for Direct Master to PCI 0x00000000 IO CFG Unused Range for PCI to Local Address Space Unused 0x00000000 Local Base Address Remap for PCI to Local Address Space 1 0x00000000 Unused 38 OxF4 0 174 j 0 178 Local Bus Region Descriptor Space 1 for PCI to Local Accesses 0 00000000 Unused 3 2 1 LOCAL ADDRESS SPACE 0 RANGE REGISTER FOR PCI TO LOCAL BUS PCI 0x00 RESET OXFFFFF000 D0 Memory Space Indicator A 0 indicates register maps into Memory space D2 1 Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space D3 Prefetchable A 0 indicates reads are not prefetchable D31 4 Specifies which PCI address bits will be used to decode a PCI access to Local Address Space 0 A 1 indicates bit is included in address decode Local Address Space 0 value OXFFFFF000 maps 4kbyte range Since entire Local Address Space can be mapped into 4kb range the remap register is not used 3 2 2 MODE ARBITRATION REGISTER PCI 0x08 D7 0 Local bus Latency Timer Unused D8 15 Local bus Pause Timer Unused D16 Local bus Latency Timer Enable Unused D17 Local bus Pause Timer Enable Unused 018 Local bus Enable Unused D20 19 DMA Channel Priorit
65. turn to clear this bit it will clear itself Enable the Channel 3 Transmitters for the Upper portion of the cable will drive the cable Writing a 1 to this bit will turn on the transmitters for the Channel 3 upper portion of the cable The signals that are turned on are the Channel 3 TxD and Channel 3 CTS on the upper portion of the cable This will cause these signals on the cable to go from a tri state condition to a driven state Enable the Channel 3 Transmitters for the Lower portion of the cable will drive the Cable Writing a 1 to this bit will turn on the transmitters for the Channel 3 lower portion of the cable The signals that are turned on are the Channel 3 TxD and Channel 3 CTS on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to a driven state Enable the Channel 3 Receivers for the Upper portion of the cable will load the cable Writing a 1 to this bit will turn on the receivers for the Channel 3 upper portion of the cable The signals that are turned on are the Channel 3 RxD and Channel 3 DCD on the upper portion of the cable This will cause these signals on the cable to go from a tri state condition to a loaded condition Enable the Channel 3 Receivers for the Lower portion of the cable will load the cable D7 D8 D10 D11 D12 D13 D14 D15 Writing 1 to this bit will turn on the receivers for the Channel 3 lower portion of the ca
66. uest DMA on Serial Channel 3 Rx FIFO Almost Full Hold until Serial Channel 3 Rx FIFO Almost Empty Request DMA on Serial Channel 3 Tx FIFO Almost Empty Hold until Serial Channel 3 Rx FIFO Almost Empty Request DMA on Serial Channel 4 Rx FIFO Almost Full Hold until Serial Channel 4 Rx FIFO Almost Empty 111 Request DMA on Serial Channel 4 Tx FIFO Almost Empty Hold until Serial Channel 4 Rx FIFO Almost Empty Serial Channel D31 7 Reserved 21 2 CLOCK CONTROL LOC 0X0C D0 15 Clock Controls for all 4 channels D0 Channel 1 Enable Drive Upper Writing a 1 to this bit will turn on the transmitter for the Channel Tx Clk on the upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a driven state Di Channel 1 Enable Drive Lower Writing a 17 to this bit will turn on the transmitter for the Channel I Tx Clk on the lower portion of the cable This will cause this signal on the cable to go from a tri state condition to a driven state D2 Channel 1 Enable Receive Upper Writing a 1 to this bit will turn on the receiver for the Channel 1 Rx clock on the upper portion of the cable This will cause this signal on the cable to go from a tri state condition to a loaded condition D3 Channel 1 Enable Receive Lower CIk Writing a 1 to this bit will turn on the receiver for the Channel 1 Rx clock on the lower portion of the cable This will cause this signal on the
67. us IE RW Status IE RW Transmit Data IE RW Transmit Status IE RW Receive Data RW Receive Status IE Command encoded as follows 2 3 14 2 D1 3 D4 D5 D6 D7 00 01 10 11 Null Command Null Command Reset IE Set IE HIGH LOC 0 19 RW 000 001 010 011 100 101 110 11 VIS Level encoded as follows All All I O Status and Above Transmit Data and Above Transmit Status and Above Receive Data and Above Receive Status Only None MIE DLC NV VIS 2 3 15 DAISY CHAIN CONTROL REGISTER 2 3 15 1 DO D1 D2 D3 D4 D5 D6 7 2 3 15 2 D1 D2 D3 D5 D6 7 Low LOC 0XN1A RW RW RW RW RW RW Device Status INTERRUPT PENDING I O Status INTERRUPT PENDING Transmit Data INTERRUPT PENDING Transmit Status INTERRUPT PENDING Receive Data INTERRUPT PENDING Receive Status INTERRUPT PENDING INTERRUPT PENDING Command encoded as follows 00 01 10 11 Null Command Reset INTERRUPT PENDING and IUS Reset INTERRUPT PENDING Set INTERRUPT PENDING HIGH RW LOC 0XN1B RW Device Status IUS RW I O Status IUS RW Transmit Data IUS RW Transmit Status IUS RW Receive Data IUS RW Receive Status IUS IUS Command encoded as follows Null Command Null Command 10 Reset IUS 11 Set IUS 2 3 16 MISCELLANEOUS INTERRUPT STATUS REGISTER MISR 2 3 16 1 DO D1 D2 D3 D4 D5 D6 D7 2 3 16 2 DO D1 D2 D3
68. will clear itself Reset Channel 4 Rx FIFO Pulsed Writing a 1 to this bit will cause the channel 4 Rx FIFOs to be reset If the channel 4 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 4 Rx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Enable the Channel 4 Transmitters for the Upper portion of the cable will drive the cable Writing a 1 to this bit will turn on the transmitters for the Channel 4 upper portion of the cable The signals that are turned on are the Channel 4 TxD and Channel 4 CTS on the upper portion of the cable This will cause these signals on the cable to go from a tri state condition to a driven state Enable the Channel 4 Transmitters for the Lower portion of the cable will drive the Cable Writing a 1 to this bit will turn on the transmitters for the Channel 4 lower portion of the cable The signals that are turned on are the Channel 4 TxD and Channel 4 CTS on the lower portion of the cable This will cause these signals on the cable to go from a tri state condition to a driven state Enable the Channel 4 Receivers for the Upper portion of the cable will load the cable Writing a 1 to this bit wil
69. y 00 Rotational priority 01 Channel 2 priority 10 Channel 1 priority 11 Reserved D21 Local bus direct slave give up bus mode A value of 1 indicates local bus will be released when PCI9080 write FIFO empty or read FIFO full D22 Direct slave LLOCKo Enable Unused D23 PCI Request Mode D24 PCI Rev 2 1 Mode D25 PCI Read No Write Mode D26 PCI Read with Write Flush Mode D27 Gate the Local Bus Latency Timer with BREQ Unused D28 PCI Read No Flush Mode D29 Reads Device Vendor ID or SubDevice Sub Vendor ID D31 30 Reserved 3 2 3 BIG LITTLE ENDIAN DESCRIPTOR REGISTER PCI 0x0C Since local bus is little endian all bits should be left zero 3 2 4 LOCAL ADDRESS SPACE 0 EXPANSION ROM BUS REGION DESCRIPTOR REGISTER PCI 0x18 RESET 0x40030143 D1 0 Memory Space 0 Local Bus Width 11 indicates 32 bit local bus D5 2 Memory Space 0 Internal Wait States A 0 indicates no wait states required D6 Memory Space 0 Ready Input Enable A 1 indicates Local Ready input enabled D7 Memory Space 0 Bterm Input Enable Unused D8 Memory Space 0 Prefetch Disable Unused D9 Expansion ROM Space Prefetch Disable Unused D10 Read Prefetch Count Enable Unused D14 11 Prefetch Counter Unused D15 Reserved D17 16 Expansion ROM Space Local Bus Width Unused D21 18 Expansion ROM Space Internal Wait States Unused D22 Expansion ROM Space Ready Input Enable Unused D23 Expansion ROM Space Bterm Input Enable Unused D24 Memory Spac

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