Home

8X9X USER`S MANUAL

1. Aje NORMALIZE MNEMONIC OPCODE BYTES STATE TIMES o 3 NOTES 6 This instruction takes 2 states to pull RESET low then holds it low for at least one state time to initiate a reset The reset takes 13 states at which time the program restarts at location 2080H 7 Execution will take at least 8 states even for O shift 8 State times shown for 16 bit bus 2 54 intel 8X9X HARDWARE DESIGN INFORMATION 11 8 SFR Summary A D Result LO 02H A D Command 02H CHANNEL SELECTS WHICH OF THE 8 ANALOG INPUT CHANNELS IS TO BE CHANNEL NUMBER CONVERTED TO DIGITAL FORM STATUS A D CURRENTLY IDLE 1 CONVERSION IN PROCESS GO INDICATES WHEN THE CONVERSION IS TO BE INITIATED GO 1 MEANS START NOW GO 0 MEANS THE CONVERSION IS INITIATED BY THE HSO UNIT AT A SPECIFIED TIME 270246 53 X X A D RESULT LEAST SIGNIFICANT 2 BITS SPCON SPSTAT 11H BIT1 BITO SPECIFY THE MODE O0zMODEO 10 MODE 2 01 1 11 MODE 5 PEN ENABLE THE PARITY FUNCTION REN ENABLES THE RECEIVE FUNCTION TB8 PROGRAMS THE 9TH DATA BIT IS THE TRANSMIT INTERRUPT FLAG RI IS THE RECEIVE INTERRUPT FLAG IS THE 9TH DATA RECEIVED NOT PARITY RPE IS THE PARITY ERROR INDICATOR 1F PARITY ACTIVE 270246 54 270246 50 HSI Mode 03H gt 5 5 2 1 0 MO
2. mr e S bseAtmemgst m o EwbeAmempst 0 ___ E E E ietshi imsb gt id erga I II 2010H NOTES 1 If the mnemonic ends a byte operation is performed otherwise a word operation is done Operands D B and must conform to the alignment rules for the required operand type D and B are locations in the register file A can be located anywhere in memory 5 Offset is a 2 s complement number 6 Specified bit is one of the 2048 bits in the register file 7 The L Long suffix indicates double word operation 8 Initiates a Reset by pulling RESET low Software should re initialize all the necessary registers with code starting at 2080H 9 The assembler will not accept this mnemonic 1 24 intel 3 5 Software Standards and Conventions For a software project of any size it is a good idea to modularize the program and to establish standards which control the communication between these mod ules The nature of these standards will vary with the needs of the final application A common component of all of these standards however must be the mechanism for passing parameters to procedures and returning re sults from procedures In the absence of some overrid ing consideration which prevents their use it is s
3. _____ DNE PC 8 bit offset Dec DecB __ 1 1 7 NEG NEGB 1 0 0 0 O 1 2 ________ T De bD t e NOT NOTS _____ D j 7 9 9 ___ omen J 1 1 o o o SHL SHLB SHLL 2 msb wr 7 SHR SHRB SHRL 2 0 gt msb i e SHRA SHRAB SHRAL 2 gt msb isp 7 PSST i ee I CEC _________ 0 FemvT RST o lt 200 0 0 0 0 0 0 8 D 0 J OiebeAlltempsi eo E 0 J EnmbeAlitemps lt ___ c ______ __ en mI I II SP SP 2 5 lt lt 2010H NOTES 1 If the mnemonic ends in B a byte operation is performed otherwise a word operation is done Operands D B and A must conform to the alignment rules for the required operand type D and B are locations in the Register File can be located anywhere in memory 5 Offset is a 2 s complement number 6 Specified bit is one of the
4. 4 7m 5 12 2 3 vn 4 5 812 LDBSE 2 3 4 3 4 en 712 4 5 712 LDBZE 2 jAC 3 4 3 4 3 er 712 AF 4 en 5 712 STACK OPERATIONS internal stack pusu 11 lt 2 s s 2 uis 2 i216 3 1216 11 2 12 2 mois 2 5 1428 4 1418 eusar poe Joler 9 1 L STACK OPERATIONS external stack PUSH 2 12 3 12 2 1519 2 1620 5 1519 1620 eor 2 14 1 2 120 2 1620 1620 4 16720 ros pop e pore TI FIE JUMPS AND CALLS MNEMONIC OPCODE BYTES STATES OPCODE BYTES STATES 3 13165 sme 299 2 s scar 29 2 136 wm ies 2 1 es mam 270246 64 NOTES Number of state times shown for internal external operands 2 The assembler does not accept this mnemonic The least significant 3 bits of the opcode are concatenated with the following 8 bits to form an 11 bit 2 s complement offset for the relative call or jump State times for stack located internal external
5. 2 ____ 2 4 4 010 LD LDB E __ a ee 2 lt AD 1e signa 34 oor E pM PoP ___ 1 52 2 PUSHF SP SP 2 SP lt PSW PSW 0000H 1 lt 0 sre 1 sume LPC BR indire 1 feat ELESEXS PC 11 bit offset EUN ETE RENE ee d E ER PC PC 16 bit offset RET 0 PC SP SP e SP J amp ondWonay 1 PC lt lt PC 5 x CN E 5 1 the mnemonic ends in a byte operation is performed otherwise word operation is done Operands D B and A must conform to the alignment rules for the required operand type D and B are locations in the register file A can be located anywhere in memory 2 D D 2 are consecutive WORDS in memory D is DOUBLE WORD aligned 3 D D 1 are consecutive BYTES in memory D is WORD aligned 4 Changes a byte to a word 5 Offset is a 2 s complement number intel MCS
6. 1 33 6 3 HSI Interrupts 1 33 6 4 HSI Status 1 33 CONTENTS PAGE 7 0 HIGH SPEED OUTPUTS 1 34 HSO 1 34 7 2 HSO Stat s LR 1 35 7 3 Clearing the HSO 1 35 7 4 Using Timer 2 with the HSO 1 35 7 5 Software Timers 1 36 8 0 ANALOG INTERFACE 1 36 8 1 Analog Inputs 1 36 8 2 A D Commands 1 37 8 3 A D Results 1 37 8 4 Pulse Width Modulation Output DA Pseud 1 38 8 5 PWM Using the HSO 1 39 9 0 SERIAL PORT 1 39 9 1 Serial Port Modes 1 39 9 2 Controlling the Serial Port 1 40 9 3 Determining Baud Rates 1 41 9 4 Multiprocessor Communications 1 42 10 0 1 0 PORTS 1 42 10 1 Input Ports 1 42 10 2 Quasi Bidirectional Ports 1 43 10 3 Output Ports 1 43 10 4 Ports and 4 15 1 43 11 0 AND CONTROL REGISTERS 1 44 11 1 Control Register 0 IOCO 1 44 11 2 1 O Control Register 1 IOC1 1 45 11 3 Status Register 0 1050 1 45 11 4 1 0 Status Register 1 IOS1 1 45 12 0 WATCHDOG TIMER 1 46 12 1 Software Protection Hints 1 46 12 2 Di
7. 8397BH 8397BH B395BH 8097BH 8097BH 8095BH 8797BH 8795BH 8797BH 8797JF 8798 8397 8397 8398 E E Ee E Transistor Count MTBF Calculations Device Type MOS Gates 8X9XBH 3 8 x 107 Device Hours 55 839XBH 879XBH 120 000 8X9XBH 1 7 X 107 Device Hours 70 C 809XBH 50 000 8X9XJF 5 2 X 106 Device Hours 55 MTBF data was obtained through calculations based upon the actu 839XJF 879XJF 2300 al average mede inter stress at 55 C and 70 C 809XJF 72 000 ambient Thermal Characteristics same for 8X9XJF and 8X98 Package Type oa seem wow zw 2 46 8X9X HARDWARE DESIGN INFORMATION 11 4 Package Diagrams SOF en RXD P2 1 1 5 B 2 pensez pnd 5 22222223 2 96 2 4 512 504 E 5 9 8765 4 3 2 1 68 67 66 65 64 63 62 61 HSi3 HS05 6 45 ACH4 PO 4 ACHS PO 5 10 5 60 L2 ADO P3 0 7 42 7 5 5 4 4 C 11 59 3 P3 1 8 41 2 7 7 ANGND C 12 58 3 4D2 P3 2 6 Veer 13 57 0 05 5 5 Vpp 14 E 2 56 AD4 P3 4 96 EXTINT P2 2 C 15 68 PIN 555 05 5 5 Vpe Am RESET C 16 PLCC 54 A06 P3 6 PWN P2 5 RXD P2 1 C 17 53 407 P3 7 TXD P2 0 C 18 52 3 08 4 0 WRH BHE E TOP VIEW 1 0 C 19 LOOKING DOWN ON 51 F3 A09 P4 1 AD15 P4 7
8. 2 22 6 2 Mode 1 Timings 2 22 6 3 Mode 2 and 3 Timings 2 23 7 0 BUS TIMING AND MEMORY INTERFACE 2 23 7 1 Bus Functionality 2 23 7 2 Timing Specifications 2 24 7 3 READY Line Usage 2 24 7 4INST LineUsage 2 27 CONTENTS PAGE 7 5 BUSWIDTH Pin Usage 2 27 7 6 Address Decoding 2 27 7 7 Port Reconstruction 2 30 8 0 NOISE PROTECTION TIPS 2 30 9 0 PACKAGING 2 30 10 0 USING THE EPROM 2 32 10 1 Power Up and Power Down 2 32 10 2 Reserved Locations 2 33 10 3 Auto Configuration Byte Programming Mode 2 35 10 4 Auto Programming Mode 2 36 10 4 1 Auto Programming Mode and the CCB PCCB 2 36 10 4 2 Gang Programming with the Auto Programming Mode 2 36 10 5 Slave Programming Mode 2 38 10 5 1 Slave Programming Commands 2 38 10 5 2 Gang Programming with the Slave Programming Mode 2 39 10 5 3 Slave Programming Mode and the CCB PCCB 2 39 10 6 Run Time Programming 2 39 10 6 1 Run Time Programming and the CCB PCCB 10 7 ROM EPROM Program Lock 2 41 10 7 1 Lock Features 2 41 10 7 2 ROM Dump Mode 2 42 10 8 Modified Quick Pulse ProgrammingTM Algorit
9. ADD ADB 3 __ ee 1 ApCc acB 2 0 ____ __ 2 ee SUB SUES 3 De tul sum suCB 2 lt 0 1 COO qs 5 J l 1 1 1 2 MUUMUU 3 pDra2 8 4 2 Se PMULE MULUB 3 50 0 eBt 2 D 2 lt remainder t 2 2 D amp D 1 AD 1 lt remainder T 3 Dv 2 bD 2 AD 2 lt Dvs 2 Oe DD 1 AD 1 lt remainder 7 2 D DadA 10 lt 4 4 0 0 puo __ 2 ____ XOR KORB 2 D D eio 4 4 0 0 La c snss iss __ 2 De AD 1e 34 Ds ee gp ec Shae Shy eA Te epe d c Ae ASP SP pedo PUSHF SP SP 2 SP lt PSW 0000H 0 lt lt 15 e sme 1 lt Peritos
10. 2 2 5 55 5555 x 9 1 15 S ad 44 9 sme 1 2 w u 9 1715 5 5 66 lt oo ALA AL ALAA ala elke 5 sanu sic EIS 8s 3IS S S SIS SIS S8 03115 9 SSDS S IRIRIZIR al SiS 3 A RSA zz x e ___ eklere 200240 elelsisixixisisxizizizis e e 0240 o lt 3009d0 4 5 45 15 6 4614 712 340940 DIRECT IMMEDIATE Eu lin DIVB 216131 es 5 6 61 ADD 8 0 OPCODES INSTRUCTION LENGTH AND STATE TIMES 272110 20 NOTES d In all cases the second byte of the de specifies the exact mode used If the second byte is even use Indirect or Short indexed If it is odd use Indirect or Long indexe instruction always specifies an even word location for the address referenced indexed and Indirect instructions have identical opcodes with Short indexed and Indirect modes respectively The Number of state times shown for internal externa
11. 3 and ICOO 5 control the resetting of Timer 2 Figure 23 shows the different ways of manipulating Timer 2 It is recommended that the IOCO register only be used once during power on reset to initialize the timers and pins followed by an HSO command 14 to clear Timer 2 internally or externally cleared by the T2RST or 1 0 pins T2RST is not available on the 8X98 Some 8X9XBH devices have errata associated with Timer 2 See the data sheets for more information 5 3 Timer Interrupts Both Timer 1 and Timer 2 can be used to trigger a timer overflow interrupt and set a flag in the I O Status Register 1 1051 The interrupts are controlled by 2 and JOC1 3 respectively The flags are set in IOS1 5 and IOS1 4 respectively Caution must be used when examining the flags as any access including Compare and Jump on Bit of 1051 clears bits O through 5 including the software timer flags It is therefore recommended to write the byte to a temporary register before testing bits The general en abling and disabling of the timer interrupts are con trolled by the Interrupt Mask Register bit O In all cas es setting a bit enables a function while clearing a bit disables it T2 CLK 9 4 HSI 1 270250 22 Figure 23 Timer 2 Clock and Reset Options 1 31 intel MCS 96 8X9X ARCHITECTURAL OVERVIEW 5 4 Timer Related Sections The High Speed I O unit is coupled to the timers in that the HSI records the value on Timer 1
12. Y lt lt e N N e N a 64L SDIP 68L PGA or LCC 68L PLCC Name 2 0 o tn e 5 a E o 220 122 lt 2 LE 2 dE iba m ur a e ololololoioloiojaojojoloj gnio amp 010 c lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 2 313 3 8 8X9X QUICK REFERENCE 68L PGA or LCC 3 0 PIN DEFINITION TABLE ML Pin 68L Name PLCC tiren a amp _ oj oln ojja o 9 e e Zr HE x gt 6 e o 20 59 O gt 68L PLCC 68L PGA or LCC 3 9 8X9X QUICK REFERENCE 4 0 PACKAGE PIN ASSIGNMENT Foa aoro 6 EA Vss XTAL1 XTAL2 Ls eorn ALE ADV rawr 22 19 ADUPS 22 23 BE 10 EN AD4 P3 4 AD5
13. 32 3 4D0 P3 0 20 pues A010 P4 2 AD14 P4 6 CI 31 1 1 2 E121 49 3 401 1 4 3 AD13 P4 5 a02 P3 2 1 5 9 22 48 1 012 4 4 AD12 P4 4 29 03 5 3 P1 4 23 47 2 013 4 5 AD11 P4 5 C 28 5 04 5 4 50 24 46 3 014 4 6 AD10 P4 2 C 27 0 AD5 P3 5 5 25 45 3 015 4 7 AD9 P4 1 C 26 J 06 5 6 HSI2 HS04 26 44 3 T2CLK P2 3 AD8 P4 0 C 25 8 407 P 3 7 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 TUUUUU on cC x 270246 45 35835 55 04 89 gt aa Sa 5 rr gt gt 48 Pin Package 2 x s E 2 a 270246 46 Pins Facing Down 68 Pin Package PLCC Top View 171513 11 9 7 5 3 1 18 19 16 14 12 10 8 6 4 2 68 20 21 67 66 22 23 65 64 24 25 63 62 61 60 59 58 7 56 55 54 lt 96 1234567 8 9 1011 12 15 14 15 16 17 68 PIN GRID ARRAY 26 27 28 29 30 31 32 53 34 36 38 40 42 44 46 48 50 53 52 35 57 39 41 43 45 47 49 51 270246 47 TOP VIEW LOOKING DOWN ON COMPONENT SIDE OF PC BOARD ucs 96 68 PIN LEADLESS CHIP CARRIER TYPE B EPROM ONLY TOP VIEW LOOKING DOWN ON COMPONENT SIDE OF PC BOARD 68 Pin Package Pin Grid Array Top View 51 50 49 48 47 46 45 44 45 42 41 40 39 38 37 36 35 270246 48 68 Pin Package LCC Top View 2 47 intel 8X9X HARDWARE DESIGN INFORMATI
14. 4 4 0 421 ACH5 P0 5 PMOD 1 417 ACH7 P0 7 PMOD 3 ACHE P0 6 PMOD 2 363 XTAL 1 35 XTAL2 34 ALE ADV 32L1400 P3 0 51 AD1 P3 1 30 AD2 P3 2 290 AD3 P3 3 04 3 4 27 05 3 5 26 06 6 25 AD7 P3 7 272110 19 m intel 8X9X QUICK REFERENCE 5 0 PIN DESCRIPTIONS Symbo Name and Function Main supply voltage 5V Digital circuit ground 0V There are two Vss pins both of which must be connected VREF Reference voltage for the A D converter 5V Vngr is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected to use A D or Port O ANGND Reference ground for the A D converter Must be held at nominally the same potential as V SS and will float to SV otherwise The pin should not be above for ROM and CPU RAM standby supply voltage 5V This voltage must be during normal operation aa devices This pin must be left floating in the application circuit for EPROM devices Programming voltage for the EPROM devices It should be 12 75V for programming In a Power Down condition i e drops to zero if RESET is activated before drops below spec and Vpp continues to be held within spec the top 16 bytes in the Register File will retain their contents XTAL1 input of the oscillator inverter and of the internal clock generator XTAL2 Ou
15. These pins have two functions They are either bidirec tional ports with open drain outputs or System Bus pins which the memory controller uses when it is acces ing off chip memory If the EA line is low the pins always act as the System Bus Otherwise they act as bus pins only during a memory access If these pins are being used as ports and bus pins ones must be written to them prior to bus operations Accessing Port 3 and 4 as I O is easily done from inter nal registers Since the LD and ST instructions require the use of internal registers it may be necessary to first move the port information into an internal location be fore utilizing the data If the data is already internal the LD is unnecessary For instance to write a word value to Port 3 and 4 register lt data not needed if already internal ST intreg lFFEH 1 43 register Port 3 and 4 intel MCS 96 8X9X ARCHITECTURAL OVERVIEW To read Port 3 and 4 requires that ones be written to the port registers to first setup the input port configuration circuit Note that the ports are reset to this input condition but if zeroes have been written to the port then ones must be re written to any pins which are to be used as inputs Reading Port 3 and 4 from a previously written zero condition is as follows LD intregA setup port change mode pattern ST intregA LFFEH written as ones register Port 3 and 4 LD
16. 270250 13 16 Bit Bus Cycle MCS 96 8X9X ARCHITECTURAL OVERVIEW Address Valid Strobe Mode If CCR bit 3 is a 0 then an Address Valid strobe is provided in the place of ALE Figure 14 When the address valid mode is selected ADV will go low after an external address is set up It will stay low until the end of the bus cycle where it will go inactive high This can be used by ROM devices to provide a chip select for a single external RAM device in a minimum chip count system Address Valid with Write Strobe If both CCR bits 2 and 3 are Os both the Address Valid strobe and the Write Strobes will be provided for bus control Figure 15 shows these signals ADO 7 ADDR LOW DATA OUT 08 15 ADDRESS HIGH 270250 14 8 Bit Bus Cycle Figure 13 Write Strobe Mode ADO 15 ADDR DATA OUT 270250 15 16 Bit Bus Cycle AD8 15 ADDRESS OUT HIGH 270250 16 8 Bit Bus Cycle Figure 14 Address Valid Strobe Mode WRL WRH ADOR DATA OUT 270250 17 16 Bit Bus Cycle MCS 96 8X9X ARCHITECTURAL OVERVIEW ADO 7 ADOR LOW DATA OUT 08 15 ADDRESS HIGH 270250 18 8 Bit Bus Cycle Figure 15 Write Strobe with Address Valid Strobe READY CONTROL To simplify ready control four modes of internal ready control logic have been provided The modes are cho sen by properly configuring bits 4 and 5 of the CCR The internal ready control logic can be used to limit the number of wait states
17. tions reserved for later sections There are several restrictions on using special function registers Neither the source or destination addresses of the Mul tiply and Divide instructions can be a writable special function register These registers may not be used as base or index regis ters for indirect or indexed instructions These registers can only be accessed as bytes unless otherwise specified in Figure 6 Note that some of these registers can only be accessed as words and not as bytes Within the SFR space are several registers labeled RESERVED These registers are reserved for future expansion and test purposes Operations should not be performed with these registers as reads from them and writes to them may produce unexpected results For example in some versions of the 8X9X writing to loca tion will set both timers to OFFFXH This may not be the case in future products so it should not be used as a feature 1 7 MCS 96 8X9X ARCHITECTURAL OVERVIEW 2 3 Power Down The upper 16 RAM locations through receive their power from the Vpp pin If it is desired to keep the memory in these locations alive during a pow er down situation one need only keep voltage on the pin The current required to keep the RAM alive is approximately 1 milliamp refer to the data sheet for the exact specification Both Vcc and Vpp must have power applied for normal operation If Vpp is not ap
18. 1103 5857 39V110A LNdNI v 30443 31n10s8v 1 17301 135330 0837 Figure 16 Actual and Ideal Characteristics 2 17 8X9X HARDWARE DESIGN INFORMATION 81 9v20 c SU Shj310 VH VHO qasva TVNII3L WNLOV NOILISNVAL 3000 31 25 1113 WNLV 5851 35 V110A LNANI v 3009 1 301 ALRIV3NIT1 NON 79143333314 ALIIV3NI1 NON 1 4 NOILISNVYL 3009 31 25 101 1 301 Figure 17 Terminal Based Characteristi 2 18 ntel 8X9X HARDWARE DESIGN INFORMATION 3 5 A D Glossary of Terms Figures 15 16 and 17 display many of these terms ABSOLUTE ERROR The maximum difference be tween corresponding actual and ideal code transitions Absolute Error accounts for all deviations of an actual converter from an ideal converter ACTUAL CHARACTERISTIC The characteristic of an actual converter The characteristic of a given con verter may vary over temperature supply voltage and frequency conditions An Actual Characteristic rarely has ideal first and last transition locations or ideal code widths It may even vary over multiple conversion un der the same conditions BREAK BEFORE MAKE The property of a multi plexer which guarantees that a previously selected channel will be deselected before a new channel is se lected e g the converter will not short inputs together CHANNEL TO CHANNEL MATCHING The dif ference between co
19. Once it is enabled it can only be disabled by resetting the 8X9X The internal bit which controls the watchdog can typically maintain its state through power glitches as low as Vss and as high as 7 0V for up to one millisec ond Enabling and clearing the WDT is done by writing a OLEH followed by a to the WDT register at location OAH This double write is used to help prevent accidental clearing of the timer 12 1 Software Protection Hints Glitches and noise on the PC board can cause software upsets typically by changing either memory locations or the program counter These changes can be internal to the chip or be caused by bad data returning to the chip There are both hardware and software solutions to noise problems but the best solution is good design practice and a few ounces of prevention The software can be designed so that the watchdog times out if the program does not progress properly The watchdog will also time out if the software error was due to ESD Electrostatic Discharge or other hardware related problems This prevents the controller from having a malfunction for longer than 16 milliseconds if a 12 MHz oscillator is used When using the WDT to protect software it is desirable to reset it from only one place in code This will lessen the chance that an undesired WDT reset will occur The section of code that resets the WDT should moni tor the other code sections for proper operation This
20. Read Protected Write Protected No Protection Only code executing from internal memory can read protected internal memory while a write protected memory can not be written to even from internal exe cution As a result of 8X9X prefetching of instructions however accesses to protected memory are not allowed for instructions located above 3FFAH on the 8X9XBH and the 8X98 and above 5 on the 8X9XJF This is because the lock protection mechanism is gated off of the Memory Controller s slave program counter and not the CPU program counter If the bus controller receives a request to perform a read of protected memo ry the read sequence occurs with indeterminate data being returned to the CPU Note that the interrupt vec tors and the CCR are not protected To provide verification and testing when the program lock feature is enabled the 8X9X verifies the security key before programming or test modes are allowed to read from protected memory Before protected memory can be read the chip reads external memory locations 4020H through 402FH and compares the values intel found to the internal security key located from 2020H through 202FH Only when the values exactly match will accesses to protected memory be allowed The de tails of ROM EPROM accessing are discussed in Sec tion 10 of the Hardware Design chapter 3 0 SOFTWARE OVERVIEW This section provides information on writing programs to execute in the 8X9X Additional i
21. The DI and TRAP instructions will also cause the same situa tion Typically the PUSHF POPF and TRAP instruc tions would only effect latency when one interrupt routine is already in process as these instructions are seldom used at other times 5 0 TIMERS Two 16 bit timers are available for use on the 8096 The first is designated Timer 1 the second Timer 2 Timer 1 is used to synchronize events to real time while Timer 2 can be clocked externally and synchro nizes events to external occurrences 5 1 Timer 1 Timer 1 is clocked once every eight state times and can be cleared only by executing a reset The only other way to change its value is by writing to 000CH but this is a test mode which sets both timers to OFFFXH and should not be used in programs 5 2 Timer 2 Timer 2 can be incremented by transitions one count each transition rising and falling on either T2CLK or HSI 1 T2CLK is not available on the 8X98 The mul MCS 96 8X9X ARCHITECTURAL OVERVIEW tiple functionality of the timer is determined by the state of I O Control Register 0 bit 7 IOCO 7 To en sure that all CAM entries are checked each count of Timer 2 the maximum transition speed is limited to once per eight state times Timer 2 can be cleared by executing a reset by setting IOCO 1 by triggering HSO channel OEH or by pulling T2RST or HSI 0 high The HSO and CAM are described in Section 7 and 8
22. 1 20 TOP VIEW 5071 AD10 P4 2 LOOKING DOWN ON COMPONENT SIDE bi 23 471 AD13 P4 5 510 510 1 124 OF PC BOARD 46 014 4 6 HSI1 SID 2 125 45 015 4 7 HSI2 HS04 SID 3 C 44171 T2CLK P2 3 WRL WR BHE WRH T2RST P2 4 513 505 51 4 500 PWM P2 5 PDO SPROG 272110 17 3 12 n 8X9X QUICK REFERENCE Vcc Vss XTAL 1 XTAL2 ALE ADV ADO P3 0 AD1 P3 1 AD2 P3 2 AD3 P3 3 AD4 P3 4 ADS P3 5 AD6 P3 6 07 5 7 RXD P2 1 PALE I AD8 P4 0 TXD P2 0 PVER SALE 8X97BH AD9 PA 1 8X97JF AD10 P4 2 AD11 P4 3 AD12 P4 4 AD13 P4 5 AD14 P4 6 HSI 0 SID 1 AD15 P4 7 HSI 1 SID 2 lt I T2CLK P2 3 HSO 4 HSI 2 SID 3 READY 50 5 5 3 510 4 T2RST P2 4 HSO 0 PACT CLS BHE WRH To WR WRL PWM P2 5 PDO SPROG ACH3 P0 3 ACH1 PO 1 ECT ACHO PO 0 ACH2 P0 2 T ACH6 P0 6 PMOD 2 7 P0 7 PMOD 3 lt E ACH5 P0 5 PMOD 1 ECL ACH4 P0 4 PMOD 0 oon AO 450 272110 18 Shrink DIP Package 8X9X QUICK REFERENCE RXD P2 1 PALE 1 TXD P2 0 PVER SALE 7 HSI 0 SID 1 C 51 1 510 2 1 2 0 4 10 5 5 5 50 5 510 4 C 50 0 PWM P2 5 PD0 SPROG WRL WR AD15 P4 7 AD14 P4 6 AD13 P4 5 AD12 P4 4 AD11 P4 3 010 4 2 9 4 1 C AD8 P4 0 48 1 RESET 47 2 2 ANGND 433
23. 11H HIT 1 BITO SPECIFY THE MODE 00 MODE 0 10 MODE 2 01 MODE 1 11 MODE 3 PEN ENABLE THE PARITY FUNCTION REN ENABLES THE RECEIVE FUNCTION PROGRAMS THE 9TH DATA BIT IS THE TRANSMIT INTERRUPT FLAG IS THE RECEIVE INTERRUPT FLAG IS THE 9TH DATA RECEIVED IF NOT PARITY 1 THE PARITY ERROR INDICATOR IF PARITY ACTIVE 272110 7 Chip Configuration 7 5 5 2 conricuration resister RESERVED Set to 1 for compatibility with future ports 895 WIDTH SELECT 16 BIT BUS 8 BIT BUS WRITE STROBE MODE SELECT WR BRE WRL AND ADDRESS VALID STROBE SELECT ALE ADV CIRCO INTERNAL READY CONTROL mci MODE PROGRAM LOCK MODE Loc 1 272110 8 Internal Ready Control IRC1 IRCO Description 0 Limit to 1 Wait State 1 Limit to 2 Wait States 0 Limit to 3 Wait States 1 Disable Internal Ready Control Program Lock Modes LOC1 LOCO Protection Read and Write Protected Read Protected Write Protected No Protection Interrupt Pending Mask Register LOCATION 08H 09H 2 L HSI DATA AVAILABLE HSO EVENT HSI BIT 0 SOFTWARE TIMERS SERIAL 1 0 EXTERNAL INTERRUPT 272110 9 0 15H HSI O INPUT ENABLE DISABLE TIMER 2 RESET EACH WRITE HSI 1 INPUT ENABLE DISABLE TIMER 2 EXTERNAL RESET ENABLE DISABLE HSI 2 INPUT ENABLE DISABLE TIMER 2 RESET SOURCE HSI 0 T2RST 1 3 INPUT ENABLE DI
24. 96 8X9X ARCHITECTURAL OVERVIEW Table 3 Instruction Summary Continued Oper 0 peration Note 1 1 1 I 1 JmpiN o0amdz 0 5 1 2 1 1 5 P JumpitC 1 2 0 pepe Ies JNH 5 Lv 5 JNV 1 5 oT 1 JXmeitvr zceavr ____ 5 _____ epo anst ____ _ _ 1 yes 3 1 se psc Ts pumerseseaet o ____ 5 me 8 bit offset 1 1 NCNB EXT 1 lt 2 lt 590 0 0 em 3 oco 1 9 SHUSHB SHL 2 mb mco 7 72 wc gt 7 SHRA SHRAB SHRAL 2 7 Ds 0 Oe uoc ce pamm 9
25. BHE 1 to the high byte only 1 0 or both bytes 0 0 If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location See Section 2 7 Ready input to lengthen external memory cycles for interfacing to slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the Memory Controller goes into a wait mode until the next positive transition in CLKOUT occurs with READY high The bus cycle can be lengthened by up to 1 us When the external memory is not being used READY has effect Internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of CCR READY has a weak internal pullup so it goes to 1 unless externally pulled low See Section 2 7 Inputs to High Speed Input Unit Four HSI pins are available HS 0 HSI 1 HSI 2 and HSI 3 Two of them HSI 2 and HSI 3 are shared with the HSO Unit The HSI pins are also used as inputs by EPROM devices in Programming mode See Section 6 Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 and HSO 5 Two of them HSO 4 and HSO 5 are shared with the HSI Unit See Section 7 8 bit high impedance input only port These pins can be used as digital inputs and or as analog inputs to the on chip A D converter Th
26. CHANNEL NUMBER STATUS 0 A D CURRENTLY IDLE 1 z CONVERSION IN PROCESS A D RESULT LEAST SIGNIFICANT 2 BITS MOST SIGNIFICANT BYTE 270250 30 Figure 31 A D Result Register 1 37 intel MCS 96 8X9X ARCHITECTURAL OVERVIEW times after the go command so it is necessary to wait 8 state times before testing it Information on using the HSO is in Section 7 8 4 Pulse Width Modulation Output D A Digital to analog conversion can be done with the Pulse Width Modulation output a block diagram of the cir cuit is shown in Figure 32 The 8 bit counter is incre mented every state time When it equals 0 the PWM output is set to a one When the counter matches the value in the PWM register the output is switched low When the counter overflows the output is once again switched high A typical output waveform is shown in DATA BUS x8 OVERFLOW Figure 33 Note that when the PWM register equals 00 the output is always low Additionally the PWM regis ter will only be reloaded from the temporary latch when the counter overflows This means that the com pare circuit will not recognize a new value to compare against until the counter has expired the remainder of the current 8 bit count The output waveform is a variable duty cycle pulse which repeats every 256 state times 64 us at 12 MHz Changes in the duty cycle are made by writing to the PWM register at location 17H There are several types of motors which requir
27. CLOCKOUT PHASE B PHASE Figure 4 Internal Timings Relative to XTAL 1 1 5 270250 4 intel MCS 96 8X9X ARCHITECTURAL OVERVIEW 2 0 MEMORY SPACE The addressable memory space on the 8X9X consists of 64K bytes most of which is available to the user for program or data memory Locations which have special purposes are through OOFFH 0100H through 8X9XJF only and 1FFEH through 2080H All other locations can be used for either program or data storage or for memory mapped peripherals A memory map is shown in Figure 5 POWER DOWN RAM INTERNAL REGISTER FILE RAM STACK POINTER PWM_CONTROL RESERVED 10 PORT 2 10 PORT 1 BAUD RATE RESERVED HSO TIME LO WHEN WRITTEN STACK POINTER RESERVED SP_STAT PORT 2 10 PORT 1 WHEN READ 2 1 Register File Locations 00H through OFFH contain the Register File and Special Function Registers SFRs No code can be executed from this internal RAM section If an at tempt to execute instructions from locations 000 through OFFH is made the instructions will be fetched from external memory This section of external memo ry is reserved for use by Intel development tools Exe cution of a nonmaskable interrupt NMI will force a EXTERNAL MEMORY OR 1 0 EXTERNAL MEMORY OR 1 0 8X9XBH INTERNAL PROGRAM STORAGE ROM EPROM OR EXTERNAL MEMORY 8X9XJF INTERNAL PROGRAM STORAGE ROM EPROM OR
28. HIGH SPEED OUTPUTS The High Speed Output unit HSO is used to trigger events at specific times with minimal CPU overhead These events include starting an A to D conversion resetting Timer 2 setting 4 software flags and switch ing 6 output lines HSO 0 through HSO 5 Up to eight events can be pending at one time and interrupts can be generated whenever any of these events are triggered HSO 4 and HSO 5 are bidirectional pins which can also be used as HSI 2 and HSI 3 respectively Bits 4 and 6 of I O Control Register 1 IOC1 4 IOCI 6 enable HSO 4 and HSO 5 as outputs The HSO unit can generate two types of interrupts The HSO execution interrupt vector 2006H is gener ated if enabled for HSO commands which operate one or more of the six output pins The other HSO inter rupt is the software timer interrupt vector 200BH which is generated if enabled by any other HSO command e g triggering the A D resetting Timer 2 or generating a software time delay CAM CONTROL LOGIC HOLDING REGISTER HSO_COMMAND HSO_TIME E 6 HSO HSO_STATUS COMMAND DECODER 1051 16H TIMER FLAGS PORT PINS MCS 96 8X9X ARCHITECTURAL OVERVIEW 7 1 HSO CAM A block diagram of the HSO unit is shown in Figure 28 The Content Addressable Memory CAM file is the center of control One CAM register is compared with the timer values every state time taking 8 state times to compare all CAM register
29. Input of the oscillator inverter and of the internal clock generator See Section 1 5 2 Output of the oscillator inverter See Section 1 5 CLKOUT Output of the internal clock generator The frequency of CLKOUT is 14 the oscillator frequency It has a 33 duty cycle See Section 1 5 Reset input to the chip Input low for at least 1OXTAL1 cycles to reset the chip The subsequent low to high transition re synchronizes CLKOUT and commences a 10 state time sequence in which the PSW is cleared a byte read from 2018H loads CCR and a jump to location 2080H is executed Input high for normal operation RESET has an internal BUSWIDTH positive transition causes a vector to external memory location 0000H External memory from 00H through OFFH is reserved for Intel development systems INST Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle ALE ADV external memory ALE ADV is activated only during external memory accesses Section 2 7 pullup See Section 13 Read signal output to external memory RD is activated only during external memory reads Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus cycle in progress If BUSWIDTH is a 1 a 16 bit bus cycle occurs If BUSWIDTH is a 0 an 8 bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8 bit bus If this pin i
30. P0 6 ACH6 MOD 2 P0 7 ACH7 MOD 3 AW 68 Pin 68 Pin 48 Pin PLCC PGA DIP P2 0 TXD PVER P2 1 RXD PALE P2 2 EXTINT P2 3 T2CLK 44 P2 4 T2RST 42 P2 5 PWM PDO 39 P2 6 33 P2 7 38 P3 0 ADO PVAL 60 P3 1 AD1 PVAL 59 P3 2 AD2 PVAL 58 P3 3 AD3 PVAL 57 P3 4 AD4 PVAL 56 P3 5 AD5 PVAL 55 P3 6 AD6 PVAL 54 P3 7 AD7 PVAL 53 P4 0 AD8 PVAL 52 P4 1 AD9 PVAL 51 P4 2 AD10 PVAL 50 P4 3 AD11 PVAL 49 P4 4 AD12 PVAL 48 P4 5 AD13 PVAL 47 P4 6 AD14 PVAL 46 P4 7 AD15 PVAL 64 Pin SDIP 29 SALE PVER P2 0 SPROG PDO P2 5 TXD P2 0 SALE T2CLK P2 3 T2RST P2 4 The following pins are not bonded out in the 48 pin package P1 0 through P1 7 through P2 3 P2 4 P2 6 P2 7 CLKOUT INST NMI TEST T2CLK P2 3 T2RST P2 4 2 45 intel 8X9X HARDWARE DESIGN INFORMATION 11 3 Packaging The MCS 96 products are available in 48 pin 64 pin and 68 pin packages with and without A D and with and without on chip ROM or EPROM The MCS 96 numbering system shown below this section shows the pinouts for the 48 and 68 pin packages The 48 pin version is offered in a Dual In Line package while the 68 pin versions come in a Plastic Leaded Chip Carrier PLCC a Pin Grid Array PGA or a Type B Leadless Chip Carrier The MCS 96 Family Nomenclature Factory User Programmable Masked ROM
31. P3 5 Pins Facing Down 17 1513 119 7 5 3 18 19 16 14 12 10 8 6 4 2 68 20 21 57 66 22 23 65 64 24 25 63 62 26 27 61 50 28 29 59 58 30 31 57 56 32 33 55 54 34 36 38 40 42 44 46 48 50 53 52 35 37 39 41 43 45 47 49 51 ucs 96 68 PIN GRID ARRAY TOP VIEW LOOKING DOWN ON COMPONENT SIDE OF PC BOARD 26 rw AD12 P4 4 AD13 P4 5 AD14 P4 6 AD15 P4 7 T2CLK P2 3 T2RST P2 4 D I m 14 5 lt 2 3 2 WM P2 5 PDO SPRO 7 E ag 5 HSO 2 gt gt gt A o gt e P1 7 3 10 272110 15 Description m sw mos mw wma se Pis 57 5 Pit _____ D P1 59 PI R PZU PVER SALE EIL A A EXINUPRZIPRUS Vp per es intel 8X9X QUICK REFERENCE D a o o z a a oc o gt c gt 2 CN zx I I I I Uv 2 4 lt lt o a a 2 3 4 5 6 14 6 ACH5 P0 5 PMOD 1 C ACH4 P0 4 PMOD 0 C ADO P3 0 AD1 P3 1 AD2 P3 2 AD3 P3 3 AD4 P3 4 AD5 P3
32. Sets the duration of the PWM puise Figure 6 SFR Summary XTAL1 CYCLES CLOCK NOT NECESSARY MCS 96 8X9X ARCHITECTURAL OVERVIEW XTAL1 CYCLES AFTER CLOCK IS STABLE 270250 6 Figure 7 Power Down Timing 2 4 Reserved Memory Spaces listing of locations with special significance is shown in Figure 8 The locations marked Reserved are re served by Intel for use in testing or future products All reserved locations except 2019H must be filled with Hex value OFFH to insure compatibility with future devices Location 2019H must be filled with 20H Locations 1FFEH and 1FFFH are reserved for Ports 3 and 4 respectively This is to allow easy reconstruction of these ports if external memory is used in the system An example of reconstructing the ports is given in section 7 of the Hardware Design chapter If ports 3 and 4 are not going to be reconstructed these locations can be treated as any other external memory location The 9 interrupt vectors are stored in locations 2000H through 2011H The 9th vector is used by Intel devel opment systems as explained in Section 4 Locations 2012H through 2017H are reserved for fu ture use Location 2018H is the Chip Configuration byte which will be discussed in the next section The Jump To Self opcodes at locations 201A H and 201 are provided for EPROM programming as detailed in the Hardware Design chapter Locations 2020H through 202FH are the security key use
33. State times shown for 16 bit bus 2 53 intel 8X9X HARDWARE DESIGN INFORMATION CONDITIONAL JUMPS All conditional jumps are 2 byte instructions They require 8 state times if the jump is taken 4 if it is not 9 OPCODE MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC OPCODE c we ic fo o o Lm fo x o s JNH JNV JUMP ON BIT CLEAR OR BIT SET These instructions are byte instructions They require 9 state times if the jump is taken 5 if it is not 8 BIT NUMBER LOOP CONTROL MNEMONIC BYTES STATE TIMES DJNZ o a 5 9 STATE TIME NOT SINGLE REGISTER INSTRUCTIONS MNEMONIC OPCODE BYTES STATES MNEMONIC OPCODE BYTES STATES he 4 4 ee NOT 2 3 LG gt 4 Jar 2 4 me 7 4 Jar n 2 e SHIFT INSTRUCTIONS INSTR womb _ INSTR Aue MNEMONIC MNEMONIC oP B MNEMONIC op B o 7 1 PERSHIFT ___ o 7 sema s sas 34 3 sema oe 3 7 1PERSHIFTO SPECIAL CONTROL INSTRUCTIONS aves stares owcooe
34. WRH ADDRESS VALID STROBE SELECT ALE ADV IRCO INTERNAL READY CONTROL MODE LOCO PROGRAM LOCK Loc1 MODE 270246 61 internal Ready Control IRC1 IRCO Description Limit to 1 Wait State Limit to 2 Wait States Limit to 3 Wait States Disable interna Ready Control LOC1 LOCO Protection Read and Write Protected Read Protected Write Protected No Protection Programming Function PMODE Values _PMODE ProgrammingMode Reserved 5 Stave Programming 6 08H Reseved ODH Program Configuration Byte OEH OFH Reseved 8X9X HARDWARE DESIGN INFORMATION Slave Programming Mode Commands Word Dump Data Verify Data Program Reserved 8X9XBH Signature Word Device Signature Word 879XBH 896FH 839XBH 896EH 809XBH Undefined Port 2 Pin Functions Port Function Alternate Function TXD Serial Port Transmit Serial Port Receive EXTINT External Interrupt T2CLK Timer 2 Clock T2RST Timer 2 Reset PWM Pulse Width Modulation Interrupt Pending Register LOCATION 09H 78 5 3 2 Lo HSI DATA AVAILABLE HSO EVENT HSI BIT 0 SOFTWARE TIMERS SERIAL 1 0 EXTERNAL INTERRUPT 270246 62 PSW Register 15 14 13 12 11 10 09 07 06 os 04 02 01 00 lt imeruptmaskfeg gt 2 57 8x9x Quick Refer
35. a variance of about 50 ns assuming a stable clock on XTALI However conversions initiated by writing a one to the ADCON register GO Bit will start within three state times after the instruction has completed execution re sulting in a variance of about 0 75 ps 12 MH2 Once the A D unit receives a start conversion signal there is a one state time delay before sampling sample delay while the successive approximation register is re set and the proper multiplexer channel is selected Af ter the sample delay the multiplexer output is connect ed to the sample capacitor and remains connected for four state times sample time After this four state time sample window closes the input to the sample itor is disconnected from the multiplexer so that chang es on the input pin will not alter the stored charge while the conversion is in progress The comparator is then auto zeroed and the conversion begins The sample de lay and sample time uncertainties are each approxi mately 50 ns independent of clock speed To perform the actual analog to digital conversion the 8X9X implements a successive approximation algo rithm The converter hardware consists of a 256 resis tor ladder a comparator coupling capacitors and a 10 bit successive approximation register SAR with logic that guides the process The resistor ladder pro vides 20 mV steps Vref 5 12V while capacitive coupling is used to create 5 mV st
36. able a byte is an eight bit unit of data of any type BYTES BYTES are unsigned 8 bit variables which can take on the values between 0 and 255 Arithmetic and relational operators can be applied to BYTE operands but the MCS 96 8X9X ARCHITECTURAL OVERVIEW result must be interpreted in modulo 256 arithmetic Logical operations on BYTES are applied bitwise Bits within BYTES are labeled from 0 to 7 with 0 being the least significant bit There are no alignment restrictions for BYTES so they may be placed anywhere in the MCS 96 address space WORDS WORDS are unsigned 16 bit variables which can take on the values between 0 and 65535 Arithmetic and relational operators can be applied to WORD operands but the result must be interpreted modulo 65536 Logi cal operations on WORDS are applied bitwise Bits within words are labeled from O to 15 with 0 being the least significant bit WORDS must be aligned at even byte boundaries in the MCS 96 address space The least significant byte of the WORD is in the even byte ad dress and the most significant byte is in the next higher odd address The address of a word is the address of its least significant byte Word operations to odd ad dresses are not guaranteed to operate in a consistent manner SHORT INTEGERS SHORT INTEGERS are 8 bit signed variables which can take on the values between 128 and 127 Arithmetic operations which generate results outside of the range of a SHOR
37. amp ST not needed if previously LD intregB register lt Port 5 and 4 Note that while the format of the LD and ST instructions are similar the source and destination directions change When acting as the system bus the pins have strong drivers to both Vcc and Vss These drivers are used whenever data is being output on the system bus and are not used when data is being output by Ports 3 and 4 Only the pins and input buffers are shared between the bus and the ports The ports use different output buffers which are configured as open drain and require pullup resistors open drain is the MOS version of open collector The port pins and their system bus functions are shown in Table 5 Table 5 P3 4 AD0 15 Pins System Bus Function 11 0 STATUS AND CONTROL REGISTERS There are two I O Control registers IOCO and IOC1 IOCO controls Timer 2 and the HSI lines IOC1 con trols some pin functions interrupt sources and 2 HSO pins Whenever input lines are switched between two sourc es or enabled it is possible to generate transitions on these lines This could cause problems with respect to edge sensitive lines such as the HSI lines Interrupt line and Timer 2 control lines 11 1 Control Register 0 IOCO IOCO is located at 0015H The four HSI lines can be enabled or disabled to the HSI unit by setting or clear ing bits in IOCO Timer 2 functions including clock and reset sources are also determin
38. an image of lower five bits of the register Any time a hardware timer interrupt or a HSO software timer in terrupt occurs the byte can be updated ORB 1051 1 1051 leaving 1051 image containing all the flags that were set before plus all the new flags that were read and cleared from IOS1 Any other routine which needs to sample the flags can safely check 1081 image Note that if these routines need to clear the flags that they have acted on then the modification of IOS1__image must be done from inside a critical region see Section 4 4 intel 12 0 WATCHDOG TIMER The WatchDog Timer WDT provides a means to re cover gracefully from a software upset When the watchdog is enabled it will initiate a hardware reset unless the software clears it every 64K state times The WDT is implemented as an 8 bit timer with an 8 bit prescaler The prescaler is not synchronized so the timer will overflow between 65280 and 65535 state times after being reset When the timer overflows it pulls down the RESET pin for at least one state time resetting the 8X9X and any other devices tied to the RESET line If a large capacitor is connected to the line the pin may take a long time to go low This will effect the length of time the pin is low and the voltage on the pin when it is finished falling Section 1 4 of the Hardware Design chapter contains more information about reset hardware connections The WDT is enabled the first time it is cleared
39. and PCCB 2 Make necessary minimum connections for power ground and clock Figure 34 The Auto CCR Programming Mode 2 35 intel 10 4 Auto Programming Mode The Auto Programming Mode provides the ability to program the 879X EPROM without using an EPROM programmer For this mode follow the power up se quence described in Section 10 1 with PMODE OCH When RESET rises the 879XBH and 8798 devic es automatically program themselves with the data found at external locations 4000H through SFFFH The 879XJF programs itself with the data found at ex ternal locations 4000H through 7FFF Figure 35 shows a minimum configuration for using an 8K x 8 EPROM to program one 879X in the Auto Programming Mode The 879X reads a word from external memory then the Modified Quick Pulse Programming Algorithm described later is used to program the appropriate EPROM location Since the erased state of a byte is OFFH the Auto Programming Mode will skip loca tions where the data to be programmed is OFFH When all 8K of the 879XBH and 8798 and all 16K of the 879XJF has been programmed PACT goes high and the devices outputs a O on Port 3 0 PVAL if it pro grammed correctly and a 1 if it failed 10 4 1 AUTO PROGRAMMING MODE AND THE CCB PCCB In the Auto Programming Mode the CCR is loaded with the PCCB The PCCB must correspond to the memory system of the programming setup including the READY and bus control selections You can pro gr
40. are five types of I O lines on the 8X9X Of these two are inputs and three are outputs All of the pins of the same type have the same current voltage character istics Some of the control input pins such as XTAL1 and RESET may have slightly different characteristics These pins are discussed in Section 1 While discussing the characteristics of the I O pins some approximate current or voltage specifications will be given The exact specifications are available in the lastest version of the data sheet that corresponds to the device being used 2 1 Quasi Bidirectional Ports The Quasi Bidirectional pins of Port 1 Port 2 6 and Port 2 7 have both input and output port configura tions They have three distinct states low impedance current sink Q2 low impedance current source 01 and high impedance current source Q3 As a low im pedance current sink the pin has specification of sink ing up to around 0 5 mA while staying below 0 45 volts The pin is placed in this condition by writing a 0 to the SFR Special Function Register controlling the pin Examine Figure 10 When the SFR contains a 0 and a is written to it Q1 a low impedance MOSFET pull up is turned on for one state then it is turned off and the depletion pullup holds the line at a logical 1 state The low impedance pullup is used to shorten the rise time of the pin and has current source capability on the order of 100 times that of the depleti
41. bit cycle If a zero is seen the bus access progresses as an 8 bit cycle The BUSWIDTH setup and hold timing requirements appear in the data sheet The BUSWIDTH pin can be overridden by causing the BUS WIDTH SELECT bit in the Chip Configuration Register CCR to be zero This will permanently select an 8 bit bus width However if the BUS WIDTH SE LECT bit in the CCR is a one the BUSWIDTH pin determines the bus width See Section 3 5 of the 8X9X Architecture chapter Since the BUSWIDTH pin is not available on 48 pin or 64 pin devices the BUS WIDTH SELECT bit in the CCR determines bus width 7 6 Address Decoding The multiplexed bus of the 8X9X must be demulti plexed before it can be used This can be done with two 74LS373 transparent latches for an 8X9X in 16 bit 741574 bus mode 741 8373 for an 8X9X 8 bit bus mode As explained in Section 3 5 of the 8X9X Archi tecture chapter the latched address signals will be re ferred to as MAO through MA15 Memory Address and the data lines will be called MDO through MD15 Memory Data Since the 8X9X can make accesses to memory for ei ther bytes or words it is necessary to have a way of determining the type of access desired when the bus is 16 bits wide For write cycles the signals Write Low WRL and Write High WRH are provided WRL will go low during all word writes and during all byte writes to an even location Similarly WRH will go low during all wor
42. by the A to D converter The 8X98 devices only have 4 Port 0 pins The 8X9X samples the input to the A D for 4 state times at the beginning of the conversion Details on the A to D converter can be found in Section 8 of this chapter and in Section 3 of the Hardware Design chap ter 10 2 Quasi Bidirectional Ports Port 1 Port 2 6 and Port 2 7 are quasi bidirectional ports Port 1 Port 2 6 and Port 2 7 are not available on the 8X98 Quasi bidirectional means that the port pin has a weak internal pullup that is always active and an internal pulldown which can be on to output a 0 or off to output a 1 If the internal pulldown is left off by writing a 1 to the pin the pin s logic level can be con trolled by an external pulldown If the external pull down is on it will input a 0 to the 8X9X if it is off a 1 will be input From the user s point of view the main difference between a quasi bidirectional port and a standard input port is that the quasi bidirectional port will source current if externally pulled low It will also pull itself high if left unconnected In parallel with the weak internal pullup is a much stronger internal pullup that is activated for one state time when the pin is internally driven from 0 to 1 This is done to speed up the 0 to 1 transition time When this pullup is on the pin can typically source 30 milli amps to Vss When the processor writes to the pins of a quasi bidi rectional port it a
43. by the address of its least significant byte Note that the hardware supports some operations on double words e g normalize and divide For these operations the double word must be in the internal register file and must have an address which is evenly divisible by four SUBROUTINE LINKAGE Parameters are passed to subroutines in the stack Pa rameters are pushed into the stack in the order that they are encountered in the scanning of the source text Eight bit parameters BYTES or SHORT INTE GERS are pushed into the stack with the high order 1 25 MCS 96 8X9X ARCHITECTURAL OVERVIEW byte undefined Thirty two bit parameters LONG INTEGERS DOUBLE WORDS and REALS are pushed into the stack as two 16 bit values the most significant half of the parameter is pushed into the stack first As an example consider the following PLM 96 proce dure example procedure PROCEDURE param l param2 param3 DECLARE BYTE param2 DWORD param3 WORD When this procedure is entered at run time the stack will contain the parameters in the following order 22227 param1 high word of param2 low word of param2 lt Stack_pointer Figure 18 Stack Image If a procedure returns a value to the calling code as opposed to modifying more global variables then the result is returned in the variable PLMREG PLMREG is viewed as either an 8 16 or 32 bit variable depend ing on the type of the procedure The st
44. control register before writing to SBUF tx The 8 bit is cleared on every transmission so it must be set prior to writing to SBUF tx each time it is desired During reception the serial port interrupt and the Receive Interrupt RI bit will not be set unless the 9th bit being received is set This provides an easy way to have selective reception on a data link Parity cannot be enabled in this mode MODE 3 Mode 3 is the asynchronous 9th bit mode The data frame for this mode is identical to that of Mode 2 The transmission differences between Mode 3 and Mode 2 are that parity can be enabled PEN 1 and cause the 9th data bit to take the even parity value The TBS bit can still be used if parity is not enabled PEN 0 When in Mode 3 a reception always causes an inter rupt regardless of the state of the 9th bit The 9th bit is stored if 0 and can be read in bit RBS If PEN 1 then RB8 becomes ihe Receive Parity Error RPE flag 9 2 Controlling the Serial Port Control of the serial port is done through the Serial Port Control SP CON and Serial Port Status SP STAT registers shown in Figure 37 Writing to location 11H accesses CON while reading it access SP STAT Note that reads of SP STAT will return indeterminate data in the lower 5 bits and writing to the upper 3 bits of SP CON has no effect on chip func tionality The TB8 bit is cleared after each transmission and both TI and RI are cleared whe
45. converter The port is sam pled once every state time however sampling is not synchronized to Timer 1 If this port is used the input signal on the pin must be stable one state time before the reading of the SFR Port 1 and Port 2 have quasi bidirectional I O pins When used as inputs the data on these pins must be stable one state time prior to reading the SFR This timing is also valid for the input only pins of Port 2 and is similar to the HSI in that the sample occurs just after the rising edge of CLKOUT When used as outputs the quasi bidirectional pins will change state shortly after CLKOUT falls If the change was from 0 to a the low impedance pullup will remain on for one state time after the change Ports 3 and 4 are addressed as off chip memory mapped 1 0 The port pins will change state shortly after the rising edge of CLKOUT When these pins are used as Ports 3 and 4 they are open drains their struc ture is different when they are used as part of the bus See Section 10 4 of the 8X9X Architecture chapter Ad ditional information on port reconstruction is available in Section 7 7 of this chapter 6 0 SERIAL PORT TIMINGS The serial port on the 8X9X was designed to be com patible with the 8051 serial port Since the 8051 uses a divide by 2 clock and the 8X9X uses a divide by 3 the serial port on the 8X9X had to be provided with its own clock circuit to maximize its compatibility with the 8051 at high bau
46. ent in actual converters Figure 15 shows the transfer function for an ideal 3 bit A D converter i e the Ideal Characteristic intel Note that in Figure 15 the Ideal Characteristic possess es unique qualities it s first code transition occurs when the input voltage is 0 5 LSB it s full scale code tran sition occurs when the input voltage equals the full scale reference minus 1 5 LSB and it s code widths are all exactly one LSB These qualities result in a digitiza tion without offset full scale or linearity errors In oth er words a perfect conversion Figure 16 shows an Actual Characteristic of a hypo thetical 3 bit converter which is not perfect When the Ideal Characteristic is overlaid with the imperfect char acteristic the actual converter is seen to exhibit errors in the location of the first and final code transitions and code widths The deviation of the first code transition from ideal is called zero offset and the deviation of the final code transition from ideal is full scale error The deviation of the code widths from ideal causes two types of errors Differential Non Linearity and Non Linearity Differential Non Linearity is a local linearity error measurement whereas Non Linearity is an over all linearity error measure Differential Non Linearity is the degree to which actual code widths differ from the ideal one LSB width Dif ferential Non Linearity gives the user a measure of how much t
47. exclusion which basical ly means that if more than one routine can change a variable then the programmer must ensure exclusive access to the variable during the entire operation on the variable In many cases the instruction set of the 8X9X allows the variable to be modified with a single instruction The code in the above example can be implemented with a single instruction ANDB INT PENDING bit mask intel MCS 96 8X9X ARCHITECTURAL OVERVIEW Instructions are indivisible so mutual exclusion is en sured in this case Changes to the INT_PENDING register must be made as a single instruction since bits can be changed in this register even if interrupts are disabled Depending on system configurations several other SFRs might also need to be changed in a single instruction for the same reason When variables must be modified without interruption and a single instruction can not be used the program mer must create what is termed a critical region in which it is safe to modify the variable One way to do this is to simply disable interrupts with a DI instruc tion perform the modification and then re enable in terrupts with an EI instruction The problem with this approach is that it leaves the interrupts enabled even if they were not enabled at the start A better solution is to enter the critical region with a PUSHF instruction which saves the PSW and also clears the interrupt en able flags The region can then be termin
48. forcing the call requires 21 state times If the stack is in external RAM an additional 3 state times are required The maximum number of state times required from the time an interrupt is generated not acknowledged until the 8X9X begins executing code at the desired location is the time of the longest instruction NORML Nor malize 42 state times plus the 4 state times prior to the end of the previous instruction plus the response time 21 to 24 state times Therefore the maximum response time is 70 42 4 24 state times This does not include the 12 state times required for PUSHF if it is used as the first instruction in the interrupt rou tine or additional latency caused by having the inter rupt masked or disabled Refer to Figure 22A Inter rupt Response Time to visualize an example of a worst case scenario 42 lt 21 53 lt 12 ENDING END CALL IS IF STACK GY EXTINT PENDING BIT RESPONSE TIME INTERRUPT ROUTINE hol xoxo STATE TIMES 270250 60 Figure 22A Interrupt Response Time 1 30 intel Interrupt latency time can be reduced by careful selec tion of instructions in areas of code where interrupts are expected Using EI followed immediately by a long instruction e g MUL NORML etc will in crease the maximum latency by 4 state times as an interrupt cannot occur between EI and the instruction following EI
49. gram the WRITE lock bit when no further program ming will be done to the array If the READ lock bit is enabled the array can still be programmed using run time programming but data accesses will only be per formed when the program counter ts between 2000H and 3FFFH on the 879XBH and the 8798 and between 2000H and 5FFFH on the 879XJF 10 7 ROM EPROM Program Lock Protection mechanisms have been provided on the ROM and EPROM versions of the 8X9X to inhibit unauthorized accesses of internal program memory However there must always be a way to allow autho rized program memory dumps for testing purposes The following describes 8X9X lock features and the mode provided for authorized memory dumps 10 7 1 LOCK FEATURES Write protection is provided for EPROM devices while READ protection is provided for both ROM and EPROM devices Write protection is enabled by causing the LOCO bit in the CCR to take the value 0 When WRITE protection is selected the bus controller will cycle through the write sequence but will not actually drive data to the EPROM and will not enable Vpp to the EPROM This protects the entire EPROM locations 2000H 3FFFH MM EE CCB 1 0 PCCB 1 0 RD WR RD WR Protection Lock Lock Lock Lock 1 1 1 Array is unprotected ROM Dump Mode and all programming modes are allowed Array is read protected Run time programming and ROM Dump Mode with security k
50. in the same time frame it is possible that multiple software timer interrupts will be generated Each read or test of any bit in IOS1 will clear bits 0 through 5 Be certain to save the byte before testing it unless you are only concerned with 1 bit See also Sec tion 11 5 A complete listing of the functions of IOSO IOS1 and 1 can be found in Section 11 The Timers are de scribed in Section 5 and the HSI is described in Section 6 1 36 8 0 ANALOG INTERFACE The 8X9X can easily interface to analog signals using its Analog to Digital Converter and its Pulse Width Modulated PWM output and HSO Unit There are 8 inputs to the 10 bit to D converter on the 8X9XBH and 8X9XJF There are 4 inputs on the 8X98 The PWM and HSO units provide digital signals which can be filtered for use as analog outputs 8 1 Analog Inputs A to D conversion is performed on one input at a time using successive approximation with a result equal to the ratio of the input voltage divided by the analog supply voltage If the ratio is 1 00 then the result will be all ones The A D converter is available on selected members of the MCS 96 family See Section 14 for the device selection matrix Each conversion on the 8X9X requires 88 state times 22 us at 12 MHz independent of the accuracy desired or value of input voltage The input voltage must be in the range of 0 to Vg gr the analog reference and supply voltage For proper operation Vpgr the
51. low XX0000B Figure 43 Bus Control Pins Reset Status HSO Lines It is important to note that the Stack Pointer and Inter rupt Pending Register are undefined and need to be initialized in software The Interrupts are disabled by both the mask register and PSW 9 after a reset 13 3 Reset Sync Mode The RESET line can be used to start the 8X9X at an exact state time to provide for synchronization of test equipment and multiple chip systems RESET is active low To synchronize devices RESET is brought high on the rising edge of XTAL1 Complete details on syn chronizing devices can be found in Section 1 5 of the Hardware Design chapter It is very possible that devices which start in sync may not stay that way The best example of this would be when a jump on I O bit is being used to hold the processor in a loop If the line changes during the time it is being tested one processor may see it as a one while the other sees it as a zero The result is that one processor will do an extra loop thus putting it several states out of sync with the other intel MCS 96 8X9X ARCHITECTURAL OVERVIEW Power Supply Rise Time 5 5Vpc 4 5 111 External to Internal Release Time 50 0 50 5 2 0 2 5 T des ADDRESS HDATAH ADDRESS ccs 10XTAL CYCLES FIRST BUS FETCH CYCLE External RESET Low to Port Valid Time RESET FUNCTION REGISTERS TOTAL 8X9XJF RESET TIME Figure 44 TRLPV 270250 43
52. many as 16 slaves However a Data Verify Command does not have to follow every Data Program Com mand WORD DUMP COMMAND When the Word Dump Command is issued 879X being pro grammed adds 2000H to the address field of the com mand and places the value found at the new address on Ports 3 and 4 For example when the slave receives the command 0100 it will place the word found at lo cation 2100H on Ports 3 and 4 PROG from the pro grammer governs when the slave drives the bus The signals are the same as shown in Figure 22 Note that this command only works when a single slave is attached to the bus and that there is no restriction on commands that precede or follow a Word Dump Com mand 10 5 2 GANG PROGRAMMING WITH THE SLAVE PROGRAMMING MODE Gang programming of 879Xs can be done using the Slave Programming Mode There is no 879X based lim it on the number of chips that may be hooked to the same Port 3 Port 4 data path for gang programming If more than 16 chips are being gang programmed the PVER and PDO outputs of each chip can be used for verification The master programmer can issue a data program command and then either watch every chip s error signals or AND all the signals together to get a system PVER and PDO If 16 or fewer 879Xs are to be gang programmed at once a more flexible form of verification is available by 2 39 270246 38 giving each chip being programmed a unique SID The master pr
53. may then be incremented to one before the HSO CAM entry can be read and acted upon This can be avoided by setting the event to occur when Timer 2 is equal to one This method will ensure that there is enough time for the CAM entry recogni tion The same asynchronous nature can affect events sched uled to occur at the same time as an internal Timer 2 reset These events should be logged into the CAM with a Timer 2 value of zero When using this method to make a programmable modulo counter the count will stay at the maximum Timer 2 value only until the Reset T2 command is recognized The count will stay at zero for the transition which would have changed the count from to zero and then changed to a one on the next transition 7 5 Software Timers The HSO can be programmed to generate interrupts at preset times Up to four such Software Timers can be in operation at a time As each preprogrammed time is reached the HSO unit sets a Software Timer Flag If the interrupt bit in the command tag was set then a Software Timer Interrupt will also be generated The interrupt service routine can then examine I O Status register 1 1051 to determine which software timer expired and caused the interrupt When the HSO resets Timer 2 or starts an to D conversion it can also be programmed to generate a software timer interrupt but there is no flag to indicate that this has occurred If more than one software timer interrupt occurs
54. of 8 events were be stored by considering the holding regis ter part of the FIFO If the FIFO and holding register are full any additional events will cause an overflow condition Any eight consecutive events will overflow on the ninth event if the program does not clear all entries in the FIFO before the ninth event occurs Some versions of the 8X9X have errata associated with the HSI unit See the data sheets for more information 6 3 HSI Interrupts Interrupts can be generated by the HSI unit in three ways two FIFO related interrupts and O to 1 tran sitions on the HSLO pin The HSI O pin can generate interrupts even if it is not enabled to the HSI FIFO Interrupts generated by this pin cause a vector through location 2008H The FIFO related interrupts are con trolled by bit 7 of I O Control Register 1 IOC1 7 If the bit is a 0 then an interrupt will be generated every time a value is loaded into the holding register If it is a 1 an interrupt will only be generated when the FIFO independent of the holding register has six entries in it Since all interrupts are rising edge triggered if 7 1 the processor will not be re interrupted until the FIFO first contains 5 or less records then contains six or more 6 4 HSI Status Bits 6 and 7 of the I O Status register 1 1051 indicate the status of the HSI FIFO If bit 6 is a 1 the FIFO contains at least six entries If bit 7 is a 1 the FIFO contains at least 1 entr
55. provide bus control signals of several types Three control lines have dual functions designed to reduce external hardware Bits 2 and 3 of the CCR specify the functions per formed by these control lines Figures 12 15 show the signals which can be modified by changing bits in the CCR all other lines will operate as shown in Figure 9 00 15 ADDR DATA OUT 270250 11 16 Bit Bus Cycle Standard Bus Control If CCR bits 2 and 3 are 1s then the standard 8X9X control signals WR BHE and ALE are provided Fig ure 12 WR will come out for every write BHE will be valid throughout the bus cycle and can be combined with WR and address line 0 to form WRL and WRH ALE will rise as the address starts to come out and will fall to provide the signal to externally latch the address AD8 15 ADDRESS HIGH 270250 12 8 Bit Bus Cycle Figure 12 Standard Bus Control Write Strobe Mode The Write Strobe Mode eliminates the necessity to ex ternally decode for odd or even byte writes If CCR bit 2 is a 0 and the bus is in a 16 bit cycle WRL and WRH signals are provided in place of WR and BHE Figure 13 WRL will go low for all byte writes to an even address and all word writes WRH will go low for all byte writes to an odd address and al word writes Write Strobe Mode is particularly well suited to memo ry systems latching data on the falling edge of WRITE WRL is provided for all 8 bit bus write cycles ADDR DATA OUT
56. rounding after a right shift Consider multiplying two eight bit quantities and then scaling the result down to 12 bits AX CL DL SHR 4 CL DL Shift right 4 places If the C flag is set after the shift it indicates that the bits shifted off the end of the operand were greater than or equal to one half the least significant bit LSB of the result If the C flag is clear after the shift it indicates that the bits shifted off the end of the operand were less than half the LSB of the result Without the ST flag the rounding decision must be made on the basis of this information alone Normally the result would be rounded up if the C flag is set The ST flag allows a finer resolution in the rounding decision Value of the Bits Shifted Off 0 lt Value lt 1 2 LSB 10 Value 72158 Value gt Ye LSB Figure 17 Rounding Alternatives Imprecise rounding can be a major source of error in a numerical calculation use of the ST flag improves the options available to the programmer 3 4 Instruction Set The MCS 96 instruction set contains a full set of arith metic and logical operations for the 8 bit data types BYTE and SHORT INTEGER and for the 16 bit data types WORD and INTEGER The DOUBLE WORD and LONG data types 32 bits are supported for the products of 16 by 16 multiplies and the dividends of 32 intel MCS 96 8X9X ARCHITECTURAL OVERVIEW by 16 divides and for shift operat
57. selectively pro gramming 05 into the desired bit locations Although only 06 will be programmed both 15 and 05 can be present in the data word The only way to change a 0 to a is by ultraviolet light erasure Erasing begins upon exposure to light with wavelengths shorter than approximately 4000 Angstroms A It should be noted that sunlight and certain types of fluo rescent lamps have wavelengths in the 3000 4000 A range Constant exposure to room level fluorescent lighting could erase the typical 879X in approximately 3 years while it would take approximately 1 week to cause erasure when exposed to direct sunlight If the 879X is to be exposed to light for extended periods of time opaque labels must be placed over the EPROM s window to prevent unintentional erasure The recommended erasure procedure for the 879X is exposure to shortwave ultraviolet light which has a wavelength of 2537A The integrated dose UV tensity X exposure time for erasure should be a mini mum of 15 Wsec cm2 The erasure time with this dos age is approximately 15 to 20 minutes using an ultravi olet lamp with 12000 W cm power rating The 879X should be placed within 1 inch of the lamp tubes during erasure The maximum integrated dose an 879X can be exposed to without damage is 7258 Wsec cm 1 week 12000 cm Exposure of the 879X to high intensity UV light for long periods may cause perma nen
58. specified range to affect full scale error Other factors that affect a real A D Converter system include sensitivity to temperature failure to completely reject all unwanted signals multiplexer channel dissim ilarities and random noise Fortunately these effects are small Temperature sensitivities are described by the rate at which typical specifications change with a change in temperature Undesired signals come from three main sources First noise on Rejection Second input signal changes on the channel being converted after the sam ple window has closed Feedthrough Third signals applied to channels not selected by the multiplexer Off Isolation Finally multiplexer on channel resistances differ slight ly from one channel to the next causing Channel to Channel Matching errors and random noise in general results in Repeatability errors 8X9X HARDWARE DESIGN INFORMATION 91 9 204c 8s1 SIC HLOIM 3009 3 1 SNOILISNVYL 3002 N33A4138 39NYHO 39V110A 3HL 5857 39V110A 1ndNI 851 2 1 OL Si 39VLIOA O3llddV JHL N3HM 540220 NOILISNVYL 33002 15414 83183ANOO G V 1 301 NY 30 OlLSIH310Y3YHO 1VhnioV gs13 2 1 1924 01 1vno3 5 JHL 31990 3009 1YNIJ Figure 15 Ideal A D Characteristi 2 16 8X9X HARDWARE DESIGN INFORMATION 1 9720 6 IVNLIY 30343 3195
59. term reliability It is further recommended that any de vice used in this way for more than several seconds not be used in production versions of products Section 1 6 of the Hardware Design chapter has more information on disabling the Watchdog Timer 13 0 RESET 13 1 Reset Signal As with all processors the 8X9X must be reset each time the power is turned on This is done by holding the RESET pin low for at least 2 state times after the power supply is within tolerance and the oscillator has stabi lized See Figure 44 TRLPV After the RESET pin is brought high a ten state reset sequence is executed During this time the Chip Con figuration Byte CCB is read from location 2018H and written to the 8X9X Chip Configuration Register CCR If the voltage on the EA pin selects the inter nal external execution mode the CCB is read from in ternal ROM EPROM If the voltage on the EA pin selects the external execution only mode the CCB is read from external memory intel The 8X9X can be reset using a capacitor 1 shot or any other method capable of providing a pulse of at least 2 state times longer than required for and the oscil lator to stabilize For best functionality it is suggested that the reset pin be pulled low with an open collector device In this way several reset sources can be wire ORed together Remember the RESET pin itself can be a reset source when the RST instruction is executed or when the Watc
60. type Note that the indirect ad dress can refer to an operand anywhere within the ad dress space of the 8X9X including the register file The Examples LD AX AX ADDB AL BL CX POP AX register which contains the indirect address is selected by an eight bit field within the instruction An instruc tion can contain only one indirect reference and the remaining operands of the instruction if any must be register direct references lt WORD AL BL MEM_BYTE CX MEM_WORD MEM_WORD SP SP SP 2 MCS 96 8X9X ARCHITECTURAL OVERVIEW INDIRECT WITH AUTO INCREMENT REFERENCES This addressing mode is the same as the indirect mode except that the WORD variable which contains the in direct address is incremented after it is used to address the operand If the instruction operates on BYTES or Examples LD ADDB AL BL PUSH AX SHORT INTEGERS the indirect address variable will be incremented by one if the instruction operates on WORDS or INTEGERS the indirect address variable will be incremented by two AX zMEM WORD BX BX BX 2 AL BL MEM_BYTE CX CX CX 1 SP SP 2 SP MEM_WORD 2 IMMEDIATE REFERENCES This addressing mode allows an operand to be taken directly from a field in the instruction For operations on BYTE or SHORT INTEGER operands this field is eight bits wide for operations on WORD or Ex
61. 0 0 HSI 0 HSI 060 2 HSI 1 T2CLK 060 7 060 4 51 2 10 0 6 51 5 HSI TIMER2 CLOCK HSI HSI 270246 57 1050 15H 50 0 CURRENT STATE HSO 1 CURRENT STATE HSO 2 CURRENT STATE HSO 3 CURRENT STATE HSO 4 CURRENT STATE 50 5 CURRENT STATE CAM HOLDING REGISTER IS FULL HSO HOLDING REGISTER IS FULL Do 270246 58 2 56 8X9X HARDWARE DESIGN INFORMATION 16H SELECT PWM SELECT P2 5 EXTERNAL INTERRUPT ACH7 EXTINT TIMER 1 OVERFLOW INTERRUPT ENABLE DISABLE TIMER 2 OVERFLOW INTERRUPT ENABLE DISABLE HSO 4 OUTPUT ENABLE DISABLE SELECT TXD SELECT P2 0 50 5 OUTPUT ENABLE DISABLE HSI INTERRUPT FIFO FULL HOLDING REGISTER LOADED 270246 59 Vector Location Location Vector High Low Priority Byte Byte Software Trap Extint Serial Port Software Timers HSI 0 High Speed Outputs HS Data Available A D Conversion 2003H Complete Timer Overflow 2001H 0 Lowest 1051 16H SOFTWARE TIMER EXPIRED SOFTWARE TIMER 1 EXPIRED SOFTWARE TIMER 2 EXPIRED SOFTWARE TIMER 3 EXPIRED TIMER 2 HAS OVERFLOW TIMER 1 HAS OVERFLOW HSI FIFO IS FULL HSI HOLDING REGISTER DATA AVAILABLE 27024660 E B E 5 6 Chip Configuration RESERVED Set to 1 for compatibility with future parts BUS WIDTH SELECT 16 BUS 8 BIT BUS WRITE STROBE MODE SELECT WR AND BHE WRL AND
62. 1 48 8X9X Hardware Design Information November 1990 8X9X HARDWARE DESIGN INFORMATION 8X9X HARDWARE DESIGN INFORMATION CONTENTS PAGE OVERVIEW 2 3 1 0 REQUIRED HARDWARE CONNECTIONS 2 3 1 1 Power Supply Information 2 3 1 2 Other Needed Connections 2 3 1 3 Oscillator Information 2 3 1 4 Reset Information 2 5 1 5 Sync Mode 2 8 1 6 Disabling the Watchdog Timer 2 8 1 7 Power Down Circuitry 2 9 2 0 DRIVE AND INTERFACE LEVELS desea ona Deal d 2 9 2 1 Quasi Bidirectional Ports 2 9 2 2 Quasi Bidirectional Hardware Connections 2 9 2 3 Input Only Ports 2 11 2 4 Open Drain Ports 2 11 2 5 HSO Pins Control Outputs and PINS o 2 12 3 0 ANALOG INPUTS 2 12 3 1 A D Overview 2 13 3 2 A D Interface Suggestions 2 13 3 3 Analog References 2 14 3 4 The A D Transfer Function 2 14 3 5 A D Glossary of Terms 2 19 4 0 ANALOG OUTPUTS 2 20 5 0 170 TIMINGS 2 21 5 1 HSO Outputs 2 21 5 2 HSI Input Sampling 2 21 5 3 Standard I O Port Pins 2 22 6 0 SERIAL PORT TIMINGS 2 22 6 1 Mode Q
63. 10 1 8X9X QUICK REFERENCE 2 0 SFR BIT SUMMARY A D Result LO 02H 0 CHANNEL NUMBER STATUS 0 A D CURRENTLY IDLE X 1 z CONVERSION IN PROCESS x A D RESULT LEAST SIGNIFICANT 2 BITS 272110 2 HSI_Mode 03H 2 HSI 0 MODE HSI 1 MODE 51 2 MODE 51 5 MODE WHERE EACH 2 MODE CONTROL FIELD OEFINES ONE OF 4 POSSIBLE MODES 00 8 POSITIVE TRANSITIONS 01 EACH POSITIVE TRANSITION 10 EACH NEGATIVE TRANSITION 11 EVERY TRANSITION POSITIVE AND NEGATIVE 272110 3 HSO Command 06H CHANNEL 0 5 50 0 HS0 5 BIT 6 50 0 AND 50 7 50 2 AND HSO 3 8 8 SOFTWARE TIMERS E RESET TIMER2 F START A D CONVERSION INTERRUPT NO INTERRUPT SET CLEAR 2 TIMER 1 X 272110 4 5 Status 06H 5 2 51 0 STATUS HSI 1 STATUS HSi 2 STATUS HSI 3 STATUS WHERE FOR EACH 2 STATUS FIELO THE LOWER BIT INDICATES WHETHER OR NOT AN EVENT HAS OCCURRED ON THIS PIN AND THE UPPER BIT INDICATES THE CURRENT STATUS OF THE PIN 272110 5 A D Command 02H CHANNEL SELECTS WHICH OF THE 8 ANALOG INPUT CHANNELS IS TO BE CONVERTEO TO DIGITAL FORM GO INDICATES WHEN THE CONVERSION 1S TO BE INITIATEO GO MEANS START NOW 60 0 MEANS THE CONVERSION IS TO BE INITIATED BY THE HSO UNIT AT A SPECIFIEO TIME RSV RESERVED BITS MUST BE WRITTEN AS 0 272110 6 SPCON SPSTAT
64. 2048 bits in the register file 7 The L Long suffix indicates double word operation 8 Initiates a Reset by pulling RESET low Software should re initialize all the necessary registers with code starting at 2080H 9 The assembler will not accept this mnemonic 2 51 intel 8X9X HARDWARE DESIGN INFORMATION 11 7 Opcode and State Time Listing INDIRECTO nr imer BYTES STATE TIMES OPCODE BYTES OPERANDS OPCODE STATE TIMES OPCODE BYTES aoo 2 641 3 4 65 4 5 eu 3 712 67141 eu s 72 aoo 44 4 as s 46 4 7 2 a 47 5 712 6 apog 2 74 3 4 75 3 4 712 4 s 712 3 54 4 5 54 56 4 712 57 712 6 anoc 2 A s 4 asja 5 3 en 712 arja on s 712 ADDCB 2 3 4 5 3 4 3 en 712 87 4 ew s 72 sus 2 68 3 ejaj 5 eu 3 712 eu s 712 sus sfasa s 14915 6 safaf 4 5 712 e sns jum i278 3 4 4 eu 3 712 78 4 en s 712 sues 3 58 41 5 soja 5 sala sp s 712 6 813 susc 2 3 4 Jasja 5 3 eu 712 4 s 712 SUBCB 2 3 4 en 712 4 en s 712 cme 2 se s 4 94 s sais en 712 a ew s 712 emes 2 98 3
65. 3 OPS ANDB IMMEDIATE 3 OPS ANDB INDIRECT 3 OPS ANDB INDEXED 3 OPS ADDB DIRECT 3 OPS ADDB IMMEDIATE 3 OPS ADDB INDIRECT 3 OPS ADDB INDEXED 3 OPS SUBB DIRECT 3 OPS SUBB IMMEDIATE 3 OPS SUBB INDIRECT 3 OPS SUBB INDEXED 3 OPS MULUB DIRECT 3 OPS MULUB IMMEDIATE 3 OPS MULUB INDIRECT 3 OPS MULUB INDEXED 3 OPS AND DIRECT 2 OPS AND IMMEDIATE 2 OPS AND INDIRECT 2 OPS AND INDEXED 2 OPS ADD DIRECT 2 OPS ADD IMMEDIATE 2 OPS ADD INDIRECT 2 OPS ADD INDEXED 2 OPS 8X9X QUICK REFERENCE 6 0 OPCODE TABLE Continued SUB DIRECT 2 OPS SUB IMMEDIATE 2 OPS SUB INDIRECT 2 OPS SUB INDEXED 2 OPS MULU DIRECT 2 OPS MULU IMMEDIATE 2 OPS MULU INDIRECT 2 OPS MULU INDEXED 2 OPS ANDB DIRECT 2 OPS ANDB IMMEDIATE 2 OPS ANDB INDIRECT 2 OPS ANDB INDEXED 2 OPS ADDB DIRECT 2 OPS ADDB IMMEDIATE 2 OPS ADDB INDIRECT 2 OPS ADDB INDEXED 2 OPS SUBB DIRECT 2 OPS SUBB IMMEDIATE 2 OPS SUBB INDIRECT 2 OPS SUBB INDEXED 2 OPS MULUB DIRECT 2 OPS MULUB IMMEDIATE 2 OPS MULUB INDIRECT 2 OPS MULUB INDEXED 2 OPS OR DIRECT OR IMMEDIATE OR INDIRECT OR INDEXED XOR DIRECT XOR IMMEDIATE XOR INDIRECT XOR INDEXED CMP DIRECT CMP IMMEDIATE CMP INDIRECT CMP INDEXED DIVU DIRECT DIVU IMMEDIATE DIVU INDIRECT DIVU INDEXED ORB DIRECT ORB IMMEDIATE ORB INDIRECT ORB INDEXED XORB DIRECT XORB IMMEDIATE XORB INDIRECT XORB INDEXED CMPB DIRECT CMPB IMM
66. 4 9 3 4 9 131 3 7 2 98 4 en fs 712 eee ee ea ae p 2 3 25 6014 2732 3 2833 oF 4 2732 s 2833 Mutu 26 4p s 27 2833 4 2934 5 2833 6 29734 Murus 2 72 3 17 713 17 7 3 1924 3 2025 7F 4 1924 5 20725 MULUB 3 sc 18 5 4 18 se 4 2025 4 2026 5 2025 6 2126 2 2 o s o 4 31136 3237 5 6 3237 MUL 4214 9 fots 12151 nsr 7 noe 2 O9 4 4 2328 a 2429 5 2328 6 2429 tols 2 oso o 5 s 2590 2 sc3 25 2832 3 2933 4 2832 5 29 33 2 9c 3 17 3 17 E 3 20 24 3 225 oF 4 2024 5 2125 29 5 a 3236 3337 5 3236 6 3337 4 21 4 228 a 2529 5 2428 6 25 29 270246 63 NOTES Long indexed and Indirect instructions have identical opcodes with Short indexed and Indirect modes respectively The second byte of instructions using any Indirect or indexed addressing mode specifies the exact mode used If the second byte is even use Indirect or Short indexed If it is odd use Indirect or Long indexed In all cases the second byte of the instruction always specifies an e
67. 5 UMP 1 1 lt ______ 5 Sra SCALL 1 SP lt SP 2 SP lt PC lt 11 bit offset LCALL 1 SP SP 2 SP PC 16 bit offset gr o 1 4 1 26 PC ebtoftectittaxes 3 mc 5 hg NOTES 1 If the mnemonic ends in B a byte operation is performed otherwise a word operation is done Operands D B and A must conform to the alignment rules for the required operand type D and B are locations in the Register File A can be located anywhere in memory 2 D D 2 are consecutive WORDS in memory D is DOUBLE WORD aligned 3 D D 1 are consecutive BYTES in memory D is WORD aligned 4 Changes a byte to a word 5 Offset is a 2 s complement number intel 8X9X HARDWARE DESIGN INFORMATION ands peration Note 1 PINE 1 1 2 GLEA CE OE MGG JumpifN OandZ 0 wmiN 1 2 1 185 11 wmetc iadz 0 ____ 5 NH 1 092 1 5 TT E EIE DN dero 8 eg 5 TUENDIS NNI eee JNT 1 lt 0 0 5 or just _______ 2 2 12121 6 Jc 3
68. 5 AD6 P3 6 AD7 P3 7 AD8 P4 0 09 4 1 010 4 2 AD11 P4 3 AD12 P4 4 AD13 P4 5 AD14 P4 6 AD15 P4 7 T2CLK P2 3 8797BH ps 68 25 62 LEADLESS CHIP CARRIER 24 TYPE B RXD P2 1 PALE TXD P2 0 PVER SALE P1 0 P1 1 P1 2 1 5 1 4 HSI 0 HSI 1 HSO 4 HSI 2 TOP VIEW LOOKING DOWN ON 18 57 COMPONENT SIDE 29 56 OF PC BOARD 30 2i gt eo gt an 45 44 43 42 41 40 3 a M o ams LI LI LJ LI LJ ONM gt 2 gt 4 X gu I o o N I PWM P2 5 PDO SPROG 272110 16 8X9X QUICK REFERENCE In p Se a ooo T gt 5 N D gt lt mnm 55555 5 lt lt lt lt lt 5 9k kom lt 111 11 8 7 6 5 43 2 1 ACHS PO 5 PMOD 1 10 AD0 P3 0 o o o o o o ACH4 P0 4 PMOD 0 1 59 AD1 P3 1 12 581 AD2 P3 2 13 8X96BH 57 1 AD3 P3 3 14 8X97BH 56 04 3 4 15 8X97JF 553 AD5 P3 5 16 68 PIN 54 L3 4D6 P3 6 RXD P2 1 PALE 17 5 AD7 P3 7 TXD P2 0 PVER SALE 18 521 08 4 0 19 51 AD9 P4
69. 5 5 5 lojojo 019 c wn c 5 1 w gt lt 1 SUBC SUBCB MUL MULU DIVUB 2 PUSH PUSHF POPF SJMP v gt DO 2 lt D A D D 2 lt 0 0 1 lt D A 0 1 lt D D 2 0 2 lt remainder D lt D D 1 A D 1 lt lt remainder D lt D D 2 0 2 lt remainder D lt D D 1 A D 1 lt lt remainder D lt DandA D BandA DorA D D excl A D A D D 6 1 lt SIGN A 1 SP lt SP 2 SP lt lt SP SP lt SP 2 SP SP 2 SP lt PSW PSW 0000H PSW lt SP SP lt SP 2 lt PC 11 bit offset 1 PC 16 bit offset lt A SCALL 1 SP lt SP 2 SP lt PC PC PC 11 bit offset LCALL SP lt SP SP PC 16 bit offset SP SP lt SP 2 c c c o gt lt Clo z c qu gt 1 aek E M pepe te gt gt 3 20 intel 8X9X QUICK REFERENCE 7 0 INSTRUCTION SUMMARY Continue
70. ARCHITECTURAL OVERVIEW NORMAL CYCLE 270250 42 Figure 9A multiplex the bus A typical circuit and the required timings are shown in Section 7 of the Hardware Design chapter Since the 8X9X s external memory can be ad dressed as either bytes or words the decoding is con trolled with two lines Bus High Enable BHE and Address Data Line 0 ADO To avoid confusion during the explanation of the mem ory system it is reasonable to give names to the demulti plexed address data signals The address signals will be called MAO through 15 Memory Address and the data signals will be called MDO through MD15 Memory Data When is active low the memory connected to the high byte of the data bus should be selected When is low the memory connected to the low byte of the data bus should be selected In this way accesses to a 16 bit wide onamory can be to the low even byte only MA0 0 BHE 1 to the high odd byte only MAO 1 BHE 0 or to both bytes 0 BHE 0 When a memory block is being used only for reads BHE and MAO need not be decoded TIMINGS Figure 9 shows the idealized waveforms related to the following description of external memory manipula tions For exact timing specifications please refer to the latest data sheet When an external memory fetch be gins the address latch enable ALE line rises the ad dress is put on ADO AD15 and is set to the re quired state A
71. Channel 0 triggers it The A D command regis ter must be written to for each conversion even if the HSO is used as the trigger A to D commands are for matted as shown in Figure 30 A D Command Register LOCATION 02H MCS 96 8X9X ARCHITECTURAL OVERVIEW The command register is double buffered so it is possi ble to write a command to start a conversion triggered by the HSO while one is still in progress Care must be taken when this is done since if a new conversion is started while one is already in progress the conversion in progress is cancelled and the new one is started When a conversion is started the result register is cleared For this reason the result register must be read before a new conversion is started or data will be lost 8 3 A D Results Results of the analog conversions are read from the A D Result Register at locations 02H and 03H Al though these addresses are on a word boundary they must be read as individual bytes Information in the A D Result register is formatted as shown in Figure 31 Note that the status bit may not be set until 8 state CHANNEL SELECTS WHICH OF THE 8 ANALOG INPUT CHANNELS IS TO BE CONVERTED TO DIGITAL FORM GO INDICATES WHEN THE CONVERSION 1 TO BE INITIATED GO 1 MEANS START NOW GO 0 MEANS THE CONVERSION IS TO INITIATED BY THE HSO UNIT AT A SPECIFIED TIME 270250 29 Figure 30 A D Command Register RESULT REGISTER LOCATION 03H LOCATION 02H A D
72. D CONVERSION INTERRUPT NO INTERRUPT SET CLEAR TIMER 2 TIMER 1 270250 28 Figure 29 HSO Command Tag Format 1 35 MCS 96 8X9X ARCHITECTURAL OVERVIEW 7 2 HSO Status Before writing to the HSO it is desirable to ensure that the Holding Register is empty If it is not writing to the HSO will overwrite the value in the Holding Register I O Status Register 0 IOSO bits 6 and 7 indicate the status of the HSO unit This register is described in Section 11 If IOSO 6 equals 0 the holding register is empty and at least one CAM register is empty If IOSO 7 equals 0 the holding register is empty The programmer should carefully decide which of these two flags is the best to use for each application 7 3 Clearing the HSO All 8 CAM locations of the HSO are compared before any action is taken This allows a pending external event to be cancelled by simply writing the opposite event to the CAM However once an entry is placed in the CAM it cannot be removed until either the speci fied timer matches the written value or the chip is reset If as an example a command has been issued to set HSO 1 when TIMER 1 1234 then entering a second command which clears HSO 1 when TIMER 1 1234 will result in no operation on HSO 1 Both commands will remain in the CAM until TIMER 1 1234 Internal events are not synchronized to Timer 1 and therefore cannot be cleared This includes events on HSO channels 8 through F and all
73. DE HSI 1 MODE 1 2 MODE 5 5 MODE WHERE EACH 2 MODE CONTROL FIELD DEFINES ONE OF 4 POSSIBLE MODES 00 8 POSITIVE TRANSITIONS Baud Rate Calculations 01 EACH POSITIVE TRANSITION 10 EACH NEGATIVE TRANSITION 11 EVERY TRANSITION POSITIVE AND NEGATIVE Using XTAL1 Baud _ XTAL1 frequency Mode 0 Rate 4 B 1 B 0 270246 51 Baud _ XTAL1 frequency Others Rate 64 B 1 HSO Command 06H Using T2CLK CHANNEL 0 5 50 0 HSO 5 6 650 0 AND HSO 1 7 50 2 AND HSO 3 8 B SOFTWARE TIMERS E RESET TIMER2 F START A D CONVERSION INTERRUPT NO INTERRUPT SET CLEAR TIMER 2 TIMER 1 X Baud _ T2CLK frequency Mode 0 Baud _ T2CLK frequency Others Rate zep 970 Note that B cannot equal 0 except when using XTALI in other than Mode 0 Status 06H gt 3 2 1 5 0 STATUS HSi 1 STATUS HSI 2 STATUS HSI 3 STATUS WHERE FOR EACH 2 BIT STATUS FIELD THE LOWER BIT INDICATES WHETHER OR NOT AN EVENT HAS OCCURED ON THIS PIN AND THE UPPER BIT INDICATES THE CURRENT STATUS OF THE PIN 270246 55 270246 52 2 55 1 15H HSI O INPUT ENABLE DISABLE TIMER 2 RESET EACH WRITE HSI 1 INPUT ENABLE DISABLE TIMER 2 EXTERNAL RESET ENABLE DISABLE 1 2 INPUT ENABLE DISABLE TIMER 2 RESET SOURCE HSI 0 T2RST HSI 3 INPUT ENABLE DISABLE TIMER 2 CLOCK SOURCE HSI 1 T2CLK 270246 56 IOCO 15H T2RST O 1000 5 T2 RESET 10 0 5 10
74. E 173 e JUMPS AND CALLS wNEMONIC evres states mnemonic BYTES STATES ui m o o x e Ole g s jE mes sme moe 2 s seau 2 ineo pu s jer _ 1 mie 272110 21 emo o 1_ TRAP The least significant 3 bits of the opcode are concatenated with the following 8 bits to form an 11 bit 2 s complement Number of state times shown for internal external operands offset for the relative call or jump G The assembler does not accept this mnemonic State times for stack located internal external State times shown for 16 bit bus NOTES 3 24 intel 8X9X QUICK REFERENCE 8 0 OPCODES INSTRUCTION LENGTH AND STATE TIMES Continued CONDITIONAL JUMPS LOOP CONTROL MNEMONIC OPCODE BYTES STATE TIMES DJNZ EO a 5 9 5 NOT SINGLE REGISTER INSTRUCTIONS 3 25 8X9X QUICK REFERENCE intel 8 0 OPCODES INSTRUCTION LENGTH AND STATE TIMES Continued SPECIAL CONTROL INSTRUCTIONS MNEMONIC orcobe STATES ec e NORMALIZE MNEMONIC OPCODE BYTES STATE TIMES NORML oF 11 1 PER SHIFT NOTES 6 This instruction takes 2 states to pull RESET low then holds it low for at
75. EA pin is latched on RESET rising Information on programming EPROMs can be found in Section 10 of the Hardware Design chapter Do not execute code out of the last three locations of internal ROM EPROM inte 2 6 internal Executable RAM XRAM 8X9XJF only Locations 0100H through 01 8X9XJF only con tain the internal executable RAM space In struction fetches will be performed in this region if the program counter points to the addresses 0100H through Data accesses can also be performed from this region The XRAM is accessed and executed from as if it were external RAM that is contained on chip No external bus signals wil be generated when accessing the XRAM The XRAM is not part of the Register File 8 bit direct addressing can not be used on this address space 2 7 Memory Controller The RALU talks to the memory except for the loca tions in the register file and SFR space through the memory controller which is connected to the RALU by the A Bus and several control lines Since the A Bus is eight bits wide the memory controller uses a Slave Pro gram Counter to avoid having to always get the instruc tion location from the RALU This slave PC is incre mented after each fetch When a jump or call occurs the slave PC must be loaded from the A Bus before instruction fetches can continue MCS 96 8X9X ARCHITECTURAL OVERVIEW In addition to holding a slave PC the memory control ler c
76. EDIATE CMPB INDIRECT CMPB INDEXED 3 18 DIVUB DIRECT DIVUB IMMEDIATE DIVUB INDIRECT DIVUB INDEXED LD DIRECT LD IMMEDIATE LD INDIRECT LD INDEXED ADDC DIRECT ADDC IMMEDIATE ADDC INDIRECT ADDC INDEXED SUBC DIRECT SUBC IMMEDIATE SUBC INDIRECT SUBC INDEXED LDBZE DIRECT LDBZE IMMEDIATE LDBZE INDIRECT LDBZE INDEXED LDB DIRECT LDB IMMEDIATE LDB INDIRECT LDB INDEXED ADDCB DIRECT ADDCB IMMEDIATE ADDCB INDIRECT ADDCB INDEXED SUBCB DIRECT SUBCB IMMEDIATE SUBCB INDIRECT SUBCB INDEXED LDBSE DIRECT LDBSE IMMEDIATE LDBSE INDIRECT LDBSE INDEXED ST DIRECT RESERVED ST INDIRECT ST INDEXED STB DIRECT RESERVED STB INDIRECT STB INDEXED PUSH DIRECT PUSH IMMEDIATE PUSH INDIRECT PUSH INDEXED POP DIRECT RESERVED POP INDIRECT POP INDEXED 8X9X QUICK REFERENCE RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED LCALL RET RESERVED PUSHF POPF RESERVED RESERVED RESERVED TRAP CLRC RESERVED RESERVED BR INDIRECT RESERVED RESERVED RESERVED LUMP DIV DIVB MUL MULB RST Two Byte Instruction Opcodes which do not have a corresponding instruction wili not generate an interrupt if executed 3 19 a 8X9X QUICK REFERENCE intel 7 0 INSTRUCTION SUMMARY Oper ands Operation Note 1 o o E o vo D gt gt gt 0 gt gt gt
77. EXTERNAL MEMORY CHIP CONFIGURATION BYTE INTERRUPT VECTORS 2080H 2072H 207FH 2070H 2071H 2030H 206FH 2020H 202FH 201CH ZO1FH 201AH 2018H 2019H 2018H 2012H 2017H PORT 3 EXTERNAL MEMORY OR 1 0 EXTERNAL MEMORY OR 1 0 BX9XBH INTERNAL EXECUTABLE RAM XRAM 8X9XJF INTERNAL RAM REGISTER FILE STACK POINTER SPECIAL FUNCTION REGISTERS WHEN ACCESSED AS DATA MEMORY 270250 5 Figure 5 Memory Map 1 6 intel call to external location 0000H therefore the NMI and TRAP interrupt are also reserved for Intel development tools The RALU can operate on any of the 256 internal reg ister locations Locations 00H through 17H are used to access the SFRs Locations 18H and 19H contain the stack pointer These are not SFRs and may be used as standard RAM if stack operations are not being per formed The stack pointer must be initialized by the user program and can point anywhere in the 64K mem ory space The stack builds down There are no restric tions on the use of the remaining 230 locations except that code cannot be executed from them 2 2 Special Function Registers All of the I O on the 8X9X is controlled through the SFRs Many of these registers serve two functions one if they are read from the other if they are written to Figure 5 shows the locations and names of these regis ters A summary of the capabilities of each of these registers is shown in Figure 6 with complete descrip
78. EXTINT TIMER 1 OVERFLOW INTERRUPT ENABLE DISABLE TIMER 2 OVERFLOW INTERRUPT ENABLE DISABLE HSO 4 OUTPUT ENABLE DISABLE SELECT TXD SELECT P2 0 HSO 5 OUTPUT ENABLE DISABLE HSI INTERRUPT FIFO FULL HOLDING REGISTER LOADED 270250 38 Figure 39 1 Control Register 1 1OC 1 HSO 0 CURRENT STATE HSO 1 CURRENT STATE 50 2 CURRENT STATE HSO 3 CURRENT STATE HSO 4 CURRENT STATE 0 5 CURRENT STATE CAM OR HOLDING REGISTER IS FULL HSO HOLDING REGISTER 1 FULL 270250 39 Figure 40 Status Register 0 1050 1 45 MCS 96 8X9X ARCHITECTURAL OVERVIEW SOFTWARE TIMER O EXPIRED SOFTWARE TIMER 1 EXPIRED SOFTWARE TIMER 2 EXPIRED SOFTWARE TIMER 3 EXPIRED TIMER 2 HAS OVERFLOW TIMER 1 HAS OVERFLOW HSI FIFO IS FULL HSI HOLDING REGISTER DATA AVAILABLE 2 E n 5 270250 40 Figure 41 HSIO Status Register 1 IOS1 11 4 1 O Status Register 1 1051 1051 is located at O16H It contains status bits for the timers and the HSI O The positions of these bits are shown in Figure 41 Whenever the processor reads this register all of the time related flags bits 5 through 0 are cleared This applies not only to explicit reads such as LDB 1051 but also to implicit reads such as JB I0S1 5 Somewhere_else which jumps to somewhere__else if bit 3 of IOS1 is set In most cases this situation can best be handled by hav ing a byte in the register file which is used to maintain
79. Figure 14 Suggested A D Input Circuit 3 3 Analog References Reference supply levels strongly influence the absolute accuracy of the conversion For this reason it is recom mended that the ANGND pin be tied to the two Vss pins as close to the chip as possible with minimum trace length Bypass capacitors should also be used between and ANGND should be within about a tenth of a volt Ves should be well regulated and used only for the A D converter The Vggr supply can be between 4 5V and 5 5V and needs to be able to source around 5 mA Figure 6 shows all of these con nections 2 14 8X9X HARDWARE DESIGN INFORMATION Note that if only ratiometric information is desired VREF be connected to V In addition and ANGND must be connected even if the A D converter is not being used Remember that Port 0 receives its power from the and ANGND pins even when it is used as digital I O 3 4 The A D Transfer Function The conversion result is 10 bit ratiometric representa tion of the input voltage so the numerical value ob tained from the conversion will be INT 1023 Vin ANGND This produces a stair stepped transfer function when the output code is plotted versus input voltage see Fig ure 15 The resulting digital codes can be taken as simple ratiometric information or they can be used to provide information about absolute voltages or relat
80. Figure 2 RALU Block Diagram 1 4 intel MCS 96 8X9X ARCHITECTURAL OVERVIEW A separate incrementor is used for the PC however jumps must be handled through the ALU Two of the temporary registers have their own shift logic These registers are used for the operations which require logi cal shifts including Normalize Multiply and Divide The Lower Word register is used only when double word quantities are being shifted the Upper Word register is used whenever a shift is performed or as a temporary register for many instructions Repetitive shifts are counted by the 5 bit Loop Counter A temporary register is used to store the second oper and of two operand instructions This includes the mul tiplier during multiplications and the divisor during divisions To perform subtractions the output of this register can be complemented before being placed into the B input of the ALU The DELAY shown in Figure 2 is used to convert the 16 bit bus into an 8 bit bus This is required as all ad dresses and instructions are carried on the 8 bit A Bus Several constants such as 0 1 and 2 are stored in the RALU for use in speeding up certain calculations These come in handy when the RALU needs to make a 2 s complement number or perform an increment or decrement instruction 1 5 Internal Timing The 8X9X requires an input clock frequency of be tween 6 0 MHz and 12 MHz to function This frequen cy can be appli
81. HBX WRITE high to INST BHE AD8 15 Inactive Minimum time that the INST and BHE TCLVL CLOCKOUT low to ALE ADV low lines will be valid after WR goes high Also the mini help in deriving other timings Nominally 1 Tosc mum time that the upper eight address lines 8 bit bus mode will remain valid after WR goes high Nomi TLLCH ALE ADV low to CLKOUT high Used nally 1 Tosc to derive other timings nominally 1 Tosc period TWLWH WRITE low to WRITE high Write TLHLL ALE ADV high to ALE ADV low pulse width nominally 3 Tosc periods ALE ADV high time Useful in determining ALE ADV rising edge to ADDRESS valid time Nominal THLHH WRL WRH low to WRL WRH high ly 1 Tosc period for ALE and 1 Tosc for ADV with Write strobe signal pulse width Nominally 2 Tosc back to back bus cycles periods TAVLL ADDRESS valid to ALE ADV low TQVHL OUTPUT valid to WRL low Min Length of time ADDRESS is valid before ALE ADV imum time that OUTPUT data is valid prior to write falls Important timing for address latch circuitry strobes becoming active Needed for interfacing to Nominally 1 Tosc period memories that read data on the falling edge of write Nominally 1 Tosc TLLAX ALE ADV low to ADDRESS invalid Length of time ADDRESS is valid after ALE ADV TQVWH OUTPUT valid to WRITE high Time falls Important timing for address latch circuitry that the OUTPUT data is valid before WR is high Nominally 1 Tosc period No
82. ION 1 3 13 CPU BUSES nna 1 3 1 2 CPU Register File 1 4 1 3 RALU Control 1 4 14 eec reto Pu te means 1 4 1 5 Internal Timing 1 5 2 0 MEMORY SPACE 1 6 2 1 Register File 1 6 2 2 Special Function Registers 1 7 2 3 Power Down 1 7 2 4 Reserved Memory Spaces 1 9 2 5 Internal ROM and EPROM 1 9 2 6 Internal Executable RAM XRAM 8X9XJF Only 1 10 2 7 Memory Controller 1 10 2 8 System Bus 1 10 3 0 SOFTWARE OVERVIEW 1 17 3 1 Operand Types 1 17 3 2 Operand Addressing 1 18 3 3 Program Status Word 1 20 3 4 Instruction Set 1 21 3 5 Software Standards and Conventions 1 25 4 0 INTERRUPT STRUCTURE 1 26 4 1 Interrupt Control 1 28 4 2 Interrupt Priorities 1 28 4 3 Critical Regions 1 29 4 4 Interrupt Timing 1 30 50 TIMERS 1 31 5 1 1 31 o dos 1 31 5 3 Timer Interrupts 1 31 5 4 Timer Related Sections 1 32 6 0 HIGH SPEED INPUTS 1 32 6 1 Modes 1 33 6 2 HSI FIFO
83. LE then falls the address is taken off the pins and the RD Read signal goes low When RD falls external memory should present its data to the 8X9X READ The data from the external memory must be on the bus and stable for a minimum of the specified set up time before the rising edge of RD The rising edge of RD latches the information into the 8X9X If the read is for data the INST pin will be low when the address is valid if it is for an instruction the INST pin will be high during this time The 48 lead device does not have the INST pin The INST pin will be low for the Chip Configuration Byte and Interrupt Vector fetches WRITE Writing to externa memory requires timings that are similar to those required when reading from it The main difference 1 is that the write WR signal is used instead of the RD signal The timings are the same until the falling edge of the WR line At this point the 8 9 removes the address and places the data on the bus When the WR line goes high the data should be latched to the external memory In systems which can write to byte locations the ADO and BHE lines must be used to decode WR into WRite to Low byte WRL RL and WRite to High byte WRH signals INST is always low dur ing a write as instructions cannot be written The exact timing specifications for memory accesses can be found in the data sheet READY A ready line is available on the 8 9 to extend the width of the RD an
84. ON 270246 65 Shrink DIP Package 2 48 8X9X HARDWARE DESIGN INFORMATION 11 5 Memory Map POWER DOWN RAM INTERNAL REGISTER FILE RAM EXTERNAL MEMORY OR 1 0 STACK POINTER STACK POINTER EXTERNAL MEMORY OR 1 0 8X9XBH 8X98 INTERNAL PROGRAM STORAGE ROM EPROM OR EXTERNAL MEMORY OR 1 0 8X9XJF CONTROL INTERNAL PROGRAM STORAGE ROM EPROM OR RESERVED RESERVED EXTERNAL MEMORY 2080H RESERVED 2030H 207FH 2020H 202FH _______ 2014H 2018H 2019H 2018H 2012H 2017H INTERRUPT VECTORS PORT 4 SP STAT PORT 2 0 PORT 1 10 PORT 0 TIMER2 HI TIMER2 LO TIMER1 HI TIMER1 LO INT PENDING INT MASK SBUF RX STATUS SP_CON 10 PORT 2 10 PORT 1 BAUD_RATE RESERVED WATCHDOG INT_PENDING INT_MASK SBUF TX HSO COMMAND 5 TIME HI HSI LO AD RESULT HI AD_RESULT LO RO HI RO LO WHEN READ HSO TIME HI HSO TIME LO AD COMMAND RO HI RO LO WHEN WRITTEN 0 2 49 EXTERNAL MEMORY OR 1 0 8X9XBH 8 98 XRAM 8X9XJF INTERNAL RAM REGISTER FILE STACK POINTER SPECIAL FUNCTION REGISTERS WHEN ACCESSED AS DATA MEMORY 0000H 270246 49 inte 8X9X HARDWARE DESIGN INFORMATION 11 6 Instruction Summary Oper Operation Note 1 Flags O _ ME SLE eara d ands ADD ADDB 2
85. RE CONNECTIONS Although the 8X9X is a single chip microcontroller it still requires several external connections to make it work Power must be applied a clock source provided and some form of reset circuitry must be present We will Jook at each of these areas of circuitry separately Figure 6 shows the connections that are needed for a single chip system 1 1 Power Supply Information Power for the 8X9X flows through six pins They are three positive voltage pins V cc digital Vref Port O digital I O and A D power Vpp power down mode and three common returns two Vgs pins and one ANGND pin All six of these pins must be con nected on the 8X9X for normal operation The Vcc pin Vggr pin and pin should be tied to 5 volts The two Vss pins and the ANGND pin must be grounded When the analog to digital converter is being used it may be desirable to connect the VREF pin to a separate power supply or at least a separate power sup ply line The three common return pins should be connected at the chip with as short a lead as possible to avoid prob 2 3 lems due to voltage drops across the wiring There should be no measurable voltage difference between and Vss The two Vss pins and the ANGND pin must all be nominally at 0 volts The maximum current drain of the 8X9X is around 180 mA with all lines unloaded When the analog converter is being used clean stable power must be provided to the analog section
86. SABLE BH ES E E TIMER 2 CLOCK SOURCE 1 1 T2CLK 272110 10 lOCO 15H T2RST dua 10C0 5 T2 RESET 1 10 0 3 10 0 0 1 0 B E HS ons 0 2 HSI 1 TIMER2 T2CLK 1000 7 CLOCK r 060 4 A 060 6 HSI 3 HSI 272110 11 gt gt PSW Register pefe ofofo 8X9X QUICK REFERENCE 1050 15H HSO 0 CURRENT STATE HSO 1 CURRENT STATE HSO 2 CURRENT STATE HSO 3 CURRENT STATE HSO 4 CURRENT STATE 50 5 CURRENT STATE CAM OR HOLDING REGISTER IS FULL HSO HOLDING REGISTER IS FULL 272110 12 1051 16H SOFTWARE TIMER EXPIRED SOFTWARE TIMER 1 EXPIRED SOFTWARE TIMER 2 EXPIRED SOFTWARE TIMER 3 EXPIRED TIMER 2 HAS OVERFLOW TIMER 1 HAS OVERFLOW HSI FIFO 15 FULL PS HSI HOLDING REGISTER DATA AVAILABLE 272110 13 IOC1 16H SELECT PWM SELECT P2 5 EXTERNAL INTERRUPT ACH7 EXTINT TIMER 1 OVERFLOW INTERRUPT ENABLE DISABLE TIMER 2 OVERFLOW INTERRUPT ENABLE DISABLE 50 4 OUTPUT ENABLE DISABLE SELECT TXD SELECT P2 0 HSO 5 OUTPUT ENABLE DISABLE HSI INTERRUPT FIFO FULL HOLDING REGISTER LOADED 272110 14 00 X Interrupt Mask Reg gt 8X9X QUICK REFERENCE e 48L DIP e Nj T e tO eir o 414
87. SS 0 FAIL PVALTS 270246 36 and VPP on slaves must be at 12 75 Each slave s PMODE must equal 05H Ports 3 and 4 should have pullups to VCC Minimum configuration connections must also be made for slaves A 10 MHz clock is recommended for the slaves 1 Allow RESET to rise after the voltages to Voc EA and Vpp are stable Figure 36 Gang Programming with the Auto Programming Mode 2 37 inte 8X9X HARDWARE DESIGN INFORMATION 10 5 Slave Programming Mode Any number of 879Xs can be programmed by a master programmer using the Slave Programming Mode In Slave Programming Mode the device being pro grammed uses Port 3 4 as a command data path PALE and PROG demultiplex the commands and data PVER PDO and Ports 3 and 4 pass error infor mation to the programmer There is no 879X depen dent limit to the number of devices that can be gang programmed in the slave mode It is important to note that the interface to an 879X in the slave mode is similar to a multiplexed bus Issuing consecutive PALE pulses without a corresponding PROG pulses will produce unexpected results as will issuing consecutive PROG pulses without the corre sponding PALE pulses 10 5 1 SLAVE PROGRAMMING COMMANDS The commands sent to the slaves are 16 bits wide and contain two fields Bits 14 and 15 specify the action that the slaves are to perform Bits O through 13 specify the address upon which the action is to take pla
88. T INTEGER will set the overflow indicators in the program status word The actual nu meric result returned will be the same as the equivalent operation on BYTE variables There are no alignment restrictions on SHORT INTEGERS so they may be placed anywhere in the MCS 96 address space INTEGERS INTEGERS are 16 bit signed variables which can take on the values between 32 768 and 32 767 Arithmetic operations which generate results outside of the range of an INTEGER will set the overflow indicators in the program status word The actual numeric result re turned will be the same as the equivalent operation on WORD variables INTEGERS conform to the same alignment and addressing rules as do WORDS BITS BITS are single bit operands which can take on the Boolean values of true and false In addition to the nor mal support for bits as components of BYTE and WORD operands the 8X9X provides for the direct testing of any bit in the internal register file The MCS 96 architecture requires that bits be addressed as com ponents of BYTES or WORDS it does not support the direct addressing of bits that can occur in the MCS 51 architecture inte MCS 96 8X9X ARCHITECTURAL OVERVIEW DOUBLE WORDS DOUBLE WORDS are unsigned 32 bit variables which can take on the values between O and 4 294 967 295 The MCS 96 architecture provides di rect support for this operand type only for shifts and as the dividend in a 32 by 16 divide and the prod
89. There are both hardware and software solutions to noise problems but the best solution is good design practice and a few ounces of prevention The 8X9X has a Watchdog Timer which will reset the device if it fails to execute the software properly The software should be set up to take advantage of this feature 2 30 It is also recommended that unused areas of code be filled with NOPs and periodic jumps to an error routine or RST reset chip instructions This is particularly important in the code around lookup tables since if lookup tables are executed all sorts of bad things can happen Wherever space allows each table should be surrounded by 7 NOPs the longest 8X9X instruction has 7 bytes and a RST or jump to error routine in struction This will help to ensure a speedy recovery should the processor have a glitch in the program flow Many hardware solutions exist for keeping PC board noise to a minimum Ground planes gridded ground and Vcc structures bypass capacitors transient ab sorbers and power busses with built in capacitors can all be of great help It is much easier to design a board with these features than to try to retrofit them later Proper PC board layout is probably the single most important and unfortunately least understood aspect of project design Minimizing loop areas and induc tance as well as providing clean grounds are very im portant More information on protecting against noise can found in the Ap
90. _WORD TABLE CX MEM_WORD TABLE BX AX AL BL MEM_BYTE LOOKUP CX ST AX ADDB AL BL LOOKUP CX intel MCS 96 8X9X ARCHITECTURAL OVERVIEW ZERO REGISTER ADDRESSING The first two bytes in the register file are fixed at zero able in a long indexed reference This combination of by the 8096 hardware In addition to providing a fixed register selection and address mode allows any location source of the constant zero for calculations and com in memory to be addressed directly parisons this register can be used as the WORD vari Examples ADD AX 1234 0 AX MEM_WORD 1254 POP 5678 0 MEM_WORD 5678 MEM_WORD SP SP SP 2 STACK POINTER REGISTER ADDRESSING The system stack pointer in the 8X9X can be accessed can be accessed by using the stack pointer as the as register 18H of the internal register file In addition WORD variable in an indirect reference In a similar to providing for convenient manipulation of the stack fashion the stack pointer can be used in the short in pointer this also facilitates the accessing of operands in dexed mode to access data within the stack the stack The top of the stack for example Examples PUSH SP DUPLICATE TOP_OF_STACK LD 2 5 s NEXT_TO_TOP ASSEMBLY LANGUAGE ADDRESSING MODES The 8X9X assembly language simplifies the choice of The use of these features of the assembly language sim addressing modes to be used in several respec
91. a is transferred 8 bits at a time with the LSB first A dia gram of the relative timing of these signals is shown in Figure 34 Note that this is the only mode which uses RXD as an output E qma RXD in VALD VALID VALID VAUD FM mM Pm mm em VAUD VALID VALID VALID X V V VJ V VV VV uu 270250 34 Figure 34 Serial Port Mode 0 Timing intel MCS 96 8X9X ARCHITECTURAL OVERVIEW Although it is not possible to transmit and receive at the same time using this mode two external gates and a port pin can be used to time multiplex the two func tions An example of multiplexing transmit and receive is discussed in Section 6 1 of the Hardware Design chapter MODE 1 Mode 1 is the standard asynchronous communications mode The data frame used in this mode is shown in Figure 35 It consists of 10 bits a start bit 0 8 data bits LSB first and a stop bit 1 If parity is enabled the PEN bit is set to a 1 an even parity bit is sent instead of the 8th data bit and parity is checked on reception MODE 2 Mode 2 is the asynchronous 9th bit recognition mode This mode is commonly used with Mode 3 for multi processor communications Figure 36 shows the data frame used in this mode It consists of a start bit 0 9 data bits LSB first and a stop bit 1 When transmit ting the 9th bit can be set to a one by setting the TB8 bit in the
92. al is being operated in its fundamental response mode as an inductive reac intel 8X9X HARDWARE DESIGN INFORMATION tance in parallel resonance with shunt capacitance ex ternal to the crystal The crystal specifications and capacitance values C1 and C2 in Figure 2 are not critical Thirty picofarads can be used in these positions at any frequency with good quality crystals For 0 5 frequency accuracy the crystal frequency can be specified at series reso nance or for parallel resonance with any load capaci tance In other words for that degree of frequency accuracy the load capacitance simply doesn t matter For 0 05 frequency accuracy the crystal frequency TO DIVIDER CIRCUITRY 270246 2 Figure 2 Crystal Oscillator Circuit should be specified for parallel resonance with 25 pF load capacitance if C1 and C2 are 30 pF An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback ca pacitance Once the external signal meets the and specifications the capacitance will not exceed 20 pF more in depth discussion of crystal specifications and the selection of values for C1 and C2 can be found in the Intel Application Note AP 155 Oscillators for Microcontrollers To drive the 8X9X with an external clock source apply the external clock signal to XTALI and let XTAL2 float An example of this circ
93. am itself and up to 15 other 879X s The Slave Programming Mode provides a standard interface to program any number of 879X s by a mas ter device such as an EPROM programmer or anoth er 879X The Run Time Programming Mode allows individu al EPROM locations to be programmed at run time under complete software control Run Time Pro gramming is done with EA 5V Some I O pins have new functions for programming These pins determine the programming function pro vide programming control signals and slave ID num bers and pass error information Figure 32 shows how the pins are renamed Figure 33 describes each new pin function PMODE selects the function to be performed see Figure 31 PMODE Programming Mode OCH e Dump Mode oc Auto Programming Mods Figure 31 Programming Function PMODE Values 2 32 When an 879X EPROM device is not being erased the window must be covered with an opaque label This prevents functional degradation and data loss from the array 10 1 Power Up and Power Down To avoid damaging devices during programming fol low these rules RULE 1 Vpp must be within 1V of while is below 4 5V RULE 2 can not be higher than 5 0V until is above 4 5V RULE 3 Vpp must not have a low impedance path to ground when Vcc is above 4 5V RULE 4 EA must be brought to 12 75V before Vpp is brought to 12 75V not needed for run time pr
94. am the PCCB using the Auto Configuration Byte Programming Mode see Section 10 3 NOTES Ports 3 and 4 should have pullups to VCC 1 Allow RESET to rise after the voltages to EA and Vpp are stable 8X9X HARDWARE DESIGN INFORMATION Auto Programming must be done in 8 bit bus mode For 68L devices you must tie the BUSWIDTH pin to ground You do not need to program the buswidth se lection bit in the PCCB PCCB 1 For 48L and 64L devices there is no BUSWIDTH pin You must pro gram PCCB 1 using the Auto Configuration Byte Pro gramming Mode before programming the array The data in the PCCB takes effect upon reset If you enable either the READ or WRITE lock bits during Auto Programming but do not reset the device Auto Programming will continue If you enable either the READ or WRITE lock bits and then reset the device the device will no longer program or verify You should program these bits when no more programming will be done 10 4 2 GANG PROGRAMMING WITH THE AUTO PROGRAMMING MODE An 879X in the Auto Programming Mode can also be used as a programmer for up to 15 other 879XBHs that are configured in the Slave Programming Mode The 879X acts as the master The master programs the slaves with the same data the master is programming itself with The master outputs the necessary slave com mand data pairs on Ports 3 and 4 It also provides the Slave ALE SALE and Slave PROG SPROG signals to demultiplex the commands fr
95. amples ADD 540 PUSH 1234H DIVB AX 10 340 SHORT INDEXED REFERENCES In this addressing mode an eight bit field in the instruc tion selects WORD variable in the register file which is assumed to contain an address A second eight bit field in the instruction stream is sign extended and summed with the WORD variable to form the address of the operand which will take part in the calculation Examples LD AX 12 BX MULB AX BL 3 CX INTEGER operands the field is 16 bits wide An in struction can contain only one immediate reference and the remaining operand s must be register direct refer ences SP zSP 2 MEM WORD SP z1234H AL zAX 10 MOD 10 Since the eight bit field is sign extended the effective address can be up to 128 bytes before the address in the WORD variable and up to 127 bytes after it An in struction can contain only one short indexed reference and the remaining operand s must be register direct references s MEM_WORD BX 12 LONG INDEXED REFERENCES This addressing mode is like the short indexed mode except that a 76 bit field is taken from the instruction and added to the WORD variable to form the address of the operand No sign extension is necessary An in Examples BL MEM_BYTE CX 3 struction can contain only one long indexed reference and the remaining operand s must be register direct references AND AX BX TABLE CX AND MEM
96. and PDO of all slaves are 1s after PROG rises then the data program was successful everywhere If any slave s PVER is a 0 then the data programmed did not verify correctly in that device If any slave s PDO is a O then the programming pulse in those devices was terminated by an internal safety feature rather than the rising edge of PROG The safety feature prevents over programming in the slave mode Figure 37 shows the relationship of PALE PROG PVER and PDO to the Command Data Path on Ports 3 and 4 for the Data Program Command ADDRESS COMMAND DATA PALE PROG PVER VALID N VALID PDO VALID VALID Figure 37 Data Program Signals in Slave Programming Mode 270246 37 intel 8X9X HARDWARE DESIGN INFORMATION PALE PORTS 5 4 DATA VERIFY COMMAND VERIFICATION BITS PROG Figure 38 Data Verify Command Signals DATA VERIFY COMMAND When the Data Verify Command is sent the slaves indicate correct or incor rect verification of the previous Data Program by driv ing one bit of Ports 3 and 4 A 1 indicates correct verifi cation while a 0 indicates incorrect verification The SID Slave ID Number of each slave determines which bit of Ports 3 and 4 is driven PROG from the program mer governs when the slaves drive the bus Figure 38 shows the relationship of Ports 3 and 4 to PALE and PROG The data verify command is always preceded by a Data Program Command in a programming system with as
97. andard calling convention adopted by PLM 96 has several key features a Procedures can always assume that the eight bytes of register file memory starting at PLMREG can be used as temporaries within the body of the proce dure b Code which calls a procedure must assume that the eight bytes of register file memory starting at PLMREG are modified by the procedure c The Program Status Word PSW see Section 3 3 is not saved and restored by procedures so the calling code must assume that the condition flags Z N V VT C and ST are modified by the procedure d Function results from procedures are always turned in the variable PLMREG PLM 96 allows the definition of INTERRUPT proce dures which are executed when a predefined interrupt occurs These procedures do not conform to the rules of a normal procedure Parameters cannot be passed to these procedures and they cannot return results Since they can execute essentially at any time hence the term interrupt these procedures must save the PSW and PLMREG when they are entered and restore these val ues before they exit intel MCS 96 8X9X ARCHITECTURAL OVERVIEW 4 0 INTERRUPT STRUCTURE There are 21 sources of interrupts on the 8X9X These sources are gathered into 8 interrupt types as indicated in Figure 19 The I O control registers which control some of the sources are indicated in the figure Each of the eight types of interrupts has its own interrupt vecto
98. ant factors such as input pin leakage sam ple capacitor size and multiplexer series resistance from the input pin to the sample capacitor must be consid ered For the 8X9X these factors are idealized in Figure 13 The external input circuit must be able to charge a sam ple capacitor Cs through a series resistance to an accurate voltage given a D C leakage Ip On the 8X9X Cs is around 2 pF is around 5 and is specified as 3 maximum In determining the neces sary source impedance Rs the value of VgrAs is not important RsoURCE 270246 14 Figure 13 idealized A D Sampling Circuitry External circuits with source impedances of 1 or less will be able to maintain an input voltage within a tolerance of about 0 61 LSB 1 0 KQ X 3 0 pA 3 0 mV given the D C leakage Source impedances above 2 can result an external error of at least one LSB due to the voltage drop caused by the 1 leakage In addition source impedances above 25 may degrade converter accuracy as a result of the inter nal sample capacitor not being fully charged during the 1 us 12 MHz clock sample window If large source impedances degrade converter accuracy because the sample capacitor is not charged during the sample time an external capacitor connected to the pin will compensate for this degradation Since the sample capacitor is 2 pF 0 005 uF capacitor will charge the sample capacitor to an accurate inpu
99. apter BUS WIDTH The 8X9XBH and 8X9XJF external bus width can be run time configured to operate as a standard 16 bit multiplexed address data bus or as an 8051 style 16 bit address 8 bit data bus The 8X98 external bus must be configured as a 16 bit address 8 bit data bus During 16 bit bus cycles Ports 3 and 4 contain the address multiplexed with data using ALE to latch the address In 8 bit bus cycles Port 3 is multiplexed ad dress data while Port 4 is address bits 8 through 15 The address bits on Port 4 are valid throughout an 8 bit bus cycle Figure 11 shows the two options The bus width can be changed each bus cycle on the 8X9XBH and the 8X9XJF and is controlled using bit 1 of the CCR with the BUSWIDTH pin If either CCR 1 or BUSWIDTH is a 0 external accesses will be over 16 bit address 8 bit data bus If both CCR 1 and BUS WIDTH are 1s external accesses will be over a 16 bit address 16 bit data bus Internal accesses are always 16 bits wide The BUSWIDTH pin is not available on the 8X98 CCR 1 must be a 0 on the 8X98 The bus width can be changed every external bus cycle if a 1 was loaded into CCR bit 1 at reset If this is the case changing the value of the BUSWIDTH pin at run time will dynamically select the bus width For exam ple the user could feed the INST line into the BUS WIDTH pin thus causing instruction accesses to be word wide from EPROMs while data accesses are byte wide to and from RAMs A secon
100. ated with a POPF instruction which returns the interrupt enable to the state it was in before the code sequence It should be noted that some system configurations might require more protection to form a critical region An example is a system in which more than one processor has ac cess to a common resource such as memory or external I O devices 4 4 Interrupt Timing Interrupts are not always acknowledged immediately If the interrupt signal does not occur prior to 4 state times before the end of an instruction the interrupt will not be acknowledged until after the next instruction has been executed This is because an instruction is fetched and prepared for execution a few state times before it is actually executed STATE TIMES 4321 There are 6 instructions which always inhibit interrupts from being acknowledged until after the next instruc tion has been executed These instructions are EI DI Enable and Disable Interrupts POPF PUSHF Pop and Push Flags SIGND Prefix to perform signed multiply and divide Note that this is not an ASM 96 Mnemonic but is used for signed multiply and divide SOFTWARE TRAP Software interrupt When an interrupt is acknowledged the interrupt pending bit is cleared and a call is forced to the loca tion indicated by the specified interrupt vector This call occurs after the completion of the instruction in process except as noted above The procedure of get ting the vector and
101. ave an input leakage of a few microamps and are predominant ly capacitive loads on the order of 10 pF Port O pins are special in that they may individually be used as digital inputs or as analog inputs A Port 0 pin being used as a digital input acts as the high impedance input ports just described However Port 0 pins being used as analog inputs are required to provide current to the internal sample capacitor when a conversion begins This means that the input characteristics of a pin will change if a conversion is being done on that pin See Section 3 In either case if Port 0 is to be used as analog or digital I O it will be necessary to provide power to this port through the Vggr BUS OUTPUT ENABLE BUS DATA PORT DATA BUS PULLUP BUS 50 mA 25 mA 30 mA 15 mA 3 3 2 10 mA Pon 5mA 2 4 BUS PULLUP BUS PULLDOWN BUS P1 P2 2 4 Open Drain Ports Ports 3 and 4 on the 8X9X are open drain ports There is no pullup when these pins are used as I O ports These pins have different characteristics when used as bus pins as described in the next section A diagram of the output buffers connected to Ports 3 and 4 and the bus pins is shown in Figure 11 When Ports 3 and 4 are to be used as inputs or as bus pins they must first be written with a This will put the ports in a high impedance mode When they are used as outputs a pullup resistor must be used external
102. avoid a partial or complete unde sired reception REN must be set to zero before RI is cleared This can be handled in an interrupt environ ment by using software flags or in straight line code by using the Interrupt Pending register to signal the com pletion of a reception In the asynchronous modes writing to SBUF tx starts a transmission falling edge on RXD will begin a reception if REN is set to 1 New data placed in SBUF tx is held and will not be transmitted until the end of the stop bit has been sent In all modes the RI flag is set after the last data bit is sampled approximately in the middle of the bit time Also for all modes the TI flag is set after the last data bit either 8th or 9th is sent also in the middle of the bit time The flags clear when SP STAT is read but do not have to be clear for the port to receive or trans mit The serial port interrupt bit is set as a logical OR of the RI and TI bits Note that changing modes will reset the Serial Port and abort any transmission or re ception in progress on the channel If the Tx and Rx pins are tied together for loopback testing the RI flag will be written first 9 3 Determining Baud Rates Baud rates in all modes are determined by the contents of a 16 bit register at location 000 This register must be loaded sequentially with 2 bytes least signifi cant byte first The serial port will not function be tween the loading of the first and second b
103. can be done by checking variables to make sure they 1 46 MCS 96 8X9X ARCHITECTURAL OVERVIEW are within reasonable values Simply using a software timer to reset the WDT every 15 milliseconds will not provide much protection against minor problems It is also recommended that unused areas of code be filled with NOPs and periodic jumps to an error routine or RST reset chip instructions This is particularly important in the code around lookup tables since if lookup tables are executed undesired results will occur Wherever space allows each table should be surround ed by 7 NOPs the longest 8096 instruction has 7 bytes and a RST or jump to error routine instruction Since RST is a one byte instruction the NOPs are not needed if RSTs are used instead of jumps to an error routine This will help to ensure a speedy recovery should the processor have a glitch in the program flow Since RST instruction has an opcode of OFFH pulling the data lines high with resistors will cause an RST to be execut ed if unimplemented memory is addressed 12 2 Disabling The Watchdog The watchdog should be disabled by software not ini tializing it If this is not possible such as during pro gram development the watchdog can be disabled by holding the RESET pin at 2 0V to 2 5V Voltages over 2 5V on the pin could quickly damage the device Even at 2 5V using this technique for other than debugging purposes is not recommended as it may effect long
104. ce On the 879XJF P4 6 is both the least significant bit of the Data Program Upper 8K command and the most significant bit of the address Commands are sent via Ports 3 and 4 and are available to cause the slaves to program a word verify a word or dump a word Table 1 The address part of the command sent to the slaves ranges from 2000H to 3FFFH on the 879XBH and the 8798 and from 2000H to SFFFH on the 879XJF and refers to the internal EPROM memory space The fol lowing sections describe each slave programming mode command PORTS 3 4 Table 1 Slave Programming Mode Commands Word Dump Data Verify Data Program Lower 8K Data Program Upper 8K 879XJF DATA PROGRAM COMMAND After a Data Pro gram Command has been sent to the slaves PROG must be pulled low to program the data on Ports 3 and 4 into the location specified during the command The falling edge of PROG indicates data valid and also trig gers the hardware programming of the word specified The slaves will begin programming 48 states after PROG falls and will continue to program the location until PROG rises After the rising edge of PROG the slaves automatically perform a verification of the address just programmed The result of this verification is then output on PVER Program Verify and PDO Program Duration Over flowed Therefore verification information is available for programming systems that cannot use the Data Verify command If PVER
105. cle ALE ADV is activated only during external memory accesses Read signal output to external memory RD is activated only during external memory reads WRL Write and Write Low output to external memory as selected by the CCR WR will go low BHE WRH ALE ADV 3 for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is activated only during external memory writes Bus High Enable or Write High output to external memory as selected by the CCR BHE wiil go low for external writes to the high byte of the data bus will go low for external writes where an odd byte is being written BHE WRH is activated only during external memory writes 3 15 8X9X QUICK REFERENCE intel 5 0 PIN DESCRIPTIONS Continued Name and Function Ready input to lengthen external memory cycles If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait mode until the next positive transition in CLKOUT occurs with READY high When the external memory is not being used READY has no effect Internal control of the number of wait states inserted into a bus cycle held not ready is available in the CCR Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3 Two of them HSI 2 and HSI 3 are shared with the HSO Unit Outputs
106. ctly controlling the I O through the SFRs The main bene fits of this structure are the ability to quickly change context the absence of accumulator bottleneck and fast throughput and 1 0 times 1 1 CPU Buses A Control Unit and two buses connect the Register File and RALU Figure 1 shows the CPU with its FREQUENCY VREF ANGND P2 MULTIPLEXER 1 t a L 1 I 1 1 t y Li L 1 3 1 I Li L L 1 L Lj t L PORT 0 PORT 1 ALT FUNCTIONS REGISTER ALU pound if CPUS REFERENCE 8K BYTE ON CHIP EPROM B79 X BH CONTROL SIGNALS Duces E bM 270250 1 Figure 1 Block Diagram intel major bus connections The two buses are the A Bus which is 8 bits wide and the D Bus which is 16 bits wide The D Bus transfers data only between the RALU and the Register File or Special Function Regis ters SFRs The A Bus is used as the address bus for the above transfers or as a multiplexed address data bus connecting to the Memory Controller Any ac cesses of either the internal ROM or external memory are done through the Memory Controller Within the memory controller is a slave program coun ter Slave PC which keeps track of the PC in the CPU By having most program fetches from memory refer enced to the slave PC the processor saves time as ad dresses seldom have to be sent to the memory control ler If the address jumps sequence then the
107. ctually writes into a register which in turn drives the port pin When the processor reads these ports it senses the status of the pin directly If a port pin is to be used as an input then the software should write a one to its associated SFR bit this will cause the low impedance pull down device to turn off LD intreg portdata MCS 96 8X9X ARCHITECTURAL OVERVIEW and leave the pin pulled up with a relatively high im pedance pullup device which can be easily driven down by the device driving the input If some pins of a port are to be used as inputs and some are to be used as outputs the programmer should be careful when writing to the port Particular care should be exercised when using XOR opcodes or any opcode which is a read modify write instruction It is possible for a Quasi Bidirectional Pin to be written as a one but read back as a zero if an external device i e a transistor base is pulling the pin below See the Hardware Design Chapter Section 2 2 for further details on using the Quasi Bidirectional Ports 10 3 Output Ports Output pins include the bus control lines the HSO lines and some of Port 2 These pins can only be used as outputs as there are no input buffers connected to them It is not possible to use immediate logical instruc tions such as XOR PORT2 00111B to toggle these pins The output currents on these ports is higher than that of the quasi bidirectional ports 10 4 Ports 3 and 4 ADO 15
108. cutes within the priority structure established by the software f At the end of the service routine the POPF instruc tion restores the PSW to its state when the interrupt call occurred The hardware will not allow interrupts to be processed following a POPF instruction so the execution of the last instruction RET is guaranteed before further interrupts can occur The reason that this RET instruction must be protected in this fash ion is that it is quite likely that the POPF instruction will reenable an interrupt which is already pending If this interrupt were serviced before the RET in struction then the return address to the code that was executing when the original interrupt occurred would be left on the stack While this does not pres ent a problem to the program flow it could result in a stack overflow if interrupts are occurring at a high frequency The POPF instruction also pops the 1 29 INT MASK register part of the PSW so changes made to this register during a routine which ends with a POPF will be lost Notice that the and exit code for the inter rupt service routine does not include any code for sav ing or restoring registers This is because it has been assumed that the interrupt service routine has been al located its own private set of registers from the on board register file The availability of some 230 bytes of register storage makes this quite practical 4 3 Critical Regi
109. d m EX JC JNC JE 4 z 2 a Uu o ________ umpc 0 0 1 0420 MumpiN 1or2 3 1 E ES ES E 2 ele 9 NIN 2 cic 3 3 5 z 5 moc raaz Jump if ST 1 Jump if ST 0 E E cic 2 lt I lt c VT JNVT JNST DJNZ JST JBS JBC rc NEG NEGB INC INCB Jump if Specified Bit 0 D D 1 if D 0 then PC lt PC 8 bit offset 1 Sid ext pm 2 C mb Isb 0 SHRA SHRAB SHRAL ser junc e t DENN SS lt Pp 3 5 Dm sp BOP Mees 3 21 m 8X9X QUICK REFERENCE intel 7 0 INSTRUCTION SUMMARY Continued Operation Note 1 mr mz SP SP 2 SP lt PC PC 2010H EA pw E NOTES 1 If the mnemonic ends in B a byte operation is performed otherwise a word operation is done Operands D B and must conform to th
110. d WR pulses in order to allow ac cess of slow memories or for DMA purposes If the READY line is low by the specified time after ALE falls the 8X9X will hold the bus lines to their values at the falling edge of CLKOUT When the READY line rises the bus cycle will continue with the next falling edge of CLKOUT See Figure 9A Since the bus is synchronized to CLKOUT it can be held only for an integral number of state times If more than TYLYH nanoseconds are added the processor will act unpredictably There are several set up and hold times associated with the READY signal If these timings are not met the device may not respond with the proper number of wait states For falling edges of READY sampling is done inter nally on the falling edge of Phase A Since Phase A generates CLKOUT after some propagation delay the sample will be taken prior to CLKOUT falling The timing specification for this is given as TLLYV the time between when ALE falls and READY must be valid If READY changes between TLLYV max and the falling edge of CLKOUT TLLYH MIN on 48 lead devices it would be possible to have the READY sig nal transitioning as it is being sampled This situation could cause a metastable condition which could make the device operate unpredictably MCS 96 8X9X ARCHITECTURAL OVERVIEW For the rising edge of READY sampling is done inter nally on the rising edge of Phase A The rising edge logic is fully synchronized so it is
111. d example would be to place an inverted version of Address bit 15 on the BUSWIDTH pin This would make half of external memory word wide while half is byte wide Since BUSWIDTH is sampled after address decoding has had time to occur even more complex memory maps could be constructed See the timing specifica tions for an exact description of BUSWIDTH timings The bus width will be determined by bit 1 of the CCR alone on 48 pin devices since they do not have a BUS WIDTH pin When using an 8 bit bus some performance degrada tion is to be expected On the 8X9X instruction execu tion times with an 8 bit bus will slow down if any of three conditions occur First word writes to external memory will cause the executing instruction to take two extra state times to complete Second word reads from external memory will cause a one state time exten sion of instruction execution time Finally if the pre fetch queue is empty when an instruction fetch is re quested instruction execution is lengthened by one state time for each byte that must be externally ac quired worst case is the number of bytes in the instruc tion minus one BUS CONTROL 16 BIT MULTIPLEXED ADDRESS DATA 270250 9 16 Bit Bus MCS 96 8X9X ARCHITECTURAL OVERVIEW BUS CONTROL 8 BIT LATCHED ADDRESS HIGH MULTIPLEXED ADDRESS LOW DATA 270250 10 8 Bit Bus Figure 11 Bus Width Options BUS CONTROL Using the CCR the 8X9X can be made to
112. d rates This means that the serial port itself does not know about state times There is circuitry which is synchronized to the serial port and to 2 22 8X9X HARDWARE DESIGN INFORMATION the rest of the 8X9X so that information can be passed back and forth The baud rate generator is clocked by either XTALI or T2CLK Because T2CLK needs to be synchronized to the XTALI signal its speed must be limited to that of The serial port will not function during the time between the consecutive writes to the baud rate register Section 11 4 of the 8X9X Architecture chapter discusses programming the baud rate generator 6 1 Mode 0 Mode 0 is the shift register mode The TXD pin sends out a clock train while the RXD pin transmits or re ceives the data Figure 20 shows the waveforms and timing Note that the port starts functioning when is written to the REN Receiver Enable bit in the serial port control register If REN is already high clearing the RI flag will start a reception In this mode the serial port can be used to expand the I O capability of the 8X9X by simply adding shift reg isters A schematic of a typical circuit is shown in Fig ure 21 This circuit inverts the data coming in so it must be reinverted in software The enable and latch connections to the shift registers can be driven by de coders rather than directly from the low speed I O ports if the software and hardware are properly de sig
113. d with the ROM Lock feature which will be discussed in the next section All unspecified addresses in locations 2000H through 207FH including those marked Reserved should be considered reserved for use by Intel Resetting the 8X9X causes instructions to be fetched starting from location 2080H This location was chosen to allow a system to have up to 8K of RAM continuous with the register file Further information on reset can be found in Section 13 1 9 Register Mapped 1 0 SFRs Stack Pointer Ports 3 and 4 Interrupt Vectors Reserved Chip Configuration Byte Reserved Jump to Self Opcode 27H Reserved Security Key Reserved Reset Location Figure 8 Registers with Special Significance 2 5 Internal ROM and EPROM When ROM device is ordered or an EPROM device is programmed the internal memory locations 2080H through 3FFFH on the 8X9XBH and 8X98 and loca tions 2080H through SFFFH on the 8X9XJF are user specified as are the interrupt vectors Chip Configura tion Register and Security Key in locations 2000H through 202FH Instruction and data fetches from the internal ROM or EPROM occur only if the device has ROM or EPROM EA is tied high and the address is between 2000H and 3FFFH on the 8X9XBH and 8X98 and between 2000H and the 8X9XJF At all other times data is accessed from either the internal RAM space or external memory and instructions are fetched from external memory The
114. d writes and during all byte writes to an odd location During read cycles an 8X9X in 16 bit bus mode will always do a word read of an even loca tion If only one byte of the word is needed the chip discards the byte it does not need Since 8X9X memory accesses over an 8 bit wide bus are always bytes only one write strobe is needed for write cycles For this purpose the WRL signal was made to go low for all write cycles during 8 bit bus accesses When a word operation is requested the bus controller performs two byte wide bus cycles In many cases it may be desirable to have a write signal with a longer pulse width than WRL WRH The Write WR line of the 8X9X is an alternate control signal that shares a pin with WRL and is only available in 16 bit bus mode WR is nominally one Tosc longer than the WRL WRH signals but goes low for any write cycle Therefore it is necessary to decode for the type of write byte or word desired The Byte High Enable signal and can be used for this purpose BHE is an alternate control WRITE HIGH WRITE LOW 270246 27 Figure 24 Decoding WR and BHE to Generate WriteLow and WriteHigh 2 27 signal that shares a pin with When BHE is low the high byte of the 16 bit bus is enabled When MAO is low the lower byte is enabled When MAO is low and BHE is low both bytes are enabled Figure 24 shows how to use WR BHE and MAO to decode bus accesses It s important to
115. ding Register with both the time and the last written command tag The command does not actually enter the CAM file until an empty CAM register becomes available Commands in the holding register will not execute even if their time tag is reached Commands must be in the CAM for this to occur Commands in the holding regis ter can also be overwritten Since it can take up to 8 state times for a command to move from the holding register to the CAM 8 states must be allowed between successive writes to the CAM To provide proper synchronization the minimum time that should be loaded to Timer 1 is Timer 1 2 Smaller values may cause the Timer match to occur 65 636 counts later than expected A similar restriction applies if Timer 2 is used Care must be taken when writing the command tag for the HSO If an interrupt occurs during the time be tween writing the command tag and loading the time value and the interrupt service routine writes to the HSO time register the command tag used in the inter rupt routine will be written to the CAM at both the time specified by the interrupt routine and the time specified by the main program The command tag from the main program will not be executed One way of avoiding this problem would be to disable interrupts when writing commands and times to the HSO unit See also Section 4 5 CHANNEL 0 5 50 0 50 5 6 50 0 AND HSO 1 7 HSO 2 AND HSO 3 8 8 SOFTWARE TIMERS E RESET TIMER2 F START A
116. e a PWM waveform for most efficient operation Additionally if this waveform is in tegrated it will produce a DC level which can be changed in 256 steps by varying the duty cycle 270250 31 PWM Period XTAL 12 MHz 64 us Frequency 15 625 KHz Duty Cycle Programmable in 256 Steps Figure 32 Pulse Width Modulated D A Output PWM CONTROL REGISTER VALUE 99 Lo OUTPUT WAVEFORM HI 1 1 1 LO o U d LO 270250 32 Figure 33 Typical PWM Outputs intel Details about the hardware required for smooth accu rate D A conversion can be found in Section 4 of the Hardware Design chapter Typically some form of buffer and integrator are needed to obtain the most use fulness from this feature The PWM output shares a pin with Port 2 pin 5 so that these two features cannot be used at the same time equal to 1 selects the PWM function instead of the standard port function More information on IOCI is in Section 11 8 5 PWM Using the HSO The HSO unit can be used to generate PWM wave forms with very little CPU overhead If the HSO is not being used for other purposes a 4 line PWM unit can be made by loading the on and off times into the CAM in sets of 4 The CAM would then always be loaded and only 2 interrupts per PWM period would be needed 9 0 SERIAL PORT The serial port on the 8X9X has 3 asynchronous and one synchronous mode The asynchronous modes are full duplex m
117. e alignment rules for the required operand type D and B are locations in the Register File A can be located anywhere in memory D D 2 are consecutive WORDS in memory D is DOUBLE WORD aligned D D 1 are consecutive BYTES in memory D is WORD aligned Changes a byte to a word Offset is a 2 s complement number Specified bit is one of the 2048 bits in the register file The L Long suffix indicates double word operation Initiates a Reset by pulling RESET low Software should re initialize all the necessary registers with code starting at 2080H 9 The assembler will not accept this mnemonic 3 22 8X9X QUICK REFERENCE eS3NWLL Sl SIS Sj Sj SiS SIS 2 031 15 Ajj ALM k 1 oj CES EIE EA E E Do EG El Rd Bd bd 052 Nj usi m 5 5185 alal BIAS Sl 2 229 323 228 ala z z zelziziziziaiza 21212 lt lt lt lt lt nlaln Sl e e 53
118. e time in the HS Time registers and the current state of the pins Transmit buffer for the serial port holds contents to be outputted Receive buffer for the serial port holds the byte just received by the serial port Interrupt Mask Register Enables or disables the individual interrupts Interrupt Pending Register Indicates that an interrupt signal has occurred on one of the sources and has not been serviced Watchdog Timer Register Written to periodically to hold off automatic reset every 64K state times Timer 1 Hi Lo Timer 1 high and low bytes word read only Timer 2 Hi Lo Timer 2 high and low bytes word read only Port 0 Register Levels on pins of port 0 Register which determines the baud rate this register is loaded sequentially Port 1 Register Used to read or write to Port 1 Port 2 Register Used to read or write to Port 2 Serial Port Status Indicates the status of the serial port Serial Port Control Used to set the mode of the serial port Status Register 0 Contains information on the HSO status Status Register 1 Contains information on the status of the timers and of the Control Register 0 Controls alternate functions of HS pins Timer 2 reset sources and Timer 2 clock sources Control Register 1 Controls alternate functions of Port 2 pins timer interrupts and HSI interrupts Pulse Width Modulation Control Register
119. eaning they can transmit and receive at the same time The receiver is double buffered so that the reception of a second byte can begin before the first byte has been read The port is functionally compatible with the serial port on the MCS 51 family of microcon trollers although the software used to control the ports is different MCS 96 8X9X ARCHITECTURAL OVERVIEW Control of the serial port is handled through the Serial Port Control Status Register at location 11H Figure 37 shows the layout of this register The details of using it to control the serial port will be discussed in Section 9 2 Data to and from the serial port is transferred through SBUF and SBUF tx both located at 07H Al though these registers share the same address they are physically separate with SBUF rx containing the data received by the serial port and SBUF tx used to hold data ready for transmission The program cannot write to SBUF rx or read from SBUF tx The baud rate at which the serial port operates is con trolled by an independent baud rate generator The in puts to this generator can be either the XTAL or the T2CLK pin Details on setting up the baud rate are given in Section 9 3 9 1 Serial Port Modes MODE 0 Mode 0 is a synchronous mode which is commonly used for shift register based I O expansion In this mode the TXD pin outputs a set of 8 pulses while the RXD pin either transmits or receives data Dat
120. ed by IOCO The control bit locations are shown in Figure 38 IOCO is for initial ization only 1 0 INPUT ENABLE DISABLE TIMER 2 RESET EACH WRITE HSI 1 INPUT ENABLE DISABLE TIMER 2 EXTERNAL RESET ENABLE DISABLE HSI 2 INPUT ENABLE DISABLE TIMER 2 RESET SOURCE 51 0 T2RST HSI 3 INPUT ENABLE DISABLE TIMER 2 CLOCK SOURCE HSI 1 T2CLK 270250 37 Figure 38 O Control Register 0 intel 11 2 1 0 Control Register 1 IOC1 is used to select some pin functions and enable or disable some interrupt sources Its location is O016H Port pin P2 5 can be selected to be the PWM output instead of a standard output The external interrupt source can be selected to be either EXTINT same pin as P2 2 or Analog Channel 7 ACH7 same pin as 7 Timer and Timer 2 overflow interrupts can individually enabled or disabled The HSI interrupt can be selected to activate either when there is 1 FIFO en try or 7 Port pin P2 0 can be selected to be the TXD output HSO 4 and HSO 5 can be enabled or disabled to the HSO unit More information on interrupts is available in Section 4 The positions of the IOC1 con trol bits are shown in Figure 39 11 3 Status Register 0 1050 There are two I O Status registers IOSO and IOSI 1050 located at 0015H holds the current status of the HSO lines and CAM The status bits of IOSO are shown in Figure 40 SELECT PWM SELECT P2 5 EXTERNAL INTERRUPT ACH7
121. ed directly to XTALI Alternatively since XTAL1 and are inputs and outputs of an inverter it is also possible to use a crystal to generate the clock A block diagram of the oscillator section is shown in Figure 3 Details of the circuit and sugges tions for its use can be found in Section 1 of the Hard ware Design chapter The crystal or external oscillator frequency is divided by 3 to generate the three internal timing phases as shown in Figure 4 Each of the internal phases repeat every 3 oscillator periods 3 oscillator periods are re ferred to as one state time the basic time measure ment for 8X9X operations Most internal operations are synchronized to either Phase A B or C each of which have a 33 duty cycle Phase is represented externally by CLKOUT a signal available on the 68 pin device Phases B and C are not available exter nally The relationships of XTAL1 CLKOUT and Phases A B and C are shown in Figure 4 It should be noted that propagation delays have not been taken into account in this diagram Details on these and other tim ing relationships can be found in the Hardware Design chapter 270250 3 Figure 3 Block Diagram of Oscillator The RESET line can be used to start the 8X9X at an exact time to provide for synchronization of test equip ment and multiple chip systems Use of this feature is fully explained under RESET Section 13 x FLILILTLILITLT LI ONE STATE PHASE
122. ed with the data on Port 3 After programming PVER is driv en high if the bytes programmed correctly and low if N 2 75 ON ERROR XTAL2 NOTES they did not Programming takes approximately 250 ms Figure 34 shows a minimum configuration for Auto Configuration Byte Programming Once the CCB and PCCB are programmed all pro gramming activities and bus operations use the selected bus width READY control bus controls and READ WRITE protection until you erase the device You must be careful when programming the READ and WRITE lock bits in the CCB and PCCB If you enable the READ and WRITE lock bits in the CCB or the PCCB and then reset the device the array may no long er be programmed or verified see Figure 41 in Section 10 7 1 Therefore you should program tbe buswidth READY control and bus controls using the Auto Con figuration Byte Programming Mode You should pro gram the READ and WRITE lock bits when all pro gramming is complete If the PCCB is not programmed the CCR will be load ed with OFFFH when the device is in the Programming Mode Specific requirements for CCB and PCCB program ming are included in the Auto Slave and Run time Programming sections 01275 Ye 012 75 PULLUPS TO PORT 3 BINARY SWITCH PALE PUSH TO PROGRAM 270246 39 1 Tie Port 3 to the value desired to be programmed into
123. en using the serial port to connect more than two devices in half duplex i e one wire for transmit and receive If the receiving proces sor does not wait for one bit time after RI is set before starting to transmit the stop bit on the link could be squashed This could cause a problem for other devices listening on the link 6 3 Mode 2 and 3 Timings Modes 2 and 3 operate in a manner similar to that of Mode 1 The only difference is that the data is now made up of 9 bits so 11 bit packages are transmitted and received This means that TI and RI will be set on the 9th data bit rather than the 8th The 9th bit can be used for parity or multiple processor communications see Section 11 of the 8X9X Architecture chapter 2 23 7 0 BUS TIMING AND MEMORY INTERFACE 7 1 Bus Functionality The X9X has a multiplexed address data bus which can be dynamically configured to have an 8 bit or 16 bit data width There are control lines to demultiplex the bus ALE or ADV indicate reads 5 RD indicate writes WRL and WRH or WR with BHE and ADO and a signal to indicate accesses that are for an instruc tion fetch INST Section 3 5 of the 8X9X Architec ture chapter contains an overview of the bus operation intel 7 2 Timing Specifications Figure 22 shows the timing of the bus signals and data lines Please refer to the latest data sheet for the exact device you are using to ensure that your system is de signed to the proper
124. ence 8 9 Quick Reference August 1992 Order Number 272110 002 8X9X QUICK REFERENCE CONTENTS PAGE CONTENTS PAGE 1 0 MEMORY AND SFR 3 5 7 0 INSTRUCTION SUMMARY 3 20 2 0 SFR BIT SUMMARY 3 6 8 0 OPCODES INSTRUCTION LENGTH 3 0 PIN DEFINITION TABLE 3 8 ae Pc IS PACKAGE BICASSIGNMENTS 3 40 SO INTERRUPT TABLE 3 26 MN ARE 5 10 0 FORMULAS 3 27 6 0 OPCODE TABLE 34 PORESET STATUS 3 3 3 4 intel 8X9X QUICK REFERENCE 10 MEMORY AND SFR MAP POWER DOWN RAM INTERNAL REGISTER FILE RAM STACK POINTER RESERVED 10 PORT 2 HSI_TIME LO WHEN READ STACK POINTER PWM_CONTROL RESERVED 10 PORT 2 10 PORT 1 BAUD_RATE INT_ PENDING INT_MASK SBUF TX HSO TIME HI HSO TIME 10 WHEN WRITTEN EXTERNAL MEMORY OR 1 0 INTERNAL PROGRAM STORAGE ROM EPROM OR EXTERNAL MEMORY 2072H 207FH SIGNATURE WORD 2070H 207 1H SECURITY KEY 2020H 202FH RESERVED 201CH 20 1FH SELF JUMP OPCODE 27H 201AH 201BH RESERVED 2019H CHIP CONFIGURATION BYTE 2018H RESERVED 2012H 2017H INTERRUPT VECTORS EXTERNAL MEMORY OR 1 0 INTERNAL RAM REGISTER FILE STACK POINTER SPECIAL FUNCTION REGISTERS WHEN ACCESSED AS DATA MEMORY 0000H 2721
125. eps within the 20 mV ladder voltages Therefore 1024 internal reference volt ages are available for comparison against the analog input to generate a 10 bit conversion result A successive approximation conversion is performed by comparing a sequence of reference voltages to the ana log input in a binary search for the reference voltage that most closely matches the input The full scale reference voltage is the first tested This corresponds to a 10 bit result where the most significant bit is zero and all other bits are ones 0111 1111 11b If the ana log input was less than the test voltage bit 10 of the SAR is left a zero and a new test voltage of full scale 0011 1111 11b is tried If this test voltage was lower than the analog input bit 9 of the SAR is set and bit 8 is cleared for the next test 0101 1111 11b This binary search continues until 10 tests have occurred at which time the valid 10 bit conversion result resides in the SAR where it can be read by software 2 13 8X9X HARDWARE DESIGN INFORMATION The total number of state times required is 88 for a 10 bit conversion Attempting to short cycle the 10 bit conversion process by reading A D results before the done bit is set is not recommended 3 2 A D Interface Suggestions The external interface circuitry to an analog input is highly dependent upon the application and can impact converter characteristics In the external circuit s de sign import
126. er 0 is seen a third wait state is inserted in the bus cycle and the READY pin is again latched on the following rising edge of CLOCKOUT If internal Ready Control is not used the READY line must at this point be a 1 to ensure proper operation TLLGV ALE ADV low to BUSWIDTH valid Maximum time after ALE ADV is low until BU SWIDTH must be valid If this time is exceeded the part could malfunction necessitating a chip reset Nominally less than 1 Tosc TLLGX BUSWIDTH hold after ALE ADV low Minimum time that BUSWIDTH must be valid after ALE ADV is low Nominally 1 Tosc TRLDV READ low to DATA valid Maximum time that the memory has to output data after READ goes low Nominally a maximum of 3 Tosc periods TRHDZ READ high to DATA float Time after READ is high until the memory must float the bus The memory signal can be removed as soon as READ is not low and must be removed within the specified maximum time from when READ is high Nominally a maximum of 1 Tosc period TRHDX DATA hold after READ goes high Mini mum time that memory must hold input DATA valid after RD is high The hold time minimum is always zero nanoseconds TRLAZ READ low to ADDRESS float This is the bus control specifying the time from an active low READ signal until the 8X9X ADDRESS drivers for the cycle are off the bus This is specified in order for data to be returned from the memory system without bus contention Typically this is O ns for no b
127. ernal execution mode the CCB is read from in ADV SELECTED CHIP CONFIGURATION BYTE 270246 4 ternal ROM EPROM If the voltage on the EA pin selects the external execution only mode the CCB is read from external memory See Figure 5 and 5A There are several ways to provide a good reset to an 8X9X the simplest being just to connect a capacitor from the reset pin to ground The capacitor should be on the order of 2 microfarads for every millisecond of reset time required This method will only work if the rise time of Vcc is fast and the total reset time is less than around 50 milliseconds It also may not work if the RESET pin is to be used to reset other devices on the board An 8X9X with the minimum required con nections is shown in Figure 6 ALE SELECTED THE BYTE 8 BIT BUS OR WORD 16 BIT BUS AT 2080H 270246 5 Figure 5 Reset Sequence intel 8X9X HARDWARE DESIGN INFORMATION Power Supply Rise Time 5 5Vpc 4 5Vpc Start Time from Power Supply Rise to External Output Low FALL External to Internal Release Time HSO 0 HSO 3 P2 0 P2 5 PORT 5 amp 4 WITH PULLUPS ADDRESS 2018H CCB 1OXTAL CYCLES FIRST BUS FETCH CYCLE External RESET Low to Port Valid Time 270246 44 270246 7 270246 40 NOTES 1 These capacitors are needed only if A to D is used 2 Vaer 8 ANGND may be connected to the same traces as the digital power supply if the A to D is not used Figure 6 Minimum Ha
128. es with each pin will limit current to a reasonable value without impeding the ability to override the high impedance pullup If all 8 pins are tied together a 1202 resistor would be rea sonable The problem is not quite as severe when the inputs are tied to electronic devices instead of switches as most external pulldowns will not hold 20 mA to 0 0 volts Writing to a Quasi Bidirectional Port with electronic devices attached to the pins requires special attention Consider using P1 0 as an input and trying to toggle P1 1 as an output ORB 1 00000001 Set P1 0 for input XORB IOPORT1 000000108 Complement 1 PORT 1 INTERNAL CLOCK LOW IMPEDANCE PULLUP Q1 NOTE These graphs show typical pin capabilities they are not guaranteed specifications HIGH IMPEDANCE 8X9X HARDWARE DESIGN INFORMATION 270246 11 LOW IMPEDANCE PULLUP PULLDOWN Q3 Q2 270246 12 Figure 10 Quasi Bidirectional Port The first instruction will work as expected but two problems can occur when the second instruction exe cutes The first is that even though 1 1 is being driven high by the 8X9X it is possible that it is being held low externally This typically happens when the port pin is used to drive the base of an NPN transistor which in turn drives whatever there is in the outside world which needs to be toggled The base of the transistor will clamp the port pin to the transistors Vbe above ground typica
129. ese pins are also a mode input to EPROM devices in the Programming mode See Section 10 8 bit quasi bidirectional 1 port See Section 10 8 bit multi functional port Six of its pins are shared with other functions in the 8X9X the remaining 2 are quasi bidirectional These pins are also used to input and output control signals on EPROM devices in Programming Mode See Section 10 8 bit bidirectional O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Ports 3 and 4 are also used as a command address and data path by EPROM devices operating in the programming mode See Sections 2 7 and 10 2 44 8X9X HARDWARE DESIGN INFORMATION 11 2 Pin List The following is a list of pins in alphabetical order Where a pin has two names it has been listed under both names except for the system bus pins ADO AD15 which listed under Port 3 and Port 4 68 Pin 68 Pin 48 Pin 64 Pin PLCC PGA DIP SDIP 0 1 1 ACH2 P0 2 ACH3 P0 3 ACH4 P0 4 MOD 0 ACH5 P0 5 MOD 1 ACH6 P0 6 MOD 2 ACH7 P0 7 MOD 3 ALE ADV ANGND BHE WRH BUSWIDTH CLKOUT EA EXTINT P2 2 PROG HSI 0 HSI 1 HSI 2 HSO 4 HSI 3 HSO 5 HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 HSI 2 HSO 5 HSI 3 INST NMI PWM P2 5 PDO PALE P2 1 RXD PROG P2 2 EXTNT PVER P2 0 TXD P0 0 ACHO 1 1 2 2 4 4 0 P0 5 ACH5 MOD 1
130. expected and actual input voltage corresponding to the first code transition 4 0 ANALOG OUTPUTS Analog outputs can be generated by two methods ei ther by using the PWM output or the HSO Either device will generate a rectangular pulse train that varies in duty cycle and for the HSO only period If a smooth analog signal is desired as an output the rec tangular waveform must be filtered In most cases this filtering is best done after the signal is buffered to make it swing from 0 to 5 volts since both of the outputs are guaranteed only to TTL levels A block diagram of the type of circuit needed is shown in Figure 18 By proper selection of components account ing for temperature and power supply drift a highly accurate 8 bit D to A converter can be made using ei ther the HSO or the PWM output Figure 19 shows two typical circuits If the HSO is used the accuracy could be theoretically extended to 16 bits however the tem perature and noise related problems would be extreme ly hard to handle When driving some circuits it may be desirable to use unfiltered Pulse Width Modulation This is particularly true for motor drive circuits The PWM output can be used to generate these waveforms if a fixed period on the order of 64 is acceptable If this is not the case then the HSO unit can be used The HSO can generate a variable waveform with a duty cycle variable in up to 65536 steps and a period of up to 131 milliseconds Both
131. ey verification are allowed Auto slave and auto PCCB programming are not allowed _ 1 1 Same as above Array is write protected ROM dump mode with security key verification is allowed Auto slave auto PCCB and run time programming are not allowed Array is read and write protected ROM dump mode with security key 1 1 verification is allowed Auto slave auto PCCB and run time programming are not allowed 8X9X HARDWARE DESIGN INFORMATION on the 879XBH and the 8798 and locations 2000H 5FFFH on the 879XJF from inadvertant or unautho rized programming also prevents writes to the EPROM from upsetting program execution If write protection is not enabled a data write to an internal EPROM location will begin programming that loca tion and continue programming the location until a data access of the internal EPROM is executed While programming instruction fetches from internal EPROM will not be successful and programming will stop READ protection is selected by causing the LOCI bit in the to take the value 0 When READ protec tion is enabled the bus controller will only perform a data read from the address range 2020H 3FFFH if the slave program counter is in the range 2000H 3FFFH on the 879XBH and the 8798 The bus controller will only perform a data read from the address range 2020H SFFFH if the slave program counter is in the range 2000H 5SFFAH 879XJF Note that since the s
132. from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 and HSO 5 Two of them HSO 4 and HSO 5 are shared with the HSI Unit Port Ot 8 bit high impedance input only port These pins can be used as digital inputs and or as analog inputs to the on chip A D converter Port 1t 8 bit quasi bidirectional I O port Port 21 8 bit multi functional port Six of its pins are shared with other functions in the 8096BH the remaining 2 are quasi bidirectional Ports 4 8 bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus Ports 3 and 4 are also used as a command address and data path by EPROM devices operating in the Programming Mode PMODE Determines the EPROM programming mode PACT A low signal in Auto Programming Mode indicates that programming is in progress A high signal indicates programming is complete PVAL A low signal in Auto Programming Mode indicates that the device was programmed correctly SALE A falling edge of Auto Programming Mode indicates that Ports 3 and 4 contain valid programming address command information output from master SPROG A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid programming data output from master Assigns a pin of Ports 3 and 4 to each slave to pass programming verification A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
133. function It can be attached to a 8X9X system which has the required address decoding and bus demultiplexing The output circuitry is basically just a latch that oper ates when or 1FFFH are placed on the lines The inverters surrounding the latch create an open collector output to emulate the open drain output found on the 8X9X The reset line is used to set the ports to all 15 when the 8X9X is reset It should be noted that the voltage and current characteristics of the port will differ from those of the 8X9X but the basic functionality will be the same The input circuitry is just a bus transceiver that is ad dressed at or If the ports are going to be used for either input or output but not both some of the circuitry can be eliminated 8 0 NOISE PROTECTION TIPS Designing controllers differs from designing other com puter equipment in the area of noise protection A mi crocontroller circuit under the hood of a car in a pho tocopier CRT terminal or a high speed printer is sub ject to many types of electrical noise Noise can get to the processor directly through the power supply or it can be induced onto the board by electromagnetic fields It is also possible for the PC board to find itself in the path of electrostatic discharges Glitches and noise on the PC board can cause the processor to act unpredictably usually by changing either the memory locations or the program counter
134. g Mode Used to signify that the PROG pulse applied for a programming operation was longer than allowed PROGRAM VERIFIED A signal output after programming in the Auto Configuration Byte Programming Mode The signal is on Port 2 0 and is asserted as a logic 1 if the bytes program correctly PROGRAMMING ALE INPUT Used by a device in the Auto Program Configuration Byte Mode to indicate that Port 3 contains the data to be programmed into the PCCB and CCB Figure 33 Programming Mode Pin Definitions 2 34 intel 8X9X HARDWARE DESIGN INFORMATION 10 3 Auto Configuration Byte Programming Mode The Programming Chip Configuration Byte PCCB is a non memory mapped EPROM location It gets load ed into the CCR during reset for auto and slave pro gramming The Auto Configuration Byte Programming Mode programs the PCCB The Chip Configuration Byte CCB is at location 2018H and can be programmed like any other EPROM location using auto slave and run time programming However you can also use the Auto Configuration Byte Programming to program the CCB when no other locations need to be programmed The CCB is pro grammed with the same value as the PCCB The Auto Configuration Byte Programming Mode is entered by following the power up sequence described in Section 10 1 with PMODE ODH Port 4 OFFH and Port 3 the data to be programmed into the PCCB and CCB When a 0 is placed on PALE the CCB and PCCB are automatically programm
135. g because address 201AH is not part of the PROGRAM POP temp POP address_temp POP data temp PUSH temp PUSHF LDB int mask fenable swt only LDB HSO COMMAND fSWIO ovf ADD HSO TIME TIMER1 fprogram pulse EI ST data temp address_temp CALL 201AH POPF RET SWT ISR SwtO expired POP 0 RET 8X9X HARDWARE DESIGN INFORMATION EPROM If the program is executing from external memory no program fetches or pre fetches will occur from internal memory 10 6 1 RUN TIME PROGRAMMING AND THE CCB PCCB For run time programming CCR is loaded with the Run time programming is done with equal to a TTL high internal execution so the internal CCB must correspond to the memory system of the applica tion setup You can use Auto Configuration Byte Pro gramming or a generic programmer to program the CCB before using run time programming The CCB can also be programmed during Run Time Programming like any other EPROM location stake parameters from the STACK save current status enable only swt interrups sload swt command to interrupt swhen program pulse time has elapsed Start programming Jump to Self until program pulse time has expired Figure 39 Programming the EPROM from Internal Memory Execution 2 40 intel Data programmed into the CCB takes effect upon reset If the WRITE lock bit of the CCB is enabled the array can no longer be programmed You should only pro
136. ggr 1 5 LSB and all code widths equal to one LSB INPUT RESISTANCE The effective series resistance from the analog input pin to the sample capacitor LSB LEAST SIGNIFICANT BIT The voltage value corresponding to the full scale voltage divided by 2n where n is the number of bits of resolution of the con verter For a 10 bit converter with a reference voltage of 5 12 volts one LSB is 5 0 mV Note that this is different than digital LSBs since an uncertainty of two LSB when referring to an A D converter equals 10 mV This has been confused with an uncertainty of two digital bits which would mean four counts or 20 mV MONOTONIC The property of successive approxi mation converters which guarantees that increasing in put voltages produce adjacent codes of increasing value and that decreasing input voltages produce adjacent codes of decreasing value NO MISSED CODES For each and every output code there exists a unique input voltage range which produces that code only NON LINEARITY The maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal characteris tics intel OFF ISOLATION Attenuation of a voltage applied on a deselected channel of the A D converter Also referred to as Crosstalk REPEATABILITY tThe difference between corre sponding code transitions from different actual charac teristics taken from the same converter on t
137. gram counter onto the stack and then loads the program counter with the contents of the vector table entry corre sponding to the interrupt The hardware will not al low another interrupt to be serviced immediately fol lowing the interrupt call This guarantees that once the interrupt call starts the first instruction of the interrupt service routine will execute b The PUSHF instruction which is now guaranteed to execute saves the PSW in the stack and then clears the PSW The PSW contains in addition to the arithmetic flags the MASK register and the global disable flag I The hardware will not allow an interrupt following a PUSHF instruction and by the time the LD instruction starts all of the inter rupt enable flags will be cleared Now there is guar anteed execution of the LD INT MASK instruc tion c The LD INT MASK instruction enables those in terrupts that the programmer chooses to allow to interrupt the serial I O interrupt service routine In this example only the HSI data available interrupt will be allowed to do this but any interrupt or combi nation of interrupts could be enabled at this point even the serial interrupt It is the loading of the INT MASK register which allows the software to establish its own priorities for interrupt servicing in dependently from those that the hardware enforces d The EI instruction reenables the processing of inter rupts e The actual interrupt service routine exe
138. h the device puts itself into an endless loop of internal execution If the keys match the device dumps data to external locations 4000 5 and 9000H 91FFH on the 879XBH and the 8798 and to external locations 4000H 7FFFH and 9000H 937FH on the 879XJF The data starting at location 9000H will be indeterminate The data start ing at location 4000H will contain the internal ROM EPROM beginning with internal address 2000H 10 8 Modified Quick Pulse Programming Algorithm The Modified Quick Pulse Programming Algorithm calls for each EPROM location to receive 25 separate 100 ps 5 us program cycles Verification of correct programming is done after the 25 pulses If the location verifies correctly the next location is programmed If the location fails to verify the location has failed Once all locations are programmed and verified the entire EPROM is again verified Programming of 879X devices is done with Vpp 12 75V 0 25 and 5 0 0 5 10 9 Signature Word The 8X9X contains a signature word at location 2070H The word can be accessed in the slave mode by executing a word dump command see Table 2 Table 2 8X9XBH Signature Words Deve Signature Word B79XBH 896FH 839XBH 896EH 809XBH Undefined 879XJF 896BH 839XJF 896AH 809XJF Undefined 10 10 Erasing the EPROM Initially and after each erasure all bits of the 879X are in the 1 state Data is introduced by
139. hdog Timer overflows Details of hardware sug gestions for reset can be found in Section 1 4 of the Hardware Design chapter 13 2 Reset Status The I O lines and control lines of the 8X9X will be in their reset state within 10 XTALI periods after reset is low with and the oscillator stabilized See Figure 44 Prior to that time the status of the I O lines is indeterminate After the 10 state time reset se quence the Special Function Registers will be set as follows Port 1 XXXXXXXXB Port 2 XXOXXXX1B Port 3 11111111B Port 4 11111111B PWM Control 00H Serial Port Transmit undefined Serial Port Receive undefined Baud Rate Register undefined Serial Port Control XXXXOXXXB Serial Port Status X00XXXXXB A D Command undefined A D Result undefined Interrupt Pending undefined Interrupt Mask 00000000B Timer 1 0000H Timer 2 0000H Watchdog Timer 0000H HSI Mode XXXXXXXXB HSI Status undefined 1050 00000000B 1051 00000000B 0 0 IOC1 XOXOXXX18 HSI FIFO empty HSO CAM empty HSO SFR 000000B PSW 0000H Stack Pointer undefined Program Counter 2080H Figure 42 Register Reset Status 1 47 MCS 2 96 8X9X ARCHITECTURAL OVERVIEW Port 1 and Port 2 6 2 7 reset to a strong or weak pull up condition HSO 4 and HSO 5 reset to a floating con dition as they are disabled by IOC1 4 and IOC1 6 Other conditions following a reset are Pin ResetVaue RD high WR WRL high high high
140. he input voltage may have changed in order to produce a one count change in the conversion result Non Linearity is the worst case deviation of code tran sitions from the corresponding code transitions of the Ideal Characteristic Non Linearity describes how much Differential Non Linearities could add up to pro duce an overall maximum departure from a linear char acteristic If the Differential Non Linearity errors are too large it is possible for an A D converter to miss codes or exhibit non monotonicity Neither behavior is desireable in a closed loop system converter has missed codes if there exists for each output code a unique input voltage range that produces that code 2 15 8X9X HARDWARE DESIGN INFORMATION only converter is monotonic if every subsequent code change represents an input voltage change in the same direction Differential Non Linearity and Non Linearity are quantified by measuring the Terminal Based Linearity Errors A Terminal Based Characteristic results when an Actual Characteristic is shifted and rotated to elimi nate zero offset and full scale error see Figure 17 The Terminal Based Characteristic is similar to the Actual Characteristic that would be seen if zero offset and full scale error were externally trimmed away In practice this is done by using input circuits which include gain and offset trimming In addition on the 8X9X could also be closely regulated and trimmed within the
141. he same channel at the same temperature voltage and frequency conditions RESOLUTION The number of input voltage levels that the converter can unambiguously distinguish be tween Also defines the number of useful bits of infor mation which the converter can return SAMPLE DELAY The delay from receiving the start conversion signal to when the sample window opens SAMPLE DELAY UNCERTAINTY The variation in the Sample Delay SAMPLE TIME The time that the sample window is open SAMPLE TIME UNCERTAINTY The variation in the sample time SAMPLE WINDOW Begins when the sample capac itor is attached to a selected channel and ends when the sample capacitor is disconnected from the selected channel SUCCESSIVE APPROXIMATION An A D con version method which uses a binary search to arrive at the best digital representation of an analog input TEMPERATURE COEFFICIENTS Change in the stated variable per degree centigrade temperature change Temperature coefficients are added to the typi cal values of a specification to see the effect of tempera ture drift BUFFER TO MAKE OUTPUT SWING ACTIVE OPTIONAL 8X9X HARDWARE DESIGN INFORMATION TERMINAL BASED CHARACTERISTIC An Ac tual Characteristic which as been rotated and translat ed to remove zero offset and full scale error REJECTION Attenuation of noise on the line to the A D converter ZERO OFFSET The difference between the
142. hm 2 42 10 9 Signature Word 2 42 10 10 Erasing the EPROM 2 42 11 0 QUICK REFERENCE 2 42 11 1 Pin Description 2 42 2 45 11 3 Packaging 2 46 11 4 Package Diagrams 2 47 11 5 Memory Map 2 49 11 6 Instruction Summary 2 50 11 7 Opcode and State Time Listing 2 52 11 8 SFR Summary eese intel 8X9X HARDWARE DESIGN INFORMATION OVERVIEW This chapter of the manual is devoted to the hardware engineer All of the information you need to connect the correct pin to the correct external circuit is provid ed Many of the special function pins have different characteristics which are under software control Therefore it is necessary to define the system complete ly before the hardware is wired up Frequently within this chapter a specification for a cur rent voltage or time period is referred to the values provided are to be used as an approximation only The exact specification can be found in the latest data sheet for the particular device and temperature range that is being used This chapter is written about 8X9XBH 8X9XJF and 8X98 devices These devices are generically referred to as the 8X9X information in this chapter refers to the 8X9X BH the 8X9XJF and the 8X98 unless other wise noted 1 0 REQUIRED HARDWA
143. ification af ter ALE falls or the processor could lock up There is j b Tos TYLYH 2 gt 2 para 4 gt TwHLH 2 TwHox T RHBX 7 I Twn wi CC 270246 26 Figure 22 Bus Signal Timings 2 24 ntel 8X9X HARDWARE DESIGN INFORMATION no requirement as to when READY may go high as long as the maximum READY low time TYLYH is not violated To ensure that only one wait state is in serted it is necessary to provide external circuitry which brings READY high TLLYH after the falling edge of ALE ADV or program the Chip Configuration Regis ter to select a Ready Control limit of one Internally the chip latches READY on the first falling edge of Phase A after ALE ADV falls Phase A is buff ered and brought out externally as CLOCKOUT so CLOCKOUT is a delayed Phase A If a 1 is seen the bus cycle proceeds uninterrupted with no wait state in sertions If a O is seen one wait state 3 Tosc is insert ed Tosc Oscillator Period one cycle time on XTALI Timings the Memory System Must Meet TLLYH ALE ADV low to READY high Maxi mum time after ALE ADV falls until READY is brought high to ensure no more wait states If this time s exceeded une
144. indicates that Ports 3 and 4 contain valid programming address command information input to slave PROG A falling edge in Slave Programming Mode indicates that Ports 3 and 4 contain valid programming data input to slave A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly A high signal in Slave Programming Mode indicates the device was programmed correctly PDO A low signal in Slave Programming Mode indicates that the PROG pulse was applied for longer than allowed Not available on Shrink DIP package available on 48 pin device Port 0 0 1 2 3 not available on 48 pin device 3 16 intel 6 0 OPCODE TABLE SHR SHL SHRA RESERVED SHRL SHLL SHRAL NORML RESERVED CLRB NOTB NEGB XCHB DECB EXTB INCB SHRB SHLB SHRAB RESERVED RESERVED RESERVED RESERVED SJMP SJMP SJMP SJMP SJMP SJMP SJMP SJMP SCALL SCALL SCALL SCALL SCALL SCALL SCALL SCALL JBC JBC JBC JBC 3 17 8X9X QUICK REFERENCE JBS JBS JBS JBS AND DIRECT 3 OPS AND IMMEDIATE 3 OPS AND INDIRECT 3 OPS AND INDEXED 3 OPS ADD DIRECT 3 OPS ADD IMMEDIATE 3 OPS ADD INDIRECT 3 OPS ADD INDEXED 3 OPS SUB DIRECT 3 OPS SUB IMMEDIATE 3 OPS SUB INDIRECT 3 OPS SUB INDEXED 3 OPS MULU DIRECT 3 OPS MULU IMMEDIATE 3 OPS MULU INDIRECT 3 OPS MULU INDEXED 3 OPS ANDB DIRECT
145. ins three types of port lines quasi bidirectional input and output The input and output lines are shared with other functions in the 8X9X as shown in Table 4 Ports 3 and 4 are open drain bidirectional ports which share their pins with the address data bus Table 4 Port 2 Alternate Functions Alternate Controlled Function by P2 0 Output TXD Serial Port Transmit RXD Serial Port Receive M1 3 RXD Serial Port Output MO EXTINT External Interrupt T2CLK Timer 2 Input T2RST Timer 2 Reset PWM Pulse Width Modulation Quasi Bidirectional Quasi Bidirectional Section 2 of the Hardware Design chapter contains ad ditional information on the timing drive capabilities and input impedances of I O pins Input Output Input Input Input Output 10 1 Input Ports Input ports and pins can only be read There are no output drivers on these pins The input leakage of these pins is in the microamp range The specific values can be found in the data sheet for the device being consid ered In addition to acting as a digital input each line of Port O can be selected to be the input of the A to D converter as discussed in Section 8 The pins on Port O are tested intel to have D C leakage of 3 microamps or less as speci fied in the data sheet for the device being considered The capacitance on these pins is approximately 5 pF and will instantaneously increase by around 5 pF when the pin is being sampled
146. intel 8X9X USER S MANUAL ORDER NO 272457 001 DECEMBER 1993 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein Intel retains the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation Intel Corporation and Intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Other brands and names are the property of their respective owners Additional copies of this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 c INTEL CORPORATION 1993 8X9X USER S MANUAL CONTENTS PAGE CHAPTER 1 MCS 96 8X9X Architectural Overview 1 1 CHAPTER 2 8X9X Hardware Design Information 2 1 CHAPTER 3 8X9X Quick Reference 3 1 MCS 96 8X9X Architectural 1 Overview October 1990 MCS 96 8X9X Architectural Overview Order Number 270250 005 MCS 96 8X9X ARCHITECTURAL OVERVIEW CONTENTS PAGE 1 0 CPU OPERAT
147. interrupts Since interrupts are not synchronized it is possible to have multiple interrupts at the same time value 7 4 Using Timer 2 with the HSO Timer 1 is incremented only once every 8 state times When it is being used as the reference timer for an HSO action the comparator has a chance to look at all 8 CAM registers before Timer 1 changes its value Fol lowing the same reasoning Timer 2 has been synchro nized to allow it to change at a maximum rate of once per 8 state times Timer 2 increments on both edges of the input signal When using Timer 2 as the HSO reference caution must be taken that Timer 2 is not reset prior to the highest value for a Timer 2 match in the CAM This is because the HSO CAM will hold an event pending until a time match occurs if that match is to a time value on Timer 2 which is never reached the event will remain pending in the CAM until the device is reset Additional caution must be used when Timer 2 is being reset using the HSO unit since resetting Timer 2 using the HSO is an internal event and can therefore happen at any time within the eight state time window This situation arises when the event is set to occur when MCS 96 8X9X ARCHITECTURAL OVERVIEW Timer 2 is equal to zero If HSI O or the T2RST pin is used to clear Timer 2 and Timer 2 equal to zero trig gers the event then the event may not occur This is because HSLO and T2RST clear Timer 2 asynchro nously and Timer 2
148. ions The remaining operations on 32 bit variables can be implemented by combinations of 16 bit operations As an example the sequence ADD ADDC AX CX BX DX performs a 32 bit addition and the sequence SUB SUBC AX CX BX DX performs a 32 bit subtraction Operations on REAL i e floating point variables are not supported directly by the hardware but are supported by the floating point library for the 8X9X FPAL 96 which implements a single precision subset of the proposed IEEE standard for floating point operations The performance of this software is significantly improved by the 8X9X NORML instruction which normalizes a 32 bit vari able and by the existence of the ST flag in the PSW In addition to the operations on the various data types the 8X9X supports conversions between these types 1 22 LDBZE load byte zero extended converts a BYTE to a WORD and LDBSE load byte sign extended con verts SHORT INTEGER into an INTEGER WORDS can be converted to DOUBLE WORDS by simply clearing the upper WORD of the DOUBLE WORD CLR and INTEGERS can be converted to LONGS with the EXT sign extend instruction The MCS 96 instructions for addition subtraction and comparison do not distinguish between unsigned words and signed integers Conditional jumps are provided to allow the user to treat the results of these operations as either signed or unsigned quantities As an example the CMPB compare byte instruction is
149. ive voltage changes on the inputs The more demanding the application is on the A D converter the more im portant it is to fully understand the converter s opera tion For simple applications knowing the absolute er ror of the converter is sufficient However closing a servo loop with analog inputs necessitates a detailed understanding of an A D converter s operation and er rors The errors inherent in an analog to digital conversion process are many quantizing error zero offset full scale error differential non linearity and non linearity These are transfer function errors related to the A D converter In addition converter temperature drift rejection sample hold feedthrough multiplexer off isolation channel to channel matching and random noise should be considered Fortunately one Absolute Error specification is available which describes the sum total of all deviations between the actual conver sion process and an ideal converter However the vari ous sub components of error are important in many applications These error components are described in Section 3 5 and in the text below where ideal and actual converters are compared An unavoidable error simply results from the conver sion of a continuous voltage to an integer digital repre sentation This error is called quantizing error and is always 0 5 LSB Quantizing error is the only error seen in a perfect A D converter and is obviously pres
150. l operands The opcodes for signed multiply and divide are the opcodes for the unsigned functions with an FE appended as a second byte of instructions using any Indirect or indexed addressing mo prefix Long State times shown for 16 bit bus 3 23 8X9X QUICK REFERENCE 8 0 OPCODES INSTRUCTION LENGTH AND STATE TIMES Continued INDEXED SHORT ONG S31A8 3 31V1S 2 INDIRECT O NORMAL 1 lt 5 31715 g IMMEDIATE o o a o DIRECT eic 0310181 5 5 413 S ea zie 2341915 el Sl r s SlSpepe P nlii a alata ala EI o sted 2 sanu Z 3 8 D t 2 2 lt lt 82202848581 858 lt lt ONEN 8454 4824 1828601 reu 90 a comm tele oo 3 o S
151. lave PC can be many bytes ahead of the CPU program counter an instruction that is located after address 3FFAH may not be allowed to access protected memo ry even though the instruction is itself protected If the bus controller receives a request to perform a READ of protected memory the READ sequence oc curs with indeterminant data being returned to the CPU Figure 41 shows the effects of enabling the READ and WRITE lock bits Figure 41 intel 8X9X HARDWARE DESIGN INFORMATION Other enhancements were also made to the 8X9X for program protection For example the value of EA is latched on reset so that the device cannot be switched from external to internal execution mode at run time In addition if READ protection is selected an NMI event will cause the device to switch to external only execution mode Internal execution can only resume by resetting the chip 10 7 2 ROM DUMP MODE You can use the security key and ROM dump mode to dump the interna ROM EPROM for testing purposes The security key is a 16 byte number The internal ROM EPROM must contain the security key at loca tions 2020H 202FH The user must place the same security key at external address 4020H 402FH Before doing ROM dump the device checks that the keys match The ROM dump mode is entered by following the power up sequence described in Section 10 1 with PMODE 06H The device first verifies the security keys If the security keys do not matc
152. least one state time to initiate a reset The reset takes 13 states at which time the program restarts at location 2080H 7 Execution will take at least 8 states even for 0 shift 8 State times shown for 16 bit bus 9 0 INTERRUPT TABLE Vector Location High Low Byte Byte Software Trap Not Applicable Extint 7 Highest Serial Port Software Timers 1 0 High Speed Outputs HSI Data Available A D Conversion Complete Timer Overflow 0 Lowest 3 26 intel 8X9X QUICK REFERENCE 10 0 FORMULAS 11 0 RESET STATUS 000090008 Baud Rate Calculations Using XTAL1 Baud _ XTAL1 frequency Mode 0 Rate 4 B 3 1 Baud _ XTAL1 frequency Rate 64 1 Others Using T2CLK Baud _ T2CLK frequency Mode 0 Baud _ T2CLK frequency Others Rate 16 B 0 Note that B cannot equal 0 except when using XTAL1 in other than Mode 0 8X9XBH Signature Word Signature Word 879XBH 896FH 839XBH 896EH 809XBH Undefined HSO 0 HSO 1 HSO 2 HS0 3 low _____ HSO 4 HSOS _______ floating high ALE RD hn EHE WRR INST 3 27
153. lly 0 7V The 8X9X will input this value as a zero even if a one has been written to the port pin When this happens the XORB instruction will always write a one to the port pin s SFR and the pin will not toggle The second problem which is related to the first is that if P1 0 happens to be driven to a zero when Port 1 is read by the XORB instruction then the XORB will write a zero to P1 0 and it will no longer be useable as an input The first situation can best be solved by the external driver design A series resistor between the port pin and the base of the transistor often works by bringing up the voltage present on the port pin The second case can be taken care of in the software fairly easily LDB AL IOPORT1 XORB AL 0108 ORB AL 0018 STB AL A software solution to both cases is to keep a byte in RAM as an image of the data to be output to the port any time the software wants to modify the data on the port it can then modify the image byte and copy it to the port If a switch is used on a long line connected to a quasi bidirectional pin a pullup resistor is recommended to reduce the possibility of noise glitches and to decrease 2 10 inte 8X9X HARDWARE DESIGN INFORMATION the rise time of the line On extremely long lines that are handling slow signals a capacitor may be helpful in addition to the resistor to reduce noise 2 3 Input Only Ports The high impedance input pins on the 8X9X h
154. log outputs can be 2 z o 2 lt 8X9X HARDWARE DESIGN INFORMATION generated with either the chip s PWM output or HSO unit This section describes the analog input sugges tions See Section 4 for analog output The 8X9X s Integrated A D converter includes an eight channel analog multiplexer sample and hold cir cuit and 10 bit analog to digital converter Figure 12 The 8X9X can therefore select one of eight analog in puts to convert sample and hold the input voltage and convert the voltage into a digital value Each conver sion takes 22 microseconds including the time required for the sample hold with XTAL1 12 MHz The method of conversion is successive approximation Section 3 5 contains the definitions of numerous terms used in connection with the A D converter SUCCESSIVE APPROXIMATION A D CONVERTER AD_COMMAND START CONVERSION 270246 13 Figure 12 A D Converter Block Diagram 2 12 3 1 A D Overview The conversion process is initiated by the execution of HSO command OFH or by writing a one to the GO Bit in the A D Control Register Either activity causes a start conversion signal to be sent to the A D converter control logic If an HSO command was used the con version process will begin when Timer 1 increments This aids applications attempting to approach spectral ly pure sampling since successive samples spaced by equal Timer 1 delays will occur with
155. lowing INST pin for memory expansion Four additional Analog Input channels Non Maskable Interrupt for debugging One additional Quasi Bidirectional B Bit Parallel Port ePackage Designators Four additional Port 2 pins with multiplexed features PLCC Timer 2 Clock Source Pin C Ceramic DIP Timer 2 Reset pin Ceramic Pin Grid Array Two additional quasi bidirectional port pins P Plastic OIP Ceramic LCC Shrink DIP 2 31 inte 8X9X HARDWARE DESIGN INFORMATION 10 0 USING THE EPROM This section refers to the 879XBH 8798 and 879XJF devices These devices are generically referred to as the 879X All information in this section refers to all three devices unless otherwise noted 879XBH and the 8798 contain 8 Kbytes of ultraviolet Erasable and electrically Programmable Read Only Memory EPROM The 879XJF contains 16 Kbytes of EPROM When EA is a TTL high the EPROM is located at memory locations 2000H through 3FFFH on the 879XBH and the 8798 It is at locations 2000H through 5FFFH on the 879XJF Applying 12 75V to EA when the chip is reset places the 879X device in the EPROM Programming The Programming Mode supports EPROM program ming and verification The following is a brief descrip tion of each of the programming modes The Auto Configuration Byte Programming Mode programs the Programming Chip Configuration Byte and the Chip Configuration Byte The Auto Programming Mode enables an 879X to progr
156. ly The sink capability of these pins is on the order of 0 8 milliamps so the total pullup current to the pin must be less than this A 15K pullup resistor will source a maximum of 0 33 milliamps so it would be a reasonable value to choose if no other circuits with pullups were connected to the pin PUS PULLDOWN POAT 3 4 OPEN ORAIN DRIVER 270246 19 PORT PULLDOWN BUS P1 P2 TYPICAL 270246 20 These graphs show typical pin capabilities they are not guaranteed specifications Figure 11 Bus and Port 3 and 4 Pins intel 2 5 HSO Pins Control Outputs and Bus Pins The control outputs and HSO pins have output buffers with the same output characteristics as those of the bus pins Included in the category of control outputs are TXD RXD in_Mode 0 PWM CLKOUT ALE BHE RD and WR The bus pins have 3 states output high output low and high impedance input As a high output the pins are specified to source around 200 pA to 2 4 volts but the pins can source on the order of ten times that value in order to provide the fast rise times When used as a low output the pins can sink around 2 mA at 0 45 volts and considerably more as the voit age increases When in the high impedance state the pin acts as a capacitive load with a few microamps of leakage Figure 11 shows the internal configuration of a bus pin 3 0 ANALOG INPUTS The on chip A D converter of the 8X9X can be used to digitize analog inputs while ana
157. mes except when the 8 transition mode is used in which case it is 1 transition per state time The divide by eight counter can only be zeroed in mid count by performing a hard ware reset on the 8 9 HSI Mode 03H 51 0 MODE HSI 1 MODE HSI 2 MODE 51 5 MODE WHERE EACH 2 MODE CONTROL FIELD DEFINES ONE OF 4 POSSIBLE MODES 00 8 POSITIVE TRANSITIONS O1 EACH POSITIVE TRANSITION 10 EACH NEGATIVE TRANSITION 11 EVERY TRANSITION POSITIVE AND NEGATIVE 270250 24 Figure 25 HSI Mode Register Diagram The HSI lines can be individually enabled and disabled using bits in IOCO at location 0015H Figure 26 shows the bit locations which control the HSI pins If the pin is disabled transitions will not be entered in the FIFO T2RST 10 0 5 060 3 1000 0 060 2 T2 RESET HSI HSI TIMER2 CLOCK zES T20LK 060 7 7 10CO 4 HSL2 060 6 5 5 O HSI HSI 270250 25 Figure 26 IOCO Control of HSI Pin Functions 6 2 HSI FIFO When an HSI event occurs a 9X 20 FIFO stores the 16 bits of Timer 1 and the 4 bits indicating which pins had 1 33 MCS 96 8X9X ARCHITECTURAL OVERVIEW events It can take up to 8 state times for this informa tion to reach the holding register For this reason 8 state times must be allowed between consecutive reads of HSI TIME When the FIFO is full for a total
158. minally 3 Tosc periods TLLRL ALE ADV low to READ WRITE low high to OUTPUT not valid Length of time after ALE ADV falls before RD or Time that the OUTPUT data is valid after WR is WR fall Could be needed to ensure that proper mem high Nominally 1 Tosc period ory decoding takes place before it is output enabled Nominally 1 Tosc period TWHLH WRITE high to ALE ADV high Time between write high and next ALE ADV also used to TLLHL ALE ADV low to WRL low Min calculate the time between WR high and next AD imum time after ALE ADV is low that the write DRESS valid Nominally 2 Tosc periods strobe signals will go low Could be needed to ensure Figure 23 Timing Specification Explanations Continued 2 26 inte 8X9X HARDWARE DESIGN INFORMATION 7 4 INST Line Usage The INST Instruction line is high during bus cycles that are for an instruction fetch and low for any other bus cycle The INST signal not present on 48 pin ver sions can be used with a logic analyzer to debug a system In this way it is possible to determine if a fetch was for instructions or data making the task of tracing the program much easier 7 5 BUSWIDTH Pin Usage The BUSWIDTH pin is a control input which deter mines the width of the bus access in progress BUSWIDTH is sampled after the rising edge of the first CLOCKOUT after ALE ADV goes low If a one is seen the bus access progresses as 16
159. n Figure 22 can be read or modified as a byte register It can be read to deter mine which of the interrupts are pending at any given time or modified to either clear pending interrupts or generate interrupts under software control Any soft ware which modifies the INT PENDING register should ensure that the entire operation is indivisible The easiest way to do this is to use the logical instruc tions in the two or three operand format for example ANDB INT_PENDING 11111101B 3 Clears the A D Interrupt ORB INT_PENDING 00000010B Sets the A D Interrupt Caution must be used when writing to the pending reg ister to clear interrupts If the interrupt has already been acknowledged when the bit is cleared a 4 state time partial interrupt cycle will occur This is be cause the 8X9X will have to fetch the next instruction of the normal instruction flow instead of proceeding with the interrupt processing as it was going to The effect on the program will be essentially that of an extra NOP This can be prevented by clearing the bits using a 2 operand immediate logical as the 8X9X holds off acknowledging interrupts during these read modify write instructions LOCATION 09H E TIMER OVERFLOW A D COMPLETION HSI DATA AVAILABLE HSO EVENT HSI BIT O SOFTWARE TIMERS SERIAL 1 0 EXTERNAL INTERRUPT 270250 19 Figure 22 interrupt Pending Register interrupt Mask Register Individual interrupt
160. nd the current through the pin to 40 milliamps If it is necessary to disable the Watchdog Timer for more than a brief test the software solution of never initiating the timer should be used See Section 14 in the Architecture Chapter 270246 9 270246 10 Figure 9 Reset Logic 2 8 inte 8X9X HARDWARE DESIGN INFORMATION 1 7 Power Down Circuitry Battery backup can be provided on the 8X9X with a 1 mA current drain at 5 volts This mode will hold loca tions OFOH through OFFH valid as long as the power to the Vpp pin remains on The required timings to put the device into power down and an overview of this mode are given in Section 2 3 in the 8X9X Architecture Chapter A key can be written into power down RAM while the device is running This key can be checked on reset to determine if it is a start up from power down or a complete cold start In this way the validity of the pow er down RAM can be verified The length of this key determines the probability that this procedure will work however there is always a statistical chance that the RAM will power up with a replica of the key Under most circumstances the power fail indicator which is used to initiate a power down condition must come from the unfiltered unregulated section of the power supply The power supply must have sufficient storage capacity to operate the 8X9X until it has com pleted its reset operation 2 0 DRIVE AND INTERFACE LEVELS There
161. ned 6 2 Mode 1 Timings Mode 1 operation of the serial port makes use of 10 bit data packages a start bit 8 data bits and a stop bit The transmit and receive functions are controlled by sepa rate shift clocks The transmit shift clock starts when the baud rate generator is initialized the receive shift clock is reset when a 1 to 0 transition start bit is received The transmit clock may therefore not be in sync with the receive clock although they will both be at the same frequency The TI Transmit Interrupt and RI Receive Inter rupt flags are set to indicate when operations are com plete TI is set when the last data bit of the message has been sent not when the stop bit is sent If an attempt to send another byte is made before the stop bit is sent the port will hold off transmission until the stop bit is com plete RI is set when 8 data bits are received not when the stop bit is received Note that when the serial port status register is read both TI and RI are cleared TXD 8X9X HARDWARE DESIGN INFORMATION bes cr NEC oca 00 o Jj os A Jj os 01 02 RXD IN XTAL1 03 05 05 07 UU TU Jeux 050 353 02 270246 24 Figure 20 Serial Port Timings in Mode 0 CLOCK INHIBIT SHIFT LOAD 270246 25 Figure 21 Mode 0 Serial Port Example Caution should be used wh
162. never SP STAT not SP CON is accessed Whenever the TXD pin is used for the serial port it must be enabled by setting IOC1 5 to a 1 IOCI is discussed further in Section 11 3 Information on the hardware connections and timing of the serial port is in Section 6 of the Hard ware Design chapter STOP NSTART X Di X X 04 05 D6 07 STOP ace 10 BIT FRAME 270250 35 Figure 35 Serial Port Frame Mode 1 stop _start Do X o o2 y os 4 os oe X De stop 8 BITS OF DATA ho res PROGRAMMABLE STH BIT 11 FRAME 270250 36 Figure 36 Serial Port Frame Modes 2 and 3 1 40 LOCATION 11H SP STAT READ ONLY MCS 96 8X9X ARCHITECTURAL OVERVIEW SP CON WRITE ONLY 7 RBS RPE NOTE and RI are cleared when STAT is read M2 1 SPECIFIES THE ENABLE THE PARITY FUNCTION EVEN PARITY ENABLES THE RECEIVE FUNCTION PROGRAMS THE STH DATA SIT IF NOT PARITY ON TRANSMISSION IS THE TRANSMIT INTERRUPT FLAG IS THE RECEIVE INTERRUPT FLAG 15 THE 9TH DATA BIT RECEIVED IF NOT PARITY IS THE PARITY ERROR INDICATOR IF PARITY ACTIVE 270250 33 Figure 37 Serial Port Control Status Register In Mode 0 if REN 0 writing to SBUF tx will start a transmission Causing a rising edge on REN or clear ing RI with REN 1 will start a reception Setting REN 0 will stop a reception in progress and inhibit further receptions To
163. nformation can be found in the following documents MCS 96 MACRO ASSEMBLER USER S GUIDE Order Number 186 ASM 96 Intel Systems Order Number D86 ASM 96NL DOS Systems 96 USER S GUIDE Order Number D86 C96NL DOS Systems PL M 96 USER S GUIDE Order Number 186 PLM 96 Intel Systems Order Number D86 PLM 96NL DOS Systems Throughout this section short sections of code are used to illustrate the operation of the device For these sec tions it has been assumed that a set of temporary regis ters have been predeclared The names of these registers have been chosen as follows AX BX CX and DX are 16 bit registers AL is the low byte of AX AH is the high byte BL is the low byte of BX CL is the low byte of CX DL is the low byte of DX These are the same as the names for the general data registers used in the 8086 80186 It is important to note however that in the 8X9X these are not dedicat ed registers but merely the symbolic names assigned by the programmer to an eight byte region within the on board register file 3 1 Operand Types The MCS 96 architecture provides support for a vari ety of data types which are likely to be useful in a con trol application In the discussion of these operand types that follows the names adopted by the PLM 96 programming language will be used where appropriate To avoid confusion the name of an operand type will be capitalized A is an unsigned eight bit vari
164. ng edge of CLKOUT and be stable by its falling edge Information from the HSO can be latched on the CLKOUT falling edge Internal events can occur any time during the 8 state time window Timer 2 is synchronized to increment no faster than Timer 1 so there will always be at least one increment ing of Timer 1 while Timer 2 is at a specific value 5 2 HSI Input Sampling The HSI pins are sampled internally once each state time Any value on these pins must remain stable for at least 1 full state time to guarantee that it is recognized The actual sample occurs at the end of Phase A which due to propagation delay is just after the rising edge of CLKOUT Therefore if information is to be synchro nized to the HSI it should be latched in on CLKOUT intel falling The time restriction applies even if the divide by eight mode is being used If two events occur on the same pin within the same 8 state time window only one of the events will be recorded If the events occur on different pins they will always be recorded regardless of the time difference The 8 state time window i e the amount of time during which Timer 1 remains con stant is stable to within about 20 ns The window starts roughly around the rising edge of CLKOUT however this timing is very approximate due to the amount of internal circuitry involved 5 3 Standard I O Port Pins Port 0 is different from the other digital ports in that it is actually part of the A D
165. not possible to cause a metastable condition once the device is in a valid not ready condition To cause one wait state to occur the rising edge of READY must occur before TLLYH MAX after ALE falls If the signal is brought up after this time two wait states may occur If two wait states are desired READY should be brought high within the TLLYH specification 3 Tosc Additional wait states can be caused by adding additional state times to the READY low time The maximum amount of time that a device may be held not ready is specified as TYLYH The 8X9X has the ability to internally limit the number of wait states to 1 2 or 3 as determined by the value in the Chip Configuration Register CCR Using the CCR for ready timing is discussed at the end of this section If a ready limit is set the TLLYH MAX speci fication is not used OPERATING MODES The 8X9X supports a variety of options to simplify memory systems interfacing requirements and ready control Bus flexibility is provided by allowing selection of bus control signal definitions and runtime selection of the external bus width In addition several ready control modes are available to simplify the external hardware requirements for accessing slow devices The Chip Configuration Register CCR is used to store the operating mode information intel MCS 96 8X9X ARCHITECTURAL OVERVIEW CHIP CONFIGURATION REGISTER CCR Configuration information is stored in the Chip C
166. note that this decoding inserts a delay in the write signal which must be considered in a sys tem timing analysis 8X9X HARDWARE DESIGN INFORMATION External memory systems for the 8X9X can be set up in many ways Figures 25 through 28 show block dia grams of memory systems using an 8 bit bus with a single EPROM using an 8 bit bus with RAM and EPROM using a 16 bit bus with two external EPROMs and using 16 bit bus in a RAM and ROM system The timings for the systems shown are opti mized for 10 MHz operation OE HIGH ADDRESS DATA EPROM LOW ADDRESS OPTIONAL IF LATCHED EPROM IS USED 270246 28 65 cs HIGH ADDRESS DATA EPROM LOW ADDRESS LOW ADDRESS OE E OE Figure 26 An 8 Bit Bus with EPROM and RAM 270246 29 2 28 BUSWIDTH 8 15 8X9X HARDWARE DESIGN INFORMATION es es HIGH ADDRESS HIGH ADDRESS iin 173 LOW ADDRESS LOW ADDRESS 270246 30 Figure 27 16 Bit Bus with EPROM Only cs HIGH ADDRESS HIGH ADDRESS HIGH ADDRESS EPROM RAM DATA 270246 31 Figure 28 Memory System with Dynamic Bus Width 2 29 intel 8X9X HARDWARE DESIGN INFORMATION 7 7 O Port Reconstruction When a single chip system is being designed using a multiple chip system as a prototype it may be neces sary to reconstruct I O Ports 3 and 4 using a memory mapped I O technique The circuit shown in Figure 30 provides this
167. of the chip to assure highest accuracy To achieve this it may be desirable to separate the analog power supply from the digital power supply The pin supplies the digital circuitry in the A D converter and provides the 5 volt reference to the analog portion of the converter and ANGND must be connected even if the A D converter is not used More information on the analog power supply is in Section 3 1 1 2 Other Needed Connections Several other connections are needed to configure the 8X9X In normal operation the following pins should be connected to the indicated power supply Power Supply to allow internal execution Vss to force external execution Although the EA pin has an internal pulldown it is best to tie this pin to the desired level This will prevent induced noise from disturbing the system Raising EA to 12 75 volts will place an 8X9X in a special operat ing mode designed for programming and program memory verification see Section 10 1 3 Oscillator Information The 8 9 requires a clock source to operate This clock is provided to the chip through the XTALI in put The frequency of operation is from 6 MHz to 12 MHz The on chip circuitry for the 8X9X oscillator is a single stage linear inverter as shown in Figure 1 It is intended for use as a crystal controlled positive reactance oscil lator with external connections as shown in Figure 2 In this application the cryst
168. of these outputs produce TTL levels FILTER PASSIVE OR POWER xti AMP LOG OUTPUT OPTIONAL 270246 21 Figure 18 D A Buffer Block Diagram 8X9X HARDWARE DESIGN INFORMATION 1 2 VQ3001P 270246 22 This resistor limits rise time to reduce spikes amp high frequency noise 8 and C are chosen for best HIGH IMPEDANCE AMP ANALOG OUTPUT 270246 23 filtering at the user s frequency Figure 19 Buffer Circuits for D A 5 0 1 0 TIMINGS The I O pins on the 8X9X are sampled and changed at specific times within an instruction cycle The changes occur relative to the internal phases shown in Figure 4 Note that the delay from to the internal clocks range from about 30 ns to 100 ns over process and temperature Signals generated by internal phases are further delayed by 5 ns to 15 ns The timings shown in this section are idealized no propagation delay factors have been taken into account Designing a system that depends on an I O pin to change within a window of less than 50 ns using the information in this section is not recommended 5 1 HSO Outputs Changes in the HSO lines are synchronized to Timer 1 All of the external HSO lines due to change at a certain value of a timer will change just pior to the increment ing of Timer 1 This corresponds to an internal change 2 21 during Phase B every eight state times From an exter nal perspective the HSO pin should change just prior to the risi
169. ogrammer can then issue a data verify com mand after the data program command When a verify command is seen by the slaves each will drive one pin of Port 3 or 4 with a 1 if the programming verified correctly or a 0 if programming failed The SID of each slave determines which Port 3 4 bit it is assigned An 879X in the Auto Programming Mode could be the master programmer if 15 or fewer slaves need to be programmed see Gang Programming with the Auto Programming Mode 10 5 3 SLAVE PROGRAMMING MODE AND THE CCB PCCB Devices in the Slave Programmng Mode use Ports 3 and 4 as the command data path The data bus is not used Therefore you do not need to program either the CCB or the PCCB before starting slave programming You can program the CCB during slave mode pro gramming like any other location Data programmed into the CCB takes effect upon reset If you enable ei ther the READ or WRITE lock bits in the CCB and do not reset the device slave programming will continue If you enable either the READ or WRITE lock bits and do reset the device the device will no longer pro gram or verify You should program the READ and WRITE lock bits using slave programming when the array is fully programmed and verified 10 6 Run Time Programming Using Run Time programming the 879X can program itself under software control One byte or word can be programmed instead of the whole array The only addi tional requirements are that you apply a p
170. ogramming RULE 5 The PMODE and SID pins must be in their desired state before RESET rises RULE 6 All voltages must be within tolerance and the oscillator stable before RESET rises RULE 7 The supplies to Vpp EA and RESET must be well regulated and free of glitches and spikes To adhere to these rules you can use the following pow er up and power down sequences POWER UP RESET 0 EA 5V CLOCK on if using an external clock instead of the internal oscillator PALE PROG PORT3 4 SID and PMODE valid EA 12 75V Vpp 12 75 3 WAIT wait for supplies and clock to settle RESET 5V WAIT Tshil see data sheet BEGIN inte 8X9X HARDWARE DESIGN INFORMATION POWER DOWN NOTES 1 logical 2 4V minimum RESET 0V Hd 28 2 The same power supply can used for EA and Vpp 5V Vpp However the EA pin must be powered up be fore Vpp is powered up Also EA should be protect EA 5v ed from noise to prevent damage to EA 3 Exceeding the maximum limit on Vpp for any PALE PROG SID PMODE PORT3 4 amount of time could damage the device permanent OV ly The Vpp source must be well regulated and free __ of glitches and spikes Vpp EA CLOCK OFF 10 2 Reserved Locations Fill all Intel Reserved locations except address 2019H when mapped internally or externally with OFFH to ensure compatibility with f
171. om the data Figure 36 is a block diagram of a gang programming system using one 879XBH in the Auto Programming Mode The Slave Programming Mode is described in the next sec tion 270246 35 Figure 35 The Auto Programming Mode 2 36 intel The master 879X reads a word from the external mem ory controlled by ALE RD and WR It then drives Ports 3 and 4 with a Data Program command using the appropriate address and alerts the slaves with a falling edge on SALE Next the data to be programmed is driven onto Ports 3 and 4 and slave programming be gins with a falling edge on SPROG At the same time the master begins to program its own EPROM location with the data read in Intel s Modified Quick Pulse Programming Algorithm is used with Data Verify ON ACTIVE SALE SPROG RD 50 0 0 7 P0 6 P0 5 P0 4 8797BH NMI BUSWIDTH ANGND V XTAL1 XTAL2 NOTES 8X9X HARDWARE DESIGN INFORMATION commands being given to the slaves after each pro gramming pulse When programming is complete PACT goes high and Ports 3 and 4 are driven with ail 1s if all devices pro grammed correctly Individual bits of Port 3 and 4 will be driven to O if the slave with that bit number as an SID did not program correctly The 879X used as the master assigns itself an SID of 0 HSI_SID 1 SLAVE 87978H PORT 3 PORT 4 2764 2 12 75 5 0 Voc 0 PA
172. on pullup While the depletion mode pullup is the only device on the pin may be used as an input with a leakage of around 100 microamps from 0 45 volts to It is ideal for use with TTL or CMOS chips and may even be used directly with switches However if the switch option is used certain precautions should be taken It is important to note that any time the pin is read the value returned will be the value on the pin not the value placed in the control register This could cause logical operations made directly on these pins to inda vertently write a 0 to pins being used as inputs In order to perform logical operations on a port where a quasi bidirectional pin is an input it is necessary to guarantee that the bit associated with the input pin is always a one when writing to the port 2 2 Quasi Bidirectional Hardware Connections When using the quasi bidirectional ports as inputs tied to switches series resistors may be needed if the ports will be written to internally after the device is initial ized The amount of current sourced to ground from each pin is tyically 20 mA or more Therefore if all 8 pins are tied to ground 160 mA will be sourced This is equivalent to instantaneously doubling the power used by the chip and may cause noise in some applications This potential problem can be solved in hardware or software In software never write a zero to a pin being used as an input In hardware a resistor in seri
173. onfig uration Register CCR Four of the bits in the register specify the bus control mode and ready control mode Two bits also govern the level of ROM EPROM pro tection and one bit is NANDed with the BUSWIDTH pin every bus cycle to determine the bus size The CCR bit map is shown in Figure 10 The functions associated with each bit are described in this section 7 e s 4 3 2 1 o CONFIGURATION REGISTER RESERVED Set to 1 for compatibility with future parts BUS WIDTH SELECT 16 BIT BUS 8 BUS WRITE STROBE MODE SELECT WR AND WRL AND ADDRESS VALID STROBE SELECT ALE ADV IRCO INTERNAL READY CONTROL MODE Figure 10 Chip Configuration Register IRC1 Loco PROGRAM LOCK MODE 270250 8 The CCR is loaded on reset with the Chip Configura tion Byte located at address 2018H The CCR register is a non memory mapped location that can only be written to during the reset sequence once it is loaded it cannot be changed until the next reset occurs The 8X9X will correctly read this location in every bus mode If the EA pin is set to a logical 0 the access to 2018H comes from external memory If EA is a logical 1 the access comes from internal ROM EPROM If EA is T 12 75V the CCR is loaded with a byte from a sepa rate non memory mapped location called PCCB Pro gramming CCB The Programming mode is described in Section 10 of the Hardware Design ch
174. ons Interrupt service routines must share some data with other routines Whenever the programmer is coding those sections of code which access these shared pieces of data great care must be taken to ensure that the integrity of the data is maintained Consider clearing a bit in the interrupt pending register as part of a non in terrupt routine LDB AL INT PENDING ANDB AL bit_mask STB AL INT_PENDING This code works if no other routines are operating con currently but will cause occasional but serious prob lems if used in a concurrent environment All pro grams which make use of interrupts must be considered to be part of a concurrent environment To demon strate this problem assume that the INT PENDING register contains 00001111B and bit 3 HSO event in terrupt pending is to be reset The code does work for this data pattern but what happens if an HSI interrupt occurs somewhere between the LDB and the STB in structions Before the LDB instruction INT PEND ING contains 00001111B and after the LDB instruc tion so does AL If the HSI interrupt service routine executes at this point then INT PENDING will change to 00001011 The ANDB changes AL to 00000111B and the STB changes INT PENDING to 00000111B It should be 00000011B This code se quence has manged to generate a false HSI interrupt The same basic process can generate an amazing assort ment of problems and headaches These problems can be avoided by assuring mutual
175. ontains a 4 byte queue to help speed execution This queue is transparent to the RALU and to the user unless wait states are forced during external bus cycles The instruction execution times shown in Section 14 8 show the normal execution times with no wait states added and the 16 bit bus selected Reloading the slave PC and fetching the first byte of the new instruction stream takes 4 state times This is reflected in the jump taken not taken times shown in the table 2 8 System Bus There are several operating modes on the 8X9X The standard bus mode uses a 16 bit multiplexed address data bus Other bus modes include an 8 bit mode and a mode in which the bus size can dynamically be switched between 8 bits and 16 bits In addition there are several options available on the type of control sig nals used by the bus In the standard mode external memory is addressed through lines ADO through AD15 which form a 16 bit multiplexed address data data bus These lines share pins with I O Ports 3 and 4 The falling edge of the Address Latch Enable ALE line is used to provide a clock to a transparent latch 7418373 in order to de ma f V AT CLKOUT PHASE B 7A Lu ea ff ADORESS DATA DATA IN ADRESS DATAOUT Figure 9 External Memory Timings 270250 7 CLKOUT ONE WAIT STATE CYCLE MCS 96 8X9X
176. ote that the N flag will be set to the algebraically correct state even if the calculation overflows V The V overflow flag is set to indicate that the oper ation generated a result which is outside the range that can be expressed in the destination data type For the SHL SHLB and SHLL instructions the V flag will be set if the most significant bit of the operand changes at any time during the shift VT The VT oVerflow Trap flag is set whenever the V flag is set but can only be cleared by an instruction which explicitly operates on it such as the CLRVT or JVT instructions The operation of the VT flag allows for the testing for a possible overflow condition at the end of a sequence of related arithmetic operations This is normally more efficient than testing the V flag after each instruction 1 21 MCS 96 8X9X ARCHITECTURAL OVERVIEW C The C Carry flag is set to indicate the state of the arithmetic carry from the most significant bit of the ALU for an arithmetic operation or the state of the last bit shifted out of the operand for a shift Arithmetic Borrow after a subtract operation is the complement of the C flag i e if the operation generated a borrow then 0 ST The ST STicky bit flag is set to indicate that dur ing a right shift a 1 has been shifted first into the C flag and then been shifted out The ST flag is undefined after a multiply operation The ST flag can be used along with the C flag to control
177. plication Note AP 125 Design ing Microcontroller Systems for Noisy Environments 9 0 PACKAGING The MCS 96 family of products is offered in many ver sions They are available in 48 pin or 68 pin packages with or without on chip ROM EPROM and with or without an A D converter A summary of the available options is shown in Figure 31 The 48 pin versions are available in ceramic and plastic 48 pin Dual In Line package DIP The ceramic ver sions have order numbers with the prefix C The plastic versions have the prefix The 68 pin versions are available in a ceramic pin grid array PGA a plastic leaded chip carrier PLCC and a Type B leadless chip carrier LCC PGA devices have part numbers with the prefix PLCC devices have the prefix LCC devices have the prefix SHRINK DIP is offered in 64 pin packages with a package designator of U intel 8X9X HARDWARE DESIGN INFORMATION 270246 33 Figure 29 1 0 Port Reconstruction User Bm essere sem ere ao pee se 8397JF 8397JF E 8097JF 8097JF 8098 een EX EOS 30 HMOS 5 96 Packaging 48 Pin devices have four Analog Input pins 68 Pin devices have all 48 and 64 pin features plus the following For ROM OTP EPROM devices 8X9XBH and 8X98 8 Kbytes Dynamic Buswidth sizing 8 or 16 bit bus 8X9XJF 16 Kbytes Dedicated System Clock Output CLKOUT 64 devices have all 48 Pin device features plus the fol
178. plied the power down RAM will not function properly even if Voc is applied To place the 8X9X into a power down mode the RESET pin is pulled low Two state times later the device will be in reset This is necessary to prevent the device from writing into RAM as the power goes down The power may now be removed from the pin the Vpp pin must remain within specifications The 8X9X can remain in this state for any amount of time and the 16 RAM bytes will retain their values To bring the 8X9X out of power down RESET is held low while Vcc is applied Two state times after the oscillator has stabilized the RESET pin can be pulled high The 8X9X will begin to execute code at location 02080H 10 state times after RESET is pulled high Fig ure 7 shows a timing diagram of the power down se quence To ensure that the 2 state time minimum reset time synchronous with CLKOUT is met it is recom mended that 10 cycles be used Suggestions for actual hardware connections are given in the Hardware Design Chapter Reset is discussed in Section 13 To determine if a reset is a return from power down or a complete cold start a key can be written into pow er down RAM while the device is running This key can be checked on reset to determine which type of reset has occurred In this way the validity of the pow er down RAM can be verified The length of this key determines the probability that this procedure will work howeve
179. r as listed in Figure 20 In addition to the 8 standard interrupts there is a TRAP instruction which acts as a software generated interrupt This instruction is not currently supported by the MCS 96 Assembler and is reserved for use in Intel development systems The programmer must initialize the interrupt vector ta ble with the starting address of the appropriate inter rupt service routine It is suggested that any unused interrupts be vectored to an error handling routine The error routine should contain recovery code that will not further corrupt an already erroneous situation In a de bug environment it may be desirable to have the rou tine lock into a jump to self loop which would be easily traceable with emulation tools More sophisticated rou tines may be appropriate for production code recover ies Three registers control the operation of the interrupt system Interrupt Pending Interrupt Mask and the EXTINT 7 o FLAG RI FLAG SOFTWARE TIMER 0 SOFTWARE TIMER 1 SOFTWARE TIMER 2 SOFTWARE 3 RESET TIMER 2 START A D CONVERSION 51 0 PSW which contains a global disable bit block dia gram of the system is shown in Figure 21 The tran sition detector looks for 0 to 1 transitions on any of the sources External sources have a maximum transition speed of one edge every state time If this is exceeded the interrupt may not be detected Vector Location Location High Lo
180. r there is always a statistical chance that the RAM will power up with a replica of the key Under most circumstances the power fail indicator which is used to initiate a power down condition must come from the unfiltered unregulated section of the power supply The power supply must have sufficient storage capacity to operate the 8X9X until it has com pleted its reset operation RO AD_RESULT COMMAND MODE HSI_TIME 5 5 STATUS SBUF TX SBUF RX MASK INT PENDING WATCHDOG TIMER1 TIMER2 IOPORTO BAUD RATE IOPORT1 IOPORT2 5 SP 1050 1051 IOC1 PWM CONTROL MCS 96 8X9X ARCHITECTURAL OVERVIEW Zero Register Always reads as a zero useful for a base when indexing and as a constant for calculations and compares A D Result Hi Low Low and high order Results of the A D converter byte read only A D Command Register Controls the A D HSI Mode Register Sets the mode of the High Speed Input unit HSI Time Hi Lo Contains the time at which the High Speed Input unit was triggered word read only HSO Time Hi Lo Sets the time or count for the High Speed Output to execute the command in the Command Register word write only HSO Command Register Determines what will happen at the time loaded into the HSO Time registers HSI Status Registers Indicates which HSI pins were detected at th
181. rdware Connections intel The 8 9 RESET pin can be used to allow other chips on the board to make use of the Watchdog Timer or the RST instruction When this is done the reset hardware should be a one shot with an open collector output The reset pulse going to the other devices may have to be buffered and lengthened with a one shot since the RESET low duration is only one state If this is done it is possible that the 8X9X will be reset and start running before the other devices on the board are out of reset The software must account for this possible problem 17 4093 NOTE HARDWARE DESIGN INFORMATION A capacitor directly connected to RESET cannot be used to reset the device if the pin is to be used as an output If a large capacitor is used the pin will pull down more slowly than normal It will continue to pull down until the 8X9X is reset It could fall so slowly that it never goes below the internal switch point of the reset signal 1 to 1 5 volts a voltage which may be above the guaranteed switch point of external circuitry connected to the pin circuit example is shown in Figure 7 OTHER CIRCUITRY OPTIONAL ONE SHOT 741 5125 17 745 06 270246 8 1 The diode will provide a faster cycle time repetitive power on resets Figure 7 Multiple Chip Reset Circuit 2 7 intel 1 5 Sync Mode If RESET is brought high at the same time as or just after the rising edge of XTALi the device
182. reference voltage and analog power supply must be between 4 5V and 5 5V The A D result is calculated from the formula 1023 x input voltage ANGND VRgr ANGND It can be seen from this formula that changes in VREF or ANGND effect the output of the converter This can be advantageous if a ratiometric sensor is used since these sensors have an output that can be measured as a proportion of VREF ANGND must be tied to Vss digital ground in order for the 8X9X to operate properly This common con nection should be made as close to the chip as possible and using good bulk and high frequency by pass capaci tors to decouple power supply variations and noise from the circuit Analog design rules call for one and only one common connection between analog and digi tal returns to eliminate unwanted ground variations intel The A D converter has sample and hold The sampling window is open for 4 state times which are included in the 88 state time conversion period The exact timings of the A D converter can be found in Section 3 of the Hardware Design chapter 8 2 A D Commands Analog signals can be sampled by any one of the 8 analog input pins ACHO through ACH7 which are shared with Port 0 ACH can also be used as an exter nal interrupt if IOC1 1 is set see Sections 4 and 11 The A D Command Register at location 02H selects which channel is to be converted and whether the con version should start immediately or when the HSO
183. rious sources of interrupt to the 8096 A logical 1 in these bit positions enables the servicing of the corresponding interrupt These mask bits can be accessed as an eight bit byte INT MASK address 8 in the on board register file Bit 9 in the PSW is the global interrupt disable If this bit is cleared then all interrupts will be locked out except for the Non Maska ble Interrupt NMI Note that the various interrupts are collected in the INT PENDING register even if they are locked out Execution of the corresponding service routines will procede according to their priority when they become enabled Further information on the interrupt structure of the 8X9X can be found in Section 4 CONDITION FLAGS The remaining bits in the PSW are set as side effects of instruction execution and can be tested by the condi tional jump instructions Z The Z Zero flag is set to indicate that the operation generated a result equal to zero For the add with carry ADDC and subtract with borrow SUBC operations the Z flag is cleared if the result is non zero but is never Set These two instructions are normally used in con junction with the ADD and SUB instructions to per form multiple precision arithmetic The operation of the Z flag for these instructions leaves it indicating the proper result for the entire multiple precision calcula tion N The N Negative flag is set to indicate that the operation generated a negative result N
184. rities are shown in Figure 20 7 is highest O is lowest The interrupt generator then forces a call to the location in the indicated vector location This location would be the starting location of the Interrupt Service Routine ISR This priority selection controls the order in which pending interrupts are passed to the software via inter rupt calls The software can then implement its own priority structure by controlling the mask register INT MASK To see how this is done consider the case of a serial I O service routine which must run at a priority level which is lower than the HSI data avail able interrupt but higher than any other source The preamble and exit code for this interrupt service rou tine would look like this Serial io isr PUSHF Save the PSW Includes INT MASK LDB 5 00000100 EI Enable interrupts again 2 Service the interrupt Restore the PSW RET intel MCS 96 8X9X ARCHITECTURAL OVERVIEW Note that location 200CH in the interrupt vector table would have to be loaded with the value of the label serial_io_isr and the interrupt be enabled for this routine to execute There is an interesting chain of instruction side effects which makes this or any other 8X9X interrupt service routine execute properly a After the hardware decides to process an interrupt it generates and executes a special interrupt call in struction which pushes the current pro
185. rogramming voltage to Vpp and have the ambient temperature at 25 C Run time programming is done with EA at a TTL high internal memory enabled run time program the user writes a byte or word to the location to be programmed The 879X will continu ally program that location until another data read or data write to the EPROM occurs The user must con trol the duration of the programming pulse by imple menting the Modified Quick Pulse Programming Algo rithm see Section 10 8 in software intel Figure 39 is an example of code for programming an EPROM location while the device is executing internal ly Upon entering the PROGRAM routine the device retrieves the address and data from the STACK A software timer is set to expire after one programming pulse The 879X starts programming a location by writ ing to it The device then goes into a Jump to Self loop while the location is programmed Jump to Self is a two byte instruction which can be CALL ed from address 201AH When the software timer interrupt oc curs the device escapes from the Jump to Self loop ending the programming pulse The minimum interrupt service routine would remove the 201AH return ad dress from the STACK and return Once you start programming a location you should not perform any program fetches or pre fetches from the EPROM The fetches will be done but programming will stop Using the Jump to Self prevents this from happenin
186. rresponding code transitions of actu al characteristics taken from different channels under the same temperature voltage and frequency condi tions CHARACTERISTIC A graph of input voltage ver sus the resultant output code for an A D converter It describes the transfer function of the A D converter CODE The digital value output by the converter CODE CENTER The voltage corresponding to the midpoint between two adjacent code transitions CODE TRANSITION The point at which the con verter changes from an output code of Q to a code of Q 1 The input voltage corresponding to a code tran sition is defined to be that voltage which is equally like ly to produce either of two adjacent codes CODE WIDTH The voltage corresponding to the difference between two adjacent code transitions CROSSTALK See Off Isolation 2 19 D C INPUT LEAKAGE Leakage current to ground from an analog input pin DIFFERENTIAL NON LINEARITY The differ ence between the ideal and actual code widths of the terminal based characteristic of a converter FEEDTHROUGH Attenuation of a voltage applied on the selected channel of the A D converter after the sample window closes FULL SCALE ERROR The difference between the expected and actual input voltage corresponding to the full scale code transition IDEAL CHARACTERISTIC A characteristic with its first code transition at 0 5 LSB its last code transition at Vin V
187. s can be enabled or disabled by set ting or clearing bits in the interrupt mask register INT MASK 08H The format of this register is the same as that of the Interrupt Pending Register shown in Figure 22 1 28 MCS 96 8X9X ARCHITECTURAL OVERVIEW The INT MASK register can be read or written as byte register one in any bit position will enable the corresponding interrupt source and a zero will disable the source The hardware will save any interrupts that occur by setting bits in the pending register even if the interrupt mask bit is cleared The INT MASK regis ter also can be accessed as the lower eight bits of the PSW so the PUSHF and POPF instructions save and restore the INT MASK register as well as the global interrupt lockout and the arithmetic flags GLOBAL DISABLE The processing of all interrupts can be disabled by clearing the I bit in the PSW Setting the I bit will enable interrupts that have mask register bits which are set The I bit is controlled by the EI Enable Interrupts and DI Disable Interrupts instructions Note that the I bit only controls the actual servicing of interrupts Interrupts that occur during periods of lockout will be held in the pending register and serviced on a priori tized basis when the lockout period ends 4 2 Interrupt Priorities The priority encoder looks at all of the interrupts which are both pending and enabled and selects the one with the highest priority The prio
188. s left unconnected it will rise to Vcc See Section 2 7 Input for memory select External Access EA equal to a TTL high causes memory _ accesses to locations 2000H through 3FFFH to be directed to on chip ROM EPROM EA equal to a TTL low causes accesses to these locations to be directed to off chip memory EA 12 5V causes execution to begin in the Programming mode on EPROM devices EA has an internal pulldown so it goes to 0 unless driven otherwise Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end ot the bus cycle ADV can be used as a chip select for 2 43 8X9X HARDWARE DESIGN INFORMATION PIN DESCRIPTIONS Continued Ports 3 and 4 Name and Function Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is activated only during external memory writes See Section 2 7 Bus High Enable or Write High output to external memory as selected by the CCR BHE 0 selects the bank of memory that is connected to the high byte of the data bus AO 0 selects the bank of memory that is connected to the low byte of the data bus Thus accesses to a 16 bit wide memory can be to the low byte only A0 0
189. s with the timers This defines the time resolution of the HSO to be 8 state times 2 0 microseconds at an oscillator frequency of 12 MHz HS Status Register HSI_Status LOCATION 06H 7 2 HSI 0 STATUS HSi 1 STATUS 51 2 STATUS 51 3 STATUS 270250 26 Where for each 2 bit status field the lower bit indicates whether or not an event has occurred on this pin at the time in HSt_TIME and the upper bit indicates the cur rent status of the pin Figure 27 HSi Status Register Diagram Each CAM register is 23 bits wide Sixteen bits specify the time at which the action is to be carried out and 7 bits specify both the nature of the action and whether Timer 1 or Timer 2 is the reference The format of the 8 STATE TIME cun EVENT TIMER 1 COUNTER EQUAL OMPARATOR 15 TIMER 2 INPUT TIMER 2 RESET HIGH SPEED OUTPUT CONTROL 6 OUTPUT PINS 4 SOFTWARE TIMERS INITIATE A D CONVERSION RESET TIMER 2 270250 27 Figure 28 High Speed Output Unit 1 34 intel command to the HSO unit is shown in Figure 29 Note that bit 5 is ignored for command channels 8 through OFH To enter a command into the CAM file write the 7 bit Command Tag into location 0006H followed by the time at which the action is to be carried out into word address 0004H The typical code would be LDB HSO_COMMAND what_to_do ADD HSO_TIME TIMER1 when_to_do_it Writing the time value loads the HSO Hol
190. sabling the Watchdog 1 46 13 0 RESET 1 46 13 1 Reset Signal 1 46 13 2 Reset Status 1 47 13 3 Reset Sync Mode 1 47 intel This overview is written about the 8X9XBH 8X9XJF and 8X98 devices These devices are generically re ferred to as the 8X9X information in this overview refers to the 8X9XBH the 8X9XJF and the 8X98 un less otherwise noted The 8X9X can be separated into several sections for the purpose of describing its operation There is a 16 bit CPU a programmable High Speed I O Unit an analog to digital converter a serial port and a Pulse Width Modulated PWM output for digital to analog conver sion In addition to these functional units there are some sections which support overall operation of the chip such as the clock generator The CPU and the programmable I O make the 8X9X very different from any other microcontroller Let us first examine the CPU MCS 96 8X9X ARCHITECTURAL OVERVIEW 1 0 CPU OPERATION The major components of the CPU on the 8X9X are the Register File and the RALU Communication with the outside world is done through either the Special Function Registers SFRs or the Memory Controller The RALU Register Arithmetic Logic Unit does not use an accumulator it operates directly on the 256 byte register space made up of the Register File and the SFRs Efficient I O operations are possible by dire
191. slave PC is loaded with a new value and processing continues Data fetches from memory are also done through the memory controller but the slave PC is bypassed for this operation 1 2 CPU Register File The Register File contains 232 bytes of RAM which be accessed as bytes words or doubie words Since each of these locations can be used by the RALU there are essentially 232 accumulators The first word in MCS 96 8X9X ARCHITECTURAL OVERVIEW the Register File is reserved for use as the stack pointer so it can not be used for data when stack manipulations are taking place Addresses for accessing the Register File and SFRs are temporarily stored in two 8 bit ad dress registers by the CPU hardware 1 3 RALU Control Instructions to the RALU are taken from the A Bus and stored temporarily in the instruction register The Control Unit decodes the instructions and generates the correct sequence of signals to have the RALU perform the desired function Figure 1 shows the instruction register and the control unit 1 4 RALU Most calculations performed by the 8X9X take place in the RALU The RALU shown in Figure 2 contains a 17 bit ALU the Program Status Word PSW the Pro gram Counter PC a loop counter and three tempo rary registers All of the registers are 16 bits or 17 bits 16 sign extension wide Some of the regis ters have the ability to perform simple operations to off load the ALU 270250 2
192. specifications The major timing specifications are described in Figure 23 7 3 READY Line Usage When the processor has to address a memory location that cannot respond within the standard specifications it is necessary to use the READY line to generate wait states When the READY line is held low the proces sor waits in a loop for the line to come high or until the CLOCKOUT 3 4 ALE ADV Tuyv TAVLL Tetyx ADDR OUT TRLAZ WR WRL WRH apprRouT DATA OUT gt BHE INST EM NOTES 1 8 bit bus only 2 8 bit or 16 bit bus and write strobe mode selected 3 When ADV selected 4 8 bit or 16 bit bus and no write strobe mode selected 8X9X HARDWARE DESIGN INFORMATION number of inserted wait states is equal to the limit set in the Chip Configuration Register see Section 2 of the MCS 96 Architecture chapter There is a maximum time that the READY line can be held low without risking a processor malfunction due to dynamic nodes that have not been refreshed during the wait states This time is shown as TYLYH in the data sheet In most cases the READY line is brought low after the address is decoded and it is determined that a wait state is needed It is very likely that some addresses such as those addressing memory mapped peripherals would need wait states and others would not The READY line must be stable within the TLLYV spec
193. t damage 11 0 QUICK REFERENCE 11 1 Pin Description On the 48 pin devices the following pins are not bonded out Porti PortO Analog In bits 0 3 T2CLK P2 3 T2RST P2 4 P2 6 P2 7 CLKOUT INST NMI BUSWIDTH S DIP packages do not have INST CLKOUT BUSWIDTH or NMI 2 42 intel 8X9X HARDWARE DESIGN INFORMATION PIN DESCRIPTIONS Name and Function Main supply voltage 5 Vss Digital circuit ground OV Two pins RAM standby supply voltage 5V This voltage must be present during normal operation In a Power Down condition i e Vcc drops to zero if RESET is activated before Vcc drops below spec and Vpp continues to be held within spec the top 16 bytes in the Register File will retain their contents RESET must be held low during the Power Down and should not be brought high until Vcc is within spec and the oscillator has stabilized See Section 2 3 VREF Reference voltage for the A D converter 5V Vngr is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 See Section 8 ANGND Reference ground for the A D converter Should be held at nominally the same potential as Vss See Section 8 Vpp Programming voltage for the EPROM devices It should be 12 75V when programming and will float to 5V otherwise The pin should not be above Vcc ROM or CPU devices This pin must float in the application circuit on EPROM devices EIE
194. t voltage of 0 5 LSB 2048 X 2 pF An external capacitor does not compensate for the voltage drop across the source re sistance but charges the sample capacitor fully during the sample time inte Placing an external capacitor on each analog input wili also reduce the sensitivity to noise as the capacitor combines with series resistance in the external circuit to form a low pass filter In practice one should include a small series resistance prior to the external capacitor on the analog input pin and choose the largest capacitor value practical given the frequency of the signal being converted This provides a low pass filter on the input while the resistor will also limit input current during over voltage conditions Figure 14 shows a simple analog interface circuit based upon the discussion above The circuit in the figure also provides limited protection against over voltage condi tions on the analog input Should the input voltage in appropriately drop significantly below ground diode D2 will forward bias at about 0 8 VDC Since the speci fication of the pin has an absolute maximum low volt age of 0 3V this wiil leave about 0 5V across the 2700 transistor or about 2 mA of current This should limit the current to a safe amount However before any circuit is used in an actual application it should be thor oughly analyzed for applicability to the specific problem at hand FROM USER CIRCUIT INPUT PIN 270246 15
195. tain valid data for programming into slave 879XBHs that may be attached to the master ADDRESS COMMAND DATA BUS Used by devices in the Auto Programming Mode to pass command addresses and data to slaves Also used in the Auto Programming Mode as a regular system bus to access external memory Each line should be pulled up to VCC through a resistor Also used as PVAL see above SLAVE ID NUMBER Used to assign a pin of Port 3 or 4 to each slave to Programming 1 0 1 2 3 pass programming verification acknowledgement For example if gang Mode Auto PCCB Programming Mode P2 0 PALE 2 1 programming in the Slave Programming Mode the slave with SID 0001 will use Port 3 1 to signal correct or incorrect program verification PROGRAMMING ALE INPUT Accepted by an 879X that is in the Slave Programming Mode Indicates that Ports 3 and 4 contain a command address PROGRAMMING PULSE Accepted by 879X that is in the Slave Programming Mode Used to indicate that Ports 3 and 4 contain the data to be programmed A falling edge on PROG signifies data valid and starts the programming cycle A rising edge on PROG will halt programming in the slaves PROGRAM VERIFIED A signal output after a programming operation by devices in the Slave Programming Mode This signal is on Port 2 0 and is asserted as a logic 1 if the bytes program correctly PROGRAMMING DURATION OVERFLOWED A signal output by devices in the Slave Programmin
196. that slow devices can insert into the bus cycle When the READY pin is pulled low wait states will be inserted into the bus cycle until the READY pin goes high or the number of wait states equals the number specified by CCR bits 4 and 5 whichever comes first Table 1 shows the number of wait states that can be selected Internal Ready control can be disabled by loading 11 into bits 4 and 5 of the CCR Table 1 Internal Ready Control IRC1 IRCO Description Limit to 1 Wait State Limit to 2 Wait States Limit to 3 Wait States Disable Internal Ready Control This feature provides for simple ready control For ex ample every slow memory chip select line could be ORed together and be connected to the READY pin with CCR bits 4 and 5 programmed to give the desired number of wait states to the slow devices ROM EPROM LOCK Four modes of program memory lock are available on the 8X9X devices CCR bits 6 and 7 LOCO LOCI select whether internal program memory can be read or written in EPROM devices by a program executing from external memory The modes are shown in Table 2 Internal ROM EPROM addresses 2020H through 3FFFH on the 8X9XBH and the 8X98 and addresses 2020H through SFFFH on the 8X9XJF are protected from reads 2000H through 3FFFH on the 8X9XBH and the 8X98 and 2000H through 5FFFH on the 8X9XJF are protected from writes as set by the CCR Table 2 Program Lock Modes LOC1 LOCO Protection Read and Write Protected
197. tput of the oscillator inverter CLKOUT t Output of the internal clock generator The frequency of CLKOUT is 14 the oscillator frequency It has a 33 duty cycle Reset input to the chip Input low for a minimum 10 XTAL1 cycles to reset the chip The subsequent low to high transition re synchronizes CLKOUT and commences a 10 state time RESET sequence RESET Input for bus width selection If CCR bit 1 is a one this pin selects the bus width for the bus cycle in progress If BUSWIDTH is a 1 16 bit bus cycle occurs If BUSWIDTH is a 0 8 bit cycle occurs If CCR bit 1 is a 0 the bus is always 8 bit bus If this pin is left BUSWIDTH t unconnected it will rise NMI T positive transition causes a vector to external memory location 0000H INST t Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle Input for memory select External Access equal to a TTL high causes memory accesses to locations 2000H through 3FFFH to be directed to on chip ROM EPROM EA equal to a TTL low causes accesses to these locations to be directed to off chip memory EA 12 75V causes execution to begin in the Programming Mode Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a signal to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cy
198. ts plifies the programming task and should be used wher ever possible Direct Addressing The assembly language will choose between register direct addressing and long indexed with the ZERO register depending on where the oper 3 3 Program Status Word and is in memory The user can simply refer to an oper and by its symbolic name if the operand is in the regis The program status word PSW is a collection of Bool ter file a register direct reference will be used if the ean flags which retain information concerning the state operand is elsewhere in memory a long indexed refer of the user s program The format of the PSW is shown ence will be generated in Figure 16 The information in the PSW can be bro ken down into two basic categories interrupt control Indexed Addressing The assembly language will and condition flags The PSW can be saved in the sys choose between short and long indexing depending on tem stack with a single operation PUSHF and re the value of the index expression If the value can be stored in a like manner POPF expressed in eight bits then short indexing will be used if it cannot be expressed in eight bits then long indexing will be used o 11 57 ___ gt Figure 16 PSW Register 1 20 INTERRUPT FLAGS The lower eight bits of the PSW are used to individual ly mask the va
199. ture in multiprocessor systems is described below When the master processor wants to transmit a block of data to one of several slaves it first sends out an ad dress frame which identifies the target slave An ad dress frame will differ from a data frame in that the 9th data bit is 1 in an address frame and in a data frame Slaves in Mode 2 will not be interrupted by a data frame An address frame however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave switches to Mode 3 to receive the coming data frames while the slaves that were not addressed stay in Mode 2 and go on about their business 10 0 1 0 PORTS There are five 8 bit I O ports on the 8096 Some of these ports are input only some are output only some are bidirectional and some have alternate functions In addition to these ports the HSI O unit can be used to 1 42 MCS 96 8X9X ARCHITECTURAL OVERVIEW provide extra I O lines if the timer related features of these lines are not needed Input ports connect to the internal bus through an in put buffer Output ports connect through an output buffer to an internal register that hold the bits to be output Bidirectional ports consist of an internal regis ter an input buffer and an output buffer Port 0 is an input port which is also used as the analog input for the A to D converter Port 1 is a quasi bidi rectional port Port 2 conta
200. type only for shifts and as the dividend in a 32 by 16 divide and the product of a 16 by 16 multiply LONG INTEGERS can also be normalized For these operations a LONG INTEGER variable must reside in the onboard register file of the 8X9X and be aligned at an address which is evenly divisible by 4 A LONG IN TEGER is addressed by the address of its least signifi cant byte LONG INTEGER operations which are not directly supported can be easily implemented with two INTE GER operations For consistency with Intel provided software the user should adopt the conventions for ad dressing LONG operands which are discussed in Sec tion 3 5 modes will be described as they are seen through the assembly language The six basic address modes which will be described are termed register direct indirect in direct with auto increment immediate short indexed and long indexed Several other useful addressing oper ations can be achieved by combining these basic ad dressing modes with specific registers such as the ZERO register or the stack pointer alignment rules for the operand type Depending on the instruction up to three registers can take part in the calculation AX BX CX MUL AX BX INCB CL CL zCL41 INDIRECT REFERENCES The indirect mode is used to access an operand by plac ing its address in a WORD variable in the register file The calculated address must conform to the alignment rules for the operand
201. uct of a 16 by 16 multiply For these operations a DOUBLE WORD variable must reside in the on board register file of the 8096 and be aligned at an address which is evenly divisible by 4 A DOUBLE WORD operand is addressed by the address of its least significant byte DOUBLE WORD operations which are not directly supported can be easily implemented with two WORD operations For consistency with Intel provided soft ware the user should adopt the conventions for address ing DOUBLE WORD operands which are discussed in Section 3 5 3 2 Operand Addressing Operands are accessed within the address space of the 8X9X with one of six basic addressing modes Some of the details of how these addressing modes work are hidden by the assembly language If the programmer is to take full advantage of the architecture it is impor tant that these details be understood This section will describe the addressing modes as they are handled by the hardware At the end of this section the addressing REGISTER DIRECT REFERENCES The register direct mode is used to directly access a register from the 256 byte on board register file The register is selected by an 8 bit field within the instruc tion and register address and must conform to the Examples ADD AX BX CX LONG INTEGERS LONG INTEGERS are 32 bit signed variables which can take on the values between 2 147 483 648 and 2 147 483 647 The MCS 96 architecture provides di rect support for this data
202. uggest ed that the user conform to the conventions adopted by the PLM 96 programming language for procedure link age It is a very usable standard for both the assembly language and PLM 96 environment and it offers com patibility between these environments Another advan tage is that it allows the user access to the same floating point arithmetics library that PLM 96 uses to operate on REAL variables REGISTER UTILIZATION The MCS 96 architecture provides a 256 byte register file Some of these registers are used to control register mapped I O devices and for other special functions such as the ZERO register and the stack pointer The remaining bytes in the register file some 230 of them are available for allocation by the programmer If these registers are to be used effectively some overall strategy for their allocation must be adopted PLM 96 adopts the simple and effective strategy of allocating the eight bytes between addresses 1CH and 23H as temporary storage The starting address of this region is called PLMREG The remaining area in the register file is treated as a segment of memory which is allocated as required ADDRESSING 32 BIT OPERANDS These operands are formed from two adjacent 16 bit words in memory The least significant word of the double word is always in lower address even when the data is in the stack which means that the most sig nificant word must be pushed into the stack first A double word is addressed
203. uit is shown in Figure 3 The required voltage levels on XTALI are specified in the data sheet The signal on XTAL1 must be clean with good solid levels It is important that the minimum high and low times met to avoid having the pin in the tran sition range for long periods of time The longer the signal is in the transition region the higher the proba bility that an external noise glitch could be seen by the clock generator circuitry Noise glitches on the 8X9X internal clock lines will cause unreliable operation The clock generator provides a 3 phase clock output from the pin input Figure 4 shows the wave forms of the major internal timing signals DIVIDER CIRCUITRY 270246 3 Figure 3 External Clock Drive XTAL1 8X9X HARDWARE DESIGN INFORMATION PHASE SL m ge Figure 4 Internal Timings 1 4 Reset Information In order for the 8X9X to function properly it must be reset This is done by holding the RESET pin low for at least 10 XTAL1 cycles after the power supply is within tolerance and the oscillator has stabilized After the RESET pin is brought high a ten state reset sequence is executed During this time the Chip Con figuration Byte CCB is read from location 2018H and written to the 8X9X Chip Configuration Register CCR If the voltage on the EA pin selects the inter nal ext
204. us con tention However up to 10 ns is acceptable in sys tems Figure 23 Timing Specification Explanations 2 25 intel 8X9X HARDWARE DESIGN INFORMATION Timings the 8096 Will Provide that proper memory decoding takes place before it is output enabled Nominally 2 Tosc periods high to CLOCKOUT high Delay from the rising edge of to the resultant rising TRLRH READ low to READ high RD pulse edge on CLOCKOUT Needed in systems where the width nominally 1 Tosc period signal driving XTALI is also used as a clock for ex ternal devices Typically 50 to 100 nanoseconds TRHLH READ high to ALE ADV high Time be tween RD going inactive and next ALE ADV also TCHCH CLKOUT high to CLKOUT high The used to calculate time between RD inactive and next period of CLKOUT and the duration of one state ADDRESS valid Nominally 1 Tose period time Always 3 Tosc average but individual periods pe could vary by a few nanoseconds TRHBX READ high to INST AD 8 15 In active Minimum time that the INST and BHE lines TCHCL CLKOUT high to CLKOUT low Nomi will be valid after RD goes high Also the minimum nally 1 Tosc period time that the upper eight address lines 8 bit bus mode will remain valid after RD goes high Nomi TCLLH CLKOUT low to ALE high A help in de nally 1 Tosc riving other timings Typically plus or minus 5 ns to _ 10 ns TW
205. used to compare both signed and unsigned eight bit quantities A JH jump if higher could be used following the compare if unsigned operands were involved or a JGT jump if greater than if signed operands were involved Table 3 summarizes the operation of each of the in structions Complete descriptions of each instruction and its timings can be found in the Instruction Set chapter A summary of instruction opcodes and timing is included in the quick reference section at the end of this chapter intel MCS 96 8X9X ARCHITECTURAL OVERVIEW Table 3 Instruction Summary 4 i Fass eem ADD ADOB 2 eee ee ___ __ s 2 D D A C su amp su 2 sue suug 3 8 5 2 o e 1 ____ 1 20 0 DA o c 2 DD 2 D A __ __ 2 MU MUU 3 0 0 24 8 2 MUBAULB 2 00 14 DA ____ _ 2 MUB MUUB 3 ____ 2 ovu D DD 2 AD 2 remainder 2 2 D DD 1 AD 1 lt remainder 1 ___ 2 De 5D 2 AD 2 gt Dv __ 2 D DD t AD 1 remainder 2 D DadA ___ 3
206. uture devices Fill address 2019H with 20H PROGRAMMING MODE SELECT PROGRAMMING VOLTAGE 87978 270246 34 Figure 32 Programming Mode Pin Function 2 33 8X9X HARDWARE DESIGN INFORMATION General Auto Programming Mode Slave PMODE PO 4 5 6 7 PACT HSO 0 PVAL Ports 3 and 4 SALE P2 0 SPROG P2 5 Ports 3 and 4 PROGRAMMING MODE SELECT Determines the EPROM programming algorithm that is performed PMODE is sampled after a chip reset and should be static while the device is operating PROGRAMMING ACTIVE Used in the Auto Programming Mode Indicates when programming activity is complete PROGRAM VALID These signals indicate the success or failure of programming in the Auto Programming Mode and when using this mode for gang programming For the Auto Programming Mode this signal is asserted at Port 3 0 When using this mode for gang programming all bits of Port 3 and Port 4 are asserted to indicate programming validity of the various slaves A zero indicates successful programming on PVAL O zero on PVAL 1 through PVAL 15 indicates a fail SLAVE ALE Output signal from an 879X in the Auto Programming Mode A falling edge on SALE indicates that Ports 3 and 4 contain valid address command information for slave 879XBHs that may be attached to the master SLAVE PROGRAMMING PULSE Output from an 879X in the Auto Programming Mode A falling edge on SPROG indicates that Ports 3 and 4 con
207. ven word location for the address referenced Number of state times shown for internal external operands The opcodes for signed multiply and divide are the opcodes for the unsigned functions with an FE appended as a prefix 9 State times shown for 16 bit bus 2 52 intel 8X9X HARDWARE DESIGN INFORMATION DIRECT IMMEDIATE INDIRECT NORMAL AUTO NC SHORT LONG o a gt ul ul o o a a e a a ols eo ola SZC SZ SZ or ar o o lajo LOGICAL INSTRUCTIONS 2 61 3 4 614 s 62 3 eu 3 m2 63 4 eu 5 v2 AND 5 arts 6 42 4 712 4 5 712 6 813 anog 12 7013 4 nfs 72 en 712 73 en 5 712 anog 504 5114 s 52 712 14 53 15 712 __ 2 4 4 s 82 3 en 712 4 5 712 2 0 35 4 9113 4 92 3 712 93 4 ett s 712 2 1 3 4 85 41 5 6 3 712 87 4 5 712 2 94 3 4 95 3 4 913 en 3 712 97 4 om 5j 712 DATA TRANSFER INSTRUCTIONS ip __ 2 3 4 s 2 31 en 712 azja 5 712 2 0 3 4 3 4 en 712 4 5 712 ir __ 2 4 3
208. w Priority Byte Byte Not Applicable 7 Highest 6 Software Trap Extint Serial Port High Speed Outputs HS Data Available A D Conversion 2003H Complete Timer Overflow 2001H Figure 20 Interrupt Vector Locations INTERRUPT EXTINT Ses ie SERIAL PORT HSO_COMMAND 4 SOFTWARE TIMER r HSO COMMAND 4 ANY HSO OPERATION a eae HIGH SPEED OUTPUTS r 10 1 7 FIFO IS FULL HS DATA AVAILABLE HOLDING REGISTER LOADED o A D CONVERSION COMPLETE A D CONVERSION COMPLETE po 10C1 2 TIMER OVERFLOW TIMER2 OVERFLOW 9 TIMER OVERFLOW 1001 3 NOTE Only when initiated by the HSO unit Figure 19 All Possible 1 26 270250 20 Interrupt Sources EXTINT 7 MCS 96 8X9X ARCHITECTURAL OVERVIEW SOFTWARE TIMER SERIAL PORT TIMERS HSO HSI AO CONV OVERFLOW 6 5 4 3 2 1 0 TRANSITION DETECTOR INTERRUPT PENDING REG INTERRUPT MASK REG PRIORITY ENCOOER v GLOBAL DISABLE 2 INTERRUPT GENERATOR g CONTROL UNIT 270250 21 Figure 21 Block Diagram of Interrupt System 1 27 intel 4 1 Interrupt Control interrupt Pending Register When the hardware detects one of the eight interrupts it sets the corresponding bit in the pending interrupt register INT PENDING 09H When the interrupt vector is taken the pending bit is cleared This register the format of which is shown i
209. when tran sitions occur and the HSO causes transitions to occur based on values of either Timer 1 or Timer 2 The baud rate generator can use the T2CLK pin as input to its counter a complete listing of the functions of IOSI and IOC in Section 11 DIVIDE INPUT BY 8 CHANGE COUNTER HSI PINS HLT 5 ras irs EVERY EIGHTH POSITIVE TRANSITION DETECTOR HSI STATUS 6 0 HIGH SPEED INPUTS The High Speed Input Unit HSI can be used to rec ord the time at which an event occurs with respect to Timer 1 There are 4 lines HSLO through HSI 3 which can be used in this mode and up to a total of 8 events can be recorded HSI 2 and HSL3 are bidirec tional pins which can also be used as HSO 4 and HSO 5 The I O Control Registers and are used to determine the functions of these pins A block diagram of the HSI unit is shown in Figure 24 FIFO INTERRUPT amp CONTROL LOGIC 8x20 BIT FIFO HOLDING REGISTER 1x 20 HSI TIME 270250 23 Figure 24 High Speed Input Unit 1 32 intel 6 1 HSI Modes There are 4 possible modes of operation for each of the HSI pins The HSI mode register is used to control which pins will look for what type of events The 8 bit register is set up as shown in Figure 25 High and low levels each need to be held for at least 1 state time to ensure proper operation The maximum input speed is 1 event every 8 state ti
210. will start executing 10 state time RST instruction exactly 67 XTALI cycles later This feature can be used to syn chronize several MCS 96 devices A diagram of a typi cal connection is shown in Figure 8 It should be noted that devices that start in sync may not stay that way due to propagation delays which may cause the syn chronized devices to receive signals at slightly different times 1 6 Disabling the Watchdog Timer The Watchdog Timer will pull the RESET pin low when it overflows See Figure 9 If the pin is being externally held above the low going threshold the pull down transistor will remain on indefinitely This means that once the watchdog overflows the device must be reset or RESET must be held high indefinitely Just 8X9X CHIP RESET WATCHDOG TIMER OVERFLOW RESET INSTRUCTION OFFH 8X9X HARDWARE DESIGN INFORMATION resetting the Watchdog Timer in software will not clear the flip flop which keeps the RESET pulldown on The pulldown is capable of sinking on the order of 30 milliamps if it is held at 2 0 volts This amount of cur rent may cause some long term reliability problems due to localized chip heating For this reason devices that will be used in production should never have had the Watchdog Timer over ridden for more than a second or two Whenever the reset pin is being pulled high while the pulldown is on it should be through a resistor that will limit the voltage on RESET to 2 5 volts a
211. xpected wait states may result Nominally 1 Tosc 3 Tosc X number of wait states desired TLLYV ALE ADV low to READY low Maxi mum time after ALE ADV falls until READY must be valid If this time is exceeded the device could mal function necessitating a chip reset Nominally 2 Tosc periods TCLYX READY hold after CLOCKOUT low Minimum time that the value on the READY pin must be valid after CLOCKOUT falls The minimum hold time is always zero nanoseconds TYLYH READY low to READY high Maximum time the part can be in the not ready state If it is exceeded the 8X9X dynamic nodes which hold the current instruction may forget how to finish the in struction TAVDV ADDRESS valid to DATA valid Maxi mum time that the memory has to output valid data after the 8X9X outputs a valid address Nominally a maximum of 5 Tosc periods TAVGV ADDRESS valid to BUSWIDTH valid Maximum time after ADDRESS becomes valid until BUSWIDTH must be valid Nominally less than 2 Tose periods If a wait state is inserted READY is internally latched on the next rising edge of Phase A If a 1 is found the bus cycle resumes with the net impact being the inser tion of one wait state If a 0 is seen a second wait state is inserted The READY pin is again latched on the next rising edge of CLOCKOUT if two wait states were inserted If the chip sees a 1 the bus cycle is resumed with the result being an insertion of two wait states If anoth
212. y and the HSI holding register has data available to be read The FIFO may be read after verifying that it contains valid data Caution must be used when reading or testing bits in IOS1 as this action clears bits 0 5 including the software and hard ware timer overflow flags It is best to store the byte and then test the stored value See Section 11 Reading the HSI is done in two steps First the HSI Status register is read to obtain the current state of the HSI pins and which pins had changed at the recorded time The format of the HSI STATUS Register is shown in Figure 27 Second the HSI Time register is read Reading the Time register unloads one level of the FIFO so if the Time register is read before the Status register the event information in the Status register will be lost The HSI Status register is at location O6H and the HSI Time registers are in locations 04H and 05 If the HSI TIME register is read without the holding register being loaded the returned value will be indeter minate Under the same conditions the four bits in intel HSI_ STATUS indicating which events have occurred will also be indeterminate The four HSI_STATUS bits which indicate the current state of the pins will always return the correct value It should be noted that many of the Status register con ditions are changed by a reset see Section 13 A com plete listing of the functions of IOSO IOS1 and IOCI can be found in Section 11 7 0
213. ytes The MSB of this register selects one of two sources for the input frequency to the baud rate generator If it is a 1 the frequency on the pin is selected if not the external frequency from the T2CLK pin is used It should be noted that the maximum speed of T2CLK is one transition every 2 state times with a minimum pe riod of 16 XTAL cycles This provides the needed synchronization to the internal serial port clocks The unsigned integer represented by the lower 15 bits of the baud rate register defines number B where B has a maximum value of 32767 The baud rate for the four serial modes using either XTAL or T2CLK as the clock source is given by Using XTAL 1 Baud _ XTAL1 frequency Mode 0 Rate B 0 intel Baud _ XTAL1 frequency Others Rate 645817 Using T2CLK Baud _ T2CLK frequency Mode 0 Rate MEL MED Others Baud T2CLK frequency Rate 16 8 Note that B cannot equal 0 except when using XTAL1 in other than mode O Common baud rate values using XTAL at 12 MHz are shown below Baud Register Value Modeo Others Baud Rate The maximum baud rates are 1 5 Mbaud synchronous and 187 5 Kbaud asynchronous with 12 MHz on XTALI 9 4 Multiprocessor Communications Mode 2 and 3 are provided for multiprocessor commu nications In Mode 2 if the received 9th data bit is not 1 the serial port interrupt is not activated The way to use this fea

8X9X USER`S MANUAL

Contents

Download Pdf Manuals

Related Search

Related Contents