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Renesas Peripheral Driver Library User`s Manual (RX63N Group)

1. PDL_INTC_REG_IPR_BSC_BUSERR PDL_INTC_REG_IPR_TPUO PDL_INTC_REG_IPR_FCU_FIFERR PDL_INTC_REG_IPR_TPU1 PDL_INTC_REG_IPR_FCU_FRDY I PDL_INTC_REG_IPR_TPU2 PDL_INTC_REG_IPR_ICU_SWINT PDL_INTC_REG_IPR_TPU3 PDL_INTC_REG_IPR_CMTO_CMI PDL_INTC_REG_IPR_TPU4 PDL_INTC_REG_IPR_CMT1_CMI PDL_INTC_REG_IPR_TPUS5 PDL_INTC_REG_IPR_CMT2_CMI PDL_INTC_REG_IPR_TPU6 PDL_INTC_REG_IPR_CMT3_CMI PDL_INTC_REG_IPR_TPU7 PDL_INTC_REG_IPR_ETHER_EINT PDL_INTC_REG_IPR_TPU8 PDL_INTC_REG_IPR_USBO_DOFIFO PDL_INTC_REG_IPR_TPU9 PDL_INTC_REG_IPR_USBO_D1FIFO PDL_INTC_REG_IPR_TPU10 PDL_INTC_REG_IPR_USBO_ USBI PDL_INTC_REG_IPR_TPU11 PDL_IN
2. PDL_INTC_REG_DTCER_ICU_SWINT PDL_INTC_REG DTCER_TPU11_TGIA PDL_INTC_REG_DTCER_CMT0O_CMI PDL_INTC_REG_DTCER_TPU11_TGIB PDL_INTC_REG_DTCER_CMT1_CMI PDL_INTC_REG_DTCER_MTUO TGIA PDL_INTC_REG_DTCER_CMT2_CMI PDL_INTC_REG_DTCER_MTUO_TGIB PDL_INTC_REG_DTCER_CMT3_CMI PDL_INTC_REG_DTCER_MTUO_TGIC PDL_INTC_REG_DTCER_USBO_DOFIFO PDL_INTC_REG_DTCER_MTUO_TGID PDL_INTC_REG_DTCER_USBO_D1FIFO PDL_INTC_REG_DTCER_MTU1_TGIA PDL_INTC_REG_DTCER_USB1_DOFIFO PDL_INTC_REG_DTCER_MTU1_TGIB PDL_INTC_REG_DTCER_USB1_D1FIFO PDL_INTC_REG_DTCER_MTU2_ TGIA PDL_INTC_REG_DTCER_SPI0_SPRI PDL_INTC_REG_DTCER_MTU2_TGIB PDL_INTC_REG_DTCER_SPI0_SPTI PDL_INTC_REG_DTCER_MTU3_TGIA PDL_INTC_REG DTCER_SPI1_SPRI PDL_INTC_REG_DTCER_MTU3 TGIB PDL_INTC_REG_ DTCER_SPI1_SPTI PDL_INTC_REG_DTCER_MTU3_ TGIC PDL_INTC_REG_DTCER_SPI2_SPRI PDL_INTC_REG_DTCER_MTU3_TGID PDL_INTC_REG_DTCER_SPI2_SPTI PDL_INTC_REG_DTCER_MTU4_ TGIA PDL_INTC_REG_DTCER_ICU_IRQ
3. PDL_INTC_REG _IR_BSC_BUSERR PDL_INTC_REG_IR_ICU_GROUP2 PDL_INTC_REG_IR_FCU_FIFERR PDL_INTC_REG_IR_ICU_GROUP3 PDL_INTC_REG_IR_FCU_FRDYI PDL_INTC_REG _IR_ICU_GROUP4 PDL_INTC_REG_IR_ICU_SWINT PDL_INTC_REG_IR_ICU_GROUP5 PDL_INTC_REG_IR_CMTO_CMI PDL_INTC_REG_IR_ICU_GROUP6 PDL_INTC_REG_IR_CMT1_CMI PDL_INTC_REG_IR_ICU_GROUP12 PDL_INTC_REG_IR_CMT2_CMI PDL_INTC_REG_IR_SCI12_SCIX0O PDL_INTC_REG_IR_CMT3_CMI PDL_INTC_REG_IR_SCI12_SCIX1 PDL_INTC_REG_IR_ETHER_EINT PDL_INTC_REG_IR_SCI12_SCIX2 PDL_INTC_REG_IR_USBO_DOFIFO PDL_INTC_REG_IR_SCI12_SCIX3 PDL_INTC_REG_ IR_USBO_D1FIFO PDL_INTC_REG_IR_TPUO_TGIA PDL_INTC_REG_IR_USBO_USBI PDL_INTC_REG_IR_TPUO_TGIB PDL_INTC_REG IR_USB1_DOFIFO PDL_INTC_REG_IR_TPUO_TGIC PDL_INTC_REG_ IR_USB1_D1FIFO PDL_INTC_REG_IR_TPUO_TGID PDL_INTC_REG_IR_USB1_USBI PDL_INTC_REG_IR_TPU1_TGIA PDL_INTC_REG _IR_SPIO_SPRI PDL_INTC_REG_IR_TPU1_TGIB PDL_INTC_REG _IR_SPIO_SPTI PDL_INTC_REG_IR_TPU2 TGIA PDL_INTC_REG_IR_SPIO_SPII PDL_INTC_REG_IR_TPU2_TGIB PD
4. 4 2 3 I O Port I O Port functions may operate on a complete port or on individual port pins The available definitions are listed below 1 O port definitions PDL_IO_PORT_0 Port PO PDL_IO_PORT_7 Port P5 PDL_IO_PORT_E Port PE PDL_IO_PORT_1 Port P1 PDL_IO_PORT_8 Port P8 PDL_IO_PORT_F Port PF PDL_IO_PORT_2 Port P2 PDL_IO_PORT_9 Port P9 PDL_IO_PORT_G Port PG PDL_IO_PORT_3 Port P3 PDL_IO_PORT A Port PA PDL_IO_PORT_H Port PH PDL_IO_PORT_ 4 Port P4 PDL_IO_PORT_B Port PB PDL_IO_PORT_J Port PJ PDL_IO_PORT_5 Port P5 PDL_IO_PORT_C Port PC PDL_IO_PORT_K Port PK PDL_IO_PORT_6 Port P6 PDL_IO_PORT_D Port PD PDL_IO_PORT_L Port PL Note Refer to the hardware manual for the ports which are available on the device that you have selected I O port pin definitions PDL_IO_PORT_0_0 Port pin POo PDL_IO_PORT_5_0 Port pin P5o PDL_IO_PORT_A_O Port pin PAo PDL_IO_PORT_0_1 Port pin PO PDL_IO_ PORT 5_1 Port pin P54 PDL_IO_PORT_A_1 Port pin PA PDL_IO_PORT_0_2 Port pin P02 PDL_IO_PORT_5 2 Port pin P52 PDL_IO_PORT_A 2 Port pin PA2 PDL_IO_PORT_0_3 Port pin P03 PDL_IO_PORT_5 3 Port pin P53 PDL_IO PORT_A_3_ Port pin PAs PDL_IO_PORT_0_5_ Port pin POs PDL_IO_PORT_5_4 Port pin P54 PDL_IO_PORT_A 4 Port pin PA PDL_IO_PORT_0_7 Port pin P07 PDL_IO_PORT_5_5 Port pin P55 PDL_IO_PORT_A_5 Port pin PAs
5. R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS PDL_INTC_REG_IR_MTUS5_TGIU PDL_INTC_REG_IR_SCIO_RXI PDL_INTC_REG_IR_MTU5_TGIV PDL_INTC_REG_IR_SCIO_TXI PDL_INTC_REG_IR_MTU5S_TGIW PDL_INTC_REG_IR_SCIO_TEI PDL_INTC_REG_IR_POE_OEI1 PDL_INTC_REG_IR_SCI1_RXI PDL_INTC_REG_IR_POE_OEI2 PDL_INTC_REG_IR_SCI1_TXI PDL_INTC_REG_IR_TMRO_CMIA PDL_INTC_REG_IR_SCI1_TEI PDL_INTC_REG_IR_TMRO_CMIB PDL_INTC_REG_IR_SCI2_RXI PDL_INTC_REG_IR_TMRO_OVI PDL_INTC_REG_IR_SCI2_TXI PDL_INTC_REG_IR_TMR1_CMIA PDL_INTC_REG_IR_SCI2_TEI PDL_INTC_REG_IR_TMR1_CMIB PDL_INTC_REG_IR_SCI3_RXI PDL_INTC_REG_IR_TMR1_ OVI PDL_INTC_REG_IR_SCI3_TXI PDL_INTC_REG_IR_TMR2_CMIA PDL_INTC_REG_IR_SCI3_TEl PDL_INTC_REG_IR_TMR2_CMIB PDL_INTC_REG_IR_SCI4_RXI PDL_INTC_REG_IR_TMR2_OVI PDL_INTC_REG_IR_SCI4_TXI PDL_INTC_REG_IR_TMR3_CMIA PDL_INTC_REG_IR_SCI4_ TEI PDL_INTC_REG_IR_TMR3_CMIB PDL_INTC_REG_IR_SCI5_RXI PDL_INTC_REG_IR_TMR3_OVI PDL_INTC_REG_IR_SCI5_TXI PDL_INTC_REG_IR_IICO_EEI PDL_INTC_REG_IR_SCI5_ TE PDL_INTC_REG_IR_IICO_RXI PDL_INTC_REG_IR_SCI6_RXI PDL_INTC_REG_IR_IICO_TX PDL_INTC_REG_IR_SCI6_TXI PDL_INTC_REG_IR_IICO_TEI PDL_INTC_REG_IR_SCI6_TEI PDL_INTC_REG_IR_IIC1_EEl PDL_INTC_REG_IR_SCI7_RXI PDL_INTC_REG_IR_IIC1_RXI PDL_INTC_REG_IR_SCI7_TXI PDL_INTC_REG_IR_IIC1_ TX PDL_INTC_REG_IR_SCI7_TEI PDL_INTC_REG_IR_IIC1_TEI PDL_INTC_REG_IR_SCI8_RXI PDL_INTC_REG_IR_IIC2_EEI PDL_INTC_REG
6. Valid edge or level detected on an external interrupt pin PDL_INTC_VECTOR_IRQ11 Interrupt PDL_INTC_VECTOR_IRQ12 controller PDL_INTC_VECTOR_IRQ13 PDL_INTC_VECTOR_IRQ14 PDL_INTC_VECTOR_IRQ15 PDL_INTC_VECTOR_GROUPO Group 0 event PDL_INTC_VECTOR_GROUP Group 1 event PDL_INTC_VECTOR_GROUP2 Group 2 event PDL_INTC_VECTOR_GROUP3 Group 3 event PDL_INTC_VECTOR_GROUP4 Group 4 event PDL_INTC_VECTOR_GROUP5 Group 5 event PDL_INTC_VECTOR_GROUP6 Group 6 event PDL_INTC_VECTOR_GROUP12 Group 12 event PDL_INTC_VECTOR_ADIO 10 bit ADC Conversion completed PDL_INTC_VECTOR_S12ADI0 12 bit ADC Conversion completed PDL_INTC_VECTOR SCIXO PDL_INTC_VECTOR SCIX1 PDL_INTC_VECTOR SCIX2 PDL_INTC_VECTOR SCIX3 SCI channel 12 Extended serial mode Break field Extended serial mode Control field Extended serial mode Bus collision Extended serial mode Valid edge PDL_INTC_VECTOR_TGIOA PDL_INTC_VECTOR TGIOB PDL_INTC_VECTOR TGIOC PDL_INTC_VECTOR TGIOD PDL_INTC_ VECTOR TGI1A PDL_INTC_VECTOR TGI2A PDL_INTC_VECTOR_TGI2B Timer Pulse Unit channel 0 Timer Pulse Unit PDL_INTC_ VECTOR _TGI1B channel 1 Compare match or Input capture B Timer Pulse Unit channel 2 Compare match or Input capture A Compare match or Input capture B Compare matc
7. data3 The initial and next output values for the enabled pins using the following format b7 b6 b5 b4 b3 b2 b1 bO Group Next pulse output values Initial output values 0 PO3 PO2 PO1 POO PO3 PO2 PO1 POO 1 PO7 PO6 PO5 PO4 PO7 PO6 PO5 PO4 2 PO11 PO10 PO9 PO8 PO11 PO10 PO9 PO8 3 PO15 PO14 PO13 PO12 PO15 PO14 PO13 PO12 4 PO19 PO18 PO17 PO16 PO19 PO18 PO17 PO16 5 PO23 PO22 PO21 PO20 PO23 PO22 PO21 PO20 6 PO27 PO26 PO25 PO24 PO27 PO26 PO25 PO24 7 PO31 PO30 PO29 PO28 PO31 PO30 PO29 PO28 Return value True if all parameters are valid and exclusive otherwise false Category Programmable Pulse Generator Reference None R20UT1963EE0100 Rev 1 00 ae ENESAS Page 222 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Program example If more than one group must be configured use multiple calls of this function The applicable PPG unit 0 or 1 is brought out of the stop state e This function disables the alternative modes on each PO pin that is enabled include r_pdl_ppg h RPDL device specific definitions include r_pdl_definitions h void func void Configure PPG outputs PO4 and PO6 group 1 R_PPG_Create PDL_PPG_PO4_PIN_P24 PDL_PPG_PO6_PIN_P26 PDL_PPG_TRIGGER_MTU2 0x15 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 223 of 487 Jul 19 2012 RX63N Group 4
8. PDL ADC 10 PIN ANO PE2 Select PE2 for ANO PDL_ADC_10 PIN AN1 PE3 Select PES for ANT PDL ADC 10 PIN AN2 PE4 Select PE4 for AN2 PDL_ADC_10 PIN AN3 PE5 Select PES for AN3 PDL ADC 10 PIN AN4 PEG Select PEG for AN4 PDL_ADC_10_PIN_AN5 PE7 Select PE7 for AN5 PDL_ADC 10 PIN AN6 PD6 Select PD6 for ANG PDL ADC 10 PIN AN7 PD7 Select PD7 for AN7 PDL ADC 10 PIN ANEXO PEO Select PEO for ANEXO PDL ADC 10 PIN ANEX1 PE1 Select PE1 for ANEX1 SEE fate io Biy peal ae Select P13 or P17 for ADTRG True if all parameters are valid and exclusive otherwise false Program example Category 10 bit ADC Reference R_ADC_10 Create Remarks e If there are I O pins to be used call this function before calling RLADC_10_Create RPDL definitions include r_pdl_ADC_10 h RPDL device specific definitions include r_pdl_definitions h void func void Set analog channel ANO R_ADC_10_Set PDL_ADC_10_PIN_ANO_PE2 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 364 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_ADC_10 Create Synopsis Prototype Description 1 2 Configure a 10 bit ADC unit bool R_ADC_10_Create uint8_t data1 ADC unit selection uint32_t data2 ADC configuration uint32_t data3 float data4 void func uint8_t data5 Callback function Int
9. PDL_SCI_PIN_SCI6_ RXD6_P01 or PDL_SCI_PIN_SCI6_RXD6_P33 or RXD6 PDL SCI PIN SCI6 RXD6 PBO PDL_SCI_PIN_SCI6_SMISO6_P01 or PDL_SCI_PIN_SCI6_SMISO6_P33 or SMISO6 PDL_SCI_PIN_SCI6_SMISO6_PBO PDL_SCI_PIN_SCI6_SSCL6 P01 or PDL_SCI_PIN_ SCI6 SSCL6_ P33 or SSCL6 PDL_SCI_PIN SCI6 SSCL6 PBO PDL_SCI_PIN_SCI6_TXD6_ P00 or PDL_SCI_PIN SCI6_ TXD6 P32 or TXD6 PDL SCI PIN SCI6 TXD6 PB1 PDL_SCI_PIN_SCI6_SMOSI6_P00 or PDL_SCI_PIN_SCI6_SMOSI6_P32 or SCI6 SMOSI6 PDL_SCI_PIN_SCI6_SMOSI6_PB1 PDL_SCI_PIN_SCI6_SSDA6_ P00 or PDL_SCI_PIN SCI6 SSDA6_ P32 or SSDA6 PDL_SCI_PIN SCI6 SSDA6 PB1 PDL_SCI_PIN_ SCI6_ SCK6 P02 or PDL_SCI_PIN_SCI6_SCK6 P34 or SCK6 PDL_SCI_PIN SCI6 SCK6 PB3 PDL_SCI_PIN_SCI6 CTS6 PB2 or CTS6 PDL SCI PIN SCI6 CTS6 PJ3 PDL_SCI_PIN_SCI6_RTS6_PB2 or RTS6 PDL_SCI_PIN_SCI6_RTS6_PJ3 PDL_SCI_PIN_SCI6_SS6_PB2 or ss6 PDL_SCI_PIN_SCI6_SS6_PJ3 Valid when n 7 PDL _SCI_PIN SCI7_RXD7_ P92 RXD7 PDL SCI PIN SCI7 SMISO7_ P92 SMISO7 PDL_SCI_PIN SCI7_SSCL7_P92 SSCL7 PDL_SCl_PIN SCI7_TXD7_P90 TXD7 PDL _SCI_PIN SCI7_SMOSI7_P90 SCI7 SMOSI7 PDL SCI PIN SCI7 SSDA7_ P90 SSDA7 PDL_SCI_PIN SCI7_SCK7_P91 SCK7 PDL SCI PIN SCI7_CTS7 P93 CTS7 PDL _SCI_PIN SCI7_RTS7_ P93 RTS7 PDL SCI PIN SCI7 SS7 P93 SS7 Valid when n 8 PDL_SCI_PIN SCI8 RXD8 PC6 RXD8 PDL_SCI_PIN_SCI8_SMISO8_ PC6 SMISO8 PDL_SCI_ PIN SCI8 SSCL8 PC6 SSCL8 PDL SCI PIN SCI8 TXD8 PC7 TXD8 PDL_SCI_PIN_SCI8_ SM
10. Flag volatile uint8_t data_received Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 void main void Data Buffer volatile uint8_t IIC_Buffer 10 DTC needs to write dummy data to SCI TDR when reading uint8_t IIC_Dummy_value OxFF Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set Channel 2 pin options R_SCI_Set 2 PDL_SCI_PIN_SCI2_SSCL2_P12 PDL_SCI_PIN_SCI2_SSDA2_P13 Setup the SCI IIC channel R_SCI_Create CHANNEL_SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_ DELAY _SDA_20_21 9600 1 0 Configure the DTC controller R_DTC_Set R20UT1963EE0100 Rev 1 00 AS Page 443 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples o SO DL_DTC_ADDRESS_FULL 200 dtc_vector_table Set current EEPROM address ITIC_Buffer 0 EEPROM_ADDRESS Use blocking function for this DTC will be used for the data part R_SCI_IIC_Writ
11. Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create IIC_CHANNEL PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E 300 3 lt lt 16 200 Enable the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Write the data into the EEPROM write_eeprom data T EPROM Prepare the next data to write to the R_DTC_Control PDL_DTC_UPDATE SOURCE PDL _DTC_UPDATE_COUNT dtc_iicl_tx_transfer_data eeprom_data_array_2 PDL_NO_PTR ARRAY 2 SIZE PDL_NO_DATA T T Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend ITIC_CHANNEL PDL_IIC_STOP_DISABL EPROM_ADDRESS eprom_data_array_l T ca T e 1 P rd DL_NO_FUNC R20UT1963EE0100 Rev 1 00 Page 455 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Read data from the EEPROM using the DTC read_eeprom_data Prepare to read the next data R_DTC_Control PDL_DTC_UPDATE_DESTINATION PDL_DTC_UPDATE_COUNT dtc_iicl_rx_transfer_data PDL_NO_PTR amp data_storage ARRAY_1_
12. Transmit buffer empty on SCI unit n n 0 to 12 data4 The source start address data5 The destination start address data6 The number of transfers to take place For normal mode valid between 0 and 65535 0 free running mode For repeat and block mode valid between 0 and 1023 0 1024 transfers data7 The repeat or block size for each transfer For repeat and block mode valid between 0 and 1023 0 1024 units Ignored in normal mode data8 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected data9 3 The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if the extended repeat function is not required for the source address data10 The destination address extended repeat value The value can be any power of 2 from 2 to 27 Specify PDL_NO_DATA if the extended repeat function is not required for the destination address func The function to be called when a DMA transfer completes Specify PDL_NO_FUNC if not required data11 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 147 of 487 Jul 19 2012 RX
13. PDL_TPU_COUNTER Update the timer counter register TCNT PDL_TPU_TGRA Update the general register A TGRA PDL_TPU_TGRB Update the general register A TGRB PDL_TPU_TGRC Update the general register A TGRC PDL_TPU_TGRD Update the general register A TGRD data3 The counter value This will be ignored if the register is not selected data4 The general register A value This will be ignored if the register is not selected data5 The general register B value This will be ignored if the register is not selected data6 The general register C value This will be ignored if the register is not selected data7 The general register D value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Timer Pulse Unit Reference Remarks e Channels 6 to11 are not available for device packages with 100 pins R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 217 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tpu h RPDL device specific definitions include r_pdl_definitions h void func void Load the counter on channel TPU channel 0 R_TPU_Control 0 PDL_TPU_COUNTER OxFFDD R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 218 of 487 RX63N Group 4 Library Reference 5 R_TPU_Read Synopsi
14. Write data into the backup registers R_LPC_WriteBackup data_to_save R_PDL_LPC_BACKUP_AR vefer section 1 2 5 of the API manual If the sub clock oscillator will not be used use R_CGC_Control to disable the oscillation circuit R20UT1963EE0100 Rev 1 00 Page 394 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples for deep Software Standby mode the sub clock oscillator is not fitted MUST call R_CGC_Control once to disable the sub clock oscillation circuit before calling R_LPC_Control R_CGC_Control PDL_NO_DATA PDL_NO_DATA PDL_CGC_SUB_CLOCK_DISABL a Enter deep software standby mode R_LPC_Control PDL_LPC_MODE_D EP_SOFTWARE_STANDBY T i An internal reset will occur when exiting from deep software standby The program counter will not return to here while 1 void NMI_handler_lpc void nop Figure 5 8 Example of Deep Software Standby Mode R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 395 of 487 Jul 19 2012 RX63N Group 5 Usage Examples 5 7 Bus Controller 5 7 1 External bus CS area Figure 5 9 shows an example of external bus controller usage to chip select areas Peripheral driver function prototypes include r_pdl_bsc h include r_pdl_cgc h evice specific definitions RPDL devi pecific definiti include r_pdl_definitions
15. R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 158 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_EXDMAC_ Destroy Synopsis Disable the EXDMA controller Prototype bool R_EXDMAC_Destroy uint8_t data II Channel number Description Shutdown the EXDMAC module data The channel number n where n 0 to 1 Return value True if the shutdown succeeded otherwise false Category EXDMA controller Reference R_EXDMAC_Create Remarks e Ifall channels have been suspended the EXDMAC module will be shut down e Ifthe MTU is being used to trigger an EXDMA transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function Program example RPDL definitions include r_pdl_exdmac h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channel 1 R_EXDMAC_Destroy 1 i R20UT1963EE0100 Rev 1 00 ae AS Page 159 of 487 Jul 19 2012 XENES RX63N Group 4 Library Reference 4 R_EXDMAC Control Synopsis Prototype Description 1 2 Control the EXDMA controller bool R_ EXDMAC_Conitrol uint8_t data1 Channel number uint16_t data2 II Control options void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint16_t data6
16. Return value True if all parameters are valid otherwise false Category Interrupt control References R_INTC_ControlGroup Remarks gt Use R_INTC_ControlGroup to clear the flags Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t Status_flags Read the group 3 status flags R_INTC_GetStatusGroup 3 amp Status_flags R20UT1963EE0100 Rev 1 00 R AS Page 87 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 14 R_INTC Control Synopsis Control the operation of the interrupt controller Prototype bool R_INTC_Conirol uint16_t data Interrupt selection Description Modify the interrupt selection register data Select the MTU or TPU interrupt requests All selections are optional If multiple selections are required use to separate each selection PDL_INTC_SEL_MTUO or PDL_INTC_SEL_TPU6 PDL_INTC_SEL_MTU1 or PDL_INTC_SEL_TPU7 PDL_INTC_SEL_MTU2 or PDL_INTC_SEL_TPU8 PDL_INTC_SEL_MTU3 or PDL_INTC_SEL_TPUQ PDL_INTC_SEL_MTU4 or PDL_INTC_SEL_TPU10 PDL_INTC_SEL_MTUS or PDL_INTC_SEL_TPU11 MTU channel 0 or TPU channel 6 MTU channel 1 or TPU channel 7 MTU channel 2 or TPU channel 8 MTU channel 3 or TPU channel 9 MTU channel 4 or TPU channel 10 MTU channel 5 or TPU cha
17. b31 b24 b23 b16 b15 b8 b7 b0 Day of week Hours Minutes Seconds Valid from 0 to 6 0 Sunday Specify OxFF for Valid from O Valid from O Valid from automatic calculation using the values in data5 to 23 to 59 0 to 59 12 Hour Mode b31 b24 b23 b22 b16 b15 b8 b7 b0 Day of week Valid from 0 to 6 0 Sunday EM aus Minutes Seconds Specify OxFF for automatic 0 AM Valid from Valid from Valid from 1 PM 1 to 12 0 to 59 0 to 59 calculation using the values in data3 R20UT1963EE0100 Rev 1 00 ae ENESAS Page 260 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 4 4 data10 The alarm year month and day BCD format is used If not required specify PDL_NO_DATA b31 b16 b15 b8 b7 b0 Year Month Day Valid from 0 to 9999 Valid from 1 to 12 Valid from 1 to the number of days in the month func1 The function to be called when an alarm occurs Specify PDL_NO_FUNC if not required data11 The alarm interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 func2 The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data12 The periodic interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if P
18. Allow 100 ps for the main clock to stabilise R_CMT_CreateOneShot 0 PDL_NO_DATA 100E 6 PDL_NO_FUNC 0 Select the PLL R_CGC_Control R20UT1963EE0100 Rev 1 00 AS Page 474 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Use port C for the IEBus pins R_IEB_Set PDL_IEB_PIN_IERXD_PC2 PDL_IEB_PIN_IETXD_PC3 Configure IEBus channel 0 R_IEB_Create 0 PDL_IEB_MODE_1 PDL_IEB_POLARITY_HIGH 0x0345 15 Prepare data for transmission when requested R_IEB_SlaveWrite 0 uint8_t iebus_tx_data_a uint8_t strlen iebus_tx_data_a iebus_rx_data_length 0 General_status 0 Tx_status 0 Rx_status 0 while 1 Monitor channel 0 R_IEB_SlaveMonitor 0 iebus_rx_data amp iebus_rx_data_length PDL_NO_FUNC Has data been received if iebus_rx_data_length 0 received_sum 0 checksum 0 Analyse the received data for counter 0 counter lt iebus_rx_data_length counter received_sum iebus_rx_data counter checksum counter 1 Bad data if received_sum checksum while 1 Reset the receive buffer and counter for counter 0 counter lt 32 counter iebus_rx_data counter OxFF else Read the Receive status
19. e Sampling time calculation PDL_ADC 10 ADSSTR_ CALCULATE or Select whether parameter data4 is used to calculate the ADSSTR register value or PDL ADG 10 ADSSTR SPECIFY contains the value to be stored in ADSSTR Self Diagnostic PDL_ADC_10_ SELF_DIAGNOSTIC_DISABLE or Disable or enable Self diagnostic PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0 or function of Vref x 0 voltage value or PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0_5 or Vref x voltage value or PDL_ADC_10_SELF_DIAGNOSTIC_VREF_1 Vref x 1 voltage value Extended analog input PDL_ADC_10_ ANEX_DISABLE or Disable extended analog input PDL_ADC_10_INPUT_ANEX1 Select ANEX1 as the input source data3 The desired frequency of the conversion clock ADCLK in Hertz Up to four frequencies are available as a division of the peripheral clock Please see the Remarks data4 The data to be used for the sampling state register value calculations The data should be at least 02h if PDL_ADC_10_ADSSTR_SPECIFY is selected Data use Parameter type The timer period in seconds or float The value to be put in register ADSSTR uint8_t func The function to be called when the ADC conversion or scan cycle is complete Specify PDL_NO_FUNC if no callback function is required data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specif
20. T channel 0 for 10ys operation R_CMT_Create 0 PDL_CMT_PERIOD 10E 6 PDL_NO_FUNC 0 nfigure CMT channel 1 for 1kHz operation Create 1 PDL_CMT_FREQUENCY 1E3 PDL_NO_FUNC 0 nfigure CMT channel 2 using register values R_CMT_Create 2 PDL_CMT_PCLK_DIV_32 Ox55AA PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 251 of 487 RX63N Group 4 Library Reference 2 R_CMT_CreateOneShot Synopsis Prototype Description Return value Configure a CMT channel as a one shot event bool R_CMT_CreateOneShot uint8_t data1 Timer channel selection uint16_t data2 Configuration selection double data3 Period void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Control the CPU during the one shot operation PDL_CMT_CPU_ON or Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts PDL CMT_CPULOFF The CPU will re start when any valid interrupt occurs e DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENA
21. DTC event trigger control Valid for n 5 PDL_MTU2_TGRU_DTC_TRIGGER_DISABLE or TGRU compare match or input PDL_MTU2_TGRU_DTC_TRIGGER_ENABLE capture PDL_MTU2_TGRV_DTC_TRIGGER_DISABLE or TGRV compare match or input PDL_MTU2_TGRV_DTC_TRIGGER_ENABLE capture PDL_MTU2_TGRW_DTC_TRIGGER_DISABLE or TGRW compare match or input PDL_MTU2_TGRW_DTC_TRIGGER_ENABLE capture counter_operation Configure the counter operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults TCNT counter clock source selection Valid for n 0 to 4 unless stated otherwise Not effective for n 1 and 2 in Phase Counting Mode PDL_MTU2_CLK_PCLK_DIV_1 or PDL_MTU2_ CLK_PCLK_DIV_4or PDL_MTU2 CLK _PCLK_DIV_16 or PDL_MTU2_ CLK_PCLK_DIV_64 or PDL _MTU2 CLK PCLK_DIV_ 256 or PCLKB 256 Valid for n 1 3 and 4 PDL_MTU2 CLK PCLK_DIV_1024 or PCLKB 1024 Valid for n 2 3 and 4 The internal clock signal PCLKB 1 4 16 or 64 PDL_MTU2_CLK_MTCLKA or MTCLKA pin input Valid for n 0 to 4 PDL_MTU2_CLK_MTCLKB or MTCLKB pin input Valid for n 0 to 4 PDL_MTU2_CLK_MTCLKC or MTCLKC pin input Valid for n 0 or 2 PDL_MTU2_CLK_MTCLKD or MTCLKD pin input Valid for n 0 PDL MTU2 CLK CASCADE The overflow underflow signal from channel
22. PDL_IIC_STOP Issue a Stop condition e NACK generation PDL_IIC_NACK Set the Acknowledge bit to the NACK state e Pin control PDL_IIC_SDA_LOW or PDL IIC SDA HI Z PDL_IIC_SCL_LOW or PDL_IIC_SCL_HI_Z Set the SDA pin to low level or high impedance Set the SCL pin to low level or high impedance Extra clock cycle generation Generate an extra clock cycle on the SCL pin This can be used in PDL_IIC_CYCLE_SCL Master mode to try and unlock a slave device that is holding the SDA signal low Reset control PDL_IIC_RESET Carry out an internal reset of the I C module the settings are preserved Return value True if all parameters are valid exclusive and achievable otherwise false Category lC Reference R_IIC_Create Remarks e Channels 1 and 3 are not available with the 100 pin package This function will return false in this case Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Issue a Stop condition on channel 0 R_ITIC Control 0 PDL ILIC STOP i R20UT1963EE0100 Rev 1 00 R AS Page 322 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 9 R_IIC_GetStatus Synopsis Prototype Description Read the status for an I C channel bool R_IIC_GetStatus uint8_t data1 C
23. RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Terminate SCI reception on channel 0 R_SCI_Control 0 PDL_SCI_STOP_RX R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 305 of 487 RX63N Group 4 Library Reference 11 R_SCI_GetStatus Synopsis Check the status of an SCI channel Prototype bool R_SCI_ GetStatus uint8_t data1 Channel selection uint8_t data2 II Status flags uint8_t data3 Last byte received uint16_t data4 Bytes transmitted uint16_t data5 II Bytes received Description Acquires the channel status and the byte counts data1 Select channel SClin where n 0 to 12 data2 The status flags shall be stored in one of the following formats depending on the current mode Note Some bits are Not Applicable NA in all modes see descriptions Asynchronous or Synchronous modes Not IIC Mode b7 b6 b5 b4 b3 b2 b1 bO Reception error detection Overrun Framing Parity Transmit RxD pin level 0 Async Async status 0 NA to SPI mode mode only mode only 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High Smart card mode b7 b6 b5 b4 b3 b2 b1 bO Error detection RxD pin Transmit st
24. Category Reference Remarks Read from timer unit registers bool R_TMR_Readunit uint8_t data1 Unit selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location uint16_t data4 A pointer to the data storage location uint16_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The unit number n where n 0 or 1 data2 The status flags shall be stored in the format below A flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read The unit 0 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 b1 bO TMRO TMR1 0 Compare Compare 0 Compare Compare Overflow match B match A NEIG match B match A The unit 1 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 b1 bO TMR2 TMR3 0 Compare Compare 0 Compare Compare idealists match B match A Cueniow match B match A data3 Where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True Timer TMR R_TMR_CreateUnit e Ifthe status flags are read any f
25. Configure a timer TMR unit bool R_TMR_CreateUnit uint8_t data1 uint32_t data2 uint8_t data3 uint16_t data4 uint16_t data5 uint16_t data6 Unit selection Configuration selection Output control Register value Register value Register value void func1 Callback function void func2 Callback function void func3 Callback function uint8_t data7 Interrupt priority level Set up a timer TMR unit in 16 bit count mode data1 The unit number n where n 0 or 1 data2 Configure the unit If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Counter clock source selection PDL_TMR_CLK_OFF or PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or PDL_TMR_CLK EXT BOTH or The clock input is disabled The external clock signal TMCIx x 1 or 3 for n 0 or 1 is used with rising falling or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 The internal clock signal PCLKB 1 2 8 32 64 1024 or 8192 Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL TMR CLEAR CM Aor Cleared after a compare match A occurs PDL_TMR_CLEA
26. Configure the frequency measurement circuit bool R_MCK_Control uint16_tdata Reference clock selection Configure the operation of the frequency measurement circuit data Choose the reference clock settings Use to separate each selection e Reference clock selection for system 1 PDL_MCK_1_DISABLE or Allow normal MTU operation or select the PDL_MCK_1_REFERENCE_MTCLKD or MTCLKD pin PDL_MCK_1_REFERENCE_LOCO or low speed on chip oscillator PDL_MCK_1_REFERENCE_MAIN or main clock oscillator PDL_MCK_1 REFERENCE SUB CLOCK or sub clock oscillator to be monitored e Reference clock selection for system 2 PDL_MCK_2_DISABLE or Allow normal TPU operation or select the PDL_MCK_2_REFERENCE_TCLKD or TCLKD pin PDL_MCK_2_REFERENCE_LOCO or low speed on chip oscillator PDL_MCK_2_REFERENCE_MAIN or main clock oscillator PDL_MCK_2 REFERENCE SUB CLOCK or sub clock oscillator to be monitored True if all parameters are valid and exclusive otherwise false Frequency measurement circuit R_CGC_Set R_CGC_Control e The clock to be compared with the reference clock is the peripheral clock PCLKB e Ensure that the required clocks have been enabled using R_CGC_Set The PCLKB clock source is selected using R_CGC_Control e This function will temporarily enable the MTU if a reference clock is selected for system 1 and TPU if a reference clock is selected for system 2 modules if they were disable
27. Enable channel 0 R_DMAC_Control 0 r DL_DMAC_ENABLE DL_NO_PTR DL_NO_PTR DL_NO_DATA DI DI DI DI L_NO_DATA L_NO_DATA L_NO_DATA L _NO_DATA ao ao Sao Bao ao ao ao a e Enable and start channel 1 R_DMAC_Control 1 r DL_DMAC_ENABLE PDL_DMAC_START DL_NO_PTR DL_NO_PTR DL_NO_DATA DI DI DI DI L_NO_DATA L_NO_DATA L_NO_DATA L NO_DATA ao ao Sao Bao ae ao ao a e Read the status for channel 0 R_DMAC_GetStatus 0 amp StatusValue amp SourceAddr amp DestAddr amp TransferCount amp SizeCount while 1 void DMACO_transfer_end_handler void Invert the LED2 port pin R20UT1963EE0100 Rev 1 00 Page 403 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples R_IO_PORT_ PDI PDI 1 Stop channel 0 R_DMAC_Control 0 DL_DMAC_SUSPI DL_NO_PTR DL_NO_PTR DL_NO_DATA DI DI DI DI L_NO_DATA L_NO_DATA L_NO_DATA L_ NO_DAT P P P P P P P P Shutdown channel 0 R_DMAC_Destroy 0 3 Figure 5 11 Two examples of DMAC use R20UT1963EE0100 Rev 1 00 az AS Page 404 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 9 Data Transfer Controller 5 9 1 Block transfer mode Figure 5 12 shows an example of Data Transfer Controller usage with a single block transfer Peripheral driver fun
28. R_EXDMAC _ Control R_EXDMAC_ GetStatus Control the EXDMA controller Check the status of an EXDMAC channel Data Transfer Controller R DTC Set Set the Data Transfer Controller options R_DTC_Create Configure the DTC for a transfer R_DTC_Destroy Shutdown the Data Transfer Controller R_DTC_Control Control the Data Transfer Controller R_DTC_GetStatus Check the status of the Data Transfer Controller Multi function Timer pulse unit R_MTU2 Set Configure the Multi function Timer Pulse Units R_MTU2_Create Configure a MTU channel R_MTU2_Destroy Disable a Multi function Timer Pulse Unit R_MTU2_ControlChannel Control an MTU channel R_MTU2 _ ControlUnit Control a Multi function Timer Pulse Unit R_MTU2 ReadChannel Read from MTU channel registers R_MTU2_ReadUnit Read from MTU registers gt N D O BY SVINI ON BY OO DO On BY Oo Po gt A Oo Po R_POE_Set Configure the Port Output Enable module Port Output 2 R_POE_Create Configure the Port Output Enable event handling Enable 3 R_POE_Control Control the Port Output Enable module 4 R POE GetStatus Check the
29. The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Window End Position PDL_IWDT_WIN_END_0 or PDL_IWDT_WIN_END_ 25 or PDL_IWDT_WIN_END_50 or PDL_IWDT_WIN_END_75 The window end position specified as a percentage of the down counter 0 is when the down counter would underflow Hence specifying 0 is equivalent to no window end position Sleep Mode Count Stop PDL_IWDT_STOP_DISABLE or PDL_IWDT_STOP_ENABLE Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode deep software standby mode or all module clock stop mode R_MCU_OFS R_CGC_Set R_CGC_Control R_INTC_CreateExtInterrupt Return value True if all parameters are valid and exclusive otherwise false Category Independent Watchdog Timer Reference Remarks If using the Initial Setting Memory using R_MCU_OFS to enable the IWDT from reset this function will have no affect and can be omitted The IWDTCLK must be enabled using R_CGC_Set or R_CGC_Control If configuring to use a NMI handler then R_INTC_CreateExtInterrupt must be used to enable the NMI for IWDT R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 275 of 487 RX63N Group 4 Library Reference Program exam
30. Description 2 2 data6 The repeat or block size for each transfer Valid between 0 and 1023 0 1024 units Ignored in normal mode Specify PDL_NO_DATA if not required data7 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected Specify PDL_NO_DATA if not required data8 The source address extended repeat value The value can be any power of 2 from 2 to 27 Specify PDL_NO_DATA if not required data9 The destination address extended repeat value The value can be any power of 2 from 2 to 27 Specify PDL_NO_DATA if not required Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_Create Remarks The Software trigger control is valid only if the Software trigger option has been selected e This function must be called in order to start the DMAC The Suspend Enable and Start control is executed at the end of the function If a channel has completed a transfer parameters may be changed and the channel re enabled in one function call R20UT1963EE0100 Rev 1 00 2tENESAS Page 151 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h include lt string
31. Select a low power consumption mode bool R_LPC_Control uint32_t data Mode selection Transition to one of the low power modes data Control selection All selections are optional The default settings are shown in bold If multiple selections are required use to separate each selection Mode selection PDL_LPC_MODE_SLEEP or PDL_LPC_MODE_ALL_MODULE_CLOCK_STOP or PDL_LPC_MODE_SOFTWARE_STANDBY or PDL_LPC MODE DEEP SOFTWARE STANDBY Select the mode to be entered Check the Remarks section for any restrictions PDL_LPC_CHANGE_HIGH_SPEED or PDL_LPC_CHANGE_LOW_SPEED_1 or PDL_LPC_CHANGE LOW SPEED 2 e Operating power control Select the operating power control mode PDL_LPC_SLEEP_RETURN_CHANGE_DISABLE or PDL_LPC_SLEEP_RETURN_CHANGE_HOCO or PDL_LPC_SLEEP_RETURN CHANGE MAIN e Sleep mode return clock source switching Control clock source switching at cancellation of sleep mode All module clock stop cancellation modification PDL_LPC_TMR_OFF or PDL_LPC_TMR_UNIT_0 or PDL_LPC_TMR_UNIT_1 or PDL_LPC_TMR_BOTH Select whether the TMR units can be used to exit from All module clock stop mode e I O port retention cancellation PDL_LPC_IO_RELEASE Cancel the retention of I O port pin states True if all parameters are valid and exclusive otherwise false LPC R_LPC_Create R20UT1963EE0100 Rev
32. Transfer mode selection PDL_DTC_NORMAL or Normal or PDL_DTC_REPEAT or Repeat or PDL_DTC_BLOCK Block mode PDL_DTC_SOURCE or PDL_DTC_DESTINATION If Repeat or Block mode is selected select the source or destination side to be the Repeat or Block area Address direction selection PDL_DTC_SOURCE_ADDRESS FIXED or PDL DTC SOURCE ADDRESS PLUS or PDL _DTC_SOURCE_ADDRESS_MINUS After a data transfer leave the source address unchanged increment it or decrement it PDL_DTC_DESTINATION_ADDRESS_FIXED or PDL_DTC_DESTINATION_ADDRESS_PLUS or PDL_DTC_DESTINATION_ADDRESS_MINUS After a data transfer leave the destination address unchanged increment it or decrement it Transfer data size PDL_DTC_SIZE_8 or PDL_DTC_SIZE_16or PDL_DTC_SIZE_ 32 Select 1 2 or 4 bytes to be transferred in one operation e Chain transfer control PDL_DTC_CHAIN_DISABLE or Disable chain transfer operation PDL_DTC_CHAIN_ CONTINUOUS or PDL_DTC_CHAIN_0 Perform continuous chain transfers or Perform a chain transfer when the transfer counter is changed from 1 to 0 or 1 to transfer size block size e Interrupt generation PDL_DTC_IRQ_COMPLETE or PDL_DTC_IRQ_TRANSFER Select interrupt request generation when the transfer sequence completes or for every transfer e Trigger selection Name Trigger cause PDL_DTC_TRIGGER_CHAIN or Chain tra
33. RPDL device specific definitions include r_pdl_definitions h void func void Configure SPI channel 0 commands 0 and 1 R_SPI_Command 0 0 PDL_SPI_CLOCK_MODE_0 PDL_SPI_LENGTH_8 PDL_NO_DATA R_SPI_Command 0 1 PDL_SPI_CLOCK_MODE_1 PDL_SPI_LENGTH_8 PDL_NO_DATA PDL_SPI_ASSER PDL_SPI_MSB_FIRST PDL_SPI_ASSER PDL_SPI_LSB_FIRST _SSLO _SSL1 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 332 of 487 RX63N Group 4 Library Reference 5 R_SPI Transfer Synopsis Prototype Description 1 2 Transfer data over an SPI channel bool R_SPI_Transfer uint8_t data1 Channel selection uint8_t data2 DMAC DTC control uint32_t data3 Transmit data start address uint32_t data4 Receive data start address uint16_t data5 Sequence loop count void func1 Callback function uint8_t data6 Interrupt priority level void func2 Callback function uint8_t data7 Interrupt priority level In Master mode transfer the data to and or from the Slave device In Slave mode transfer the data under control of the Master device data1 Select channel SPIn where n 0 1 or 2 data2 Select the automatic data transfer options The default setting is shown in bold Specify PDL_NO_DATA to use the default e
34. Set up a DMAC channel for IIC reception This will read back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DMAC_Create 2 PDL_DMAC_NORMAL PDL_DMAC_SOURC R20UT1963EE0100 Rev 1 00 Jul 19 2012 PDL_DMAC_SIZE ESS_FIX E ADDR RENESAS Page 450 of 487 RX63N Group 5 Usage Examples PDL DMAC_ DESTINATION _ADDRESS_ PLUS PDL _DMAC_IRQ_END DL_DMAC_TRIGGER_IICO_RX P uint8_t amp RIIC0 ICDRR data_storage ARRAY_1_SIZE 2 Array size written sub address byte last byte PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA iic_rx_dmac_end_handler 7 Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create IIC_CHANNEL PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E 300 di T EPROM Write the data into the write_eeprom_data j Prepare the next data for writing to the EEPROM R_DMAC_Control 3 D D L_DMAC_SUSPEND PDL_DMAC_ENABLE L_DMAC_UPDATE_SOURCE PDL _DMAC_UPDATE_COUNT PDL_DMAC_CLEAR_DTIF eprom_data_array_2 L_NO_PTR D RRAY_2 SIZE D D L_NO_DATA L_NO_DATA DL_NO_DATA DL_NO_DATA W W Y o o i d T Write the data into the EEPROM write_eeprom_data Clear the data storage area
35. 0 0 5E 3 PDL_NO_FUNC 0 static void read_eeprom_data void bus_busy true Read data from the EEPROM using the DMAC if false R_IIC_MasterReceive IIC_CHANNEL PDL_IIC_DMAC_TRIGGER_ENABLE EPROM _ADDRESS DL_NO_PTR O L_NO_FUNC OUVONVE while 1 while bus_busy true void iic_tx_dmac_end_handler void uint32_t status_flags 0 Wait for the transmission to complete do R20UT1963EE0100 Rev 1 00 Page 452 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples R_IIC_GetStatus IIC_CHANNEL status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x0080u 0x0u Issue a Stop condition R_IIC_Control IIC_CHANNEL PDL_IIC_STOP bus_busy false void iic_rx_dmac_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DMAC_GetStatus 2 PDL_NO_PTR PDL_NO_PTR amp DestAddr PDL_NO_PTR PDL_NO_PTR Read one more byte with NACK condition and stop R_IIC_MasterReceiveLast IIC_CHANNEL uint8_t DestAddr i bus_busy false Figure 5 45 An example of writing data to and reading data from an EEPROM using two DMAC channels R20UT1963EE0100 Rev 1 00 Page 453 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 18 3 M
36. Group 0 Group 1 Unit 0 Group 2 Group 3 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 224 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example PDL_PPG_PO28_PIN_P82 or PDL_PPG_PO28_PIN_PB4 or PDL_PPG_PO28 PIN PE4 PDL_PPG_PO29_ PIN_PB5 or PDL_PPG_PO29 PIN PC5 Group 7 Unit 1 PDL_PPG_PO30_PIN_PB6 or PDL_PPG PO30 PIN PC6 PDL_PPG_PO31_PIN_PB7 or PDL_PPG_PO31_PIN_PC7 True if the unit selection is valid otherwise false Programmable Pulse Generator R_PPG_Create e If all the outputs in a unit become disabled that unit will be put into the stop state to reduce power consumption include r_pdl_ppg h RPDL device specific definitions include r_pdl_definitions h void func void Disable outputs P024 and PO26 R_PPG_Destroy PDL_PPG_PO24_ PIN_PBO PDL_PPG_PO26_PIN_PE3 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 225 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_PPG_Control Synopsis Control a PPG group Pro
37. Prototype Description Return value Category Reference Transmit data over an IEBus channel bool R_IEB_MasterSend uint8_t data1 Channel selection uint16_t data2 Communication configuration uint16_t data3 Slave address uint8_t data4 Data storage start address uint8_t data5 Data length void func Callback function Transmit data on the specified channel data1 Select channel n where n 0 only data2 Configure the channel mode and connection settings If multiple selections are required use to separate each selection The default settings are shown in bold e Communication type PDL_IEB_NORMAL or PDL_IEB_BROADCAST Select Normal one to one or Broadcast one to many e Data type and control PDL_IEB_COMMAND or PDL_IEB_DATA The slave shall interpret the data field as a command or data e Re transmission count PDL_IEB_RETRY_0or PDL_IEB_RETRY_1 or PDL_IEB_RETRY_2 or PDL_IEB_RETRY_3 or PDL_IEB_RETRY_4 or PDL_IEB_RETRY_5 or PDL_IEB_RETRY_6 or PDL_IEB RETRY 7 The number of re transmissions to be attempted if arbitration is lost data3 The slave address valid from 0000h to OFFFh data4 The start address of the data to be transmitted in the data field data5 The number of data field bytes to be transmitted Valid from 1 to 16 mode 0 or 32 mode 1 func Specify PDL_NO_FUNC or a c
38. Alarm handler Alarm priority Periodic Handler Periodic priority x W Y o w a o o g a w a Om OOO OO G OO Oo Figure 5 25 Example of using the Real time Clock with Vbatt mode R20UT1963EE0100 Rev 1 00 Page 421 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 16 Independent Watchdog Timer Figure 5 26 shows an example of Independent Watchdog timer usage At start up the underflow is checked to identify if the reset was caused by the Independent Watchdog timer The watchdog timer is then configured for a 1024 count timeout period and started Because the watchdog timer is not refreshed after two seconds this depends on the frequency of the on chip oscillator the MCU is reset and the underflow condition is detected Peripheral driver function prototypes include r_pdl_iwdt h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h void main void uintl6_t Status Enable the IWDTCLK clock Configure the IWDTLOCO settings R_CGC_Set PDL_CGC_CLK_IWDTLOCO 125E3 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDI O_DATA Read the timer status R_IWDT_Read amp Status i Has an underflow occurred if Status amp BIT_14 0x0u Handle the watchdog induced reset here Configure
39. Base clock pulse cycle count PDL_SCI_BCP_32 or PDL_SCI_BCP_64 or PDL_SCI_BCP_93 or PDL_SCI_BCP_128 or PDL_SCI_BCP_186 or PDL_SCI_BCP_256 or PDL_SCI_BCP_372 or PDL_SCI_BCP_512 The number of base clock cycles in a 1 bit data transfer period Parity selection PDL_SCI_PARITY_EVEN or PDL_SCI_ PARITY ODD Block transfer mode selection Select even or odd parity bit PDL_SCI_BLOCK_MODE_OFF or PDL_SCI_ BLOCK MODE ON Control Block transfer mode GSM mode selection PDL_SCI_GSM_MODE_OFF or PDL_SCI_GSM_MODE_ON Control GSM mode SCKn pin output control Note how the default option changes depending upon the mode In Normal Mode the default is an I O Pin In GSM Mode the default is Fixed Low Normal mode GSM mode PDL_SCIl_SCK_OUTPUT_OFF or O pin Not applicable PDL_SCI_SCK_OUTPUT_LOW or Not applicable Fixed low PDL_SCI_SCK_OUTPUT_ON or Outputs the bit clock PDL_SCI_SCK_OUTPUT_HIGH Not applicable Fixed high R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 286 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 4 4 Return value data3 The format must be either e The transfer bit rate in bits per second bps Use this format only if the on chip baud rate generator is selected the clock source and division values will be calculated using this value See the Rem
40. Select the P33 or PA3 pin for TIOCDO e Valid when n 1 PDL_TPU_PIN_A1_P56 or PDL_TPU_PIN_A1_PA4 Select the P56 or PA4 pin for TIOCA1 PDL_TPU_PIN_B1_P16 or PDL_TPU_PIN_B1_PAS Select the P16 or PAS pin for TIOCB1 e Valid when n 2 PDL_TPU_PIN_A2_P87 or PDL_TPU_PIN A2_ PA6 Select the P87 or PAG pin for TIOCA2 PDL_TPU_PIN_B2_P15 or PDL_TPU_PIN_B2_PA7 Select the P15 or PA7 pin for TIOCB2 e Valid when n 3 PDL_TPU_PIN_A3_P21 or PDL_TPU_PIN A3 PBO Select the P21 or PBO pin for TIOCA3 PDL_TPU_PIN_B3_P20 or PDL_TPU_PIN_B3 PB1 Select the P20 or PB1 pin for TIOCB3 PDL_TPU_PIN_C3_P22 or PDL_TPU_PIN_C3_PB2 PDL_TPU_PIN_D3_P23 or PDL_TPU_PIN_D3_PB3 Select the P22 or PB2 pin for TIOCC3 Select the P23 or PB3 pin for TIOCD3 e Valid when n 4 PDL_TPU_PIN_A4_P25 or PDL_TPU_PIN_A4 PB4 Select the P25 or PB4 pin for TIOCA4 PDL_TPU_PIN_B4 P24 or PDL_TPU_PIN B4 PB5 Select the P24 or PB5 pin for TIOCB4 e Valid whenn 5 PDL_TPU_PIN_A5 P13 or PDL_TPU PIN A5 PB6 Select the P13 or PB6 pin for TIOCAS PDL_TPU_PIN_B5 P14 or PDL_TPU_PIN B5 PB7 Select the P14 or PB7 pin for TIOCB5 stENESAS Page 207 of 487 RX63N Group 4 Library Reference Description 2 2 e Valid when n 6 Return value Category Refe
41. data4 Where the current destination address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data5 Where the current transfer count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data6 Where the current block size count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR Return value True if all parameters are valid and exclusive otherwise false Category Data Transfer Controller Reference R_DTC_Create Remarks e The start address of the transfer data area is the same as that declared in R_DTC_Create R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 172 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDI include RPDI L definitions L device specific definitions Yrpdl_dtie h include r_pdl_definitions h Declared in the R_DTC_Create example extern uint32_t dtc_cmt0O_transfer_data void func void uintl6_t StatusValue uint32_t SourceAddr Read the status and current source address for the CMTO transfer a R_DTC_GetStatus dtc_cmt0O_transfer_data amp StatusValue amp SourceAddr PDI PD L NO_P1 L_NO_P1 PD TR TR L_NO_P1 TR R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 173 of 487 RX63N Group 4 Library Ref
42. func The function to be called when a DMA transfer completes Specify PDL_NO_FUNC if not required data12 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false EXDMA controller None e If another peripheral will be used to trigger an EXDMAC transfer call this function before calling the Create function for the peripheral e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e If using any EXDMAC pins then RLEXDMAC_ Set must be used before calling this function e When an EXDMAC interrupt is generated the EXDMAC is disabled It must be re enabled before it can be re triggered RPDL definitions include r_pdl_exdmac h RPDL device specific definitions include r_pdl_definitions h void func void Configure EXDMAC channel 0 R_EXDMAC_Create 0 PDL_EXDMAC_NORMAL PDL_EXDMAC_SOURCE_ADDRESS_PLUS PDL_EXDMAC_DESTINATION_ADDRESS_PLUS PDL_EXDMAC_ADDRESS_MODE_DUAL PDL_EXDMAC_SIZE_32 PDL_EXDMAC_TRIGGER_FALLING PDL_NO_DATA void 0x0000AA400 void 0x0000BB00 10 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0
43. uint8_t Flags uintl6_t General_A uintl6_t General_D void func void Read the status flags and registers of channel 3 R_MTU2_ReadChannel 3 amp Flags PDL_NO_PTR amp General_A PDL_NO_PTR PDL_NO PTR amp General_D PDL_NO_PTR PDL_NO_PTR R20UT1963EE0100 Rev 1 00 AS Page 198 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 7 R_MTU2_ReadUnit Synopsis Read from MTU registers Prototype bool R_MTU2_ReadUnit uint8_t data1 Unit selection uint16_t data2 A pointer to the data storage location uint8_t data3 A pointer to the data storage location Description Read any of the timer unit s counter registers data1 The unit number n where n 0 data2 A pointer to where the Timer subcounter register TCNTS value shall be stored Specify PDL_NO_PTR if it is not required data3 Where the Timer Interrupt Skipping Counter register TITCNT value shall be stored Specify PDL_NO_PTR if it is not required Return value True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference None Remarks e None Program example RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h uintl6_t Sub count uint8_t Skip_count void func void Read the counter registers for
44. 200 2 1 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC Figure 5 19 Example of Pulse Output code Counter value Figure 5 20 Example of pulse output operation R20UT1963EE0100 Rev 1 00 AS Page 414 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 14 Compare Match Timer Figure 5 21 shows an example of Compare Match Timer usage One channel is used to generate interrupts at regular intervals Peripheral driver function prototypes include r_pdl_cmt h include r_pdl_cgc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void CMTO_handler void void CMT1l_handler void void main void uint8_t Flags uintl6_t Counter uint32_t delay_counter 0 Initialise the system clocks OTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the MAIN as the clock source R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA PDL_NO_DATA Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Configure a port pin for output R_IO_PORT_Set PDL_IO_PORT_0_5 PDL_IO_PORT_OUTPUT R_IO_ PORT Set PDL_IO_PORT_1_0 PDL_IO_PORT_OUTPUT R_IO_ PORT Write PDL_IO_ PORT R_IO_ PORT Write PDL_IO_ PORT 0_
45. 4 Library Reference 4 R_ADC_10 Control Synopsis Prototype Description Return value Category Reference Remarks Program example Start or stop an ADC unit bool R_ADC_10_Control uint16_tdata Conversion unit control Controls start stop operation of the specified ADC data To select multiple units at the same time use to separate each value e On off control compulsory option PDL_ADC_10_0_ON or PDL_ADC_10_ 0 OFF Start or stop ADC unit 0 conversion e Control the CPU during the ADC conversion The default setting is shown in bold PDL_ADC_10_CPU_ON or Allow the CPU to run normally during the conversion Stop the CPU when the conversion starts fies oa i a The CPU will re start when any valid interrupt occurs True if all parameters are valid and exclusive otherwise false 10 bit ADC None e For single or one cycle scan modes the ADC will stop automatically when the conversion is complete e The time delay between starting conversions on multiple units is minimised but has to use separate instructions This function minimises the delay between starts by using an interrupt to prevent other interrupts from occurring during the start sequence If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For true simultaneous
46. PDL_WDT_RESET_COUNTE User code is omitted here static void NMI_handler void uint1l6_t Status Read the WDT status R_WDT_Read amp Status de Has an underflow occurred Status amp BIT_14 0x0u Handle the watchdog underflow here while 1 Has a refresh error occurred Status amp BIT_15 0x0u Handle the watchdog refesh error here while 1 Figure 5 17 Example of Watchdog Timer use R20UT1963EE0100 Rev 1 00 Page 412 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 13 8 bit Timer 5 13 1 Periodic operation Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 500us and an on time of 200us Peripheral driver function prototypes include r_pdl_tmr h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void main void Initialise the system clocks NOTE The code to initialise the system clock using 4 2 1 1 is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Configure TMRO input and output pins R_TMR_Set 0 PDL_TMR_TMRO_TMOO_PB3 PDL_TMR_TMRO_TMCIO_PB1l PDL_
47. Point to start of SDRAM sdram_location_16 uint16_t 0x08000000ul Configure the bus controller for SDRAM R_BSC_Create PDL_NO_DATA PDL_BSC_A23_A16_ DISABLE PDL_BSC_SDRAM_ PINS_ENABLE R20UT1963EE0100 Rev 1 00 Page 400 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples PDL_BSC_SDRAM DOQM1 ENABLE PDL_BSC_RCV_SRRS_ENABLE PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE PDL_BSC_ERROR_TIME_OUT_ENABLE PDL_NO_FUNC x Enable the bus operation NOTE This must be done before calling R_BSC_SDRAM_CreateArea R BSC Control PDL_BSC_ENABLE Configure the SDRAM area R_BSC_SDRAM_CreateArea PDL_BSC_SDRAM_WIDTH_16 PDL_BSC_SDRAM_8_BIT_SHIFT 0x0176u RFC 375 cycles 0x04u REFW 5 cycle 0x00u ARFI 3 cycles Ox0Fu ARFC 15 times 0x00u PRC 3 cycles 0x02u CL 2 cycles 0x00u WR 1 cycles OxOlu RP 2 cycle 0x00u RCD 1 cycle 0x00u RAS 1 cycle 0x0220u SDMOD 0x220u Perform SDRAM initialization R_BSC_Control PDL_BSC_SDRAM_INITIALIZATIO Start Auto Refresh R_BSC_Control PDL_BSC_SDRAM_AUTO_REFRESH_ENABLE Enable SDRAM operation R_BSC_Control PDL_BSC_SDRAM_ENABLE Write pattern to SDRAM for index 0 index lt SD
48. R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 132 of 487 RX63N Group 4 Library Reference Description 3 3 data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid and exclusive otherwise false Category Bus Controller Reference R_BSC_Set R_BSC_CreateArea R_BSC_Control Remarks If required call R_LBSC_Set before using this function e Call this function after all calls of function R_BSC_CreateArea e After calling this function use R_BSC_Control to start the external bus operation e Multifunction Pin Control registers are modified by this function e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e Some pins are not available on some device packages This function will return false if a selected pin is not available Please check the hardware manual Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h Bus error handler void BusErrorFunc void void func void Select CS2 on pin P62 all address signals enable interrupts and register the callback function R_BSC_Create PDL
49. RX63N Group 5 Usage Examples ED1 DL_IO_PORT_XOR Figure 5 51 Example of IEBus Master use R20UT1963EE0100 Rev 1 00 az AS Page 473 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 20 2 Slave operation using polling Figure 5 52 shows how a slave unit checks for data to be received from or sent to a master unit Peripheral driver function prototypes include r_pdl_ieb h include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h include lt string h gt void main void uint8_t iebus_rx_data 32 uint8_t iebus_rx_data_length uint1l6_t General_status uint8_t Tx_status uint32_t Rx_status uintl6_t received_sum uintl6_t checksum uint8_t counter const char iebus_tx_data_a First slave message const char iebus_tx_data_b Second slave message Configure main clock operation using a 12 0 MHz clock R_CGC_Set PDL_CGC_CLK_MAIN L_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABL E fon Ovo OV OV L_NO_DAT L_NO_DAT L_NO_DAT DUUHMAAANOU J P 1 3 3 3 3 P P P Configure PLL operation The PLL will be set to 192 MHz ICLK 96 MHz PCLKA 48 MHz PCLKB 48 MHz FCLK 48 MHz IECLK 24 MHz R_CGC_Set PDL_CGC_CLK_PLL PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABL 192E6 96E6 48E6 48E6 48E6 PDL_NO_DAT 24E6 PDL_NO_DA1
50. R_RWP_GetStatus amp PRCR_value amp PWPR_value i 2tEN ESAS Page 129 of 487 RX63N Group 4 Library Reference 4 2 10 Bus Controller 1 R_BSC Set Synopsis Configure the internal bus operation Prototype bool R_BSC_Set uint16_tdata Bus priority selection Description Configure the priority of the internal and external buses data e Bus priority control If multiple selections are required use to separate each selection The default settings are shown in bold Bus to be accessed Priority PDL BSC PRIORITY RAM MB2 or l l PDL BSC PRIORITY RAM _CPU RAM Tpi to ee PDL_BSC_PRIORITY ROM _MB2or oy oe ee Wih hE GEU PDL BSC PRIORITY ROM CPU i PDL BSC PRIORITY PB1 MB2 or PDL BSC PRIORITY PB1 MB1 PDL BSC PRIORITY PB23_MB2 or PDL BSC PRIORITY _PB23 MB1 Peripheral 1 Peripheral 2 and 3 PDL_BSC PRIORITY PB45 MB2or 500 Fixed fo intemal main bus PDL_BSC_PRIORITY_PB45_MB1 eae oa a bl PDL_BSC_PRIORITY_PB6_MB2 or Peripheral 6 f PDL_BSC_PRIORITY_PB6_MB1 eine PDL_BSC_PRIORITY_EB_MB2 or Ext i PDL_BSC_PRIORITY_EB_MB1 xema Return value True if all parameters are valid and exclusive otherwise false Category Bus Controller Reference None Remarks e If itis necessary to call this function call it once only Ensure that both the DTC and DMAC are stopped Program example RPDL definitions include r
51. Repeat or Block size int32_t data7 Address offset uint32_t data8 Source address extended repeat area uint32_t data9 Destination address extended repeat area Change the state of a DMA controller channel data1 The channel number n where n 0 to 1 data2 Control the channel operation If multiple selections are required use to separate each selection e Enable suspend control PDL_EXDMAC_ENABLE Enable re enable DMA transfers PDL_EXDMAC_SUSPEND Suspend DMA transfers e Software trigger control PDL_EXDMAC_START or Start an EXDMA transfer PDL_EXDMAC_START_RUN or Start EXDMA transfers until stopped PDL_EXDMAC_STOP Stop software triggered transfers e Transfer end interrupt flag control PDL_EXDMAC_CLEAR_DTIF Clear the Transfer End flag PDL_EXDMAC_CLEAR_ESIF Clear the Transfer Escape End flag The values to be modified PDL_EXDMAC UPDATE SOURCE Source address using parameter data3 PDL_EXDMAC_UPDATE_DESTINATION Destination address using parameter data4 PDL_EXDMAC_UPDATE_COUNT Transfer count using parameter data5 PDL_EXDMAC_UPDATE_SIZE Repeat block or cluster size using parameter data6 PDL_EXDMAC_ UPDATE OFFSET Address offset using parameter data7 PDL EXDMAC UPDATE REPEAT SOURCE Source address extended repeat area using parameter data8 Destination address extended repeat PDL_EXDMAC_UPDAT
52. Synopsis Prototype Description Check the status of the voltage detection module bool R_LVD_GetStatus uint8_t data 3 Status flags pointer Return value Category Reference Remarks Program example Return the status flags data The Monitor 1 and Monitor 2 status flag shall be stored in the following format b7 b6 b5 b4 b3 b2 b1 bO Monitor 2 Monitor 1 Status Change Status Change 0 0 VCC lt Vdet2 0 0 VCC lt Vdet1 1 VCC 2 Vdet2 0 None 1 VCC 2 Vdet1 0 None or the monitor is 1 Detected or the monitor is 1 Detected disabled disabled True LVD R_LVD_Control R_LVD_Create e Use R_LVD_Control to clear the detection flags e Adetection flag is not valid if Monitor only operation was selected in R_LVD_Create RPDL include definitions r pdl_ivd h RPDL device specific definitions r pdl_definitions h include void fun uint c void 8_t StatusFlags Read the LVD status R_LVD_GetStatus amp StatusFlags R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 115 of 487 RX63N Group 4 Library Reference 4 2 7 Frequency Measurement Circuit 1 R_MCK_Control Synopsis Prototype Description Return value Category References Remarks Program example
53. Valid from 1 to the number of days in the month data5 Configure the Capture 0 RTCICO pin options To set multiple options at the same time use to separate each value The default settings are shown in bold e Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or PDL_RTC_CAPTURE_EDGE_FALLING or PDL_RTC_CAPTURE EDGE BOTH event Select the edge that will trigger a capture e Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or PDL_RTC_CAPTURE_FILTER_ON_DIV_1 or PDL_RTC_CAPTURE_FILTER_ON DIV_32 to the count source Configure the capture noise filter If enabling select the sampling period relative R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 259 of 487 RX63N Group 4 Library Reference Description 3 4 data6 Configure the Capture 1 RTCIC1 pin options To set multiple options at the same time use to separate each value The default settings are shown in bold Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or Select the edge that will trigger a capture PDL_RTC_CAPTURE_EDGE_FALLING or event PDL_RTC_CAPTURE_EDGE_BOTH Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or Configure the capture noise filter If PDL_RTC_CAPTURE_FILTER_ON_DIV_1 or enabling select the sampling period relative PDL_RTC_CAPTURE_FILTER_ON_DIV_32 to the count
54. for i 0 i lt 20 i data_storage i 0x00 T Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend TIC_CHANNEL PDL_IIC_STOP_DISABL EPROM_ADDRESS eeprom_data_array_l 1 P 0 Fi T DL_NO_FUNC Read data from the EEPROM using the DMAC read_eeprom_data Prepare to read the next data This will read back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DMAC_Control 2 R20UT1963EE0100 Rev 1 00 Page 451 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples PDL _DMAC_ SUSPEND PDL _DMAC_ENABLE PDL_DMAC_UPDATE_DESTINATION PDL_DMAC_UPDATE_COUNT PDL_NO_PTR amp data_storage ARRAY_1_SIZE 1 ARRAY_2_SIZE 2 Array size written sub address byte last byte PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Read data from the EEPROM using the DMAC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the EEPROM using the DMAC if false R_IIC_MasterSend IIC_CHANNEL PDL_IIC_DMAC_TRIGGER_ENABLE EEPROM_ADDRESS PDL_NO_PTR PDL_NO_FUNC 0 while 1 while bus_busy true T Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot
55. rpe Interrupt_ 4DC_10 c C wWorkSpace rpe Cancel Interrupt_BSC c C wWorkSpace rpe Interrupt_CMT c C WorkSpace pe Remove Interrupt_DMAC c C wWorkSpace rpe Interrupt_INTC c C wWorkSpace pe Interrupt_not_RPDL c C wWorkSpace pe Remove All Interrupt_SCl c C wWorkSpace rpe Interrupt_TMA c C WorkSpace rpe Interrupt_TPU c C WorkSpace rpe Interrupt WDT c C WorkSpace rpe intpra Ied c C wWorkSpace rpe resetprg c C wWorkSpace pe sbrk c C WorkSpace rpe vecttbl c C WorkSpace rpc R20UT1963EE0100 Rev 1 00 az AS Page 9 of 487 Jul 19 2012 SENES RX63N Group 1 Introduction b Exclusion Select the two files and use the key sequence Alt B to exclude them 33 rpdl_lib_test High performance Embedded Workshop File Edit view Project Build Debug Setup Tools Test Window Help Dei Gls relo la Ane tpdl_lib_test H E C source file dbsct c Interrupt_4DC_10 c Interrupt_BSC c Interrupt_CMT c Interrupt_DMAC c Interrupt_INTC c Interrupt_not_RPDL c Interrupt_SCl c Interrupt_TMR c Interrupt_TPU c Interrupt WDT c intprg c led c resetprg c sbrk c vecttbl c Dependencies enl a g E E 5 E E Default1 desktop 4 Figure 1 3 intprg c and vecttbl c have been excluded R20UT1963EE0100 Rev 1 00 R AS Page 10 of 487 Jul 19 2012 SENES RX63N Group 1 Introduction 9 Set the build options Use the key sequence Alt B R to open the RX Standard Toolchain
56. to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output control for pin TMOn PDL_TMR_OUTPUT_IGNORE_CM_A or No change if a compare match A occurs PDL_TMR_OUTPUT_LOW_CM_Aor 0 is output if a compare match A occurs PDL_TMR_OUTPUT_HIGH_CM_Aor 1 is output if a compare match A occurs PDL_TMR_OUTPUT_INV_CM_A The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or Nochange if a compare match B occurs PDL_TMR_OUTPUT_LOW_CM_B or 0 is output if a compare match B occurs PDL_TMR_OUTPUT_HIGH_CM_B or 1 is output if a compare match B occurs PDL_TMR_OUTPUT_INV_CM_B The output toggles if a compare match B occurs data4 The counter value data5 The compare match A value data6 The compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 and funcs3 True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_Set Remarks e Please use R_TMR
57. 0 1 Event detected 0 No event detected data3 The day of the week and time Specify PDL_NO_PTR if it is not required See R_RTC_Create for the format data4 The year month and day Specify PDL_NO_PTR if it is not required See R_RTC_Create for the format R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 269 of 487 Jul 19 2012 RX63N Group 4 Library Reference Return value Category Reference Remarks Program example True if all parameters are valid otherwise false Real time clock R_RTC_Create 1 1 ui i Vo If an interrupt request flag is set to 1 it shall be automatically cleared to 0 by this function Refer to R_RTC_Create for the time and date formats If the Carry flag is read as 1 the current time and date were updated during the read process and should be re read The year and day of week is not recorded when using the capture registers and will therefore be read back as zero The year returned will be in the range 0 to 99 The hundreds and thousands units are not stored After reading a capture time the event detected flag will be automatically cleared To read the correct value after return from a reset period in software standby mode deep software standby mode or back up state wait for 1 128 second while the RTC clock is operating RPDL definitions nclude r_pdl_rtc h RPDL device specific definitions nclude
58. E6 oo a MASTE PDL_SPI_PIN_SS PDL_SPI_PIN_SSI Prepare the transfer with slave 0 R_SPI_ Command MASTER_CHANNEL 0 PD PD PD i L_SPI_CLOCK_MOD E L_SPI_ASSERT_SS L_NO_DATA 0 0 l PDL_SPI_I LSB_FIRST PDL_SPI_L ENGTH_8 Prepare the transfer with slave 1 R_SPI_ Command MASTER_CHANNEL 1 PD PD PD i L_SPI_CLOCK_MOD E L_SPI_ASSERT_SS L_NO_DATA 1 0 l PDL_SPI_I LSB_FIRST PDL_SPI_L ENGTH_9 Prepare the transfer with slave 2 R_SPI_ Command MASTER_CHANNEL 2 PD PD PD i L_SPI_CLOCK_MOD pah L_SPI_ASSERT_SS L_NO_DATA 12 0 l PDL_SPI_I LSB_FIRST PDL_SPI_L ENGTH_15 Prepare the transfer with slave 3 R_SPI_ Command MASTER_CHANNEL 3 PD PD PD i L_SPI_CLOCK_MOD i L_SPI_ASSERT_SS L_NO_DATA 13 0 l PDL_SPI_I LSB_FIRST PDL_SPI_L Transfer all the data once R_SPI_ Transfer MASTER_CHANNEL ENGTH_24 PDL_SPI_MISOA_PAT7 L1 LOW L3 LOW R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 468 of 487 RX63N Group 5 Usage Examples PDL_NO_DATA master_tx_data master_rx_data 1 PDL_NO_FUNC 0 PDL_NO_FUNC Figure 5 50 Example of multiple sl
59. Jul 19 2012 RENESAS Page 235 of 487 RX63N Group 4 Library Reference Description 2 2 data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for both parameters functand func2 Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_CGC_Control R_LTMR_CreateChannel R_TMR_CreateUnit Remarks e Function R_CGC_Set must be called with the current clock source selected before using this function e This function is an alternative to R TMR_CreateChannel and R_TMR_CreateUnit e Please use R_LTMR_Set to select the output TMOn pin as required This function will return false if a pin is enabled but is not set properly e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 The timing limits depend on the peripheral module clock PCLKB fecike MHZ Equation 50 48 12 5 12 8 1 Timer resolution al 20ns 20 8ns 80ns 83 3ns 125ns Socixe 2 Periodmin 40ns 41 7ns 160ns 166 7ns 250ns Socixe 9 Periodmax_cHANNEL 41 9ms 43 7ms 167 7ms 174 8ms 262ms Srcrxe 29 Periodmax_unit 10 7s 11 2s 42 9s 44 7s 67 1s Socrxs Widthwin Periodmin Widthmax_cHanneL Periodmax CHANNEL Widthmax_unit
60. PDL_MTU2_NF_B_V_DISABLE or Enable or disable noise filter for MTIOCnB n 0 to PDL_MTU2_NF_B_V_ENABLE 4 or TIOC5V n 5 PDL_MTU2_NF_C_W_DISABLE or Enable or disable noise filter for MTIOCnC n 0 3 PDL_MTU2_NF_C_W_ENABLE or 4 or TIOC5W n 5 Not valid for n 1 or 2 PDL_MTU2_NF_D_DISABLE or Enable or disable noise filter for MTIOCnD n 0 3 PDL MTU2 NF D ENABLE or 4 Not valid for n 1 2 or 5 Noise filter clock select for register NFCRn PDL_MTU2_NF_PCLK_DIV_1 or PDL_MTU2_ NF_PCLK_DIV_ 8or Set the clock of the noise filter as PCLKB 1 8 32 PDL_MTU2_NF_PCLK_DIV_32 or or the count source PDL_MTU2_NF_PCLK_DIV_SRC TCNT_TCNTU_ value For n 0 to 4 The timer counter TCNT value For n 5 The timer counter TCNTU value TGRA_TCNTV_value For n 0 to 4 The register TGRA value For n 5 The timer counter TCNTV value TGRB_TCNTW_value For n 0 to 4 The register TGRB value For n 5 The timer counter TCNTW value TGRC_TGRU_value For n 0 3 or 4 The register TGRC value For n 5 The register TGRU value Ignored for n 1 or 2 TGRD_TGRV_value For n 0 3 or 4 The register TGRD value For n 5 The register TGRV value Ignored for n 1 or 2 TGRE_TGRW_value For n 0 The register TGRE value For n 5 The register TGRW value Ignored for n 1 2 3 or 4 TGRF_TADCORA_ value For n 0 The register TGRF value For n 4 The register TADCORA value Ignored for n
61. Return value Category Reference Remarks Program example Disable a DAC channel bool R_DAC_10_Destroy uint8_t data Channel selection Disable the channel output data1 Disable selection To set multiple options at the same time use to separate each value PDL_DAC_10_ CHANNEL_0 Disable channel 0 PDL_DAC_10_CHANNEL_1 Disable channel 1 True if the parameter is valid otherwise false DAC None Once both channels are disabled the module is put into the power down state e Channel 0 is not available on 100 pin package RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down DAC channel 1 R_DAC_10_Destroy PDL_DAC_10_CHANNEL_1 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 374 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_DAC_10_Write Synopsis Prototype Description Return value Category Reference Remarks Program example Write data to a DAC channel bool R_DAC_10_Write uint8_t data1 Channel selection uint16_t data2 Output value uint16_tdata3 Output value Write data to the selected DAC channel s data1 Select the DAC channel output to be modified PDL_DAC_10_CHANNEL_0 Select channel 0 PDL_DAC_10 CHANNEL 1
62. SCl2 RXD2 SMISO2 SSCL2 TXD2 SMOSI2 SSDA2 SCK2 CTS2 RTS2 SS2 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 280 of 487 RX63N Group 4 Library Reference Description 3 5 Valid when n 3 PDL_SCI_PIN_SCI3_RXD3_P16 or ea PDL_SCI_PIN_SCI3_RXD3_P25 PDL_SCI_PIN_SCI3_SMISO3_P16 or PDL_SCI_PIN_SCI3_SMISO3_P25 SMOR PDL_SCI_PIN_SCI3_SSCL3_P16 or PDL_SCI_PIN_SCI3_SSCL3_P25 PDL_SCI_PIN_SCI3_TXD3_P17 or ae PDL_SCI PIN SCI3_TXD3 P23 PDL_SCI_PIN_SCI3_SMOSI3_P17 or SCI3 oe PDL_SCI_PIN_SCI3_SMOSI3_P23 PDL_SCI_PIN_SCI3_SSDA3_P17 or Benne PDL_SCI_PIN SCI3_SSDA3 P23 PDL_SCI_PIN_SCI3_SCK3_P15 or aa PDL_SCI_PIN_SCI3_SCK3_P24 PDL SCI PIN SCI3_CTS3 P26 CTS3 PDL_SCI_PIN_SCI3_RTS3 P26 RTS3 PDL_SCI_PIN_SCI3_SS3_P26 553 Valid when n 4 PDL_SCI PIN SCI4_RXD4 PBO RXD4 PDL_SCI PIN SCI4_SMISO4_PBO SMISO4 PDL_SCI_PIN SCI4_SSCL4_PBO SSCLA PDL_SCI_PIN SCI4_TXD4_PB1 TXD4 PDL_SCI_PIN _SCI4_SMOSI4_PB1 eT SMOSI4 PDL SCI PIN SCI4_SSDA4 PB1 SSDA4 PDL_SCI_PIN_SCI4_SCK4_PB3 SCK4 PDL_SCI_PIN SCI4_CT
63. Slave 3 24 bit data words Figure 5 50 shows how data of appropriate bit lengths is transferred to each SPI slave Commands 0 to 3 are executed in sequence with each command asserting the appropriate SSL pin Peripheral driver function prototypes include r_pdl_spi h include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h define MASTER_CHANNEL 0 void main void const uint32_t master_tx_data 4 Ox000000A4 8 bit data 0x00000132 9 bit data Ox00007F34 15 bit data 0x00345678 24 bit data uint32_t master_rx_data 4 0x00000000 R20UT1963EE0100 Rev 1 00 R AS Page 467 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 0x00000000 0x00000000 0x00000000 Initialise the system clocks The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit NOTE Configure SPI Pin R_SPI_ Set MASTER_CHANNEL PD PD PD PD di L_SPI_SSLAO_PA4 L_SPI_SSLA2_PA1 L_NO_DATA L_SPI_RSPCKA_PA5 P PD PD DL_SPI_MOSIA_PA6 L_SPI_SSLA1_PAO L_SPI_SSLA3_PA2 Configure the master SPI channel R_SPI_ MASTER_CHANNEL Nw wy D D D D D i Create r L_SPI_MODE_SPI L_SPI_PIN_SSLO L_SPI_FRAME_4 L_NO_DATA L_SPI_PIN_SSL2
64. The source start address The valid range depends on the address mode short or full data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers data6 The size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Set R_DTC_Control Ifaddress increment or decrement is selected the address changes according to the number of bytes 1 2 or 4 in each transfer Before calling this function call RLDTC_Set e Call this function before configuring the peripherals that will be involved in the data transfer e Call this function once for each peripheral that will trigger a transfer and for each chained transfer e For chain transfers each transfer data area in the chain must be contiguous e When all calls to this function are complete call R_LDTC_Control to start the DTC Some of MTU MTUO to MTUS5 and TPU TPU6 to TPU11 trigger selections are sharing the same interrupt vectors For details please refer to device hardware manual RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Rese
65. e Channels 1 and 3 are not available with the 100 pin package This function will return false in this case Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 5 bytes from device OxAA on channel 0 using polling R_IIC_MasterReceive 0 PDL_NO_DATA OxAA data_array 5 PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 2tENESAS Page 317 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_lIC_MasterReceiveLast Synopsis Prototype Description Return value Category Reference Remarks Program example Complete a DMAC or DTC based read process bool R_IIC_MasterReceiveLast uint8_t data1 Channel selection uint8_t data2 Data storage address Read one data byte with NACK and stop data1 Select channel IICn where n 0 to 3 data2 The storage location for the data byte True if all parameters are valid and the function completed otherwise false C R_IIC_GetStatus e This function must only be used to terminate a Read process that has used the DMAC or DTC e Use R_IIC_GetStatus to determine if the transfer was successful e Please specify one byte less in the Transfer Count when using with the DMAC or DTC e Channels 1 and 3 are not
66. uint8_t data1 Monitor 1 control uint8_t data2 Monitor 2 control Control the voltage detection configuration data1 Monitor 1 control All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Monitor control PDL_LVD_DISABLE Disable monitor 1 operation Flag control PDL_LVD_CLEAR_DETECTION Clear the monitor 1 change detection flag data2 Monitor 2 control All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Monitor control PDL_LVD_DISABLE Disable monitor 2 operation e Flag control PDL_LVD_CLEAR_DETECTION Clear the monitor 2 change detection flag True Voltage detection circuit R_LVD_Create Other operation changes require the shutdown of both voltage monitors If such changes are required call R_LVD_Create with the new settings RPDL definitions include r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void func void Disable monitor 1 clear the monitor 2 flag R_LVD_Control PDL_LVD_DISABLE PDL _LVD_CLEAR_ DETECTION R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 114 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_LVD_GetStatus
67. 0 Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Figure 5 1 Example of Clock configuration and control R20UT1963EE0100 Rev 1 00 AS Page 381 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 2 Interrupt control Figure 5 2 shows an example of external interrupt use Pin IRQ2 on port pin P32 is used to detect a falling edge and generates an interrupt The interrupt handler inverts the edge detection and disables further interrupts Pin IRQ12 on port pin P44 is used to detect a falling edge and utilises the digital filter Pin IRQ4 on port pin P07 is used to detect a low level signal and generates an interrupt Peripheral driver function prototypes include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototypes void SWl_handler void void SW2_handler void void SW3_handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Select the pins for SW1 SW2 and SW3 R_INTC_SetExtInterrupt PDL_INTC_IRQ2_P32 PDL_INTC_IRQ12_ P44 PDL_INTC_IRQ15_PO7 Configure the SW1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_FALLING Swl_handler 7 Configure the SW2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ12 PDL_IN
68. 0 or 2 PDL_TMR_CLK_TMRO_CM_Aor PDL_TMR_CLK_TMR2_CM_A Counter clearing The compare match A signal from TMR n 1 Valid for n 1 or 3 PDL_TMR_CLEAR_ DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or PDL_TMR_CLEAR_RESET_HIGH Cleared by a rising edge on the external reset pin TMRIn Cleared when the external reset pin TMRIn is high ADC tri PDL_TMR_ADC_TRIGGER_DISABLE or PDL_TMR_ADC_TRIGGER_ENABLE er control Disable or enable ADC conversion start requests on a compare match A signal Only applicable for channels TMRO or TMR2 Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_CM_A DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match A occurs Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL TMR CM B DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match B occurs R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 229 of 487 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference data3 Configure the output control If multiple selections are required use
69. 1 Requested e Group 3 b31 b5 b4 b3 b2 b1 bO TPU interrupts Underflow on Overflow on Underflow on Overflow on Overflow on 0 channel 5 channel 5 channel 1 channel 1 channel 0 0 Not requested 1 Requested e Group 4 b31 b5 b4 b3 b2 b1 bO TPU interrupts Underflow on Overflow on Overflow on Underflow on Overflow on 0 channel 4 channel 4 channel 3 channel 2 channel 2 0 Not requested 1 Requested e Group 5 b31 b5 b4 b3 b2 b1 bO TPU interrupts Underflow on Overflow on Underflow on Overflow on Overflow on 0 channel 11 channel 11 channel 7 channel 7 channel 6 0 Not requested 1 Requested R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 86 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 e Group 6 b31 b5 b4 b3 b2 b1 bO TPU interrupts Underflow on Overflow on Overflow on Underflow on Overflow on 0 channel 10 channel 10 channel 9 channel 8 channel 8 0 Not requested 1 Requested e Group 12 b31 b16 b15 b14 b13 SPI error 0 Channel 2 Channel 1 Channel 0 0 Not requested 1 Requested b12 b11 b10 b9 b8 b7 SCI reception error Channel 12 Channel 11 Channel 10 Channel 9 Channel 8 Channel 7 0 Not requested 1 Requested b6 b5 b4 b3 b2 b1 bO SCI reception error Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 0 Not requested 1 Requested
70. 10 bit Digital to Analog converter These driver functions are used for configuring the DAC module and setting the output voltages R20UT1963EE0100 Rev 1 00 Page 18 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 3 Clock Generation Circuit Driver The driver functions support the control of the internal clock generator providing the following operations 1 Configuration of the multiple clock outputs for system peripheral and external bus operation 2 Controlling the clock generator operation 3 Reading the Clock generator status flags Note Configuring the Clock Generation Circuit also provides information on clock frequencies that will be used by the integrated drivers for other peripherals R20UT1963EE0100 Rev 1 00 Page 19 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 4 Interrupt Control Driver The driver functions support the use of the interrupt controller providing the following operations 1 Selecting the applicable interrupt pins 2 Configuration of an external interrupt signal for use 3 Enabling use of the software interrupt 4 Assigning an interrupt to be processed using the Fast Interrupt route 5 Assigning handlers for the fixed exception interrupts 6 Controlling an external interrupt input 7 Reading the status of an external interrupt 8 Reading an interrupt register 9 Writing to an interrupt register 10 Modifying an interrupt register 11 Configuring a group of i
71. 2 2 e Group 6 selections PDL_INTC_GRP6_TCI8V PDL_INTC_GRP6_TCI8U PDL_INTC_GRP6_TCI9V PDL_INTC_GRP6_TCI10V PDL_INTC_GRP6_TCI10U Overflow on TPU channels 8 9 or 10 Underflow on TPU channels 8 or 10 e Group 12 selections Flag clearing using PDL_INTC_GROUP_CLEAR is not possible PDL_INTC_GRP12_ERIO PDL_INTC_GRP12_ERI1 PDL_INTC_GRP12_ERI2 PDL_INTC_GRP12_ERI3 PDL_INTC_GRP12_ERI4 PDL_INTC_GRP12_ERI5 PDL_INTC_GRP12_ERI6 Reception error on SCI channels 0 to 12 PDL_INTC_GRP12_ERI7 PDL_INTC_GRP12_ERI8 PDL_INTC_GRP12_ERI9 PDL_INTC_GRP12_ERI10 PDL_INTC_GRP12_ERI11 PDL_INTC_GRP12_ERI12 PDL_INTC_GRP12_SPEI0 PDL_INTC_GRP12_SPEI1_ SPI error on channels 0 to 2 PDL_INTC_GRP12_SPEI2 Return value False if the group number is invalid otherwise true Category Interrupt control Reference R_INTC_CreateGroup Remarks Do not use this function if RPDL functions will be used to control the applicable peripheral e Call R_INTC_CreateGroup before calling this function e Flag clearing is done after any interrupt disabling and before any interrupt enabling e Group 12 interrupts use level detection so clearing must be done by clearing the source of the interrupt Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func vo
72. 5 R_TMR_CreateOneShot Synopsis Prototype Description Return value Configure and use a one shot timer bool R_TMR_CreateOneShot uint8_tdata1 8 bit channel or 16 bit unit timer selection uint32_tdata2 Configuration selection double data3 Period void func Callback function uint8_t data4 Interrupt priority level Set up a TMR timer channel or unit for one shot operation and start the timer data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR_UNIT1 The channel n n 0 1 2 or 3 or unit n n 0 or 1 to be configured data2 Configure the timer Use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output pin control For the duration of the one shot period generate a PDL_TMR_OUTPUT_HIGH or high level output PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 e DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR_PULSE_DTC_TRIGGER_ENABLE DTC when the one shot period ends e Control the CPU during the one shot operation PDL_TMR_CPU_ONor Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts POATE
73. Library Reference 2 R_PPG_Desiroy Synopsis Prototype Description 1 2 Disable PPG outputs bool R_PPG_Destroy uint32_tdata Output pin selection Disable the pulse output on the selected pins data Select the outputs to be disabled If multiple selections are required use to separate each selection Select only outputs within one group PDL_PPG_PO0_PIN_P20 PDL_PPG_PO1_PIN_P21 PDL_PPG_PO2_PIN_P22 PDL_PPG_PO3_PIN_P23 PDL_PPG_PO4_PIN_P24 PDL_PPG PO5 PIN P25 PDL_PPG_PO6_PIN_P26 PDL_PPG_PO7_PIN P27 PDL_PPG_PO8_PIN_P30 PDL_PPG PO9 PIN P31 PDL_PPG_PO10_PIN P32 PDL_PPG PO11_PIN P33 PDL_PPG PO12 PIN P34 PDL_PPG_PO13_PIN_P13 or PDL_PPG PO13 PIN P15 PDL_PPG_PO14_PIN P16 PDL_PPG_PO15_PIN_P14 or PDL_PPG_PO15_PIN P17 PDL_PPG_PO16_PIN_P73 or PDL_PPG_PO16_PIN PAO PDL_PPG_PO17_PIN_PA1 or PDL_PPG_PO17_PIN_PCO PDL_PPG_PO18_PIN_PA2 or Group 4 PDL_PPG_PO18_PIN_PC1 or PDL_PPG PO18 PIN PE PDL_PPG_PO19_PIN_P74 or PDL_PPG _PO19 PIN PA3 PDL_PPG_PO20_PIN_P75 or PDL_PPG PO20 PIN PA4 PDL_PPG_PO21_PIN_PA5 or PDL_PPG_PO21_PIN_PC2 PDL_PPG_PO22_PIN_P76 or Group 5 Unit 1 PDL_PPG_PO22_PIN PAG PDL_PPG_PO23_PIN_P77 or PDL_PPG_PO23_PIN_PA7 or PDL_PPG_PO23 PIN PE2 PDL_PPG_PO24_PIN_PBO or PDL_PPG PO24 PIN PC3 PDL_PPG_PO25_PIN_PB1 or PDL_PPG PO25 PIN PC4 PDL_PPG_PO26_PIN_P80 or Group 6 PDL_PPG_PO26_PIN_PB2 or PDL_PPG_PO26_PIN PE3 PDL_PPG_PO27_PIN_P81 or PDL_PPG _PO27_PIN PB3
74. Multifunction Pin Controller Driver 0 ccccceccccecceeeeeeeeeceecaeeeeeeeeesecaeaeeeeeeeseseccaeaeeeeeeeseeennieeeeeeeetenes 22 2 iMCU Operation Driveri sade a sce cates aera acd cae aan ar aaae reaa aae e SA aaa snare anda eneees Qed hate daat 23 2 8 Voltage Detection Circuit Driver iisen arna AE EE EAA AA ARAA ARAE EA ARAE 24 2 9 Frequency Measurement Circuit Driver essssseessseeessrssesnneetinnestinnestanaddtnnnadtanaeatanansnaaadatanadaddnnaeeannt 25 2 10 Low Power Consumption Driver cccccccececeeceeceeeeeeeeeceecaeeeeeeeeescaaeaeeeeeeesescaeaeeeeeeesetsenieeeeeseeetes 26 2 11 Register Write Protection Driver ssssesssssessssnesennassnnnnssnnneentnnastnnnnsnnnannnnnnanttanantinnaanaananntannanaanaaaanne 27 2 127 Bus Controllers Driver e tate saectie ae ee aac alte aaetee ea tae Oh add 28 2 13 DMA Controller DiVersi eend atcha ds canteen tabids acetates aa eth dal acrtes 29 2 14 External DMA Controller Driver ccccccceceeeececce cece ee eeceaeaeeeeeee ees caaeaeceeeeesaeeneaeeeeeeeeeseeeenieeeeeeeeeeees 30 2 15 Data Transfer Controller Driver ccccccceeeeeecee cece eeeeeeccaeceeeeeeesecaeaeeeeeeesesecaeaeeeeeeeseeensaeeeeeeeenees 31 2 16 Multi Function Timer Pulse Unit Driver ccccecccceceeeeeceecee cece eeeeeecaeaeeeeeeeeeeecaeaeeeeeeesetensieeeeeeeeetes 32 2T J Port O tput Enable Driver svete a laiaetidscceadadseedhedbeccoviadgdagit id ateviad iecieltaadeet ala
75. One port pin definition data2 The value to be compared with Between 0x00 and OxFF for a port 0 or 1 for a pin True if the parameters are valid otherwise false Program example Category I O port References R_IO_PORT_Set Remarks e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed e This function waits for the I O port or port pin value to match the comparison data If the I O port s control registers are directly modified by the user this function may lock up The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Wait until pin P05 reads as 0 R_IO_PORT_Wait PDL_IO_PORT_0_5 0 i Wait until port 6 reads as 0x55 R_IO PORT Wait PDL_IO_PORT_6 0x55 i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 100 of 487 Jul 19 2012 RX63N Group 4 Library Reference 9 R_IO_PORT_NotAvailable Synopsis Prototype Description Return value Category References Remarks Program example Configure I O port pins that are not available bool R_IO_PORT_NotAvailable void No parameter is required Set the port pins that are not available on smaller packages to the recommended state True
76. PD2 or PE4 pin for MTIOC4D e Valid whenn 5 PDL_MTU2_PIN_5U_P12 or PDL_MTU2_PIN_5U_PA4 or Select the P12 PA4 or PD7 pin for MTIOCSU PDL_MTU2_PIN_5U_PD7 PDL_MTU2_PIN_5V_P11 or PDL_MTU2_PIN_5V_PA6 or Select the P11 PA6 or PD6 pin for MTIOCS5V PDL MTU2 PIN 5V_ PD6 PDL_MTU2_ PIN 5W_P10 or PDL_MTU2_ PIN_5W_PBO or Select the P10 PBO or PD5 pin for MTIOCSW PDL_MTU2_ PIN 5W_PD5 data3 MTCLK Pin configuration Use to separate each selection Specify PDL_NO_DATA if no MTCLK pin is required e Valid when n O 1 2 3 0r4 PDL_MTU2_ PIN CLKA P14 or PDL_MTU2_ PIN CLKA P24 or PDL_MTU2_PIN_CLKA_ PA4 or PDL_MTU2 PIN CLKA PC6 PDL_MTU2_ PIN CLKB P15 or PDL_MTU2_ PIN CLKB P25 or PDL_MTU2_ PIN CLKB_ PA6 or PDL_MTU2_PIN_CLKB PC7 Select the P14 P24 PA4 or PC6 pin for MTCLKA Select the P15 P25 PA6 or PC7 pin for MTCLKB e Valid when n 0or2 PDL_MTU2_ PIN CLKC_ P22 or PDL_MTU2_PIN_CLKC_PA1 or Select the P22 PA1 or PC4 pin for MTCLKC PDL_MTU2 PIN CLKC PC4 PDL_MTU2_ PIN CLKD_ P23 or PDL_MTU2_ PIN _CLKD_PA3 or PDL_MTU2 PIN CLKD PC5 Select the P23 PA3 or PC5 pin for MTCLKD When n 2 required in Phase Counting Mode only Return value True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference R_MTU2_Create Remarks e Before calling R_M
77. PDL _NO_DATA PDL _NO_DATA R20UT1963EE0100 Rev 1 00 Page 410 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples PDL_NO_DATA PDL_NO_DATA Shutdown channels 0 to 5 R_TPU_Destroy 0 Figure 5 15 Example of Timer pulse Unit use The counter is reset when it reaches 399 The 0 value is a valid state so the output toggle frequency is 50 MHz 400 Counter value TIOCBO TIOCAO Figure 5 16 Example of TPU operation R20UT1963EE0100 Rev 1 00 R AS Page 411 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 12 Watchdog Timer Here the watchdog is configured to generate an NMI interrupt when the counter underflows Notice how the NMI is enabled for WDT interrupts Peripheral driver function prototypes include r_pdl_intc h include r_pdl_wdt h PDL device specific definitions include r_pdl_definitions h static void NMI_handler void void main void Enable the NMI interrupt for WDT R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_WDT_ENABLE NMI_handler 7 i Configure WDT with a 25 to 75 window no reset hence generate NMI R_WDT_Set PDL_WDT_TIMEOUT_1024 PDL_WDT_PCLK_DIV_2048 PDL_WDT_WIN_START_75 PDL_WDT_WIN_END_25 PDL_WDT_TIMEOUT_NMI i Main program loop while 1 Refresh the watchdog R_WDT_Control
78. PDL_INTC_REG_IPL amp ipl R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 80 of 487 Jul 19 2012 RX63N Group 4 Library Reference 9 R_INTC Write Synopsis Prototype Description Return value Category Reference Remarks Program example Update an interrupt register bool R_INTC_Write uint16_t data1 Register selection uint8_t data2 Register value Write the new value to an interrupt register data1 e The register to be updated PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR_ register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register or DTC Activation Enable register or PDL_INTC_REG_SWINTR Software interrupt activation register data2 The value to be written to the register True if the parameter is within range otherwise false Interrupt control None e This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up e For register select one of the registers listed in the tables starting on page 75 e Write 1 to the SWINTR register to generate a software interrupt reque
79. PDL_MTU2_MODE_PHASE3 or PDL_MTU2_MODE_PHASE4 or Phase counting mode 1 2 3 or 4 Valid for n 1 and 2 PDL_MTU2_ MODE _PWM_RS or Reset synchronised PWM mode Valid for n 3 PDL_MTU2_MODE_PWM_COMP1 or PDL_MTU2_MODE_PWM_COMP2 or PDL_MTU2_MODE_PWM_COMP3 configuring channel 4 Complementary PWM mode 1 2 or 3 Valid for n 3 Select Normal operation when R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 177 of 487 RX63N Group 4 Library Reference Description 2 9 e Synchronous mode Valid for n 0 to 4 PDL_MTU2_SYNC_DISABLE or Disable or enable synchronous presetting PDL_MTU2_SYNC_ENABLE clearing DMAC DTC event trigger control Valid for n 0 to 4 unless stated otherwise PDL_MTU2_TGRA_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRA_DMAC_TRIGGER_ENABLE or PDL_MTU2_TGRA _DTC_TRIGGER_ENABLE PDL_MTU2_TGRB_DTC_TRIGGER_DISABLE or TGRB compare match or input PDL_MTU2_TGRB DTC_TRIGGER_ENABLE capture PDL_MTU2_TGRC_DTC_TRIGGER_DISABLE or TORC compare match or input capture PDL_MTU2_TGRC_DTC_TRIGGER_ENABLE Valid for n 0 3 and 4 PDL_MTU2 TGRD_DTC_TRIGGER_DISABLE or a match or input PDL_MTU2_TGRD_DTC_TRIGGER_ENABLE Valid for n 0 3 and 4 PDL_MTU2_TCIV_DTC_TRIGGER_DISABLE or Counter overflow or underflow PDL_MTU2_TCIV_DTC_TRIGGER_ENABLE Valid for n 4 TGRA compare match or input capture
80. PDL_SCI_STOP_1 or PDL_SCI_STOP_2 One or two stop bits The option PDL_SCI_8N1 can be used to select 8 bit data length no parity and one stop bit Options which are available in all Clock Synchronous modes including IIC and SPI SPI mode selection PDL_SCI_SPI_MODE SPI Mode selected Use the R_SCI_SPI_Transfer function not R_SCI_Send or R_SCI_Receive IIC mode selection PDL_SCI_IIC_MODE IIC Mode selected Use the functions R_SCI_IIC_Read and R_SCI_IIC_ Write not R SCI Send or R SCI Receive Options which are available in Clock Synchronous and SPI mode Data clock source selection Select the On chip baud rate generator PDL_SCI_CLK_INT_OUT or The SCKn pin outputs the bit clock In SPI Mode this is Master mode Input the clock to the SCKn pin In SPI Mode this is Slave mode SPI Clock Polarity Inversion PDL SCI CLOCK POLARITY INVERTED The SCK clock is inverted SPI Clock Phase Dela PDL SCI CLOCK PHASE DELAYED The SCK clock is delayed Options which are available in Clock Synchronous mode Not SPI or IIC Hardware Flow Control PDL_SCI_CLK_EXT Select the Hardware Flow Control Option Notes ie ety pet eae e CTS can only be selected if using an internal clock source for SCLK EPEC PES e RTS can only be selected if using external clock source for SCLK Options which are available in SPI mode e SPI
81. PDL_SPI_NEXT DELAY 8 The number of bit clock periods plus two cycles of the peripheral clock between the end of one frame and the start of the next frame Ignored in Slave mode R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 328 of 487 RX63N Group 4 Library Reference Description 3 3 Return value Category Reference Remarks Program example data5 The format must be either e The maximum required bit rate Or b31 b30 to b8 b7 bO 1 0 The SPBR register value If only Slave mode will be used specify PDL_NO_DATA True if all parameters are valid otherwise false SPI R_CGC_Set R_SPI_Set R_SPI_ Command e Function R_CGC_Set must be called with the current clock source selected before using this function Channel 2 is not available for 100 pin package R_IO_PORT_Set can be used to select between CMOS and Open drain output Function R_SPI_Set must be called before any use of this function The actual bit rate will be reduced if division gt 1 is specified in R_SPI_Command RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Configure SPI channel 0 R_SPI_Create 0 PDL_SPI_MODE_SPI_MASTER PDL_SPI_PIN_SSLO_LOW PDL_SPI_FRAME_1_1 PDL_NO_DATA 2E6 R20UT
82. This is ignored if SDRAM pins are not enabled data3 e Recovery cycle insertion control The controls are disabled by default Specify PDL_NO_DATA to use the defaults If multiple selections are required use to separate each selection Bus access Bus type Current Next ee PDL_BSC_RCV_SRRS_ENABLE Read Same PDL_BSC_RCV_SRRD_ENABLE Read Different PDL_BSC_RCV_SRWS_ENABLE Write Same PDL_BSC_RCV_SRWD_ENABLE Separate Different PDL_BSC_RCV_SWRS_ENABLE Read Same PDL_BSC_RCV_SWRD_ENABLE Write Different PDL_BSC_RCV_SWWS_ENABLE Write Same PDL_BSC_RCV_SWWD_ENABLE Different PDL_BSC_RCV_MRRS_ ENABLE Read Same PDL_BSC_RCV_MRRD_ENABLE Read Different PDL_BSC_RCV_MRWS_ENABLE Write Same PDL_BSC_RCV_MRWD_ENABLE Multiplexed Different PDL_BSC_RCV_MWRS_ENABLE Read Same PDL_BSC_RCV_MWRD_ENABLE Write Different PDL_BSC_RCV_MWWS ENABLE Write Same PDL_BSC_RCV_MWWD_ENABLE Different data4 Error monitoring PDL_BSC_ERROR_ILLEGAL_ADDRESS_DISABLE or Disable or enable illegal PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE address access detection PDL_BSC_ERROR_TIME_OUT_DISABLE or Disable or enable bus time out PDL_BSC_ERROR_TIME_OUT_ENABLE detection func The function to be called when a bus error occurs Specify PDL_NO_FUNC if not required
83. amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x0080u Ox0u Tssue a Stop condition R_IIC_Control IIC_CHANNEL PDL_IIC_STOP i bus_busy false void iic_rx_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DTC_Get Status dtc_iicl_rx_transfer_data PDL_NO_PTR PDL_NO_PTR amp DestAddr PDL_NO_PTR PDL_NO_PTR Read one more byte with NACK condition and stop R_IIC_MasterReceiveLast IIC_CHANNEL uint8_t DestAddr bus_busy false Figure 5 46 An example of writing data to and reading data from an EEPROM using the DTC R20UT1963EE0100 Rev 1 00 Page 457 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 18 4 Slave mode In this example the MCU behaves as a virtual slave memory device on channel 0 It will respond to 7 bit address 0001001b The sample is interrupt driven after the initial setup Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h Define the size of the virtual memory define STORAGE_SIZE 0x100 define RX _BUFFER_SIZE STORAGE_SIZE 1 define SLAVE HANNEL 0 iC define SLAVE_ADDRESS 0xA0 static void slave_callback
84. r_pdl_definitions h nt8_t Flags nt32_t CurrentTime id func void Read the current time and flags R_RTC_Read PDL_RTC_READ CURRENT amp Flags amp CurrentTime PDL_NO_PTR R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 270 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 2 21 1 R WDT Set Synopsis Prototype Description Return value Category Reference Watchdog Timer Configure the Watchdog timer bool R_WDT_Sei uint32_t data Set up and start the Watchdog timer data II Configuration selection Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold e Time out selection PDL_WDT_TIMEOUT_1024 or PDL_WDT_TIMEOUT_4096 or PDL_WDT_TIMEOUT_8192 or PDL_WDT_TIMEOUT_16384 Time out period specified in cycles of the divided clock as specified in the Clock Selection below e Clock selection PDL_WDT_PCLK_DIV_4 or PDL_WDT_PCLK_DIV_64 or PDL_WDT_PCLK_DIV_128 or PDL_WDT_PCLK_DIV_512 or PDL_WDT_PCLK_DIV_2048 or PDL_WDT_PCLK_DIV_8192 The division ratio for the internal clock signal PCLKB e MCU reset control PDL_WDT_TIMEOUT_RESET or Window Start Position When the WDT times out select if either a Reset or an PDL_WDT TIMEOUT NMI NMI interrupt will be generated PDL
85. static void SW1l_handler void Figure 5 7 Example of Software Standby Mode R20UT1963EE0100 Rev 1 00 AS Page 393 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 6 2 Deep Software Standby Mode Figure 5 8 shows an example of entering Deep Software Standby mode through Low Power Consumption control PDL functions include r_pdl_cgc h include r_pdl_lpc h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h void NMI_handler_lpc void void main void const uint8_t data_to_save Hello_World_1234567890_abcdefghi uint8_t data_to_restore R_PDL_LPC_BACKUP_AREFA SIZE uint32_t status_flags1 uint32_t status_flags2 Read the LPC status R_LPC_Get Status status_flags1 amp status_flags2 Check if this is an exit from deep software standby BIT_23 1 if status_flagsl amp 0x00800000 0 Read data from the backup registers R_LPC_ReadBackup data_to_restore R_PDL_LPC_BACKUP_AR Have exited deep standby sample finishes here while 1 Configure the NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_FALLING NMI_handler_lpc 7 Allow a falling edge on NMI to cancel deep software standby R_LPC_Create PDL _NO_DATA PDL _NO_DATA PDL_NO_DATA PDL _LPC_CANCEL_NMI_FALLING L_NO_DATA L_NO_DATA L_NO_DATA
86. void iic_rx_dmac_end_handler void define EEPROM_MEMORY_ADDR ESS_UPPER 0x00 define EEPROM RY_ADDR ESS LOWER 0x00 define EEPROM_ADDRESS 0x00A0 define IIC_CHANNEL 0 volatile uint8_t bus_busy volatile uint8_t void main void EEPROM _MEMORY_ADDRESS_UPP data_storage 20 define ARRAY_1 SIZE 6 5 Data bytes 1 address define ARRAY_2 SIZE 11 10 Data bytes 1 address const uint8_t eeprom_data_array_1 ARRAY_1_SIZE EEPROM_MEMORY_ADDRESS_LOWER 1 0x22 0x33 0x44 0x55 const uint8_t eeprom_data_array_2 ARRAY_2_ SIZE EEPROM_MEMORY_ADDRESS_LOWER 5 6 0x07 0x08 0x09 OxO0A OxOB Ox0C 0x0D 0x0E Ox0F 0x1 0x0 uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set up a DMAC channel for IIC transmission R_DMAC_Create 3 PDL_DMAC_ NORMAL PDL AC_SOURC PDL _DMAC_IRO_E PDL_DMAC_TRIGGER_I eeprom_data_array_l uint8_t amp RIICO ARRAY _1_SIZE PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA iic_tx_dmac_end_ha 7 i PDL_DMAC_SIZE_8 E_ADDRESS_PLUS CD PDL_DMAC_DESTINATION_ADDRESS_FIX iD ND ICO_TX ICDR1 ndler
87. 0 PDL_ADC_10_CHANNELS_OPTION_2 48E6 0 6E 6 ADCOIntFunc 2 Set up ADC 0 at 48 MHz in single mode using AN1 R_ADC_10_Create 0 PDL_ADC_10_CHANNELS_OPTION_2 PDL_ADC_10_ADSSTR_SPECIFY 48E6 0x40 ADCOIntFunc 2 i R20UT1963EE0100 Rev 1 00 2tENESAS Page 368 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_ADC_10_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down an ADC unit bool R_ADC_10_Destroy uint8_t data ADC unit selection Put the ADC into the Power down state with minimal power consumption data Select the ADC unit 0 only to be shut down True if a valid unit is selected otherwise false 10 bit ADC None e This function waits for the ADST flag to indicate that the converter has stopped If the ADC unit s control registers are directly modified by the user this function may lock up e Ifthe D A A D synchronous conversion is enabled the 10 bit ADC should not be shut down as it will halt the D A conversion too RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down ADC unit 0 R_ADC_10_Destroy 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 369 of 487 Jul 19 2012 RX63N Group
88. 00 Jul 19 2012 2tEN ESAS Page 209 of 487 RX63N Group 2 R_TPU_Create Synopsis Prototype Configure a Timer Pulse Unit channel bool R_TPU_Create uint8_t data1 uint32_t data2 uint32_t data3 uint32_t data4 uint32_t data5 uint16_t data6 uint16_t data7 uint16_t data8 uint16_t data9 uint16_t data10 4 Library Reference Channel selection II Configuration selection II Configuration selection Configuration selection II Configuration selection Register value Register value Register value Register value Register value void func Callback function void func2 Callback function void func3 Callback function void func4 Callback function uint8_t data11 Interrupt priority level void funcd Callback function void func6 Callback function uint8_t data12 Interrupt priority level 3 Set up a 16 bit TPU channel Description 1 5 data1 The channel number n where n 0 to 11 data2 Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Operation mode PDL_TPU_MODE_NORMAL or PDL_TPU_MODE_PWM1 or PDL_TPU_MODE_PWM2 or PDL_TPU_MODE_PHASE1 or PDL_TPU_MODE_PHASE2 or PDL_TPU_MODE_PHASES3 or PDL_TPU_MODE_PHASE4 Normal operation Pulse Width Modulation PWM mode
89. 1 2 3 or 5 TADCORB_ value The register TADCORB value ignored for n 4 TADCOBRA_ value The register TADCOBRA value ignored for n 4 TADCOBRB_ value The register TADCOBRB value ignored for n 4 R20UT1963EE0100 Rev 1 00 R AS Page 184 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Description 9 9 Return value func1 For n 0 to 4 The function to be called when a TGRA event occurs For n 5 The function to be called when a TGRU event occurs Specify PDL_NO_FUNC if not required func2 For n 0 to 4 The function to be called when a TGRB event occurs For n 5 The function to be called when a TGRV event occurs Specify PDL_NO_FUNC if not required func3 For n 0 3 or 4 The function to be called when a TGRC event occurs For n 5 The function to be called when a TGRW event occurs Specify PDL_NO_FUNC if not required func4 For n 0 3 or 4 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required interrupt_priority_1 The interrupt priority level for TGR A to D or U to W events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 1 to 4 func5 For n 0 The function to be called when a TGRE event occurs Specify PDL_NO_FUNC if not required func6 For n 0 The function to be called when
90. 1 00 Jul 19 2012 2tENESAS Page 122 of 487 RX63N Group 4 Library Reference Remarks Program example Sleep mode is utilised by some peripheral drivers to turn off the CPU when required When entering software standby or deep software standby mode the oscillation stop detection function is disabled The detection is re enabled if software standby mode is interrupted If the sub clock oscillator is not be used use R_CGC_Control to disable the oscillation circuit On exit from deep software standby mode the MCU is reset If Sleep mode return clock source switching has been enabled the only possible clock sources are the LOCO or sub clock oscillator Do not set up the DMACA and DTC to rewrite any registers related to WDT while the chip is in sleep mode If IWDT is stopped do not set up the DMACA and DTC to rewrite any registers related to IWDT while the chip is in sleep mode If a condition for the independent watchdog timer to stop counting applied at the time of a transition to all module clock stop mode using a reset from the independent watchdog timer to release the chip from all module clock stop mode is impossible because the independent watchdog timer is stopped The peripheral Create functions bring modules out of the clock stop state as required The peripheral Destroy functions put modules into the clock stop state as required When All Module Clock Stop mode is cancelled the peripher
91. 1 00 R AS Page 117 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Description 2 4 data2 Select the interrupt IRQO to IRQ7 to cancel deep software standby mode The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Deep software standby cancel control PDL_LPC_CANCEL_IRQO_DISABLE or PDL_LPC_CANCEL_IRQO_FALLING or PDL_LPC_CANCEL_IRQO_ RISING Prevent or allow an edge on the IRQO DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ1_DISABLE or PDL_LPC_CANCEL_IRQ1_FALLING or PDL_LPC_CANCEL_IRQ1_ RISING Prevent or allow an edge on the IRQ1 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ2_DISABLE or PDL_LPC_CANCEL_IRQ2_FALLING or PDL_LPC_CANCEL_IRQ2 RISING Prevent or allow an edge on the IRQ2 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ3_DISABLE or PDL_LPC_CANCEL_IRQ3_FALLING or PDL_LPC_CANCEL_IRQ3 RISING Prevent or allow an edge on the IRQ3 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ4_DISABLE or PDL_LPC_CANCEL_IRQ4_FALLING or PDL_LPC_ CANCEL _IRQ4_ RISING Prevent or allow an edge on the IRQ4 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ5_DISABLE or PDL_LPC_CANCEL_IRQ5_ FALLING or PDL_LPC_CANCEL_IRQ5 RISING Prevent or allow an edge on the IRQ5 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ6_DI
92. 1 comprises channels TMR2 and TMR3 True Timer TMR None The timer unit is put into the stop state to reduce power consumption RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_TMR_Destroy 0 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 240 of 487 RX63N Group 4 Library Reference 7 R_TMR_ControlChannel Synopsis Prototype Description Write to timer channel registers bool R_TMR_ConirolChannel uint8_t data1 Channel selection uint32_tdata2 Configuration selection uint8_t data3 Register value uint8_t data4 Register value uint8_t data5 Register value Modify a timer channel s operation counter and compare registers data1 The channel number n where n 0 1 2 or 3 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source e The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB
93. 2 1 2 4 0 6 25 6 00 oa 228 6 00 4 00 ADCLK MHz Maximum feck 50 00 48 00 0 0 12 00 48 0 cae as Maximum 4 00 4 17 6 25 4 00 4 17 6 25 Conversion time uS F Minimum RARR 05 052 0 78 2 00 2 08 3 13 s mplinatim Minimum 0 5us ping Maximum 255 ADCLK e g 5 1us at 50 MHz Total conversion Conversion time time us Minimum sampling time 1 1 02 1 28 2 5 2 58 3 63 If any of Self Diagnostic enabled options is selected please do not select the Scan mode Input channel selection and Trigger selection Their default settings will be used The user is expected to call RLADC_10_Control and R_LADC_10_Read to get the conversion result Please refer to Section 5 21 for a usage example Simultaneous use of the ADC and DAC peripherals may affect ADC conversion accuracy Please refer to the Hardware Manual for countermeasures The ANEX1 is used when an external operational amplifier is connected to perform A D conversion for the multiple analog values R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 367 of 487 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h ADC unit 0 callback function void ADCOIntFunc void void func void Set up ADC 0 at 48 MHz in single mode using AN1 with 0 6 us sampling time R_ADC_10_Create
94. 3 True if the shutdown succeeded otherwise false R_DMAC Create Program example Return value Category DMA controller Reference Remarks e Ifall channels have been suspended the DMAC module will be shut down e Disabling the DMAC module will also shut down the DTC e If another peripheral is being used to trigger a DMA transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown DMAC channel 2 R_DMAC_Destroy 2 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 149 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_DMAC_Conirol Synopsis Control the DMA controller Prototype bool R_DMAC_Control uint8_t data1 Channel number uint16_t data2 Control options void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint16_t data6 Repeat or Block size int32_t data7 Address offset uint32_t data8 Source address extended repeat area uint32_t data9 Destination address extended repeat area 3 Description 1 2 Change the state of a DMA controller channel data1 The channel number n where n 0 to 3 data2 Control the channel operation If multiple
95. 328 US 735 us 1 31 ms Period pcik 64 1 31 ms 5 24 ms 11 8 ms 21 0 ms Period pcik 128 2 62 ms 10 5 ms 23 5 ms 41 9 ms Period pcik 512 10 5 ms 41 9 ms 94 1 ms 168 ms Period pcik 20438 41 9 ms 168 ms 377 ms 671 ms Period pcik 8192 168 ms 671 ms 1 51s 2 68s Program example RPDL definitions include r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h void func void Configure the watchdog timer for PCLKB 4 Timeout cycles 4096 no windowing and reset operation R_WDT_Set PDL_WDT_PCLK_DIV_4 PDL_WDT_TIMEOUT_RESET PDL_WDT_TIMEOUT_4096 Configure the watchdog timer for PCLKB 128 Timeout cycles 8192 windowing 50 to 25 and reset operation R_WDT_Set PDL_WDT_PCLK_DIV_128 PDL_WDT_TIMEOUT_8192 PDL_WDT_TIMEOUT_RESET PDL_WDT_WI START_50 PDL_WDT_WIN_END_25 R20UT1963EE0100 Rev 1 00 R AS Page 272 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 2 R_WDT Control Synopsis Prototype Description Return value Category Reference Control the Watchdog operation bool R_WDT_Conitrol uint8_t data Control selection Modify the operation of the Watchdog timer data Control the Watchdog timer e Counter update PDL_WDT_RESET_COUNTER_ Refresh the counter True if all para
96. 4 Library Reference Description 2 2 data2 Select the post reset WDT configuration settings If multiple selections are required use to separate each selection e Auto start control PDL_MCU_OFS_WDT_HALTED or p PDL MCU OFS WDT AUTOSTART Disable or enable the WDT auto start mode If auto start mode is enabled select one setting from each of the following e Timeout period PDL_MCU_OFS_WDT_TIMEOUT_1024 or PDL_MCU_OFS_WDT_TIMEOUT_4096 or PDL_MCU_OFS_WDT_TIMEOUT_8192 or PDL_MCU_OFS_WDT_TIMEOUT_16384 Timeout period specified in cycles of the divided clock as specified in the Clock Selection below e Clock division PDL_MCU_OFS_WDT_CLOCK_PCLK 4 or PDL_MCU_OFS_WDT_CLOCK_PCLK_64 or PDL_MCU_OFS WDT_CLOCK_PCLK_128 or PDL_MCU_OFS_WDT_ CLOCK _PCLK_512 or PDL_MCU_OFS_WDT_ CLOCK _PCLK_2048 or PDL_MCU_OFS_WDT_CLOCK_PCLK_8192 The selected clock The PCLKB 4 64 128 512 2048 or 8192 Window end position PDL_MCU_OFS_WDT_WIN_END_75 or The window end position specified as a PDL_MCU_OFS_WDT_WIN_END_50 or percentage of the down counter 0 is when PDL_MCU_OFS_WDT_WIN_END_25 or the down counter would underflow Selecting PDL_MCU_OFS_WDT_WIN_END_0 0 is equivalent to no window end position e Window start position PDL_MCU_OFS_WDT_WIN_START_25 or PDL_MCU_OFS_WDT_WIN_START_50 or PDL_MCU_OFS_WDT_WIN_
97. 4 175 kbps to 168 5 kbps 45 9 kbps to 44 2 kbps to 116 kbps to 30 0 kbps to 1 Mbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 806 kbps PCLKB 8 86 7 kbps to 83 6 kbps to 23 7 kbps to 22 7 kbps to 57 8 kbps to 15 3 kbps to 1 Mbps 1 Mbps 658 kbps 635 6 kbps 1 Mbps 446 kbps PCLKB 16 45 9 kbps to 44 2 kbps to 12 0 kbps to 11 5 kbps to 30 0 kbps to 7 73 kbps to 1 Mbps 1 Mbps 316 kbps 306 1 kbps 806 kbps 217 kbps PCLKB 32 23 7 kbps to 22 7 kbps to 6 06 kbps to 5 8 kbps to 15 3 kbps to 3 89 kbps to 658 kbps 635 6 kbps 175 kbps 168 5 kbps 446 kbps 116 kbps PCLKB 64 12 0 kbps to 11 5 kbps to 3 04 kbps to 2 9 kbps to 7 73 kbps to 1 95 kbps to 316 kbps 306 1 kbps 86 7 kbps 83 6 kbps 217 kbps 57 8 kbps PCLKB 128 6 06 kbps to 5 82 kbps to 1 52 kbps to 1 5 kbps to 3 89 kbps to 975 bps to 175 kbps 168 5 kbps 45 9 kbps 44 2 kbps 116 kbps 30 0 kbps R20UT1963EE0100 Rev 1 00 R AS Page 311 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Select I C mode at 100kHz 100ns rise and fall times R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 100 lt lt 16 100 Select I C mode with two slave addresses R_IIC
98. ADC start request cycle set buffer A This will be ignored if the register is not selected TADCOBRB_ value For n 4 ADC start request cycle set buffer B This will be ignored if the register is not selected Return value True if the channel number is valid otherwise false Category Multi function Timer Pulse Unit Reference R_MTU2_Create R_MTU2_ControlUnit Remarks Before calling this function use R_MTU2_Create to configure the channel operation e Either this function or RLMTU2_ControlUnit must be used to start the timers e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call e If noise filter is enabled before starting the timer make sure at least 2 cycles of the selected noise filter clock has elapsed after the timer configuration use R_MTU2_Create R20UT1963EE0100 Rev 1 00 a2 AS Page 189 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Program example RPDL defini include r_pd RPDL device include r_pd void func void tions l mtu nY specific definitions l_definitions h Allocate a copy of the structure for the selected channel R_MTU2_Con Set the ch3_parame trolChannel_structure ch3_parameters control options for channel 3 ters control_setting PDL_MTU2_STA
99. Channel n forms the higher 16 bits and channel n 1 forms the lower 16 bits PDL_MTU2_CASCADE_AL_IC_EXC_Hor Exclude or include pin MTIOCnA in the TGRA PDL_MTU2_CASCADE_AL_IC_INC_H input capture conditions for channel n 1 PDL_MTU2_CASCADE_BL_IC_EXC Hor Exclude or include pin MTIOCnB in the TGRB PDL_MTU2_CASCADE_BL_IC_INC_H input capture conditions for channel n 1 PDL_MTU2_CASCADE_AH_IC_EXC_Lor Exclude or include pin MTIOC n 1 A in the PDL_MTU2 CASCADE AH_IC_INC L TGRA input capture conditions for channel n PDL_MTU2_CASCADE_BH_IC_EXC_Lor Exclude or include pin MTIOC n 1 B in the PDL_MTU2_CASCADE_BH_IC_INC_L TGRB input capture conditions for channel n R20UT1963EE0100 Rev 1 00 ztENESAS Page 181 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 6 9 TGR_C_D_ operation Configure the operation for general registers TGRC and TGRD Valid for n 0 3 and 4 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRC PDL_MTU2_C_OC_DISABLED or PDL_MTU2_C_OC_LOW or PDL_MTU2_C_OC_LOW_CM HIGH or PDL_MTU2_C_OC_LOW_CML_INV or PDL_MTU2_C_OC_HIGH_CM_LOW or PDL_MTU2_C_OC_HIGH or PDL_MTU2_C_OC_HIGH_CM_INV or MTIOCnC output disabled MTIOCnC output low MTIOCnC initial ou
100. Configure the trigger and output options Use to separate each selection The default settings are shown in bold e EDACKn pin output control PDL_EXDMAC_EDACK_DISABLE or Disable EDACKn output or select PDL_EXDMAC_EDACK_LOW or active low or PDL_EXDMAC_EDACK_HIGH active high operation PDL_EXDMAC_EDACK_SYNC or If the EDACKn output is enabled select negate PDL_EXDMAC_EDACK_WAIT timing with respect to the RD and WR outputs If the EDACKn output is enabled select to enable PDL_EXDMAC_EDACK_TOGGLE toggling of the EDACK pin during transfer to the SDRAM area in single address mode Trigger selection PDL_EXDMAC_TRIGGER_SW or Select activation by software PDL_EXDMAC_TRIGGER_RISING or a rising edge PDL_EXDMAC_TRIGGER_FALLING or falling edge or PDL_EXDMAC_TRIGGER_LOW or low level on the EDREQn pin or PDL_EXDMAC_TRIGGER_MTU1_TPU7__ compare match from MTU1 or TPU data4 Select the completion actions The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Interrupt generation These are all optional PDL_EXDMAC_IRQ_END Transfer completion PDL EXDMAC IRQ REPEAT SIZE END 1 repeat size or 1 block data transfer completion PDL_EXDMAC_IRQ_EXT_SOURCE Extended repeat area overflow on the source PDL_EXDMAC_IRQ_EXT DESTINATION Extended repeat area overflow on the S destination e DTC trigger control PDL_EXDMAC_DTC_TRIGGER_DISABLE
101. Controller LOCO Low speed On Chip Oscillator LSB Least Significant Bit MB Mega Byte 1024 kB MCU Microcontroller Unit MPC Multifunction Pin Controller MSB Most Significant Bit MTU Multi function Timer pulse Unit NMI Non Maskable Interrupt OFS Option Function Select PDG Peripheral Driver Generator PLL Phase Locked Loop POE Port Output Enable PPG Programmable Pulse Generator PWM Pulse Width Modulation RAM Random Access Memory ROM Read Only Memory RPDL Renesas Peripheral Driver Librar RSPI Renesas SPI SCl Serial Communications Interface SDRAM Synchronous Dynamic RAM SMBus System Management Bus SPI Serial Peripheral Interface USB Universal Serial Bus VGA Video Graphics Array WDT Watchdog Timer All trademarks and registered trademarks are the property of their respective owners R20UT1963EE0100 Rev 1 00 R AS Page 16 of 487 Jul 19 2012 SENES RX63N Group 2 Driver 2 Driver 2 1 Overview This library provides a set of peripheral function control programs peripheral drivers for Renesas microcontrollers and allows the peripheral driver to be built into a user program 2 2 Control Functions summary This library has the following control functions available as peripheral drivers 1 Clock Generation Circuit These driver functions are used to configure the multiple internal clock signals 2 Interrupt These driver functions are used for configuring the external interrupt pins handling fixed interrupts and con
102. D o ONHAN VUDWwWwWwe Configure PLL operation The PLL will be set to 192 MHz ICLK 96 MHz PCLKA 48MHz PCLKB 48 MHz FCLK 48 MHz IECLK 24MHz R_CGC_Set PDL_CGC_CLK_PLL PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABL R20UT1963EE0100 Rev 1 00 Page 470 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 192E6 96E6 48E6 48E6 48E6 PDL_NO_DATA 24E6 PDL_NO_DATA Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set the LEDO pin low R_IO_PORT Write LEDO 0 Set the LED1 pin low R_IO_PORT_Write LED1 0 i Set the LEDO pin to output R_IO_PORT_Set LEDO DL_IO_PORT_OUTPUT PDL_IO_PORT_TYPE_CMOS PDL_IO_PORT_DRIVE_HIGH As i Set the LED1 pin to output R_IO_PORT_Set LED1 PDL_IO_PORT_OUTPUT PDL_IO_PORT_TYPE_CMOS PDL_IO_PORT_DRIVE_HIGH T T Use port C for the IEBus pins R_IEB_Set PDL_IEB_PIN_IERXD_PC2 PDL_IEB_ PIN_IETXD_PC3 Configure IEBus channel 0 R_IEB_Create 0 PDL_IEB_MODE_1 PDL_IEB_POLARITY_HIGH 0x0001 0 while 1 Read the status from slave 345h using polling if R_IEB_MasterReceive 0 PDL_IEB_STATUS 0x0345 amp iebus_slave_status amp iebus_rx_data_length PDL_NO_FUNC tru
103. Detected 1 Detected 1 Active 1 Detected data3 The storage location for the number of sequence loops that have been completed in the current transfer Specify PDL_NO_PTR if this information is not required True if all parameters are valid otherwise false SPI None e Ifthe status flags are read and an error or fault flag is set to 1 the flag will be cleared to 0 by this function e Channel 2 is not available for 100 pin package RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t StatusValue Read the status of channel 0 R_SPI_GetStatus 0 amp StatusValue PDL_NO_PTR RENESAS Page 337 of 487 RX63N Group 4 Library Reference 4 2 26 1 R_IEB Set Synopsis Prototype Description Return value Category Reference Remarks Program example IEBus Controller Configure the IEBus pin selection bool R_IEB_Set uint8_t data Pin selection Set up the IEBus options data Configure the IEBus module Use to separate each selection e IERXD pin selection PDL_IEB_PIN_IERXD_P16 or PDL_IEB_PIN_IERXD_PC2 Select the IERXD pin optional IETXD pin selection PDL IEB PIN _IETXD_P17 or PDL_IEB_PIN_IETXD_PC3 Select the ED pin True if
104. E Ea Aa Ra Aadan 130 RIiBSC Setna Se aa a a teed aaa aa ate ete a det AAT aa a aei 130 R BSC Create ait eect 8 eaae a eaa a aaaea aeaa aaa aa da cd tne aada aae AT aed aetna 131 R BSC Cr ateArea ee eaaa eaan a aane eaa e elea ead ae alaaa aeea ee acento aD Eel doere 134 R BSC Dest y rreren lates an n era at ea aaant aaa ea Sanaa dates sae aaa aa ADOT eaS AEAEE eani 137 RO D o R PAE EE T A AE EA E AEE A E ate 138 R_BSC_SDRAM_CreateArea cccccccceeeeescececeeeeeeeeeceaeeeceeeeeseseanaeceeeeeeesasnaeeeeeeeeesensanaeeeeees 140 RN o OEL ENE U EEEE A EE E E A eet ne EAA Yat nee ae 143 NDMA C ntroler s raia e aa aea aaar T aa a eaa vidas eanl Te aa ae aa aE aaar IRO iaa 145 RABINO OET I EAE E E E E A E E A A 145 RA OMA CDOS OV fete Aah ae eee hiner A ene a anaa 149 Re DMAC Controle r tea ned Aaa ee aN sen nee hg Aes She tena ne aa 150 RA DMAGC2Getstatus 424 cre hee e tee ae ec hint a aka hes a sg teas a dats techs canes 153 External DMA Controle ttcicsis seca aces eas eeegaee ee ceuuaaee aa aae aA a A A A a aa 155 ROEXDMAGC Sets retorts Meee ate te e Ne Yea caine haa otis dats teeta ae 155 ROEXDMAG Cheaters octrs tet ie ae ee net a aie hae a Ng tener a hag Aah Sages nee 156 REX MAO DeSttOyi22ccvctts Acee ties he ec knee a Aan a eh ea Ae Yea cine Nag Gotti nee dats tect aoe 159 ROEXDMAG Controls tccccrs tet ihe oe tee net a aie tee a Ne tenner a hag atin Sates tines ale 160 RO EXDMAGC lt GetStatusss fcc cia tenes ac ec ent a ana ie ia
105. EEN Orr The CPU will re start when any valid interrupt occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends Specify PDL_NO_FUNC for this function to wait for the timer to complete before returning You should always specify a function if PDL_TMR_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_CGC_Control R_LTMR_CreateChannel R_TMR_CreateUnit R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 238 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Function R_CGC_Set must be called with the current clock source selected before using this function This function is an alternative to R_LTMR_CreateChannel and R_TMR_CreateUnit Please use R_TMR_Set to select the output TMOn pin as required This function will return false if a pin is enabled but is not set properly This function stops the timer on completion so no other TMR function calls are required If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 If no callback function is specified this fun
106. ESAS Page 319 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Program example 1 1 Vo Vo If a callback function is specified interrupts are used Use R_IIC_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 If using polling mode When the function returns use R_IIC_GetStatus to identify the activity that has occurred Call this function for each transfer required even if the master has ended the previous transfer with a repeat start If the DMAC or DTC is not being used to perform a slave transmission then if a slave transmission is required function R_IIC_SlaveSend must be called to send the data Note If R_IIC_GetStatus reports that the slave is in transmit mode then a slave transmission is required If the master sends more data than is expected and the DMAC DTC trigger is disabled this function will issue a NACK to the master If using the DMAC or DTC for transferring data then ensure they are configured correctly before calling this function False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create Normally bus activity for other slaves is ignored with no CPU involvement However in the specific case where a callback function is specified and the DTC or DMAC is specified for data transmission then any stop condition on the bus will cause the callback
107. Examples Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 L E 3 DL_NO_FUNC G Wo Confirm this write worked by reading back the data from the EEPROM 1 Set current EEPROM address IIC_Buffer 0 EEPROM_ADDRESS R_SCI_IIC_Write CHANNEL_SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 1 IIc_Buffer PDL_NO_FUNC 2 Read data from current address R_SCI_IIC_Read CHANNEL_SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 1 IIC_Buffer PDL_NO_FUNC Confirm the value written is the same as the value read if IIC_Buffer 0 EEPROM_VALUE User Handle Error Figure 5 35 Example of SCI in IIC mode R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 440 of 487 Jul 19 2012 RX63N Group 5 Usage Examples 5 17 10 SCI in IIC Mode using DMAC This shows the setting of SCI channel 2 in to IIC mode and then a write to an IIC EEPROM using the DMAC PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_dmac h PDL device specific definitions include r_pdl_definitions h static void Callback void SCI IIC Channel define CHANNEL _SCI_IIC 2 IIC Slave address of EEPROM define SLAVE _ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM ADDRESS 0x01 volatile bool data_sent false v
108. Group 5 Usage Examples R_INTC_SetExt Interrupt PDL_INTC_IRQ2_P32 PDL_NO_DATA j Enable the SW1 IRQ2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_FALLING PDL_INTC_DTC_TRIGGER_ENABLE IRQ2_handler 7 Start the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA i Wait for user key press of SW1 while 1 void IRQ2_ handler void uintl6_t StatusValue uint32_t SourceAddr uint32_t DestAddr uintl6_t TransferCount Read the status and current source address for the IRQ2 transfer R_DTC_Get Status dtc_irq_transfer_data amp StatusValue amp SourceAddr amp DestAddr amp TransferCount PDL_NO_DATA 3 Invert the LED2 port pin R_IO_PORT_Modify PDL_IO_PORT_1_0 PDL_IO_PORT_XOR i Re enable IRQ2 as a DTC trigger R_DTC_Control PDL_DTC_TRIGGER_IRQ2 PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Figure 5 12 Example of DTC use R20UT1963EE0100 Rev 1 00 Page 406 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 9 2 Chain transfer operation Figure 5 13 shows an example of Data Transfer Controller operation using chain transfer of blocks Address space destination_string_3 destination_string_2 destination_string_1 Transfer 1 is triggered by a
109. Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 24 10 bit Digital to Analog Converter Figure 5 57 shows an example of DAC_10 usage Peripheral driver function prototypes include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void main void VREFH 3 3V cd Expected output voltages are shown in comments g Test align right default R_DAC_10_Create PDL_DAC_10_CHANNEL_1 0x0 0x0 ff 00V Write new data to both DAC channels R_DAC_10_Write PDL_DAC_10_CHANNEL_1 0x0 0x200 fy Let Shut down both DAC channels R_DAC_10_Destroy PDL_DAC_10_ CHANNEL 1 Test align left R_DAC_10_Create PDL_DAC_10_CHANNEL_1 PDL_DAC_10_ALIGN_L 0x0 OxffcO 3 3V Write new data to both DAC channels R_DAC_10_Write PDL_DAC_10_CHANNEL_1 0x0 0x8000 1 7V Shut down both DAC channels R_DAC_10_Destroy PDL_DAC_10_ CHANNEL _1 Figure 5 57 Example of DAC_10 R20UT1963EE0100 Rev 1 00 Page 483 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 25 Programmable Pulse Generator Figure 5 58 shows an example Programmable Pulse Generator usage Peripheral driver function prototypes include r_pdl_ppg h RPDL device specific definitions include r_pdl_definitions h void main void Configure PPG
110. O pins that shall be controlled by the high impedance request software control or the oscillation stop detection flag Select the MTIOCOA MTIOCOB MTIOCOC MTIOCOD MTIOC3B MTIOC3D MTIOC4A PDL_POE_HI_Z_REQ_OSTSTE MTIOC4B MTIOC4C and MTIOC4D pins in high impedance on detection that oscillation has stopped e Output short detection If a short is detected place the all the selected MTU PBL POR SHORT ale channel 3 and 4 pins in the high impedance state PDL_POE_SHORT_MTIOC4BD_A_ Select the MTU channel I O pin pairs that shall be PDL_POE_SHORT_MTIOC4AC_A_ controlled by the short detection response software PDL_POE_ SHORT _MTIOC3BD_A control or the oscillation stop detection flag True if all parameters are valid and exclusive otherwise false Port Output Enable R_POE_Control R_POE_GetStatus R_ MTU2_Set e Do not select MTU pins that are not used e Using R_POE_GetStatus to get the oscillation stop detection flag RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void Configure POE pins 0 and 3 R_POE_Set PDL_POE MODE _0_EDGE PDL POE MODE 3 LOW _128 PDL_POE_0_PORT_D_7 PDL_POE 3 PORT_D 4 PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 201 of 487 Jul 19 2012 RX63N Group 4 L
111. PDL_NO_DATA if no change is required e Counter stop control PDL_MTU2_STOP_C PDL_MTU2_STOP_C PDL_MTU2 STOP C HO H1 PDL MTU2 STOP CH 2 H 3 H4 PDL_MTU2 STOP C Stop the count operation for the selected channels Counter start control PDL_MTU2_START_C PDL_MTU2_START_C PDL_MTU2_START_C HO H1 PDL MTU2 START CH 2 H3 H4 PDL_MTU2_START C Start the count operation for the selected channels R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 191 of 487 RX63N Group 4 Library Reference Description 2 4 R20UT1963EE0100 Rev 1 00 Jul 19 2012 output_control The output control settings to be modified All settings are optional If multiple selections are required use to separate each selection e Output control To apply output control make sure the operation of the corresponding channel is stopped Select one option for each output PDL_MTU2_OUT_P_PHASE_1_ENABLE or PDL_MTU2_OUT_N_PHASE_3_DISABLE PDL_MTU2 OUT P_PHASE_1 DISABLE nore PDL MTU2 OUT N PHASE DISABLE MTIOCSD PDL MTU2 OUT P PHASE 2 DISABLE MTIOCAA PDL MTU2 OUT N PHASE 2_DisagLE MTIOCAC PDL MTU2 OUT P PHASE 3 DISABLE MTIOC4B ee ae oi PDL_MTU2_OUT_P_PHASE_ALL_ENABLE or PDL_MTU2_OUT_P_PHASE_ALL_DISABLE Or all six
112. PDL_SCI_PIN SCI10_ SS10 P83 SS10 e Valid when n 11 PDL SCI PIN SCl11_ RXD11_P76 RXD11 PDL _SCI_PIN SCl11_SMISO11_ P76 SMISO11 PDL_SCI_PIN_SCI11_SSCL11_P76 SSCL11 PDL_SCI_PIN SCl11_TXD11_ P77 TXD11 PDL_SCI_PIN_SCI11_SMOSI11_P77 sci SMOSI11 PDL_SCI_PIN_SCI11_SSDA11_P77 SSDA11 PDL_SCI_PIN_SCI11_SCK11_P75 SCK11 PDL_SCI_PIN_SCI11_CTS11_P74 CTS11 PDL_SCI_PIN_SCI11_RTS11_P74 RTS11 PDL SCI PIN SCl11_SS11_ P74 SS11 e Valid when n 12 PDL SCI PIN SCl12 RXD12 PE2 RXD12 PDL SCI PIN SCIl12 SMISO12 PE2 SMISO12 PDL_SCI_PIN_SCI12_SSCL12_PE2 SSCL12 PDL_SCI_PIN_SCI12_TXD12_PE1 TXD12 PDL _ SCI PIN SCl12 SMOSI12 PE1 Ssci2 SMOSI12 PDL SCI PIN SCI12 SSDA12 PE1 SSDA12 PDL SCI PIN SCl12 SCKi2 PEO SCK12 PDL_SCI_PIN_SCI12_CTS12_PE3 CTS12 PDL SCI PIN SCl12 RTS12 PE3 RTS12 PDL_SCI_PIN SCl12_SS12 PE3 SS12 True if all parameters are valid and exclusive otherwise false SCI R_SCl_Create e Before calling R_SCI_Create call this function to configure the relevant pins e Please refer to the Multifunction Pin Controller MPC section in the RX63N Hardware Manual for details of SCI pin selection e Pins which are not used for the SCI functions may be omitted e This function configures each specified SCI pin It also disables the alternative modes on those pins e Device packages with 145 or fewer pins do not have all of the pin options include r_pdl_sci h void func void Configure RXD1 and TXD1 pins R_SCI_Set 1 PDL
113. Pointer to the variable in which the value shall be stored Gets the value of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 e One port definition or One port pin definition data2 The value will be between 0x00 and OxFF for a port O or 1 for a pin If the I O port specification is incorrect false is returned otherwise true is returned Category I O port Reference R_IO_PORT_Set Remarks Program example e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data Get the value of port pin P12 R_IO_PORT_Read PDL_IO_PORT_1 2 amp data i Get the value of port 4 R_IO_PORT_Read PDL_IO_PORT_4 amp data i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 96 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_IO_PORT_Write Synopsis Prototype Description Return value Category References Remarks Program example Write data to an I O port bool R_IO_PORT_Write uint16_t data1 Port or port pin selection uint8_t data2 The data to be
114. RSC IG Write etenari e aa a aa beg ee een eee neds ee ee 299 RSC IIG Radak e ataa aa aa aaa aaa a AE aa een needed eee dae 301 R SCI IIG ReadLastByte wists neoa aa aaa aaa eaa a a aaia daa eaaet iaaea ieaS a aei 303 RSC Controlere aaia aaa aa aa a fev eaa a aa ae aata a a A a aa raaa iaa Aad 304 R SCl G tStatu Sie a a e i deine A esd ae aa eaaa ae ae 306 PC Bus Interface iaci a lds Meek e ai ae a de ed dee a Meee 308 RENO 8 Create ez emn t A da cada bak e a A diets Mental Ne 308 2 RUC Desttoy viccccae ik tds ented dan niet edi edie dite E daniel 313 3 RIC MasterSend iinne netted ies aae at ten A deat needa nate ie tt 314 4 RIC MasterReceive siiciccccectceciicuaetetenndeevseueae tan aces aa stead a a a o a aaia desu Ei 316 5 RillC MasterReceivelast isis ceccccctnten seb ae eaa ee aea eaaa ana aiaia aa ia eade 318 6 RoC Slav eMonitor moone i a a e aes a a aa a a nun ens ee ee 319 7 RIC Slav Send tinne ation he eae ie tee a ae nee ee 321 8 RoC Control ns na ea tatiana ie aay ng ea An ee 322 9 RiAlIC GetStatus can ccnentts a be eee tA ad ieee ene Lee 323 42 25 Serial PeripheraliIntertace cet letercetiastestecceet ee cbh hee cdtscenddastededdastean add ugete aaa t ea aae anaa 325 1 RSP Setuuica sii adenine nei dre eine a ante ee T 325 2 R SPI Create nn e u nat tendle a aa e aan le ad ad ihe fae needed nine Ae 327 3 Ri SPI De Stroy wee hilec ice cet esnecces cance cena diccev elude cevesunecev ease TN dav NEARE AN
115. RX63N Group 5 Usage Examples 5 4 Voltage Detection Circuit Figure 5 4 shows an example of Voltage detection circuit usage An NMI is generated if the supply voltage drops below 2 95V Peripheral driver function prototypes include r_pdl_lvd h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h static void Callback_NMI void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Configure the NMI to be triggered by the LVD1 signal only no NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_LVD1_ENABLE Callback_NMI PDL_NO_DATA Setup VDET1 to callback if VCC drops below 2 95V R_LVD_Create PDL_LVD_INTERRUPT_NMI_DETECT_FALL PDL_LVD_FILTER_DISABL PDL_NO_DATA NMI Callback function static void Callback_NMI void uint8_t status 0 Read the NMI status R_INTC_GetExtInterruptStatus PDL_INTC_NMI amp status Did an LVD1 trigger occur if status amp BIT_6 0 Clear the LVD monitor 1 flag R_LVD_Control PDL_LVD_CLEAR_DETECTION PDL_NO_DATA Clear the NMI LVD1 flag R_INTC_ControlExtInterrupt PDL_INTC_NMI PDL_INTC_CLEAR_LVD1_FLAG Figure 5 4 Example of Voltage Detection Circuit use R2
116. R_DMAC_Control 3 PDL_DMAC_ENABLE PDL_NO_PTR DL_NO_PTR DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA MU UU ari ho td Clear flag data_sent false Start IIC Write R_SCI_IIC_ Write CHANNEL _SCI_IIC PDL_SCI_IIC_DMAC_TRIGGER_ENABLE SLAVE_ADDRESS PDL_NO_DATA No data length as using DMAC PDL_NO_DATA No buffer as using DMAC PDL_NO_FUNC Wait for write to complete while false data_sent Because using DMAC need to manually send a stop to end the transfer R_SCI_Control CHANNEL_SCI_IIC PDL_SCI_IIC_STOP Callback done static void Callback void data_sent true Figure 5 36 Example of SCI in IIC mode using DMAC R20UT1963EE0100 Rev 1 00 AS Page 442 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 17 11 SCI in IIC Mode using DTC This shows the setting of SCI channel 2 in to IIC mode and then a read from an IIC EEPROM using the DTC PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_dtc h PDL device specific definitions include r_pdl_definitions h static void CallbackRx void SCI IIC Channel define CHANNEL _SCI_IIC 2 IIC Slave address of EEPROM define SLAVE_ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM ADDRESS 0x01
117. Rev 1 00 Jul 19 2012 stENESAS Page 212 of 487 RX63N Group 4 Library Reference Description 4 5 data5 Configure the operation for general registers C and D valid for n 0 3 6 and 9 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Input capture output compare control for register TGRC PDL_TPU_C_OC DISABLED or PDL_TPU_C_OC_LOW or PDL_TPU_C_OC_LOW_CM HIGH or PDL_TPU_C_OC_LOW_CM_INV o PDL_TPU_C_OC_HIGH_CM_LOW or PDL_TPU_C_OC_HIGH or PDL_TPU_C_OC_HIGH_CM_INV or PDL_TPU_C_IC_RISING_EDGE or PDL_TPU_C_IC_FALLING EDGE or PDL_TPU_C_IC_BOTH EDGES or TIOCCn output disabled TIOCCn output low TIOCCn initial output low goes high at compare match TIOCCn initial output low toggles at compare match TIOCCn initial output high goes low at compare match TIOCCn output high TIOCCn initial output high toggles at compare match Input capture at TIOCCn rising edge Input capture at TIOCCn falling edge Input capture at TIOCCn both edges PDL_TPU_C_IC_TPU_COUNT_CLK Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 Input capture output compare control for register TGRD PDL_TPU_D_OC DISABLED or PDL_TPU_D_OC_LOW or PDL_TPU_D_OC_LOW_CM HIGH or PDL_TPU_D_OC_LOW_CM_INV or
118. SCI RXI interrupt routine See source file Interrupt_SCl c for details e The range of achievable bit rates bps is listed below Data fecike Mode clock Limit so rce 50 MHz 32 MHz 12 5 MHz 12 MHz 8 MHz intemal Minimum 96 62 24 23 16 Asynchronous Maximum 3 125 000 2 000 000 781 250 750 000 500 000 External 1 562 500 1 000 000 390 625 375 000 250 000 int rnal Minimum 763 489 191 184 123 Synchronous Maxit 6 250 000 4 000 000 1 562 500 1 500 000 1 000 000 External 8 333 333 5 333 333 2 083 333 2 000 000 1 333 333 Smart card Internal Minimum 2 1 i i Maximum 781 250 500 000 195 312 187 500 125 000 Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Configure SCIO for asynchronous 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC 38400 1 0 PDL_SCI_8N1 Configure SCI1 for asynchronous 8N1 register values supplied R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 BIT_31 PDL_SCI_PCLK_DIV_1 PDL_SCI_CYCLE_BIT_16 115200 amp OxOOFFFFO0O 0x50 1 0 R20UT1963EE0100 Rev 1 00 RENESAS Page 288 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_SCI_ Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down a SCI channel bool R_SCI_De
119. SCI9 TXI PDL_INTC_REG DTCER SCI11_TXI PDL_INTC_REG DTCER SCI10 RXI PDL_INTC_REG DTCER SCI12 RXI PDL INTC REG DTCER SCI10 TXI PDL INTC REG DICER SCI12 TXI R20UT1963EE0100 Rev 1 00 az AS Page 79 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 8 R_INTC_Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read an interrupt register bool R_INTC_Read uint16_t data1 Register selection uint8_t data2 Data storage location Read an interrupt register and store the value data1 e The register to be read PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR_ register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register DTC Activation Enable register data2 The location where the register s value shall be stored True if all parameters are valid and exclusive otherwise false Interrupt control None e For register select one of the registers listed in the tables starting on page 75 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t ipl Read the IPL bits R_INTC_Read
120. SS Pin PDL_SCI_SPI_SS_DISABLE or The SS pin is not used Single master environment The SS pin is used PDL_SCI_SPI_SS_ENABLE Note This option is not available if using SPI Master mode if selected the function will return false Data inversion PDL_SCI_INVERSION_OFF or PDL _SCIl_INVERSION ON Control data inversion transmission and reception R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 285 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 3 4 Options which are available in IIC mode Noise Filter Clock Select PDL_SCI_IIC_FILTER_ DISABLED or The noise filter is disabled PDL_SCI_IIC_FILTER_CLOCK_DIV1 or PDL_SCI_IIC_FILTER_CLOCK_DIV2 or The clock signal 1 2 4 or 8 is used with the PDL_SCI_IIC_FILTER_CLOCK_DIV4 or noise filter PDL_SCI_IIC_FILTER_CLOCK_DIV8 SSDA Delay Output Select Delay on SDA Pin relative to SCL pin PDL_SCI_lIC_DELAY_SDA_0_1 or 0 to 1 cycle delay PDL_SCI_lIC_DELAY_ SDA 1 2or 1 to 2 cycle delay PDL_SCI_IIC_DELAY_SDA 2 3or 2 to 3 cycle delay sequence continues PDL_SCI_IIC_DELAY_SDA_29 30 or 29 to 30 cycle delay PDL_SCI_IIC_DELAY_SDA_30_31 30 to 31 cycle delay Options which are available in Smart Card Interface mode Data inversion PDL_SCI_INVERSION_OFF or PDL_SCI_INVERSION_ON Control data inversion transmission and reception
121. Set flag data_received true Figure 5 30 Example of Synchronous Transmission and Reception code R20UT1963EE0100 Rev 1 00 Page 430 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 17 5 Synchronous Full Duplex Operation This shows the configuration of SCI channel 0 as a clock master with both Rx and Tx data pins enabled Data is received at the same time as data is transmitted Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h evice specific definitions RPDL devi pecific definiti include r_pdl_definitions h SCI channel selection define MASTER_CHANNEL 0 define DATA_LENGTH 5 Rx complete flag volatile uint8_t data_received Callback function prototype static void SCI_Rx_Callback void void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set Master Channel 0 pin options R_SCI_Set 0 PDL_SCI_PIN_SCIO_RXDO_P21 PDL_SCI_PIN_SCIO_TXDO_P20 PDL_SCI_PIN_SCIO_SCKO_P22 Create Clock Master channel for Rx and Tx R_SCI_Create MASTER_CHANNEL PDL_SCI_SYNC PDL_SCI_CLK_INT_OUT PD
122. Valid edge detected on pin IRQn n 0 to 15 PDL_DTC_TRIGGER_ADC10 or Conversion completed on the 10 bit ADC unit PDL_DTC_TRIGGER_ADC12 or Conversion completed on the 12 bit ADC unit PDL_DTC_TRIGGER_TPU_TGIOA or PDL_DTC_TRIGGER_TPU_TGIOB or PDL_DTC_TRIGGER_TPU_TGIOC or PDL_DTC_TRIGGER_TPU_TGIOD or Input capture compare match signals on TPU channel 0 PDL_DTC_ TRIGGER TPU_TGI1A or PDL_DTC TRIGGER TPU TGI1B or Input capture compare match signals on TPU channel 1 PDL_DTC_TRIGGER_TPU_TGI2A or PDL_DTC_TRIGGER_TPU_TGI2B or Input capture compare match signals on TPU channel 2 PDL_DTC_ TRIGGER TPU_TGI3A or PDL_DTC TRIGGER TPU TGI3B or PDL_DTC_TRIGGER_TPU_TGI8C or PDL_DTC_ TRIGGER TPU_TGI3D or PDL_DTC_TRIGGER_TPU_TGI4A or PDL_DTC_TRIGGER_TPU_TGI4B or Input capture compare match signals on TPU channel 3 Input capture compare match signals on TPU channel 4 PDL_DTC_TRIGGER_TPU_TGI5A or PDL_DTC_ TRIGGER TPU_TGI5B or Input capture compare match signals on TPU channel 5 PDL_DTC_ TRIGGER TPU_TGI6A or PDL_DTC_TRIGGER_TPU_TGI6B or PDL_DTC_TRIGGER_TPU_TGI6C or PDL_DTC_TRIGGER_TPU_TGI6D or Input capture compare match signals on TPU channel 6 PDL_DTC TRIGGER TPU TGI7A or PDL_DTC_TRIGGER_TPU_TGI7B or Input capture compare ma
123. a new reading ready if mck_completed true Calculate the frequency of the less stable clock Examples of both equations are given below Calculate the frequency of the reference clock measured_frequency f_system_clock system_clock_count reference_count Calculate the frequency of the system clock measured_frequency f_reference_clock system_clock_count reference_count Process the result here nop Allow a new reading to be taken mck_completed false static void Read_the_MCK void Is it safe to update the stored timer value if mck_completed false Read TGRA from timer 1 R_MTU2_ReadChannel I ock_count x a D D S D D D D D re ie o e s a DD uUtiy yd Ui me yt Signal that the reading is updated mck_completed true Figure 5 5 Example of clock monitoring using MCK system 1 R20UT1963EE0100 Rev 1 00 AS Page 389 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 5 2 Using System 2 Figure 5 6 shows an example of using MCK system 2 and the TPU module to monitor the high speed on chip oscillator HOCO by comparing it with the main clock oscillator Peripheral driver function prototypes include r_pdl_mck h include r_pdl_cgc h include r_pdl_tpu h RPDL device specific definitions include r_pdl_definitions h Ca
124. a new reception process is started PDL_SCI_STOP_RX The option PDL_SCI_STOP_TX_AND_RX can be used to select both processes If both processes are selected transmission and reception will stop immediately e Generate a Space or Mark signal when idle Only applicable in Async and Async Multi Processor Modes Set the idle output to Space logic 0 ERE CLOSE race This can be used to generate a Break condition PDL_SCI_OUTPUT_MARK Set the idle output to Mark logic 1 e Error flag control PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS Try to clear the receive error flags e Manual SCK control PDL_SCI_GSM_SCK_STOP or Disable or enable the clock output can be used while PDL_SCI_GSM_SCK_START GSM mode is enabled data2 IIC Mode only Control the channel e Stop condition generation PDL_SCI_IIC_STOP A stop will be output on the bus e Clock Synchronisation Disable or enable the IIC clock PDL_SCI_IIC_CLOCK_SYNC_DISABLE or synchronisation PDL_SCI_IIC_CLOCK_SYNC_ENABLE Note Clock synchronisation is enabled by default as required for normal operation Return value True if all parameters are valid otherwise false Category SCI Reference Remarks e Device packages with 100 pins do not have all of the SCI channels R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 304 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example
125. all parameters are valid exclusive and achievable otherwise false IEBus R_IEB_Create e Before calling R_IEB_Create call this function to specify the relevant pins RPDL definitions include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h void func void Use port 1 for the IEBus pins R_IEB_ Set PDL_IEB_ PIN_IERXD_P16 PDL_IEB PIN_IETXD_P17 R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 338 of 487 RX63N Group 4 Library Reference 2 R_IEB_Create Synopsis Prototype Description Return value Category Reference Configure the IEBus channel bool R_IEB_Create uint8_t data1 uint32_t data2 uint16_t data3 uint8_t data4 Unit address Set up the selected IEBus channel data1 Select channel n where n 0 only data2 Configure the channel mode and connection settings If multiple selections are required use to separate each selection The default settings are shown in bold Module clock frequency division Channel selection Channel configuration Interrupt priority level PDL_IEB_CLOCK_INTEGER or PDL_IEB_CLOCK_VGA or Select between integer type e g 12 0 MHz and VGA derived type e g 12 58 MHz for the IEBus clock IECLK frequency The division applied to IECLK will be determined by this function P
126. be used for signal CS3 PDL_BSC_CS4_P64 or PDL_BSC_CS4_P74 or PDL_BSC_CS4 P24 PDL_BSC_CS5_P65 or PDL_BSC_CS5_P75 or PDL_BSC_CS5 P25 PDL_BSC_CS6_P66 or PDL_BSC_CS6_P76 or PDL_BSC_CS6 P26 Select the port pin to be used for signal CS4 Select the port pin to be used for signal CS5 Select the port pin to be used for signal CS6 PDL_BSC_CS7_P67 or PDL_BSC_CS7_P77 or PDL_BSC_CS7_P27 WAIT pin selection only re Select the port pin to be used for signal CS7 uired if the WAIT signal is to be used PDL_BSC_WAIT_P51 or PDL_BSC_WAIT_P55 or PDL_BSC_WAIT_P57 or PDL_BSC_WAIT_PC5 Select the port pin to be used for signal WAIT ALE signal control only required if the ALE signal is to be used PDL_BSC_ALE_ENABLE Enable the ALE signal on pin P54 Address pins A16 to A23 pin selection only required if any of A16 to A23 are to be used PDL_BSC_A16_A23 PC or PDL_BSC_A16_A23 P9 Select either Port C or Port 9 for address A16 to A23 pins R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 131 of 487 RX63N Group 4 Library Reference Description 2 3 data2 e Address output control The signals are enabled by default unless the pin is allocated to a bus control signal If multiple selections are required use to separate each selection Specify PDL_NO_DATA for no change PDL_BSC_A7_A0O_DISABLE Disable the o
127. been selected This will allow for the user s code to be ported to another project that does use a smaller MCU package 2 Initialisation of the sub clock oscillator if not used If the sub clock oscillator will not be used it should be put into a stable state using the R_CGC_Control function Stop the sub clock oscillator R_CGC_Control PDL_NO_DATA PDL_NO_DATA PDL_CGC_SUB_CLOCK_DISABLE R20UT1963EE0100 Rev 1 00 R Page 14 of 487 Jul 19 2012 2 XENESAS RX63N Group 1 Introduction 1 3 Document structure The drivers are summarised in section 2 and explained in detail in section 4 Section 5 provides usage examples Section 6 provides details which are specific to the RX CPU R20UT1963EE0100 Rev 1 00 Page 15 of 487 Jul 19 2012 RENESAS RX63N Group 1 Introduction 1 4 List of Abbreviations and Acronyms Abbreviation Full form Analog to Digital Converter Application Programming Interface Binary Coded Decimal Binary digit Bits per second Bus State Controller Controller Area Network Central Processing Unit CRC DAC Digital to Analog Converter DC Direct Current DMA Direct Memory Access DMAC DMA Controller DSP Digital Signal Processing DTC Data Transfer Controller EEPROM Electrically Erasable and Programmable ROM EXDMA External DMA EXDMAC External DMAC FIFO First In First Out Global System for Mobile communications High performance Embedded Workbench Interrupt
128. data3 The counter value This will be ignored if the register is not selected data4 The compare match A value This will be ignored if the register is not selected data5 The compare match B value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateChannel Remarks None R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 241 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Load the counter on channel TMRO R_TMR_ControlChannel 0 PDL_TMR_COUNTER OxFF PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 242 of 487 RX63N Group 4 Library Reference 8 R_TMR_ConitrolUnit Synopsis Prototype Description Write to timer unit registers bool R_TMR_ControlUnit uint8_t data1 Unit selection uint32_t data2 Configuration selection uint16_t data3 Register value uint16_t data4 Register value uint16_t data5 Register value Modify a timer units counter and compare registers data1 The unit number n where n 0 or 1 data2 The channel settings to be modified If multiple selections are requir
129. detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from t
130. detected Figure 5 24 Example of Real Time Clock use with Capture Pin R20UT1963EE0100 Rev 1 00 Page 420 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 15 4 Real time Clock operation with Vbatt mode Figure 5 25 shows an example of using the Real time Clock operate with Vbatt mode Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h include r_pdl_definitions h include r_pdl_mcu_ofs h Enable LVD channel 0 R_MCU_OFS PDL_MCU_OFS_IWDT PDL_MCU_OFS_WDT_HALTED PDL_MCU_OFS_LVD_0O_ENABLE PDL_MCU_OFS_CGC_HOCO_DISABLI void main void uintl6_t status 0 Initialise the system clocks NOTE The code to initialise the system clock using 4 2 1 1 is omitted here NOTE Ensure the Sub clock is enabled and stable before calling 4 2 20 1 Get Reset Status Flag R_MCU_Get Status PDL_NO_PTR amp status PDL_NO_PTR PDL_NO_PTR Check Voltage Monitoring 0 Reset Detect Flag Do not call R_RTC_Create again if LVDO reset is detected recovering from Vbatt mode status amp BIT_1 0 R_RTC_Create PDL_RTC_COUNT_SOURCE_SUBCLK DL_NO_DATA Pin settings xFF173350 Automatic day of week 17 33 50 110518 18 May 2011 DAT Capture 0 DATA Capture 1 DATA Capture 2 DAT Periodic DAT Alarm Alarm date
131. e ID transmission control valid only in Multi processor mode Transmit the upper byte as the ID byte POE SCI eee OVEL E The valid ID range is 0 to 255 data3 The start address of the data to be sent Specify PDL_NO_PTR for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data4 For sending binary data set this to the number of bytes to be sent The valid range is 1 to 65535 Set this to 0 for transmission of a null terminated character string For the ID cycle in Multi processor mode specify 0 If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Use R_SCI_Control to terminate this operation early R_SCl_GetStatus can be used to find out how many characters have been transmitted Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling fag eis bytes has been sent Interrupts The function to be called when the last byte has been sent DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback function specified in R DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create True if all parameters are valid and the operation completed without errors False if a paramet
132. edie Badd Sabet stan 263 Re RUG Control acc tte cect cite et ate eta ee ahs ee ae ee teas ala setea ae Recta vs a Teach 264 RURT Ge Rag wicca tes Mea ye he tac nc A Aye a a Ye eine Neg cole gate fects ten cats 269 Watchdog Timeni s Since ites en A een at ee eee 271 ReaWiDT Sets tic ae hac hintee hea het ate ec ener hak eee a a Yen telnet ies keds ta tenant 271 RAN ABIE o Ko essa tee oot E as teen a eae te a Ng tenner hag atin ee a eaten ote eta le 273 Re WiDTe UREA yee asset cee ae ahs a eg Ne Yee tain hae Gotta a folate a cate 274 Independent Watchdog Timer e ccceesecceceeeeceeeeeseeceeeeneneeeeeneneeseenneeeeeneneeeeeneneeeeeneeeeeneneees 275 RelWiD Isoelectric Acai eee a Aa eg a A ee Gotta ee gate fete Pence 275 RelW DTC OnMtMols 42 te ices cage et ae tee neta hai ee a Ns tenner hag Ae ee gate a 277 PREIWID Ti ROG cet ties os ea ane a E Aa A ea Ne A hae Gane Nae EEN 278 Serial Communication Interface cccccccececeeeeeeeeceeceeeeeeececeaeaeeeeeeeeesecaeaeeeeeeesensenaeeeeeeeeteees 279 PRED C ESC a ce eed tee E eager Ace E Meee ee cht at els ee ne 279 RSC Create nani naar i Sieve A a a ees a eaa hee ete ae 284 RSCl Destroy s n e aaae nee a aaa aa aaa ene ee ile ia eve de 289 ReSCl S Nd tvs cecis acdsee Sereda tre deveined A eel een edani de dee 290 RSC Receive shades e aa ainsi i eed bead ae dessin eed aaia daa aaeanoa dette da 293 R SCI SPI Transfer srin aeaoe aa aaa aaaea eels eee aeaa iaaa aaa aS aaa 296
133. endian 166 pins big endian 1 2 3 4 5 6 8 9 6 i 3 Please enter the path where you wish RPDL for RX63N to be installed ci my_project_folder Creating the destination directory c my_project_folderNRPDL Copying the generic files Copying the files for a 1 76 pin package with little endian support Finished Press any key to continue Press any key to close the window R20UT1963EE0100 Rev 1 00 R AS Page 4 of 487 Jul 19 2012 SENES RX63N Group 1 Introduction 3 Include the new directory Use the key sequence Alt B R to open the RX Standard Toolchain window Select the C C tab Use the key sequence S to show the included file directories Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Base path Project directory v j WorkSpace rpdl_lib_test rpdl_lib_test Sub Directory RPDL Cancel Click on OK to close the window Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Base path Project directory v i WorkSpace rpdl_lib_test rpdl_lib_test Sub Directory Cancel Click on OK to close the window R20UT1963EE0100 Rev 1 00 az AS Page 5 of 487 Jul 19 2012 XENES RX63N Group 1 Introduction 4 Add the RPDL library file The library
134. for registers TGRA and TGRC PDL_TPU_BUFFER_BD_DISABLE or PDL_TPU_BUFFER_BD_ENABLE Disable or enable buffer operation for registers TGRB and TGRD ADC trigger control PDL_TPU_ADC_TRIG_DISABLE or PDL_TPU_ADC_ TRIG ENABLE Disable or enable ADC conversion start requests on a TGRA input capture compare match data4 Configure the operation for general registers A and B If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRA PDL_TPU_A_OC DISABLED or PDL_TPU_A_OC_LOW or PDL_TPU_A_OC_LOW_CM HIGH or PDL_TPU_A_OC_LOW_CM_INV or PDL_TPU_A_OC_HIGH_CM_LOW or PDL_TPU_A_OC_HIGH or PDL_TPU_A_OC_HIGH_CM_INV or PDL_TPU_A_IC_RISING_EDGE or PDL_TPU_A_IC_FALLING EDGE or PDL_TPU_A_IC_ BOTH EDGES or TIOCAn output disabled TIOCAn output low TIOCAn initial output low goes high at compare match TIOCAn initial output low toggles at compare match TIOCAn initial output high goes low at compare match TIOCAn output high TIOCAn initial output high toggles at compare match Input capture at TIOCAn rising edge Input capture at TIOCAn falling edge Input capture at TIOCAn both edges PDL_TPU_A_IC_TPU_COUNT_CLK or Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses
135. function This means that no other interrupt can be processed until the callback function has completed R20UT1963EE0100 Rev 1 00 ae ENESAS Page 233 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure TMR unit 0 PCLKB clear after a compare match A R_TMR_CreateUnit 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_ CLEAR _CM_A 0 0 199 Oo PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 234 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_TMR_CreatePeriodic Synopsis Prototype Description 1 2 Select periodic operation bool R_TMR_CreatePeriodic uint8_t data1 8 bit channel or 16 bit unit selection uint32_tdata2 Configuration selection double data3 Period or frequency double data4 Pulse width or duty cycle void func1 Callback function void func2 Callback function uint8_t data5 Interrupt priority level Set up a TMR timer channel or unit for periodic operation and start the timer data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR_UNIT1 The channel n n 0 1 2 or 3 or unit n 0 or 1 to be configured data2 Configure the timer If m
136. function R_SPI_Set to select the respective output pin PDL_SPI_PIN_SSLO_LOW or Select active low or active high PDL_SPI_PIN_SSLO_HIGH or for output signal SSLO PDL_SPI_PIN_SSL1_LOW or Select active low or active high PDL_SPI_PIN_SSL1_HIGH or for output signal SSL1 PDL_SPI_PIN_SSL2_LOW or Select active low or active high PDL_SPI_PIN_SSL2_HIGH or for output signal SSL2 PDL_SPI_PIN_SSL3_LOW or Select active low or active high PDL_SPI_PIN_SSL3_HIGH or for output signal SSL3 PDL_SPI_PIN_MOSI_IDLE_LAST or bos PDL SPI PIN MOSI IDLE LOW or Lia output state when no SSLn pin is PDL_SPI_PIN_MOSI_IDLE_HIGH R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 327 of 487 Jul 19 2012 RX63N Group Description 2 3 data3 Configure the data format If multiple selections are required use to separate each selection The default settings are shown in bold 4 Library Reference Buffer size PDL_SPI_BUFFER_64 or Select a buffer size of 64 bits up to four 16 bit frames or PDL_SPI_BUFFER_128 128 bits up to four 32 bit frames Frame configuration selection refer to Table 38 4 in the hardware manual Number of Number of frames in Number of Selection command each command transfer transfers transfer frames PDL_SPI_FRAME_1_1 or 1 1 1 PDL_SPI_FRAME_1_2 or 1 2 2 PDL_SPI_FRAME_1_3 or 1 3 3 PDL_SPI_FRAME_1_4 or 1 4 4 PDL_SPI_FRAME_2_1 or 2 1 2 PDL_SPI_FRAME_2_2 or 2 2 4 PDL_SPI_FRAME_3 or 3 1 3 PDL_SPI_FRAME_
137. ge 437 DNB SCI iM NC Modere e ad celetietaa lattes hee lagsebbetiate dite detent 439 5 17 10 SC in IWC Mode using DMAC 1 00 0 eeccceeeeceeeeeneeeeee entree ee eaeeeeeeaeeeeeeaeeeeeeaeeeeeenaeeeseenaeeeeneaas 441 5 17 11 SCI in IWC Mode using DTC ec een eee tee e eet e a a ean 443 5 18 FC Bus Interface serde i aha feed eaten ave elena a a a a mation leiden 446 5 18 1 Master mode sicdlis wie oie e aa tae taeda den eas ae ra a eee a 446 1 Configuration and transmission 0 ccc eeeeee ee eene ee ee enne ee ee tne ee ee ttnan ee taeeeeetaeeeeeeieeeernnaeeeeee 447 2 Recepto nanei shades nees tenth et shade eet rth eee teetering athe 448 3 Repeated Startas ctscchi unean raa i aie tinea ee noted T 449 5 18 2 Master mode with DMAC cceceeccecce cece ee eeeenaeeeceeeeesgeanaeceeeeeeeseaaaeaeceeeeeceseceaeaeeeeeeeeeeensaees 450 5 18 3 Master mode with DTC rirse eni e a e a e aa eri a a aaea 454 518 4 Slave MOda en n hie a a a e a ta e a eaaa 458 5 19 Serial Peripheral Int rface n snesena e e e a aa e e e e el ee ed 461 O19 Ay Usmgone ave Ta a a E suds Sev das E E EEA 461 TIa Usm One SENE 2ra T E EE E E E E 464 5 19 3 Master operation with multiple SIAVES cececeeeecceceeeeeeeeeeeaeceeeeeeeseceaeaeeeeeeeseseneaeaeeeeeersesenaees 467 520 EBUS IMG aCe vievets tert anii e ee ea eee tad uals Sue ed lak Mn Mute ae th 470 5 20 15 Master Operation ii oare thet e cist deeiscaeniestabiieetcaseheii
138. h gt const char source_string_1 Renesas RX63N volatile char destination_string_l 008 ny void func void Re enable transfers on channel 2 R_DMAC_Control DMAC_ENABLE L_NO_PTR L_NO_PTR L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA ao Sao Sae ae ae a ao UN OOO Oo oO oO Os Reload and trigger channel 1 R_DMAC_Control 1 PDL _DMAC_ENABLE PDL_DMAC_ START PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDATE_DESTINATION PDL_DMAC_UPDATE_COUNT PDL_DMAC_UPDATE_SIZE source_string_l destination_string_l 1 uintl6_t strlen source_string_l PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 152 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_DMAC_GetStatus Synopsis Prototype Description Check the status of a DMA channel bool R_DMAC_GetStatus uint8_t data1 Channel number uint8_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint16_t data6 Current Repeat or Block size count pointer Return status flags and current channel registers data1 The channel number n where n 0 to 3 data2 The status fla
139. include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h include r_pdl_definitions h void main void Prepare the LOCO settings R_CGC_Set PDL_CGC_CLK_LOCO PDL_CGC_BCLK_DISABLE 125E3 125E3 125E3 125E3 125E3 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Initialise sub clock R_CGC_Control PDL_NO_DATA PDL_NO_DATA PDL_CGC_SUB_CLOCK_ENABLE i Wait for the Subclock stabilisation time 2 seconds minimum NOTE As currently running from the LOCO the R_CMT_CreateOneShot max time limit is gt 2 Secs R_CMT_CreateOneShot 0 PDL_NO_DATA 2 0 PDL_NO_FUNC 0 i Set the current time and enable the alarm R_RTC_Create PDL _RTC_COUNT_SOURCE_SUBCLK PDL_RTC_24 HOUR _MODE PDL_NO_DATA OxFF114250 Automatic day of week 11 42 50 0x20101118 18 Nov 2010 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO_DATA Figure 5 22 Example of enabling the Sub clock before using the Real Time Clock R20UT1963EE0100 Rev 1 00 Page 417 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 15 2 Running from the Sub clock before using the Real time Clock Figure 5 23 shows an example of running from the Sub clock before using the Real time Clock Peripheral driver function prototype
140. interrupt processing for one interrupt bool R_INTC_CreateFastinterrupt The interrupt to be selected uint8_t data data Choose the interrupt vector to be processed using the fast interrupt process Name PDL_INTC_ VECTOR BUSERR Module External bus Interrupt cause Error illegal access or timeout PDL_INTC_VECTOR_FIFERR PDL_INTC_VECTOR_FRDYI Flash memory Error Ready PDL_INTC_VECTOR_SWINT Interrupt control Software interrupt PDL_INTC_ VECTOR CMTO PDL_INTC_VECTOR_CMT3 PDL_INTC_VECTOR_CMT1 PDL_INTC_VECTOR_CMT2 Compare match timer Compare match PDL_INTC_VECTOR_EINT Ethernet control Event detection PDL_INTC_VECTOR_DOFIFOO PDL_INTC_VECTOR_D1FIFOO PDL_INTC_VECTOR USBIO PDL_INTC_VECTOR_USBRO USB channel 0 DOFIFO transfer request D1FIFO transfer request Event detection Resume PDL_INTC_VECTOR_DOFIFO1 PDL_INTC_VECTOR_D1FIFO1 PDL_INTC_VECTOR USBI PDL_INTC_ VECTOR USBR1 USB channel 1 DOFIFO transfer request D1FIFO transfer request Event detection Resume PDL_INTC_VECTOR SPRIO Receive buffer full PDL_INTC_VECTOR SPII2 PDL_INTC_VECTOR_RXFO PDL_INTC_VECTOR_TXFO PDL_INTC_VECTOR_RXMO PDL_INT
141. k bytes has been received The function to be called when the number of received bytes reaches the Interrupts threshold number Either the function to be called when each byte is received or DMAC PDL_NO_FUNC if the callback function specified in R_LDMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create func3 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range Category SCI Reference R_SCl_Control R_SCl_GetStatus Remarks The maximum number of characters to be received or transmitted is 65535 e Wait until a transmission on the same channel is complete before calling this function If no error callback function func3 is specified the error flags are cleared automatically to allow the reception process to complete e Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed In SPI master mode the slave s SS pin must be asserted before calling this function A general I O pin can be used for this see the I O Port API If using the DMAC or DTC this module does not kn
142. mode to be the same or opposite to that of the CPU Multiplexed mode PDL_BSC_SEPARATE or PDL_BSC_MULTIPLEXED Select separate or multiplexed address and data pins Write access mode PDL_BSC_WRITE_BYTE or External wait control PDL BSC WRITE SINGLE single write strobe mode Select byte or PDL_BSC_WAIT_DISABLE or PDL_BSC_WAIT ENABLE Disable or enable external wait control using the WAIT signal Page access control PDL_BSC_PAGE_READ_DISABLE or PDL_BSC_PAGE_READ_NORMAL or PDL_BSC_PAGE_READ CONTINUOUS Disable or enable page read accesses using normal access compatible mode or continuous assertion mode PDL_BSC_PAGE_WRITE_DISABLE or PDL_BSC_PAGE_WRITE_ENABLE Disable or enable page write accesses data3 The number of read recovery cycles RRCV Valid between 0 and 15 data4 The number of write recovery cycles WRCV Valid between 0 and 15 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 134 of 487 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference data5 The number of wait cycles used for second and subsequent accesses during a page read sequence CSPRWAIT Valid between 0 and 7 data6 The number of wait cycles used for second and subsequent accesses during a page write sequence CSPWWAIT Valid between 0 and 7
143. n 1 Valid for n 1 TCNT counter clock edge selection Valid for n 0 to 4 Not effective for n 1 and 2 in Phase Counting Mode PDL_MTU2_CLK_RISING or PDL_MTU2_CLK_FALLING or PDL_MTU2_CLK_BOTH The TCNT counter clock signal shall be counted on rising falling or both edges TCNT counter clearing Valid for n 0 to 4 unless stated otherwise PDL_MTU2_CLEAR_DISABLE or Clearing is disabled PDL_MTU2 CLEAR TGRA or Cleared by TGRA compare match or input capture PDL_MTU2_CLEAR_TGRB or Cleared by TGRB compare match or input capture PDL_MTU2_CLEAR_SYNC Cleared by counter clearing on another channel configured for synchronous operation Cleared by TGRC compare match or input capture Valid for n 0 3 and 4 Cleared by TGRD compare match or input capture Valid for n 0 3 and 4 PDL_MTU2_CLEAR_TGRC or PDL_MTU2_CLEAR_TGRD R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 178 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 3 9 e Counter clock source selection Valid for n 5 PDL_MTU2_CLKU_PCLK_DIV_1 or PDL_MTU2_CLKU_PCLK_DIV_4 or PDL_MTU2_CLKU_PCLK_DIV_16 or PDL_MTU2_CLKU_PCLK DIV_64 Counter TCNTU is supplied by the internal clock signal PCLKB 1 4 16 or 64 PDL_MTU2_CLKV_PCLK_DIV_1 or PDL_MTU2_CLKV_PCLK_DIV_4 or PDL_MTU2_CLKV_PCLK_DIV_16 or PDL MTU2 CLKV_PCLK DIV 64 PDL_MTU2_CLKW_PCLK_DIV_1 or PDL_MTU2_CLKW_PCLK_DIV_4 or PDL_MTU2_CLKW_
144. of 487 Jul 19 2012 RX63N Group 4 Library Reference Reference Remarks Program example e The validity of the digital filter division when 2 3 or 4 is selected is not checked RPDL definitions include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h void func void Change the IEBus mode to 1 and the unit address to 078h R_IEB_Control 0 PDL_IEB_MODE_1 PDL_IEB_UPDATE_ADDRESS 0x0078 R20UT1963EE0100 Rev 1 00 az Page 349 of 487 Jul 19 2012 2 XENESAS RX63N Group 4 Library Reference 9 R_IEB_GetStatus Synopsis Prototype Description 1 2 Check the status of an IEBus channel bool R_IEB_GetStatus uint8_t data1 uint16_t data2 uint8_t data3 uint32_t data4 uint16_t data5 uint16_t data6 3 Channel selection General status flags Transmit status flags II Receive status flags Unit address Unit address Acquires the IEBus channel status data1 Select channel n where n 0 only data2 The General status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b15 b11 b10 b8 0 The division applied to the IECLK clock signal b7 b6 b4 I
145. of channel 0 R_IEB_Get Status 0 R20UT1963EE0100 Rev 1 00 Page 475 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Read the Transmit status of channel 0 R_IEB_GetStatus 0 PDL_NO_PTR amp Tx_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR Slave transmission complete Tx_status amp BIT_5 0 Prepare new data to be sent R_IEB_SlaveWrite 0 const uint8_t iebus_tx_data_b uint8_t strlen iebus_tx_data_b Are any error flags set if Tx_status amp 0x0F 0 Rx_status amp 0x1F 0 Read the General status of channel 0 R_IEB_GetStatus 0 amp General_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR Use General_status Tx_status and Rx_status to handle the error while 1 Figure 5 52 Example of IEBus Slave use using polling R20UT1963EE0100 Rev 1 00 Page 476 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 20 3 Slave operation using interrupts Figure 5 53 shows how a slave unit checks for data to be received from or sent to a master unit Peripheral driver function prototypes include r_pdl_ieb h include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h include lt string h gt volatile bool ieb_error volatile uint8_t iebus_rx_data 32 volatile uint8_t ieb
146. or PDL_EXDMAC_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when an event specified in the Interrupt generation options occurs data5 The source start address data6 The destination start address data7 The number of transfers to take place For normal mode valid between 0 and 65535 0 free running mode For repeat block and cluster mode valid between 0 and 1023 0 1024 transfers data8 The repeat block or cluster size for each transfer For repeat and block mode valid between 0 and 1023 units 0 1024 transfers For cluster mode valid between 0 and 7 units 0 8 units Ignored in normal mode data9 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected data10 The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if the extended repeat function is not required for the source address R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 157 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 3 3 Return value Category Reference Remarks Program example data11 The destination address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if the extended repeat function is not required for the destination address
147. phase outputs can be controlled together by selecting one of each All P phase outputs PDL_MTU2_OUT_N_PHASE_ALL_ENABLE or PDL_MTU2_OUT_N_PHASE_ALL_DISABLE All N phase outputs e Output inversion control applies only to reset synchr Each phase output can be configured for a initial high level active low level or b initial low level active high level onised or complementary PWM modes If dead time is not generated the options for negative phases will be ignored as their output are always the inversion of the positive phases All six phase outputs can be controlled together by s electing one of each PDL_MTU2_OUT_P_PHASE_ALL_HIGH_LOW or PDL_MTU2_OUT_P_PHASE_ALL_LOW_HIGH Positive phase outputs PDL_MTU2_OUT_N_PHASE_ALL_HIGH_LOW or PDL_MTU2_OUT_N_PHASE_ALL_LOW_HIGH Or independently by selecting one option for each required output Negative phase outputs PDL_MTU2_OUT_P_PHASE_1_HIGH LOWor MTIOC3B PDL_MTU2_OUT_P_PHASE_1_LOW_HIGH PDL_MTU2_OUT_N_PHASE_1_HIGH LOWor yrtigg3p PDL_MTU2_OUT_N PHASE_1 LOW_HIGH PDL_MTU2_OUT_P_PHASE 2 HIGH LOWor MTIOC4A PDL_MTU2_OUT_P_PHASE 2 LOW_HIGH PDL_MTU2_OUT_N_PHASE_2 HIGH LOWor yrtiggac PDL_MTU2_OUT_N PHASE 2 LOW HIGH PDL_MTU2_OUT_P_PHASE_3 HIGH LOWor MTIOC4B PDL _MTU2 OUT P PHASE 3 LOW_HIGH PDL_MTU2_OUT_N_PHASE_3 HIGH LOWor yTiocaD P
148. pin input Valid for n 0 2 4 and 5 PDL_TPU_CLK_TCLKD or TCLKD pin input Valid for n 0 and 5 PDL_TPU_CLK_TCLKE or TCLKE pin input Valid for n 6 to 11 PDL_TPU_CLK_TCLKF or TCLKF pin input Valid for n 6 7 and 8 PDL_TPU_CLK_TCLKG or TCLKG pin input Valid for n 6 8 10 and 11 PDL_TPU_CLK_TCLKH or TCLKH pin input Valid for n 6 and 11 The overflow underflow signal from TPU n 1 PDL TPU CLK_TPU Valid for n 1 4 7 and 10 Counter clock edge selection PDL_TPU_CLK_FALLING or PDL_TPU_CLK_RISING or PDL_TPU_CLK_ BOTH The clock signal shall be counted on falling rising or both edges Counter clearing PDL_TPU_CLEAR_DISABLE or Clearing is disabled PDL_TPU_CLEAR_CM_Aor Cleared after a TGRA compare match occurs PDL_TPU_CLEAR_CM_B or Cleared after a TGRB compare match occurs Cleared after a TGRC compare match occurs Valid for n 0 3 6 and 9 Cleared after a TGRD compare match occurs Valid for n 0 3 6 and 9 Cleared by counter clearing on another channel configured for synchronous operation PDL_TPU_CLEAR_CM_C or PDL_TPU_CLEAR_CM_D or PDL_TPU_CLEAR_CM_SYNC R20UT1963EE0100 Rev 1 00 R AS Page 211 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Description 3 5 Buffer operation valid for channels 0 3 6 and 9 PDL_TPU_BUFFER_AC_DISABLE or PDL_TPU_BUFFER_AC_ENABLE Disable or enable buffer operation
149. processor modes supervisor and user The API driver functions may be executed by the CPU in either mode However any callback functions which are called by the API interrupt handlers will always be executed by the CPU in supervisor mode This means that the privileged CPU instructions RTFI RTE and WAIT can be executed by the callback function and any function that is called by the callback function The user must 1 Avoid using the RTFI and RTE instructions These instructions are issued by the API interrupt handlers so there should be no need for the user s code to use these instructions 2 Use the wait intrinsic function with caution This instruction is used by some API functions as part of power management so there should be no need for the user s code to use this instruction More information on the processor modes can be found in 1 4 of the RX Family software manual 6 2 Interrupts and DSP instructions The accumulator ACC register is modified by the following instructions i DSP MACHI MACLO MULHI MULLO MVTACHI MVTACLO and RACW ii Multiply and multiply and accumulate EMUL EMULU FMUL MUL and RMPA The accumulator ACC register is not pushed onto the stack by the API interrupt handlers If DSP instructions are being utilised in the users code callback functions which are called by the API interrupt handlers should either a Avoid using instructions which modify the ACC register b Take aco
150. results If the ADC unit s control registers are directly modified by the user this function may lock up Program example RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t ADCresult 2 Read the ADC values for unit 0 R_ADC_10_Read 0 ADCresult R20UT1963EE0100 Rev 1 00 R AS Page 371 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 4 2 30 10 bit Digital to Analog Converter 1 R_DAC_10 Create Synopsis Prototype Description Configure the 10 bit DAC module bool R_DAC_10_Create uint8_t data1 Configuration uinti6 tdata2 Output value uint16_tdata3 Output value Enable the DAC module and set the operating conditions data1 Configuration options To set multiple options at the same time use to separate each value The default settings are shown in bold Channel enable PDL_DAC_10_CHANNEL_0 Enable channel 0 PDL_DAC_10 CHANNEL 1 Enable channel 1 e Data alignment selection The alignment of the 10 bit output data within the 16 bit PDL_DAC_10_ALIGN_LEFT or parameters data2 and data3 PDL_DAC_10_ALIGN_RIGHT Left padded at the MSB end Right padded at the LSB end e D AAID Synchronous Start Control PDL_DAC_10_ADC_SYNC_CONV_DISABLE or Disable or enable the D
151. selected it must be an integer of the IECLK 6 0 or 6 29375 for the VGA type e If automatic calculation of the module clock division is selected a tolerance of 1 5 is used when checking the IECLK frequency RPDL definitions include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h void func void Configure I R_IEB_Create EBus channel 0 0 PDL_IEB_MODE_0 PDL_IEB_POLARITY_HIGH 0x0123 15 R20UT1963EE0100 Rev 1 00 REN ESAS Page 340 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_IEB_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shutdown an IEBus channel bool R_IEB_Destroy uint8_t data Channel selection Shutdown the selected IEBus channel data Select channel n where n 0 only True if all parameters are valid otherwise false IEBus None e The IEBus module is put into the power down state RPDL definitions include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown IEB channel 0 R_IEB_Destroy 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 341 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_IEB_MasterSend Synopsis
152. source data7 Configure the Capture 2 RTCIC2 pin options To set multiple options at the same time use to separate each value The default settings are shown in bold Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or Select the edge that will trigger a capture PDL_RTC_CAPTURE_EDGE_FALLING or event PDL_RTC_CAPTURE_EDGE_BOTH e Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or Configure the capture noise filter If PDL_RTC_CAPTURE_FILTER_ON_DIV_1 or enabling select the sampling period relative PDL_RTC_CAPTURE_FILTER_ON_DIV_32 to the count source data8 Configure the clock periodic interrupt The default setting is shown in bold e Periodic interrupt selection PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256_HZ or PDL_RTC_PERIODIC_128_ HZ or PDL_RTC_PERIODIC_64_HZ or PDL_RTC_PERIODIC_32_HZ or PDL_RTC_PERIODIC_16_HZ or PDL_RTC_PERIODIC_8_HZ or PDL_RTC_PERIODIC_4 HZ or PDL_RTC_PERIODIC_2_HZ or PDL_RTC_PERIODIC_1_HZ or PDL_RTC_PERIODIC_2S The frequency or interval for periodic interrupt requests When main clock is selected as count source PDL_RTC_PERIODIC_256_HZ is generated every 1 128 second data9 The alarm day of the week and time in hours minutes and seconds BCD format is used If not required specify PDL_NO_DATA The format is dependent upon if using 12 hour or 24 hour mode 24 Hour Mode
153. start with a re start rather than the default behaviour of a start condition Stop Condition selection By default the transfer will end with a stop condition PDL_SCI_IIC_NOSTOP Select this option to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address data4 The number of data bytes that must be transferred before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The start address of the buffer that will receive the data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 301 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Polling PDL_NO_FUNC This function will continue until the required number of bytes has been transferred or an error occurs The function to be called when the transfer has completed or an error Return value Category Reference Interrupts detected Ei
154. status flag data1 The channel number n where n 0 1 2 or 3 data2 The compare match status flag shall be stored in the following format Specify PDL_NO_PTR if the flag is not to be read b7 b1 bO 0 0 Idle 1 Compare match condition detected data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid otherwise false Compare Match Timer R_CMT_Create Remarks Program example e Ifthe flag is read and is set to 1 it shall be automatically cleared to 0 by this function RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uintl6_t Counter void func void Read the channel 2 values R_CMT_Read 2 amp Flags amp Counter R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 257 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 2 20 Real time Clock 1 R_RTC_Create Synopsis Prototype Description 1 4 Configure the Real time clock bool R_RTC_Creaite uint32_t data1 Configuration selection uint8_t data2 Pin selection uint32_t data3 Current time uint32_t data4 Current date uint8_t data5 Capture 0 configuration uint8_t data6 II Capture 1 configuration uint8_t data7 Capture 2 configuration uint16_t data8 Periodic configurat
155. status of the Port Output Enable module 1 R_TPU_Set Configure the Timer Pulse Unit pins 46 bit Timer 2 R_TPU_Create Configure a Timer Pulse Unit channel Pulse Unit 3 R_TPU_Destroy Disable a timer unit 4 R_TPU_Control Control a timer channel 5 R_TPU_Read Read from timer channel registers Programmable 1 R_PPG_Create Configure a PPG group P ls Generator 2 R_PPG_Destroy Disable PPG outputs 3 R_PPG_ Control Control a PPG group 1 R_TMR_Set Configure the optional TMR pins 2 R_TMR_CreateChannel Configure a TMR timer channel 3 R_TMR_CreateUnit Configure a TMR timer unit 4 R_TMR_CreatePeriodic Select periodic operation 5 R_TMR_CreateOneShot Configure and use a one shot timer 8 bit Timer 6 R_TMR_Destroy Disable a TMR timer unit 7 R_TMR_ControlChannel Write to timer channel registers 8 R_TMR_ControlUnit Write to timer unit registers 9 R_TMR_ControlPeriodic Control periodic operation 10 R_TMR_ReadChannel Read from timer channel registers 11 R_TMR_ReadUnit Read from timer unit registers 1 R_CMT_Create Configure a CMT channel Compare Match 2 R_CMT_CreateOneShot Configure a CMT channel as a one shot event Timer 3 R_CMT_Destroy Disable a CMT unit 4 R_CMT_Control Control CMT operation 5 R_CMT_Read Read CMT channel status and registers 1 R_RTC_Create Configure the Real time clock 2 R_RTC_Destroy Shut down the Real time clock Real time Clock 3 R_RTC_Control Modify the Real time clock operation 4 R RTC Read Read
156. uint16_t strlen master_data_to_be_sent PDL_NO_FUNC 0 PDL_NO_FUNC 0 while slave_transfer_complete false R20UT1963EE0100 Rev 1 00 Page 465 of 487 Jul 19 2012 RENESAS RX63N Group for i 0 i lt strlen master_data_to_be_sent i Did the Master output match the Slave input if master_data_to_be_sent i uint8_t slave_rx_data i while 1 Did the Master input match the Slave output if uint8_t master_rx_data i slave_data_to_be_sent i while 1 void spi_slave_callback void uint16_t StatusValue 0 uint16_t Sequence_count Read the slave channel status R SPI GetStatus SLAVE_CHANNEL amp StatusValue amp Sequence_count i No errors if StatusValue amp 0x000Du 0x0u slave_transfer_complete true else while 1 Figure 5 49 Example of Serial Peripheral Interface use 5 Usage Examples R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 466 of 487 RX63N Group 5 Usage Examples 5 19 3 Master operation with multiple slaves This is an example of Serial Peripheral Interface usage where one SPI master communicates with four SPI slaves Each slave requires different data bit lengths RSPCKB A SPI channel 0 MOSIB A MISOB A Master SSLBO A SSLB1 A SSLB2 A SSLB3 A Slave 0 8 bit data words Slave 1 9 bit data words Slave 2 15 bit data words 7
157. void func void Configure the applicable SPI pins R_SPI_Set 0 PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSIA_PA6 PDL_SPI_MISOA_PA7 PDL_SPI_SSLAO_PA4 PDL_SPI_SSLA1_PAO PDL_SPI_SSLA2_PA1 PDL_SPI_SSLA3_PA2 PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 326 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_SPI_Create Synopsis Configure an SPI channel Prototype bool R_SPI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Data format uint32_t data4 Extended timing control uint32_t data5 Bit rate or register value Description 1 3 Set up the selected SPI channel data1 Select channel SPIn where n 0 1 or 2 data2 Configure the channel mode and connection settings If multiple selections are required use to separate each selection The default settings are shown in bold Connection mode PDL_SPI_MODE_SPI_MASTER or PDL_SPI_MODE_SPI_MULTI_MASTER or The required SPI four wire or Clock PDL_SPI_MODE_SPI_SLAVE or synchronous three wire operation PDL_SPI_MODE_SYNC_MASTER or connection type PDL_SPI_MODE_SYNC_SLAVE e Reception control PDL_SPI_FULL_DUPLEX or Enabl disabl ti ti PDL_SPI TRANSMIT_ONLY nable or disable reception operations e Pin control If output signal SSLx where x 0 1 2 or 3 is used call
158. window a Set the optimisation To avoid linking unused RPDL functions adjust the Compiler and Linker settings i Compiler Select the C C tab Use the key sequence Y O O to show the optimisation options Ensure that the Inter module optimization option is enabled RX Standard Toolchain Configuration C C Assembly Link Library Standard Library RTOS 4 gt Debug_AX600_E1_E20_5YSTE v Category M All Loaded Projects z E Optimize level C source file 2 Details C source file Assembly source file Speed or size Linkage symbol file Optimize for size V Inter module optimization 0 external variables Options C C cpu rx600 endian big dbl_size 8 patch rx610 include PROJDIR SAPDL include PROJDIR output obj CONFIGDIR S FILELEAF obi debug R20UT1963EE0100 Rev 1 00 a2 AS Page 11 of 487 Jul 19 2012 SENES RX63N Group 1 Introduction ii Linker Select the Link Library tab Use the key sequence Y O O to show the optimisation options If the Eliminate dead code option is not enabled from the Optimize drop down list select Custom and enable the option RX Standard Toolchain Configuration C C Assembly Link Library Standard Library ATos4 gt Debug_RX600_E1_E20_SYSTE 7 ELE E All Loaded Projects a Show entries for E C source file Optimize items C source file Assembly s
159. written to the I O port or port pin Write data to an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 e One port definition or One port pin definition data2 The value must be between 0x00 and OxFF for a port O or 1 for a pin True if the parameters are valid otherwise false I O port None e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the output of port pin P05 R_IO_PORT_Write PDL_IO_PORT_0_5 0 i Set the output of port 6 R_IO_PORT_Write PDL_IO_PORT_6 0x55 i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 97 of 487 Jul 19 2012 RX63N Group 4 Library Reference 6 R_l1O_PORT_Compare Synopsis Prototype Description Return value Check the pin states on an I O port bool R_IO_PORT_Compare uint16_t data1 Input port or port pin selection uint8_t data2 Comparison value void func Function pointer Read the input state of an I O port or I O port pin and call a function if a match occurs data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value to be compared with Between 0x00 and
160. 0 Figure 5 47 Virtual IIC Slave memory R20UT1963EE0100 Rev 1 00 Page 460 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 19 Serial Peripheral Interface 5 19 1 Using one slave 1 This is an example of Serial Peripheral Interface usage where one SPI master communicates with one SPI slave The RSK evaluation board is used to connect the two SPI channels together RSPCKB A SPI channel 1 MOSIB A master MISOB A SSLBO A RX63N MCU SSLAO A SPI channel 0 MISOA A slave MOSIA A RSPCKA A Figure 5 48 shows how four 32 bit words are transmitted and received simultaneously by the master and slave The received data is then checked to confirm that the transfer was successful Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_spi h PDL device specific definitions include r_pdl_definitions h void spi_slave_callback void volatile bool slave_transfer_complete define SLAVE_CHANNEL 0 define MASTER_CHANNEL 1 void main void const uint32_t master_0_tx_data 4 0x00000001 0x98765432 OxABCDEF34 0x12345678 uint32_t master_0_rx_data 4 0x00000000 0x00000000 0x00000000 0x00000000 const uint32_t slave_0_tx_data 4 0x32323232 0x3456789A OxDEADBEEF OxFEEDCEDE R20UT1963EE0100 Rev 1 00 az AS Page 461 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples uin
161. 00 1 0 Send message register callback to say when sent R_SCI_Send 0 PDL_NO_DATA r nHello Type 5 characters and I will echo them back r n 0 SCItx i Wait for message to be sent while false data_sent Start a pending read of 5 characters R_SCI_Receive 0 PDL_NO_DATA rx_buffer R20UT1963EE0100 Rev 1 00 Page 425 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 SCIrx PDL_NO_FUNC i Wait for characters to be received while false data_received Echo the 5 characters back R_SCI_Send 0 PDL_NO_DATA rx_buffer 5 PDL_NO_FUNC 3 Callback function for Rx void SCIrx void data_received true Callback function for Tx void SCItx void data_sent true Figure 5 28 Example of SCI Asynchronous operation using interrupts R20UT1963EE0100 Rev 1 00 Page 426 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 17 3 SCI Asynchronous Using DMAC This shows the setting of SCI channel 0 and transmission of data using the DMAC Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h include lt stddef h gt include lt string h gt const uint8_t string Hello from Renesas RX63N SCI DMAC r n void main void uint8_t SCI_statu
162. 00 Rev 1 00 Jul 19 2012 2tENESAS Page 331 of 487 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example data4 Extended timing control If multiple selections are required use to separate each selection The default settings are shown in bold For Slave mode select PDL_NO_DATA e Extended timing selection SSL negation delay PDL_SPI_CLOCK_DELAY_MINIMUM or PDL_SPI_CLOCK_DELAY_EXTENDED Select the minimum or extended delay between the assertion of the SSL pin and the start of RSPCK oscillation Next access delay PDL_SPI_SSL_DELAY_MINIMUM or PDL_SPI_SSL_DELAY_EXTENDED Select the minimum or extended delay between the end of RSPCK oscillation and the negation of the active SSL pin PDL_SPI_NEXT_DELAY_MINIMUM or PDL_SPI_NEXT_DELAY_EXTENDED frame Select the minimum or extended delay between the end of one frame and the start of the next True if all parameters are valid otherwise false SPI R_SPI_Create For Slave mode operation configure command 0 e When Clock synchronous Slave mode is used avoid selecting mode 0 or mode 2 e If parity is enabled while in Master mode both the frame data length and data transfer format should be the same for each command e Channel 2 is not available for 100 pin package RPDL definitions include r_pdl_spi h
163. 012 2tENESAS Page 90 of 487 RX63N Group 4 Library Reference 1 RIO PORT Set Synopsis Configure an I O port Prototype bool R_IO_PORT_Sei uint16_tdata1 Port pin selection uint16_t data2 Configuration Description Set the operating conditions for I O port pins data1 Select the port pins to be configured from 4 2 3 Do not use any whole port definitions Multiple pins on the same port may be specified using to separate each pin data2 Choose the pin settings Use to separate each selection Each selection is optional If a selection is not made the control setting will be left unchanged e Direction control PDL_IO_PORT_INPUT or PDL IO PORT OUTPUT Input or output e Output type control PDL_IO_PORT_TYPE_CMOS or Select CMOS push pull output Available on all PDL_IO_PORT_TYPE_NMOS or N channel open drain ins PDL_IO_PORT_TYPE_PMOS or P channel open drain or Available on pin PDL_IO_PORT_TYPE_HI_Z high impedance PE 1 only e Input pull up resistor control PDL_IO_PORT_PULL_UP_ON or PDL_IO_PORT_PULL_UP_OFF On or off e Drive capacity control PDL_IO_PORT_DRIVE_NORMAL or Normal or high current drive PDL_IO_PORT_DRIVE_HIGH Valid for ports 0 2 5 to 7 9 to E and G Return value True if all parameters are valid and exclusive otherwise false Category 1 Oport References
164. 012 RX63N Group 4 Library Reference Program example RPDI include RPDI L definitions r pdl_exdmac h L device specific definitions include r_pdl_definitions h void func void uint8_t StatusValue uint32_t SourceAddr the status and current source address for channel 1 R20UT1963EE0100 Rev 1 00 Jul 19 2012 Read R_EXDMAC_GetStatus 1 amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR 2tENESAS Page 163 of 487 RX63N Group 4 Library Reference 4 2 13 1 R DTC Set Data Transfer Controller Synopsis Prototype Description Return value Category Reference Remarks Program example Set the Data Transfer Controller options bool R_DTC_Set uint8_t data1 II Configuration options uint32_t data2 Vector table base address Set the global options for the Data Transfer Controller data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Read skip control PDL_DTC_READ_SKIP_DISABLE or Disable or enable skipping of transfer data read PDL_DTC_READ_SKIP_ENABLE when the vector numbers match Address size control PDL_DTC_ADDRESS_FULL or PDL_DTC_ADDRESS_SHORT Select 32 bit
165. 0UT1963EE0100 Rev 1 00 AS Page 386 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 5 Frequency Measurement Circuit 5 5 1 Using System 1 Figure 5 5 shows an example of using MCK system 1 and the MTU module to monitor the low speed on chip oscillator LOCO by comparing it with the main clock oscillator Peripheral driver function prototypes include r_pdl_mck h include r_pdl_cgc h include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h Callback function static void Read_the_MCK void volatile bool mck_completed volatile uintl6_t system_clock_count define EXPECTED_F_MAIN 12E6 define EXPECTED_F_LOCO 125E3 void main void uintl6_t reference_count double f_system_clock double f_reference_clock volatile double measured_frequency MTU parameters that are structures R_MTU2_Create_structure mtu_create_parameters R_MTU2_ControlChannel_structure mtu_control_parameters Configure the LOCO settings R_CGC_Set PDL_CGC_CLK_LOCO PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABLI EXPEC LOCO EXPEC LOCO EXPEC _ LOCO EXPEC OCO EXPECTED OCO PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Configure main clock operation R_CGC_Set PDL _CGC_CLK_MAIN PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABLI EXPECTED _F_ MAIN EXPECTED _F_
166. 1 or 2 Phase counting mode 1 2 3 or 4 Valid for n 1 2 4 5 7 8 10 and 11 e Synchronous mode PDL_TPU_SYNC_DISABLE or PDL_TPU_SYNC_ENABLE Disable or enable synchronous operation Noise Filter for TIOCA PDL_TPU_TIOCA_NF_DISABLE or PDL_TPU_TIOCA_NF_ENABLE Disable or enable noise filter for TIOCA e Noise Filter for TIOCB PDL_TPU_TIOCB_NF_DISABLE or PDL_TPU_TIOCB_NF_ENABLE Disable or enable noise filter for TIOCB e Noise Filter for TIOCC valid for n 0 3 6 and 9 PDL_TPU_TIOCC_NF_DISABLE or PDL TPU TIOCC NF ENABLE Disable or enable noise filter for TIOCC Noise Filter for TIOCD valid for n 0 3 6 and 9 PDL_TPU_TIOCD_NF_DISABLE or PDL_TPU_TIOCD NF ENABLE Disable or enable noise filter for TIOCD R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 210 of 487 RX63N Group 4 Library Reference Description 2 5 e Noise filter clock select PDL_TPU_NF_CLK_PCLK_DIV_1 or PDL TPU NF CLK PCLK DIV 8 or The noise filter clock signal PCLK 1 8 32 or the PDL_TPU_NF_CLK_PCLK_DIV_32 or same as the TPU counting clock PDL_TPU_NF_CLK_COUNTING e DMAC and or DTC trigger control for TGRA PDL_TPU_TGRA_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_TPU_TGRA_DMAC_TRIGGER_ENABLE or the DMAC or DTC when a PDL_TPU_TGRA_DTC_TRIGGER_ENABLE TGRA compare match occurs e DTC
167. 131072 or PDL_LPC_MAIN_262144 or PDL_LPC_MAIN_524288 mode stopped Select the oscillation settling time of the main clock oscillator before the CPU resumes after exiting from software standby When updating this value the main clock oscillator must be R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 119 of 487 RX63N Group 4 Library Reference Description 4 4 Return value Category References data6 Select the sub clock oscillator waiting times If no selections are required specify PDL_NO_DATA e Deep Software Standby waiting time PDL_LPC_SUB_2 or PDL_LPC_SUB 4 or PDL_LPC_SUB_8 or PDL_LPC_SUB_16 or PDL_LPC_SUB_32 or PDL_LPC_SUB_64 or PDL_LPC_SUB_512 or PDL LPC SUB 1024 or PDL LPC SUB 2048 or PDL LPC SUB 4096 or PDL_LPC_SUB_ 16384 or PDL_LPC_SUB_32768 or PDL_LPC_SUB_65536 or PDL_LPC_SUB_524288 data7 Select the PLL waiting times PDL_LPC_SUB_ 131072 or PDL_LPC_SUB_262144 or Select the oscillation settling time of the sub clock oscillator before the CPU resumes after exiting from software standby mode When updating this value the sub clock oscillator must be stopped If no selections are required specify PDL_NO_DATA e Deep Software Standby waiting time PDL_LPC_PLL_16 or PDL_LPC_PLL_32 or PDL_LPC_PLL_64 or PDL_LPC_PLL_512 or PDL_LPC_PLL_1024 or PDL_LPC_PLL_2048 or PDL_LPC_PLL_4096 or PDL_LPC_PLL_16384
168. 19 2012 RENES RX63N Group 4 Library Reference 6 R_SCI_SPI_ Transfer Synopsis Perform an SPI transfer on an SCI channel Prototype bool R_SCI_SPI_Transfer uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Number of bytes to transfer uint8_t data4 Data transmit buffer void func Callback function Transmit Done uint8_t data5 Data receive buffer void func2 Callback function Receive Done void func3 II Callback function Error Description 1 2 Perform an SPI transfer This may be sending receiving or both sending and receiving data data1 Select channel SCIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_SPI_TX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_TX_DMAC_TRIGGER_ENABLE or the DMAC or DTC when a PDL_SCI_SPI_TX_DTC_TRIGGER_ENABLE data byte is transmitted e DMAC DTC trigger control PDL_SCI_SPI_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_RX_DMAC_TRIGGER_ENABLE or the DMAC or DTC when a PDL_SCI_SPI_RX_DTC_TRIGGER_ENABLE data byte is received data3 The number of bytes that must be transferred either transmitted received or both before the function completes or the callback function is called If the DMAC o
169. 19 2012 RENESAS RX63N Group SLAVE_CHANNEL PDL_NO_DATA slave_0O_tx_data slave_0O_rx_data 1 spi_slave_callback L5 PDL_NO_FUNC 0 slave_transfer_complete false Transfer all the data once R_SPI_Transfer MASTER_CHANNEL PDL _NO_DATA master_0O_tx_data master_0O_rx_data 1 PDL_NO_FUNC 0 PDL_NO_FUNC 0 while slave_transfer_complete false for i 0 i lt 4 i Did the Master output match the Slave input if master_0_tx_data i slave_0_rx_data i Handle the error Did the Master input match the Slave output if master_O_rx_data i slave_0_tx_data i Handle the error void spi_slave_callback void uintl6_t uintl6_t Read R_SPI_Ge StatusValue 0 Sequence_count the slave channel status tStatus SLAVE_CHANNEL amp Sta amp Seq No er if Sta slav else H tusValue uence_count rors tusValue amp 0x000Du 0x0u e_transfer_complete true andle the error 5 Usage Examples Figure 5 48 Example of Serial Peripheral Interface use R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 463 of 487 RX63N Group 5 Usage Examples 5 19 2 Using one slave 2 Figure 5 49 shows how strings of 8 bit data are copied into 32 bit buffers then transmitted and received simu
170. 1963EE0100 Rev 1 00 Page 329 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 3 R_SPI_Desitroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shutdown an SPI channel bool R_SPI_Destroy uint8_t data Channel selection Shutdown the selected SPI channel data Select channel SPIn where n 0 1 or 2 True if all parameters are valid otherwise false SPI None The SPI channel is put into the power down state e Channel 2 is not available for 100 pin package RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SPI channel 0 R_SPI_Destroy 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 330 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_SPI_Command Synopsis Prototype Description 1 2 Configure an SPI command bool R_SPIl_Command uint8_t data1 uint8_t data2 uint32_t data3 uint8_t data4 Select the options for a command data1 Channel selection Command selection Command options Extended timing control Select channel SPIn where n 0 1 or 2 data2 Select command n where n 0 to 7 data3 Select the command options If multiple selections are require
171. 2 RX63N Group 4 Library Reference Description 2 2 PDL_PPG_PO24_PIN_PBO or PDL_PPG_PO24 PIN _PC3 PDL_PPG_PO25_PIN_PB1 or PDL_PPG_PO25 PIN PC4 PDL_PPG_PO26_PIN_P80 or PDL_PPG_PO26_PIN_PB2 or PDL_PPG_PO26_PIN_PE3 PDL_PPG_PO27_PIN_P81 or PDL_PPG_PO27_PIN_PB3 Group 6 PDL_PPG_PO28_PIN_P82 or PDL_PPG_PO28_PIN_PB4 or PDL_PPG_PO28_ PIN PE4 PDL_PPG_PO29_PIN_PB5 or PDL_PPG_PO29 PIN _PC5 PDL_PPG_PO30_PIN_PB6 or PDL_PPG_PO30_PIN_PC6 PDL_PPG_PO31_PIN_PB7 or PDL_PPG_PO31_PIN_PC7 data2 Operation control Group 7 Unit 1 If multiple selections are required use to separate each selection e Output trigger selection PDL_PPG_TRIGGER_MTUO or PDL_PPG_TRIGGER_MTU1 or PDL_PPG_TRIGGER_MTU2 or PDL_PPG_TRIGGER_MTU3 or PDL_PPG_TRIGGER_TPUO or PDL_PPG_TRIGGER_TPU1 or PDL_PPG_TRIGGER_TPU2 or PDL_PPG_TRIGGER_TPU3 Select Compare Match on MTU channel 0 to 3 as the output trigger Select Compare Match on TPU channel 0 to 3 as the output trigger valid only for groups 4 to 7 e Non overlap control PDL_PPG_NORMAL or PDL_PPG NON OVERLAP Select overlapping Compare Match A or non overlapping Compare Match A or B operation e Invert control PDL_PPG_DIRECT or PDL_PPG_INVERT Select direct or inverted output
172. 2 The function to be called if an error occurs Specify PDL_NO_FUNC to ignore errors R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 333 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example data7 The interrupt priority level for error detection Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 Use the same error interrupt priority level as R_SCI_Create parameter data5 True if all parameters are valid otherwise false SPI R_SPI_Create The amount of data for must match the total number of transfer frames refer to parameter data3 in R_SPI_Create If a callback function is specified and DMAC DTC control is not used interrupts are used to handle the data transfer Please see the notes on callback function usage in 6 If an error interrupt function is specified for parameter func 2 while PDL_NO_FUNC is specified for parameter func 1 the error flag is polled without using an interrupt and the error interrupt function will be called when an error occurs After using this function use R_SPI_GetStatus to check for and clear any error flags Channel 2 is not available for 100 pin package RPDL definitions include r_pdl_spi h RPDL device specific definitions i
173. 2 PIN 3A PC7 PDL_MTU2_PIN_3B_P17 or PDL_MTU2_PIN_3B_P22 or PDL_MTU2_PIN_3B_P80 or Select the P17 P22 P80 PB7 or PC5 pin for MTIOC3B PDL_MTU2_PIN_3B_PB7 or PDL_MTU2_PIN 3B _PC5 PDL_MTU2_PIN_3C_P16 or PDL_MTU2_PIN_3C_P56 or PDL_MTU2_PIN_3C_PCO or Select the P16 P56 PCO PC6 or PJ3 pin for MTIOC3C PDL_MTU2_PIN_3C_PC6 or PDL _MTU2 PIN 3C PJ3 PDL_MTU2_PIN_3D_P16 or PDL_MTU2_PIN_3D_P23 or PDL_MTU2_PIN_3D_P81 or Select the P16 P23 P81 PB6 or PC4 pin for MTIOC3D PDL_MTU2_PIN_3D_PB6 or PDL_MTU2_PIN 3D _PC4 Select the P14 P17 PC1 or PC7 pin for MTIOC3A R20UT1963EE0100 Rev 1 00 R AS Page 174 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Description 2 2 e Valid when n 4 PDL_MTU2_PIN 4A P24 or PDL_MTU2_PIN_3D_P82 or PDL_MTU2_PIN_4A PAO or Select the P24 P82 PAO PB3 or PE2 pin for MTIOC4A PDL_MTU2_PIN_4A_PB3 or PDL_MTU2 PIN 4A PE2 PDL_MTU2_PIN 4B P30 or PDL_MTU2_PIN 4B P54 or PDL_MTU2_PIN 4B _PC2 or Select the P30 P54 PC2 PD1 or PE3 pin for MTIOC4B PDL_MTU2_PIN 4B _PD1 or PDL_MTU2 PIN 4B PE3 PDL_MTU2_PIN 4C_P25 or PDL_MTU2_PIN_4C_P83 or PDL_MTU2_PIN_4C_PB1 or Select the P25 P83 PB1 PE1 or PES pin for MTIOCAC PDL_MTU2_PIN_4C_PE1 or PDL_MTU2 PIN 4C_PE5 PDL_MTU2_PIN 4D_P31 or PDL_MTU2_PIN_4D_P55 or PDL_MTU2_PIN 4D_PC3 or PDL_MTU2_PIN_4D_PD2 or PDL_MTU2 PIN 4D PE4 Select the P31 P55 PC3
174. 2_ControlUnit must be used to start the timers e Ifa callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e Ifthe channel is configured for phase counting mode the counter clock source setting is ignored e If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC If buffer operation is selected for registers TGRB and TGRD input capture output compare is not valid for register TGRD e If synchronous mode is required at least two channels must be enabled for synchronous operation e Acompanion function R_LMTU2_Create_load_defaults can be used to load the default values into the structure If the channel operation mode will be changed ensure that the timer is stopped use R_MTU2_ControlChannel or R_LMTU2_ControlUnit e If noise filter is enabled wait for 2 cycles of the selected noise filter clock before starting the timer use R_MTU2_ControlChannel or RLMTU2_ControlUnit If using Complementary PWM mode with Synchronous Clearing and Waveform Retention enabled then be aware of the cautions specified in the Usage Notes section of the hardware manual RPDL definitions include r_pdl_mtu2 h RPDL d
175. 2stENESAS D D T Z S gt Renesas Peripheral Driver Library User s Manual OO N RX63N Group All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Renesas Electronics www renesas com Rev 1 00 Jul 2012 10 11 12 Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any
176. 32_t data3 Pin selection Set up the global SPI options data1 Select channel SPIn where n 0 1 or 2 data2 Configure the SPI input and output pins for channel 0 Use to separate each selection Settings for RSPCKA MOSIA and MISOA are compulsory if channel 0 is selected Specify PDL_NO_DATA if channel 0 is not selected e Pin selection for channel 0 PDL_SPI_RSPCKA_PAS5 or PDL_SPI_LRSPCKA_PBO or Select the RSPCKA pin PDL_SPI_RSPCKA PC5 PDL_SPI_MOSIA_P16 or PDL_SPI_MOSIA_PA6 or Select the MOSIA pin PDL_SPI_MOSIA_ PC6 PDL_SPI_MISOA_P17 or PDL_SPI_MISOA_PA7 or Select the MISOA pin PDL _SPI_MISOA PC7 PDL_SPI_SSLAO_PA4 or PDL_SPI_SSLAO PC4 PDL_SPI_SSLA1_PAO or PDL_SPI_SSLA1_PCO PDL_SPI_SSLA2_PA 1 or PDL SPI SSLA2 PC1 PDL_SPI_SSLA3_PA2 or PDL_SPI_SSLA3_PC2 Select the SSLAO pin optional Select the SSLA1 pin optional Select the SSLA2 pin optional Select the SSLA3 pin optional data3 Configure the SPI input and output pins for channel 1 and 2 Use to separate each selection Settings for RSPCKB MOSIB and MISOB are compulsory if channel 1 is selected Specify PDL_NO_DATA if channel 1 and 2 are not selected e Pin selection for channel 1 PDL_SPI_RSPCKB_P27 or PDL_SPI_LRSPCKB_PE1 or Select the RSPCKB pin PDL SPI_RSPCKB PE5 PDL_SPI_MOSIB_P26 or PDL_SPI_MOSIB_PE2 or Select the MOSIB pin PDL_SPI_MOSIB_PE6 PDL_SPI_MISOB
177. 392 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 6 Low Power Consumption 5 6 1 Software Standby Mode Figure 5 7 shows an example of entering Software Standby mode through Low Power Consumption control Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_lpc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h static void SWl_handler void void main void Set Switchl SW1 interrupt R_INTC_SetExtInterrupt PDL_INTC_IRQ2_ P32 PDL_NO_DATA Enable the switch SW1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_FALLING SWl_handler 7 Select the default options R_LPC_Create PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA di refer section 1 2 5 of the API manual If the sub clock oscillator will not be used use R_CGC_Control to disable the oscillation circuit for deep Software Standby mode the sub clock oscillator is not fitted MUST call R_CGC_Control once to disable the sub clock oscillation circuit before calling R_LPC_Control R_CGC_Control PDL_NO_DATA PDL_NO_DATA PDL_CGC_SUB_CLOCK_DISABLE Enter software standby mode LPC_Control PDL _LPC_MODE_SOFTWARE_STANDBY Normal execution will resume after switch SW1 is pressed while 1
178. 4 or 4 1 4 PDL_SPI_FRAME_5 or 5 1 5 PDL_SPI_FRAME_6 or 6 1 6 PDL_SPI_FRAME_7 or 7 1 7 PDL_SPI_FRAME_8 8 1 8 Parity bit control PDL_SPI_PARITY_NONE or PDL_SPI_PARITY_EVEN or Disable or enable the addition of the parity bit PDL_SPI_PARITY_ODD data4 Extended timing control optional All items apply only to Master mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA if not required e Extended clock delay PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK_DELAY 8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or PDL_SPI_SSL_DELAY_4 or PDL_SPI_SSL_DELAY_5 or PDL_SPI_SSL_DELAY_6 or PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY 8 The number of bit clock periods between the end of RSPCK oscillation and the negation of the active SSL pin Ignored in Slave mode Extended next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or PDL_SPI_NEXT_DELAY_4 or PDL_SPI_NEXT_DELAY_5 or PDL_SPI_NEXT_DELAY_6 or PDL_SPI_NEXT_DELAY_7 or
179. 5 1 off LED1 1_0 r 0 on LED2 Configure CMT channel 0 for 1kHz operation but not start CMT first R_CMT_ Create 0 PDL_CMT_FREQUENCY PDL_CMT_STOP E3 11 CMTO_handler 7 Configure CMT channel 1 in 0 1sec period and start CMT R_CMT_Create 1 PDL_CMT_PERIOD 1E 1 CMT1_handler 7 Change the frequency to 10kHz R_CMT_Control 0 PDL_CMT_FREQUENCY 10 R_CMT_Read 0 PDL_NO_PTR PDL_NO_PTR R_CMT_Read 1 amp Flags amp Counter Wait for 2sec R_CMT_CreateOneShot 0 PDL_NO_DATA 2 0 PDL_NO_FUNC 0 R_CMT_Control 0 PDL_CMT_START 0 now start CMTO R20UT1963EE0100 Rev 1 00 Page 415 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples R_CMT_Control 1 PDL_CMT_STOP 0 now stop CMT1 while 1 void CMTO_handler void Invert the port pin R_IO_PORT_Modify PDL_IO_PORT_0_5 PDL_IO_PORT_XOR 1 void CMT1_handler void Toggle the LED1 state R_IO_PORT_Modify PDL_IO_PORT_1_0 PDL_IO_PORT_XOR 1 Figure 5 21 Example of Compare Match Timer use R20UT1963EE0100 Rev 1 00 Page 416 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 15 Real time Clock 5 15 1 Enabling the Sub clock using R_CGC_Control Figure 5 22 shows an example of enabling the Sub clock using 4 2 1 2 before using the Real time clock Peripheral driver function prototypes
180. 58 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2012 Renesas Electronics Corporation All rights reserved Colophon 1 1 RX63N Group 2tENESAS Renesas Electronics Corporation R20UT1963EE0100
181. 6 R MCU Control nin e a e a a acide eee lee a eae ited ee eae eae 106 R MCU GetStatuS enau a a deen read e sida tae needed nen a A tia 107 RiMCU ORS rent e es atin ei a a ten A at needed pie Aa E AET 109 Voltage Detection Circuit otera aE e a Ea dad cece A NEA aR 112 ROEM DC Pe ate niseni a ea a eaaa eae s aaae aaa aba a aaan ainai 112 RoLVDe Control ian aa ea e a ee aa a rea a aA A AEE 114 REV D Getstatus itis aenea e aeaa aa aaa aa iae dads daaa aaee 115 Frequency Measurement GiIroUilssia irienner kaini enaa e EaR TEE AEEA AEE RETENE RRE 116 R MOCK Control sia a a aeaa a aaa a aa e a eaaa a ee beets lait 116 Low Power Consumption vic enoii eaea aaaea a a Ea ed peach n Ea raaa a a naian 117 E A Greate E EE A T E A 117 Rik PC CONTON aai na aaea e aae asda e a er ea aAa aaae a a A AAE aR A aed 122 R LPC WriiteBack p asarana aa een techs deans ee a e nee coat r ARa Ara aaaea es eaea aA Taaa a ane es 124 R LPC Re dB ck p eraa aerei anp tea aan aae ees eaaa a Eataa Teea Taaa A Aa AAEE aR TEA ieee 125 RLPC GetStatus en eaaa een hath aaae aae neu a Raa Aa aaaea eaaa aeee aN aaa ate ed 126 Register Write Protection cecccceeseeeeeeeetneeeeeenneeeeeeneeeeeeaeeeeeeaeeeeeeaeeeseeaeeeeeeneeeeeenaeeeeseaas 128 R RW P Control esta 4 ane Ale eet a aele a ates raat cd ne tna ane ete ead 128 R amp RWP GetStatusic222 cele ea ae aa aeea aa aoran a eaten ae sane aa oar eared 129 Bus Controller sarii a e sedate eats a a eee Cada Acne a aaea aAa aA
182. 63N Group 4 Library Reference Description 5 5 func3 The function to be called when a TGRC event occurs Specify PDL_NO_FUNC if not required func4 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required data11 The interrupt priority level for TGRx events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 func3 and func4 func5 The function to be called when an overflow occurs Specify PDL_NO_FUNC if not required func6 The function to be called when an underflow occurs Specify PDL_NO_FUNC if not required data12 The interrupt priority level for overflow or underflow events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for both parameters func5 and func6 Return value True if all parameters are valid and exclusive otherwise false Category Timer Pulse Unit Reference Remarks e If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e Ifthe channel is configured for phase counting mode the counter clock sour
183. 63N Group 4 Library Reference Return value Category Reference Remarks Program example True if all parameters are valid and exclusive otherwise false DMA controller None e If another peripheral will be used to trigger a DMA transfer call this function before calling the Create function for the peripheral Some peripheral channels are not available on some device packages Please check the hardware manual e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Configure DMA channel 2 R_DMAC_Create 2 PDL_DMAC_ NORMAL PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL _DMAC_SIZE_8 PDL _DMAC_TRIGGER_IRQO 0x0000A400 0x0000BB00 10 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 148 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_DMAC_Desiroy Synopsis Prototype Description Disable the DMA controller bool R_DMAC_Destroy uint8_t data II Channel number Shutdown the DMAC module data The channel number n where n 0 to
184. A 330 4 RSP Command aae a Ma stette a eee aaa Eaa aaao a a eaaa cesta aane ie aa eaae 331 5 RSP Transfer i n aaae e aeaea a eae ien adaa aa eaaa oaaae aen aiaa aa 333 6 RSP CONO a a ae ear T tastes aaa a a a a e a aaa aaaea aa eaa ea aeaa aia 335 7 RS CS r i E E AE E E E O E E pbatharaaiae 337 4 220 EBUS COntrole ria ee aaa eaa a naaa r aea Taa a a aaa E a aaa aeaa e ee aa aa aa aD 338 Wi REIEB ES E E EE EE E A E E S A E T 338 2 SA Create EE A EA EA E AE E E beaue daze 339 3h R IEB DOStroy einnar e raer aei RE ARE ELLET SAA AEE RAL LS I A OA R aS 341 4 Ri IEB MasterSend danaa aaee e dane Sea aaa aae aer eaaa E Ea aaae a aaa a ANE aR Aai 342 5 REB M sterR cSi Ve Aaaa eea atana aa ae aak a r ARa Aara aaaea es Aaea aN Taaa aadar nea 344 6 REB Slave Monit t serna aaeeei anp tea aan ee S Conca ates satan eaaa A Aa AAEE arsenite ed 346 7 REB Slav Wnte serenan aa ree aana aaae ne Scand ERa Aa aaaeeeaa aeeoa aA Taaa ade edad 347 8 RalEB Control atre a aa a E vase eee vat aaa Pa Ea Aaa eadar 348 9 RiIEBsGetstatuss ser Aea a ea e aael ra ada aaa da cd dee aaa tee ed Sas oe ae ee shad 350 42 21 CRE CaleulatO tis riae aa a aae eaae a aaaeeeaa atacand lea aenea ee alanis daea aea Sdan 352 1 R CRC Create sner eaaa aa a aaaea ea eaten arate es cd tne aada et Sas E edi 352 2 CROCRG Destop inort aa Giese er nets EE ARES TAR ane ne Geet 353 3 R CRC WING i e Serana cae e a a de adaa aea RaRa A ea aae aR aAa oA E aS R ieda 354 A SE
185. AA D PDL_DAC_10_ ADC _SYNC_CONV_ENABLE synchronous conversion data2 The value to be written to the channel 0 output register Ignored if the channel is not enabled data3 The value to be written to the channel 1 output register Ignored if the channel is not enabled Return value True if all parameters are valid and exclusive otherwise false Category DAC References None Remarks e This function configures the relevant pin of selected channel for DAC operation e This function brings the converter module out of the power down state e Channel 0 is not available on 100 pin package Ifthe D A A D synchronous conversion is enabled the 10 bit ADC should not be shut down as it will halt the D A conversion too e User should ensure that the 10 bit A D converter remains stopped when setting the D A A D synchronous conversion R20UT1963EE0100 Rev 1 00 ae ENESAS Page 372 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Set up DAC channel 1 with default operation mid voltage R_DAC_10_Create PDL_DAC_10_CHANNEL_1 0 1024 2 R20UT1963EE0100 Rev 1 00 AS Page 373 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 2 R_DAC_10_Destroy Synopsis Prototype Description
186. ABLE Disable or enable the NMI signal when the oscillation stop detection interrupt occurs PDL_INTC_WDT_DISABLE or PDL_INTC_WDT_ ENABLE Disable or enable the NMI signal when a WDT underflow interrupt occurs PDL_INTC_IWDT_DISABLE or PDL_INTC_IWDT_ENABLE Disable or enable the NMI signal when an IWDT underflow interrupt occurs PDL_INTC_LVD1_DISABLE or PDL_INTC_LVD1_ENABLE Disable or enable the NMI signal when a low voltage detection 1 interrupt occurs PDL_INTC_LVD2_DISABLE or PDL_INTC_LVD2_ENABLE Disable or enable the NMI signal when a low voltage detection 2 interrupt occurs R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 64 of 487 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no IRQn interrupt is required A function must be specified for the NMI data3 The IRQn interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func This value does not apply to the NMI and is ignored True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_SetExtinterrupt e Function R_INTC_SetExtInterrupt must be
187. AM status flags shall be stored in the format Specify PDL_NO_PTR if this information is not required b7 b5 b4 b3 b2 b1 bO Transition recovery Initialization sequence Mode register setting 0 0 Inactive 0 Inactive 0 0 Inactive 1 In progress 1 In progress 1 In progress Return value True Category Bus Controller Reference R_BSC_Control Remarks e Call R_BSC_Control to clear the status registers after reading the status R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 143 of 487 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t statusl uint1l6_t status2 Read the BSC status flags but not the SDRAM status R_BSC_GetStatus amp statusl amp status2 PDL_NO_PTR i R20UT1963EE0100 Rev 1 00 AS Page 144 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 4 2 11 DMA Controller 1 R_DMAC_Create Synopsis Prototype Description 1 3 Configure the DMA controller bool R_DMAC_Create uint8_t data1 Channel selection uint32_t data2 Configuration selection uint8_t data3 Trigger selection void data4 Source start address void data5 Destination start address uint16_t data6 Transfer count uint16_t data7 Repeat or Block size int32_t data8 Addre
188. B6 Configure the RS232 port specify Async MP mode R_SCI_Create 9 PDL_SCI_8N1 PDL_SCI_ASYNC_MP 57600 Async MP mode data Transmission by CPU ISR E The receiving side must be ready before this ID is transmitted Send Target Station ID 0x0A by internal polling R_SCI_Send 9 0x0A00 PDL_SCI_MP_ID_CYCL PDL_NO_PTR 0 PDL_NO_FUNC tx_end false Send data to Target Station ID 0x0A using interrupts R_SCI_Send 9 PDL_NO_DATA send_data0 R20UT1963EE0100 Rev 1 00 Page 435 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples while tx_end false Async MP mode data Transmission by polling NOTE The receiving side must be ready before this ID is transmitted Send Target Station ID 0x01 by internal polling R_SCI_Send 9 0x0100 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 PDL_NO_FUNC Send data to Target Station ID 0x01 by polling R_SCI_Send 9 PDL_NO_DATA send_data 0 PDL_NO_FUNC void SCItx void tx_end true Figure 5 33 Example of SCI Transmission code in Asynchronous Multi Processor mode R20UT1963EE0100 Rev 1 00 Page 436 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 17 8 SCI in SPI Mode This shows the setting of SCI channel 6 in to SPI master mode and the transmission of data using interrupts PDL functions includ
189. BLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends If you specify PDL_NO_FUNC this function will wait for the timer to complete before returning You should always specify a function if PDL_CMT_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CGC_Set R20UT1963EE0100 Rev 1 00 REN ESAS Page 252 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Program example e Function R_CGC_Set must be called with the current clock source selected before using this function e Function R_CMT_Create is not required e Ensure that the timer channel is stopped before calling this function Note that the timer is stopped automatically when the one shot period is reached e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has co
190. CK_LOCO_16 or CLOCK_LOCO_32 or CLOCK_LOCO_64 or CLOCK_LOCO_128 or CLOCK_LOCO_256 The selected clock The LOCO 1 16 32 64 128 or 256 Window end position PDL_MCU_OFS_IWDT_WIN PDL_MCU_OFS_IWDT_WIN PDL_MCU_OFS_IWDT_WIN PDL_MCU_OFS_IWDT_WIN END_75 or END_50 or END_ 25 or END 0 The window end position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 0 is equivalent to no window end position e Window start position PDL_MCU_OFS_IWDT_WIN PDL_MCU_OFS_IWDT_WIN The window start position specified as a percentage of the down counter 0 is PDL MCU OFS IWDT WIN START 75 or when the down counter would underflow PDL MCU OFS IWDT WIN START 100 Selecting 100 is equivalent to no window start position START_25 or START_50 or Underflow action PDL_MCU_OFS_IWDT_NMI or PDL MCU OFS_IWDT RESET Select an NMI or reset when the IWDT down counter underflows Count stop mode Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode deep software standby mode or all module clock stop mode PDL_MCU_OFS_IWDT_STOP_DISABLE or PDL_MCU_OFS_IWDT_STOP_ENABLE R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 109 of 487 RX63N Group
191. C_CAPTURE_EDGE_BOTH Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or Configure the capture noise filter If PDL_RTC_CAPTURE_FILTER_ON_DIV_1 or enabling select the sampling period PDL_RTC_CAPTURE_FILTER_ON_DIV_32 relative to the count source data9 Configure the Capture 1 RTCIC1 pin options To set multiple options at the same time use to separate each value e Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or Select the edge that will trigger a capture PDL_RTC_CAPTURE_EDGE_FALLING or event PDL_RTC_CAPTURE_EDGE_BOTH Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or Configure the capture noise filter If PDL_RTC_CAPTURE_FILTER_ON_DIV_1 or enabling select the sampling period PDL_RTC_CAPTURE_FILTER_ON_DIV_32 relative to the count source R20UT1963EE0100 Rev 1 00 R AS Page 266 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Description 4 4 data10 Configure the Capture 2 RTCIC2 pin options To set multiple options at the same time use to separate each value Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or Select the edge that will trigger a capture PDL_RTC_CAPTURE_EDGE_FALLING or event PDL_RTC_CAPTURE_EDGE_BOTH Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or Configure the capture noise filter If PDL_
192. C_Control and call R_LPC_Create to set the new value e Ifthe PLL will be used first use this function to configure the main clock oscillator settings e Ifthe PLL will be used the frequencies of the internal clocks ICLK PCLKA PCLKB FCLK and BCLK must be no more than the PLL output clock frequency 2 e If the main clock will be used the frequencies of the internal clocks ICLK PCLKA PCLKB FCLK BCLK and IECLK must be no more than the main clock frequency 4 e Ifthe PLL output frequency is to be changed while the PLL is enabled before calling this function use R_CGC_Control to select another clock source and stop the PLL Ifthe IWDTLOCO is selected specify PDL_NO_DATA for parameters data2 and data4 to data10 The BCLK pin output will not be active until the external bus is enabled using R_BSC_Control e The SDCLK pin output will not be active until the BSC functions are used to configure and enable the SDRAM controller If the HOCO is selected the HOCO power must not be turned off e If the sub clock will be selected while in low speed operating mode 2 see R_LPC_Create ficLK Sub clock ANd frcLK Sub clock Must equal fsuB cLock If low speed operating mode 1 or 2 is selected do not call this function to configure the PLL R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 56 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_cgc h RP
193. C_NMI IRQn n 0 to 15 interrupt pin or NMI data2 Choose the settings If multiple selections are required use to separate each selection The default settings are shown in bold e Digital filter selection PDL_INTC_FILTER_DIV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC_FILTER_DIV_64 PDL_INTC_FILTER_DISABLE or The interrupt pin input can be unfiltered or sampled using the peripheral clock PCLKB divided by 1 8 32 or 64 For the NMI signal this selection is ignored if the NMI pin is not enabled Options which only apply to the IRQ pins Input sense selection PDL_INTC_LOW or PDL_INTC_FALLING or PDL_INTC_RISING or PDL_INTC_BOTH Select Low level Falling edge Rising edge or Falling and rising edge detection DMAC DTC trigger control Not enabled if low level detection is selected PDL_INTC_DMAC_DTC_TRIGGER_DISABLE or PDL_INTC_DMAC_TRIGGER_ENABLE or PDL_INTC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a valid edge transition is detected on a valid IRQn pin Options which only apply to the NMI e Pin enable and input sense selection PDL_INTC_FALLING or Internal detection control Enable the NMI pin and select falling or rising edge PDL_INTC RISING detection Required only if the NMI pin is to be used PDL_INTC_OSD_DISABLE or PDL_INTC_OSD EN
194. C_REG_IPR_RTC_PRD PDL_INTC_REG_IPR_DMAC_DMACOI PDL_INTC_REG_IPR_AD_ADI PDL_INTC_REG_IPR_DMAC_DMAC1I PDL_INTC_REG_IPR_S12AD_ 12ADI PDL_INTC_REG_IPR_DMAC_DMAC2I PDL_INTC_REG_IPR_ICU_GROUPO PDL_INTC_REG_IPR_DMAC_DMAC3I PDL_INTC_REG_IPR_ICU_GROUP1 PDL_INTC_REG_IPR_EXDMAC_EXDMACOI PDL_INTC_REG_IPR_ICU_GROUP2 PDL_INTC_REG_IPR_EXDMAC_EXDMAC1I PDL_INTC_REG_IPR_ICU_GROUP3 PDL_INTC_REG_IPR_SCIO PDL_INTC_REG_IPR_ICU_GROUP4 PDL_INTC_REG_IPR_SCI1 PDL_INTC_REG_IPR_ICU_GROUP5 PDL_INTC_REG_IPR_SCI2 PDL_INTC_REG_IPR_ICU_GROUP6 PDL_INTC_REG_IPR_SCI3 PDL_INTC_REG_IPR_ICU_GROUP12 PDL_INTC_REG_IPR_SCI4 PDL_INTC_REG_IPR_SCI12_SCIX PDL_INTC_REG_IPR_SCI5 PDL_INTC_REG_IPR_SCI6 PDL_INTC_REG_IPR_SCI7 PDL_INTC_REG_IPR_SCI8 PDL_INTC_REG_IPR_SCI9 PDL_INTC_REG_IPR_SCI10 PDL_INTC_REG_IPR_SCI11 PDL_INTC_REG_IPR_SCI12 PDL_INTC_REG_IPR_IEB R20UT1963EE0100 Rev 1 00 2tENESAS Page 77 of 487 Jul 19 2012 RX63N Group 4 Library Reference DTCER register definitions
195. C_VECTOR_TXMO CAN channel 0 PDL_INTC_VECTOR_SPTIO SPI channel 0 Transmit buffer empty PDL_INTC_VECTOR_SPIIO Idle PDL_INTC_VECTOR_SPRI1 Receive buffer full PDL_INTC_VECTOR_SPTI1 SPI channel 1 Transmit buffer empty PDL_INTC_VECTOR_SPII1 Idle PDL_INTC_VECTOR_SPRI2 Receive buffer full PDL_INTC_VECTOR_SPTI2 SPI channel 2 Transmit buffer empty Idle Receive FIFO Transmit FIFO Reception complete Transmission complete PDL_INTC_VECTOR_RXF1 PDL_INTC_ VECTOR _TXF1 PDL_INTC_VECTOR_RXM1 PDL_INTC_VECTOR_RXF2 PDL_INTC_VECTOR_TXF2 PDL_INTC_VECTOR_RXM2 PDL_INTC_VECTOR_TXM2 CAN channel 1 CAN channel 2 Receive FIFO Transmit FIFO Reception complete PDL_INTC_ VECTOR _TXM1 Transmission complete Receive FIFO Transmit FIFO Reception complete Transmission complete PDL_INTC_VECTOR CUP PDL_INTC_ VECTOR ALM PDL_INTC_ VECTOR PRD Real time clock Carry Alarm Periodic R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 67 of 487 RX63N Group 4 Library Reference Description 2 4 PDL_INTC_VECTOR_IRQO PDL_INTC VECTOR IRQ1 PDL_INTC_VECTOR IRQ2 PDL_INTC_VECTOR_IRQ3 PDL_INTC_VECTOR IRQ4 PDL_INTC_VECTOR IRQS PDL_INTC_VECTOR _IRQ6 PDL_INTC_VECTOR_IRQ7 PDL_INTC_VECTOR _IRQ8 PDL_INTC_VECTOR_IRQ10 PDL_INTC_VECTOR_IRQ9
196. Configure I O pins for all SCI channels There is no default option data1 The channel number n where n 0 to 12 data2 Configure the I O pins for channels 0 to 12 required only if the pins are used for the SCI function Use to separate each selection e Valid when n 0 PDL SCI PIN SCIO_RXDO_P21 or PDL SCI PIN SCIO RXDO P33 PDL_SCI_PIN SCIO SMISOO P21 or PDL SCI PIN SCIO SMISOO P33 SMISO0 PDL SCI_PIN_SCI0_SSCLO_P21 or an PDL SCI PIN SCIO SSCLO P33 PDL SCI_PIN SCIO TXDO P20 or ae PDL_SCI_PIN_SCIO_TXD0_P32 oko feces ec SMOSIO PDL SCI PIN SCIO SSDAO P20 or Scio ae PDL SCI PIN SCIO SSDAO P32 PDL SCI_PIN SCIO SCKO P22 or a PDL_SCI_PIN_SCIO_SCKO_P34 PDL SCI PIN SCIO CTSO P23 or zae PDL SCI PIN SCIO _CTS0_PJ3 PDL SCI_PIN SCIO RTSO P23 or sa PDL SCI PIN SCI0_RTS0_PJ3 PDL_SCI_PIN SCIO SSO P23 or Si PDL SCI PIN SCIO SS0_PJ3 R20UT1963EE0100 Rev 1 00 Page 279 of 487 Jul 19 2012 2tENESAS RX63N Group 4 Library Reference Description 2 5 Valid when n 1 PDL_SCI_PIN_SCI1 RXD1_P15 or PDL_SCI_PIN_SCI1 RXD1_P30 or PDL_SCI_PIN_SCI1 RXD1_PF2 PDL_SCI_PIN_SCI1_ PDL SCI PIN SC PDL_SCI_PIN SCI1_ SMISO1_P15 or SMISO1_P30 or SMISO1_PF2 PDL_SCI_PIN_SCI1 SSCL1_P15 or PDL_SCI_PIN_SCI1 SSCL1_P30 or PDL_SCI_PIN_SCI1 SSCL1_P
197. Control of the clock including e Changing the alarm settings e Changing the current date or time e Error adjustment 4 Reading the clock status flags current time and date alarm time and date and any captured times R20UT1963EE0100 Rev 1 00 Page 38 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 23 Watchdog Timer Driver The driver functions support the use of the watchdog timer providing the following operations 1 Configuring the timer for use including Clock selection Time out period Window position Reset or NMI Interrupt selection when timer overflows 2 Control of the timer including e Counter refresh to prevent timeout 3 Reading the timer status including counter value R20UT1963EE0100 Rev 1 00 Page 39 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 24 Independent Watchdog Timer Driver The driver functions support the use of the independent watchdog timer providing the following operations 1 Configuring the timer for use 2 Refreshing the timer to prevent the reset operation 3 Reading the timer status and counter register R20UT1963EE0100 Rev 1 00 Page 40 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 25 Serial Communication Interface Driver The driver functions support the use of the serial communication SCI channels providing the following operations 1 2 8 9 Selection of the SCI pins for use Configuration for use in
198. Create to resume channel operations e Channel 2 is not available for 100 pin package Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Enable direct loopback mode R_SPI_Control 0 PDL_SPI_LOOPBACK_DIRECT PDL_NO_DATA i Change the extended timings R SPI Control 0 PDL_NO_DATA PDL_SPI_CLOCK_DELAY_8 PDL_SPI_SSL_DELAY_5 i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 336 of 487 Jul 19 2012 RX63N Group 4 Library Reference R_SPI_GetStatus Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT1963EE0100 Rev 1 00 Jul 19 2012 Check the status of an SPI channel bool R_SPI_GetStatus uint8_t data1 Channel selection uint16_t data2 Status flags uint16_t data3 Sequence count Acquires the SPI channel status data1 Select channel SPIn where n 0 1 or 2 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b15 b14 b12 b11 b10 b8 0 Error command 0 Command pointer b7 b6 b5 b4 b3 b2 b1 bO Receive Transmit Parity error Mode fault Bus state Overrun buffer 0 buffer 0 error 0 Empty 0 Full 0 No error 0 No fault 0 Idle 0 No error 1 Full 1 Empt 1
199. DATA 2 di Configure the slave SPI channel R20UT1963EE0100 Rev 1 00 AS Page 464 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples R_SPI_Create SLAVE_CHANNEL PDL_SPI_MODE_SPI_SLAVE PDL_SPI_FRAME_1_1 PDL_NO_DATA PDL_NO_DATA T i Configure the Master R_SPI_Command MASTER_CHANNEL 0 PDL_SPI_CLOCK_MODE_0 PDL_SPI_LENGTH_8 PDL_SPI_LSB_ FIRST PDL_SPI_ASSERT_SSLO PDL_NO_DATA i Configure the slave R_SPI_Command SLAVE_CHANNEL 0 PDL_SPI_CLOCK_MODE_O PDL_SPI_LENGTH_8 PDL_SPI_LSB_FIRST PDL_NO_DATA i Clear the receive buffers for i 0 i lt BUFFER_LENGTH i master_rx_data i 0x00000000 slave_rx_data i 0x00000000 Copy the source data into the transmit buffers for i 0 i lt strlen master_data_to_be_sent i master_tx_data i uint32_t master_data_to_be_sent i slave_tx_data i uint32_t slave_data_to_be_sent il Prepare the Slave for data transfer R_SPI_Transfer SLAVE_CHANNEL PDL_NO_DATA slave_tx_data slave_rx_data uintl6_t strlen slave_data_to_be_sent spi_slave_callback 15 PDL_NO_FUNC 0 slave_transfer_complete false Transfer all the data once R_SPI_Transfer MASTER_CHANNEL PDL_NO_DATA master_tx_data master_rx_data
200. DATA_ALIGNMENT_RIGHT e Result register clearing PDL_ADC_12_RETAIN_RESULT or Retain or clear the value in each result register PDL_ADC 12 CLEAR RESULT after it has been read e Input source PDL_ADC_12_INPUT_AN or Select input from analog channels PDL ADC 12 INPUT TS or the temperature sensor or PDL_ADC_12_INPUT_REF the internal reference voltage e DMAC DTC trigger control PDL_ADC_12_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_ADC_12_DMAC_TRIGGER_ENABLE or DMAC or DTC when a scan cycle PDL_ADC_12_DTC_TRIGGER_ENABLE completes Sampling time excluding temperature sensor PDL_ADC_12_SAMPLING_TIME_CALCULATE or PDL_ADC_12_SAMPLING_TIME_SPECIFY Select whether parameter data7 is used to calculate the ADSSTRO1 value or contains the value to be stored in register ADSSTRO1 e Sampling time for temperature sensor PDL_ADC_12_SAMPLING_TIME_TEMP_CALCULATE or Select whether parameter PDL_ADC_12_SAMPLING_TIME_TEMP_SPECIFY data6 is used to calculate the ADSSTR23 value or contains the value to be stored in register ADSSTR23 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 357 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 3 4 data4 Trigger control selection To set multiple options at the same time use to separate each value Trigger selection PDL_ADC_12_ TRIGGER_SOFTWARE or Software t
201. DL device specific definitions include r_pdl_definitions h void func void Configure main clock operation using a 12 0 MHz crystal ICLK 3 MHz PCLKA 3 MHz PCLKB 3 MHz FCLK 3 MHz BCLK IECLK UCLK not used BCLK pin not used R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABLE 12E6 3E6 3E6 3E6 3E6 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Configure PLL operation The PLL will be set to 192 MHz ICLK 96 MHz PCLKA 96 MHz PCLKB 48 MHz FCLK 48 MHz BCLK 48 MHz BCLK pin 48 MHz IECLK UCLK not used R_CGC_Set PDL_CGC_CLK_PLL PDL_CGC_BCLK_DIV_1 PDL_CGC_SDCLK_ENABLE 192E6 96E6 96E6 48E6 48E6 48E6 PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 AS Page 57 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 2 R_CGC_Control Synopsis Prototype Description 1 2 Modify the clock generation circuit operation bool R_CGC_Conirol uint8_t data1 Clock selection uint32_t data2 Clock control options uint8_t data3 Clock control options Modify the clock control registers data1 Clock source selection If no change is required specify PDL_NO_DATA e Clock source selection PDL_CGC_CLK_LOCO or Select the low speed on chip oscillator LOC
202. DL_DTC_CHAIN_0 PDL_DTC_TRIGGER_SW dtc_sw_transfer_data source_string_l destination_string_l 1 uint8_t strlen source_string_1 Configure the DTC for chain transfer R_DTC_Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_ PLUS PDL_DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DTC_CHAIN_0 PDL_DTC_TRIGGER_CHAIN dtc_sw_transfer_data 4 source_string_2 destination_string_2 1 uint8_t strlen source_string_2 Configure the DTC for chain transfer R_DTC_Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_ PLUS PDL_DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DIC_TRIGGER_CHAIN dtc_sw_transfer_data 8 source_string_3 destination_string_3 1 uint8_t strlen source_string_3 Start the controller R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Generate a software interrupt request R_INTC_Write PDL_INTC_REG_SWINTR 1 Figure 5 13 Example of DTC chain transfer R20UT1963EE0100 Rev 1 00 Page 408 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 10 Port Output Enable Figure 5 14 shows a usage example of Port Output Enable function PDL functions include r_pdl_poe h PDL device specific definit
203. DL_IEB_CLOCK_IECLK_DIV_2 or PDL_IEB_CLOCK_IECLK_DIV_3 or PDL_IEB_CLOCK_IECLK_DIV_4 or PDL_IEB_CLOCK_IECLK_DIV_5 or PDL_IEB_CLOCK_IECLK_DIV_6 or PDL_IEB_CLOCK_IECLK_DIV_7 Alternatively the division applied to IECLK can be specified directly Communication mode PDL_IEB_MODE_0 or PDL_IEB_MODE 1 The communication mode Reception control PDL_IEB_RX_ENABLE or PDL_IEB_RX DISABLE Input Output polarity control Enable or disable reception PDL_IEB_POLARITY_LOW or PDL_IEB_POLARITY_HIGH Select active low or active high polarity Digital filter control PDL_IEB_FILTER_IECLK_DIV_1 or PDL_IEB_FILTER_IECLK_DIV_2 or PDL_IEB_FILTER_IECLK_DIV_3 or PDL_IEB_FILTER_IECLK_DIV_4 or PDL_IEB_ FILTER DISABLE Disable or enable the digital filter using the IEBus clock IECLK 1 2 3 or 4 data3 The unit address valid from 0000h to OFFFh data4 The interrupt priority level Select between 0 disabled and 15 highest priority True if all parameters are valid and pins have been selected otherwise false IEBus R_CGC_Set R_IEB_Set R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 339 of 487 RX63N Group 4 Library Reference Remarks Program example e Functions R_CGC_Set and R_IEB_Set must be called before any use of this function e If the digital filter clock division of 2 3 or 4 is
204. DL_IIC_ HOST ADDRESS ENABLE address data4 Slave address 0 Ignored if slave address 0 detection is disabled data5 Slave address 1 Ignored if slave address 1 detection is disabled data6 Slave address 2 Ignored if slave address 2 detection is disabled data7 Transfer rate control Either The maximum bit rate in bits per second For Master mode the clock division values will be calculated using a 50 duty cycle For Slave mode the rate will be used to calculate the clock stretching period Or b31 b30 b13 b12 b8 b7 b5 b4 bO 1 E Bit rate high level register E Bit rate low level register ICBRH value ICBRL value R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 309 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 3 3 Return value Category Reference Remarks data8 Rise and fall time compensation If the transfer rate is specified in bits per second the high level and low level durations can be adjusted to allow for application dependent rise and fall times If unsure use 0 b31 b16 b15 bO The SCL rise time in nanoseconds The SCL fall time in nanoseconds Valid from 0 to 65535 Valid from 0 to 65535 True if all parameters are valid exclusive and achievable otherwise false IC R_CGC_Set e Function R_CGC_Set must be called with the current clock source selected before
205. DL_MTU2_OUT_N PHASE 3 LOW_HIGH Write access control applies only to reset synchroni sed or complementary PWM modes PDL_MTU2_OUT_LOCK_ENABLE Prevent further changes to the phase output control Toggle output control applies only to reset synchron ised or complementary PWM modes PDL_MTU2_OUT_TOGGLE_ENABLE or 2tENESAS PDL MTU2 OUT TOGGLE DISABLE synchronised with the PWM cycle Enable or disable toggle output Page 192 of 487 RX63N Group 4 Library Reference Description 3 4 buffer_control The buffer control settings to be modified All settings are optional If multiple selections are required use to separate each selection e Output level buffer control applies only to reset synchronised or complementary PWM modes Set the output control to be transferred to the output PDL_MTU2_OUT_BUFFER P_PHASE_1_LOWor MTIOC3B PDL_MTU2 OUT BUFFER P_PHASE_1_HIGH PDL_MTU2_OUT BUFFER _N PHASE 1 LOWor MTIOC3D PDL_MTU2_OUT_BUFFER_N PHASE 1 HIGH PDL_MTU2_OUT_BUFFER P PHASE 2 LOWor MTIOC4A PDL_MTU2_OUT BUFFER P_PHASE 2 HIGH PDL_MTU2_OUT_BUFFER_N_PHASE_2 LOWor MTiocac PDL_MTU2_OUT BUFFER N PHASE 2 HIGH PDL_MTU2_OUT_BUFFER P PHASE 3 LOWor MTIOC4B PDL_MTU2_OUT BUFFER P_PHASE 3 HIGH PDL_MTU2_OUT_BUFFER N_PHASE_3 LOWor MTIOC4D PDL_MTU2_OUT_BUFFER_N PHASE 3 HIGH e Set the transfer timing In
206. DL_NO_FUNC is specified for parameter func2 Return value True if all parameters are valid and exclusive otherwise false Category Real time clock Reference R_CGC_Set R_CGC_Control R LMCU_OFS Remarks The check for days in the month allows for leap years If entering software standby or deep software standby mode soon after starting the RTC use R_RTC_Read first to confirm that the values are correct If the main clock is selected as the RTC count source the operating frequency of the peripheral module clock and the main clock should be in the relationship that the peripheral module clock frequency 2 main clock frequency Use R_CGC_Set to configure the clock frequencies e lf capture is enabled for a capture pin that has not been selected this function will return false The oscillation accuracy of the sub clock is affected when an on chip debugger emulator is connected and the sub clock drive setting is low e Before calling this function the count source must be enabled and stable Hence use R_CGC_Set or R_CGC_Control to enable the count source and then allow the clock stabilisation time to pass before calling this function e If this function has been used and then a warm reset is performed it is not necessary to call this function again to continue using the RTC However if this function is to be called it is necessary to call R_ CGC_Set or R_CGC_Control to enable the subclock even if it is already enabled before ca
207. DMAC DTC trigger control PDL_SPI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SPI_DMAC_TRIGGER_ENABLE or DMAC or DTC for data transmission PDL_SPI_DTC_TRIGGER_ENABLE and reception data3 The start address of the data to be transmitted The data must be stored as 32 bit values Specify PDL_NO_PTR if no data is to be transmitted or if the data content is not important or if the DMAC or DTC shall be used to handle the data transfer data4 The start address of the data to be received The data will be stored as 32 bit values Specify PDL_NO_PTR if no data is to be received or if the DMAC or DTC shall be used to handle the data transfer data5 The number of times that the command sequence will be executed If the DMAC or DTC shall be used to handle the transfer specify PDL_NO_DATA func1 Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Pollin PDL_NO_FUNC R_SPI_Transfer will handle the data transfer until 9 completion Interrupts The function to be called when the transfer has completed DMAC or DTC The function to be called when the DMAC or DTC passes on the transfer interrupt data6 The interrupt priority level for data transmission Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 func
208. E or PDL_ADC_12_SAMPLING_TIME_SPECIFY If PDL_ADC_12_SAMPLING_TIME_CALCULATE is selected then specify the required sampling time in seconds This must not be less than 4 us If PDPL_ADC_12_SAMPLING_TIME_SPECIFY is selected specify the value to be written to the ADSSTRO1 SST1 bits Range 10 to 255 data7 This parameter is ignored if data3 does not specify PDL_ADC_12_SAMPLING_TIME_TEMP_CALCULATE or PDL_ADC_12_SAMPLING_TIME_TEMP_SPECIFY If PDL_ADC_12_SAMPLING_TIME_TEMP_CALCULATE is selected then specify the required sampling time in seconds This must not be less than 4 us If PDL_ADC_12_SAMPLING_TIME_TEMP_SPECIFY is selected specify the value to be written to the ADSSTR23 SST2 bits Range 10 to 255 func The function to be called when the ADC conversion scan cycle is complete Specify PDL_NO_FUNC if no callback function is required data8 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false 12 bit ADC R_CGC Set e Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in e If an external trigger is used the low level pulse width must be at least 1 5 PCLK cycles e This function brings the converter unit out of the power down state e Acallback function is executed by t
209. E0100 Rev 1 00 R AS Page 265 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference Description 3 4 data7 Configure the Error Adjustment options To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA This setting will be ignored when the main clock is selected as the RTC count source e Auto Error Adjustment PDL_RTC_ERROR_AUTO_ADJUST_DISABLE or Enable or disable automatic PDL_RTC_ERROR_AUTO_ADJUST_ENABLE error adjustment e Auto Error Adjustment Period PDL_RTC_ERROR_AUTO_ADJUST_PERIOD_60S or Select the automatic error PDL_RTC_ERROR_AUTO_ADJUST_PERIOD_10S adjustment period Auto Error Adjustment Addition or Subtraction selection PDL_RTC_ERROR_ADJUST_PLUS or PDL_RTC_ERROR_ADJUST_MINUS Select if the adjustment value will be added or subtracted from the count Update the Error Adjustment value PDL_RTC_ERROR_UPDATE_ERROR_ADJUST_VALUE Select to specify a new error adjustment value Error Adjustment Value New automatic error adjustment value ignored Valid Range 0 to 3FEh if not selected above data8 Configure the Capture 0 RTCICO pin options To set multiple options at the same time use to separate each value Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or Select the edge that will trigger a capture PDL_RTC_CAPTURE_EDGE_FALLING or event PDL_RT
210. ECOND ENABLE Select 12 or 24 hour mode All three can be controlled using PDL_RTC_ALARM_TIME_DISABLE or PDL_RTC_ALARM_TIME_ENABLE PDL_RTC_ALARM_YEAR_DISABLE or PDL_RTC_ALARM_YEAR_ENABLE PDL_RTC_ALARM_MONTH_DISABLE or PDL_RTC_ALARM_ MONTH ENABLE PDL_RTC_ALARM_DAY_DISABLE or PDL_RTC_ALARM_DAY_ENABLE PDL_RTC_ALARM_DOW_DISABLE or PDL_RTC_ALARM_DOW_ENABLE All four can be controlled using PDL_RTC_ALARM_DATE_DISABLE or PDL_RTC_ALARM_DATE_ENABLE Clock output control PDL_RTC_OUTPUT_DISABLE or PDL_RTC_OUTPUT_ENABLE Disable or enable the 1 Hz clock output on the RTCOUT pin Clock control PDL_RTC_CLOCK_STOP or PDL_RTC_CLOCK_START Stop or re start the clock 30 second adjustment control PDL_RTC_ADJUST_ START Start the 30 second adjustment process Reset control PDL_RTC_RESET START Start the reset process R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 264 of 487 RX63N Group 4 Library Reference Description 2 4 data2 Select the values to be changed To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA e Select the time counters to be updated using values supplied in parameter data3 PDL_RTC_UPDATE_CURRENT_HOUR PDL_RTC_UPDATE_CURRENT_MINUTE PDL_RTC_UPDATE_CURRENT_SECOND All three can be se
211. EG PD2PFS PDL_MPC_REG PD3PFS PDL_MPC_REG P16PFS PDL_MPC_REG P80PFS PDL_MPC_REG PD4PFS PDL_MPC_REG P17PFS PDL_MPC_REG_P81PFS PDL_MPC_REG_PD5PFS PDL_MPC_REG_P20PFS PDL_MPC_REG P21PFS PDL_MPC_REG_P82PFS PDL_MPC_REG P83PFS PDL_MPC_REG_PD6PFS PDL_MPC_REG PD7PFS PDL_MPC_REG_P22PFS PDL_MPC_REG_P86PFS PDL_MPC_REG_PEOPFS PDL_MPC_REG_P23PFS PDL_MPC_REG_P87PFS PDL_MPC_REG PE1PFS PDL_MPC_REG_P24PFS PDL_MPC_REG_P90PFS PDL_MPC_REG_PE2PFS PDL_MPC_REG_P25PFS PDL_MPC_REG_P91PFS PDL_MPC_REG_PE3PFS PDL_MPC_REG_P26PFS PDL_MPC_REG P92PFS PDL_MPC_REG_PE4PFS PDL_MPC_REG_P27PFS PDL_MPC_REG_P93PFS PDL_MPC_REG_PESPFS PDL_MPC_REG_P30PFS PDL_MPC_REG_PAOPFS PDL_MPC_REG PE6PFS PDL_MPC_REG P31PFS PDL_MPC_REG_PA1PFS PDL_MPC_REG PE7PFS PDL_MPC_REG_P32PFS PDL_MPC_REG_PA2PFS PDL_MPC_REG_PFOPFS PDL_MPC_REG_P33PFS PDL_MPC_REG_PA3PFS PDL_MPC_REG_ PF1PFS PDL_MPC_REG_P34PFS PDL_MPC_REG_PA4PFS PDL_MPC_REG_PF2PFS PDL_MPC_REG_P40PFS PDL_MPC_REG_PAS5PFS PDL_MPC_REG_PF5PFS PDL_MPC_REG P41PFS PDL_MPC_REG P42PFS PDL_MPC_REG_PA6PFS PDL_MPC_REG_PA7PFS PDL_MPC_REG_PJ3PFS PDL_MPC_REG PFCSE PDL_MPC_REG P43PFS PDL_MPC_REG_PBOPFS PDL_MPC_REG PFCSSO PDL_MPC_REG P44PFS PDL_MPC_REG PB1PFS PDL_MPC_REG PFCSS1 PDL_MPC_REG P45PFS PDL_MPC_REG PB2PFS PDL_MPC_REG_PFAOEO PDL_MPC_REG_P46PFS PDL_MPC_RE
212. E_REPEAT_DESTINATION area using parameter data9 data3 The new source address Specify PDL_NO_PTR if not required data4 The new destination address Specify PDL_NO_PTR if not required data5 The transfer count value Specify PDL_NO_DATA if not required data6 The repeat block or cluster size for each transfer Specify PDL_NO_DATA if not required data7 The address offset value Specify PDL_NO_DATA if not required R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 160 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example data8 The source address extended repeat value Specify PDL_NO_DATA if not required data9 The destination address extended repeat value Specify PDL_NO_DATA if not required True if all parameters are valid and exclusive otherwise false EXDMA controller R_EXDMAC_Create e The Software trigger control is valid only if the Software trigger option has been selected e This function must be called in order to start the EXDMAC e Refer to RLEXDMAC_Create for the valid parameter values The Suspend Enable and Start control is executed at the end of the function If a channel has completed a transfer parameters may be changed and the channel re enabled in one function call RPDL definitions include r_pdl_exdma
213. F2 PDL_SCI_PIN_SCI1 TXD1_P16 or PDL_SCI_PIN_SCI1 TXD1_P26 or PDL_SCI_PIN_SCI1 PDL SCI PIN SCN PDL SCI PIN SC PDL SCI PIN SCI1_ TXD1_PFO SMOSI1_P16 or SMOSI1_P26 or SMOSI1_PFO PDL_SCI_PIN_SCI1 SSDA1_P16 or PDL_SCI_PIN_SCI1 SSDA1_P26 or PDL_SCI_PIN_SCI1 SSDA1_PFO PDL_SCI_PIN_SCI1 SCK1_P17 or PDL_SCI_PIN_SCI1 SCK1_P27 or PDL_SCI_PIN_SCI1 SCK1_PF1 PDL_SCI_PIN_SCI1 CTS1_P14 or PDL_SCI_PIN_SCI1_ CTS1_P31 PDL SCI PIN SCI1 RTS1_P14 or PDL_SCI_PIN_SCI1 RTS1_P31 PDL_SCI_PIN_SCI1 S1_P14 or PDL_SCI_PIN_SCI1 SS1_P31 SCl1 RXD1 SMISO1 SSCL1 TXD1 SMOSI1 SSDA1 SCK1 CTS1 RTS1 SS1 Valid when n 2 PDL_SCI_PIN_SCI2 RXD2_P12 or PDL_SCI_PIN_SCI2 PDL_SCI_PIN_SCI2_ PDL_SCI_PIN SCI2_ RXD2_P52 SMISO2_P12 or SMISO2_P52 PDL_SCI_PIN_SCI2 SSCL2_P12 or PDL_SCI_PIN_SCI2 SSCL2_P52 PDL_SCI_PIN_SCI2 TXD2_P13 or PDL_SCI_PIN_SCI2 TXD2_P50 PDL_SCI_PIN_SCI2_ PDL_SCI_PIN_SCI2_ SMOSI2_P13 or SMOSI2_P50 PDL_SCI_PIN_SCI2 SSDA2_P13 or PDL_SCI_PIN_SCl2 SSDA2_P50 PDL_SCI_PIN_SCI2 SCK2_P11 or PDL_SCI_PIN_SCI2 SCK2_P51 PDL_SCI_PIN_SCl2 CTS2_P54 PDL_SCI_PIN_SCIl2 RTS2_P54 PDL_SCI_PIN_SCl2 SS2_P54
214. G PB3PFS PDL_MPC_REG_PFAOE1 PDL_MPC_REG P47PFS PDL_MPC_REG PB4PFS PDL_MPC_REG_PFBCRO PDL_MPC_REG_P50PFS PDL_MPC_REG_PB5PFS PDL_MPC_REG PFBCR1 PDL_MPC_REG_P51PFS PDL_MPC_REG PB6PFS PDL_MPC_REG_PFENET PDL_MPC_REG_P52PFS PDL_MPC_REG_P54PFS PDL_MPC_REG_P55PFS PDL_MPC_REG_P56PFS PDL_MPC_REG_P57PFS R20UT1963EE0100 Rev 1 00 Jul 19 2012 PDL_MPC_REG_PB7PFS PDL_MPC_REG_PFUSBO PDL_MPC_REG_PFUSB1 2tENESAS Page 102 of 487 RX63N Group 4 Library Reference 1 R_MPC_Read Synopsis Prototype Description Return value Category References Remarks Program example Read an MPC register bool R_MPC_Read uint8_t data1 MPC register selection uint8_t data2 Pointer to the variable where the MPC register s value shall be stored Get the value of an MPC register data1 One of the definition values from 4 2 4 data2 The value read from the register True if a valid MPC register is specified otherwise false MPC registers None None RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data Get the value of register PFCSE R_MPC_Read PDL_MPC_REG_PFCSE amp data R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 103 o
215. GLE PDL_ADC_12 DATA _ALIGNMENT_RIGHT L_ADC_12_RETAIN_RESULT PDL_ADC_12_DIv_1 L_ADC_12_TRIGGER_SOFTWARE L_ADC_12_ VALUE_ADD_TIME_1 L_NO_DATA 6 Temperature sensor sampling time Seconds DC_callback El to ee oPuTo Start up temperature sensor operation R_TS_Create Wait for 30us for stabilization of the reference voltage for the temperature sensor tTSTBL 30 us R_CMT_CreateOneShot 0 PDL_NO_DATA 30E 6 PDL_NO_FUNC 0 Enable the Temperature Sensor output R_ TS Control PDL_TS_OUTPUT_ENABL Start A D conversion R_ADC_12_ ControlAll1 PDL_ADC_12_0_ON Reset the variables to value 0 ts_result 0 ADC_end false Waiting for conversion trigger signal whil ADC_end false R20UT1963EE0100 Rev 1 00 Page 485 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Put the temperature sensor into power down state R_TS_Destroy Shut down ADC channel 0 R_ADC_12_Destroy 0 while 1 void ADC_callback void ADC_end true R_ADC_12_ Read 0 amp ts_result Figure 5 59 Example of Temperature sensor R20UT1963EE0100 Rev 1 00 Page 486 of 487 Jul 19 2012 RENESAS RX63N Group 6 RX specific notes 6 RX specific notes 6 1 Interrupts and processor mode The RX CPU has two
216. I O port e All pins that are not available on the selected package will be configured for CMOS type low level output RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set all reserved I O port pins to the recommended state R_IO_PORT_NotAvailable R20UT1963EE0100 Rev 1 00 2tENESAS Page 101 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 2 4 Multifunction Pin Controller The peripheral functions can be assigned to different pins controlled by the Multifunction Pin Controller The definitions available to the MPC functions are listed below MPC register definitions PDL_MPC_REG_POOPFS PDL_MPC_REG_P60PFS PDL_MPC_REG_PCOPFS PDL_MPC_REG_PO1PFS PDL_MPC_REG_P61PFS PDL_MPC_REG PC1PFS PDL_MPC_REG_P02PFS PDL_MPC_REG_P66PFS PDL_MPC_REG PC2PFS PDL_MPC_REG_P03PFS PDL_MPC_REG_P67PFS PDL_MPC_REG PC3PFS PDL_MPC_REG_POSPFS PDL_MPC_REG_P70PFS PDL_MPC_REG PC4PFS PDL_MPC_REG_PO7PFS PDL_MPC_REG_P71PFS PDL_MPC_REG PC5PFS PDL_MPC_REG_P10PFS PDL_MPC_REG_P72PFS PDL_MPC_REG PC6PFS PDL_MPC_REG P11PFS PDL_MPC_REG_P73PFS PDL_MPC_REG PC7PFS PDL_MPC_REG P12PFS PDL_MPC_REG P13PFS PDL_MPC_REG P14PFS PDL_MPC_REG P15PFS PDL_MPC_REG P74PFS PDL_MPC_REG P75PFS PDL_MPC_REG P76PFS PDL_MPC_REG P77PFS PDL_MPC_REG PDOPFS PDL_MPC_REG PD1PFS PDL_MPC_R
217. IIC_SlaveMonitor Monitor the bus and receive data from a master R_IIC_SlaveSend Write data to a master device lEBus Controller R_IIC_Control lC channel control R_IIC_GetStatus Read the status for an C channel R_SPI_Set Configure the SPI pin selection R_SPI_Create Configure an SPI channel Serial R_SPI_Destroy Shutdown an SPI channel Peripheral R_SPI_Command Configure an SPI command Interface R_SPI_Transfer Transfer data over an SPI channel R_SPI_Control Control an SPI channel R_SPI_GetStatus Check the status of an SPI channel R_IEB_Set Configure the IEBus pin selection R_IEB_ Create Configure the IEBus channel R_IEB_Destroy Shutdown an IEBus channel R_IEB MasterSend Transmit data over an IEBus channel R_IEB MasterReceive R_IEB_ SlaveMonitor R_IEB_SlaveWrite Receive data over an IEBus channel Monitor the IEBus Prepare data for sending to a master unit R_IEB_ Control Change the IEBus channel configuration R_IEB_ GetStatus Check the status of an IEBus channel eolo NI D O R O P NID A wN O O N OD An AVN a gt R_CRC_Create Configure the CRC calculator 2 R_CRC_Destroy Shut down the CRC calculator E
218. IN_CLKC_P16 or PDL_TPU_PIN_CLKC_PB2 or PDL_TPU_PIN_CLKC_PCO Select the P16 PB2 or PCO pin for TCLKC PDL_TPU_PIN_CLKD_P17 or PDL_TPU_PIN_CLKD_PB3 or PDL_TPU_PIN_CLKD_PC1 Select the P17 PB3 or PC1 pin for TCLKD e Valid when n 6 7 8 9 10 11 PDL_TPU_PIN_CLKE_PC4 Select the PC4 pin for TCLKE e Valid when n 6 7 8 11 PDL_TPU_PIN_CLKF_PC5 Select the PC5 pin for TCLKF e Valid when n 6 8 10 11 PDL_TPU PIN CLKG PD1 Select the PD1 pin for TCLKG PDL_TPU_PIN_CLKH_PD3 Select the PD3 pin for TCLKH True if all parameters are valid and exclusive otherwise false Timer Pulse Unit R_TPU_Create R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 208 of 487 RX63N Group 4 Library Reference Remarks gt Program example Before calling R_TPU_Create call this function to configure the relevant pins Device packages with 100 pins do not have all of the pin options Not more than one peripheral function can be assigned to a single pin Make sure the configuration of TCLK pins is consistent for all the channels RPDL definitions include r_pdl_tpu h RPDL device specific definitions include r_pdl_definitions h void func void Configure TPU TIOCAO and TCLKA R_TPU_Set 0 PDL_TPU_PIN_A0_P86 PDL_TPU_PIN_CLKA_P14 R20UT1963EE0100 Rev 1
219. KK KK KK KK KKK KK KKK e He e He e He e He KKK KK He he He KKK He He e He e He e He e ke e ke ke ke ke ke kek KKK Wait for the SCI transmission to end do R_SCI_GetStatus 0 amp SCI_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR While the Transmit status BIT_2 is not reporting idle while SCI_status amp 0x04 0 Stop the SCI R_ SCI Control 0 PDL_SCI_STOP_TX Figure 5 29 Example of SCI Asynchronous operation using DMAC R20UT1963EE0100 Rev 1 00 Page 428 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 17 4 Synchronous Transmission and Reception This shows the configuration of SCI channel 0 as the clock master and channel 2 as the slave The master transmits data to the slave The slave receive function call uses interrupts to call a callback function on completion Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h SCI channel selection define MASTER_CHANNEL 0 FE CHANNEL 2 define SLAV Rx complete flag volatile uint8_t data_received Callback function prototype static void SCI9RxFunc void void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please r
220. LAG PDL_INTC_CLEAR_OSD_FLAG Clear the IRQ or NMI interrupt request flag This is not required if e Acallback function has been specified e The interrupt priority level is higher than 0 e The processor interrupt priority level is lower than the interrupt priority level This operation should not be applied when low level detection is used Clear the Oscillation Stop detection NMI flag PDL_INTC_CLEAR_WDT_FLAG Clear the WDT event detection NMI flag PDL_INTC_CLEAR_IWDT_ FLAG Clear the IWDT event detection NMI flag PDL_INTC_CLEAR LVD1_FLAG Clear the LVD1 event detection NMI flag PDL_INTC_CLEAR LVD2 FLAG Clear the LVD2 event detection NMI flag True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_CreateExtInterrupt R_INTC_GetExtInterruptStatus Remarks e The NMI pin was enabled during R_INTC_CreateExtInterrupt and cannot be disabled an MCU design feature e When disabling an IRQn pin the Interrupt Request flag will be cleared automatically e Acallback function may be called once more if a valid event occurs just before the interrupt pin is disabled R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 72 of 487 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h
221. LTER_LOCO_DIV_4 or PDL_LVD_FILTER_LOCO _DIV_8 data2 Monitor 2 voltage detection configuration If the monitor is not required specify PDL_NO_DATA otherwise use selection to separate each e Operation PDL_LVD_MONITOR_ONLY or PDL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_DELAY or PDL_LVD_INTERRUPT_NMI_DETECT_RISE or PDL_LVD_INTERRUPT_NMI_DETECT_FALL or PDL_LVD_INTERRUPT_NMI_DETECT_RISE_AND_FALL Select no action a reset on low voltage detection or non maskable interrupt when a specified voltage event is detected e Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL_LVD_FILTER_LOCO_DIV_2 or Configure the digital filter PDL_LVD_FILTER_LOCO_DIV_4 or PDL_LVD_FILTER_LOCO_DIV_8 True if the parameters are valid otherwise false Category Voltage detection circuit References R_INTC_CreateExtInterrupt R_ CGC_Set R_LPC_GetStatus R_CGC_Control R_LPC_Create RLMCU_OFS R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 112 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Program example If a non maskable interrupt will be generated call R_INTC_CreateExtInterrupt to set up the NMI handler and to accept LVD based interrupt signals If using the digital filter function R_CGC_Set must be called with the current clock source selected before usin
222. L_INTC_IRQ7_PE7 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 62 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category References Remarks Program example data2 Allocate the pins for signals IRQ8 to IRQ15 All selections are optional If multiple selections are required use to separate each selection If no pins are required specify PDL_NO_DATA PDL_INTC_IRQ8_P40 or PDL_INTC_IRQ8_P00 or PDL_INTC_IRQ8 P20 PDL_INTC_IRQ9_P41 or PDL_INTC_IRQQ P01 or PDL_INTC_IRQQ P21 PDL_INTC_IRQ10_P42 or PDL_INTC_IRQ10_P02 or PDL_INTC_IRQ10_P55 PDL_INTC_IRQ11_P43 or PDL_INTC_IRQ11_P03 or PDL_INTC_IRQ11_PA PDL_INTC_IRQ12_P44 or PDL_INTC_IRQ12_PBO or PDL_INTC_IRQ12 PC1 PDL_INTC_IRQ13_P45 or PDL_INTC_IRQ13_P05 or PDL_INTC_IRQ13_PC6 PDL_INTC_IRQ14_P46 or PDL_INTC_IRQ14_PCO or PDL_INTC_IRQ14_PC7 PDL_INTC_IRQ15_P47 or PDL_INTC_IRQ15_PO07 or PDL_INTC_IRQ15 P67 Select the pins to be used for signals IRQ8 to IRQ15 True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_CreateExtInterrupt Before calling R_INTC_CreateExtInterrupt call this function to select the required pins e The Multifunction Pin Control registers are modified to enable each selected IRQ pin and the I O Port PMR and PDR registers are m
223. L_INTC_REG_IR_SPI1_SPRI PDL_INTC_REG_IR_TPU3_TGIA PDL_INTC_REG_IR_SPI1_SPTI PDL_INTC_REG_IR_TPU3_TGIB PDL_INTC_REG_IR_SPI1_SPII PDL_INTC_REG_IR_TPU3_TGIC PDL_INTC_REG_IR_SPI2_SPRI PDL_INTC_REG_IR_TPU3_TGID PDL_INTC_REG _IR_SPI2_SPTI PDL_INTC_REG_IR_TPU4 TGIA PDL_INTC_REG _IR_SPI2_SPIl PDL_INTC_REG_IR_TPU4 TGIB PDL_INTC_REG_IR_CANO_RXF PDL_INTC_REG_IR_TPU5S_TGIA PDL_INTC_REG_IR_CANO_TXF PDL_INTC_REG_IR_TPUS_TGIB PDL_INTC_REG_IR_CANO_RXM PDL_INTC_REG_IR_TPU6_TGIA PDL_INTC_REG_IR_CANO_TXM PDL_INTC_REG_IR_TPU6_TGIB PDL_INTC_REG_IR_CAN1_RXF PDL_INTC_REG_IR_TPU6_TGIC PDL_INTC_REG_IR_CAN1_TXF PDL_INTC_REG_IR_TPU6_TGID PDL_INTC_REG_IR_CAN1_RXM PDL_INTC_REG_IR_TPU7_TGIA PDL_INTC_REG_IR_CAN1_TXM PDL_INTC_REG_IR_TPU7_TGIB PDL_INTC_REG_IR_CAN2_RXF PDL_INTC_REG_IR_TPU8_TGIA PDL_INTC_REG_IR_CAN2_TXF PDL_INTC_REG_IR_TPU8_TGIB PDL_INTC_REG_IR_CAN2_RXM PDL_INTC_REG_IR_TPU9 TGIA PDL_INTC_REG_IR_CAN2_TXM PDL_INTC_REG_IR_TPU9 TGIB PDL_INTC_REG_IR_RTC_CUP PDL_INTC_REG_IR_TPU9_TGIC PDL_INTC_REG_IR_ICU_IRQO PDL_INTC_REG_IR_TPU9_ TGID PDL_INTC_REG_IR_ICU_IRQ1 PDL_INTC_REG_IR_TPU10_TGIA PDL_INTC_REG _IR_ICU_IRQ2 PDL_INTC_REG_IR_TPU10_TGIB PDL_INTC_REG _IR_ICU_IRQ3 PDL_INTC_REG_IR_TPU11_TGIA PDL_INTC_REG_IR_ICU_IRQ4 PDL_INTC_REG_IR_TPU11_TGIB PDL_INTC_REG_IR_ICU_IRQ5 PDL_INTC_REG_IR_MTUO_TGIA PDL_INTC_REG_IR_ICU_IRQ6 PDL_INTC_REG_IR_MTUO_TGIB PDL_INTC_REG_IR_ICU_IRQ7 PDL_INTC_REG_IR_MTUO_TGIC PDL_INTC_REG_IR_ICU_IRQ8 PDL_INTC_REG_IR_MTUO_TGID PDL_INTC_REG_IR_ICU_IRQ9 PDL_IN
224. L_SCI_TX_CONNECTED PDL_SCI_RX_CONN 19200 1 0 Set flag to wait on data_received false Setup master to receive Non polling NOTE No clocks pulses will be generated until R_SCI_Send is called R_SCI_Receive MASTER_CHANNEL PDL_NO_DATA rx_buffer R20UT1963EE0100 Rev 1 00 Page 431 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples DATA_LENGTH SCI_Rx_ Callback PDL_NO_FUNC di Dummy send so the Slave Tx and Master Rx will happen R_SCI_Send MASTER_CHANNEL PDL_NO_DATA Dummy DATA_LENGTH PDL_NO_FUNC Wait for Rx to finish while data_received false Process the received data here while 1 Callback function for Rx static void SCI_Rx_Callback void data_received true Figure 5 31 Example of Synchronous Full Duplex operation R20UT1963EE0100 Rev 1 00 Page 432 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 17 6 SCI Reception in Asynchronous Multi Processor mode This shows the setting of SCI channel 9 and the Multi Processor mode reception of data using interrupts and polling PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_io_port h PDL device specific definitions include r_pdl_definitions h yoid SCIrx void void SCIEr void define NUM_DATA 50 volatile ui
225. M output 10 Reading the registers of a single timer channel 11 Reading the registers of a 16 bit timer channel pair Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT1963EE0100 Rev 1 00 Page 36 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 21 Compare Match Timer Driver The driver functions support the use of the two 16 bit timers providing the following operations 1 Configuration for use including e Automatic clock setting using frequency or period as an input e Manual clock setting using register values as inputs e Automatic interrupt control 2 Configuration for use as a one shot timer 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer including constant register updates change of frequency 5 Reading the counter value and status flag Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT1963EE0100 Rev 1 00 Page 37 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 22 Real time Clock Driver The driver functions support the use of the real time clock providing the following operations 1 Configuring the clock for use including Count source selection Alarm configuration Optional day of week calculation 12 or 24 hour mode selection Automatic alarm and periodic interrupt control Setup of capture pins 2 Disabling the clock 3
226. MAIN EXPECTED_F_MAIN DL D_ EXPEC F_MAIN EXPEC F_MAIN PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Select the main clock oscillator as the system clock R_CGC_Control PDL_CGC_CLK_MAIN PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 AS Page 387 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples f_system_clock EXPECTED_F_MAIN Select the LOCO as the reference clock for system 1 R_MCK_Control PDL_MCK_1_REFERENCE_LOCO PDL_MCK_2 DISABLI EJ f_reference_clock EXPECTED_F_LOCO Set the channel 0 counter value to the mid point of the channel 1 counter reference_count uint1l6_t UINT16_MAX 2 f_system_clock f_reference_clock PDL PDL Configure MTU channel 0 Load the MTU Create defaults R_MTU2_Create_load_defaults amp mtu_create_parameters Set the channel 0 options Normal operation mtu_create_parameters channel_mode PDL_MTU2_MODE_NORMAL Counter input is the MTCLKD input counter cleared by compare match A mtu_create_parameters counter_operation PDL_MTU2_CLK_MTCLKD TU2_CLEAR_TGRA Compare match A output disabled mtu_create_parameters TGR_A_B_ operation PDL_MTU2_A_OC_DISABLED m Set the reference count as the compare match A value tu_create_parameters TGRA_TCNTV_v
227. MR CreateOne Shot inire 5 5d occu cued lesen eean a es eaaa E Aeaaeai aa AE aa R TAAA ESA TERASTA 238 R TMR DESO iaae eraan a area a aaaea aana a a Aaa ae a a e AAA ten Raana d ea 240 R TMR C ntrolehanneli mssi adanan a e eaaa aaee eataa a ARE aa RTEA nara 241 Rot MR Control nit ess Arae aree eae aaea anae ea Ra Aaa aae eaaa ae e AA eee ete 243 R_TMR_ControlPeriodic senesinden aaeeea edan reat fiaa inp eaea iaaiaee naaa Eduart d a Traat 245 R TMR ReadChannel sssaaa eea edaran eae adaos aad eds aa aeaa aaa aAa T eaa ah dadada eaat 247 R TMR ReadU it mrii eaae ad eean a aaraa de ae aes ea eee eaaa aaa ede dane aR ania adaa aie 248 Compare Match TIMen redii d ea aae eaa eaea odao aR a a aar eaaa aiaa nde ah adda AaS 250 REGMil Create iire deaa aae aaa ae aE aea aia araa de et aeS Pea ee sade aaa a a AAE ea anaa aada 250 R CME CreateOne Shota da aa aaan aeae dente aa eds sane aad ee eds as Bae 252 ReMi Destroy iaer cai ede ada eaan daaa a ade an ee aaar aaa ee ate eee Aisa trees 254 RCM Ie Contr Ollie 2222 6 cttae cea ad cee tee een ee A Danse aac dds aaa teed tee asa ded ee eee ates ana 255 RCMP RAG esces sictee cent is tia te eae aac ak ea Ne gia he hg Yeas A acs tat ene Mates cee eect 257 Real time Clock E cause eb eae he eee tie hates eee E at ioe alee ea he Fae aa 258 RiklGs Create iz safest ientre hk ore as ls ne dk he ns alg cots alae a hak Goines a he yal Actin ane 258 R RIC DesttOyins kite ance eatin ae eaa ate eh cases Buel aaa ade
228. Men ee dates fence te 375 4 2 31 Temperature SQNSOF e a cece cece a ae esa aaaeaeceeeeeeesgaaeaeceeeeeeeseeceaeceeeeeeeeeesanaeeeeess 376 1 RalS Createi EETA T tontre Anatase ae a cere Mega eee hee Yd nee Ace ees A Za a 376 2 RTS Destroy onceki ea ie tian Silo an Banca ede ee age 377 3 RTS Controlia na Siete een Led iin eves ei a Ma eda 378 9 sUSage Examples sorokra tra aa A Aa a RAA LET evadanach ATOT RELEET AA ETT aueed 379 DT Glock Generato O OUE a a a aaa a aaea a aae aa aer raaa aiiai 380 52 lnterrupt controls ei i a ae te een ie ae ante ee ee 382 Doty OUP OM iia tactt ie ite sets ee dawunt atcha tain A E das aac AiR eed athens saan 384 5 4 Voltage Detection Circuits onssa iiiar a e a eaa e a aeaa 386 5 5 Frequency Measurement Circuitos eate nans E A EEEE E AEE IE REEE E A EEEa ETER 387 554 Using System 1 vees dsch lage eckslecdece eee ede vedas vlece adi AAA A viade acl sbetdea rnin N 387 552 Using System 2 aerians diae iera EE NAE EA T A R EA A 390 5 6 Low Power Consumption ccceccececcececeeeeeeencae cece ee eeeeceaeaeeeeeeeseccaaeaeeeeeeesececeaeaeeeeeeeseeseseeeeeeeeeeeed 393 5 6 1 Software Standby Mode ccccsecccceeeeccecessenceeeseecceeesseneceeseneceeesnanceaesnseceeesneneeeeeneeceeesneeeeeesnaees 393 5 6 2 Deep Software Standby Mode cccccceeeeeneeeeeecneeeeeenneeeeeeneeeeeecaeeeseeaeeeeeenaeeeeeenaeeeseenaeeeeeeaas 394 Sle Bus Controllet assis csietn ss tae Head ee dn ee een ietciat
229. Multifunction Pin Control registers are modified by this function The cycle count parameters are not checked for validity Use the hardware manual to check these values Setting single write strobe mode is prohibited in the 8 bit bus space A 32 bit data bus width is only supported on the 176 and 177 pin device packages A 32 bit data bus width cannot be specified unless A16 to A23 has been disabled If a 32 bit data bus width has been selected then a multiplexed address and data cannot be used e Do not call this function while the external bus is being accessed R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 135 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Configure CS2 8 bit width maximum cycle counts R_BSC_CreateArea 2 PDL_BSC_WIDTH_8 15 15 7 7 R20UT1963EE0100 Rev 1 00 AS Page 136 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 4 R_BSC_Desiroy Synopsis Prototype Description Return value Category Reference Stop the External Bus Controller bool R_BSC_Destroy uint8_t data Area selection Disable an external bus area data Select the external bus area CSn where n 0 to 7 to be disabled True Bus Controller R_BSC_Cont
230. NCEL_RTCA_DISABLE or PDL_LPC_CANCEL_RTCA ENABLE Prevent or allow the RTC alarm interrupt signal to cancel deep software standby mode PDL_LPC_CANCEL_NMI_DISABLE or PDL_LPC_CANCEL_NMI_FALLING or PDL_LPC_CANCEL_NMI_RISING Prevent or allow an edge on the NMI pin to cancel deep software standby mode PDL_LPC_CANCEL_lICD_DISABLE or PDL_LPC_CANCEL_lICD_FALLING or PDL_LPC_CANCEL_lICD_RISING Prevent or allow an edge on the IIC SDA pin to cancel deep software standby mode PDL_LPC_CANCEL_lICC_DISABLE or PDL_LPC_CANCEL_lICC_FALLING or PDL_LPC_CANCEL_lICC_RISING Prevent or allow an edge on the IIC SCL pin to cancel deep software standby mode PDL_LPC_CANCEL_USB_DISABLE or PDL_LPC_CANCEL_USB_ENABLE PDL_LPC_CANCEL_CAN_DISABLE or PDL_LPC_CANCEL_CAN_FALLING or PDL_LPC_CANCEL_CAN_ RISING Prevent or allow the USB Suspend Resume interrupt signal to cancel deep software standby mode Prevent or allow an edge on the CRX1 DS pin to cancel deep software standby mode data5 Select the main clock oscillator waiting times If no selections are required specify PDL_NO_DATA e Software Standby waiting time PDL_LPC_MAIN_2 or PDL_LPC_MAIN_4 or PDL_LPC_MAIN_8 or PDL_LPC_MAIN_16 or PDL_LPC_MAIN_32 or PDL_LPC_MAIN_64 or PDL_LPC_MAIN_512 or PDL_LPC_MAIN_1024 or PDL_LPC_MAIN_2048 or PDL_LPC_MAIN_4096 or PDL_LPC_MAIN_16384 or PDL_LPC_MAIN_32768 or PDL_LPC_MAIN_65536 or PDL_LPC_MAIN_
231. NF_4 data3 Detection settings Specify PDL_NO_DATA to use the defaults e NACK Transmission Arbitration Lost Detection control PDL_IIC_NTALD_DISABLE or Disable or enable arbitration to be lost when an ACK is PDL_IIC_NTALD_ENABLE detection during transmission of a NACK in receive mode Slave Arbitration Lost Detection control PDL_IIC_SALD_ DISABLE or Disable or enable arbitration to be lost when a mismatch PDL_IIC_SALD_ENABLE occurs during slave data transmission e Slave address detection control PDL_IIC_SLAVE_0_DISABLE or Disable or enable detection of slave address 0 in PDL_IIC_SLAVE_0_ENABLE 7 or 7 bit or PDL_IIC_SLAVE 0 ENABLE 10 10 bit format PDL_IIC_SLAVE_1_DISABLE or Disable or enable detection of slave address 1 in PDL_IIC_SLAVE_1_ENABLE _7 or 7 bit or PDL_IIC_SLAVE_ 1 ENABLE 10 10 bit format PDL_IIC_SLAVE_2 DISABLE or Disable or enable detection of slave address 2 in PDL_IIC_SLAVE_2 ENABLE 7 or 7 bit or PDL_IIC_SLAVE 2 ENABLE 10 10 bit format PDL_IIC_SLAVE_GCA_DISABLE or Disable or enable detection of the General Call PDL_IIC_SLAVE_GCA_ ENABLE address e Device ID detection control PDL_IIC_DEVICE_ID_DISABLE or Disable or enable detection of the Device ID PDL_IIC_DEVICE_ID_ ENABLE address 1111 100b Host Address detection control PDL_IIC_HOST_ADDRESS_DISABLE or Disable or enable detection of the SMBus host P
232. NT_B OxAAFF 0x100 0x5600 R20UT1963EE0100 Rev 1 00 EN ESAS Page 244 of 487 Jul 19 2012 RX63N Group 4 Library Reference 9 R_TMR_ControlPeriodic Synopsis Prototype Description Control periodic operation bool R_TMR_ConirolPeriodic uint8_t data1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection double data3 The new period or frequency double data4 The new pulse width or duty cycle Modify a periodic timer operation data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or The channel n n 0 1 2 or 3 or unit n 0 or 1 to PDL_TMR_TMR3 or be configured PDL_TMR_UNITO or PDL_TMR_UNIT 1 data2 Select the options to be modified Use to separate each selection e Period or frequency calculation PDL_TMR_PERIOD or The parameters data3 and data4 will contain either PDL_TMR_FREQUENCY period and pulse width or frequency and duty cycle Output pin control PDL_TMR_OUTPUT_ENABLE or Enable or disable the periodic output on pin TMOn PDL_TMR_OUTPUT_DISABLE 16 bit operation the pin shall be TMO2 when n ADC trigger control Disable or enable periodic ADC conversion start PDL_TMR_ADC_TRIGGER_OFF or requests PDL_TMR_ADC_TRIGGER_ON Applicable only for channels TMRO or TMR2 or units 0 or 1 Counter stop start PDL_TMR_STOP or PDL_TMR_STA
233. O PDL_CGC_CLK_HOCO or high speed on chip oscillator HOCO PDL_CGC_CLK_MAIN or main clock oscillator PDL_CGC_CLK_SUB _CLOCKor sub clock oscillator PDL_CGC_CLK_PLL Phase locked loop PLL circuit data2 Clock control selection All selections are optional If no change is required specify PDL_NO_DATA If multiple selections are required use to separate each selection e BCLK pin output control ignored if the device package does not support the external bus PDL_CGC_BCLK_ENABLE or F PDL_CGC_BCLK DISABLE Enable or disable the BCLK pin output e Low speed on chip oscillator control PDL_CGC_LOCO_ENABLE or PDL_CGC_LOCO_DISABLE Enable or disable the LOCO e High speed on chip oscillator control PDL_CGC_HOCO_ENABLE or i PDL_CGC_HOCO_ DISABLE Enable or disable the HOCO e High speed on chip oscillator power control PDL_CGC_HOCO_POWER_ON or PDL_CGC_HOCO_POWER_OFF Control the HOCO power supply e Main clock oscillator control PDL_CGC_MAIN_ENABLE or PDL_CGC_MAIN_DISABLE Enable or disable the main clock oscillator e Main clock oscillator forced oscillation control PDL_CGC_MAIN_FORCED_ENABLE or Enable or disable forced oscillation of the main PDL_CGC_MAIN FORCED_ DISABLE clock oscillator e Main clock Oscillation Stop Detection control PDL_CGC_OSC_STOP_ENABLE or Enable without or with interrupt request output PDL_CGC_OSC_STOP_INTERRUPT or or disable
234. O A OAE CET o PE A TE E EEEE TEA A E A A A 355 4 2 28 12 bit Analog to Digital Converter eceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseneaeeeseeeeeeeseeeaeeeseeeaeeeeeeaaes 356 M R ADC 12 Create its echt hs ites a ae ated ha tae a a ate nee ce 356 2 RYADGS12s DESIOY AAAA AEE Meee eae einer a hak ay ces eid ines gee eo nes ahd Yon cette ate 361 3 4 RADCA Controle cs tacre Aha ee ek ee a she net at ne a hk aon ae yt tle 362 4y R amp ADG 212 Reade neeaaea ra ea aan a an Sed ana Det teaa alah Sadaetes anti aae aaa aE Ea Aa edee Rae 363 4 2 29 10 bit Analog to Digital Converter seeessseessrreessrnessrrnessrrnesrennssrunnestennadtennddnnnnantnnnenneanaatennennanne 364 M RADO O S a tes ah see ence e a aah aea 364 2 RADOU Create e teh ease a No ae gs tea a a a Clee te 365 3 RiADCS 10 DE SO hee ties aoe tec tnt Aaa aes ge en caine haa teats dats tence ants 369 A OREADCS 10s Controlls cccente eee ese Meter ones hem eee gh sean nt athe aia a a net 370 BD HRYADCS1OWREAG such ace ase ole ahs sa hoes Aaa eM a Ne Yee tole Aaa eens Boats eect ante 371 4 2 30 10 bit Digital to Analog Converter ceeccececeeneeeeeeeeeeeeeeeeeeeseeeeeeseneeeeeteeeaeeeseeeaeeeseeaaeeeseeaaees 372 D HIRE DACs AO Creates 2 c cies e eee hee Naas tae det intra hie a heats tate Zee cn ee ole 372 2 Re DACS 10 DESWOY sec iets se Ah Aiea ahs tee net a aa ee as en nena hag E She tna tne ae 374 3 sRDAC TAO VWI saci oct hia ee hes sac ees Ais ae as le a Na Yon Tolan hag
235. O PDL_INTC_REG_DTCER_MTU4_ TGIB PDL_INTC_REG DTCER_ICU_IRQ1 PDL_INTC_REG_DTCER_MTU4 TGIC PDL_INTC_REG_DTCER_ICU_IRQ2 PDL_INTC_REG_DTCER_MTU4_ TGID PDL_INTC_REG_DTCER_ICU_IRQ3 PDL_INTC_REG_DTCER_MTU4_TCIV PDL_INTC_REG_ DTCER_ICU_IRQ4 PDL_INTC_REG_DTCER_MTUS5 TGIU PDL_INTC_REG_DTCER_ICU_IRQ5 PDL_INTC_REG_DTCER_MTUS5_TGIV PDL_INTC_REG_ DTCER_ICU_IRQ6 PDL_INTC_REG_DTCER_MTUS_TGIW PDL_INTC_REG_ DTCER_ICU_IRQ7 PDL_INTC_REG_DTCER_TMRO_CMIA PDL_INTC_REG_ DTCER_ICU_IRQ8 PDL_INTC_REG_DTCER_TMRO_CMIB PDL_INTC_REG_DTCER_ICU_IRQQ PDL_INTC_REG_DTCER_TMR1_CMIA PDL_INTC_REG_DTCER_ICU_IRQ10 PDL_INTC_REG_DTCER_TMR1_CMIB PDL_INTC_REG_ DTCER_ICU_IRQ11 PDL_INTC_REG_DTCER_TMR2_CMIA PDL_INTC_REG_ DTCER_ICU_IRQ12 PDL_INTC_REG_DTCER_TMR2_CMIB PDL_INTC_REG_DTCER_ICU_IRQ13 PDL_INTC_REG_DTCER_TMR3_CMIA PDL_INTC_REG_DTCER_ICU_IRQ14 PDL_INTC_REG_DTCER_TMR3_CMIB PDL_INTC_REG_DTCER_ICU_IRQ15 PDL_INTC_REG_DTCER_IICO_RXI PDL_INTC_REG_DTCER_AD_ADI PDL_INTC_REG DTCER IICO_TXI PDL_INTC_REG_DTCER_S12AD_S12ADI PDL_INTC_REG_DTCER_IIC1_RXI PDL_INTC_REG_DTCER_TPUO TGIA PDL_INTC_REG DTCER IIC1_TXI PDL_INTC_REG_DTCER_TPUO_TGIB PDL_INTC_REG_DTCER_IIC2_RXI PDL_INTC_REG_DTCER_TPUO_TGIC PDL_INTC_REG_DTCER IIC2_TXl PDL_INTC_REG_DTCER_TPUO TGID PDL_INTC_REG_DTCER _IIC3_RXI PDL_INTC_REG_DTCER_TPU1_TGIA PDL_INTC_REG_DTCER IIC3_TXI PDL_INTC_REG_DTCER_TPU1_TGIB PDL_INTC_REG_DTCER_DMAC_DMACOI PDL_INTC_REG_DTCER_TPU2_TGIA PDL_INTC_REG_DTCER_DMAC_DMAC1I PDL_INTC_REG_DTCER_TPU2_TGIB PDL_INTC_REG_DTCER_DMAC
236. OFS_IWDT_AUTOSTAR PDL_MCU_OFS_IWDT_TIMEOUT_4096 PDL _MCU_OFS_IWDT_CLOCK_LOCO_16 PDL_MCU_OFS_IWDT_WIN_END_50 PDL _MCU_OFS_IWDT_WIN_START_75 PDL_MCU_OFS_IWDT_NMI PDL MCU_OFS_IWDT_STOP_DISABLE PDL MCU_OFS_WDT_HALTED PDL_MCU_OFS_LVD_0O_ENABLE PDL MCU_OFS_CGC_HOCO_DISABLE R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 111 of 487 RX63N Group 4 Library Reference 4 2 6 Voltage Detection Circuit 1 R_LVD_Create Synopsis Prototype Description Return value Configure the voltage detection circuit bool R_LVD_Create uint16_tdata1 Monitor 1 Configuration selection uint16_t data2 Monitor 2 Configuration selection Set the voltage detection configuration data1 Monitor 1 voltage detection configuration If the monitor is not required specify PDL_NO_DATA otherwise use to separate each selection e Operation PDL_LVD_MONITOR_ONLY or PDL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_DELAY or PDL_LVD_INTERRUPT_NMI_DETECT_RISE or PDL_LVD_INTERRUPT_NMI_DETECT_FALL or PDL_LVD_INTERRUPT_NMI_DETECT_RISE_AND_FALL Select no action a reset on low voltage detection or non maskable interrupt when a specified voltage event is detected e Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL_LVD_FILTER_LOCO_DIV_2 or Configure the digital filter PDL_LVD_FI
237. OGC Set eter ee tests alee srt dads ofa ee ee neared edd a ner art ms abd a a nate 55 2 R CGC C ntrolis nae ennen er a ieee hander Seo tien dante es ea ee 58 3 RaCGGs GetStatus iw iisiisacts iter sachets ties teeta test tached ria a aaa aa teen restr aea a aa ee 61 4 2 2 Interrupt Control Untied sien testers e a eens te chet atider daca len ed nated tee eee 62 1 Re INTC SetExtl nte ru pts igen recdedess ea a tiers a a a aaa aa te ened ees dee dees 62 2 R INTC Create Extinterrul pt inisin hoenear er Heisei ded none ed eae adie 64 3 R_INTC_CreateSoftwarelnterrupt ccceceeeeececeeeeeeecencaeceeeeeeeseceaaaeceeeeeeeseceaeaeceeeeesesensaceeeeees 66 4 R_INTC_CreateFastinterrupt ccccccccceeeeeencececeeeeeceeeanaece cess ee sgeaeaeceeeeeeesesaeaeceeeeesesessineeeeess 67 5 R_INTC_CreateExceptionHandlers c cececcecceceeeeeeeceeeaeceeeeeeesecaeaeceeeeeeesecceaeceeeeesesensineeeeess 71 6 R2INT C ControlExtlintertu ptosis tin eaen tines dace ieee een awed sees dete oe 72 7 R_INTC_GetExtlnterruptStatus cccccccceeeeceecee cece cece cece ecaeceeeeeeesecaeaeeeeeeeeesecaeaeeeeeeeeesecsnnaeeeeees 74 e RE UREN CREA rst Stes poetics da A EE E E E E A 80 oD EEN ROATA E AEE EEEE E E E E E 81 LONGA E IN RO oTe M A ETE EA EA E alta A A E Sahn 82 M R NTO Oeae OOD a a r aa aa Gates tha aa e aE e a aA 83 12 RAINTC ControlGrou Da a a a a a T E a a R a a ease aE 84 13 R INTC GetStat sGro D a m e ae
238. OSI8_PC7 Scig SMOSI8 PDL_SCI_PIN SCI8 SSDA8 amp PC7 SSDA8 PDL_SCI_PIN SCI8 SCK8 PC5 SCK8 PDL SCI_PIN SCI8 CTS8 PC4 CTS8 PDL SCI PIN SCI8 RTS8 PC4 RTS8 PDL_SCI_PIN SCI8 SS8 PC4 SS8 Valid when n 9 PDL SCI PIN SCI9 RXD9 PB6 RXD9 PDL SCI PIN SCI9 SMISO9 PB6 SMISO9 PDL_SCI_PIN SCI9_ SSCL9 PB6 SSCL9 PDL_SCI_PIN SCI9_ TXD9 PB7 TXD9 PDL_SCI_PIN_SCI9_SMOSI9_PB7 Scig SMOSI9 PDL SCI PIN SCI9 SSDA9 PB7 SSDAQ PDL SCI_PIN SCI9_SCK9 PB5 SCK9 PDL SCI PIN SCI9 CTS9 PB4 CTS9 PDL SCI PIN SCI9 RTS9 PB4 RTS9 PDL_SCI_PIN SCI9 SS9 PB4 Ss9 R20UT1963EE0100 Rev 1 00 RENESAS Page 282 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 5 5 Return value Category Reference Remarks Program example e Valid when n 10 PDL_SCI_PIN SCI10 RXD10 P81 RXD10 PDL_SCI_PIN_SCI10_SMISO10_P81 SMISO10 PDL SCI PIN SCI10 SSCL10 P81 SSCL10 PDL_SCI_PIN SCI10_TXD10 P82 TXD10 PDL_SCI_PIN_SCI10_SMOSI10_P82 sco SMOSI10 PDL SCI PIN SCI10 SSDA10 P82 SSDA10 PDL_SCI_PIN_SCI10_SCK10_P80 SCK10 PDL_SCI_PIN_SCI10_CTS10_P83 CTS10 PDL_SCI_PIN_SCI10_RTS10_P83 RTS10
239. OSTSTF POE8 0 Not detected 0 No request 1 Detected 1 Requested b7 b6 b5 b4 b3 b2 b1 bO 0 No request 1 Requested Returnvalue True Category Port Output Enable Reference R_POE_Control Remarks e Use R_POE_Control to clear the flags Program example RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t StatusFlags Read the POE status R_POE_GetStatus amp StatusFlags R20UT1963EE0100 Rev 1 00 R AS Page 206 of 487 Jul 19 2012 SENES RX63N Group 4 2 16 1 R_TPU Set Synopsis Prototype Description 1 2 R20UT1963EE0100 Rev 1 00 Jul 19 2012 16 bit Timer Pulse Unit Configure the Timer Pulse Unit pins bool R_TPU_Set uint8_t data1 4 Library Reference Channel selection uint32_tdata2 Pin configuration Initialise the TPU pins data1 The channel number n where n 0 to 11 data2 Configure the TPU input and output pins for the channel Use to separate each selection e Validwhenn 0 PDL_TPU_PIN_AO_P86 or PDL_TPU_PIN AO PAO Select the P86 or PAO pin for TIOCAO PDL_TPU_PIN_BO_P17 or PDL_TPU_PIN BO _PA1 PDL_TPU_PIN_DO_P33 or PDL_TPU_PIN DO PA3 Select the P17 or PA1 pin for TIOCBO PDL_TPU_PIN_CO_P32 Select the P32 pin for TIOCCO
240. O_FUNC Send 50 bytes of binary data on channel 1 R_SCI_Send 1 PDL_NO_DATA data_store 50 PDL_NO_FUNC Send the ID byte 0x0A shifted into the upper byte R_SCI_Send 2 PDL_SCI_MP_ID_CYCLE 0x0A00 PDL_NO_PTR 0 PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 292 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_SCI_ Receive Synopsis Prototype Description Receive data on a SCI channel bool R_SCI_Receive uint8_t data1 Channel selection uint16_t data2 Channel configuration and Station ID of receiving device uint8_t data3 Data start address uint16_t data4 Receive threshold void func Callback function void func2 Callback function Enable SCI reception and acquire any incoming data data1 Select channel SCIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SCI_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_SCI_DTC_TRIGGER_ENABLE received e ID reception control valid only in Multi processor mode Use the upper byte as the station ID PPR CLMPIDEC IGLE The valid ID range is 0 to 255 data3 The start address of the storage area for the expected data Specify PDL
241. O_PTR PDL_NO_PTR PDL_NO_PTR R20UT1963EE0100 Rev 1 00 Page 154 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 4 2 12 External DMA Controller 1 R_EXDMAC Set Synopsis Prototype Description Return value Category Reference Remarks Program example Configure the EXDMAC pins bool R_EXDMAC_Set uint8_t data1 Channel selection uint16_t data2 Pin configuration Set up the global EXDMAC options data1 The channel number n where n O or 1 data2 Configure the EXDMAC pins for the channel Use to separate each selection e Valid when n 0 PDL_EXDMAC_PIN_EDREQO_P22 or PDL_EXDMAC_PIN_EDREQO_P55 or Select the pin for EDREQO PDL_EXDMAC PIN EDREQO P80 PDL_EXDMAC_PIN_EDACKO_P23 or PDL_EXDMAC_PIN_EDACKO_ P54 or Select the pin for EDACKO PDL _EXDMAC_ PIN EDACKO P81 e Valid when n 1 PDL_EXDMAC_PIN_EDREQ1_ P24 or PDL_EXDMAC_PIN_EDREQ1_ P57 or Select the pin for EDREQ1 PDL _EXDMAC PIN EDREQ1 P82 PDL_EXDMAC_PIN_EDACK1_P25 or PDL_EXDMAC_PIN_EDACK1_P56 or Select the pin for EDACK1 PDL_EXDMAC_PIN_EDACK1_P83 True if all parameters are valid and exclusive otherwise false EXDMA Controller None e Before calling the RLEXDMAC_Create function call this function to configure the relevant pins if required e Call this function multiple times if more than one c
242. OxFF for a port 0 or 1 for a pin func The function to be called if a match occurs True if the parameters are valid otherwise false Program example Category I O port References R_IO_PORT_Set Remarks e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void IoHandlerl void IoHandler2 void func void Call function IoHandlerl if port pin P05 is high R_IO_PORT_Compare PDL_IO_PORT_0_5 1 ToHandlerl i Call function IoHandler2 if port 6 reads as 0x55 R_IO_PORT_Compare PDL_IO_PORT_6 0x55 ToHandler2 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 98 of 487 Jul 19 2012 RX63N Group 4 Library Reference 7 RIO PORT_Modify Synopsis Prototype Description Return value Category References Remarks Program example R20UT1963EE0100 Rev 1 00 Jul 19 2012 Modify the pin states on an I O port bool R_IO_PORT_Modify uint16_t data1 Output port or port pin selection uint16_t data2 Logical operation uint8_t data3 Modification value Read the output state of an I O port or I O port pin modify the result and write it b
243. PCLK 1 Valid for n 0 3 6 and 9 PDL_TPU_A_IC_TPU_CM_IC Input capture at TPU n 1 TGRA compare match or input compare Valid for n 1 4 7 and 10 Input capture output compare control for register TGRB PDL_TPU_B_OC DISABLED or PDL_TPU_B_OC_LOW or PDL_TPU_B_OC_LOW_CM HIGH or PDL_TPU_B_OC_LOW_CM_INV or PDL_TPU_B_OC_HIGH_CM_LOW or PDL_TPU_B_OC_HIGH or PDL_TPU_B_OC_HIGH_CM_INV or TIOCBn output disabled TIOCBn output low TIOCBn initial output low goes high at compare match TIOCBn initial output low toggles at compare match TIOCBn initial output high goes low at compare match TIOCBn output high TIOCBn initial output high toggles at compare match PDL_TPU_B_IC_RISING_EDGE or PDL_TPU_B_IC_FALLING EDGE or PDL_TPU_B_IC_BOTH_EDGES or Input capture at TIOCBn or TIOCAn rising edge Input capture at TIOCBn or TIOCAn falling edge Input capture at TIOCBn or TIOCAn both edges See below for TIOCBn or TIOCAn pin selection PDL_TPU_B_IC_TPU_COUNT_CLK or PDL_TPU_B_IC_TPU_CM_IC Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 Valid for n 0 3 6 and 9 Input capture at TPU n 1 TGRC compare match or input compare Valid forn 1 4 7 and 10 TGRB input capture input selection PDL_TPU_B_IC_TIOCB or PDL_TPU_B IC TIOCA Input capture using pin TIOCBn or TIOCAn R20UT1963EE0100
244. PCLK_DIV_16 or PDL_MTU2_ CLKW_PCLK_DIV_64 Counter TCNTV is supplied by the internal clock signal PCLKB 1 4 16 or 64 Counter TCNTW is supplied by the internal clock signal PCLKB 1 4 16 or 64 Counter clearing U V and W counters Va lid for n 5 PDL_MTU2_CLEAR_TGRU_DISABLE or PDL_MTU2 CLEAR TGRU_ ENABLE Disable or enable clearing of TCNTU by TGRU compare match or input capture PDL_MTU2_CLEAR_TGRV_DISABLE or PDL_MTU2_CLEAR_TGRW_DISABLE or PDL_MTU2_ CLEAR TGRW_ENABLE PDL_MTU2 CLEAR TGRV_ ENABLE compare match or input capture Disable or enable clearing of TCNTV by TGRV Disable or enable clearing of TCNTW by TGRW compare match or input capture ADC_irigger_operation Configure the ADC trigger operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e ADC conversion trigger control Valid for n 0 to 4 unless stated otherwise PDL_MTU2_ADC_TRIG_TGRA_DISABLE PDL_MTU2_ADC_TRIG_TGRA_ENABLE Disable or enable ADC start requests on aTGRA compare match or input capture or PDL_MTU2_ADC_TRIG_TROUGH_DISAB PDL_MTU2_ADC_TRIG_TROUGH_ENABLE Disable or enable ADC start requests on aTCNT underflow Valid for n 4 in complementary PWM mode LE or Control ADC trigger interrupt skipping Valid for n 4 i
245. PDL_ADC_12_CHANNEL_2 PDL_ADC_12 CHANNEL 3 PDL_ADC_12_CHANNEL_4 PDL_ADC_12_CHANNEL_5 PDL_ADC_12_CHANNEL_6 PDL_ADC_12_CHANNEL_7 PDL_ADC_12_CHANNEL _8 PDL_ADC_12_CHANNEL_9 PDL_ADC_12_CHANNEL_10 PDL_ADC_12_CHANNEL_11 PDL_ADC_12_CHANNEL_12 PDL_ADC_12_CHANNEL_13 PDL_ADC_12_CHANNEL_14 PDL_ADC_12_CHANNEL_15 PDL_ADC_12_CHANNEL_16 PDL_ADC_12_CHANNEL_17 PDL_ADC_12_CHANNEL_18 PDL_ADC_12_CHANNEL_19 PDL_ADC_12_CHANNEL_20 Carry out a conversion on each of the selected channels ANO to AN20 R20UT1963EE0100 Jul 19 2012 Rev 1 00 2tEN ESAS Page 356 of 487 RX63N Group 4 Library Reference Description 2 4 data3 Conversion options To set multiple options at the same time use to separate each value The default settings are shown in bold Scan mode PDL_ADC_12_SCAN_SINGLE or PDL_ADC_12_SCAN_CONTINUOUS Select Single scan or Continuous scan mode See the Remarks section Continuous mode is only available when reading the analog inputs e Clock division PDL_ADC_12_DIV_1 or PDL_ADC_12_DIV_2 or PDL_ADC_12_DIV_4or PDL ADC 12 DIV 8 Use the peripheral clock PCLK 1 2 4 or 8 Data alignment The alignment of the 12 bit ADC conversion result within the 16 bit register Ignored for channels using value addition mode the 14 bit result is always left aligned PDL_ADC_12_DATA_ALIGNMENT_LEFT or PDL_ADC_12_
246. PDL_DTC_TRIGGER MTU TGIB4 or PDL_DTC_TRIGGER_MTU_TGIC4 or PDL_DTC_TRIGGER_MTU_TGID4 or Input capture compare match signals on MTU channel 4 PDL_DTC_TRIGGER_MTU_TCIV4 or Counter over or underflow on MTU channel 4 PDL_DTC_TRIGGER_MTU_TGIU5 or PDL_DTC_TRIGGER_MTU_TGIV5 or PDL_DTC_TRIGGER_MTU_TGIW5 or Input capture compare match signals on MTU channel 5 PDL_DTC_TRIGGER_CMIAO or PDL_DTC_TRIGGER_CMIA1 or PDL_DTC_TRIGGER_CMIA2 or PDL_DTC_ TRIGGER _CMIA3 or Compare match A on TMR channel n n 0 to 3 PDL_DTC_ TRIGGER _CMIBO or PDL_DTC_TRIGGER_CMIB1 or PDL_DTC_TRIGGER_CMIB2 or PDL_DTC_TRIGGER_CMIB3 or PDL_DTC_TRIGGER_IICO_RX or PDL_DTC_TRIGGER_IIC1_RX or PDL_DTC_TRIGGER_IIC2_RX or PDL_DTC_TRIGGER_IIC3_RX or Compare match B on TMR channel n n 0 to 3 Receive buffer full on I C channel n n 0 to 3 PDL_DTC_TRIGGER_IICO_TX or PDL_DTC_TRIGGER_IIC1_TX or PDL_DTC_TRIGGER_IIC2_TX or PDL_DTC_TRIGGER_IIC3_TX or Transmit buffer empty on I C channel n n 0 to 3 PDL_DTC_TRIGGER_DMACIO or PDL_DTC_TRIGGER_DMACI1 or PDL_DTC_TRIGGER_DMACI2 or PDL_DTC_TRIGGER_DMACIS3 or Transfer complete on DMAC channel n n 0 to 3 PDL_DTC_TRIGGER_EXDMACIO or PDL_DTC_TRIGGER_EXDMACI1 or PDL_DTC_TRIGGER_RXIO
247. PDL_IO PORT 4 2 PDL_IO PORT 4 3 PDL_IO PORT_4 4 PDL_IO PORT 4 _5 PDL_IO_PORT_4 6 PDL_IO PORT _4_7 PDL_IO_PORT_INPUT Configure port pin P21 as an N channel open drain output R_IO_PORT_Set PDL_IO_PORT_2_1 PDL_IO_PORT_OUTPUT PDL_IO_PORT_TYPI Read the value of all the pins on port R_IO_PORT_Read PDL_IO_PORT_4 amp result Set pin P21 to output high R_IO_PORT_Write PDL_IO PORT 2 1 1 i Invert pin P21 R_IO_PORT_Modify PDL_IO_PORT_2_1 PDL_IO_PORT_XOR i And the value on port 4 with 55h R_IO_PORT_Modify PDL_IO_PORT_4 PDL_IO_PORT_AND 0x55 Read the control registers for port PC R_IO_PORT_ReadControl PDL_IO_PORT_C PDL_IO_PORT_TYP amp register_value R20UT1963EE0100 Rev 1 00 Page 384 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Read the direction for pin P03 R_IO_PORT_ReadControl PDL_IO_PORT_0_3 PDL_IO_PORT_DIRECTION amp register_value Set the lower 4 bits on port P1 to output R_IO_PORT_ModifyControl PDL_IO_PORT_1 PDL_IO PORT DIRECTION PDL_IO_PORT_OR Ox0OF Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL_IO_PORT_A_3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR Figure 5 3 Examples of I O Port Operations R20UT1963EE0100 Rev 1 00 AS Page 385 of 487 Jul 19 2012 RENES
248. PDL_IO_PORT_5 6 Port pin P56 PDL_IO_PORT_A_6 Port pin PAs PDL_IO_PORT_1_0 Port pin P1o PDL_IO_PORT_5_7 Portpin P57 PDL_IO PORT_A 7 Port pin PA PDL_IO_PORT_1_1 Port pin P14 PDL_IO_PORT_1_2 Port pin P12 PDL_IO_PORT_6_0 Port pin P6o PDL_IO PORT _B_0 Port pin PBo PDL_IO_PORT_1_3 Port pin P13 PDL_lIO_PORT_6_1 Port pin P6 PDL_IO_PORT_B_1_ Port pin PB PDL_IO_PORT_1_4 Port pin P14 PDL_IO_PORT_6_2 Port pin P62 PDL_IO_PORT_B 2 Port pin PB PDL_IO_PORT_1_5 Port pin P15 PDL_IO_PORT_6_3_ Port pin P63 PDL_IO_PORT_B_3 Port pin PB3 PDL_IO_PORT_1_6 Port pin P16 PDL_IO_PORT_6 4 Port pin P64 PDL_IO PORT_B 4 Port pin PB4 PDL_IO_PORT_1_7 Port pin P17 PDL_IO_PORT_6_5 Port pin P65 PDL_IO_PORT_B 5 Port pin PBs PDL_IO_PORT 6 6 Port pin P6 PDL_IO PORT _B 6 Port pin PBe PDL_IO_PORT_2_0 Port pin P2o PDL_IO_PORT_6_7 Port pin P67 PDL_IO_PORT_B 7 Port pin PB7 PDL_IO_PORT_2_1 Port pin P2 PDL_IO_PORT_2_2 Port pin P22 PDL_IO_PORT_7_0 Port pin P7o PDL_IO_PORT_C_0O Port pin PCo PDL_IO_PORT_2_3 Port pin P23 PDL_IO_PORT_7_1 Port pin P71 PDL_IO_PORT_C_1_ Port pin PC PDL_IO_PORT_2_4 Port pin P24 PDL_IO_PORT_7_2 Port pin P72 PDL_IO PORT C_2 Port pin PC2 PDL_IO_PORT_2_5 Port pin P25 PDL_IO_PORT_7_3 PortpinP73 PDL_IO PORT_C_3 Port pin PCs PDL_IO_PORT_2 6 Port pin P26 PDL_IO_PORT_7_4 Port pin P74 PDL_IO PORT_C 4 Port pin PC PDL_IO_PORT_2_7 Port pin P27 PDL_IO_PORT_7_5 PortpinP7s PDL
249. PDL_TPU_D_OC_HIGH_CM_LOW or PDL_TPU_D_OC_HIGH or PDL_TPU_D_OC_HIGH_CM_INV or TIOCDn output disabled TIOCDn output low TIOCDn initial output low goes high at compare match TIOCDn initial output low toggles at compare match TIOCDn initial output high goes low at compare match TIOCDn output high TIOCDn initial output high toggles at compare match PDL_TPU_D_IC_RISING_EDGE or PDL_TPU_D_IC_FALLING EDGE or PDL_TPU_D_IC_BOTH EDGES or Input capture at TIOCDn or TIOCCn rising edge Input capture at TIOCDn or TIOCCn falling edge Input capture at TIOCDn or TIOCCn both edges See below for TlOCDn or TIOCCn pin selection PDL_TPU_D_IC_TPU_COUNT_CLK Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 e TGRD input capture input selection PDL_TPU_D_IC_TIOCD or PDL_TPU_D_IC_TIOCC Input capture using pin TIOCDn or TIOCCn data6 The timer counter value data7 The register TGRA value data8 The register TGRB value data9 The register TGRC value ignored for n 0 3 6 or 9 data10 The register TGRD value ignored for n 0 3 6 or 9 func1 The function to be called when a TGRA event occurs Specify PDL_NO_FUNC if not required func2 The function to be called when a TGRB event occurs Specify PDL_NO_FUNC if not required R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 213 of 487 RX
250. Page 398 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples BSC error callback function void BSC_error_handler void Clear the error signals R_BSC_Control PDL_BSC_ERROR_CLEAR Figure 5 9 Example of using the Bus Controller R20UT1963EE0100 Rev 1 00 AS Page 399 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 7 2 External bus SDRAM area Figure 5 10 shows an example of accessing SDRAM PDL functions include r_pdl_bsc h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h SDRAM size define SDRAM NUM_BYTES 16 1024 1024 Main clock frequency Hz define FREQ_MAIN 12E6 void main void uintl6_t sdram_location_16 uint32_t index Configure clocks Run from PLL and enable the SDRAM clock SDCLK Prepare the main clock settings R_CGC_Set L_CGC_CLK_MAIN CGC_SDCLK_ENABLE PDL_CGC_BCLK_DISABLE MAIN MAIN 4 MAIN 4 MAIN 4 MAIN 4 MAIN 4 L_NO_DATA L_NO_DATA UU Ae g g hj Prepare the PLL clock settings R_CGC_Set PDL_CGC_CLK_PLL PDL_CGC_SDCLK_ENABLE PDL_CGC_BCLK_DISABLE 192E6 96E6 48E6 48E6 24E6 24E6 PDL_NO_DATA PDL_NO_DATA Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA
251. Periodmax_unit fmax frare 25 mz 24m 625 oui amie 2 MHz MIN_CHANNEL Lou 23 8 Hz 22 9 Hz 5 96 Hz 5 7 Hz 3 81 Hz f Treize 0 0931 0 0894 0 0232 0 0224 0 0149 MIN UNIT 22 Hz Hz Hz Hz Hz e If the requested period is not a multiple of the timer resolution the actual time period will be more than the requested time period e The actual duty cycle will be less than the requested duty cycle if the resulting pulse width is not a multiple of the timer resolution e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT1963EE0100 Rev 1 00 ae AS Page 236 of 487 Jul 19 2012 ENES RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure pin TMO1 for 500ns period 200ns pulse width R_TMR_CreatePeriodic PDL_TMR_TMR1 PDL_TMR_PERIOD PDL_TMR_OUTPUT_HIGH 500E 9 200E 9 PDL_NO_FUNC PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 Jul 19 2012 Configure pin TMO1 for 5MHz frequency 60 duty cycle R_TMR_CreatePeriodic PDL_TMR_TMRI1 PDL_TMR FREQUENCY PDL_TMR_OUTPUT_HIGH 5E6 60 PDL_NO_FUNC PDL_NO_FUNC 0 2tEN ESAS Page 237 of 487 RX63N Group 4 Library Reference
252. R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 182 of 487 RX63N Group 4 Library Reference Description 7 9 TGR_U_V_W_ operation Configure the input capture compare match control for general registers TGRU TRGV and TGRW Valid for n 5 The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture compare match control for register TGRU PDL_MTU2_U_CM or PDL_MTU2_U_IC_RISING_EDGE or PDL_MTU2_U_IC_FALLING_EDGE or PDL_MTU2_U_IC_BOTH EDGES or Compare match Input capture at MTICnU rising edge Input capture at MTICnU falling edge Input capture at MTICnU both edges PDL_MTU2_U_IC_PWM_LOW_TROUGH or PDL_MTU2_U_IC_PWM_LOW_CREST or PDL_MTU2_U_IC_ PWM LOW _BOTH or Input capture at trough crest or both for low pulse width measurement PDL_MTU2_U_IC_PWM_HIGH_TROUGH or PDL_MTU2_U_IC_PWM_HIGH_CREST or PDL_MTU2_U_IC_PWM_HIGH_BOTH Input capture at trough crest or both for high pulse width measurement PDL_MTU2_V_IC_RISING_EDGE or PDL_MTU2_V_IC_FALLING_EDGE or Input capture compare match control for register TGRV PDL_MTU2_V_CMor Compare match Input capture at MTICnV rising edge Input capture at MTICnV falling edge PDL_MTU2_V_IC_BOTH_EDGES or Input capture at MTICnV both edges PDL_MTU2_V_IC_PWM_LOW_TROUGH or Input capture at trough PDL_MTU2_V_IC_PWM_LOW_C
253. R20UT1963EE0100 Rev 1 00 R AS Page 226 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 4 2 18 8 bit Timer 1 R_TMR Set Synopsis Prototype Description Return value Configure the optional TMR pins bool R_TMR_Sei uint8_t data1 Channel selection uint32_t data2 Pin configuration Set up the global TMR options data1 The channel number n where n 0 1 2 or 3 data2 Configure the TMR input and output pins for the channel Use to separate each selection e Validwhenn 0 PDL TMR IMRO THON PEs or Select the pins for TMOO PDL_TMR_TMRO_TMCIO_ P01 or PDL_TMR_TMRO_TMCIO_P21 or Select the pins for TMCIO PDL_TMR_TMRO TMCIO PB1 PDL_TMR_TMRO_TMRIO_ POO or PDL_TMR_TMRO_TMRIO_P20 or Select the pins for TMRIO PDL_TMR_TMRO_TMRIO_ PA4 e Valid when n 1 PDL_TMR_TMR1_TMO1_P17 or PDL_TMR_TMR1_TMO1 P26 PDL_TMR_TMR1_TMCI1_ P02 or PDL_TMR_TMR1_TMCI1_ P12 or PDL_TMR_TMR1_TMCI1_P54 or PDL_TMR_TMR1_TMCI1_PC4 PDL_TMR_TMR1_TMRI1_ P24 or PDL_TMR_TMR1_TMRI1_PB5 Select the pins for TMO1 Select the pins for TMCI1 Select the pins for TMRI1 e Valid when n 2 PDL_TMR_TMR2_TMO2_P16 or PDL_TMR_TMR2 TMO2 PC7 PDL_TMR_TMR2_TMCI2_ P15 or PDL_TMR_TMR2_TMCI2_P31 or Select the pins for TMCI2 PDL_TMR_TMR2_ TMCI2 PC6 PDL_TMR_TMR2_TMRI2_P14 or PDL_TMR_TMR2 TMRI2 PC5 Sel
254. RAM _NUM_BYTES 2 index 2 sdram_location_16 index OxAAAAu sdram_location_16 index 1 0x5555u Read SDRAM and check contents are as expected for index 0 index lt SDRAM_NUM_BYTES 2 index 2 if sdram_location_16 index OxAAAAu Error while 1 if sdram_location_16 index 1 0x5555u Error while 1 while 1 Figure 5 10 Example of using the Bus Controller to access SDRAM R20UT1963EE0100 Rev 1 00 Page 401 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 8 DMA controller The following example shows the use of triggers by software and IRQ pin edge detection Channel 0 will copy the string Renesas RX63N into the destination area when a falling edge occurs on pin IRQ2 P32 Channel 1 will copy the string Hello World into the destination area as soon as it is enabled PDL functions and definitions include r_pdl_dmac h include r_pdl_intc h include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Callback function prototype void DMACO_transfer_end_handler void Data source and destination declarations const char source_string_1 Renesas RX63N const char source_string_2 Hello World volatile uint8_t destination_string_1 volatile uint8_t
255. RAM_ENABLE or PDL_MCU_RAM_DISABLE Enable or disable the on chip RAM Software reset control PDL_MCU_RESET_START Start a software reset of the MCU e Start type flag control PDL_MCU_WARM_START Set the Start type status flag to Warm Return value True if a valid register is specified otherwise false Category MCU registers References R_CGC_Set R_RTC_Create Remarks e If R_CGC_Set is used to configure the sub clock oscillator or R_LRTC_Create is called the Start type status flag will be set to Warm In either case do not use this function to set the flag to Warm Program example RPDL definitions include r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void func void Modify the MCU operation R_MCU_Control PDL_MCU_ROM_DISABLE i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 106 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_MCU_GetStatus Synopsis Prototype Description Read the MCU status bool R_MCU_GetStatus uint16_t data1 The location where the mode status flags shall be stored uint16_t data2 The location where the reset status flags shall be stored uint32_t data3 The storage location for the Option Function Select Register 0 uint32_t data4 The storage location for the Option Function Select Register 1 Read
256. REST or crest or PDL_MTU2_V_IC_PWM_LOW_BOTH or both for low pulse width measurement PDL_MTU2_V_IC_PWM_HIGH_TROUGH or Input capture at trough PDL_MTU2_V_IC_PWM_HIGH_CREST or crest or PDL_MTU2_V_IC_PWM_HIGH_BOTH both for high pulse width measurement PDL_MTU2_W_CM or Input capture compare match control for register TGRW Compare match PDL_MTU2_W_IC_RISING_EDGE or PDL_MTU2_W_IC_FALLING_EDGE or PDL_MTU2_W_IC_BOTH EDGES or Input capture at MTICnW rising edge Input capture at MTICnW falling edge Input capture at MTICnW both edges PDL_MTU2_W_IC_PWM_LOW_TROUGH or _ Input capture at trough PDL_MTU2_W_IC_PWM_LOW_CREST or crest or PDL_MTU2_W_IC_PWM_LOW_BOTH or both for low pulse width measurement PDL_MTU2_W_IC_PWM_HIGH_TROUGH or Input capture at trough PDL_MTU2_W_IC_PWM_HIGH_CREST or crest or PDL_MTU2_W_IC_PWM_HIGH_BOTH both for high pulse width measurement R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 183 of 487 RX63N Group 4 Library Reference Description 8 9 noise_filter_operation Noise filter control for register NFCRn n 0 to 5 The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Noise filter control for register NFCRn PDL_MTU2_NF_A_U_ DISABLE or Enable or disable noise filter for MTIOCnA n 0 to PDL_MTU2_NF_A_U_ ENABLE 4 or TIOC5U n 5
257. RG calculator 3 R_CRC_Write Write data into the CRC calculation register 4 R_CRC_Read Read the CRC calculation result 1 R_ADC_12 Create Configure the 12 bit ADC unit 12 bit Analog to 2 R_ADC_12_ Destroy Shut down the ADC unit Digital converter 3 R_ADC_12_ Control Start or stop the ADC unit 4 R_ADC_12_Read Read the ADC conversion results 1 R_ADC_10_Set Select the I O pins for 10 bit ADC 40 bit Analog to 2 R_ADC_10_ Create Configure a 10 bit ADC unit a 3 R_ADC_10_ Destroy Shut down an ADC unit Digital converter 4 R_ADC_10 Control Start or stop an ADC unit 5 R_ADC_10_ Read Read the ADC conversion results 10 bit Digital to 1 R_DAC_10_ Create Configure the 10 bit DAC module Analog 2 R_DAC_10_ Destroy Disable a DAC channel converter 3 R_DAC_10_Write Write data to a DAC channel Temperature 1 R_TS_Create Configure the Temperature Sensor 2 R_TS_Destroy Shut down the Temperature Sensor sensor 3 R_TS_Control Control the Temperature Sensor operation R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 53 of 487 RX63N Group 4 Library Reference 4 2 Description of Each API This section describes each API and explains how to use them showing a program example for each The description of each API is divided into the following items Synopsis Summarises processing by the API function Prototype The function format and a brief explanation of the arguments Description Explains how to use the API function and shows
258. RRAY_2_ SIZE EEPROM_MEMORY_ADDRESS_LOWER 5 0x66 0x77 0x88 0x99 OxAA OxBB OxCC OxDD OxEE OxFF uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure the DTC controller R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table Set up a DTC channel for IIC transmission R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOU FE ADDRESS_P PDL_DTC_DESTINATION_ADDR PDL_DTC_SIZE_8 PDL_DTC_IRQ_COMPLETE PDL_DTC_TRIGGER_IICO_TX dtc_iicl_tx_transfer_data eeprom_data_array_l uint8_t amp RIICO ICDRT ARRAY _1_SIZE R20UT1963EE0100 Rev 1 00 AS Page 454 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples PDL_NO_DATA Set up a DTC channel for IIC reception This will read back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_FIXED PDL _DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DTC_IRQ_COMPLETE PDL_DTC_TRIGGER_IICO_RX dtc_iicl_rx transfer data uint8_t amp RIIC0 ICDRR data_storage ARRAY_1_SIZE 2 Array size written sub address byte last byte PDL_NO_DATA
259. RT ch3_param ters register_selection PDL_MTU2_REGISTER_COUNTER PDL_MTU2_REGIS TER_TGRB ch3_parame ch3_parame Modify R_MTU2_Con 3 ters TCNT_TCNTU_value ters TGRB_TCNTW_value OxFFDD 0x0020 the operation of channel 3 trolChanneli amp ch3_parameters R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 190 of 487 RX63N Group 4 Library Reference 5 Synopsis Prototype Description 1 4 R_MTU2_ConirolUnit Control a Multi function Timer Pulse Unit bool R_MTU2_ConirolUnit uint8_t data1 Unit selection R_MTU2_ControlUnit_structure data2 A pointer to the structure R_MTU2_ControlUnit_structure members uint16_t simultaneous_control Control selection uint32_t output_control uint32_t buffer_control Control selection Control selection uint16_t brushless DC_motor_control Control selection uint32_t general_control uint8_t register_selection uint16_t TDDR_value uint16_t TCDR_value uint16_t TCBR_value Modify a timer unit s registers data1 The unit number n where n 0 simultaneous_control Control selection Register selection Register value Register value Register value Simultaneous stop start control All selections are optional If multiple selections are required use to separate each selection Specify
260. RT Disable or re enable the counter clock source data3 The new period or frequency This will be ignored if a timing change is not requested data4 The new pulse width or duty cycle This will be ignored if a timing change is not requested Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreatePeriodic Remarks See the remarks for R_TMR_CreatePeriodic R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 245 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Change timer TMR1 to 600ns period R_TMR_ControlPeriodic PDL_TMR_TMRI1 PDL_TMR_PERIOD 600E 9 100E 9 100ns pulse width R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 246 of 487 RX63N Group 4 Library Reference 10 R_TMR_ReadChannel Synopsis Prototype Description Return value Category Reference Remarks Program example Read from timer channel registers bool R_TMR_ReadChannel uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint8_t data3 A pointer to the data storage location uint8_t data4 A pointer to the data storage location uin
261. RTC_CAPTURE_FILTER_ON_DIV_1 or enabling select the sampling period PDL_RTC_CAPTURE_FILTER_ON_DIV_32 relative to the count source data11 Configure the clock periodic interrupt Periodic interrupt selection PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256_HZ or PDL_RTC_PERIODIC_128_ HZ or PDL_RTC_PERIODIC_64_HZ or PDL_RTC_PERIODIC_32_HZ or The frequency or interval for periodic interrupt PDL_RTC_PERIODIC_16_HZ or requests PDL_RTC_PERIODIC_4 HZ or PDL_RTC_PERIODIC_2_HZ or PDL_RTC_PERIODIC_1_HZ or PDL_RTC_PERIODIC_2S Return value True if all parameters are valid and exclusive otherwise false Category Real time clock Reference R_RTC_Create RLRTC_Read R_CGC_Control R_CGC_Set Remarks e Refer to R_RTC_Create for the time and date formats Ifthe current time or date values are updated the clock is stopped during the update If the day of week is updated using automatic calculation the most recent year month and date will be used e The range checking for either day value uses the most recent year and month values e If entering software standby or deep software standby mode soon after modifying the RTC values use R_RTC_Read first to confirm that the values are correct e If the output of the RTCOUT pin is enabled or disabled the clock is stopped during the update e If capture is enabled for a capture pin that has not been selected in R_RTC_Create this function will return false If R_RTC_Create h
262. RT_9_5 Port pin P95 PDL_IO_PORT_E_5 Port pin PEs PDL_IO_PORT_9 6 PortpinP9 PDL_IO_PORT_E 6 Port pin PEs PDL_IO_PORT_9_7 Port pin P97 PDL_IO_PORT_E 7 Port pin PE7 R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 89 of 487 Jul 19 2012 RX63N Group 4 Library Reference PDL_IO_PORT_ Port pin PFo PDL_IO PORT G0 PortpinPGy PDL_IO PORT_ Port pin PKo PDL_IO PORT Port pin PF4 PDL_IO PORT G1 PortpinPG PDL_IO PORT_ Port pin PK PDL_IO PORT Port pin PF2 PDL IO PORT G 2 PortpinPG PDL_IO PORT_ Port pin PK PDL_I1O PORT Port pin PFs PDL IO PORT G 3 PortpinPGs PDL_IO PORT Port pin PK3 PDL_IO PORT Port pin PF4 PDL_IO PORT G 4 PortpinPG PDL_IO PORT Port pin PK PDL_IO PORT Port pin PFs PDL_IO PORT G 5 PortpinPG PDL_IO PORT Port pin PKs PDL_IO PORT G 6 Port pin PGs PDL_IO PORT_ Port pin PKs PDL_1O PORT G 7 PortpinPG PDL_IO PORT Port pin PK7 PDL_IO_PORT_H 4 Port pin PH PDL_IO_ PORT Port pin PLo PDL IO PORT H 5 Portpin PHs PDL_IO PORT Port pin PL PDL_IO_PORT_ Port pin PL2 PDL IO PORT J 3 Portpin PJ PDL_IO_PORT Port pin PL PDL_IO PORT_J 5 Portpin PJs PDL_IO_PORT_ Port pin PL4 Note Refer to the hardware manual for the port pins which are available on the device that you have selected R20UT1963EE0100 Rev 1 00 Jul 19 2
263. RX63N Group 4 Library Reference 3 R_lO_PORT_ModifyControl Synopsis Prototype Description Modify an I O port s control registers bool R_IO_PORT_ModifyConirol uint16_t data1 Port or port pin selection uint8_t data2 Control register and logical operation selection uint16_tdata3 Modification value Modifying the operation of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 Select the register to be modified and the logical operation using to separate the selections e The control register to be modified PDL_IO_PORT_DIRECTION or Data direction PDL_IO_PORT_MODE or General or Peripheral I O mode control PDL_IO_PORT_TYPE or Open drain control PDL_IO_PORT_PULL_UP or Pull up control Drive capacity control PDL IO _PORT_DRIVE Valid for ports 0 2 5 to 7 9 to E and G e The logical operation to be applied to the control register PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PDL_IO_PORT_XOR data3 The value to be used for the modification using one of the formats below Pin not PE1 open drain control b15 b1 bO Do not care Oor1 Pin PE1 open drain control b15 b2 b1 b0 D
264. R_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRIn PDL_TMR_CLEAR_RESET_HIGH Cleared when the external reset pin TMRIx x 0 or 2 for n 0 or 1 is high ADC trigger control PDL_TMR_ADC_TRIGGER_DISABLE or PDL_TMR ADC TRIGGER ENABLE Disable or enable ADC conversion start requests on a compare match A signal Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_CM_A_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when a Compare Match A occurs Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL_TMR_CM_B_DTC_TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match B occurs R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 232 of 487 RX63N Group 4 Library Reference Description 2 2 data3 Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold e Output control for pin TMOy y 0 or 2 forn 0 or 1 PDL_TMR_OUTPUT_IGNORE_CM_Aor No change if a compare match A occurs PDL_TMR_OUTPUT_LOW_CM_Aor 0 is output if a compare match A occurs PDL_TMR_OUTPUT_HIGH_CM_Aor 1 is output if a compare match A occurs PDL_TMR_OUTPUT_INV_CM_A The ou
265. R_IO_PORT_NotAvailable Remarks Ensure that the specified functions are valid for the selected port pin The data direction and mode registers may be modified by other driver functions Take care to not overwrite existing settings e Pin P35 is fixed as an input and cannot be modified All pins that are not available on the selected package can be set to the required state using the R_IO_PORT_NotAvailable function Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set up port P13 as an input port with the pull up on R_IO_PORT_Set PDL_IO_PORT_1_3 PDL_IO_PORT_INPUT PDL_IO_PORT_PULL_UP_ON R20UT1963EE0100 Rev 1 00 R AS Page 91 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 2 R_lIO_PORT_ReadConirol Synopsis Prototype Description Read an I O port s control register bool R_IO_PORT_ReadControl uint16_t data1 Port or port pin selection uint8_t data2 Control register selection uint16_t data3 Data storage location Read an I O port pin control setting data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 e Select the register to be read PDL_IO_PORT_DIRECTION or Data di
266. ReadLastByte to read the last byte e Ifa callback function is specified and the interrupt priority level is zero this function will return false e Device packages with 100 pins do not have all of the SCI channels PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 9 define SLAVE_ADDRESS OxAO Buffer for IIC data extern uint8_t IIC_Buffer 10 void func void Wait while read 10 bytes R_SCI_IIC_Read CHANNEL _SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 IIc_Buffer PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 302 of 487 RX63N Group 4 Library Reference 9 R_SCI_lIC_ReadLastByte Synopsis Prototype Description Read the last byte of an IIC read transfer bool R_SCI_IIC_ReadLastByte uint8_t data1 Channel selection uint8_t data2 II Buffer to receive byte If R_SCI_IIC_Read has been used to start an IIC read where the DMAC or DTC will read all the Return value Category Reference Remarks Program example data except for the last byte this function can be used to read the last byte A NACK will then be generated followed by a stop condition unless the original transfer request asked for the stop condition to be omitted data1 Select channel SCIn wher
267. S4 PB2 CTS4 PDL SCI PIN SCI4_RTS4 PB2 RTS4 PDL_SCI_PIN_SCI4_SS4_PB2 554 Valid when n 5 PDL_SCI_PIN_SCI5_RXD5_PA2 or PDL_SCI_PIN_SCI5_RXD5_PA3 or RXD5 PDL_SCI_PIN_SCI5_RXD5_PC2 PDL_SCI_PIN_SCI5_SMISO5_PA2 or PDL_SCI_PIN_SCI5_SMISO5_PA3 or SMISOS5 PDL_SCI_PIN_SCI5_SMISO5_PC2 PDL_SCI_PIN_SCI5_SSCL5_PA2 or PDL_SCI_PIN_SCI5_SSCL5_PA3 or SSCL5 PDL_SCI_PIN_SCI5_SSCL5_PC2 PDL_SCI_PIN_SCI5_TXD5_PA4 or ae PDL_SCI_PIN SCI5 TXD5 PC3 PDL_SCI_PIN_SCI5_SMOSI5_PA4 or PDL_SCI_PIN_SCI5_SMOSI5_PC3 oo SMOSIS PDL_SCI_PIN_SCI5_SSDA5_PA4 or Sen PDL_SCI_PIN_SCI5_SSDA5_PC3 PDL_SCI_PIN_SCI5_SCK5_PA1 or PDL_SCI_PIN_SCI5_SCK5_PC1 or SCKS5 PDL_SCI_PIN SCI5 SCK5 PC4 PDL_SCI_PIN_SCI5_CTS5_PAG or ae PDL_SCI_PIN_SCI5_CTS5_PCO PDL_SCI_PIN_SCI5_RTS5_PAG or me PDL_SCI_PIN_SCI5_RTS5_PC0 PDL_SCI_PIN_SCI5_SS5_PA6 or age PDL SCI PIN SCI5_SS5 PCO R20UT1963EE0100 Rev 1 00 RENESAS Page 281 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 4 5 Valid when n 6
268. SABLE or PDL_LPC_CANCEL_IRQ6_FALLING or PDL_LPC_CANCEL_IRQ6 RISING PDL_LPC_CANCEL_IRQ7_DISABLE or PDL_LPC_CANCEL_IRQ7_FALLING or PDL_LPC_CANCEL_IRQ7_ RISING Prevent or allow an edge on the IRQ6 DS pin to cancel deep software standby mode Prevent or allow an edge on the IRQ7 DS pin to cancel deep software standby mode data3 Select the interrupt IRQ8 to IRQ15 to cancel deep software standby mode The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Deep software standby cancel control PDL_LPC_CANCEL_IRQ8_DISABLE or PDL_LPC_CANCEL_IRQ8_ FALLING or PDL_LPC_CANCEL_IRQ8_RISING Prevent or allow an edge on the IRQ8 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ9_DISABLE or PDL_LPC_CANCEL_IRQ9_FALLING or PDL_LPC_CANCEL_IRQ9 RISING Prevent or allow an edge on the IRQ9 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ10_FALLING or PDL_LPC_CANCEL_IRQ10_RISING PDL_LPC_CANCEL_IRQ11_FALLING or PDL_LPC_CANCEL_IRQ11_RISING PDL_LPC_CANCEL_IRQ10_DISABLE or PDL_LPC_CANCEL_IRQ11_DISABLE or Prevent or allow an edge on the IRQ10 DS pin to cancel deep software standby mode Prevent or allow an edge on the IRQ11 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ12_FALLING or PDL_LPC_CANCEL_IRQ12_ RISING PDL_LPC_CANCEL_IRQ12_DISABLE or Prevent or allow an edge on the IRQ12 DS pin to cancel d
269. SIZE 1 ARRAY_2_SIZE 2 Array size written sub address byte last byte PDL_NO_DATA T Read data from the EEPROM using the DTC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the EEPROM using the DTC R_IIC_MasterSend IIC_CHANNEL PDL_IIC_DTC_TRIGGER_ENABLE EEPROM _ADDRESS PDL_NO_PTR 0 iic_tx_end_handler 7 while bus_busy true uint32_t iic_flags uintl6_t flags int32 t sre uint32_t dest uintl6_t counter R_DTC_GetStatus dtc_iicl_tx_transfer_data flags amp src amp dest amp counter PDL_NO_PTR R_IIC_GetStatus IIC_CHANNEL amp iic_flags PDL_NO_PTR PDL_NO_PTR T Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 5E 3 PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 Page 456 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples static void read_eeprom_data void bus_busy true Read data from the EEPROM using the DTC R_IIC_MasterReceive TIC_CHANNEL PDL _IIC_DTC_TRIGG EEPROM_ADDRESS PDL_NO_PTR 0 iic_rx_end_handler 7 while bus_busy true void iic_tx_end_handler void uint32_t status_flags 0 Wait for the transmission to complete do R_IIC_GetStatus TIC_CHANNEL
270. START_75 or PDL_MCU_OFS_WDT_WIN_START_100 The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Underflow action PDL_MCU_OFS_WDT_NMIl or Select an NMI or reset when the WDT PDL_MCU_OFS_WDT_RESET down counter underflows data3 Select the post reset LVD configuration settings e Auto start control PDL_MCU_OFS_LVD_0_DISABLE or Disable or enable the Voltage monitor 0 auto start PDL_MCU_OFS_LVD_0O_ENABLE mode data4 Select the post reset CGC configuration settings Auto start control PDL_MCU_OFS_ CGC _HOCO DISABLE or PDL MCU OFS CGC HOCO ENABLE Disable or enable the HOCO after a reset Category MCU registers References R_IWDT_Set R_WDT_Set R_CGC_ Set Remarks e This is a macro not a function call There is no error checking or return value e The auto start setting for each parameter must be selected R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 110 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_mcu_ofs h Enable the IWDT auto start mode Leave the WDT disabled Enable reset at Vdet0O Leave the HOCO disabled R_MCU_OFS PDL MCU_
271. Select channel 1 data2 The value to be written to the channel 0 output register Ignored if the channel is not selected data3 The value to be written to the channel 1 output register Ignored if the channel is not selected True if all parameters are valid otherwise false DAC R_DAC_10_Create e Refer to the data alignment that was selected when R_DAC_10_Create was called e Channel 0 is not available on 100 pin package RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Write new data to DAC channel 1 R_DAC_10_Write PDL_DAC_10_CHANNEL_1 0 100 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 375 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 2 31 1 R_TS Create Synopsis Prototype Description Return value Category References Remarks Temperature Sensor Configure the Temperature Sensor bool R_TS_Create void II No parameter is required Enable the Temperature Sensor True TS None e R_ADC_12_Create must be called to configure the temperature sensor as the target of A D Program example conversion before use this function RPDL definitions include r_pdl_ts h RPDL device specific definitions include r_pdl_definitions h void func void Enable TS R_TS_Crea
272. Significant bit first PDL_SCI_MSB_FIRST elect least or most significant bit first Options which are available in Asynchronous mode or Multi Processor Asynchronous mode e Noise Filter PDL_SCI_RX_FILTER_DISABLE or Enable or disable the Digital Noise Filter on the PDL_SCI_RX_FILTER_ENABLE RXDn pin e Hardware Flow Control PDL_SCIl_HW_FLOW_NONE or Select the Hardware Flow Control Option PDL_SCI_HW_FLOW_CTS or Note CTS and RTS functions cannot both be used PDL_SCI_LHW_FLOW_RTS as they share the same pin e Data clock source selection PDL_SCI_CLK_INT_ 10 or Select the on chip SCKn pin available as an I O pin PDL_SCI_CLK_INT_OUT or baud rate generator SCKn pin SCI bit clock output Input a clock of 8 or 16 times the desired bit rate to the SCKn POLASCI OEK EXT or pin See parameter data3 for the multiplier selection For SCI5 select Timer output TMOO TMO1 For SCI6 select Timer output TMO2 TMO3 PDE SGL CLK IMR For SCI12 select Timer output TMOO TMO1 The SCKn pin is set to high impedance e Data length PDL_SCI_8_BIT_LENGTH or PDL_SCI_7_BIT_LENGTH 8 or 7 bit data length e Parity mode PDL_SCI_PARITY_NONE or No parity bit even parity bit or odd parity bit PDL_SCI_PARITY_EVEN or Note Do not set parity bit for Multi Processor PDL_SCI_PARITY_ODD Asynchronous mode R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 284 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 4 e Stop bit length
273. TART PDL_SCI_IIC_DTC_TRIGGER_ENABLE SLAVE_ADDRESS PDL_NO_DATA No data length as using DTC PDL_NO_DATA No buffer as using DTC CallbackRx R20UT1963EE0100 Rev 1 00 AS Page 444 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples Wait for rx while data_received false Because using DMAC need to manually get the last byte This will also generate the stop condition R_SCI_IIC_ReadLastByte CHANNEL_SCI_IIC amp IlIC_Buffer 4 Callback function for Rx static void CallbackRx void data_received true Figure 5 37 Example of SCI in IIC mode using DTC R20UT1963EE0100 Rev 1 00 AS Page 445 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 18 IC Bus Interface In the following examples the bus activity will be illustrated using the following format ae ee Pal Pale A Acknowledge SDA held low A Not Acknowledge SDA released high S Start condition P Stop condition Sr Repeated Start condition R Read SDA released high W Write SDA held low Figure 5 38 I C bus activity notation 5 18 1 Master mode In this example an EEPROM device has been connected to channel 0 The EEPROM responds to the 7 bit slave address 1010xxxb During a read process the bits xxx can be any value During a write process i The bits xxx represent the EEPROM memory address bi
274. TC The function to be called at the interval specified in R_DTC_Create data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false Category lC Reference R_IIC_Create R_IIC_GetStatus R_IIC_MasterReceiveLast R20UT1963EE0100 Rev 1 00 EN ESAS Page 316 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks e Ifa callback function is specified reception interrupts are used Please see the notes on callback function usage in 6 e Ifthe previous transfer did not issue a Stop condition a Repeated Start condition shall be generated The last byte to be read shall be completed with a NACK signal e If no callback function is specified this function will operate in polling mode The status flags will be used to manage the data reception If the IPC channels control registers are directly modified by the user this function may lock up If an error occurs during this polling process the function will terminate Ifthe DMAC or DTC is used use R_IIC_MasterReceiveLast to complete the transfer e Use R_IIC_GetStatus to determine if the transfer was successful e False will be returned if the DMAC channel has not been allocated using R_ DMAC_Create e False will be returned if the bus is busy due to another master on the bus
275. TC_FILTER_DIV_32 PDL_INTC_FALLING SW2_handler 7 Configure the SW3 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ15 PDL_INTC_LOW SW3_handler 7 void SWl_handler void uint8_t irq status 0u R_INTC_GetExtInterruptStatus PDL_INTC_IRQ2 amp irg_status i R20UT1963EE0100 Rev 1 00 AS Page 382 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples Falling edge detected if irq_status amp 0x0C 0x04 Disable and invert the edge interrupt R_INTC_ControlExtInterrupt PDL_INTC_IRQ2 PDL_INTC_RISING PDL_INTC_DISABLE else if irq status amp 0x0C 0x08 Disable and invert the edge interrupt R_INTC_ControlExtInterrupt PDL_INTC_IRQ2 PDL_INTC_FALLING PDL_INTC_DISABLE Figure 5 2 Example of External Interrupt R20UT1963EE0100 Rev 1 00 AS Page 383 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 3 I O Port Figure 5 3 shows examples of I O port configuration reading and writing Peripheral driver function prototypes include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void main void uint8_t result uintl6_t register_value Set all reserved I O port pins to the recommended state R_IO_PORT_NotAvailable Configure port 4 as an input R_IO_PORT_Set PDL_IO PORT _4_0 PDL_IO PORT 4 1
276. TC_REG_IPR_USB1_DOFIFO PDL_INTC_REG_IPR_MTUO_TGIAD PDL_INTC_REG_IPR_USB1_D1FIFO PDL_INTC_REG_IPR_MTUO_TGIEF PDL_INTC_REG_IPR_USB1_USBI PDL_INTC_REG_IPR_MTU1 PDL_INTC_REG_IPR_SPIO PDL_INTC_REG_IPR_MTU2 PDL_INTC_REG_IPR_SPI1 PDL_INTC_REG_IPR_MTU3 PDL_INTC_REG_IPR_SPI2 PDL_INTC_REG_IPR_MTU4_TGIAD PDL_INTC_REG_IPR_CANO PDL_INTC_REG_IPR_MTU4_ TCIV PDL_INTC_REG_IPR_CAN1 PDL_INTC_REG_IPR_MTUS5 PDL_INTC_REG_IPR_CAN2 PDL_INTC_REG_IPR_POE PDL_INTC_REG_IPR_RTC_CUP PDL_INTC_REG_IPR_TMRO PDL_INTC_REG_IPR_ICU_IRQO PDL_INTC_REG_IPR_TMR1 PDL_INTC_REG_IPR_ICU_IRQ1 PDL_INTC_REG_IPR_TMR2 PDL_INTC_REG_IPR_ICU_IRQ2 PDL_INTC_REG_IPR_TMR3 PDL_INTC_REG_IPR_ICU_IRQ3 PDL_INTC_REG_IPR_IICO_EEI PDL_INTC_REG_IPR_ICU_IRQ4 PDL_INTC_REG_IPR_IICO_RXI PDL_INTC_REG_IPR_ICU_IRQ5 PDL_INTC_REG_IPR_IICO_TXI PDL_INTC_REG_IPR_ICU_IRQ6 PDL_INTC_REG_IPR_IICO_TEI PDL_INTC_REG_IPR_ICU_IRQ7 PDL_INTC_REG_IPR_IIC1_EEl PDL_INTC_REG_IPR_ICU_IRQ8 PDL_INTC_REG_IPR_IIC1_RxXI PDL_INTC_REG_IPR_ICU_IRQ9 PDL_INTC_REG_IPR_IIC1_TXI PDL_INTC_REG_IPR_ICU_IRQ10 PDL_INTC_REG_IPR_IIC1_TEl PDL_INTC_REG_IPR_ICU_IRQ11 PDL_INTC_REG_IPR_IIC2_EEI PDL_INTC_REG_IPR_ICU_IRQ12 PDL_INTC_REG_IPR_IIC2_RXl PDL_INTC_REG_IPR_ICU_IRQ13 PDL_INTC_REG_IPR_IIC2_TXI PDL_INTC_REG_IPR_ICU_IRQ14 PDL_INTC_REG_IPR_ IC2_TEl PDL_INTC_REG_IPR_ICU_IRQ15 PDL_INTC_REG_IPR_IIC3_EEI PDL_INTC_REG_IPR_USBO_USBR PDL_INTC_REG_IPR_IIC3_RXI PDL_INTC_REG_IPR_USB1_USBR PDL_INTC_REG_IPR_IIC3_TXI PDL_INTC_REG_IPR_RTC_ALM PDL_INTC_REG_IPR_IIC3_TEl PDL_INT
277. TC_REG_IR_MTUO_TGIE PDL_INTC_REG_IR_ICU_IRQ10 PDL_INTC_REG_IR_MTUO_TGIF PDL_INTC_REG_IR_ICU_IRQ11 PDL_INTC_REG_IR_MTU1_TGIA PDL_INTC_REG _IR_ICU_IRQ12 PDL_INTC_REG_IR_MTU1_TGIB PDL_INTC_REG_IR_ICU_IRQ13 PDL_INTC_REG_IR_MTU2_TGIA PDL_INTC_REG_IR_ICU_IRQ14 PDL_INTC_REG_IR_MTU2_TGIB PDL_INTC_REG_IR_ICU_IRQ15 PDL_INTC_REG_IR_MTU3_TGIA PDL_INTC_REG_IR_USBO_USBR PDL_INTC_REG_IR_MTU3_TGIB PDL_INTC_REG_IR_USB1_USBR PDL_INTC_REG _IR_MTU3_TGIC PDL_INTC_REG_IR_RTC_ALM PDL_INTC_REG_IR_MTU3_TGID PDL_INTC_REG_IR_RTC_PRD PDL_INTC_REG_IR_MTU4 TGIA PDL_INTC_REG_IR_AD_ADI PDL_INTC_REG_IR_MTU4_TGIB PDL_INTC_REG_IR_S12AD_S12ADI PDL_INTC_REG_IR_MTU4_ TGIC PDL_INTC_REG_IR_ICU_GROUPO PDL_INTC_REG_IR_MTU4 TGID PDL_INTC_REG_IR_ICU_GROUP1 PDL_INTC_REG_IR_MTU4_TCIV R20UT1963EE0100 Rev 1 00 2tENESAS Page 75 of 487 Jul 19 2012 RX63N Group 4 Library Reference
278. TMR_TMRO_TMRIO_PA4 Configure TMRO for 500us pulse width 200us on time R_TMR_CreatePeriodic PDL_TMR_TMRO PDL_TMR PERIOD PDL_TMR_OUTPUT_HIGH 500E 6 200E 6 PDL_NO_FUNC PDL_NO_FUNC 0 The same operation using frequency and duty cycle R_TMR_CreatePeriodic PDL_TMR_TMRO MR_FREQUENCY PDL_TMR_OUTPUT_HIGH D DL E6 0 DL_NO_FUNC DL_NO_FUNC Figure 5 18 Example of Pulse Output code R20UT1963EE0100 Rev 1 00 Page 413 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples For full flexibility the R_TMR_CreateChannel function can be used In this example Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 200 ticks of PCLKB and a duty cycle of 50 Note that the output transitions and counter clearing occur after the compare match has occurred So the values for compare match A and compare match B should be 1 less than the required count Peripheral driver function prototypes include r_pdl_tmr h include r_pdl_definitions h void main void Configure TMRO input and output pins R_TMR_Set 0 PDL_TMR_TMRO_TMOO_PB3 i Configure TMRO to clear on a compare match A output 1 at a compare match A and output 0 at a compare match B R_TMR_CreateChanneli 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_TMR_OUTPUT_HIGH_CM_A PDL_TMR_OUTPUT_LOW_CM_B 0 200 1
279. TR PDL_NO_DATA PDL_NO_DATA Update the parameters for CMT0 triggered transfers R_DTC_Control PDL_DTC_UPDATE_DESTINATION PDL_DTC_UPDATE_COUNT dtc_cmt0O_transfer_data PDL_NO_PTR 0x0000BBO0 100 PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tENESAS Page 171 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_DTC_GetStatus Synopsis Prototype Description Check the status of the Data Transfer Controller bool R_DTC_GetSiatus uint32_t data1 Transfer data start address uint16_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint8_t data6 Current block size count pointer Return status flags and current channel registers data1 The start address of the transfer data area If all parameters data3 data4 data5 and data6 are not required specify PDL_NO_PTR data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the status flags are not required b15 b14 b8 b7 bO 0 Idle 1 A transfer is in progress 0 The trigger vector valid only when bit b15 1 data3 Where the current source address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR
280. TR if it is not required data5 For n 0 to 4 A pointer to where the TGRB register value shall be stored For n 5 Apointer to where the TNCTW register value shall be stored Specify PDL_NO_PTR if it is not required data6 For n 0 3 or 4 A pointer to where the TGRC register value shall be stored For n 5 Apointer to where the TGRU register value shall be stored Specify PDL_NO_PTR if it is not required data7 For n 0 3 or 4 A pointer to where the TGRD register value shall be stored For n 5 Apointer to where the TGRV register value shall be stored Specify PDL_NO_PTR if it is not required data8 For n 0 A pointer to where the TGRE register value shall be stored For n 5 Apointer to where the TGRW register value shall be stored Specify PDL_NO_PTR if it is not required data9 For n 0 A pointer to where the TGRF register value shall be stored Specify PDL_NO_PTR if it is not required Return value True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference None Remarks e Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to O by this function R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 197 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h
281. TU2_Create call this function to configure the relevant pins e Make sure no more than one peripheral function is assigned to a single pin e Make sure the configuration of MTCLK pins is consistent for all the channels There are some pin restrictions when not using the 176 pin device package R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 175 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example include r_pdl_mtu2 h void func void Configure the MTU pins R_MTU2_Set 0 PDL_MTU2_PIN_0A_P34 PDL_MTU2_PIN_CLKA_P14 R20UT1963EE0100 Rev 1 00 AS Page 176 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 2 R_MTU2_Create Synopsis bool Prototype Configure an MTU channel R_MTU2_Create uint8_t data1 R_MTU2_Create_structure data2 R_MTU2_Create_structure members Description 1 9 uint32_t channel_mode uint32_t counter_operation uint32_t ADC_trigger_operation uint16_t buffer_operation uint32_t T R_A_B_ operation uint32_t TGR_C_D_ operation uint32_t T 4R_U_V_W_ operation uint16_t noise_filter_operation uinti16_t TCNT_TCNTU_value uinti6_t T 4RA_TCNTV_value uinti6_t T 4RB_TCNTW_value uint16_t TGRC_TGRU_value uinti6_t T 4RD_TGRV_value uinti6_t T 4RE_TGRW_value uint16_t T 4RF_TADCORA_ value uinti6_t TADCORB_ value uinti16_t TADCOBRA_ value uinti6_t TADCOBRB_ value void func1 void func2 void func3 void fun
282. USB1_DOFIFO1 or PDL_DMAC_TRIGGER_USB1_D1FIFO1 or FIFO interrupt from USB1 PDL_DMAC_TRIGGER_SPIO_RX or PDL_DMAC_TRIGGER_SPI1_RX or PDL_DMAC_TRIGGER_SPI2_RX or Receive buffer full on SPI channel n n 0 to 2 PDL_DMAC_TRIGGER_SPI0_TX or PDL_DMAC_TRIGGER_SPI1_TX or PDL_DMAC_TRIGGER_SPI2_TX or Transmit buffer empty on SPI channel n n 0 to 2 PDL_DMAC_TRIGGER_IRQO or PDL_DMAC_TRIGGER_IRQ1 or PDL_DMAC_TRIGGER_IRQ2 or PDL_DMAC_TRIGGER_IRQ3 or Valid edge detected on pin IRQn n 0 to 3 PDL_DMAC_TRIGGER_ADC10 or Conversion completed on the 10 bit ADC unit PDL_DMAC_TRIGGER_ADC12 or Conversion completed on the 12 bit ADC unit PDL_DMAC_TRIGGER_TPUO or PDL_DMAC_TRIGGER_TPU1 or PDL_DMAC_TRIGGER_TPU2 or PDL_DMAC_TRIGGER_TPUS3 or PDL_DMAC_TRIGGER_TPU4 or PDL_DMAC_TRIGGER_TPU5 or PDL_DMAC_TRIGGER_TPU6 or PDL_DMAC_TRIGGER_TPU7 or PDL_DMAC_TRIGGER_TPU8 or PDL_DMAC_TRIGGER_TPU9 or PDL_DMAC_TRIGGER_TPU10 or PDL_DMAC_TRIGGER_TPU11 or PDL_DMAC_TRIGGER_MTUO or PDL_DMAC_TRIGGER_MTU1 or PDL_DMAC_TRIGGER_MTU2 or PDL_DMAC_TRIGGER_MTU3 or PDL_DMAC_TRIGGER_MTU4 or Input capture or compare match on TPU channel n n 0 to 11 Input capture or co
283. XI11 SCI channel 11 Start of next data transfer PDL_INTC_VECTOR_TEI11 End of data transfer PDL_INTC_ VECTOR RXI12 Data received PDL_INTC VECTOR _TXI12 SCI channel 12 Start of next data transfer PDL_INTC_VECTOR_TEI12 End of data transfer PDL_INTC_VECTOR_IEBINT IEBus Any enabled event Return value True Category Reference Remarks Program example Interrupt control e The fast interrupt processing is allocated to only one interrupt handler Open the file r_pdl_user_definitions h and edit the definition FAST_INTC_VECTOR to give it the same value as the interrupt vector used in parameter data1 For example define FAST_INTC_VECTOR PDL_INTC_VECTOR_IRQ2 This will direct the compiler to generate the instructions required for a fast interrupt vector e This function uses an interrupt routine to modify the FINTV register If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Assign the fast interrupt to the handler for pin IRQ3 R_INTC_CreateFastInterrupt PDL_INTC_VECTOR_IRQ3 Remember to edit r_pdl_user_definitions h see remark 2 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 70 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_INTC_CreateE
284. _ADC_12_VALUE_ADD_CHANNEL_7 PDL_ADC_12_VALUE_ADD_CHANNEL_6 PDL_ADC_12_VALUE_ADD_CHANNEL_8 PDL_ADC_12_VALUE_ADD_CHANNEL_9 PDL_ADC_12_VALUE_ADD_CHANNEL_10 PDL_ADC_12_VALUE_ADD_CHANNEL_11 PDL_ADC_12_VALUE_ADD_CHANNEL_12 PDL_ADC_12_VALUE_ADD_CHANNEL_13 PDL_ADC_12_VALUE_ADD_CHANNEL_14 PDL_ADC_12_VALUE_ADD_CHANNEL_15 PDL_ADC_12_VALUE_ADD_CHANNEL_16 PDL_ADC_12_VALUE_ADD_CHANNEL_18 PDL_ADC_12_VALUE_ADD_CHANNEL_17 PDL_ADC_12_VALUE_ADD_CHANNEL_20 PDL_ADC_12_VALUE_ADD_CHANNEL_19 Enable value addition mode on each of the selected channels ANO to AN20 Only enabled channels may be selected PDL_ADC_12_VALUE_ADD_TS Enable value addition mode for the temperature sensor PDL_ADC_12_VALUE_ADD_REF Enable value addition mode for the reference voltage R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 358 of 487 RX63N Group 4 Library Reference Description 3 4 e Value addition count selection Return value Category References Remarks PDL_ADC_12_VALUE_ADD_TIME_1 or PDL_ADC_12_VALUE_ADD_TIME_2 or The number of conversions applied to each PDL_ADC_12_VALUE_ADD_TIME_3 or channel selected for value addition mode PDL_ADC_12_ VALUE _ADD_TIME_4 data6 This parameter is ignored if data3 does not specify PDL_ADC_12_SAMPLING_TIME_CALCULAT
285. _BSC_CS2_P62 PDL_BSC_A16_A23_PC PDL_NO_DATA PDL_NO_DATA PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE PDL_BSC_ERROR_TIME_OUT_ENABLE BusErrorFunc 5 R20UT1963EE0100 Rev 1 00 Page 133 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 3 R_BSC_CreateArea Synopsis Prototype Description 1 2 Configure an external bus area bool R_BSC_CreateArea uint8_t data1 Area selection uint16_t data2 Configuration selection uint8_t data3 RRCV cycles uint8_t data4 WRCV cycles uint8_t data5 CSPRWAIT cycles uint8_t data6 CSPWWAIT cycles uint8_t data7 CSRWAIT cycles uint8_t data8 CSWWAIT cycles uint8_t data9 CSROFF cycles uint8_t data10 CSWOFF cycles uint8_t data11 WDOFF cycles uint8_t data12 AWAIT cycles uint8_t data13 RDON cycles uint8_t data14 WRON cycles uint8_t data15 uint8_t data16 1 WDON cycles I CSON cycles Set up an external bus area data1 The address area n where n 0 to 7 data2 Configure the operation of area CSn If multiple selections are required use to separate each selection The default settings are shown in bold External bus width PDL_BSC_WIDTH_8 or PDL_BSC_WIDTH_16 PDL_BSC_WIDTH_32 Select 8 16 or 32 bit data bus width Endian mode PDL_BSC_ENDIAN_SAME or PDL_BSC_ENDIAN OPPOSITE Set the bus endian
286. _CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK_DELAY_8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPIL_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or The number of bit clock periods between the end of PDL_SPI_SSL_DELAY_4 or RSPCK oscillation and the negation of the active SSL PDL_SPI_SSL_DELAY_5 or pin PDL_SPI_SSL_DELAY_6 or Ignored in Slave mode PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY_8 Extended next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or PDL_SPI_NEXT_DELAY_4 or PDL_SPI_NEXT_DELAY_5 or PDL_SPI_NEXT_DELAY_6 or PDL_SPI_NEXT_DELAY_7 or PDL_SPI_NEXT_DELAY_8 The number of bit clock periods plus two cycles of the peripheral clock between the end of one frame and the start of the next frame Ignored in Slave mode True if all parameters are valid otherwise false SPI R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 335 of 487 RX63N Group 4 Library Reference Reference R_SPI_Create Remarks e Ifa channel is disabled using PDL_SPI_DISABLE call R_SPI_
287. _Create 0 PDL_IIC_MODE_IIC PDL_IIC_SLAVE_0O_ENABLE_7 PDL_IIC_SLAVE_1_ENABLE_7 0x0020 0x0056 PDL_NO_DATA 100E3 300 lt lt 16 200 R20UT1963EE0100 Rev 1 00 AS Page 312 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 2 R_IIC_Destroy Synopsis Prototype Description Disable an 1 C channel bool R_IIC_Destroy uint8_t data Channel selection Shut down the selected 1 C channel data Select channel IICn where n 0 to 3 Program example Return value True if the parameter is valid otherwise false Category lC Reference R_IIC_Create Remarks The l C module is put into the power down state e Channels 1 and 3 are not available with the 100 pin package This function will return false in this case RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown IIC channel 0 R_IIC_Destroy 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 313 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_lIC_MasterSend Synopsis Prototype Description Return value Write data to a slave device bool R_IIC_MasterSend uint8_t data1 Channel selection uint16_t data2 Channel configuration
288. _DMAC2I PDL_INTC_REG_DTCER_TPU3 TGIA PDL_INTC_REG_DTCER_DMAC_DMACS3I PDL_INTC_REG_DTCER_TPU3_TGIB PDL_INTC_REG_DTCER_EXDMAC_EXDMACOI PDL_INTC_REG_DTCER_TPU3_TGIC PDL_INTC_REG_DTCER_EXDMAC_EXDMAC1I PDL_INTC_REG_DTCER_TPU3_TGID PDL_INTC_REG_DTCER_SCIO_RXI PDL_INTC_REG_DTCER_TPU4 TGIA PDL_INTC_REG DTCER_SCIO_TXI PDL_INTC_REG_DTCER_TPU4 TGIB PDL_INTC_REG_DTCER_SCI1_RXI PDL_INTC_REG_DTCER_TPUS_TGIA PDL_INTC_REG_DTCER_SCI1_TXI PDL_INTC_REG_DTCER_TPU5_TGIB PDL_INTC_REG_DTCER_SCI2_RXI PDL_INTC_REG_DTCER_TPU6_TGIA PDL_INTC_REG_DTCER_SCl2_TXl PDL_INTC_REG _DTCER_TPU6_TGIB PDL_INTC_REG_DTCER_SCI3_RXI PDL_INTC_REG_DTCER_TPU6_TGIC PDL_INTC_REG DTCER_SCI3 TXI PDL_INTC_REG_DTCER_TPU6_TGID PDL_INTC_REG_DTCER_SCI4_ RXI PDL_INTC_REG_DTCER_TPU7_TGIA PDL_INTC_REG_DTCER_SCI4_TXl PDL_INTC_REG_DTCER_TPU7_TGIB PDL_INTC_REG_DTCER_SCI5_RXI PDL_INTC_REG_DTCER_TPU8 TGIA PDL_INTC_REG DTCER_SCI5 TXI PDL_INTC_REG_DTCER_TPU8_TGIB PDL_INTC_REG_DTCER_SCI6_RXI PDL_INTC_REG_DTCER_TPU9 TGIA PDL_INTC_REG_DTCER_SCI6_TXI PDL_INTC_REG_DTCER_TPU9_TGIB PDL_INTC_REG_DTCER_SCI7_RXI PDL_INTC_REG_DTCER_TPU9 TGIC PDL_INTC_REG_DTCER_SCIl7_TXI PDL_INTC_REG_DTCER_TPU9 TGID PDL_INTC_REG_DTCER_SCI8_RXI PDL_INTC_REG_DTCER_TPU10_TGIA PDL_INTC_REG DTCER_SCI8 TXI PDL_INTC_REG_DTCER_TPU10_TGIB R20UT1963EE0100 Rev 1 00 2tENESAS Page 78 of 487 Jul 19 2012 RX63N Group 4 Library Reference PDL_INTC_REG_DTCER SCI9_RXI PDL_INTC_REG DTCER_SCI11_RXI PDL_INTC_REG DTCER
289. _DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_DMAC_Create R_DTC_Create R_SCl_Control Remarks Program example e The maximum number of characters to be transmitted is 65535 e Wait until a transmission on the same channel is complete before calling this function Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed e This function unless configured not to will by default automatically start a transfer by generating a Start condition and finish with a Stop condition However if using DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_Control function to manually generate a stop e Ifa callback function is specified and the interrupt priority level is zero this function will return false The SCI IIC module is always configured to use Reception and Transmission interrupts IICINTM bit 1 rather than ACK NACK interrupts This means that if using the DMAC or DTC to transmit then all data will be transmitted even if the slave device fails to ACK e Device packages with 100 pins do not have all of the SCI channels PDL functions include r_pdl
290. _IO_PORT_C_5 Port pin PCs PDL_IO_PORT_7_6 PortpinP7 PDL_IO PORT_C_6 Port pin PC PDL_IO_PORT_3_0 Port pin P30 PDL_IO_PORT_7_7 Port pin P77 PDL_IO PORT_C_7 Port pin PC PDL_IO_PORT_3_1 Port pin P31 PDL_IO_PORT_3_2 Port pin P32 PDL_IO_PORT_8_0 Port pin P8o PDL_IO_PORT_D_O Port pin PDo PDL_IO_PORT_3_3_ Port pin P33 PDL_lIO_PORT_8_1 Port pin P81 PDL_IO_PORT_D_1 Port pin PD PDL_IO_PORT_3 4 Port pin P34 PDL_IO_PORT_8 2 Port pin P82 PDL_IO PORT _D 2 Port pin PD2 PDL_IO_PORT_3_5 Port pin P35 PDL_IO_PORT_8 3 Port pin P83 PDL_IO PORT_D_3 Port pin PDs PDL_IO_PORT_3 6 Port pin P36 PDL_IO_PORT_8 4 Portpin P84 PDL_IO PORT_D 4 Port pin PD PDL_IO_PORT_3_7 Port pin P37 PDL_IO_PORT_8_5 Port pin P85 PDL_IO_PORT_D_5 Port pin PDs PDL_IO_PORT_8 6 Port pin P86 PDL_IO PORT_D 6 Port pin PDe PDL_IO_PORT_4 0 Port pin P40 PDL_IO_PORT_8 7 Port pin P87 PDL_IO PORT_D 7 Port pin PD7 PDL_IO PORT 4 1 Port pin P44 PDL_IO_PORT_4 2 Port pin P42 PDL_IO_PORT_9 0 PortpinP9o PDL_IO PORT_E_0 Port pin PEo PDL_IO_PORT_4 3 Port pin P43 PDL_IO_ PORT 9 1 Port pin P91 PDL_IO_PORT_E_1 Port pin PE PDL_IO_PORT_4 4 Port pin P44 PDL_IO_PORT_9 2 Port pin P92 PDL_IO_PORT_E 2 Port pin PE2 PDL_IO PORT 4 5 Port pin P45 PDL_IO_PORT_9 3 Port pin P93 PDL_IO PORT_E 3 Port pin PE3 PDL_IO PORT 4 6 Port pin P46 PDL_IO_PORT_9 4 PortpinP9 PDL_IO PORT_E 4 Port pin PE PDL_IO_PORT_4_7 Port pin P47 PDL_IO_PO
291. _IR_SCI8_TXI PDL_INTC_REG_IR_IIC2_RXI PDL_INTC_REG_IR_SCI8_TEI PDL_INTC_REG_IR_IIC2_TXI PDL_INTC_REG_IR_SCI9_RXI PDL_INTC_REG_IR_IIC2_TEI PDL_INTC_REG_IR_SCI9_TXI PDL_INTC_REG_IR_IIC3_EEI PDL_INTC_REG_IR_SCI9_TEI PDL_INTC_REG_IR_IIC3_RXI PDL_INTC_REG_IR_SCI10_RXI PDL_INTC_REG_IR_IIC3_TXI PDL_INTC_REG_IR_SCI10_TXI PDL_INTC_REG_IR_IIC3_TEl PDL_INTC_REG_IR_SCI10_TEI PDL_INTC_REG_IR_DMAC_DMACOI PDL_INTC_REG_IR_SCI11_RXI PDL_INTC_REG_IR_DMAC_DMAC1I PDL_INTC_REG_IR_SCI11_TXI PDL_INTC_REG_IR_DMAC_DMAC2I PDL_INTC_REG_IR_SCI11_TEl PDL_INTC_REG_IR_DMAC_DMAC31 PDL_INTC_REG_IR_SCI12_RXI PDL_INTC_REG_IR_EXDMAC_EXDMACOI PDL_INTC_REG_IR_SCI12_TXI PDL_INTC_REG_IR_EXDMAC_EXDMAC1I PDL_INTC_REG_IR_SCI12_ TEI PDL_INTC_REG_IR_IEB_IEBINT IER register definitions PDL_INTC_REG_IER02 PDL_INTC_REG_IER12 PDL_INTC_REG_IERO3 PDL_INTC_REG_IER13 PDL_INTC_REG_IER04 PDL_INTC_REG_IER14 PDL_INTC_REG_IERO5 PDL_INTC_REG_IER15 PDL_INTC_REG_IERO6 PDL_INTC_REG_IER16 PDL_INTC_REG_IERO7 PDL_INTC_REG_IER17 PDL_INTC_REG_IER08 PDL_INTC_REG_IER18 PDL_INTC_REG_IERO9Q PDL_INTC_REG_IER19 PDL_INTC_REG_IEROB PDL_INTC_REG_IER1A PDL_INTC_REG_IEROC PDL_INTC_REG_IER1B PDL_INTC_REG_IEROD PDL_INTC_REG_IER1C PDL_INTC_REG_IEROE PDL_INTC_REG_IER1D PDL_INTC_REG_IEROF PDL_INTC_REG_IER1E PDL_INTC_REG_IER10 PDL_INTC_REG_IER1F PDL_INTC_REG_IER11 Page 76 of 487 RX63N Group 4 Library Reference IPR register definitions
292. _NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data or for ID cycle in Multi processor mode data4 The number of bytes that must be received before the function completes or the callback function is called Specify 0 for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func1 Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Transfer method Parameter Pollin PDL_NO_FUNC This function will continue until the required number of bytes has 9 been received The function to be called when the number of received bytes reaches the threshold Interrupts number DMAC Either the function to be called when each byte is received or PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create func2 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors True if all parameters are valid and the operation completed false if a parameter was out of range SCl R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 293 of 487 Jul 19 2012 RX63N Group 4 Library Reference Reference R_SCI_Control R_SCl_GetStatus R_SCI_Create R_SCl_Send Rema
293. _P30 or PDL_SPI_MISOB_PE3 or Select the MISOB pin PDL SPI MISOB PE7 PDL_SPI_SSLBO_P31 or PDL_SPI_SSLBO_PE4 PDL_SPI_SSLB1_P50 or PDL SPI SSLB1 PEO PDL_SPI_SSLB2_P51 or PDL SPI SSLB2 PE1 PDL_SPI_SSLB3_P52 or PDL SPI SSLB3 PE2 Select the SSLBO pin optional Select the SSLB1 pin optional Select the SSLB2 pin optional Select the SSLB3 pin optional R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 325 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example data3 e Additional pin selection for channel 2 PDL_SPI_SSLCO_PD4 Select the SSLCO pin optional PDL_SPI_SSLC1_PD5 Select the SSLC1 pin optional PDL_SPI_SSLC2_PD6 Select the SSLC2 pin optional PDL_SPI_SSLC3_PD7 Select the SSLC3 pin optional True if all parameters are valid otherwise false SPI R_SPI_Create e Before calling R_SPI_Create call this function to configure the relevant pins Pins which are not used for the SPI functions may be omitted Channel 2 is not available for 100 pin package If channel 2 is selected pins for RSPCKC MOSIC and MISOC will be enabled Same pin cannot be used for different pin functions RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h
294. _SCI_PIN_SCI1_RXD1_P15 PDL_SCI_PIN_SCI1_TXD1_P16 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 283 of 487 RX63N Group 4 Library Reference 2 R_SCI_Create Synopsis SCI channel setup Prototype bool R_SCI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Bit rate or register value uint8_t data4 Interrupt priority level uint8_t data5 Interrupt priority level Description 1 4 Set up the selected SCI channel data1 Select channel SCIn where n 0 to 12 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold e Operation mode PDL_SCI_ASYNC or Choose between Asynchronous PDL_SCI_SYNC or Clock synchronous includes SPI and IIC PDL_SCI_SMART or Smart Card Interface or PDL_SCI_ASYNC_MP Multi Processor Asynchronous operation e Transmit Receive connections Not applicable in IIC Mode option will be ignored PDL_SCI_TX_CONNECTED or F PDL_SCI_TX DISCONNECTED The TXDn output is required not required PDL_SCI_RX_CONNECTED or F F PDL_SCI_RX DISCONNECTED The RXDn input is required not required e Data transfer format Not applicable in IIC Mode option will be ignored PDL_SCI_LSB_FIRST or Select least t
295. _Set R20UT1963EE0100 Rev 1 00 REN ESAS Page 250 of 487 Jul 19 2012 RX63N Group Remarks this function e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Ensure that the timer channel is stopped before calling this function The timing limits depend on the frequency of the peripheral module clock PCLKB 4 Library Reference e Function R_CGC_Set must be called with the current clock source selected before using fecike MHz Equation 50 48 12 5 12 32 8 8 Periodmin 160ns 167ns 640ns 667ns 250ns 1 0us Socixe 2 Periodmax 671ms 699ms 2 68s 2 798 1 05s 4 19s Srcuxe fmax frare 6 25 MHz 6 0 MHz 1 56 MHz 1 5 MHz 4 0 MHz 1 0 MHz 8 fmin froe 1 49Hz 1 43Hz 0 37Hz 0 357 Hz 0 95 Hz 0 24 Hz 2 e If the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period Program example RPDL definitions include fE include r pdl_cmt h RPDL device specific definitions r pdl_definitions h void func void Configure C Co R_CMT Co
296. _Set to select the input TMCIn TMRIn and output TMOn pins as required This function will return false if a pin is enabled but is not set properly A closed clock loop will be created if The overflow signal from TMR1 is selected for TMRO and the compare match A signal from TMRO is selected for TMR1 or The overflow signal from TMR3 is selected for TMR2 and the compare match A signal from TMR2 is selected for TMR3 Either case should be avoided e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 230 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure TMRO PCLKB clear after a compare match A R_TMR_CreateChannel 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_NO_DATA 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 AS Page 231 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 3 R_TMR_CreateUnit Synopsis Prototype Description 1 2
297. _TX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for data transmission data3 The start address of the storage area for any received data If the DMAC or DTC shall be used to handle the received data specify PDL_NO_PTR data4 The number of bytes in the storage area If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC If not using the DMAC or DTC this function will continue until a Stop or Re Start condition is detected or the master tries to read Polling data from this slave If using the DMAC or DTC the function will return after detecting a slave address match so that the DTC DMAC can complete the transfer The function to be called when a Stop or Re Start condition is detected or Return value Interrupts the master tries to read data from this slave DMAC or DTC The function to be called when a Stop or Re Start is detected data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false Category C Reference R_IIC_Create R_IIC_GetStatus R_IIC_SlaveSend R20UT1963EE0100 Rev 1 00 ZEN
298. _WDT_WIN_START_25 or PDL_WDT_WIN_START_50 or PDL_WDT_WIN_START_75 or PDL_WDT_WIN START_100 The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Window End Position PDL_WDT_WIN_END_Oor PDL_WDT_WIN_END 25 or PDL_WDT_WIN_END_50 or PDL_WDT_WIN_END 75 The window end position specified as a percentage of the down counter 0 is when the down counter would underflow Hence specifying 0 is equivalent to no window end position True if all parameters are valid and exclusive otherwise false Watchdog Timer R_INTC_CreateExtInterrupt R_MCU_OFS R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 271 of 487 RX63N Group 4 Library Reference Remarks e If using the Initial Setting Memory using R_LMCU_OFS to enable the WDT from reset this e function will have no effect e If configuring to use a NMI handler then R_INTC_CreateExtInterrupt must be used to enable the NMI for WDT The timing limits depend on the frequency of the peripheral module clock PCLKB nx cycles Srcike Period nx cycles or Frequency PCLKB Where n 4 64 128 512 2048 or 8192 cycles 1024 4096 8192 16384 Example periods are given below for fecixs SOMHz Time out cycles 1024 4096 8192 16384 Period pcik 4 81 9 us
299. _definitions h void func void uintl6_t status Read the MCU status registers R_MCU_Get Status amp status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 108 of 487 RX63N Group 4 Library Reference 3 R_MCU_OFS Synopsis Configure the device start up operation Prototype R_MCU_OFS uint32_t data1 uint32_t data2 uint32_t data3 uint32_t data4 WDT configuration options II WDT configuration options LVD configuration options II CGC configuration options Description 1 2 Select the auto start settings to be stored in registers OFS0 and OFS1 data1 Select the post reset IWDT configuration settings If multiple selections are required use to separate each selection Auto start control PDL_MCU_OFS_IWDT_HALTED or PDL MCU OFS _IWDT AUTOSTART Disable or enable the IWDT auto start mode If auto start mode is enabled select one setting from each of the following e Timeout period PDL_MCU_OFS_IWDT_TIMEOUT 1024 or ar POL_NCU_OFS_WDT TMEOUT 086 or yout pero specified in cycles of th PDL_MCU_OFS_IWDT_ TIMEOUT 8192 or division selection ee PDL_MCU_OFS_IWDT_TIMEOUT_ 16384 me i i e Clock division PDL_MCU_OFS PDL_MCU_OFS PDL_MCU_OFS PDL_MCU_OFS PDL_MCU_OFS PDL MCU OFS IWDT IWDT IWDT IWDT IWDT IWDT CLOCK_LOCO_1 or CLO
300. _definitions h void func vo Configure SDRAM id R_BSC_SDRAM_CreateArea 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 PDL_BSC_SDRAM_WIDTH_32 FFFu Ou Ou 2u Ou 2u lu Ou Ou Ou 0x0220u 8 bit width 10 bit address shift PDL_BSC_SDRAM_8_BIT_SHIFT R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 142 of 487 RX63N Group 4 Library Reference 7 R_BSC_GetStatus Synopsis Prototype Description Read the status registers of External Bus amp SDRAM Controller bool R_BSC_GetStatus uint8_t data1 uint16_t data2 uint8_t data3 A pointer to the data1 storage location A pointer to the data2 storage location A pointer to the data3 storage location Read the status registers of Bus amp SDRAM Controller data1 The status flags shall be stored in the format Specify PDL_NO_PTR if this information is not required b7 b6 b4 b3 b2 b1 bO 000b CPU Timeout Illegal address access 0 0115 DTCIDMAC 0 0 None 0 None 110b EDMAC 1 Generated 1 Detected 111b EXDMAC i i data2 The status flags shall be stored in the format Specify PDL_NO_PTR if this information is not required b15 b3 b2 b0 The upper 13 bits of an address that was accessed when a bus error occurred 0 in units of 512 Kbytes data3 The SDR
301. _length PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 343 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_IEB_MasterReceive Synopsis Prototype Description Return value Category Reference Receive data over an IEBus channel bool R_IEB_MasterReceive uint8_t data1 Channel selection uint16_t data2 Communication configuration uint16_t data3 Slave address uint8_t data4 Data storage start address uint8_t data5 Data length storage address void func Callback function Receive data on the specified channel data1 Select channel n where n 0 only data2 Configure the channel mode and connection settings If multiple selections are required use to separate each selection The default settings are shown in bold e Data type and control PDL_IEB_STATUS or PDL_IEB_LOCKED_ADDRESS_UPPER or PDL_IEB_LOCKED_ADDRESS_LOWER or PDL_IEB_DATA The slave shall send the specified data in the data field After sending the status the slave will unlock PDLIEB_UNLOGK Optional applicable only if Status is selected above e Re transmission count PDL_IEB_RETRY_0or PDL_IEB_RETRY_1 or PDL_IEB_RETRY_2 or PDL_IEB_RETRY_3 or PDL_IEB_RETRY_4 or PDL_IEB_RETRY_5 or PDL_IEB_RETRY_6 or PDL_IEB RETRY 7 The number of re transmissions to be attempted if arbitration is lost d
302. _pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Toggle the priority to the Internal Peripheral Bus 1 between Main Bus 1 and Main Bus 2 R_BSC_Set PDL_BSC_PRIORITY_PB1_MB1 i R20UT1963EE0100 Rev 1 00 R AS Page 130 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 2 R_BSC Create Synopsis Prototype Description 1 3 Configure the external bus operation bool R_BSC_Create Bus Bus uint32_t data1 uint32_t data2 uint16_t data3 uint8_t data4 void func uint8_t data5 II Call control pin selection address pin selection II Recovery cycle insertion Error control back function Interrupt priority level Configure the I O pins cycle insertion error detection and register the callback function data1 Configure the bus control signals Use to separate each selection Chip select pin selection only required for each external memory area that will be enabled PDL_BSC_CS0_P60 or PDL_BSC_CSO_PC7 Select the port pin to be used for signal CSO PDL_BSC_CS1_P61 or PDL_BSC_CS1_P71 or PDL_BSC_CS1_PC6 Select the port pin to be used for signal CS1 PDL_BSC_CS2_P62 or PDL_BSC_CS2_P72 or PDL_BSC_CS2_PC5 Select the port pin to be used for signal CS2 PDL_BSC_CS3_P63 or PDL_BSC_CS3_P73 or PDL_BSC_CS3 PC4 Select the port pin to
303. _sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 9 define SLAVE_ADDRESS OxAO Buffer for IIC data extern uint8_t IIC_Buffer 10 void func void Wait while send 10 bytes R_SCI_IIC_Write CHANNEL_SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 IIc_Buffer PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 300 of 487 Jul 19 2012 RX63N Group 4 Library Reference 8 R_SCI_IIC_Read Synopsis Prototype Description 1 2 Perform an IIC master read on an SCI channel bool R_SCI_IIC_Read uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave Address uint16_t data4 Number of bytes to transfer uint8_t data5 Buffer void func Callback function Perform an IIC master read data1 Select channel SCIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL_SCI_IIC_10_BIT_SLAVE_ADDRESS Specify the slave address width Repeated Start PDL_SCI_IIC_RESTART The transfer will
304. a TGRF event occurs Specify PDL_NO_FUNC if not required interrupt_priority_2 The interrupt priority level for TGRE and TGRF Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 5 and 6 func7 For n 0 to 3 The function to be called when an overflow occurs For n 4 The function to be called when an overflow or underflow occurs Specify PDL_NO_FUNC if not required func8 Forn 1or2 The function to be called when an underflow occurs Specify PDL_NO_FUNC if not required interrupt_priority_3 The interrupt priority level for overflow or underflow events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 7 to 8 True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference R_MTU2_Set R_MTU2_ControlChannel R_MTU2_ControlUnit R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 185 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Program example e Ifan external clock input pin MTCLKx or I O pin MTIOCnx is made active this function will configure that pin for input or output and disable other functions on that pin e Call R_MTU2_Set before calling this function to select the pins to be used e Either RLMTU2_ControlChannel or R_LMTU
305. a anne deed 200 R POE Creates n eia nae tend ents ned ine aac tended a a a a nana Aa 202 R POE Control tance ncn oh ae ie nen eae ene ee EN 204 R POE GetStatus 2 finned tai nt e ae ene i a ieee ee ee 206 16 bit Timer Pulse Unite co c0 secon ben ent reso ens nes eden desde aE E eaa eraan ee eben eee 207 RiP PU S Oia ewe a nna tend e nab a Gags ne nde i ae ate ee nae acne ee 207 R TPU Create sce nw naar ann eh ee iene ene ieee lene a eee 210 R TPU DESO rii lisse treet e aea aaa ied atedas a eaa a eean oae adian 216 RAFPU Control pnois e tienen nade a a a Ne ie es eee ee E 217 ROTPU Read tiie ceri tenes aes tend enue tabi aan ne adden ie a aedeagal 219 Programmable Pulse Generator ceccceeeeeeeeeeeeeee ee erent ee eeeaeeeeesaeeeeeeaaeeeeeeaeeeeeeaeeeeeenaeeeeeeaas 221 R PPG Create icc uiten i aa Mastette e eea aaa Ea aaa ad di aMoas Ph caste aae aaau i aa 221 R PPG Destroy iiit ae aa ae e eaaa aaae ien saa aaea Aaa aaaeeeaa aena i a aAa 224 Ro PPG Control icc eae aeaa en aa aaae a aaa anata aaa eaaa aa aaa eaaa 226 BDI PIME eene ea aea a e e a aea Ui raaa ae ae aaa eara dias Metts bests takin 227 ReTMR Seti eieae adaa en a aa aaae iaaa eae aaa eaae aa aE eataa 227 R TMR Createchanne lti aca iaaa e aaae aaan ataata eaae iaia aa ea et bets 229 R amp rMRCreateynit aae e aa aa aaa a tide eet aaan a oaa a ertan iaaa aeaee 232 R TMR2GreatePeriodic siina aieeaa anena deateeastaddas cdeneeesaa cnn uongeassetadavteaen dane eaads 235 RoT
306. ack to the port data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The logical operation to be applied to the port or port pin PDL_IO_PORT_AND or PDL_IO_PORT_OR or PDL_IO_PORT_XOR Select between AND amp OR or Exclusive OR data3 The value to be used for the modification Between 0x00 and OxFF for a port O or 1 for a pin True if the parameters are valid otherwise false I O port None e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Invert port pin P05 R_IO_PORT_Modify PDL_IO_PORT_0_5 PDL_IO_PORT_XOR 1 i And the value port 6 with 0x55 R_IO_PORT_Modify PDL_IO_PORT_6 PDL_IO_PORT_AND 0x55 di RENESAS Page 99 of 487 RX63N Group 4 Library Reference 8 R_lO_PORT_Wait Synopsis Prototype Description Return value Wait for a match on an I O port bool R_IO_PORT_Wait uint16_t data1 Output port or port pin selection uint8_t data2 Comparison value Loop until an I O port or I O port pin matches the comparison value data1 Use either one of the following definition values from 4 2 3 e One port definition or
307. aea Ta aa a a aee a aa aa Saana Da aa aa Eea na Ea DE a SaaS Tai 86 AF AE EEIN Ooa LES EET EEE A EE E A E E N A 88 4 2 3 UO ROM e eee eres a Ceasers wide oh Pee e E A ER 89 AAO ROR Set a A steed hbase ret aa a a a ata a aie 91 2 RIO PORT Read Control e e ta vastuccratecsnalvessacqeaadaestabsa shoud caseddeveian canteen tans 92 3 RIO PORT _ModifyControl 200 00 2 cccccccccccceeeeeeeeecececeeeeeeececeaeeeeeeeeesesaaaeceeeeseeseccaaeeeeeeeeesensnneeeeees 94 4 RAO PORT Readwicci ncdk aia i nein uence ea Near ee eee aa E AG 96 5 RAO PORT Write meenomen ei rich atta i eaae deduct tates ddan Piet eee 97 NOORWNANGABRWNHANGTRWNHAMBRWNHANNOMTBRWNHAMNANOBRWHD DODGER HS SIF ON AS LVS SLS n BSNS LOSE BSL LPS LPS GG VELL RIO PORT Compare sans t civ iaaenn ieee nee Pen en ee va ee ea es 98 RJO PORT Modify oaii nated does ie nae ined a age ees tee a ee ee 99 R10 PORT Wait netic ace a e a niin aan tendon iat a en ee 100 R0 PORT NotAvailable c ccceccctnten ee tence a cided needed naan ee aie take need 101 Multifunction Pin Controller cccceceecccceceeeeeeececeeeeeeececacaeceeeeeeesecaaaeeeeeeeeeseccieaeeeeeeeeetennaees 102 RIMPC Read jac i area bor ee aioe ee tena a ae nee in ey 103 RoOMPC Write neet eet heey na tend tatu net a aan lend a a nnn ee 104 RoOMPC gt Modify tc ce tu ate beh ee ia S a ten A at ete ne a a 105 MCU Operation ee aee tent ccctetidieds a a lia tiea ctl a aaae Hd statue a araa aa aa aaaea aaea aa 10
308. allback function depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will handle the data transfer until Pollin 9 completion or an error occurs The function to be called when the transfer has completed or an error has occurred Parameter data4 in R_IEB_Create must not be 0 Interrupts True if all parameters are valid exclusive and achievable the channel was available and a normal transfer completed when polling otherwise false IEBus R_IEB_ Create R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 342 of 487 RX63N Group 4 Library Reference Remarks Program example e Ifa callback function is specified interrupts are used The callback function may be called more than once during a transfer Use R_IEB_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 In polling mode this function will use the status flags to monitor the data transmission If the IEBus channel s registers are modified directly by the user this function may lock up RPDL definitions include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t iebus_data 32 uint8_t iebus_data_length Send data to slave 456h R_IEB_MasterSend 0 PDL_IEB_DATA 0x0456 iebus_data iebus_data
309. als that were active when that mode was entered will be re activated When the flash memory is in program or erase mode do not call this function if it will result in the power mode changing This function will return false is this situation When the PLL is operating low speed operating mode 1 or 2 cannot be selected This function will return false is this situation The Low speed operating modes put restrictions on the allowable clock ranges for ICLK FCLK PCLKB and BCLK This function will return false if any of these clocks are not within the range specified in the Hardware Manual RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Enter deep software standby mode R_LPC_Control PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY Clear the I O port state retention R_LPC_Control PDL_LPC_IO_RELEASE R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 123 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_LPC_WriteBackup Synopsis Prototype Description Return value Category References Remarks Program example Write to the Backup registers bool R_LPC_WriteBackup uint8_t data1 Data pointer uint8_t data2 Data count Write data into the backup registers data1 The data to be w
310. alue uint16_t reference_count 1 Configure channel 0 R_MTU2_Create 0 amp mtu_create_parameters Configure MTU channel 1 Load the MTU Create defaults R_MTU2_Create_load_defaults amp mtu_create_parameters Set the channel 1 options Normal operation mtu_create_parameters channel_mode PDL_MTU2_MODE_NORMAL Counter input is PCLK counter cleared by input capture A mtu_create_parameters counter_operation PDL_MTU2_CLK_PCLK_DIV_1 TU2_CLEAR_TGRA Input capture is compare match A of channel 0 mtu_create_parameters TGR_A_B_ operation PDL_MTU2_A_IC_CM_IC Set the callback function m m tu_create_parameters funcl Read_the_MCK tu_create_parameters interrupt_priority_1l 5 Configure channel 1 R_MTU2_Create 1 amp mtu_create_parameters i mck_completed false Set Control options to start the timers mtu_control_parameters control_setting PDL_MTU2_START mtu_control_parameters register_selection PDL_NO_DATA Start MTU channel 0 R_MTU2_ControlChanneli 0 mtu_control_parameters R20UT1963EE0100 Rev 1 00 a2 AS Page 388 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples i Start MTU channel 1 R_MTU2_ControlChanneli 1 mtu_control_parameters i Discard the first reading while mck_completed false mck_completed false while 1 Is
311. analog input channels then ensure that the storage area has room for all 21 channels Only active channels will be read and the value stored in the appropriate array location If the unit is configured to read the temperature sensor or the reference voltage then only a single 16 bit storage is required e Thed If no ata alignment is controlled using the R_LADC_12_Create function callback function is used this function waits for the S12ADI0 flag to indicate that conversion is complete before reading the results If the ADC unit s control registers are direct RPDI ly modified by the user this function may lock up L definitions include r_pdl_adc_12 h RPDI L device specific definitions include r_pdl_definitions h void func void uintlo6_t ADCresult 21 Read the ADC R_ADC_12_ Read 0 ADCresult R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 363 of 487 RX63N Group 4 Library Reference 4 2 29 10 bit Analog to Digital Converter 1 R_ADC_10 Set Synopsis Prototype Description Return value Select the I O pins for 10 bit ADC bool R_ADC_10_Set uint16 tdata ADC unit selection Select the I O pins for 10 bit ADC data Select the pin set options To set multiple options at the same time use to separate each value e Pin selection
312. are Standby cancel request detection 0 No activity 1 The exit from deep software standby was caused by one of the following signals IRQ7 DS IRQ6 DS IRQ5 DS IRQ4 DS IRQ3 DS IRQ2 DS IRQ1 DS IRQ0 DS data2 The status flags shall be stored in the format below b7 b6 b5 b4 b3 b2 b1 bO Deep Software Standby cancel request detection 0 No activity 1 The exit from deep software standby was caused by one of the following signals IRQ15 DS IRQ14 DS IRQ13 DS IRQ12 DS IRQ11 DS IRQ10 DS IRQ9 DS IRQ8 DS Return value True Category LPC References R_LPC_Create R_LPC_Control Remarks e Ifa flag is set to 1 it shall be automatically cleared to 0 by this function apart from the Operating Power Control Mode transition flag R20UT1963EE0100 Rev 1 00 REN ESAS Page 126 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t status_flags1l uint8_t status_flags2 Find out what caused the exit from deep software standby R_LPC_GetStatus amp status_flagsl amp status_flags2 R20UT1963EE0100 Rev 1 00 AS Page 127 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 4 2 9 Register Write Protection 1 R_RWP_Coni
313. arks section for the maximum rate that the device can support Or the following using to separate each selection e b31 b30 b24 b23 b0 A value between 256 0x100 and 16 776 960 OxFFFFOO that is 1 0 nearest to the expected transfer bit rate If using an external clock this must be provided as it is used for internal timings e ABCS selection required for asynchronous mode PDL_SCI_CYCLE_BIT_16 or PDL_SCI_CYCLE_BIT_8 Select 16 or 8 base clock cycles for one bit period e CKS selection required if the on chip baud rate generator is selected as the data clock source PDL_SCI_PCLK_DIV_1 or PDL_SCI_PCLK_DIV_4 or Select the internal clock signal PCLKB 1 4 16 or 64 as PDL_SCI_PCLK_DIV_16 or the baud rate generator clock source PDL_SCI_PCLK_DIV_64 e BRR setting required if the on chip baud rate generator is selected as the data clock source The BRR register value between 0 and 255 data4 The interrupt priority level for data transmission Select between 1 lowest priority and 15 highest priority This parameter may be zero if the following functions will not be used with a callback function R_SClI_Send R_SCI_Receive R_SCI_SPI_Transfer R_SCI_IIC_Write and R_SCI_IIC_Read data5 The interrupt priority level for receive error detection Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is spe
314. art of next data transfer PDL_INTC VECTOR _TEI3 End of data transfer R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 69 of 487 RX63N Group 4 Library Reference Description 4 4 PDL_INTC_VECTOR_RXI4 Data received PDL_INTC_VECTOR_TXI4 SCI channel 4 Start of next data transfer PDL_INTC_VECTOR_TEI4 End of data transfer PDL_INTC VECTOR _ RXI5 Data received PDL_INTC VECTOR _TXI5 SCI channel 5 Start of next data transfer PDL_INTC VECTOR _TEI5 End of data transfer PDL_INTC_VECTOR_RXI6 Data received PDL_INTC VECTOR _TXI6 SCI channel 6 Start of next data transfer PDL_INTC_VECTOR_TEI6 End of data transfer PDL_INTC VECTOR _ RXI7 Data received PDL_INTC VECTOR _TXI7 SCI channel 7 Start of next data transfer PDL_INTC_VECTOR_TEI7 End of data transfer PDL_INTC VECTOR RXI8 Data received PDL_INTC VECTOR _TXI8 SCI channel 8 Start of next data transfer PDL_INTC_VECTOR_TEI8 End of data transfer PDL_INTC_VECTOR_RXI9 Data received PDL_INTC_VECTOR_TXI9 SCI channel 9 Start of next data transfer PDL_INTC VECTOR _TEI9 End of data transfer PDL_INTC_VECTOR_RXI10 Data received PDL_INTC_VECTOR_TXI10 SCI channel 10 Start of next data transfer PDL_INTC_ VECTOR _TEI10 End of data transfer PDL_INTC_VECTOR_RXI11 Data received PDL_INTC_ VECTOR_T
315. as been used and then a warm reset is performed it is not necessary to call RLRTC_Create again before using this function However it is necessary to call R_CGC_Control or R_CGC_Set to enable the subclock even if it is already enabled before calling this function R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 267 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the alarm calendar R RTC Control DISABLE ALARM_TIME Change the day R_RTC_Control PDL _RTC_ALARM DATE PDL_RTC_UPDATE PDL NO DATA PDL_NO DATA 0x00105300 PDL_NO DATA PDL_NO DATA PDL_NO DATA PDL_NO DATA PDL NO DATA PDL_NO DATA and update the alarm time Alarm at 10 53 to the 23rd PDL_NO_DATA PDL_RTC_UPDATE_CURRENT_DOW PDL_RTC_UPDATE_CURRENT_DAY OxFF000000 0x00000023 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 REN ESAS Page 268 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_RTC_Read Synopsis Prototype Description Read the Real time clock status flags and counters bool R_RTC_Read uint8_t da
316. assignable parameters separating each argument with argument Return value Describes the returned value of the API function Category Indicates the category of the API function Reference Indicates the API functions to be referred Remark Describes notes to use the API function Program example Represents how to use the API function by a program example Two examples of return value checking are shown below RPDL definitions include r_pdl_mpc h include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void bool result Write OxFF to register MPC1 result R_MPC_Write 1 OxFF i if result false Handle th rror here Keep trying to send a string if the channel is busy do result R_SCI_Send 2 Renesas RX NULL PDL_NO_FUNC whil result false For clarity the return value is not checked in the examples used in this manual The RPDL API is implemented using function macros To avoid the possibility of parameters being evaluated more than once do not use operators or function calls within the RPDL API parameter list R20UT1963EE0100 Rev 1 00 Page 54 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 4 2 1 Clock Generation Circuit 1 RCGC Set Synopsis Prototype Description 1 2 Configure the clock
317. aster mode with DTC In the following example data is written to an EEPROM in two bursts The DTC is used to handle the data transfer The same EEPROM address locations are then read out in two bursts The DTC is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_end_handler void void iic_rx_end_handler void define EEPROM_MEMORY_ADDRESS_UPPER 0x00 define EEPROM RY_ADDRESS_LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM_MEMORY_ADDRESS_UPP define ITIC_CHANNEL 0 volatile uint8_t bus_busy volatile uint8_t data_storage 20 Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00002000 uint32_t dtc_vector_table 256 Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 void main void define ARRAY_1_SIZE 6 5 Data 1 address define ARRAY_2_SIZE 11 10 Data 1 address const uint8_t eeprom_data_array_1 ARRAY_1_SIZE EEPROM_MEMORY_ADDRESS_LOWER 0x11 0x22 0x33 0x44 0x55 const uint8_t eeprom_data_array_2 A
318. at declared in R_DTC_Create If no registers are to be modified specify PDL_NO_PTR data3 The new source start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data4 The new destination start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data5 The new number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers Specify PDL_NO_DATA if not required data6 The new size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode Specify PDL_NO_DATA if not required True if all parameters are valid and exclusive otherwise false Category Data Transfer Controller Reference R_DTC_Create R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 170 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Program example e This function must be called in order to start the DTC R_DTC_Create must be called at least once before starting the DTC Start the DTC before generating a transfer trigger RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Start the controller R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_P
319. ata3 The slave address valid from 0000h to OFFFh data4 The start address of the area for storing the data to be received in the data field data5 The address of the area for storing the number of bytes that were received in the data field func Specify PDL_NO_FUNC or a callback function depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will handle the data transfer until Pollin i 9 completion or another event occurs The function to be called whenever a transfer has completed or another Interrupts event has occurred Parameter data4 in R_IEB Create must not be 0 True if all parameters are valid exclusive and achievable the channel was available and a normal transfer completed when polling otherwise false IEBus R_IEB_ Create R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 344 of 487 RX63N Group 4 Library Reference Remarks e Ifa callback function is specified interrupts are used The callback function may be called more than once during a transfer Use R_IEB_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 In polling mode this function will use the status flags to monitor the data reception If the IEBus channel s registers are modified directly by the user this function may lock up Program example RPDL definition
320. ate the pins for signals POEO to POE3 and POES8 If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required PDL_POE_0_PORT_C_4 or p i PDL POE 0 PORT D 7 Pin POEO input selection PDL_POE_1_PORT_B_5 or f PDL POE 1 PORT D 6 Pin POE1 input selection PDL_POE_2_PORT_3_4 or PDL_POE_2_PORT_A 6or Pin POE2 input selection PDL_POE_2 PORT_D 5 PDL_POE_3_PORT_3_3 or PDL_POE_3_PORT_B_3or Pin POE3 input selection PDL_POE_3_ PORT_D_4 PDL_POE_8 PORT_1_7 or PDL_POE_8 PORT_3 0or f f PDL POE 8 PORT D 3or Pin POE8 input selection PDL_POE_8 PORT_E 3 R20UT1963EE0100 Rev 1 00 ztENESAS Page 200 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example data3 Configure pin output control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required e High impedance request detection PDL_POE_HI_Z_REQ_8 ENABLE PDL_POE_HI_Z REQ MTIOCOA PDL_POE_HI_Z REQ MTIOCOB PDL_POE_HI_Z REQ MTIOCOC PDL POE HI Z REQ MTIOCOD If a request is detected on pin POE8 place the MTU channel 0 I O pins in the high impedance state Select the MTU channel 0 I
321. atus 0 Overrun 0 level 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High IIC Mode b7 b1 bO ACK NACK flag 0 This is updated every time an ACK or NACK is received 0 ACK received 1 NACK received data3 The storage location for the last byte that was received Specify PDL_NO_PTR if this information is not required data4 The storage location for the number of characters that are have been transmitted in the current transmission Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available data5 The storage location for the number of characters that are have been received in the current reception process Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available Return value True if all parameters are valid and the operation completed false if a parameter was out of range or the RX pin has not been selected by using the R_SCI_Set and or R_SCI_Receive functions Category SCI Reference R_SCI_Set R_SCI_Receive R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 306 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks e The error flags are not modified by this function They are cleared when a new reception process is started e Device packages with 100 pins do not have all o
322. available with the 100 pin package This function will return false in this case RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 1 byte on channel 0 and stop R_IIC_MasterReceiveLast 0 amp data_array 4 i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 318 of 487 Jul 19 2012 RX63N Group 4 Library Reference 6 R_IIC_SlaveMonitor Synopsis Prototype Description Monitor the bus bool R_IIC_SlaveMonitor uint8_t data1 Channel selection uint16_t data2 Channel configuration uint8_t data3 Receive data start address uint16_t data4 Receive threshold void func Callback function uint8_t data5 Interrupt priority level Monitor the bus until an address match occurs and store any data received Register the storage area and transfer method for data received on the selected 1 C channel data1 Select channel IICn where n 0 to 3 data2 Select the operation options The default setting is shown in bold Specify PDL_NO_DATA to use the default e DMAC DTC trigger control PDL_IIC_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_RX_DMAC_TRIGGER_ENABLE or DMAC or DTC when a byte is PDL_IIC_RX_DTC_TRIGGER_ENABLE received PDL_IIC_TX_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_TX_DMAC_TRIGGER_ENABLE or PDL_IIC
323. ave Serial Peripheral Interface use R20UT1963EE0100 Rev 1 00 az AS Page 469 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 20 IEBus Interface 5 20 1 Master operation Figure 5 51 shows how the status of a slave unit is checked and data is sent to or transferred from it The slave status is read as one byte with the contents in the format b7 b6 b5 b4 b3 b2 b1 bO Highest mode supported Transmission status Lock status 7 Buffer status z 0 1 20r3 0 Halted 0 Unlocked 0 Empty 0 Empty a 1 Enabled 1 Locked 1 Contains data 1 Data available Peripheral driver function prototypes include r_pdl_ieb h include r_pdl_cgc h include r_pdl_cmt h include r_pdl_io_port h PDL device specific definitions include r_pdl_definitions h include lt string h gt define LEDO PDL _IO_PORT_ define LED1 PDL_IO _PORT_ void main void const uint8_t iebus_tx_data_a 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 5 26 27 28 29 30 31 32 3 uint8_t iebus_rx_data 32 uint8_t iebus_rx_data_length 0 uint8_t iebus_slave_status 0 uint8_t counter uintl6_t General_flags uint8_t Tx_status uint32_t Rx_status Configure the clocks Prepare the main clock settings R_CGC_Set PDL_CGC_CLK_MAIN L_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABLE Pi oD NNDNODHNOE L_NO_DAT L_NO_DAT L_NO_DAT
324. be ignored e Do not use this function in SPI mode use R_SCI_SPI_Transfer e Do not use this function in IIC mode use R_SCI_IIC_Write e When using interrupts to manage the transfer if the channel is operating in synchronous mode transmit only and with an external clock the TXD pin may need to be held active for longer up to half a bit period to avoid violating the data hold time for the receiving device If a delay is required the user should refer to the comments in the Transmit End interrupt processing routines in the file interrupt_SCl c in the i_src folder and implement the delay in a way that is suitable for their application If using the DMAC or DTC this module does not know when the transmission has ended Therefore when it has completed the user must call the R_SCI_Control function with option PDL_SCI_STOP_TX to manually disable the transmission e Ifa callback function is specified and the interrupt priority level is zero this function will return false e Device packages with 100 pins do not have all of the SCI channels R20UT1963EE0100 Rev 1 00 Page 291 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data_store 100 Send a string on channel 1 R_SCI_Send 1 PDL_NO_DATA Renesas RX 0 PDL_N
325. be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limite
326. c definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_CMT_Destroy 0 3 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 254 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_CMT_Conirol Synopsis Prototype Description Control CMT operation bool R_CMT_Control uint8_t data1 Channel selection uint16_t data2 Configuration selection double data3 Period frequency or register data Modify the operation of a CMT channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer channel To set multiple options at the same time use to separate each value e Counter stop re start PDL_CMT_STOP Disable the counter clock source PDL_CMT_START Enable the counter clock source e Value change request PDL_CMT_PERIOD or The parameter data3 will contain the new period PDL_CMT_FREQUENCY or frequency PDL_CMT_CONSTANT or constant register CMCOR or PDL_CMT_COUNTER counter register CMCNT value data3 The new period frequency or register value This will be ignored if a value change is not requested Data use Parameter type The timer period in seconds or double The timer frequency in Hz or double The value to be put in the selected register uint16_t Return value True if all parameters are valid and exclusive otherwise
327. c h RPDL device specific definitions include r_pdl_definitions h include lt string h gt const char source_string_1 RX63N volatile char destination_string_l J void func void Re enable transfers on channel 0 R_EXDMAC_Control 0 iw AC_ENABLE PTR PTR DATA DAT DAT DAT DAT r f ar Sao Siae ia e ae sO ae ae gogug00g C E ooo0oo0oo0o0o0x D Dpp Reload and trigger channel 1 R_EXDMAC_Control 1 PDL_EXDMAC_ENABLE PDL_EXDMAC_START PDL_EXDMAC_UPDATE_SOURCE PDL_EXDMAC_UPDATE PDL_EXDMAC_UPDATE_COUNT PDL_EXDMAC_UPDATE void source_string_l void destination_string_l 1 uintl6_t strlen source_string_1l PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA DESTINATION SIZE y R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 161 of 487 RX63N Group 4 Library Reference 5 R_EXDMAC_GetStatus Synopsis Prototype Description Check the status of an EXDMAC channel bool R_EXDMAC_ GetStatus uint8_t data1 Channel number uint8_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_
328. c4 uint8_t interrupt_priority_1 void func5 void func6 uint8_t interrupt_priority_2 void func7 void func8 uint8_t interrupt_priority_3 Set up a 16 bit MTU2 channel data1 The channel number n where n 0 to 5 channel_mode Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold Channel selection Apointer to the structure II Configuration selection II Configuration selection Configuration selection II Configuration selection II Configuration selection II Configuration selection II Configuration selection II Configuration selection II Register value Register value Register value Register value Register value Register value Register value Register value Register value Register value Callback function II Callback function Callback function Callback function Interrupt priority level II Callback function II Callback function Interrupt priority level II Callback function II Callback function Interrupt priority level e Operation mode Valid for n 0 to 4 unless stated otherwise PDL_MTU2_MODE_NORMAL or Normal operation PDL_MTU2_MODE_PWM1 or Pulse Width Modulation PWM mode 1 PDL_MTU2_MODE_PWW2 or Valid for n 0 1 and 2 Pulse Width Modulation PWM mode 2 PDL_MTU2_MODE_PHASE1 or PDL_MTU2_MODE_PHASE2 or
329. called before any use of this function The selected interrupt is enabled automatically Please see the notes on callback function use in 6 The NMI callback function should not return It should stop operation or reset the system If the NMI interrupt fails to initialise this function will return false RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function void CallBackFunc void void func void Configure the IRQ interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ1 PDL_INTC_FALLING CallBackFunc 7 Configure the NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_FALLING CallBackFunc 15 Configure the NMI triggered by the WDT only no NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_WDT_ENABLE CallBackFunc 10 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 65 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_INTC_CreateSoftwarelnterrupt Synopsis Prototype Description Return value Category Reference Enable use of the software interrupt bool R_INTC_CreateSoftwarelnterrupt uint8_t data1 Configuration void func Callback function uint8_t data2 Interrupt priority level Configure and enable the software interrupt data1 Ch
330. ce setting is ignored For more details of the phase counting mode please refer to the RX63N hardware manual 24 3 6 e If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC e If buffer operation is selected for registers TGRB and TGRD input capture output compare is not valid for register TGRD e If synchronous mode is required at least two channels must be enabled for synchronous operation e Channels 6 to 11 are not available for device packages with 100 pins R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 214 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tpu h RPDL device specific definitions include r_pdl_definitions h void func void Configure TPUO PCLK clear after a compare match A R_TPU_Create 0 PDL_TPU_MODE_NORMAL PDL_TPU_CLK_PCLK_DIV_1 PDL_TPU_CLEAR_CM_A PDL_NO_DATA PDL_NO_DATA 199 99 55y 66 88 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 TPUO_1V_callback PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 215 of 487 RX63N Group 4 Library Reference 3 R_TPU_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a
331. channel 4 Reading the status and operation registers of a channel R20UT1963EE0100 Rev 1 00 Page 29 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 14 External DMA Controller Driver The driver functions support the control of the external bus Direct Memory Access controller EXDMAC providing the following operations 1 Selecting the pins to be used 2 Configuration for use including e Access to all control bits e Automatic interrupt control 3 Disabling EXDMAC channels that are no longer required and enabling low power mode 4 Control of a channel 5 Reading the status and operation registers of a channel R20UT1963EE0100 Rev 1 00 az AS Page 30 of 487 Jul 19 2012 SENES RX63N Group 2 Driver 2 15 Data Transfer Controller Driver The driver functions support the control of the Data Transfer Controller providing the following operations Setting the central options 2 Configuration for use including support for chain transfers 3 Disabling the controller 4 Starting stopping or modifying the operation of the controller 5 Reading the status flags and data transfer registers R20UT1963EE0100 Rev 1 00 Page 31 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 16 Multi Function Timer Pulse Unit Driver The driver functions support the use of the six 16 bit timers providing the following operations 1 Selection of the MTU pins for use 2 Configuration for use includ
332. chieved by calling R_SCI_Receive in non polling mode and then R_SCI_Send Please refer to the usage example in Section 5 17 5 Do not use this function in SPI mode use R_SCI_SPI_Transfer Do not use this function in IIC mode use R_SCI_IIC_Read If using the DMAC or DTC this module does not know when the reception has ended Therefore when it has completed the user must call the R_SCI_Control function with option PDL_SCI_STOP_RX to manually disable the reception If a callback function func 1 is specified and the interrupt priority level is zero this function will return false Device packages with 100 pins do not have all of the SCI channels R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 294 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t SCI1ReceiveBuffer 10 SCI channel 1 receive data handler void SCI1RxFunc void SCI channel 1 error handler void SCI1lErrFunc void void func void uint8_t temp Wait for 1 character to be received on channel 0 R_SCI_Receive 0 PDL_NO_DATA amp temp 1 PDL_NO_FUNC PDL_NO_FUNC Start the reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA SCI1lReceiveBuffer 9 SCI1RxFunc SCI1ErrFunc R20UT1963EE0100 Rev 1 00 AS Page 295 of 487 Jul
333. cified for error callback function in R_SClI_Send or R_SCI_Receive This parameter may be zero if the following functions will not be used with a callback function R_SClI_Send R_SCI_Receive R_SCI_SPI_Transfer R_SCI_IIC_Write and R_SCI_IIC_Read True if all parameters are valid exclusive and achievable otherwise false Category SCI Reference R_CGC_Set R_SCI_Set R_SCl_Send R_SCI_Receive R_SCl_Control R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 287 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks e Function R_CGC_Set must be called with the current clock source selected before using this function e Function R_SCI_Set must be called before any use of this function e This function configures each SCI pin that is required for operation It also disables the alternative modes on those pins In Async and Async MP modes the Tx pin is initially set to the Mark state The R_SCI_Control function can subsequently be used to set the Space state e SPI Multi Master mode is not supported Hence in SPI Master mode the SS pin cannot be enabled e Device packages with 100 pins do not have all of the SCI channels e Ifthe option of using a delayed clock phase is selected in synchronous mode then a delay is required following the final receive interrupt before the operation can be completed This delay is implemented as a software loop in the
334. cluding Automatic baud rate clock calculations Automatic interrupt control Automatic I O pin configuration Supporting the following modes Asynchronous Multi Processor Clock Synchronous Smart Card Interface Simple IIC Simple SPI 000000 Disabling channels that are no longer required Transmitting data with polling or interrupt mode automatically selected Receiving data with polling or interrupt mode automatically selected Transmitting and or receiving data in SPI mode with polling or interrupt mode automatically selected Transmitting data in simple IIC mode with polling or interrupt mode automatically selected Receiving data in simple IIC mode with polling or interrupt mode automatically selected Transmitting the last byte of data in simple IIC mode 10 Control the channel operation 11 Reading the status flags Note The Clock Generation Circuit must be configured before configuring any serial channel R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 41 of 487 Jul 19 2012 RX63N Group 2 Driver 2 26 I2C Bus Interface Driver The driver functions support the use of the I C module providing the following operations 1 Configuration for use including e Automatic clock setting using transfer rate as an input e Automatic interrupt control 2 Disabling the module that is no longer required and enabling low power mode 3 Transmitting data in Master mode 4 Receiving data in Master mode 5 Compl
335. complementary PWM modes PDL_MTU2_OUT_BUFFER_TRANSFER_DISABLE or PDL MTU2 OUT BUFFER TRANSFER CRESTor crest PDL _MTU2 OUT BUFFER TRANSFER TROUGH or trough or PDL _MTU2 OUT BUFFER TRANSFER BOTH both Disable or enable on detection of In Reset synchronised PWM mode PDL_MTU2_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU2_OUT_BUFFER_TRANSFER_CLEAR e Buffer transfer to temporary transfer control Applicable for complementary PWM modes Disable or enable on counter clear PDL_MTU2_BUFFER_TRANSFER_LINK PDL_MTU2_BUFFER_TRANSFER_DISABLE or PDL_MTU2_BUFFER_TRANSFER_ENABLE or Disable transfers enable without linking to interrupt skipping or enable and link to interrupt skipping brushless _DC_motor_control Brushless DC motor control settings All settings are optional If multiple selections are required use to separate each selection Applies only to reset synchronised or complementary PWM modes Brushless DC motor waveform control PDL_MTU2_BDCM_ENABLE or PDL_MTU2_BDCM DISABLE PDL_MTU2_BDCM_P_PHASE_ENABLE or PDL_MTU2_BDCM P_PHASE_DISABLE PDL_MTU2_BDCM_N_PHASE_ENABLE or PDL_MTU2_BDCM_N PHASE DISABLE Enable or disable brushless DC motor control Enable or disable PWM outputs on the positive phase output pins Enable or disable PWM outputs on the negative phase output pins PDL_MTU2_BDCM_OPS FB or Use input capture signals for output switch control
336. cted 1 High 1 Rising 1 Detected True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_ControlExtInterrupt e The MPC registers are used to determine which pin is used for IRQn e If this function is called from within a callback function the input detection status will be 0 e Clear the NMI status flags using R_INTC_ControlExtInterrupt RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t irq_status Read the IR flag and pin state for IRQ5 R_INTC_GetExtInterruptStatus PDL_INTC_IRQ5 amp irq_status R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 74 of 487 RX63N Group 4 Library Reference The INTC Read Write and Modify functions use one of the following register definitions IR register definitions
337. ction prototypes include r_pdl_dtc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve 16 bytes for the IRQ2 triggered transfer data area uint32_t dtc_irg_transfer_data 4 Data source and destination declarations const char source_string_1 Renesas RX63N volatile uint8_t destination_string_1 Callback function prototype void IRQ2_ handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Enable control of LED2 R_IO_PORT_Set PDL_IO_PORT_1_0 PDL_IO_PORT_OUTPUT Set the DTC options R_DTC_Set PDL_NO_DATA dtc_vector_table Configure the DTC for IRQ2 R_DTC_Create PDL_DTC_BLOCK PDL_DTC_DESTINATION PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_PLUS PDL_DTC_SIZE_8 PDL_DTC_IRQ_COMPLETE PDL_DTC_TRIGGER_IRQ2 dtc_irq_transfer_data source_string_l destination_string_l 1 uint8_t strlen char source_string_1 Set IRQ2 pin to P32 R20UT1963EE0100 Rev 1 00 Page 405 of 487 Jul 19 2012 RENESAS RX63N
338. ction waits for the CMIB flag to indicate that the one shot time delay is complete If the timer s control registers are directly modified by the user this function may lock up A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timer period limits depend on the peripheral module clock PCLKB fecixe MHZ Equation 50 48 12 5 12 8 1 Tin 20ns 20 83ns 80ns 83 3ns 125ns frcs 9 Tmax_CHANNEL 41 9ms 43 7ms 167 7ms 174 8ms 262ms reixe 22 Tmax_UNIT 10 7s 11 2s 42 9s 44 7s 67 1s Jpc Program example include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Output a pulse and wait for 40ms R_TMR_CreateOneShot PDL_TMR_TMRO PDL_TMR_OUTPUT_HIGH 40E 3 PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 R AS Page 239 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 6 R_TMR Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a TMR timer unit bool R_TMR_Destroy uint8_t data Unit selection Shut down a TMR timer unit data The timer unit n where n 0 or 1 Unit 0 comprises channels TMRO and TMR1 Unit
339. d Set the LOCO clock settings the clock source used after a power on reset ICLK 125 kHz PCLKA 125 kHz PCLKB 125 kHz FCLK 125 kHz BCLK IECLK UCLK not used R_CGC_Set PDL_CGC_CLK_LOCO PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABLE 125E3 125E3 125E3 125E3 125E3 PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT Configure main clock operation using a 12 0 MHz crystal ICLK 3 MHz PCLKA 3 MHz PCLKB 3 MHz FCLK 3 MHz BCLK IECLK UCLK not used R_CGC_Set PDL_CGC_CLK_MAIN L_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABLE E6 6 6 6 6 L_NO_DAT L_NO_DAT L_NO_DAT D D 2 D D D P I 3 3 3 3 P P P Configure PLL operation The PLL will be set to 192 MHz ICLK 96 MHz PCLKA 96 MHz PCLKB 48 MHz FCLK 48 MHz BCLK 48 MHz BCLK pin 24 MHz IECLK UCLK not used R_CGC_Set PDL_CGC_CLK_PLL PDL_CGC_BCLK_DIV_2 PDL_CGC_SDCLK_DISABLE 192E6 96E6 96E6 48E6 48E6 48E6 PDL_NO_DAT PDL_NO_DAI R20UT1963EE0100 Rev 1 00 AS Page 380 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples Allow time for the main clock and PLL oscillator to stabilise This example uses the CMT timer running from the LOCO to generate a 100 ps delay Generate the 100 ps delay R_CMT_CreateOneShot 0 PDL_NO_DATA 100E 6 PDL_NO_FUNC
340. d Call this function before configuring the MTU system 1 or TPU system 2 channels for frequency measurement operation If both MCK systems are disabled the MCK module is put into the low power state If the MTU for system 1 and TPU for system 2 are no longer required then disable these modules using R_MTU2_Destroy or R_TPU_Destroy function calls e If system 1 is disabled the MTCLKD pin signal is available as a clock input to MTU channel 0 If system 2 is disabled the TCLKD pin signal is available as a clock input to TPU channel 0 The first TGRA counter value read from the MTU or TPU modules must be discarded RPDL definitions include r_pdl_mck h RPDL device specific definitions include r_pdl_definitions h void func void Select the LOCO for system 1 and the Main clock for system 2 R_MCK_Control PDL_MCK_1_REFERENCE_LOCO PDL _MCK_2 REFERENCE _MAIN R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 116 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 2 8 Low Power Consumption 1 R_LPC_Create Synopsis Configure the MCU low power conditions Prototype bool R_LPC_Create uint32_t data1 Configuration options uint32_tdata2 Select deep standby interrupt uint32_t data3 Select deep standby interrupt uint32_tdata4 Select deep standby interrupt uint16_t data5 Main oscillator waiting times uint16_t data6 Subclock oscil
341. d use to separate each selection The default settings are shown in bold e Clock phase and polarity Idle clock Data sampling edge PDL_SPIl_CLOCK_MODE_0 or Low Rising PDL_SPI_CLOCK_MODE_1 or Falling PDL_SPI_CLOCK_MODE_2 or High Rising PDL_SPI_CLOCK_MODE 3 Falling Clock division PDL_SPI_DIV_1 or PDL_SPI_DIV_2or PDL_SPI_DIV_4 or PDL_SPI_DIV_8 Use the bit rate specified for R_SPI_Create 1 2 4 or 8 Ignored in Slave mode e SSL assertion PDL_SPI_ASSERT_SSLO or PDL_SPI_ASSERT_SSL1 or PDL_SPI_ASSERT_SSL2 or PDL_SPI_ASSERT_SSL3 The SSL pin to be asserted during the frame transfer Ignored in Slave mode e SSL negation PDL_SPI_SSL_NEGATE or PDL_SPI_SSL_KEEP Negate or retain the SSL signal after the frame transfer Ignored in Slave mode Frame data length PDL_SPI_LENGTH_8 or PDL_SPI_LENGTH_9 or PDL_SPI_LENGTH_10 or PDL_SPI_LENGTH_11 or PDL_SPI_LENGTH_12 or PDL_SPI_LENGTH_13 or PDL_SPI_LENGTH_14 or PDL_SPI_LENGTH_15 or PDL_SPI_LENGTH_16 or PDL_SPI_LENGTH_20 or PDL_SPI_LENGTH_24 or PDL_SPI_LENGTH 32 The number of bits in the frame transfer If a buffer size of 64 bits was selected when R_SPI_Create was called the number of bits must not exceed 16 Data transfer format PDL_SPI_MSB_FIRST or PDL_SPI_LSB_FIRST Select least or most significant bit first R20UT1963EE01
342. d by the RPDL Target MCU Figure 1 1 System configuration with all peripherals supported by RPDL User application Renesas Peripheral Driver Library Peripherals supported by the RPDL Target MCU Figure 1 2 System configuration with middleware taking direct control of some peripherals The library is packaged as a A binary file containing all of the peripheral driver functions b Header files containing the information that the user needs to call any of the functions from their own application code and c Interrupt handlers supplied as source code For best use of this library it is required that the user will have the following documents as a minimum i The hardware schematic diagram ii The MCU hardware manual iii This RPDL API User s manual The binary file is produced using the Renesas RX C tool chain It should be usable by another linker that conforms to the Renesas Application Binary Interface The coding standards and naming conventions are specified by Renesas R20UT1963EE0100 Rev 1 00 R AS Page 1 of 487 Jul 19 2012 SENES RX63N Group 1 Introduction 1 1 Tool chain requirements This RPDL library has been built and tested using the C C Compiler Package for RX Family V 1 02 Release 00 It cannot be used with older versions of the tool chain The latest version of the tool chain can be downloaded from the Renesas Web site Home Products Software and Tools Coding Tools C C Comp
343. d in the lower order byte True CRC R_CRC_Create R_CRC_Write e None RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t CRCresult Read the CRC result and clear it R_CRC_Read PDL_CRC_RETAIN_RESULT amp CRCresult i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 355 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 2 28 12 bit Analog to Digital Converter 1 R_ADC_12 Create Synopsis Configure the 12 bit ADC unit Prototype bool R_ADC_12_Create uint8_t data1 Unit selection uint32_t data2 Channel uint32_t data3 Configuration uint16_t data4 Trigger selection uint32_t data5 Value addition mode options double data6 Sampling time for analog inputs excluding temperature sensor double data7 Sampling time for temperature sensor void func Callback function uint8_t data8 Interrupt priority level Description 1 4 Set the ADC mode and operating condition data1 Select the ADC unit to be configured This must always be 0 data2 Channel selection To set multiple channels at the same time use to separate each value Set PDL_NO_DATA if reading the temperature sensor or an internal reference voltage rather than analog pins e _Input channel selection PDL_ADC_12_CHANNEL_0 PDL_ADC_12_CHANNEL_1
344. d to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2012 4 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For
345. d try to clear the flag R_POE_Control PDL_NO_DATA PDL_POE_FLAG POE8 CLEAR PDL_POE_IRQ_HI_Z 8 DISABLE Figure 5 14 Example of Port Output Enable function R20UT1963EE0100 Rev 1 00 Page 409 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 11 Timer Pulse Unit Figure 5 15 shows an example of Timer Pulse Unit usage Peripheral driver function prototypes include r_pdl_tpu h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void main void uint8_t Flags uintl6_t General_A uintl6_t General_D Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure TPU pins R_TPU_Set 0 PDL_TPU_PIN_AO_PAO PDL_TPU_PIN_BO_P17 i Configure channel 0 for dual waveform A and B output R_TPU_Create 0 0 PDI PU_CLK_PCLK_DIV_1 PDL_TPU_CLEAR_CM_B PDI TPU_A_OC_LOW_CM_INV PDL_TPU_B_OC_HIGH_CM_INV 0 0 200 T 400 1 0 0 L_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC L_NO_FUNC 0 L_NO_FUNC L_NO_FUNC Read the status flags and registers A and D for channel 0 R_TPU_Read 0 amp Flags PDL_NO_PTR amp General_A PDL_NO_PTR PDL_NO_PTR amp General_D Modify channel 0 R_TPU_Control 0 PDL_TPU_COUNTER OxFFDD
346. data to be transferred PDL_DMAC_SIZE_32 Interrupt generation optional PDL_DMAC_IRQ END Transfer completion PDL_DMAC_IRQ_ESCAPE_END Escape end PDL_DMAC_IRQ_REPEAT_SIZE_END 1 repeat size or 1 block data transfer completion PDL_DMAC_IRQ_EXT_SOURCE Extended repeat area overflow on the source PDL DMAC IRQ EXT DESTINATION Extended repeat area overflow on the destination R20UT1963EE0100 Rev 1 00 RENESAS Page 145 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 3 e Start trigger forwarding PDL_DMAC_TRIGGER_CLEAR or PDL_DMAC_TRIGGER_FORWARD When the DMAC transfer is complete clear the DMAC activation trigger or pass it on to the CPU e DTC trigger control PDL_DMAC_DTC_TRIGGER_DISABLE or PDL_DMAC_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when an event specified in the Interrupt generation options occurs data3 Select one activation source for channel DMAn e Trigger selection Name PDL_DMAC_TRIGGER_SW or Trigger cause By software PDL_DMAC_TRIGGER_CMTO or PDL_DMAC_TRIGGER_CMT 1 or PDL_DMAC_TRIGGER_CMT2 or PDL_DMAC_TRIGGER_CMT3 or Compare match on channel CMTn n 0 to 3 PDL_DMAC_TRIGGER_USBO_DOFIFOO or PDL_DMAC_TRIGGER_USBO_D1FIFOO or FIFO interrupt from USBO PDL_DMAC_TRIGGER_
347. data to the backup memory area 4 Reading data from the backup memory area 5 Determining the cause of the exit from the lowest power mode R20UT1963EE0100 Rev 1 00 Page 26 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 11 Register Write Protection Driver The driver functions support the control of the Register Write Protection providing the following operations 1 Enabling or disabling writing to the registers 2 Reading the status of the write protection R20UT1963EE0100 Rev 1 00 Page 27 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 12 Bus Controller Driver The driver functions support the control of the external bus providing the following operations Setting the internal bus operation 2 Configuration of the controller 3 Configuration of the eight address space areas 4 Configuration of the SDRAM address space area 5 Disabling an area that is not required 6 Controlling the bus controller 7 Reading the status of the controller R20UT1963EE0100 Rev 1 00 Page 28 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 13 DMA Controller Driver The driver functions support the control of the Direct Memory Access DMA controller providing the following operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control 2 Disabling DMA channels that are no longer required and enabling low power mode 3 Control of a
348. data7 The number of wait cycles for the first access during a normal or page read sequence CSRWAIT Valid between 0 and 31 data8 The number of wait cycles for the first access during a normal or page write sequence CSWWAIT Valid between 0 and 31 data9 The number of cycles that the CS signal is left asserted after the read strobe is negated CSROFF Valid between 0 and 7 data10 The number of cycles that the CS signal is left asserted after the write strobe is negated CSWOFF Valid between 0 and 7 data11 The number of cycles that the data output is left asserted after the write strobe is negated WDOFF Valid between 0 and 7 data12 The number of wait cycles to be inserted into a multiplexed address output cycle AWAIT Valid between 0 and 3 data13 The number of cycles before the read strobe is asserted RDON Valid between 0 and 7 data14 The number of cycles before the write strobe is asserted WRON Valid between 0 and 7 data15 The number of cycles before the write data is output WDON Valid between 0 and 7 data16 The number of cycles before the chip select is asserted CSON Valid between 0 and 7 True if all parameters are valid and exclusive otherwise false Bus Controller R_BSC_Create Remarks e Use this function to set up each required area and then call R_LBSC_Create e The endian mode of the CPU is selected by the MDE bits in the MDES or MDEB registers e
349. de r_pdl_sci h include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h SCI IIC Channel define CHANNEL _SCI_IIC 2 IIC Slave address of EEPROM define SLAVE _ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM_ADDRESS 0x01 Value to be written to the EEPROM define EEPROM_VALUE OxAA void main void Data Buffer volatile uint8_t IIC_Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set Channel 2 pin options R_SCI_Set 2 PDL_SCI_PIN_SCI2_SSCL2_P12 PDL_SCI_PIN_SCI2_SSDA2_P13 Configure the SCI IIC Channel R_SCI_Create CHANNEL _SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 1 0 Set up data buffer for the write Address in EEPROM ITIC_Buffer 0 EPROM_ADDRESS Data to write TIC_Buffer 1 EEPROM_VALUE IIC write R_SCI_IIC_Write CHANNEL_SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 2 IIC_Buffer PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 Page 439 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage
350. destination_string_2 void main void uint8_t StatusValue uint32_t SourceAddr uint32_t DestAddr uint16_t TransferCount uintl6_t SizeCount Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_ IPL 0 Enable control of LED2 R_IO_PORT_Set PDL_IO_PORT_1_0 PDL_IO_PORT_OUTPUT Configure channel 0 R_DMAC_Create 0 PDL_DMAC_BLOCK PDL_DMAC_SOURC ESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PL PDL_DMAC_SIZE_8 PDL_DMAC_IRQ_ PDL_DMAC_TRIGGER_IRQ2 source_string_l destination_string_l 1 uintl6_t strlen source_string_l PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA DMACO_transfer_end_handler 7 Configure channel 1 R_DMAC_Create R20UT1963EE0100 Rev 1 00 Page 402 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 1 PDL_DMAC_BLOCK PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_SIZ PDL_DMAC_TRIGGER_SW source_string_2 destination_string_2 1 uintl6_t strlen source_string_2 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC i ee Set IRQ2 pin to P32 R_INTC_SetExtInterrupt PDL_INTC_IRQ2_P32 PDL_NO_DATA Enable the SW1 IRQ2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_FALLING PDL_INTC_DMAC_TRIGGER_ENABLE PDL_NO_FUNC
351. ducts 1 Table of Contents Introduction ense teehee dee a a etter Tan aad acetal ee ween c tea ed asda taeda na ain teed ed dante 1 4 4 Tool chain requirement 2502 st0t2 cendedidaiede dened a iaei aia e need aae aa ada aate aaah aaa t eda 2 1 2 Using the library within your project cccceeeeeeeeece cece eeeeeeeeaeeeeeeeeeseseaaaeaeeeeeeesesencaeaeeeeeeesessenaeaeeeeeess 2 Leds Mia the PPG graphical UMY oire A gece vnc E ieee detenisd nb take RE 2 1 2 2 Added to a project by the user and used stand alone eeeccceeeeeneeeeeeneeeeeeeneeeteenaeeeeeenaeeeeeeaaes 2 1 Unzipthe REDE tiles cfc vecs oso 8 eee Se ete eid aot ere Ag dens eit de aka eon case aN 2 2 Copy the files into your project area oe eeeeeeeeeeeee ee eeeneeeeeeeeaeeeeeeaaeeeseeaaeeeseenaeeeeeeaeeeeeenaeeeeeeaes 2 3 Include the New directory osceann ri e a a E A A R a 5 4 Add the RPDL library fe e a a a a p a aaa a aa aea T e aaa a a aeaea aaen Tn 6 5 Include the New source MES curea eriin eana A E AEEA I RA EA 7 6 Peripherals that are not required ccccccecceecececeeeeeceneaeeeeeeeeeseaaaeaeceeeeeseceeaeeeeeeeeeseesecaeeeeeeeeeeeees 8 7 Peripherals that are not supported by RPDL 0 ececcccecceceeeeeeeeeeeeeeeeeeeteseeeaeceeeeeeeseceiaeeeeeeeeeeeees 8 8 Avoid conflicts with standard project files oo cece eeeeeeeeeeeeeeeeeteeeeeeeseeeeeeeseeeaeeeseeeaeeeseeeaeerseeaeees 9 9 Set the build OptiONS i 2 a0 ceeds a
352. e Was the slave status received if iebus_rx_data_length 1 Is the slave able to accept data if iebus_slave_status amp BIT_1 0x0u R20UT1963EE0100 Rev 1 00 Page 471 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Send data to the slave if R_LIEB_MasterSend 0 PDL_IEB_DATA 0x0345 iebus_tx_data_a 5 PDL_NO_FUNC true Read the status of channel 0 R_IEB_GetStatus 0 amp General_flags amp Tx_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR 3 Handle the error here Is the slave ready to send data if iebus_slave_status amp BIT_0O 0x0u Clear the data storage area for counter 0 counter lt 32 counter t iebus_rx_data counter 0x00 Read data from slave 345h if R_LIEB_MasterReceive 0 PDL_IEB_DATA 0x0345 iebus_rx_data amp iebus_rx_data_length PDL_NO_FUNC true Read the status of channel 0 R_IEB_Get Status 0 amp General_flags PDL_NO_PTR amp Rx_status PDL_NO_PTR PDL_NO_PTR Handle the error here if strcmp const char iebus_rx_data First slave message 0 R_IO_PORT_Modi fy LEDO PDL_IO_PORT_XOR if strcmp const char iebus_rx_data Second slave message 0 R_IO_PORT_Modify R20UT1963EE0100 Rev 1 00 Page 472 of 487 Jul 19 2012 RENESAS
353. e e Polynomial selection PDL_CRC_ POLY CRC 8or X54 X74 X41 PDL_CRC POLY CRC 16 or xX 4 x 4 x2 4 PDL CRC POLY CRC CCITT xX x x 1 Bit order PDL_CRC_LSB_FIRST or PDL_CRC_MSB _ FIRST Select LSB or MSB first operation True if all parameters are valid and exclusive otherwise false CRC None e None RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Set up the CRC in 8 bit mode with LSB first R_CRC_Create PDL_CRC_POLY_CRC_8 PDL_CRC_LSB_FIRST i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 352 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_CRC_Destroy Synopsis Prototype Description Shut down the CRC calculator bool R_CRC_Desitroy void No parameter is required Put the CRC calculator into the Power down state with minimal power consumption Program example Return value True Category CRC Reference R_CRC_Create Remarks e None RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the CRC R_CRC_Destroy R20UT1963EE0100 Rev 1 00 2tENESAS Jul 19 2012 Page 353 of 487 RX63N Group 4 Library Reference 3 R_CRC Write Synopsis Write data in
354. e CHANNEL_SCI_IIC PDL_SCI_IIC_NOSTOP SLAVE_ADDRESS 1 IIc_Buffer PDL_NO_FUNC Set flag data_received false Read data from current EEPROM address using DTC Start with an IIC Re start DTC on Rx R_DTC_Create PDL_DTC_NORMAL PDL _DTC_DESTINATION_ADDRESS_PLUS PDL_DTC_SOURCE_ADDRESS_FIXED PDL_DTC_SIZE_8 PDL _DTC_IRQ COMPLETE PDL_DTC_TRIGGER_RXI2 dtc_iicl_rx_transfer_data uint8_t amp SCI2 RDR Source IIC_Buffer Destination Data length is one less than we want to read as use R_SCI_IIC_ReadLastByte 4 PDL_NO_DATA DTC on Tx To write the dummy data out Data length is 2 less than we want to read as first dummy byte is written out by R_SCI_IIC_Read function and last one when we use R_SCI_IIC_ReadLastByte R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_ FIXED PDL_DTC_DESTINATION_ADDRESS_FIXED PDL_DTC_SIZE_8 PDL _DTC_IRQ_ COMPLETE PDL _DTC_TRIGGER_TXI2 dtc_iicl_tx_transfer_data amp IIC_Dummy_value Source uint8_t amp SCI2 TDR Destination 3 Data length PDL_NO_DATA Enable the DTC R_DTC_Control PDL _DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Start the IIC Read R_SCI_IIC_Read CHANNEL_SCI_IIC PDL_SCI_IIC_RES
355. e r_pdl_sci h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h static void SCItx void volatile bool data_sent false void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set Channel 6 pin options R_SCI_Set 6 PDL_SCI_PIN_SCI6_SMISO6_P01 PDL_SCI_PIN_SCI6_SMOST6_P00 PDL_SCI_PIN_SCI6_SCK6_P02 PDL_SCI_PIN_SCI6_SS6_PB2 Create SPI master R_SCI_Create 6 PDL_SCI_SYNC PDL_SCI_SPI_MODE PDL_SCI_RX_ DISCONNECTED PDL_SCI_CLK_INT_OUT 19200 1 0 Start sending data R_SCI_SPI_Transfer 6 PDL_NO_DATA 5 12345 SCIC PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC i Wait for data to be sent while data_sent false Close this channel R_SCI_Destroy 6 R20UT1963EE0100 Rev 1 00 Page 437 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples static void SCItx void data_sent true Figure 5 34 Example of SCI in SPI mode R20UT1963EE0100 Rev 1 00 az AS Page 438 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 17 9 SCI in IIC Mode This shows the setting of SCI channel 2 in to IIC mode and then a write and read to an IIC EEPROM PDL functions inclu
356. e Sensor True if success otherwise false TS R_TS_Create e R_TS_Create must be called and wait for at least 30 us before calling this function RPDL definitions include r_pdl_ts h RPDL device specific definitions include r_pdl_definitions h void func void Enable the Temperature Sensor R_TS_Control PDL_TS_OUTPUT_ENABLE R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 378 of 487 Jul 19 2012 RX63N Group 5 Usage Examples 5 Usage Examples This chapter shows programming examples for each driver in this library R20UT1963EE0100 Rev 1 00 AS Page 379 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 1 Clock Generation Circuit Figure 5 2 shows an example of configuring the clock generation circuit After a power on reset both the PLL and the main clock oscillator which drives the PLL circuit are switched off The MCU is using the LOCO as the clock source The calls to R_CGC_Set configure the LOCO dividers and enable the main clock oscillator and the PLL circuit After an appropriate time to allow for the crystal based main clock oscillator and the PLL circuit to stabilise a call to R_CGC_Control is used to select the PLL circuit as the clock source Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void main voi
357. e daai aaa aea aaa eaaa aeaeaie aaa aat 11 10 Build the projette i ae e ae ein adder el Eea 13 1 2 3 Header file inClUSiON ccccceeeeeeeeeceaeceeeeeeeceeeaeaeceeeeeeseaaaeaeceeeeeseccsaeaeeeeeeesesensanaeeeeeeeeeeaaeees 14 1 2 4 Header file order ticccccncteets edition nied ond aaea sla iad e aaea geste dee aad 14 1 2 5 Recommended initialisation code cccccececeeeeceeceeeeeeeeeceneaeeeeeeeeesenaeaeceeeeesesencueaeeeeeeeseteenaees 14 1 Initialisation of pins that are not available ccececeececceeeeeeeeceeeeeeeeeeeeeeecaeeeeeeeeesetentuseeeeeeetees 14 2 Initialisation of the sub clock oscillator if not USEC eec cee eeeeeeeeeeneeeeeeneeeeeeaeeeeeeaeeeeeeaeeeeteaas 14 1 3 Document Structure ss eai a alien adal ae a adi dd ra edad dda 15 1 4 Listof Abbreviations and ACrONYMS S sses isser ennie kui deteni enAE AAKE ee ARETE ENE EEA KEREN R EERE TARE AEEA RETER ENEEK EREKE 16 BINE AET EE E A E E O E E E T O EEE A TE E ETEN 17 2 1 ONCIVIGW a e dee E hee ce ie eek ae a AE ena eee ee 17 2 2 ControlsFunctions SUMMARY si dics n A ih coved sea T tives tein aged A Gives daa ooh aves eae 17 2 3 Clock Generation Circuit Driver c cccccceececeecee cece ee eeeeceecae cece ee eeseaaaeaeeeeeeesescaaeaeeeeeeesetsecieeeeeeeeneees 19 24 1 Interrupt Control Driver veces eezdeas nates caceces e a ade 20 2 5 VO Port Driw hiiicisei Beit eed ite ed teins Bees ed ie eel ie heel eed ee 21 2 6
358. e n 0 to 12 data2 The address of the buffer that will receive the byte True SCI R_SCI_IIC_Read e Device packages with 100 pins do not have all of the SCI channels PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 9 Buffer for IIC data extern uint8_t IIC_Buffer 10 void func void Read the last byte of the IIC read operation R_SCI_IIC_ReadLastByte CHANNEL _SCI_IIC amp IlIC_Buffer 9 i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 303 of 487 Jul 19 2012 RX63N Group 4 Library Reference 10 R_SCI_Conirol Synopsis Prototype Description Control the SCI channel bool R_SCI_Control uint8_t data1 Channel selection uint16_t data2 Channel control Control the SCI channel data1 Select channel SCIn where n 0 to 12 data2 Not IIC Mode Control the channel If multiple selections are required use to separate each selection e Select the process to be stopped Stop the transmission process PDL_SCI_STOP_TX If a reception process is active the transmit output will not become idle until the reception process has stopped Stop the reception process If a transmission process is active the receive error flags may be set erroneously These can be ignored and will be cleared when
359. e transfer rate as an input 3 Disabling channels that are no longer required and enabling low power mode 4 Sending data as a bus master 5 Receiving data as a bus master 6 Monitor the bus and receiving data as a bus slave 7 Sending data as a bus slave 8 Control of special modes 9 Reading the status of the module Note The Clock Generation Circuit must be configured before configuring any IEBus channel R20UT1963EE0100 Rev 1 00 AS Page 44 of 487 Jul 19 2012 RENES RX63N Group 2 Driver 2 29 CRC Calculator Driver The driver functions support the CRC calculator providing the following operations 1 Configuration for use including e Polynomial selection e Bit order selection e Preparation for a new calculation 2 Disabling the calculator and enabling low power mode 3 Writing data to be used for the calculation 4 Reading the calculation result R20UT1963EE0100 Rev 1 00 Page 45 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 30 12 bit Analog to Digital Converter Driver The driver functions support the use of the 12 bit ADC unit providing the following operations 1 Configuration for use including e Automatic clock setting using sampling time as an input e Automatic interrupt control e Sampling time control 2 Disabling the unit when no longer required and enabling low power mode 3 Control the ADC unit including e CPU sleep option 4 Reading the conversion results with support
360. eceived or another event P occurs Parameter data4 in R_IEB_Create must not be 0 Return value True if all parameters are valid exclusive and achievable otherwise false Category IEBus Reference R_IEB_Create R_IEB_GetStatus Remarks e Ifa callback function is specified interrupts are used The callback function may be called more than once during a transfer Please see the notes on callback function usage in 6 e Use 9 to identify the activity that has occurred In polling mode this function will use the status flags to monitor the IEBus activity If the IEBus channel s registers are modified directly by the user this function may lock up RPDL definitions include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t iebus_data 32 uint8_t iebus_data_length Monitor channel 0 using polling R_IEB_SlaveMonitor 0 iebus_data amp iebus_data_length PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 346 of 487 Jul 19 2012 RX63N Group 4 Library Reference 7 R_IEB_SlaveWrite Synopsis Prototype Description Return value Category Reference Prepare data for sending to a master unit bool R_IEB_SlaveWrite uint8_t data1 Channel selection uint8_t data2 Data storage start address uint8_t data3 II Data length Store data for transmission when requested b
361. ect the device package and endian option 177 pins litle endian 177 pins big endian 176 pins litle endian 176 pins big endian 145 pins litle endian 145 pins big endian 144 pins little endian 144 pins big endian 166 pins litle endian 166 pins big endian 1 2 3 4 5 6 8 9 6 Select the device package option by pressing a number and then press Enter BE Renesas RPDL for RX63N copy utility Please enter a number to select the device package and endian option 177 pins litle endian 177 pins big endian 176 pins litle endian 176 pins big endian 145 pins litle endian 145 pins big endian 144 pins little endian 144 pins big endian 166 pins litle endian 166 pins big endian 1 2 3 4 5 6 8 9 8 i 3 Please enter the path where you wish RPDL for RkK63N to be installed Type the full path to the folder where you wish RPDL to be copied to and then press Enter The utility will create a folder in the location that you specified and copy the files into the new folder R20UT1963EE0100 Rev 1 00 Page 3 of 487 Jul 19 2012 RX63N Group 1 Introduction c C WINDOWS system32 cmd exe Renesas RPDL for RX63N copy utility Please enter a number to select the device package and endian option 177 pins litle endian 177 pins big endian 176 pins litle endian 176 pins big endian 145 pins litle endian 145 pins big endian 144 pins little endian 144 pins big endian 166 pins litle
362. ect the pins for TMO2 Select the pins for TMRI2 e Valid when n 3 PDL_TMR_TMR3_TMO3_P13 or PDL_TMR_TMR3_TMO3_P32 or Select the pins for TMO3 PDL_TMR_TMR3_TMO3_P55 PDL_TMR_TMR3_TMCI3_P11 or PDL_TMR_TMR3_TMCI3_P27 or PDL_TMR_TMR3_TMCI3_P34 or PDL_TMR_TMR3_TMCI3_PA6 PDL_TMR_TMR3_TMRI3_P10 or PDL_TMR_TMR3_TMRI3_P30 or Select the pins for TMRI3 PDL_TMR_TMR3_TMRI3_P33 Select the pins for TMCI3 True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateChannel R_ TMR_CreateUnit R20UT1963EE0100 Rev 1 00 EN ESAS Page 227 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks Program example Before calling any R_TMR_Create function call this function to configure the relevant pins e Call this function multiple times if more than one channel is to be configured e Pins which are not used for the TMR functions may be omitted include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure the applicable TMR pins R_TMR_Set 0 PDL_TMR_TMRO_TMOO_PB3 PDL_TMR_TMRO_TMCIO_PB1 PDL_TMR_TMRO_TMRIO_PA4 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 228 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_TMR_CreateChannel Syn
363. ed If pin P32 is specified for both RTCOUT and RTCIC2 at the same time this function will return false Select PDL_NO_DATA if no pins are required To set multiple options at the same time use to separate each value e RTCOUT Pin PDL_RTC_PIN_RTCOUT_P16 or PDL_RTC_PIN_RTCOUT_P32 to use for it If using the RTCOUT pin then select the port e Capture Pins PDL_RTC_PIN_RTCICO P30 PDL_RTC PIN RTCIC1 P31 PDL_RTC PIN RTCIC2 P32 Specify any capture pins which will be used data3 The current day of the week DOW and time in hours minutes and seconds BCD format is used The format is dependent upon if using 12 hour or 24 hour mode 24 Hour Mode b31 b24 b23 b16 b15 b8 b7 b0 Day of week Hours Minutes Seconds Valid from 0 to 6 0 Sunday Specify OxFF for Valid from O Valid from O Valid from automatic calculation using the values in data3 to 23 to 59 0 to 59 12 Hour Mode b31 b24 b23 b22 b16 b15 b8 b7 bO Day of week Wildtiom 0 0 amp O Sunday PM monre Mines seconds Specify OxFF for automatic 0 z AM Valid from Valid from Valid from A 1 PM 1 to 12 0 to 59 0 to 59 calculation using the values in data3 data4 The current year month and day BCD format is used If not required specify PDL_NO_DATA b31 b16 b15 b8 b7 b0 Year Month Day Valid from 0 to 9999 Valid from 1 to 12
364. ed use to separate each selection e Counter stop re start PDL_TMR_STOP or PDL TMR_START Disable or re enable the counter clock source e The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB data3 The 16 bit counter value This will be ignored if the register is not selected data4 The 16 bit compare match A value This will be ignored if the register is not selected data5 The 16 bit compare match B value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateUnit Remarks e For unit 0 the upper byte is the value for TMRO and the lower byte is the value for TMR1 For unit 1 the upper byte is the value for TMR2 and the lower byte is the value for TMR3 R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 243 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Load the unit 1 counter and constants R_TMR_Controlunit 1 PDL_TMR_COUNTER PDL_TMR_TIME CONSTANT_A PDL_TMR_TIME_CONSTA
365. ee a cc Seacae ened a a eaa a a eae 162 Data Transfer Controler scii eaaa re aaa aaa a a a aa 164 PADAO EE EET EAE E arg O AE T E AA NE 164 R DTC Create a nthe nave Seven A aa a ieee aera ee ee aiaa aaaea adaa ea at ed 165 R DTC D6Stroy 22 22 criti e aa aaaea nae Met aaa aa aaa ode ee ad ied eens ae 169 R DTC Controlinctieceasiien a aaea a aa aa a ATA eels eens ue ee ate 170 R DTC GetStatus ii ea aa aaa aa aa aaa aa aa aa Aa a aaia daa eee ae dee eee 172 Multi Function Timer Pulse Unit c ccccccceeeeeenceceeeeeeeeeeeeaeceeeeeeeseceeaeeeeeeeeeseceaeaeeeeeeeeeseenaees 174 RiMTW2 S etnias eden aa aeaa a esi eel ied ee dei eee ise ee aa TAa 174 RiMTU2 Create ves acdsee ee ataare aa a aa aa a eect eve a Aa aa eens anda ct eve 177 RoMTU2 Destroy airn eie a aa noe ee ied ee eee nai ise deta ee 187 R_MTU2_ControlChannel ccccecccceceeeeecenceeeeeeeecetenaaeaeeeeeeececaaaeceeeeeeesecceaaeeeeeeeeesenseceeeeees 188 RoMTU2 ControlU nit ten cede age i ed diene A esd ee Sedna ae Me ee ee 191 R MTU2_ ReadChannel iniaeeaa apaan ee doevd divine la cessed deine aade eaaa ae Meesadelaetaeess 196 R MT U2 Read nit soften ieee ected set cacao eee deat set hoe oes he ent vee a aden ae 199 A D OMDNDAORWNHANwWNANORWDY wero as a a NS Sa Se eS Ewer Ser Ss Lha aa Sw go 2 3 4 5 6 7 8 9 1 0 11 4 2 24 1 Port Output Enable nnana a a de ne ee ne 200 R POEs Setrit ani ep i eee anette ie ae aioe eal te A aad need
366. eel ide adeaeld ieee 33 2 18 Timer Pulse Unit Driver serine nde ten nee dead el aden eae hele adden aden ave iaer eee 34 2 19 Programmable Pulse Generator Driver cccceeceeeeeeeeneeeeeeeneeeeeeaeeeeeeaaeeeeesaeeeeeeaeeeeeeaeeeeeenaeeeeeeaas 35 220 B DIt Timer DIVO tis on a oha hs bg chr aaa hee a e ba etc aaah eae ee da ied aaa ede aaa ee 36 2 21 Compare Match Timer Driver c ccccceceeeeeeeeeececeeeeeeeceaeaececeeeeeeeaaeaeceeeeesaeecaaeeeeeeeeeseeennieeeeeeeeetees 37 2 22 Real time Clock Driver ccccccceccecccceceeeeeeeeecaececeee cece aanaeceeeeeceseaaaeeeceeeeesaeceaeeeeeeeeeseeennieeeeeseneeees 38 2 23 Watchdog Timer Drivers s isisanen eared ete esd ett chai iene ate 39 2 24 Independent Watchdog Timer Drivel ccccceeeeeteeeeeeeeeeeeeeeneeeeeeaeeeeeeaeeeeeeaeeeeeeaeeeesenaeeeeesnaeeeeeeaas 40 2 25 Serial Communication Interface Driver ccccccccceceeeeeeeeceeceeeeeeeeecaeeeeeeeeesesecceaeeeeeeesesecnieeeeeeeereee 41 220 PO Bus Interface D Ve e a a eed a Bead peecen ea eatin seed aa aa sedans 42 2 27 Serial Peripheral Interface Driver ccccccceeceececeeeeeeeceeeaeeeeeeeeesecaeaeeeeeeeseeecaeaeeeeeeeseseecieeeeeeeeree 43 2 28 IEBUS Intermace Driver es eea a tes aa eaa aada fed cosabadatects camecehvadad aed led a naa aeaa a EAG 44 2 29 CRC Calculator OVET e a E a aaa aa a E e a aea ET 45 2 30 12 bit Analog to Digital Converter Driver sessseesssresesrresssrr
367. eep software standby mode PDL_LPC_CANCEL_IRQ13_FALLING or PDL_LPC_CANCEL_IRQ13_ RISING PDL_LPC_CANCEL_IRQ13_DISABLE or Prevent or allow an edge on the IRQ13 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ14_FALLING or PDL_LPC_CANCEL_IRQ14_RISING PDL_LPC_CANCEL_IRQ14_ DISABLE or Prevent or allow an edge on the IRQ14 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ15_ FALLING or PDL_LPC_CANCEL_IRQ15_ RISING PDL_LPC_CANCEL_IRQ15_DISABLE or Prevent or allow an edge on the IRQ15 DS pin to cancel deep software standby mode R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 118 of 487 RX63N Group 4 Library Reference Description 3 4 data4 Select the interrupt to cancel deep software standby mode The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Deep software standby cancel control PDL_LPC_CANCEL_LVD1_DISABLE or PDL_LPC_CANCEL_LVD1_FALLING or PDL_LPC_CANCEL_LVD1_RISING Prevent or allow an edge on the LVD1 pin to cancel deep software standby mode PDL_LPC_CANCEL_LVD2_DISABLE or PDL_LPC_CANCEL_LVD2_FALLING or PDL_LPC_CANCEL_LVD2_RISING Prevent or allow an edge on the LVD2 pin to cancel deep software standby mode PDL_LPC_CANCEL_RTCI_DISABLE or PDL_LPC_CANCEL_RTCI_ENABLE Prevent or allow the RTC interval interrupt signal to cancel deep software standby mode PDL_LPC_CA
368. efer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set pin options R_SCI_Set 0 PDL_SCI_PIN_SCIO_TXDO_P20 PDL_SCI_PIN_SCIO_SCKO_P22 R_SCI_Set 2 PDL_SCI_PIN_SCI2_RXD2_P52 PDL_SCI_PIN_SCI2_SCK2_P51 Create Master Channel R_SCI_Create MASTER_CHANNEL PDL_SCI_SYNC PDL_SCI_RX_DISCONN PDL_SCI_CLK_INT_OUT 19200 1 0 Create Channel slave NOTE Even though using an external clock the driver needs to know the expected baud rate Bit 31 is set to signify not generating baud R_SCI_Create SLAVE_CHANNEL PDL_SCI_SYNC PDL_SCI_TX_DISCONN PDL_SCI_CLK_EXT R20UT1963EE0100 Rev 1 00 Page 429 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 0x80000000 19200 1 0 Set flag to wait on data_received false Setup a read on channel slave R_SCI_Receive SLAVE_CHANNEL PDL_NO_DATA rx_buffer 5 SCI9RxFunc PDL_NO_FUNC Send the data from the master R_SCI_Send MASTER_CHANNEL PDL_NO_DATA 12345 5 PDL_NO_FUNC Wait for channel slave to receive while data_received false Process the received data here SCI channel 9 receive complete handler static void SCI9RxFunc void
369. efinition values from 4 2 4 data2 e The logical operation to be applied to the register contents PDL_MPC_AND or PDL_MPC_OR or Select between AND amp OR or Exclusive OR PDL_MPC_XOR data3 The value to be used for the modification Return value True if a valid MPC register is specified otherwise false Category MPC registers References None Remarks The MPC registers are modified by other driver functions Take care to not overwrite existing ee the hardware manual for valid values for each register Program example RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void Set bit 7 in PFBCRO to 1 R_MPC_Modify PDL_MPC_REG_PFBCRO PDL_MPC_OR 0x80 R20UT1963EE0100 Rev 1 00 R AS Page 105 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 4 2 5 MCU operation 1 R_MCU_Control Synopsis Control the operation of the MCU Prototype bool R_MCU_Control uint8_tdata Control options Description Modify the MCU control registers data Select the operation states All selections are optional If multiple selections are required use to separate each selection e On chip ROM control PDL_MCU_ROM_ENABLE or PDL_MCU_ROM_DISABLE Enable or disable the on chip ROM e On chip RAM control PDL_MCU_
370. efinitions include r_pdl_definitions h void func void uint8_t data_to_restore R_PDL_LPC_BACKUP_AREA SIZE Read data from the backup registers R_LPC_ReadBackup data_to_restore R_PDL_LPC_BACKUP_AREA_SIZE R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 125 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_LPC_GetStatus Synopsis Prototype Description Read the status flags bool R_LPC_GetStatus uint32_t data1 II Data pointer uint8_t data2 Data pointer Read the Low power status flags data1 The status flags shall be stored in the format below b31 b26 b25 b24 Deep Software Standby Operating Power Control Mode transition flag 0 cancel request detection 0 No activity 0 Transition completed 1 CAN RXD 1 During Transition b23 b22 b20 b19 b18 b17 b16 Event detection flags 0 not detected 1 detected An interrupt has caused an exit Poweron from deep software standby mode 0 LVD2 LVD1 LVDO reset followed by an internal reset b15 b14 b13 b12 b11 b10 b9 b8 Deep Software Standby cancel request detection 0 No activity 1 The exit from deep software standby was caused by one of the following signals USB IIC SCL Ne NMI RTC RIC LVD2 LVD1 SDA alarm interval b7 b6 b5 b4 b3 b2 b1 bO Deep Softw
371. en 0x0001 and OxOFFF Setting of 0x0000 is prohibited data3 The value to be set to REFW bits in SDRAM Refresh Control Register SDRFCR Valid between 0x00 and OxOF data4 The value to be set to ARFI bits in SDRAM Initialization Register SDIR Valid between 0x00 and OxOF data5 The value to be set to ARFC bits in SDRAM Initialization Register SDIR Valid between 0x01 and Ox0F Setting of 0x00 is prohibited data6 The value to be set to PRC bits in SDRAM Initialization Register SDIR Valid between 0x00 and 0x07 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 140 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks data7 The value to be set to CL bits in SDRAM Timing Register SDTR Valid between 0x01 and 0x03 Setting of 0x00 or more than 0x03 is prohibited data8 The value to be set to WR bit in SDRAM Timing Register SDTR Valid between 0x00 and 0x01 data9 The value to be set to RP bits in SDRAM Timing Register SDTR Valid between 0x00 and 0x07 data10 The value to be set to RCD bits in SDRAM Timing Register SDTR Valid between 0x00 and 0x03 data11 The value to be set to RAS bits in SDRAM Timing Register SDTR Valid between 0x00 and 0x06 data12 The value to be written to the SDRAM mode register Only the lower 15 bits are valid Please refer to hardware manual for rest
372. er TRGnBN requests during up count operation R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 179 of 487 RX63N Group 4 Library Reference Description 4 9 buffer_operation Configure the buffer operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Control the cycle set buffer transfer timing Valid for n 4 PDL_MTU2_CSB_DISABLE or Select no transfer PDL_MTU2_CSB_CREST or transfer on crest detection PDL_MTU2_CSB_TROUGH or transfer on trough detection or PDL_MTU2_CSB_ BOTH transfer on crest and trough detection PDL_MTU2_CSB_TROUGH and PDL_MTU2_CSB_BOTH are available only in complementary PWM mode Buffer operation PDL_MTU2_BUFFER_AC_DISABLE or PDL_MTU2_BUFFER AC ENABLE Disable or enable buffer operation for registers TGRA and TGRC Valid for n 0 to 4 PDL_MTU2_BUFFER_BD_DISABLE or PDL_MTU2 BUFFER BD ENABLE PDL_MTU2_BUFFER_EF_DISABLE or PDL_MTU2 BUFFER EF ENABLE Disable or enable buffer operation for registers TGRB and TGRD Valid for n 0 to 4 Disable or enable buffer operation for registers TGRE and TGRF Valid for n 0 Buffer data transfer PDL_MTU2_BUFFER_AC_CM Aor PDL_MTU2_BUFFER_AC_TCNT_CLR Transfer the data from TGRC to TGRA when a compare match A occurs or when TCNT is cleared in each channel Valid
373. er was out of range or if the channel was already transmitting or if an error occurred during transmission Category SCI Reference R_SCl_Control R_SCl_GetStatus R20UT1963EE0100 Rev 1 00 EN ESAS Page 290 of 487 Jul 19 2012 RX63N Group 4 Library Reference Remarks e The compiler adds a null character to the end of string constants e Ifa callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 e If polling mode is used the TXI and TEND flags will be used to manage the data transmission If the SCI channel s control registers are directly modified by the user this function may lock up The maximum number of characters to be transmitted is 65535 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e If reception is enabled and receive errors occur transmission will be blocked until the errors are cleared e In Multi processor mode R_SCI_Send is to be called in pair the first one is to send ID ID cycle the second one is to send data Data cycle For ID transmission it will be sent by internal polling operation For Data transmission it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to section 5 17 7 e For ID cycle the DMAC DTC trigger control and the callback function will
374. erence 4 2 14 Multi Function Timer Pulse Unit 1 R_MTU2 Set Synopsis Configure the Multi function Timer Pulse Unit Prototype bool R_MTU2_Set uint8_t data1 Channel selection uint32_t data2 Configuration for a channel uint16_tdata3 Configuration for MTCLK pins Description 1 2 Set up the global MTU options data1 The channel number n where n 0 to 5 data2 Pin configuration for the channel Use to separate each selection e Valid when n 0 PDL_MTU2_PIN_0A_P34 or PDL_MTU2 PIN OA PB3 PDL_MTU2_PIN_0OB_P13 or PDL_MTU2_PIN_0B P15 or Select the P13 P15 or PA1 pin for MTIOCOB PDL_MTU2 PIN OB PA PDL_MTU2_PIN_OC_P32 or PDL_MTU2_PIN OC _PB1 PDL_MTU2_PIN_OD_P33 or PDL_MTU2_ PIN OD_PA3 Select the P34 or PB3 pin for MTIOCOA Select the P32 or PB1 pin for MTIOCOC Select the P33 or PA3 pin for MTIOCOD e Valid when n 1 PDL_MTU2_PIN_1A_P20 or PDL _MTU2 PIN 1A PE4 PDL_MTU2_PIN_1B_ P21 or PDL MTU2 PIN 1B PB5 Select the P20 or PE4 pin for MTIOC1A Select the P21 or PB5 pin for MTIOC1B e Valid when n 2 PDL_MTU2_PIN_2A P26 or PDL _MTU2 PIN 2A PB5 PDL_MTU2_PIN_2B_ P27 or PDL _MTU2 PIN 2B PE5 Select the P26 or PB5 pin for MTIOC2A Select the P27 or PE5 pin for MTIOC2B e Valid when n 3 PDL_MTU2_PIN_3A_P14 or PDL_MTU2_PIN_3A_P17 or PDL_MTU2_PIN_3A_PC1 or PDL _MTU
375. errupt control Interrupt control 7 R_INTC_GetExtInterruptStatus Read the external interrupt status unit 8 R_INTC_Read Read an interrupt register 9 R_INTC_Write Update an interrupt register 10 R_INTC_Modify Modify an interrupt register 11 R_INTC_CreateGroup Configure an interrupt source group 12 R_INTC_ControlGroup Control an interrupt source group 13 R_INTC_GetStatusGroup Read the status of an interrupt source group 14 R_INTC_Control Control the operation of the interrupt controller 1 R_IO_PORT_Set Configure an I O port 2 R_lO_PORT_ReadControl Read an O port s control registers 3 R_IO_PORT_ModifyControl Modify an I O port s control registers 4 R_IO_PORT_Read Read data from an I O port I O port 5 R_lIO PORT Write Write data to an I O port 6 R_lIO_PORT_Compare Check the pin states on an I O port 7 R_IO_PORT_Modify Modify the pin states on an I O port 8 R_IO_PORT Wait Wait for a match on an I O port 9 R_IO_PORT_NotAvailable Configure I O port pins that are not available Multifunction Pin 1 R_MPC_Read Read a PFC register Controller 2 R_MPC_Write Write to a PFC register 3 R_MPC_Modify Modify a PFC register 1 R_MCU_Control Control the operation of the MCU MCU operation 2 R_MCU_GetStatus Read the MCU status 3 R_MCU_OFS Configure the device start up operation 1 R_LVD_Create Configure the voltage detection circuit Sec fae 2 R_LVD_Control Control the voltage detection circuit etection Circuit 3 R_LVD_GetStatus Check the status
376. errupt priority level Set the ADC s mode and operating condition data1 Select the ADC unit 0 only to be configured data2 I ADC conversion clock frequency ADC input sampling time Conversion options To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Scan mode PDL_ADC_10_MODE_SINGLE or PDL_ADC_10_MODE_ONE_CYCLE_SCAN PDL_ADC_10_MODE_CONTINUOUS_SCAN or Select Single mode Continuous scan mode or One cycle scan mode Input channel selection PDL_ADC_10 CHANNELS _OPTION_1 or Any mode For unit 0 channel ANO PDL_ADC_10_CHANNELS_OPTION_2 or Single mode For unit 0 channel AN1 Scan mode For unit 0 channels ANO and AN1 PDL_ADC_10_ CHANNELS OPTION 3 or PDL_ADC_10_CHANNELS_OPTION_4 or Single mode For unit 0 channel AN2 Scan mode For unit 0 channels ANO AN1 and AN2 Single mode For unit 0 channel AN3 Scan mode For unit 0 channels ANO AN1 AN2 and AN3 PDL_ADC_10_CHANNELS_OPTION_5 or Single mode For unit 0 channel AN4 Scan mode For unit 0 channels ANO AN1 AN2 AN3 and AN4 PDL_ADC_10_CHANNELS_OPTION_6 or Single mode For unit 0 channel AN5 Scan mode For unit 0 channels ANO AN1 AN2 AN3 AN4 and AN5 PDL_ADC_10_CHANNELS_OPTION_7 or Single mode For unit 0 channel AN6 Scan mode F
377. esrtnneesinnestnunetnanesttanantnnndsnnnaestnaneentanaennnne 46 2 31 10 bit Analog to Digital Converter Driver cc ccecceeeceeeeeeenee eect eeneeeeeeaeeeeeeaeeeeeeaeeesetiaeeeeeenaeeeeeeaas 47 2 32 10 bit Digital to Analog Converter Driver ccccceceeeeeceecceceeeeeeeeecaeaeeeeeeeseseceaeeeeeeeseteenieeeeeeeereee 48 2 33 Temperature Sensor Driver ge a a r a aa Ea a ea E E EN 49 TIyg s ond derinitiOns oa oa a AAN eae eee TS 50 Sidi IDala ypes ra E AAAA saath A RA E ORA E A A A i eee 50 3 2 General de rin ithons x srie en eea ee aaa aa a aa Gy a a aa aaae e E 50 32 PD NO FUN O e a a aa sche aa aaa a a a a e e a A a e ae aA 50 322 PDE NO EP TRG aa ae alar aaeeea a acid saben tales eaea a a aa aen aaaea e iaa a n EE 50 32 3 PDL NO DATA ee e e ea adhe aaa aaa a aa e a a e iaaea aa Saute anche 50 324 PDLMCV GROUP e e e eaa coke a aaeeea a aa aae a aeiae anaa eia e EA 50 329r PDL VERSION aeea aaa aaret aae aaa Aa AE a e laa aa araa aa eaa teen AEA Laaa 50 3 2 6 Bit GerinitlOns Airs esaea a vad E a a ea aat aaae a ae eraa ana ad eve Razah eet Aaaa 50 Library References iiss hae ete alc AE A a 51 4 1 API List by Peripheral FUNCtION errer ceeccceeceeeeceeeeeeceeeseeceneeeeeneceeseeeeeeeneceeeeneneneeseeeecenseeeaeeeeneeeeeeteee 51 4 2 Deseription of Each API iiisicn cece eas ead eae See a ee a ee 54 4 2 1 Clock Generation Circuit ices ccsiedrcaheces custeitatece cee susietttnctedes aa aa a aeai a aged tureuante diate 55 DW RCG
378. eting the reception of data in Master mode 6 Monitoring the bus and handling the reception of data in Slave mode 7 Transmitting data in Slave mode 8 Control of the unit including bus lock up recovery support 9 Reading the status of the module Note The Clock Generation Circuit must be configured before configuring the 1 C module R20UT1963EE0100 Rev 1 00 Page 42 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 27 Serial Peripheral Interface Driver The driver functions support the use of the SPI channels providing the following operations 1 Selection of the SPI pins for use 2 Configuration for use including e Automatic clock setting using transfer rate as an input 3 Disabling channels that are no longer required and enabling low power mode 4 Configuration of command sequence settings 5 Managing the transfer of data on the interface including e Automatic interrupt control e Automatic DMAC DTC control 6 Control of special modes such as loopback 7 Reading the status of a module Note The Clock Generation Circuit must be configured before configuring any SPI channel R20UT1963EE0100 Rev 1 00 Page 43 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 28 IEBus Interface Driver The driver functions support the use of the IEBus channel providing the following operations 1 Selection of the IEBus pins for use 2 Configuration for use including e Automatic clock setting using th
379. eturn value True Category RTC Reference None Remarks Program example RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown the RTC R_RTC_Destroy R20UT1963EE0100 Rev 1 00 R AS Page 263 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 3 R_RTC_Control Synopsis Prototype Description 1 4 Modify the Real time clock operation bool R_RTC_Conitrol uint32_t data1 uint16_t data2 uint32_t data3 uint32_t data4 uint32_t data5 uint32_t data6 uint16_t data7 uint8_t data8 uint8_t data9 uint8_t data10 uint16_t data11 II Control selection Update selection II Current time II Current date Alarm time Alarm date Error Adjustment II Capture 0 configuration II Capture 1 configuration II Capture 2 configuration Periodic configuration Change clock settings and update the time or date data1 Change the clock operation To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA 12 or 24 hour mode PDL_RTC_24_HOUR_MODE or PDL_RTC_12_HOUR_MODE Alarm control PDL_RTC_ALARM_HOUR_DISABLE or PDL_RTC_ALARM_HOUR_ENABLE PDL_RTC_ALARM_MINUTE_DISABLE or PDL_RTC_ALARM_MINUTE_ENABLE PDL_RTC_ALARM_SECOND_ DISABLE or PDL_RTC_ALARM S
380. evice specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure for the selected channel R_MTU2_Create_structure ch4_parameters Load the defaults R_MTU2_Create_load_defaults amp ch4_parameters Set the non default options for channel 4 ch4_parameters channel_mode PDL_MTU2_MODE_NORMAL PDL_MTU2_SYNC_ENABLE PDL_MTU2_TGRA_DTC_TRIGGER_ENABLE h4_parameters counter_operation PDL_MTU2_CLK_PCLK_DIV_4 h4_parameters buffer_operation PDL_MTU2_BUFFER_AC_CM_A h4_parameters TGR_C_D_operation PDL_MTU2_C_OC_HIGH_CM_LOW h4_parameters TCNT_TCNTU_value 0 h4_parameters TGRA_TCNTV_value 199 h4_parameters TGRB_TCNTW_value 99 h4_parameters TGRC_TGRU_value 50 h4_parameters TGRD_TGRV_value 100 h4_parameters TGRE_TGRW_value 0 h4_parameters TGRF_TADCORA_value 0 qagqaqaqaaQnaQaaqaaa R_MTU2_Create 4 amp ch4_parameters R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 186 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 Synopsis Prototype Description Return value Category Reference Remarks Program example R_MTU2_Destroy Disable a Multi function Timer Pulse Unit bool R_MTU2_Destroy uint8_t data Unit selection Shut down a timer pu
381. f 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_MPC Write Synopsis Prototype Description Return value Category References Remarks Program example Write to a MPC register bool R_MPC_Write uint8_t data1 MPC register selection uint8_t data2 Data to be written to the MPC register Write the value to an MPC register data1 One of the definition values from 4 2 4 data2 The value to be written to the register True if a valid MPC register is specified otherwise false MPC registers None e The MPC registers are modified by other driver functions Take care to not overwrite existing settings e Refer to the hardware manual for valid values for each register RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void Write data to register PD1PFS R_MPC_Write PDL_MPC_REG_PD1PFS OxFF R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 104 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_MPC_Modify Synopsis Modify an MPC register Prototype bool R_MPC_Modify uint8_t data1 MPC register selection uint8_t data2 Logical operation uint8_t data3 Modification value Description Write the value to an MPC register data1 One of the d
382. f the SCI channels Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h uint8_t StatusValue uintl6_t TxChars uintl6_t RxChars void func void Read the status of SCI channel 0 R_SCI_GetStatus 0 amp StatusValue PDL_NO_PTR amp TxChars amp RxChars R20UT1963EE0100 Rev 1 00 AS Page 307 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 4 2 24 1 R_IIC_Create Synopsis Prototype Description 1 3 IC Bus Interface C channel setup bool R_IIC_Create 3 uint8_t data1 uint32_t data2 uint32_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint32_t data7 uint32_t data8 Set up the selected C channel data1 Select channel IICn where n 0 to 3 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Bus mode selection PDL_IIC_MODE_IIC or PDL_IIC_MODE_SMBUS or PDL_IIC_MODE_IIC_FMP Channel selection Channel configuration II Detection configuration Slave address Slave address Slave address Transfer rate control Rise and fall time correction Choose between C Bus or SMBus mode For channel 0 2C Fast Mode Plus is also available Internal reference clock PDL_lIC_INT_PCLK_DIV_1
383. false Category Compare Match Timer Reference R_CMT_Create Remarks e R_CMT_Create must be used first to configure the channel e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with a value change in one function call To avoid register access conflicts or invalid calls to the callback function use this method when changing any value e Ifthe CMCNT register value is changed to the same value as the CMCOR register the CMCNT register will be set to 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 255 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Change channel 2 to Ims period R_CMT_Control HN r DL_CMT_STOP PDL_CMT_PERIOD PDL_CMT_START E 3 R20UT1963EE0100 Rev 1 00 AS Page 256 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 5 R_CMT_Read Synopsis Prototype Description Return value Category Reference Read CMT channel status and registers bool R_CMT_Read uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location Read and store the counter value and
384. file is added to the list used by the linker application Select the Link Library tab From the Show entries for drop down menu select Library files Click on the Add button In the Add library file window select Project directory and enter RPDL RX63N_library as the File path Add library file Base path Project directory v i WorkSpace rpdl_lib_test rpdl_lib_test File path RPD LARAX63N_library Cancel Click on OK to close the window Click on OK to return to the main HEW window R20UT1963EE0100 Rev 1 00 AS Page 6 of 487 Jul 19 2012 RENES RX63N Group 1 Introduction 5 Include the new source files Use the key sequence Alt P A to open the Add files to project lt your project gt window Double click on the RPDL folder From the Files of type drop down list select C source file C Use the key sequence Ctrl A to select all of the files as shown below Add files to project rpdl_lib_test Look in RPOL e a a c Interrupt_A4DC_10 c c Interrupt_IEB c Interrupt_POE c Deana liq abies Interrupt_RTC c re ocr re we r T a c G Interrupt_BSC c B Interrupt _INTC c Interrupt _SCI c c Interrupt _CMT c B Interrupt_MTU2 c Interrupt_SPI c Interrupt_DMAC c fe Interrupt_MTU2_TPU c WE Interrupt_TMR c Interrupt_EXDMAC c Interrupt_not_RPDL c Interrupt_TPU c File name Interrupt _ADC_10 c Inter
385. finitions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t Status_flags R_CGC_Get Status amp Status_flags 3 R20UT1963EE0100 Rev 1 00 R AS Page 61 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 4 2 2 Interrupt Control Unit 1 R_INTC_SetExiInterrupt Synopsis Prototype Description 1 2 Select the external interrupt pins bool R_INTC_SetExtInterrupt uint32_t data1 Pin selection uint32_tdata2 Pin selection Assign the external interrupt pins data1 Allocate the pins for signals IRQO to IRQ7 All selections are optional If multiple selections are required use to separate each selection If no pins are required specify PDL_NO_DATA PDL_INTC_IRQO_P30 or PDL_INTC_IRQO_P10 or PDL_INTC_IRQO_PDO PDL_INTC_IRQ1_P31 or PDL_INTC_IRQ1_P11 or PDL_INTC_IRQ1_PD1 PDL_INTC_IRQ2_P32 or PDL_INTC_IRQ2_P12 or PDL_INTC_IRQ2_PD2 PDL_INTC_IRQ3_P33 or PDL_INTC_IRQ3_P13 or PDL_INTC_IRQ3_PD3 PDL_INTC_IRQ4_PB1 or PDL_INTC_IRQ4_P14 or PDL_INTC_IRQ4_ P34 or Select the pins to be used for signals IRQO to IRQ7 PDL_INTC_IRQ4_PD4 or PDL_INTC_IRQ4_PF5 PDL_INTC_IRQ5_PA4 or PDL_INTC_IRQ5_P15 or PDL_INTC_IRQ5_PD65 or PDL_INTC_IRQ5_PE5 PDL_INTC_IRQ6_PA3 or PDL_INTC_IRQ6_P16 or PDL_INTC_IRQ6_PD6 or PDL_INTC_IRQ6_PE6 PDL_INTC_IRQ7_PE2 or PDL_INTC_IRQ7_P17 or PDL_INTC_IRQ7_PD7 or PD
386. flags shall be stored in the format below The input capture compare match flags will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read Forn 0 b7 b6 b5 b4 b3 b2 b1 bO Detection Count Overflow Input capture compare match direction v F E podic B A up Forn 1o0r2 b7 b6 b5 b3 b2 b1 bO Detection Count Underflow Overflow Input capture compare match direction 0 down U V 0 B A Tu Forn 3 b7 b6 b5 b4 b3 b2 b1 bO i Detection Count Overflow Input capture compare match direction 0 vV olpc B A 0 down 1 up Forn 4 b7 b6 b5 b4 b3 b2 b1 bO Oo _ Detection Le underflow Input capture compare match direction 0 v olp c B A 0 down 1 u Forn 5 b7 b3 b2 b1 bO E Detection Input capture compare match 0 W V U R20UT1963EE0100 Rev 1 00 ae ENESAS Page 196 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 data3 For n 0 to 4 A pointer to where the TNCT register value shall be stored For n 5 Apointer to where the TNCTU register value shall be stored Specify PDL_NO_PTR if it is not required data4 For n 0 to 4 A pointer to where the TGRA register value shall be stored For n 5 Apointer to where the TNCTV register value shall be stored Specify PDL_NO_P
387. for n 0 3 and 4 PDL_MTU2_BUFFER_BD_CM Bor PDL_MTU2_BUFFER_BD_TCNT_CLR Transfer the data from TGRD to TGRB when a compare match B occurs or when TCNT is cleared in each channel Valid for n 0 3 and 4 PDL_MTU2_BUFFER_EF_CM _E or PDL_MTU2_BUFFER_EF_TCNT_CLR Transfer the data from TGRF to TGRE when a compare match E occurs or when TCNT is cleared in either channel Valid for n 0 Transfer on TCNT clear is available only in PWM mode 1 or 2 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 180 of 487 RX63N Group 4 Library Reference Description 5 9 TGR_A_B_operation Configure the operation for general registers TGRA and TGRB Valid for n 0 to 4 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Input capture output compare control for register TGRA PDL_MTU2_A_OC_DISABLED or MTIOCnA output disabled PDL_MTU2_A_OC_LOW or MTIOCnA output low PDL_MTU2_A_OC_LOW_CM_HIGH or MTIOCnA initial output low goes high at compare match PDL_MTU2_A_OC_LOW_CM_INV or MTIOCnA initial output low toggles at compare match PDL_MTU2_A_OC_HIGH_CM_LOW or MTIOCnA initial output high goes low at compare match PDL_MTU2_A_OC_HIGH or MTIOCnA output high PDL_MTU2_A_OC_HIGH_CM_INV or MTIOCnA initial output high toggles at compare match PDL_MTU2_A_IC_RISING_EDGE o
388. for polling or interrupts Note The Clock Generation Circuit must be configured before configuring the ADC unit R20UT1963EE0100 Rev 1 00 Page 46 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 31 10 bit Analog to Digital Converter Driver The driver functions support the use of the 10 bit ADC unit providing the following operations 1 I O pin configuration 2 Configuration for use including e Automatic clock setting using sampling time as an input e Automatic interrupt control 3 Disabling units that are no longer required and enabling low power mode 4 Control the unit including e CPU sleep option 5 Reading the conversion results of the 10 bit ADC unit with support for polling or interrupts Note The Clock Generation Circuit must be configured before configuring any 10 bit ADC unit R20UT1963EE0100 Rev 1 00 Page 47 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 32 10 bit Digital to Analog Converter Driver The driver functions support the use of the DAC module providing the following operations 1 Configuring a channel for use including e Data alignment D A A D synchronous conversion 2 Disabling channels that are no longer required and enabling low power mode 3 Writing data to a channel R20UT1963EE0100 Rev 1 00 Page 48 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 33 Temperature Sensor Driver The driver functions support the use of the Temperature Sensor
389. fresh register PDL_BSC_SDRAM_SELF_REFRESH_ENABLE Set Self Refresh register e Clear Self Refresh register PDL_BSC_SDRAM_SELF_REFRESH_DISABLE Clear Self Refresh register e Enable SDRAM PDL_BSC_SDRAM_ENABLE Enable SDRAM operation e Disable SDRAM PDL_BSC_SDRAM_DISABLE Disable SDRAM operation Return value True if success False if invalid parameters are selected Category Bus Controller Reference R_BSC_Create Remarks e Before enabling the BSC operation call R_BSC_Create e This function can be called from the error handling function assigned in R_BSC_Create e This function will clear the Interrupt Status Flag indirectly Only one SDRAM control operation is allowed at one time e SDRAM is not supported by the 100 pin device package SDRAM options will be ignored R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 138 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Clear the bus error signals R_BSC Control PDL_BSC_ERROR_CLEAR R20UT1963EE0100 Rev 1 00 AS Page 139 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 6 R_BSC_SDRAM_CreaiteArea Synopsis Configure the SDRAM area Prototype bool R_BSC_SDRAM_CreaieArea uint16_t data1 Configuratio
390. full or 24 bit short address mode eri address of the area of on chip RAM where the DTC vector table shall be stored The address must be on a 4 kB boundary i e have the format xxxxx000h True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create Before calling R_DTC_Create call this function RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 void func void Configure the controller R_DTC_Set PDL_DTC_ADDRESS_SHORT dtc_vector_table R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 164 of 487 RX63N Group 4 Library Reference 2 R_DTC_Create Synopsis Prototype Description 1 4 Configure the Data Transfer Controller for a transfer bool R_DTC_Creaite uint32_t data1 uint32_t data2 void data3 void data4 uint16_t data5 uint8_t data6 II Configuration selection Transfer data start address Source start address Destination start address Transfer count Block size Configure DTC activation for one trigger source data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold
391. function to be called before any data has been transferred This function should then be called again to continue monitoring the bus Channels 1 and 3 are not available with the 100 pin package This function will return false in this case RPDL definitions nclude r_pdl_iic h RPDL device specific definitions nclude r_pdl_definitions h latile uint8_t data_array 5 id func void Monitor channel 0 using polling R_IIC_SlaveMonitor 0 PDL_NO_DATA data_array 5 PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 REN ESAS Page 320 of 487 Jul 19 2012 RX63N Group 4 Library Reference 7 R_IIC_SlaveSend Synopsis Write data to a master device Prototype bool R_IIC_SlaveSend uint8_t data1 Channel selection uint8_t data2 Data start address uint16_tdata3 Data count Description Transmit data on the specified channel data1 Select channel IICn where n 0 to 3 data2 The start address of the data to be sent data3 The number of bytes available to be sent Return value True if all parameters are valid exclusive and achievable otherwise false If this function is not called from the R_IIC_SlaveMonitor callback function it will complete when a stop condition is detected Category C Reference R_IIC_SlaveMonitor Remarks e Use this function after using R_IIC_SlaveMonitor and detecting that a slave transmi
392. g this function If using the digital filter the LOCO clock must be enabled Use R_CGC_Set with the LOCO selected Following a reset function R_LPC_GetStatus can be used to see what caused the reset If using a delay on Reset negation then the LOCO clock must be enabled See R_CGC_Set or R_CGC_Control Ensure Monitor 1 and 2 are in PDL_LVD_MONITOR_ONLY during flash memory programming erasure Disable the digital filter circuit when using voltage monitoring 1 and 2 circuit in software standby mode or deep software standby mode Do not use the voltage detection 1 and 2 circuit in deep software standby mode with PDL_LPC_DEEPCUT_RAM_USB_LVD See function R_LPC_Create For control of voltage monitor 0 see R MCU_OFS RPDL definitions include r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void Callback_LowVoltage void void func void Use Monitor 2 to generate an NMI when VCC drops below 2 95 V R_LVD_Create PDL_NO_DATA PDL_LVD_INTERRUPT_NMI_DETECT_FALL PDL_LVD FILTER DISABLE R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 113 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_LVD Control Synopsis Prototype Description Return value Category References Remarks Program example Control the voltage detection circuit bool R_LVD_Conitrol
393. generation circuit bool R_CGC_Set uint8_t data1 Clock selection uint32_t data2 Configuration options double data3 Clock frequency double data4 System clock frequency double data5 Peripheral module clock A frequency double data6 Peripheral module clock B frequency double data7 Flash interface clock frequency double data8 External bus clock frequency double data9 IEBus clock frequency double data10 USB clock frequency Set a clock source frequencies and options data1 Clock source selection e Clock source selection PDL_CGC_CLK_LOCO or Select the low speed on chip oscillator LOCO PDL_CGC_CLK_HOCO or high speed on chip oscillator HOCO PDL_CGC_CLK_MAIN or main clock oscillator PDL_CGC_CLK_SUB_ CLOCKor sub clock oscillator PDL_CGC_CLK_PLL or Phase locked loop PLL circuit or IWDT dedicated PDL_CGC_CLK_IWDTLOCO low speed clock on chip oscillator IWDTLOCO data2 Configuration settings e BCLK signal control PDL_CGC_BCLK_DIV_1 or Select the BCLK or PDL_CGC_BCLK_DIV_2 or BCLK 2 signal to be output or PDL_CGC_BCLK_DISABLE disable the BCLK signal e SDCLK signal control ignored if the device package does not support the external bus PDL_CGC_SDCLK_ENABLE or Allow the SDRAM clock SDCLKk signal to be output on PDL_CGC_SDCLK_DISABLE the SDCLK pin or leave the SDCLK pin as an I O port data3 The frequency of the selec
394. gs shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b5 b4 b3 b2 b1 bO Interrupt Transfer Escape Transfer End Status po 0 request End interrupt ESIF interrupt DTIF ACT DTE IR 0 Idle 0 Idle 0 Idle 0 Disabled 1 Generated 1 Generated 1 Operating 1 Enabled data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required data6 Where the current repeat or block size count shall be stored Specify PDL_NO_PTR if it is not required Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_Create Remarks Ifthe Interrupt request flag is set to 1 the flag will be cleared to O by this function R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 153 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t StatusValue uint32_t SourceAddr Read the status and current source address for channel 2 R_DMAC_GetStatus 2 amp StatusValue amp SourceAddr PDL_N
395. h Main clock frequency Hz define FREQ_ MAIN 12E6 Callback function prototype void BSC_error_handler void void main void volatile uint8_t csO_location_8 volatile uint8_t csl_location_8 volatile uintl6_t cs2_location_16 volatile uintl6_t cs3_location_16 volatile uint32_t cs7_location_32 Point to respective external memory areas cs7_location_32 uint32_t 0x01000000ul1 cs3_location_16 uintl6_t 0x05000000ul ecs2_location_16 uintl6_t 0x06000000ul csl_location_8 uint8_t 0x07000000ul1 csO_location_8 uint8_t OxFF000000ul Configure clocks Run from PLL and enable the External Bus clock BCLK Prepare the main clock settings R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_BCLK_ENABLE PDL_CGC_SDCLK_DISABL FREQ MAIN FREQ MAIN 4 FREQ MAIN 4 FREQ _MAIN 4 FREQ _MAIN 4 FREQ MAIN 4 PDL_NO_DATA PDL_NO_DATA Prepare the PLL clock settings R_CGC_Set PDL_CGC_CLK_PLL PDL_CGC_BCLK_ENABLE PDL_CGC_SDCLK_DISABLI 192E6 96E6 48E6 48E6 24E6 24E6 PDL_NO_DAT PDL_NO_DAT Select the PLL as the clock source R_CGC_Control R20UT1963EE0100 Rev 1 00 AS Page 396 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Configure area 0 R_BSC_CreateArea 0 PDL_BSC_WIDTH_8 155 15 7 7 31 C
396. h or Input capture C Compare match or Input capture D Compare match or Input capture A Compare match or Input capture A Compare match or Input capture B PDL_INTC_VECTOR TGI3A PDL_INTC_VECTOR TGI3B PDL_INTC_VECTOR TGI3C PDL_INTC_VECTOR_TGI3D Timer Pulse Unit channel 3 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D PDL_INTC_VECTOR_TGI4A Timer Pulse Unit Compare match or Input capture A PDL_INTC_VECTOR_TGI4B channel 4 Compare match or Input capture B PDL_INTC_VECTOR_TGI5A Timer Pulse Unit Compare match or Input capture A PDL_INTC_VECTOR_TGI5B channel 5 Compare match or Input capture B PDL_INTC_VECTOR_TGI6A_AO PDL_INTC_VECTOR_TGI6B_BO PDL_INTC_VECTOR_TGI6C_CO PDL_INTC_VECTOR_TGIEO PDL_INTC_VECTOR_TGI6D_DO PDL_INTC_VECTOR_TGIFO Timer Pulse Unit channel 6 or Multi function Timer Pulse Unit channel 0 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Compare match E Compare match F PDL_INTC_VECTOR_TGI7A_A1 PDL_INTC_VECTOR_TGI7B_B1 Timer Pulse Unit channel 7 or Multi function Timer Pulse Unit channel 1 Compare match or Input capture A Compare match or Inpu
397. hannel is to be configured e Pins which are not used may be omitted RPDL definitions include r_pdl_exdmac h RPDL device specific definitions include r_pdl_definitions h void func void Configure EDREQO on Pin P22 R_EXDMAC_Set 0 PDL_EXDMAC_PIN_EDREQO_P22 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 155 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_EXDMAC Create Synopsis Prototype Description 1 3 Configure the EXDMA controller bool R_EXDMAC_Create uint8_t data1 Channel selection uint32_t data2 Configuration selection uint16_t data3 Configuration selection uint8_t data4 Configuration selection void data5 Source start address void data6 Destination start address uint16_t data7 Transfer count uint16_t data8 Repeat or Block size int32_t data9 Address offset uint32_t data10 Source address extended repeat area uint32_t data11 Destination address extended repeat area void func Callback function uint8_t data12 Interrupt priority level Set up an EXDMAC channel data1 The channel number n where n 0 to 1 data2 Configure the operation of channel EXDMACn Use to separate each selection Transfer mode selection PDL_EXDMAC_NORMAL or Normal or PDL_EXDMAC_REPEAT or Repeat or PDL_EXDMAC_BLOCK or Block or Clu
398. hannel selection uint32_t data2 Status flags uinti6_t data3 Transmitted bytes uint16_t data4 Received bytes Read the status registers for the selected I C channel data1 Select channel IICn where n 0 to 3 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b31 b18 b17 b16 Buffer status 0 Transmit Receive 0 Full 0 Empty 1 Empty 1 Full b15 b14 b13 b12 b11 b10 b9 b8 Bus state Pin level Event detection 0 Not detected 1 detected 0 Idle sct spa nack _ StoP Start Arbitration lost Timeout 1 Busy condition condition b7 b6 b5 b4 b3 b2 b1 bO Transmission Mode Address detection 0 Not detected 1 detected 0 Active 0 Receive Slave 4 Idle 1 Transmit SMBus host Device ID General call 7 1 0 data3 The address for storing the number of bytes that are have been transmitted in the current transfer Specify PDL_NO_PTR if this information is not required data4 The address for storing for the number of bytes that are have been received in the current transfer Specify PDL_NO_PTR if this information is not required Return value True if all parameters are valid otherwise false Category lC Reference R_IIC_Create Remarks e The flags are not modified by this function The event detection flags are cleared as required by the driver fo
399. he counter clock source and compare match value will be calculated by this function The parameter data3 will specify the timer frequency PDL_CMT_FREQUENCY or The counter clock source and compare match value will be calculated by this function Select the internal clock signal PCLKB 8 32 128 or 512 as the counter clock source The parameter data3 will be the register CMCOR value PDL_CMT_PCLK_DIV_8 or PDL_CMT_PCLK_DIV_32 or PDL_CMT_PCLK_DIV_128 or PDL_CMT_PCLK_DIV_512 Counter start control PDL_CMT_START or PDL_CMT_STOP Enable or disable the starting of the timer count operation e DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENABLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The data to be used for the register value calculations Data use Parameter type The timer period in seconds or double The timer frequency in Hz or double The value to be put in register CMCOR uint16_t func The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CGC
400. he interrupt processing function This means that no other interrupt can be processed until the callback function has completed e There are some pin restrictions when using the 100 pin device packages e Function R_CGC_Set must be called with the current clock source selected before using this function Allow 10 ms to elapse from the completion of this function to the start of the first conversion For more details of the MTU or TMR trigger options please refer to the RX63N hardware manual This function will return false if an invalid unachievable sampling time is specified e When the temperature sensor output or the A D internal reference voltage is selected single scan mode must be selected R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 359 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h ADC callback function void ADCIntFunc void void func void Set up the ADC in single mode using ANO and AN2 R_ADC_12_Create 0 PDL_ADC_12_CHANNEL_O PDL_ADC_12_CHANNEL_2 PDL_ADC_12_SCAN_SINGLE PDL_ADC_12_DIv_1 PDL_ADC_12_TRIGGER_SOFTWARE PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA ADCIntFunc 2 R20UT1963EE0100 Rev 1 00 Page 360 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 2 R_ADC_12_Dest
401. he moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the pro
402. he user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For register select one of the registers listed in the tables starting on page 75 Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set bits 6 and 4 in IERO9 to 1 R_INTC_Modify PDL_INTC_REG_IERO9 PDL_INTC_OR 0x50 i R20UT1963EE0100 Rev 1 00 ae AS Page 82 of 487 Jul 19 2012 ENES RX63N Group 4 Library Reference 11 R_INTC_CreateGroup Synopsis Prototype Description Return value Category Reference Configure a group of peripheral interrupt requests bool R_INTC_CreateGroup uint8_t data1 Group selection void func Callback function uint8_t data2 Interrupt priority level Set up the grouped interrupt request callback function data1 The interrupt request group n to be configured where n 0 to 6 or 12 func The function to be called when a valid condition is detected data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_ControlGroup Remarks Program example Do not use this function if RPDL functions will be used to configure the applicable
403. ibrary Reference 2 R_POE_Create Synopsis Prototype Description Configure the Port Output Enable event handling bool R_POE_Create uint8_t data1 Input configuration selection void func Callback function void func2 Callback function uint8_t data2 Interrupt priority level Enable interrupts and register callback functions data1 Interrupt selection If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e High impedance request response Disable or enable an interrupt on detection of PDL POE IRQ Mli 0 3 DISABLE r any high impedance request on pins POEO to POE3 PDL_POE_IRQ_HI_Z_0_3 ENABLE e Output short detection response Disable or enable an interrupt on detection of Pie cen ee or fa short on any MTU channel 3 or 4 two phase JAE output pair func1 The function to be called when an enabled request on pins POEO to POE3 or an output short on MTU channels 3 or 4 occurs Specify PDL_NO_FUNC if not required func2 The function to be called when a request on pin POE8 occurs Specify PDL_NO_FUNC if not required data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 a
404. id Disable the interrupt for the overflow on MTU channel 0 and clear the flag R_INTC_ControlGroup 1 PDL_INTC_GROUP_DISABLE PDL_INTC_GROUP_CLEAR PDL_INTC_GRP1_TCIVO Enable all of the Group 3 interrupt sources R_INTC_ControlGroup 3 PDL_INTC_GROUP_ENABLE PDL_INTC_GRP3_ALL R20UT1963EE0100 Rev 1 00 R AS Page 85 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 13 R_INTC_GetStatusGroup Synopsis Prototype Description 1 2 Read the status of an interrupt request group bool R_INTC_GetStatusGroup uint8_t data1 Group selection uint32_t data2 Data storage location Read the grouped interrupt request status flags data1 The interrupt request group n to be read where n 0 to 6 or 12 data2 The status flags shall be stored in the format below e Group 0 b31 b3 b2 b1 bO CAN error interrupts 0 Channel 2 Channel 1 Channel 0 0 Not requested 1 Requested e Group 1 b31 b3 b2 b1 bO MTU interrupts Underflow on Overflow on Overflow on 0 channel 1 channel 1 channel 0 0 Not requested 1 Requested e Group 2 b31 b3 b2 b1 bO MTU interrupts Overflow on Underflow on Overflow on 0 channel 3 channel 2 channel 2 0 Not requested
405. id_received R_SCI_Receive 9 PDL_NO_PTR 0 PDL_NO_FUNC SCIEr if id_received true Receive data ID 0x01 R_SCI_Receive 9 PDL_NO_DATA receive_data 10 PDL_NO_FUNC SCIEr void SCIrx void data_received true void SCIEr void error_happen true r 0x0100 PDL_SCI_MP_ID_CYCLE by polling Figure 5 32 Example of SCI Reception code in Asynchronous Multi Processor mode R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 434 of 487 RX63N Group 5 Usage Examples 5 17 7 SCI Transmission in Asynchronous Multi Processor mode This shows the setting of SCI channel 9 and the Multi Processor mode transmission of data using interrupts and polling PDL functions include r_pdl_sci h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h void SCItx void uint8_t send_data0 n rWelcome to the Renesas RX63N n r uint8_t send_data testing ASYNC MP mode bool tx_end void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set pin options R_SCI_Set 9 PDL_SCI_PIN_SCI9_TXD9_PB7 PDL_SCI_PIN_SCI9_RXD9_P
406. ied for parameter func True if all parameters are valid and exclusive otherwise false R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 366 of 487 Jul 19 2012 RX63N Group 4 Library Reference Category 10 bit ADC References R_CGC_Set R_LADC_10_Control R LADC_10_Read Remarks e This function configures the selected pin s for ADC operation by setting the direction to input and turning off the input buffer The port control settings for any ADC pins that subsequently become inactive are not modified e This function brings the selected converter unit out of the power down state e Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in 6 e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e Function R_CGC_Set must be called with the current clock source selected before using this function e The available values for the conversion clock are PCLK 8 4 2 or 1 If the desired frequency is not an exact match the actual frequency will be the next highest frequency The timing limits depend on the peripheral module clock PCLK Use the table below with the appropriate frequency for fpcik See A fecik MHz Parameter Limit Equation 50 48 32 125 12 8 Conversioniclock Minimum fpc k 8 4
407. igure 5 56 shows ADC_12 used in single scan mode with a software trigger and a specified sampling time Peripheral driver function prototypes include r_pdl_adc_12 h include r_pdl_cmt h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h Array used to read the ADC results uintl6_t adc_results 21 void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure ADC channels 0 2 and 4 in single scan mode Specify a sampling time Use value addition mode on channel 4 R_ADC_12_Create 0 PDL_ADC_12_ CHANNEL_0 PDL_ADC_12_CHANNEL_2 PDL_ADC_12_CHANNI PDL_ADC_12_ SCAN SINGLE PDL_ADC_12_ DIV_2 PDL_ADC_12_ SAMPLING _TIME_ CALCULATE PDL _ADC_12_TRIGGER_SOFTWARI PDL_ADC_12_VALUE_ADD_CHANNEL_4 PDL_ADC_12_VALUE_ADD_TIME_4 3e 6 Sampling time 3uS PDL_NO_DATA Sampling time for temperature PDL_NO_FUNC PDL_NO_DATA Wait 10 ms for the ADC to stabilise R_CMT_CreateOneShot 0 0 10E 3 PDL_NO_FUNC 0 Start Trigger the ADC R_ADC_12_ Control PDL_ADC_12_0_ON Fetch the results R_ADC_12_Read 0 adc_results while 1 Figure 5 56 Example of ADC_12 R20UT1963EE0100 Rev 1 00 Page 482 of 487
408. ilers and Assemblers C C Compiler Package for RX Family 1 2 Using the library within your project The driver library can be used in two ways 1 2 1 Via the PDG graphical utility PDG can be downloaded from www renesas com pdg The directions for use of the PDG utility are given in the PDG manual 1 2 2 Added to a project by the user and used stand alone To add the driver library to your project s build environment you need to Unzip the RPDL distribution Copy the required source header and library files into your project folder Include the required source files a b c d Add the driver library file to the linked files list The instructions to follow for stand alone use start are given below 1 Unzip the RPDL files Double click on the file RPDL_RX63N exe to unpack the files The default location is C Renesas RPDL_RX63N 2 Copy the files into your project area Navigate to where the RPDL files were unpacked fm C Renesas RPDL_RX63N MBR File Edit view Favorites Toos Y Back gt S Ss Search gt Address C Renesas RPDL_RX63N ed Go D Device specific S fCopy RPDL_RX63N bati 3 objec 4 72 KB 4 My Computer Double click on Copy_RPDL_RX63N bat to start the copy process R20UT1963EE0100 Rev 1 00 AS Page 2 of 487 Jul 19 2012 RENES RX63N Group 1 Introduction BEE B Renesas RPDL for RX63N copy utility Please enter a number to sel
409. in BCD format xx xx For example 0100h is v1 00 A usage example is const uint1l6_t rpdl_version_number PDL_VERSION 3 2 6 Bit definitions The definitions BIT_n and INV_BIT_n where n 0 to 31 are available to the user R20UT1963EE0100 Rev 1 00 R AS Page 50 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 4 Library Reference 4 1 API List by Peripheral Function Table 4 1 lists the Renesas Embedded APIs by peripheral function Table 4 1 Renesas Embedded API List Category Number Name Description Clock 1 R_CGC_Set Configure the clock generation circuit Generation 2 R_CGC_Control Modify the clock generation circuit operation Circuit 3 R_CGC_GetStatus Read the status of the clock generation circuit 1 R_INTC_SetExtlnterrupt Select the external interrupt pins 2 R_INTC_CreateExtInterrupt Configure an external interrupt signal 3 R_INTC_CreateSoftwarelnterrupt Enable use of the software interrupt 4 R_INTC_CreateFastInterrupt Assign handlers for the fixed vector interrupts 5 R_INTC_CreateExceptionHandlers Enable faster interrupt processing for one interrupt 6 R_INTC_ControlExtInterrupt External int
410. ing e Access to all control bits e Automatic interrupt control e Automatic I O pin configuration 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer channel 5 Control of a timer unit 6 Reading the status flags and registers of a timer channel 7 Reading the status flags and registers of a timer unit Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT1963EE0100 Rev 1 00 Page 32 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 17 Port Output Enable Driver The driver functions support the use of the Port Output module providing the following operations 1 2 Configuring the pins for use Configuring the interrupts and callback functions Run time control of outputs interrupts and flags Checking the module status R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 33 of 487 RX63N Group 2 Driver 2 18 Timer Pulse Unit Driver The driver functions support the use of the twelve 16 bit timers providing the following operations 1 I O pin configuration 2 Configuration for use including e Access to all control bits e Automatic interrupt control 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer 5 Reading the status and registers of a timer R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 34 of 487 Jul 19 2012 RX63N Group 2 D
411. ing from normal power consumption mode to low power consumption mode call R_CGC_Set to change the clock settings before calling this function When PDL_LPC_SLEEP_RETURN_SWITCH_HOCO is selected ensure the power to the HOCO is enabled before the transition to sleep mode is made Sleep mode return clock source switching should only be enabled if using the LOCO or sub clock during the transition to sleep mode When the PLL is operating low speed operating mode 1 or 2 cannot be selected This function will return false is this situation The Low speed operating modes put restrictions on the allowable clock ranges for ICLK FCLK PCLKB and BCLK This function will return false if any of these clocks are not within the range specified in the Hardware Manual For more details of the operating power control please refer to the RX63N hardware manual RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Allow a falling edge on IRQ2 DS to cancel deep software standby R_LPC_Create PDL_NO_DATA PDL_LPC_CANCEL_IRQ2_FALLING PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 121 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_LPC_Conirol Synopsis Prototype Description Return value Category References
412. ion uint32_t data9 Alarm time uint32_t data10 Alarm date void func1 Callback function uint8_t data11 Interrupt priority level void func2 Callback function uint8_t data12 Interrupt priority level Set up and start the Real time clock data1 Configure the clock options To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the default if not enabling the alarm 12 or 24 hour mode PDL_RTC_24 HOUR MODE or PDL_RTC_12 HOUR MODE Select 12 or 24 hour mode Alarm enablin PDL_RTC_ALARM_HOUR_ENABLE PDL_RTC_ALARM_MINUTE_ENABLE PDL_RTC_ALARM_SECOND_ ENABLE All three can be enabled using PDL_RTC_ALARM_TIME_ENABLE PDL_RTC_ALARM_YEAR_ ENABLE PDL_RTC_ALARM_ MONTH ENABLE PDL_RTC_ALARM_DAY_ENABLE PDL_RTC_ALARM_DOW_ENABLE All four can be enabled using PDL_RTC_ALARM_DATE_ENABLE Clock output control PDL_RTC_OUTPUT_DISABLE or PDL_RTC_OUTPUT_ENABLE Disable or enable the 1 Hz clock output on the RTCOUT pin Count source selection Compulsory option PDL_RTC_COUNT_SOURCE_SUBCLK or PDL_RTC_COUNT SOURCE MAINCLK Select the count source R20UT1963EE0100 Rev 1 00 ztENESAS Jul 19 2012 Page 258 of 487 RX63N Group 4 Library Reference Description 2 4 data2 Specify pins that will be us
413. ions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void Stop the sub clock oscillator R_CGC_Control PDL_NO_DATA PDL_NO_DATA PDL_CGC_SUB_CLOCK_DISABLE Select the PLL R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 60 of 487 RX63N Group 4 Library Reference 3 R_CGC_GetStatus Synopsis Read the status of the clock generation circuit Prototype bool R_CGC_GetStatus uint16_t data Pointer to the variable where the status value shall be stored Description Read the clock status register data The status flags shall be stored in the format below b15 b14 b13 b12 b11 b10 b9 b8 HOCO Clock control 0 power HOCO IWDTLOCO LOCO Sub clock Main clock PLL 0 Power on 0 Operating 1 Power off 1 Stopped b7 b6 b4 b3 b2 b1 bO Selected clock source Main clock oscillation stop detection 000b LOCO 0 001b KOGO 0 0 Disabled 0 Normal operation 2195 Main Gioek 1 Enabled 1 Stop detected 011b Sub clock a 100b PLL Return value True Category Clock generation circuit References R_CGC_Control Remarks e Use R_CGC_Control to clear the main clock oscillation stop detection flag Program example RPDL de
414. ions include r_pdl_definitions h void POEO_3 handler void void POE8_ handler void void main void Configure POE pins R_POE_Set _POE_0_MODE_EDGE PDL _POER_1 MODE _LOW_8 PORK _2 MODE _LOW_16 PDL E 3 MODE_LOW_128 POE_8_MODE_LOW_8 0 2 8 1 POE POR 7 PDL_POE PO 1 POE POR 5 PDL_POE PO POE 3 POE_HI_Z_RE 8_ENABLE i POE HI 2 REQ OSTSTE _ POE_HI_Z REQ MTIOCOA E_HI_Z REQ MTIOCOB POE_HI_Z_RE MTIOCOC PDL EB HI_Z REQ MTIOCOD Create POK_IRQ_HI_Z_0_3_ DISABLE PDL_POE_IRQ_SHORT_3_4 DISABLE EO_3_handler POE8_handler 15 6 4 D D POR uvuguvugu vavo td Ov while 1l void POEKO0O_3_ handler void uintlo_t Statusk lags Read the POE status R_POE_GetStatus amp StatusFlags POEO request if StatusFlags amp BIT_0O 0x0u Prevent further interrupts and try to clear the flag R_POE_Control PDL_NO_DATA PDL_POE_FLAG_POEO_CLEAR PDL_POE_IRQ_HI_Z_0_3_DISABLE POE8_handler void uint16_t StatusFlags Read the POE status R_POE_GetStatus amp StatusFlags Prevent further interrupts an
415. ission and reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA 9 SCI1TxBuffer SCI1TxFunc SCI1RxBuffer SCI1RxFunc SCI1ErrFunc R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 298 of 487 RX63N Group 4 Library Reference 7 R_SCI_IIC_Write Synopsis Prototype Description 1 2 Perform an IIC master write on an SCI channel bool R_SCILIIC_Write uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave Address uint16_t data4 Number of bytes to transfer uint8_t data5 Buffer void func Callback function Perform an IIC master write data1 Select channel SCIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL_SCI_IIC_10_BIT_ SLAVE_ADDRESS Specify the slave address width Repeated Start PDL_SCI_IIC_RESTART The transfer will start with a re start rather than the default behaviour of a start condition Stop Condition selection By default the transfer will end with a stop condition PDL_SCI_IIC_NOSTOP Select this op
416. iver 2 7 MCU Operation Driver The driver functions support access to the registers which select the mode of operation for the microcontroller These functions support 1 Controlling the MCU features and on chip ROM and RAM 2 Reading the MCU status flags 3 Setting the MCU start up options R20UT1963EE0100 Rev 1 00 Page 23 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 8 Voltage Detection Circuit Driver The driver function supports configuration of VDET1 and VDET2 voltage detection circuits This function supports 1 Setting voltage thresholds 2 Defining a voltage event 3 Configuring a reset when supply voltage drops below a voltage threshold R20UT1963EE0100 Rev 1 00 Page 24 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 9 Frequency Measurement Circuit Driver The driver functions support access to the registers which control the frequency measurement circuit These functions support 1 Selecting the reference clock for each measurement system R20UT1963EE0100 Rev 1 00 Page 25 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 10 Low Power Consumption Driver The driver functions support access to the registers which select the lower power modes of operation for the microcontroller These functions support 1 Configuring the state while in standby mode and the activity that can be used to resume operation 2 Selecting one of the low power modes 3 Writing
417. l 1 C bus interface channel 2 Transfer error or event generation Data received Start of next data transfer End of data transfer Transfer error or event generation Data received Start of next data transfer End of data transfer PDL_INTC_VECTOR_ICEEI3 PDL_INTC_VECTOR_ICRXI3 PDL_INTC_VECTOR_ICTXI3 PDL_INTC_VECTOR_ICTEI3 PDL_INTC_VECTOR_DMACOI PDL_INTC_VECTOR_DMAC1I PDL_INTC_VECTOR_DMAC2I PDL_INTC_VECTOR_DMAC3I C bus interface channel 3 Direct memory access controller Transfer error or event generation Data received Start of next data transfer End of data transfer Transfer complete or Transfer escape end PDL_INTC_VECTOR_EXDMACOI PDL_INTC_VECTOR_EXDMAC1I External DMAC Transfer complete or Transfer escape end PDL_INTC_ VECTOR RXIO Data received PDL_INTC VECTOR _TXIO SCI channel 0 Start of next data transfer PDL_INTC VECTOR _TEIO End of data transfer PDL_INTC_VECTOR_RXI1 Data received PDL_INTC_VECTOR_TXI1 SCI channel 1 Start of next data transfer PDL_INTC_VECTOR_TEI1 End of data transfer PDL_INTC VECTOR RXI2 Data received PDL_INTC VECTOR _TXI2 SCI channel 2 Start of next data transfer PDL_INTC VECTOR _TEI2 End of data transfer PDL_INTC VECTOR _ RXI3 Data received PDL_INTC VECTOR _TXI3 SCI channel 3 St
418. l 3 or 4 two phase output pair Return value True if all parameters are valid and exclusive otherwise false Category Port Output Enable Reference R_POE_Create Remarks Call R_POE_Create before using this function e Clearing a level triggered event flag will fail if the trigger is still asserted e Interrupt disabling is processed at the start of the function and enabling is processed at the end This allows a flag to be cleared and the interrupt re enabled in one function call R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 204 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void Select high impedance on the MTUO I O pins R_POE_Control PDL_POE_MTUO_HI_Z_ON PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 AS Page 205 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 4 R_POE_GetStatus Synopsis Check the status of the Port Output Enable module Prototype bool R_POE_GetStatus uint16_t data Status flags pointer Description Return the status flags data The status flags shall be stored in the following format b15 b14 b13 b10 b9 b8 Output short detection High impedance request detection more 0 MTU3 or MTU4 0
419. l settings are optional Specify PDL_NO_DATA if no control is required e MTU channel high impedance control PDL_POE_MTU3_MTU4_HI_Z_ONor Control the high impedance state of the MTU3 and PDL_POE_MTU3_MTU4_HI_Z OFF MTU4 outputs PDL_POE_MTUO_HI_Z_ON or Control the high impedance state of the MTUO PDL_POE_MTUO_HI_Z_ OFF outputs data2 Event flag control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required PDL_POE_FLAG_POEO CLEAR PDL_POE_FLAG_POE1_CLEAR PDL_POE_FLAG_POE2_ CLEAR PDL_POE_FLAG_POE3_CLEAR Select the flags to be cleared PDL_POE_FLAG_POE8 CLEAR PDL_POE_FLAG OSTSTF_CLEAR PDL_POE_FLAG_SHORT_3 4 CLEAR data3 Interrupt control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required e High impedance request response PDL_POE_IRQ_HI_Z_0_3_ DISABLE Control interrupts on detection of any high PDL_POE_IRQ_HI_Z 0 3 ENABLE impedance request on pins POEO to POE3 PDL_POE_IRQ_HI_Z_ 8 DISABLE Control interrupts on detection of a high PDL_POE_IRQ_HI_Z_8 ENABLE impedance request on pin POE8 e Output short detection response PDL_POE_IRQ_SHORT_3_4 DISABLE Control interrupts on detection of a short on any PDL_POE_IRQ_SHORT_3_4 ENABLE MTU channe
420. lag that has been set to 1 shall be automatically cleared to 0 by this function R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 248 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uintl6_t Counter uintl6_t CompareMatchA uintl6_t CompareMatchB void func void Read the status flags and registers for TMR unit 0 R_TMR_ReadUnit 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB R20UT1963EE0100 Rev 1 00 Page 249 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 4 2 19 Compare Match Timer 1 R_CMT_Create Synopsis Prototype Description Return value Configure a CMT channel bool R_CMT_Create uint8_t data1 Timer channel selection uint16_t data2 Configuration selection double data3 Period frequency or register data void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold e Clock calculation The parameter data3 will specify the timer period PDL_CMT_PERIOD or T
421. lator waiting times uint16_t data7 PLL waiting times Description 1 4 Load the registers that control module or CPU operation data1 Select the required settings If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Software and Deep Software Standby mode output port control PDL_LPC_EXT_BUS _ONor Leave the external bus address and control signals PDL_LPC_EXT_BUS_HI_Z active or set them to the high impedance state e 1 O port retention control PDL_LPC IO SAME or Select whether I O port retention is cancelled when deep software standby mode is ended or a aie namin when CPU operation has resumed e Operating power control PDL_LPC_HIGH_SPEED_MODE or PDL_LPC_LOW_SPEED_MODE_1 or Select the operating power control mode PDL_LPC_LOW_SPEED_MODE_2 Sleep mode return clock source switching PDL_LPC_SLEEP_RETURN_SWITCH_DISABLE or PDL_LPC_SLEEP_RETURN_SWITCH_HOCO or PDL_LPC_SLEEP_RETURN_SWITCH_MAIN Control clock source switching at cancellation of sleep mode Deep software standby control PDL_LPC_DEEPCUT_DISABLE or At deep software standby mode extra power PDL_LPC_DEEPCUT_RAM_USB or savings can be made by cutting the power to PDL_LPC_DEEPCUT_RAM_USB_LVD both RAM and USB or RAM USB and LVD R20UT1963EE0100 Rev
422. lected using PDL_RTC_UPDATE_CURRENT_TIME Select the date counters to be updated using values supplied in parameters data3 and data4 PDL_RTC_UPDATE_CURRENT_YEAR All four can be selected using PDL_RTC_UPDATE_CURRENT_MONTH PDL_RTC_UPDATE_CURRENT_DATE PDL_RTC_UPDATE_CURRENT_DAY Parameter data3 is used for the day of the PDL_RTC_UPDATE_CURRENT_DOW week e Select the alarm time counters to be updated using values supplied in parameter data5 PDL_RTC_UPDATE_ALARM_HOUR PDL_RTC_UPDATE_ALARM_MINUTE PDL_RTC_UPDATE_ALARM_SECOND All three can be selected using PDL_RTC_UPDATE_ALARM_TIME e Select the alarm date counters to be updated using values supplied in parameters data5 and data6 PDL_RTC_UPDATE_ALARM_YEAR All four can be selected using PDL_RTC_UPDATE_ALARM_MONTH PDL_RTC_UPDATE_ALARM_DATE PDL_RTC_UPDATE_ALARM_DAY Parameter data5 is used for the day of the PDL_RTC_UPDATE_ALARM_DOW week data3 The new day of the week and time Ignored if not selected above See R_RTC_Create for the format data4 The new year month and day Ignored if not selected above See R_RTC_Create for the format data5 The new alarm day of the week and time Ignored if not selected above See R_RTC_Create for the format data6 The new alarm year month and day Ignored if not selected above See R_RTC_Create for the format R20UT1963E
423. liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems tha
424. llback function static void Read_the_MCK void volatile bool mck_completed volatile uintl6_t system_clock_count define EXPECTED _F_ MAIN 12 define EXPECTED_F_HOCO 50 6 6 void main void uintl6_t reference_count double f_system_clock double f_reference_clock volatile double measured_frequency Configure the HOCO settings R_CGC_Set PDL_CGC_CLK_HOCO PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABL EXPECTED_F_HOCO EXPECTED_F_HOCO EXPECTED_F_HOCO D_ D_ F EXPEC F_HOCO EXPEC F_HOCO PDL_NO_DATA PDL_NO_DATA PDL_NO_ DATA Configure main clock operation R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABLI EXPECTED _F_MAIN EXPECTED _F_MAIN EXPECTED _F_MAIN EXPECTED _F_MAIN EXPECTED _F_MAIN PDL_NO_DATA PDL_NO_DATA PDL_NO_ DATA Select the HOCO as the system clock R_CGC_Control PDL_CGC_CLK_HOCO PDL_NO_DATA PDL_NO_DATA f_system_clock EXPECTED_F_HOCO Select the main clock as the reference clock for system 2 R_MCK_Control PDL_MCK_1_DISABLE PDL_MCK_2_REFERENCE_MAIN R20UT1963EE0100 Rev 1 00 AS Page 390 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples f_reference_clock EXPECTED_F_MAIN Se
425. lling this function In order to use the Vbatt back up mode for the sub clock it is necessary to use R_MCU_OFS to enable the LVD channel 0 Before calling this function check the LVD channel 0 detection flag Please refer to the example 5 15 4 R20UT1963EE0100 Rev 1 00 ztENESAS Page 261 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_rtc h RPDL device specific definitions include r_pdl_definitions h void alarm_function void void func void Configure the clock for an alarm at 12 noon every day Using default 24 hour mode R_RTC_Create PDL_RTC_COUNT_SOURCE_SUBCLK PDL_RTC_ALARM HOUR_ENABLE DL_RTC_ALARM MINUTE_ENABLE PDL_RTC_ALARM_ SECOND_ENABLE DL_NO_DATA xFF114200 Automatic day of week 11 42 00 100916 16 Sep 2010 DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA 120000 Alarm at 12 noon DL_NO_DATA x e WOU yo GIU iy X N e alarm_function 15 PDL_NO_FUNC PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 262 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_RTC_Destroy Synopsis Shut down the Real time clock Prototype bool R_RTC_Desiroy void Description Stop the RTC counter and disable the subclock to the RTC R
426. lse unit data The multi function timer pulse unit n where n 0 Unit 0 comprises channels 0 to 5 True if the unit selection is valid otherwise false Multi function Timer Pulse Unit None e The unit is put into the stop state to reduce power consumption include r_pdl_mtu2 h void func void Shutdown MTU2 channels 0 to 5 R_MTU2_Destroy 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 187 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 Synopsis Prototype Description 1 2 R_MTU2_ControlChannel Control an MTU channel bool R_MTU2_ConirolChannel uint8_t data1 Channel selection R_MTU2_ControlChannel_structure data2 A pointer to the structure R_MTU2_ControlChannel_structure members uint8_t control_setting Control settings uint16_t register_selection Register selection uint16_t TCNT_TCNTU_value Register value uinti6_t T RA_TCNTV_value Register value uint16_t T 4RB_TCNTW_value Register value uint16_t T RC_TGRU_ value Register value uint16_t T RD_TGRV_value Register value uint16_t T 4RE_TGRW_value Register value uint16_t TGRF_value Register value uint16_t TADCOBRA_value II Register value uint16_t TADCOBRB_value Register value Modify a timer channel s registers data1 The channel number n where n 0 to 5 control_setting The channel settings to be modified If multiple selections are req
427. ltaneously by the master and slave The received data is then checked to confirm that the transfer was successful Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_spi h PDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt void spi_slave_callback void volatile bool slave_transfer_complete define SLAVI EL 0 define MASTI EL 1 define BUFF H 25 const char master_data_to_be_sent SPI data to slave const char slave_data_to_be_sent SPI slave output void main void uint32_t master_tx_data BUFF uint32_t master_rx_data BUFF uint32_t slave_tx_data BUFFE uint32_t slave_rx_data BUFFE uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure SPI Pin R_SPI_Set SLAVE_CHANNEL PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSIA_PA6 PDL_SPI_MISOA_PAT7 PDL_SPI_SSLAO_PA4 PDL_NO_DATA i Configure SPI Pin R_SPI_Set MASTER_CHANNEL PDL_NO_DATA PDL_SPI_RSPCKB_PE5 PDL_SPI_MOSIB_P PDL_SPI_MISOB_P PDL_SPI_SSLBO_PE4 di Configure the master SPI channel R_SPI_Create MASTER_CHANNEL PDL_SPI_MODE_SPI_MASTER PDL_SPI_PIN_SSLO_LOW PDL_SPI_FRAME_1_1 PDL_NO_
428. me Clock R20UT1963EE0100 Rev 1 00 az AS Page 419 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 15 3 Using a Capture pin with the Real time Clock Figure 5 24 shows an example of using a capture pin with the Real time Clock Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h include r_pdl_definitions h void main void bool bDetected false uint8_t flags uint32_t time uint32_t date Initialise the system clocks NOTE The code to initialise the system clock using 4 2 1 1 is omitted here NOTE Ensure the Sub clock is enabled and stable before calling 4 2 20 1 Set the current time and enable the alarm R_RTC_Create PDL_RTC_COUNT_SOURCE_SUBCLK L_RTC_24 HOUR_MODE L_RTC_PIN_RTCIC1_P31 114250 Automatic day of week 11 42 50 101118 18 Nov 2010 L_NO_DATA RTC_CAPTURE_EDGE_ FALLING RTC_CAPTURE_FILTER_ON_DIV_1 Capture 1 DATA DATA A OOD x x N Fy oF P P 0 0 P P U vouUTUUTONN asl cle eal Wakes ea while 1 Read Capture status until see that an edge has been detected R_RTC_Read PDL_RTIC_READ_CAPTURE_1 amp flags amp time amp date if 1l flags amp BIT_O bDetected true NOTE Variables time and date now hold the time when the edge was
429. meters are valid and exclusive otherwise false Watchdog Timer R_WDT_Set Remarks e R_WDT_Set must be called first to configure the timer unless using Initial Setting Memory Program example using R_MCU_OFS to enable the WDT from reset RPDL definitions include r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h void func void Prevent the watchdog timer from overflowing R_WDT_Control PDL_WDT_RESET_COUNTER R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 273 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_WDT_Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read the Watchdog timer status bool R_WDT_Read uint16_t data A pointer to the data storage location Read and store the status flags and current counter value data The timer status shall be stored in the following format b15 b14 b13 b0 Refresh Error Flag Underflow Flag 1 Refresh error 1 Underflow Down Counter Value 0 No underflow 0 No refresh error True Watchdog Timer If the Underflow flag is set to 1 it shall be automatically cleared to 0 by this function e Ifthe Refresh flag is set to 1 it shall be automatically cleared to O by this function RPDL definitions incl
430. module providing the following operations 1 Configuring and enabling the Temperature Sensor 2 Disabling the Temperature Sensor and enabling low power mode 3 Controlling the A D conversion R20UT1963EE0100 Rev 1 00 Page 49 of 487 Jul 19 2012 RENESAS RX63N Group 3 Types and definitions 3 Types and definitions 3 1 Data types This section describes the data types used in this library For details about the setting values refer to the section 4 2 Description of Each API The header files stdint h and stdbool h are included with the Renesas RX compiler Table 1 Data types Type Defined in Description Range bool stdbool h Boolean 0 false to 1 true double C Floating point 64 bits uint8_t Unsigned 8 bits 0 to 255 uint16 t stdint h Unsigned 16 bits 0to2 1 int32_t i Signed 32 bits 2 to 27 1 uint32_t Unsigned 32 bits 0 to 27 1 3 2 General definitions 3 2 1 PDL_NO_FUNC Used as a parameter when there is no applicable function 3 2 2 PDL_NO_PTR Used as a parameter when there is no applicable data location 3 2 3 PDL_NO_DATA Used as a parameter when there is no applicable data value 3 2 4 PDL_MCU_GROUP The MCU group supported by this build of the driver library It is defined as RX63N A usage example is if PDL_MCU_GROUP RX63N error Wrong RPDL fendif 3 2 5 PDL_VERSION The version number of the RPDL library The number is stored
431. mpare match on MTU channel n n 0 to 4 PDL_DMAC_TRIGGER_IICO_RX or PDL_DMAC_TRIGGER_IIC1_RX or PDL_DMAC_TRIGGER_IIC2_RX or PDL_DMAC_TRIGGER_IIC3_RX or Receive buffer full on I2C channel n n 0 to 3 PDL_DMAC_TRIGGER_IICO TX or PDL_DMAC_TRIGGER_IIC1_TX or PDL_DMAC_TRIGGER_IIC2_TX or PDL_DMAC_TRIGGER_IIC3_TX or Transmit buffer empty on I C channel n n 0 to 3 R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 146 of 487 RX63N Group 4 Library Reference Description 3 3 PDL_DMAC_TRIGGER_SCIO_RX or PDL_DMAC_TRIGGER_SCI1_RX or PDL_DMAC_ TRIGGER _SCI2_ RX or PDL_DMAC TRIGGER SCI3_RX or PDL_DMAC_TRIGGER SCI4_RX or PDL_DMAC_TRIGGER SCI5 RX or PDL_DMAC_TRIGGER_SCI6_RX or PDL_DMAC TRIGGER SCI7_RXor PDL_DMAC_TRIGGER_SCI8_RX or PDL_DMAC_ TRIGGER SCI9_ RX or PDL_DMAC_TRIGGER_SCM0_RXor PDL_DMAC_TRIGGER_SCI11_RX or PDL_DMAC TRIGGER SCI12_RXor PDL_DMAC_ TRIGGER SCIO_TXor PDL_DMAC_TRIGGER_SCI1_TXor PDL_DMAC_ TRIGGER SCI2_TX or PDL_DMAC_TRIGGER_SCI3_TX or PDL_DMAC TRIGGER SCI4_TXor PDL_DMAC_TRIGGER_SCI5_TX or PDL_DMAC TRIGGER SCI6_TXor PDL_DMAC_ TRIGGER SCI7 TXor PDL_DMAC_TRIGGER_SCI8_1X or PDL_DMAC TRIGGER SCI9_TXor PDL_DMAC_TRIGGER_SCI10_TX or PDL_DMAC TRIGGER _SCI11_TX or PDL_DMAC_TRIGGER_SCI12_TX Receive buffer full on SCI channel n n 0 to 12
432. mpleted The timing limits depend on the peripheral module clock PCLKB fecike MHZ Equation 50 48 12 5 12 32 8 Twin a 160ns 166 67ns 640ns 666 67ns 250ns ius focix 9 Tmax 671ms 699ms 2 68s 2 79s 1 05s 4 19s Jock e If the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period RPDL definitions include Yr pdl cmth RPDL device specific definitions r pdl_definitions h include void func void Use CMT channel 0 for a lms pause R_CMT_CreateOneShot 0 PDL_NO_DATA 1E 3 PD 0 L_NO_FUNC R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 253 of 487 RX63N Group 4 Library Reference 3 R_CMT_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a CMT unit bool R_CMT_Destroy uint8_t data Unit selection Shut down a CMT unit data The timer unit n where n 0 or 1 Unit 0 comprises channels CMTO and CMT1 Unit 1 comprises channels CMT2 and CMT3 True if the unit selection is valid otherwise false Compare Match Timer R_CMT_Create The timer unit is put into the stop state to reduce power consumption RPDL definitions include r_pdl_cmt h RPDL device specifi
433. munication mode e Reception control PDL_IEB_RX_ENABLE or PDL_IEB_RX_DISABLE Enable or disable reception e Input Output polarity control PDL_IEB_POLARITY_LOW or PDL_IEB_POLARITY_HIGH Select active low or active high polarity e Digital filter control PDL_IEB_FILTER_IECLK_DIV_1 or PDL_IEB_FILTER_IECLK_DIV_2 or PDL_IEB_FILTER_IECLK_DIV_3 or PDL_IEB_FILTER_IECLK_DIV_4 or PDL_IEB_FILTER_DISABLE Disable or enable the digital filter using the IEBus clock IECLK 1 2 3 or 4 Reset control PDL_IEB_RESET_ENABLE or PDL_IEB_RESET DISABLE Enable or disable the IEBus module reset signal e Slave state control PDL_IEB_SLAVE_TX_HALTED or Set the slave transmission status bit in the slave PDL_IEB_SLAVE_TX_ENABLED status e Broadcast receive error interrupt control PDL_IEB_BROADCAST_ERROR_ENABLE or Enable or disable interrupts due to PDL_IEB_BROADCAST_ERROR_DISABLE broadcast reception errors e Internal command control PDL_IEB_CANCEL_LOCK or Cancel the lock required from other units not applicable in slave operation PDL_IEB_CANCEL_TRANSFER Stop the current transfer e Unit address update control PDL_IEB_UPDATE_ADDRESS Replace the unit address using parameter data3 data3 The unit address valid from 0000h to OFFFh True if all parameters are valid otherwise false IEBus R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 348
434. n The RPDL folder contains a header file iodefine_RPDL h This file is included by the RPDL source files and will also be included by any user generated files that call RPDL functions The main HEW project folder may contain the header file iodefine h This file is normally used if access to the I O registers in the MCU is required For any user generated files that call RPDL functions there is no need to include this file iodefine h 1 2 4 Header file order The file r_pdl_definitions h must be included after any peripheral specific header file For example Peripheral driver function prototypes and definitions include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h 1 2 5 Recommended initialisation code The RX tool chain has a designated function for MCU initialisation HardwareSetup During the MCU initialisation phase it is recommended that the following functions are placed in this function Note that the file resetprg c supplied when a new project is created requires editing to remove the comment identifiers for the two lines below extern void HardwareSetup void HardwareSetup 1 Initialisation of pins that are not available For pins that are not available on the selected MCU package type set the control registers to the recommended values using R_IO_PORT_NotAvailable j This function can be called even if the largest device has
435. n complementary PWM mode PDL_MTU2_ADC_TRIG_A_TROUGH_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_A TROUGH_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnAN on a TCNT underflow PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnBN on a TCNT underflow PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnAN on a TGRA compare match PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnBN ona TGRA compare match Control ADC triggers Valid for n 4 in complementary PWM mode unless stated otherwise PDL_MTU2_ADC_TRIG_A_DOWN_DISABLE or PDL_MTU2 ADC TRIG A DOWN ENABLE requests during down count operation PDL_MTU2_ADC_TRIG_B_DOWN_DISABLE or PDL_MTU2 ADC TRIG_B DOWN ENABLE Disable or enable ADC trigger TRGnAN Disable or enable ADC trigger TRGnBN requests during down count operation PDL_MTU2_ADC_TRIG_A_UP_DISABLE or PDL_MTU2_ADC_TRIG_A UP_ENABLE Disable or enable ADC trigger TRGnAN requests during up count operation This option can be selected in other modes PDL_MTU2_ADC_TRIG_B_UP_DISABLE or PDL_MTU2 ADC TRIG_B UP ENABLE Disable or enable ADC trigg
436. n selection uint16_t data2 II RFC cycles uint8_t data3 II REFW cycles uint8_t data4 II ARFI cycles uint8_t data5 ARFC count uint8_t data6 II PRC cycles uint8_t data7 II CL cycles uint8_t data8 WR cycles uint8_t data9 RP cycles uint8_t data10 RCD cycles uint8_t data11 II RAS cycles uint16_t data12 SDRAM mode Description 1 2 Set up the SDRAM area data1 Configure the operation of SDRAM area If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e SDRAM bus width PDL_BSC_SDRAM_WIDTH_16 or PDL_BSC_SDRAM_WIDTH_8 or Select 16 bit 8 bit or 32 bit data bus width PDL_BSC_SDRAM WIDTH 32 Endian mode PDL_BSC_SDRAM_ENDIAN_SAME or Set the bus endian mode to be the same or PDL_BSC_SDRAM _ENDIAN OPPOSITE _ opposite to that of the CPU e Continuous access mode PDL_BSC_SDRAM_CONT_ACCESS DISABLE or Disable or enable Continuous PDL_BSC_ SDRAM CONT ACCESS ENABLE Access e Address multiplex selection PDL_BSC_SDRAN_8_BIT_SHIFT or PDL_BSC_SDRAM_9_BIT_SHIFT or Select the size of shift in address multiplexing PDL_BSC_SDRAM_10_BIT_SHIFT or 8 bit shift 9 bit shift 10 bit shift or 11 bit shift PDL_BSC_SDRAM_11_BIT_SHIFT data2 The value to be set to RFC bits in SDRAM Refresh Control Register SDRFCR Valid betwe
437. nclude r_pdl_definitions h void func void uint32_t transmit_data 8 uint32_t receive _data 8 Transmit and receive all enabled frames once R_SPI_Transfer 0 PDL_NO_DATA transmit_data receive_data 1 PDL_NO_FUNC 0 PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 334 of 487 Jul 19 2012 RX63N Group 4 Library Reference 6 R_SPI_Conirol Synopsis Prototype Description Return value Category Control an SPI channel bool R_SPI_Control uint8_t data1 uint8_t data2 uint32_t data3 Channel selection Control options Extended timing control Modify the operation of the selected SPI channel data1 Select channel SPIn where n 0 1 or 2 data2 Control the channel If multiple selections are required use to separate each selection All items are optional Specify PDL_NO_DATA if not required Channel control PDL_SPI_DISABLE Disable and partially initialise the SPI channel e Loopback control PDL_SPI_LOOPBACK_DISABLE or PDL_SPI_LOOPBACK_DIRECT or PDL_SPI_LOOPBACK_REVERSED Disable or enable loopback in direct or reversed mode data3 Extended timing control optional All items apply only to Master mode Specify PDL_NO_DATA if not required If multiple selections are required use to separate each selection e Extended clock delay PDL_SPI
438. nd func2 Return value True if all parameters are valid and exclusive otherwise false Category Port Output Enable Reference R_POE_Set R_POE_GetStatus Remarks e Use R_POE_GetStatus to determine the interrupt cause e Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT1963EE0100 Rev 1 00 ae ENESAS Page 202 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void POEO_handler void void func void Assign the callback function for pin POEO R_POE_Create PDL_POE_IRQ_HI_Z_0_3_ENABLE POEO_handler PDL_NO_FUNC 1 R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 203 of 487 RX63N Group 4 Library Reference 3 R_POE_Control Synopsis Prototype Description Control the Port Output Enable module bool R_POE_Conitrol uint8_t data1 Control options uint16_t data2 Control options uint8_t data3 Control options Change the state of output pins status flags and interrupt control data1 Manual high impedance control If multiple selections are required use to separate each selection Al
439. nda tee ed eee ee a 396 5 7 1 Extemali bUSs CS area a csai nenn a ct r echoes estas daa nin Gi tev abd ae tases A aaa 396 5 7 2 Extemalbus SDRAM aed kinrara a ivewstacaenasittuder sd aateasaanedads 400 5 8 DMA controllen i earen e e e atid fae Pee ie tte ed ido fee eet eet eet 402 5 9 Data Transfer Controler p ripirii dirie aei rates deevne aaaea steed ladee deve dd ANKE raa naaa canned aes 405 5 9 1 Block transfer Mde isinsin dein tenes sabe ceeds aeu et hae sede ead San De ae daaa iaaa ae ge danas angela 405 5 9 2 Chain transfer Operation c ccccceceeeeeeeeceeceee cess eecacaeeeeeeeeeccaaeaeeeeeeeseseceaeeeeeeeseneenaneeeeeeeteees 407 510 Port Output Enable iini ied esl ieee eira a adel id aed Ries el bed 409 51 s Timer Pulse T E ises ease aati eas tere ieee ha Sie eae aa te 410 5 12 Watchdog TIMEN reoaine sages eA sha cdetesageeacksadeaetead ene chshacdes a adaeetsaaeee TA RATAA iene 412 513s JO DIt DA EIEEE E E E E es eal eae cel E A E okt veda accel ag bhe aia 413 551321 Perodic Operai O a aa a e sects apsaeateddlectesades eld decbelattaelded Stacie dba steesds lecbe ll taate a 413 5 14 Compare Match Timer assent ae te ieee atid ater te a a aed ate ates ta ieee 415 Holos Realtime ClOCK 2casnate ssh EA EEE E te eg ane snabe a tauea soe E A E ieee 417 5 15 1 Enabling the Sub clock using R_CGC_COomtrol eeccceeeeeeeeeeeeeneeeeeenneeeeeenaeeeeeenaeeeeeenaeeeeeeaas 417 5 15 2 Running from the Sub clock bef
440. ndlers PDL_NO_FUNC PDL_NO_FUNC UndefinedInstruction PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 71 of 487 Jul 19 2012 RX63N Group 4 Library Reference 6 R_INTC_ControlExtInterrupt Synopsis Prototype Description Return value Category Reference External interrupt control bool R_INTC_ConitrolExtinterrupt uint8_t data1 uint32_t data2 Control Modifies the specified external interrupt data1 Pin selection Choose the interrupt pin to be controlled PDL_INTC_IRQn n 0 to 15 or PDL_INTC_NMI IRQn interrupt pin or NMI interrupt pin data2 Select the controls If multiple selections are required use to separate each selection e Enable or disable the interrupt pin for the IRQ pins PDL_INTC_ENABLE or PDL_INTC_DISABLE Enable or disable the IRQn interrupt pin e Digital filter selection PDL_INTC_FILTER_DISABLE or PDL_INTC_FILTER_DIV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC_FILTER_DIV_64 Disable the filter or select PCLKB divided by 1 8 32 or 64 Detection sense selection for the IRQ pins PDL_INTC_LOW or PDL_INTC_FALLING or PDL_INTC_RISING or PDL_INTC_BOTH Select Low level Falling edge Rising edge or Falling and rising edge detection e Interrupt request clearing PDL_INTC_CLEAR_IR_F
441. ng again bStartMonitor true Has the master just completed a read else if tx_count 0 Increment the current index by the amount the master read data_storage_index tx_count Start monitoring again bStartMonitor true Is the master starting a read Check this by seeing if in transmit mode else if 0 status_flags amp BIT_6 Send data to master based on current address R_IIC_SlaveSend SLAVE_CHANNEL amp data_storage data_storage_index uint1l6_t STORAGE_SIZE data_storage_index Don t start monitoring again until the R_IIC_SlaveSend completes bStartMonitor false if true bStartMonitor Continue monitoring R_IIC_SlaveMonitor SLAVE_CHANNEL PDL_NO_DATA Rx_Buffer RX_BUFFER_SIZE slave_callback 7 The master has sent us data now in the Rx_Buffer store it in the data_storage array static void StoreData uintl6_t count uintl6_t index 0 Update data_storage_index data_storage_index Rx_Buffer index count index Store any data while count 0 R20UT1963EE0100 Rev 1 00 Page 459 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples data_storage data_storage_index Rx_Buffer index count index data_storage_indext if data_storage_index STORAGE Wrap around data_storage_index
442. nnel 11 Returnvalue True if all parameters are valid and exclusive otherwise false Category Interrupt control References R_MTU2 Create Remarks e The selection register is modified as required by the MTU and TPU Create functions Do not use this function if RPDL functions will be used to configure the MTU or TPU Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Select interrupts from MTU channel 1 and TPU channel 11 R_INTC_Control PDL_INTC_SEL_MTU1 PDL_INTC_SEL_TPU11 R20UT1963EE0100 Rev 1 00 R Page 88 of 487 Jul 19 2012 2 XENESAS RX63N Group 4 Library Reference
443. nsfer PDL_DTC TRIGGER SW or By software PDL_DTC_ TRIGGER CMTO or PDL_DTC_TRIGGER_CMT1 or PDL_DTC_TRIGGER_CMT2 or PDL_DTC_TRIGGER_CMT3 or PDL_DTC_TRIGGER_USBO_DOFIFOO or PDL DTC TRIGGER USBO_D1FIFOO or Compare match on channel CMTn n 0 to 3 FIFO interrupt from USBO PDL_DTC_ TRIGGER _USB1_DOFIFO1 or PDL_DTC_TRIGGER_USB1_D1FIFO1 or FIFO interrupt from USB1 R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 165 of 487 RX63N Group 4 Library Reference Description 2 4 PDL_DTC_TRIGGER_SPIO_RX or R20UT1963EE0100 Rev 1 00 Jul 19 2012 PDL_DTC_ TRIGGER SPI1_RXor PDL_DTC TRIGGER SPI2_RXor Receive buffer full on SPI channel n n 0 to 2 PDL_DTC_TRIGGER_SPIO_TXor PDL_DTC_ TRIGGER SPI1_TXor PDL_DTC TRIGGER SPI2_ TX or PDL_DTC_TRIGGER_IRQO or PDL_DTC_TRIGGER_IRQ1 or PDL_DTC_TRIGGER_IRQ2 or PDL_DTC_TRIGGER_IRQ3 or PDL_DTC_TRIGGER_IRQ4 or PDL_DTC_TRIGGER_IRQ5 or PDL_DTC_TRIGGER_IRQ6 or PDL_DTC_TRIGGER_IRQ7 or PDL_DTC_TRIGGER_IRQ8 or PDL_DTC_TRIGGER_IRQQ or PDL_DTC_TRIGGER_IRQ10 or PDL_DTC_TRIGGER_IRQ11 or PDL_DTC_TRIGGER_IRQ12 or PDL_DTC_TRIGGER_IRQ13 or PDL_DTC_TRIGGER_IRQ14 or PDL_DTC_TRIGGER_IRQ15 or Transmit buffer empty on SPI channel n n 0 to 2
444. nt8_t data_received volatile uint8_t error_happen volatile uint8_t receive_data NUM_DATA void main void wintst i bool id_received Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA i 0 i lt NUM_DATA i receive_data i 0 Set pin options R_SCI_Set 9 PDL_SCI_PIN_SCI9_TXD9_PB7 PDL_SCI_PIN_SCI9_RXD9_PB6 i Configure the RS232 port specify Async MP mode R_SCI_Create 9 PDL_SCI_8N1 PDL_SCI_ASYNC_MP 57600 Async MP mode data Reception by CPU ISR data_received fals error_happen false Wait by CPU ISR until receive matching Station ID 0x0A R_SCI_Receive 9 R20UT1963EE0100 Rev 1 00 Page 433 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 0x0A00 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 SCIrx SCIEr while data_received false data_received false Receive data ID 0x0A by CPU ISR R_SCI_Receive 9 PDL_NO_DATA receive_data 10 SCIrx SCIEr i while data_received false 0 ee ee ee Async MP mode data Reception by polling De ee ee id_received false Wait by polling until receive matching Station ID 0x01
445. nternal command execution Master communication Slave communication 0 Idle 0 Idle Transmission Reception 1 Active 1 Active 0 Idle 0 Idle i 1 Active 1 Active b3 b2 b1 bO Communication type General broadcast m e 0 0 Broadcast 0 None 1 Normal 1 Detected data3 The Transmit status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b7 b6 b5 b4 Master address Completion 0 0 Not sent 0 Not occurred 0 1 Sent 1 Occurred b3 b2 b1 bO Arbitration loss Timing error Overflow Acknowledge 0 Not occurred 0 Not occurred 0 Not occurred 0 NAK not detected 1 Occurred 1 Occurred 1 Occurred 1 NAK detected R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 350 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example data4 The Receive status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b31 b24 b23 b16 0 The received message length b1i5 b12 b11 b8 0 The received command valid only in slave or broadcast reception b7 b6 b5 b4 Busy Reception Normal completion Broadcast error 0 Data is not ready 0 Not started 0 Not occurred 0 Not occurred 1 Data is ready 1 Started 1 Occurred 1 Occurred b3 b2 b1 bO Overrun Timing error Overflow Parity error 0 No
446. nterrupt sources 12 Controlling a group of interrupt sources 13 Reading the status of a group of interrupt sources 14 Choosing the timer source for shared interrupts R20UT1963EE0100 Rev 1 00 EN ESAS Page 20 of 487 Jul 19 2012 RX63N Group 2 Driver 2 5 1 O Port Driver The driver functions support the use of the I O port pins providing the following operations Configuration for use 2 Reading the pin or port configuration 3 Modifying the pin or port configuration 4 Reading a pin or 8 bit port value 5 Writing to a pin or 8 bit port 6 Comparing a pin or 8 bit port with a supplied value 7 Modifying a pin or 8 bit port using a logical operation 8 Waiting until a pin or 8 bit port matches a supplied value 9 Configuring the pins that are not available on smaller packages to the required state R20UT1963EE0100 Rev 1 00 Page 21 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 6 Multifunction Pin Controller Driver The driver functions support access to the Multifunction Pin Controller MPC registers which select the mode of operation for some I O pins The other driver functions modify the MPC registers automatically For peripherals that are not supported by the driver library these functions support 1 Reading from an MPC register 2 Writing to an MPC register 3 Modifying an MPC register R20UT1963EE0100 Rev 1 00 Page 22 of 487 Jul 19 2012 RENESAS RX63N Group 2 Dr
447. o not care 0 to3 Port not open drain control b15 b8 b7 b1 Do not care Register Port open drain control b15 b8 b7 b0 Register ODR1 Register ODRO Return value True if all parameters are valid and exclusive otherwise false Category I O port References None Remarks Ensure that the specified functions are valid for the selected port pin e The data direction and mode registers may be modified by other driver Create functions Take care to not overwrite existing settings e Pin P35 is fixed as an input and cannot be modified R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 94 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the lower 4 bits on port P1 to output R_IO_PORT_ModifyControl PDL_IO PORT 1 PDL_IO_PORT_DIRECTION Ox0F PDL_IO_PORT_OR Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL_IO_PORT_A_ 3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR 1 R20UT1963EE0100 Rev 1 00 AS Page 95 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 4 RIO PORT Read Synopsis Prototype Description Return value Read data from an I O port bool R_IO_PORT_Read uint16_t data1 Port or port pin selection uint8_t data2
448. odified to set the pin as an input e Apin can be used both as an interrupt input and a peripheral or general purpose input or output apart from an analog input If the dual operation is required call this function before configuring the peripheral or I O port operation Some pin options are not available on smaller device packages Some IRQ pins labelled in the hardware manual with the suffix DS can also be used to exit from Deep Software Standby mode Please refer to the Low Power Consumption section for details RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Select P30 for IRQO P31 for IRQ1 and P42 for IRQ10 R_INTC_SetExtInterrupt PDL_INTC_IRQO_PORT_3_0 PDL_INTC_IRQ1_PORT_3_1 PDL_INTC_IRQ10_PORT_4 2 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 63 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_INTC_CreateExiInterrupt Synopsis Prototype Description 1 2 Configure an external interrupt signal bool R_INTC_CreateExtInterrupt II Signal selection Configuration II Callback function Interrupt priority level uint8_t data1 uint32_t data2 void func uint8_t data3 Sets the specified interrupt detection and control data1 Choose the interrupt signal to be configured PDL_INTC_IRQn n 0 to 15 or PDL_INT
449. of the voltage detection module Frequency Measurement 1 R_MCK_Control Configure the frequency measurement circuit Circuit 1 R_LPC_Create Configure the MCU low power conditions Low Bower 2 R_LPC_Control Select a low power consumption mode Consumption 3 R_LPC_WriteBackup Write to the Backup registers 4 R_LPC_ReadBackup Read from the Backup registers 5 R_LPC_GetStatus Read the status flags Register Write 1 R_RWP_Control Control register write protection Protection 2 R_RWP_GetStatus Get the status of the register protection 1 R_BSC_Set Configure the internal bus operation 2 R_BSC_Create Configure the external bus controller 3 R_BSC_CreateArea Configure an external bus area Bus Controller 4 R_BSC_Destroy Stop the Bus Controller 5 R_BSC_ Control Modify the External Bus Controller operation 6 R_BSC_SDRAM _CreateArea Configure the SDRAM area 7 R_BSC_GetStatus Read the External Bus Controller status flags R20UT1963EE0100 Rev 1 00 RENESAS Page 51 of 487 Jul 19 2012 RX63N Group 4 Library Reference DMA Controller R_DMAC Create Configure the DMA controller R_DMAC_ Destroy Disable a DMA channel R_DMAC_ Control Control the DMA controller R_DMAC_GetStatus Check the status of the DMA channel External DMA Controller R_EXDMAC_Set Configure the EXDMAC pins R_EXDMAC_ Create Configure the EXDMA controller R_EXDMAC_Destroy Disable the EXDMA controller
450. oid main void Data Buffer volatile uint8_t IIC_Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set Channel 2 pin options R_SCI_Set 2 PDL_SCI_PIN_SCI2_SSCL2_P12 PDL_SCI_PIN_SCI2_SSDA2_P13 Configure the SCI IIC Channel R_SCI_Create CHANNEL _SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 1 0 Setup data to write to EEPROM Address in EEPROM TIC_Buffer 0 EEPROM_ADDRESS Data to store in EEPROM TIc_Buffer 1 1 ITIc_Buffer 2 TIC_Buffer 3 4 5 yf IIC_Buffer IIC_Buffer r f Setup DMAC to write data to IIC Configure channel 3 of DMAC to be triggered by SCI2 Tx R_DMAC_Create 3 PDL_DMAC_REPEAT PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_FIXED PDL_DMAC_SIZE_8 PDL_DMAC_IRQ_ PDL_DMAC_TRIGGER_SCI2_TX IIC_Buffer Source uint8_t amp SCI2 IDR Dest R20UT1963EE0100 Rev 1 00 AS Page 441 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 1 6 Data length Address in EEPROM 5 Data PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Callback Callback done function 7 Interrupt priority Enable DMAC channel 3
451. onfigure area 1 R_BSC_CreateArea 1 PDL_BSC_WIDTH_8 PDL_BSC_WRITE_BYTE 0 sw NNN oN ONS oO OO OC OOo 0 0 0 0 0 0 i Configure area 2 R_BSC_CreateArea 2 PDL_BSC_WIDTH_16 PDL_BSC_WRITE_SINGLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r Configure area 3 R_BSC_CreateArea 3 R20UT1963EE0100 Rev 1 00 AS Page 397 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples PDL_BSC_WIDTH 16 LS LS Ty Ty 31 3L 7 T LA D S e ES E S a Configure area CS7 R_BSC_CreateArea 7 PDL_BSC_WIDTH_32 i5 15 7 7 31 Configure the bus controller R_BSC_Create PDL_BSC_CSO_P60 PDL_BSC_CS1_PC6 PDL_BSC_CS2_P62 PDL_BSC_CS3_P63 PDL_BSC_CS7_P67 PDL_BSC_WAIT_P55 PDL _BSC_ALE ENABLE PDL_BSC_A9 DISABLE PDL_BSC_A23_A16 DISABLE PDL_BSC_RCV_SRRS_ENABLE PDL _BSC_ERROR_ILLEGAL_ ADDRESS ENABLE PDL_BSC_ERROR_TIME _OUT_ENABLE BSC_error_handler 5 i Enable the bus controller R_BSC_Control PDL_BSC_ENABLE Write to external areas xcs0_location_8 0x23u xcsl_location_8 OxAAu xcs2_location_16 0x3344u xcs3_location_16 0xAA55u cs7_location_32 0x12345678u Disable area CS1 R_BSC_Destroy 1 R20UT1963EE0100 Rev 1 00 AS
452. oose the pin settings The default setting is shown in bold e DTC trigger control PDL_INTC_DTC_SW_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_INTC_DTC_SW_TRIGGER_ENABLE when a software interrupt is generated func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no interrupt is required data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid otherwise false Interrupt control R_INTC_Write Remarks Program example e Please see the notes on callback function use in 6 Specifying PDL_NO_FUNC for the callback function allows the software interrupt to be used as a DTC trigger e Use R_INTC_Write to generate the software interrupt RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Configure the software interrupt handler R_INTC_CreateSoftwareInterrupt PDL_NO_DATA CallBackFunc 7 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 66 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_INTC_CreateFasiinterrupt Synopsis Prototype Description 1 4 Enable faster
453. opsis Prototype Description Return value Category Reference Remarks Program example Read the watchdog timer status and counter bool R_IWDT_Read uint16_t data A pointer to the data storage location Read and store the status flags and current counter value data The timer status shall be stored in the following format b15 b14 b13 b0 Refresh Error Underflow 0 No refresh error 0 No underflow 1 Refresh error 1 Underflow Down Counter Value True Independent Watchdog Timer None Ifthe Underflow flag is set to 1 it shall be automatically cleared to 0 by this function e Ifthe Refresh flag is set to 1 it shall be automatically cleared to 0 by this function RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h uintl6_t Status void func void Read the timer status R_IWDT_Read amp Status R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 278 of 487 RX63N Group 4 Library Reference 4 2 23 1 R_SCI Set Synopsis Prototype Description 1 5 Serial Communication Interface Configure the SCI pin selection for SCI channels where there is a choice of SCI pins bool R_SCI Set uint8_t data1 uint16_t data2 Channel selection II 1 0 configuration for channels 0 to 12
454. opsis Prototype Description 1 2 Configure a timer TMR channel bool R_TMR_CreateChannel uint8_t data1 Channel selection uint32_tdata2 Configuration selection uint8_t data3 Configuration selection uint8_t data4 Register value uint8_t data5 Register value uint8_t data6 Register value void func1 Callback function void func2 Callback function void func3 Callback function uint8_t data7 Interrupt priority level Set up an 8 bit timer TMR channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Counter clock source selection PDL_TMR_CLK_OFF or PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or PDL_TMR_CLK EXT BOTH or The clock input is disabled The external clock signal TMCIn is used Select rising falling or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 or The internal clock signal PCLKB 1 2 8 32 64 1024 or 8192 PDL_TMR_CLK_TMR1_OVERFLOW or PDL_TMR_CLK_TMR3_OVERFLOW or The overflow signal from TMR n 1 Valid for n
455. or PDL_DTC_TRIGGER_RXI1 or PDL_DTC_TRIGGER_RXI2 or PDL_DTC_TRIGGER_RXI8 or PDL_DTC_TRIGGER_RXI4 or PDL_DTC_ TRIGGER RXI5 or PDL_DTC_ TRIGGER RXI6 or PDL_DTC_TRIGGER_RXI7 or PDL_DTC_TRIGGER_RXI8 or PDL_DTC_TRIGGER_RXI9 or PDL_DTC_TRIGGER_RXI10 or PDL_DTC_TRIGGER_RXI11 or PDL_DTC_TRIGGER_RXI12 or Transfer complete on EXDMAC channel n n 0 or 1 Receive buffer full on SCI channel n n 0 to 12 PDL_DTC_TRIGGER_TXIO or PDL_DTC_TRIGGER_TXI1 or PDL_DTC_TRIGGER_TXI2 or PDL_DTC_TRIGGER_TXI3 or PDL_DTC_TRIGGER_TXI 4 or PDL_DTC_TRIGGER_TXI5 or PDL_DTC_TRIGGER_TXI6 or PDL_DTC TRIGGER TXI7 or PDL_DTC TRIGGER TXI8 or PDL_DTC_TRIGGER_TXI9 or PDL_DTC_TRIGGER_TXI10 or PDL_DTC_TRIGGER_TXI11 or PDL_DTC_ TRIGGER TXI12 Transmit buffer empty on SCI channel n n 0 to 12 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 167 of 487 RX63N Group 4 Library Reference Description 4 4 Return value Category Reference Remarks Program example data2 The start address of the transfer data area It must be a multiple of 4 For short address mode 12 bytes are required to store the transfer data For full address mode 16 bytes are required data3
456. or PDL_MTU2_BDCM_OPS_000 or PDL_MTU2_BDCM_OPS_001 or PDL_MTU2_BDCM_OPS_010 or PDL_MTU2_BDCM_OPS_011 or PDL_MTU2_BDCM_OPS_100 or PDL_MTU2_BDCM_OPS_101 or PDL_MTU2_BDCM_OPS_110 or PDL_MTU2_BDCM_OPS_111 Set the outputs according to table 23 39 in the hardware manual R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 193 of 487 RX63N Group 4 Library Reference Description 4 4 general_control General control settings All settings are optional If multiple selections are required use to separate each selection Interrupt skipping control PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 INT_SKIP_TROUGH_DISABLE or INT_SKIP_TROUGH_1 or INT_SKIP_TROUGH_2 or INT_SKIP_TROUGH_3 or INT_SKIP_TROUGH_4 or INT_SKIP_TROUGH_5 or INT_SKIP_TROUGH_6 or INT_SKIP_TROUGH_7 Disable TCNT underflow TCIV interrupt skipping or set the skip count between 1 and 7 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 PDL_MTU2 INT_SKIP_CREST_DISABLE or INT_SKIP_CREST_1 or INT_SKIP_CREST_2 or INT_SKIP_CREST_3 or INT_SKIP_CREST_4 or INT_SKIP_CREST_5 or INT_SKIP_CREST_6 or INT_SKIP_CREST_7 Disable TGRA compare match TGIA interrupt skipping or set the skip count between 1 and 7 Dead time generation control applies only to complementar
457. or PDL_IIC_INT_PCLK_DIV_2 or PDL_lIC_INT_PCLK_DIV_4 or PDL_lIC_INT_PCLK_DIV_8 or PDL_lIC_INT_PCLK_DIV_16 or PDL_lIC_INT_PCLK_DIV_32 or PDL_lIC_INT_PCLK_DIV_64 or PDL_lIC_INT_PCLK_DIV_128 The reference clock source derived from PCLKB used inside the l C module Timeout detection control PDL_lIC_TIMEOUT_DISABLE or PDL_IIC_TIMEOUT_LOW or PDL_IIC_TIMEOUT_HIGH or PDL_lIC_TIMEOUT BOTH Disable timeout detection or enable for SCL stuck ata low level high level or both low and high level Timeout mode PDL_IIC_TIMEOUT_LONG or PDL_IIC_TIMEOUT_ SHORT Select 16 bit long or 14 bit short mode SDA output delay count PDL_IIC_SDA_DELAY_0or PDL_IIC_SDA_DELAY_1 or PDL IIC SDA DELAY 2 or PDL IIC SDA DELAY 3 or PDL IIC SDA DELAY 4 or PDL_IIC_SDA_DELAY 5 or PDL IIC SDA DELAY 6 or PDL _IIC_SDA_DELAY 7 Select the number of cycles for the SDA output delay counter SDA output delay clock source PDL IIC_SDA DELAY _DIV_1 or PDL_lIC_SDA_DELAY_DIV_2 Select the clock source internal reference clock 1 or 2 for the SDA output delay counter R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 308 of 487 RX63N Group 4 Library Reference Description 2 3 e Noise filter control PDL_IIC_NF_DISABLE or PDL_IIC_NF_1 or PDL_IIC_NF_2 or Select the number of stages in the noise filter PDL_IIC_NF_3 or PDL_IIC_
458. or PDL_LPC_PLL_32768 or PDL_LPC_PLL_65536 or PDL_LPC_PLL_131072 or PDL_LPC_PLL_262144 or PDL_LPC_PLL_524288 or PDL_LPC_PLL_4194304 PDL_LPC_PLL_1048576 or PDL_LPC_PLL_2097152 or Select the oscillation settling time of the PLL before the CPU resumes after exiting from software standby mode When updating this value the PLL circuit must be stopped True if all parameters are valid and exclusive otherwise false LPC R_LPC_Control R_ CGC_Control R_CGC_Set R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 120 of 487 RX63N Group 4 Library Reference Remarks Program example If PDL_LPC_IO_DELAY is specified use R_LPC_Control with the PDL_LPC_IO_RELEASE option to cancel the I O port state retention The IRQn DS pins are the only IRQ pins that can be used to exit from deep software standby mode When operating power control mode switching is in progress do not call this function When the flash memory is in program or erase mode do not call this function if it will result in the power mode changing This function will return false is this situation During the period from the time of WAIT instruction issuance for a sleep mode transition to return from sleep mode to normal operation do not call this function If the NMI pin is enabled for cancelling deep software standby mode it cannot be disabled Use R_CGC_Control to stop and start the clocks as required When switch
459. or configuring and controlling the pulse generator outputs 15 8 bit Timer These driver functions are used for configuring and controlling the timers 16 Compare Match Timer These driver functions are used for configuring and controlling the timers 17 Real time Clock These driver functions are used for configuring and controlling the real time clock timer R20UT1963EE0100 Rev 1 00 R Page 17 of 487 Jul 19 2012 2 XENESAS RX63N Group 2 Driver 18 Watchdog Timer These driver functions are used for configuring and controlling the timer 19 Independent Watchdog Timer These driver functions are used for configuring and controlling the timer 20 Serial Communication Interface These driver functions are used to configure the serial channels and manage the transmission and or reception of data across them 21 CRC calculator These driver functions are used for controlling the calculator 22 C Bus Interface These driver functions are used for controlling the I C bus channels 23 Serial Peripheral Interface These driver functions are used for controlling the SPI channels 24 12 bit Analog to Digital Converter These driver functions are used for configuring the 12 bit ADC units controlling the units and reading the conversion results 25 10 bit Analog to Digital Converter These driver functions are used for configuring the 10 bit ADC units controlling the units and reading the conversion results 26
460. or unit 0 channels ANO AN1 AN2 AN3 AN4 AN5 and AN6 PDL_ADC_10_CHANNELS_OPTION_8 Single mode For unit 0 channel AN7 Scan mode For unit 0 channels ANO AN1 AN2 AN3 AN4 AN5 AN6 and AN7 R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 365 of 487 RX63N Group 4 Library Reference Description 2 2 e Trigger selection Return value PDL_ADC_10_TRIGGER_SOFTWARE or Software trigger Compare match input capture A PDL_ADC_10_TRIGGER_MTU0O_MTU4_CMIC_Aor from MTUO to MTU4 PDL_ADC_10_TRIGGER_TMRO_CM or Compare match from TMRO PDL_ADC_10_TRIGGER_ADTRG or Trigger from ADTRG Compare match input capture A from MTUO Compare match input capture A PDL_ADC_10_TRIGGER_TPUO_TPU4_CMIC_Aor from TPUO to TPU4 PDL_ADC_10_TRIGGER_MTU4_CM or Compare match from MTU4 Compare match input capture A PDL_ADC_10_TRIGGER_TPUO_CMIC_A from TPUO PDL_ADC_10_TRIGGER_MTUO_CMIC_A or e Data alignment selection The alignment of the 10 bit ADC conversion PDL_ADC_10_DATA_ALIGNMENT_LEFT or result within the 16 bit register PDL_ADC_10_DATA_ALIGNMENT_RIGHT Left padded at the MSB end Right padded at the LSB end e DMAC DTC trigger control PDL_ADC_10 DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_ADC_10_DMAC_TRIGGER_ENABLE or DMAC or DTC when a conversion PDL_ADC_10_DTC_TRIGGER_ENABLE or scan cycle completes
461. ore using the Real time CIOCK cccceeseeeeeeteeeeetteeeeeees 418 5 15 3 Using a Capture pin with the Real time CIOCK 0 2 0 0 cecececceceeeeeeeeecencaeeeeeeeeeteceaeaeeeeeeeeeeeeaees 420 5 15 4 Real time Clock operation with Vbatt mode ccccceeceeceeceeeeeeeeeceneaeeeeeeeeesecnaeaeeeeeeeeeteenaees 421 5 16 Independent Watchdog Timer cccccceeeeeececceceeeeeeeeeeeaeaeeeeeeeseeceaeaeeeeeeesecenceaeseseeesesseniseeeeeeetee 422 5 17 Serial Communication Interface cccccceceececeeceeeeeeeeeceneaeeeeeeeseceaeceeeeeeesececaeeeeeeeeesessenieeeeeeeettees 423 5 17 1 SCl Asynchronous Using Polling oreren eies ene a e e a aera 423 5 17 2 SCI Asynchronous Using Interrupts 0 ee eeccceee eee eeeeeceeeeeeeeeeeeeaeeeeeeaeeeeeeaeeeeeenaeeeseenaneeeeeaas 425 5 17 3 SCl Asynchronous Using DMAC nerenin einai ee e a aea 427 5 17 4 Synchronous Transmission and Reception sssssssssesrrsserrrsstttrssttrnssttnnssttntesttnnnsttnnnstennsneen 429 5 17 5 Synchronous Full Duplex Operation cccccececccce cece eececeee cece sees se ceacaeceeeeeeesecsaeaeeeeeeeeeneeaees 431 5 17 6 SCI Reception in Asynchronous Multi Processor mode 0 ccecccceeeeseeeeeeeeteeeceeteeeseeneeeeeeaas 433 5 17 7 SCI Transmission in Asynchronous Multi Processor Mode eeecceeeeeeeeeeeeeneeeeeeteeeeeenaeeeeeeaas 435 D106 SCM SPIIMOG E straa a Bata tia rae aaa ieee taints devia tage dant aed sid ee
462. ot selected TCDR_value The cycle data register value This will be ignored if the register is not selected TCBR_value The cycle buffer register value This will be ignored if the register is not selected True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 194 of 487 RX63N Group 4 Library Reference Reference R_MTU2_ControlChannel Remarks e Either this function or RLMTU2_ControlChannel must be used to start the timers e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call e The register access enable operation is executed at the start of this function The register access disable operation is executed at the end Therefore both options can be selected together with other changes in one function call If noise filter is enabled before starting the timer make sure at least 2 cycles of the selected noise filter clock has elapsed after the timer configuration use R_MTU2_Create Program example RPDL definitions include r_pdl_mtu2 h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure for the selected channel R_MTU2_ControlUnit_structure unit0O_parameter
463. ource file Linkage symbol file Opti ClUse short dispimm Options Link Library noprelink rom D R D_1 R_1 D_2 R_2 nomessage list CONFIGDIR PROJECTNAME map optimize symbol_delete R20UT1963EE0100 Rev 1 00 a2 AS Page 12 of 487 Jul 19 2012 SENES RX63N Group 1 Introduction b Set the floating point precision The wide range of possible internal clock frequencies requires double precision floating point number storage Select the CPU tab Click on the Details button to open the CPU details window Use the drop down menu to select Double precision CPU details Detail PIC PID Round to Nearest 7 Precision of double v Sign of char unsigned Sign of bit field junsigned atti Bit field order Right gt Width of divergence of function 24bit x l Denormalized number allower as a result I Replace from int with short I enum size is made the smallest Pack struct union and class F Use try throw and catch of C F Use dynamic_cast and typeid of C The saved and restored code of the accumulator in interrupt function Click on OK to close the window Click on OK to return to the main HEW window 10 Build the project No further configuration should be required Simply build the project R20UT1963EE0100 Rev 1 00 AS Page 13 of 487 Jul 19 2012 RENES RX63N Group 1 Introduction 1 2 3 Header file inclusio
464. output PO12 PO13 PO14 amp PO15 group 3 R_PPG_Create PDL_PPG_PO12_PIN_P34 PDL_PPG_PO13_PIN_P13 PDL_PPG_PO14_PIN_P16 PDL_PPG_PO15_PIN_P14 PDL_PPG_TRIGGER_MTUO Ox15 Configure PPG outputs PO20 and POZI group 5 R_PPG_Create PDL_PPG_PO20_PIN_PA4 PDL_PPG_PO21_PIN_PA5 PDL_PPG_TRIGGER_MTU1 PDL_PPG_NON_OVERLAP OxA5 Load the next output values on group 6 R_PPG_Control PDL_PPG_GROUP_6 OxA7 Disable outputs PO20 and PO21 R_PPG_Destroy PDL_PPG_PO20_PIN_PA4 PDL_PPG_PO21_PIN_PA5 while 1 Figure 5 58 Example of PPG R20UT1963EE0100 Rev 1 00 AS Page 484 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 5 26 Temperature Sensor Figure 5 59 shows an example Temperature Sensor usage Peripheral driver function prototypes include r_pdl_adc_12 h include r_pdl_cgc h include r_pdl_cmt h include r_pdl_ts h RPDL device specific definitions include r_pdl_definitions h void ADC_callback void unsigned short ts_result bool ADC_end void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Setup 12 bits ADC for temperature sensor R_ADC_12_ Create o L_ADC_12_INPUT_TS PDL_ADC_12_SAMPLING_TIME_TEMP_CALCULATI L_ADC_12_SCAN_SIN
465. ow when the transfer has ended Therefore when the transfer has completed the user must call the R_SCI_Control function with options PDL_SCI_STOP_TX PDL_SCI_STOP_RxX to manually disable the transmission reception as appropriate e Ifa callback function is specified and the interrupt priority level is zero this function will return false e If using this function to perform a full duplex transfer then the transfer mode for transmit and receive can be set independently If using the polling transfer mode for only one direction this function must not be called from an interrupt handler so that interrupts can still be serviced for the non polling transfer direction e Device packages with 100 pins do not have all of the SCI channels R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 297 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t SCI1RxBuffer 10 const uint8_t SCI1TxBuffer 10 4 ML pt a pt op OS gt OF pt Tg Sl gt OT pT LO SS SCI channel 1 receive data handler void SCI1RxFunc void SCI channel 1 error handler void SCI1lErrFunc void void func void Wait while send 5 characters on channel 0 R_SCI_SPI_Transfer 0 PDL_NO_DATA 5 NTZ345 PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC Start the transm
466. peripheral e Use R_INTC_ControlGroup to enable the required peripheral interrupt requests e Please see the notes on callback function use in 6 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function void CallBackFunc void void func void Assign a handler for group 4 R_INTC_CreateGroup 4 CallBackFunc 10 3 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 83 of 487 Jul 19 2012 RX63N Group 4 Library Reference 12 R_INTC_ControlGroup Synopsis Prototype Description 1 2 Control an interrupt request group bool R_INTC_ConirolGroup Group selection II Interrupt control operation Interrupt source selection uint8_t data1 uint8_t data2 uint32_t data3 Control an interrupt request group data1 The interrupt group n to be controlled where n 0 to 6 or 12 data2 The logical operations to be applied to the interrupt request group If multiple selections are required use to separate each selection PDL_INTC_GROUP_DISABLE Disable the interrupt requests PDL_INTC_GROUP_CLEAR Clear the interrupt request flags PDL_INTC_GROUP_ENABLE Enable the interrupt requests data3 Choose the peripheral interrupt request sources for the group specified in parameter data1 to be modified If multiple selections are req
467. ple RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h void func void Configure the IWDT R_IWDT_Set PDL_IWDT_TIMEOUT_16384 PDL_IWDT_CLOCK_OCO_256 R20UT1963EE0100 Rev 1 00 AS Page 276 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 2 R_IWDT Control Synopsis Prototype Description Return value Category Reference Control the Independent Watchdog operation bool R_IWDT_Conitrol uint8_t data Control selection Modify the operation of the Independent Watchdog timer data Control the timer e Counter start refresh PDL_IWDT_REFRESH Start or refresh the counter by re loading the timeout value True if the parameter is valid otherwise false Independent Watchdog Timer R_IWDT_Set Remarks e R_IWDT_Set must be used first to configure the timer unless using Initial Setting Memory Program example using R_MCU_OFS to enable the IWDT from reset RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h void func void Refresh the IWDT R_IWDT_Control PDL_IWDT_REFRESH R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 277 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_IWDT_Read Syn
468. polling if R_IIC_MasterSend 0 PDL_NO_DATA EEPROM_ADDRESS eeprom_data_array_l 4 PDL_NO_FUNC 0 false Read the channel and transfer R_IIC_GetStatus 0 amp status_flags amp TxChars PDL_NO_PTR Review the flags and transmit count to decide on the next action else R20UT1963EE0100 Rev 1 00 AS Page 447 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 0 5E 3 PDL_NO_FUNC Figure 5 40 Configure the I C channel and write 3 data bytes to the first locations 2 Reception Continuing from above The C in master is now used to read 4 bytes from a slave device from the current memory address eR om om om A A Figure 5 41 The bus activity showing 4 bytes being transmitted by the EEPROM Read data from the EEPROM using polling if R_IIC_MasterReceive 0 PDL_NO_DATA EEPROM ADDRESS data_storage 4 P 0 DL_NO_FUNC false Read the channel and transfer status R_IIC_GetStatus 0 amp status_flags PDL_NO_PTR amp RxChars Review the flags and transmit count to decide on the next action Figure 5 42 An example of reading data from the EEPROM R20UT1963EE0100 Rev 1 00 AS Page 448 of 487 Jul 19 2012 RENES RX63N Group 5 Usage Examples 3 Repeated Start Continuing from above The memory add
469. ption 2 2 Forn 5 PDL_MTU2_REGISTER_COUNTER_U Timer counter U register TCNTU PDL_MTU2_REGISTER_COUNTER_V Timer counter V register TCNTV PDL_MTU2_REGISTER_COUNTER_W_ Timer counter W register TCNTW PDL_MTU2 REGISTER _TGRU General register U PDL_MTU2_REGISTER_TGRV General register V PDL_MTU2_REGISTER_TGRW General register W TCNT_TCNTU_ value For n 0 to 4 The timer counter TCNT value For n 5 The timer counter TCNTU value This will be ignored if the register is not selected TGRA_TCNTV_value For n 0 to 4 The register TGRA value For n 5 The timer counter TCNTV value This will be ignored if the register is not selected TGRB_TCNTW_value For n 0 to 4 The register TGRB value For n 5 The timer counter TCNTW value This will be ignored if the register is not selected TGRC_TGRU_value For n 0 3 or 4 The register TGRC value For n 5 The register TGRU value This will be ignored if the register is not selected TGRD_TGRV_value For n 0 3 or 4 The register TGRD value For n 5 The register TGRV value This will be ignored if the register is not selected TGRE_TGRW_value For n 0 The register TGRE value For n 5 The register TGRW value This will be ignored if the register is not selected TGRF_value For n 0 The general register TGRF value This will be ignored if the register is not selected TADCOBRA_ value For n 4
470. py of the ACC register and restore it before exiting the callback function R20UT1963EE0100 Rev 1 00 Page 487 of 487 Jul 19 2012 RENESAS Revision History RX63N Group User s Manual Date Page Summary Ju 19 2012 Firstissu o O Renesas Peripheral Driver Library User s Manual RX63N Group Publication Date Rev 1 00 Jul 19 2012 Published by Renesas Electronics Corporation 2 CENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 903 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 78
471. r 50 The frequencies of the internal clocks ICLK PCLKA PCLKB FCLK and BCLK are achievable selected clock source 1 2 4 8 16 32 or 64 e The frequency of the IEBus clock IECLK is achievable selected clock source 2 4 6 8 16 32 or 64 e The frequency of the USB clock UCLK is achievable selected clock source 3 or 4 Category Clock generation circuit References R_CGC_Control RLMCU_GetStatus R_LLPC_Create R_BSC_Control Remarks e Call this function once for each clock source that will be used e If the current clock source is selected in parameter data1 the frequencies of the internal clocks will be changed by this function After a power on reset the MCU selects the LOCO as the clock source e This function must be called before configuring clock dependent modules e This function will enable the selected clock but will not select it as the current clock source After the required settling time use R_CGC_Control to select the desired clock source e If the sub clock is selected the Start type status flag will be set to Warm see R_MCU_GetStatus e If the sub clock oscillator is not fitted use R_CGC_Control to disable the oscillation circuit The registers MOSCWTCR main clock SOSCWTCR sub clock and PLLWTCR PLL provide stabilisation delays for the respective oscillator and must be written to while that clock is stopped If any of these registers needs to be modified stop the clock using R_CG
472. r DTC shall be used to handle the received data specify PDL_NO_DATA data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data func1 Transmit callback Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter 7 PDL_NO_FUNC This function will continue until the required number of Polling bytes has been sent Interrupts The function to be called when the last byte has been sent DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback function specified in R DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data5 The start address of the storage area for the expected data Specify PDL_NO_PTR if not receiving data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 296 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value func2 Receive callback Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling T
473. r Input capture at MTIOCnA rising edge PDL_MTU2_A_IC_FALLING_EDGE or Input capture at MTIOCnA falling edge PDL_MTU2_A_IC_BOTH_EDGES or Input capture at MTIOCnA both edges PDL MTU2 A IC COUNT or Input capture at channel rel up count or 2 nas down count Valid only for n 0 Input capture at channel n 1 TGRA compare match or input capture Valid only forn 1 PDL_MTU2_A_IC_CM_IC Input capture output compare control for register TGRB PDL_MTU2_B_OC_DISABLED or MTIOCnB output disabled PDL_MTU2_B_OC_LOW or MTIOCnB output low PDL_MTU2_B_OC_LOW_CM_HIGH or MTIOCnB initial output low goes high at compare match PDL_MTU2_B_OC_LOW_CM_INV or MTIOCnB initial output low toggles at compare match PDL_MTU2_B_OC_HIGH_CM_LOW or MTIOCnB initial output high goes low at compare match PDL_MTU2_B_OC_HIGH or MTIOCnB output high PDL_MTU2_B_OC_HIGH_CM_INV or MTIOCnB initial output high toggles at compare match PDL_MTU2_B_IC_RISING_EDGE or Input capture at MTIOCnB rising edge PDL_MTU2_B_IC_FALLING_EDGE or Input capture at MTIOCnB falling edge PDL_MTU2_B_IC_BOTH_EDGES or Input capture at MTIOCnB both edges PDL_MTU2_B_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 PDL_MTU2_B_IC_CM_IC Input capture at channel n 1 TGRC compare match or input capture Valid only for n 1 e Cascade input capture control Valid in cascade mode for n 1
474. r correct operation The transfer count values are cleared when a new transfer is started e If using the DTC or DMAC to transfer data the transfer count values will not be valid The R_DTC_GetStatus or R_LDMAC_GetStatus functions can be used to calculate the transfer count Note If the DTC DMAC transfer does not fully complete then the count reported by the DTC DMAC for a slave transmission will be one greater than the actual number of bytes read by the master Transmit mode is set when the master has started a master read transfer e Channels 1 and 3 are not available with the 100 pin package This function will return false in this case R20UT1963EE0100 Rev 1 00 Jul 19 2012 RENESAS Page 323 of 487 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t status_flags uintl6_t tx count Read the status of channel 0 R_IIC_GetStatus 0 amp status_flags amp tx_count PDL_NO_PTR R20UT1963EE0100 Rev 1 00 2tEN ESAS Jul 19 2012 Page 324 of 487 RX63N Group 4 Library Reference 4 2 25 1 R_SPI Set Synopsis Prototype Description 1 2 Serial Peripheral Interface Configure the SPI pin selection bool R_SPI_Set uint8_t data1 Channel selection uint32_t data2 Pin selection uint
475. rection PDL_IO_PORT_MODE or General or Peripheral I O mode control PDL_IO_PORT_TYPE or Open drain control PDL_IO_PORT_PULL_UP or Pull up control Drive capacity control por Leas Valid for ports 0 2 5 to 7 9 to E and G data3 The address where the register value shall be stored using one of the formats below Pin not PE1 open drain control b15 b1 bO 0 Oor1 Pin PE1 open drain control b15 b2 bi b0 0 0 to3 Port not open drain control b15 b8 b7 b1 0 Register Port open drain control b15 b8 b7 b0 Register ODR1 Register ODRO Return value True if all parameters are valid and exclusive otherwise false Category I O port References None Remarks e Ensure that the specified register is valid for the selected port or port pin R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 92 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t result Read the direction register for port C R_IO_PORT_ReadControl PDL_IO_PORT_C PDL_IO_PORT_DIRECTION result Read the output type for pin P13 R_IO_PORT_ReadControl PDL_IO_PORT_1_3 PDL_IO_PORT_TYPE result R20UT1963EE0100 Rev 1 00 AS Page 93 of 487 Jul 19 2012 RENES
476. red transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of bytes has been sent or another event occurs Interrupts The function to be called when bus activity has stopped Either the function to be called when each byte is sent or PDL_NO_FUNC Polling pe if the callback function specified in R_LDMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable and a normal transfer completed otherwise false R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 314 of 487 Jul 19 2012 RX63N Group 4 Library Reference Category Reference Remarks Program example IC R_IIC_Create R_IIC_GetStatus 1 1 co Vo If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 If the Start condition is enabled and the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated If the Start condition is disabled the slave address will not be transmitted If no callback function is specified for transmission completion this function
477. rence PDL_TPU_PIN_A6 PC6 Select the PC6 pin for TIOCAG PDL_TPU_PIN B6 PC7 Select the PC7 pin for TIOCB6 PDL_TPU_PIN_C6_PC4 Select the PC4 pin for TIOCC6 e Valid when n 7 PDL_TPU_PIN_D6_PC5 Select the PC5 pin for TIOCD6 PDL_TPU_PIN_A7_PDO PDL_TPU_PIN_B7_PD1 Select the PDO pin for TIOCA Select the PD1 pin for TIOCB7 e Valid when n 8 PDL_TPU_PIN_A8 PD2 Select the PD2 pin for TIOCA8 e Valid when n 9 PDL_TPU_PIN_B8_PD3 Select the PD3 pin for TIOCB8 PDL_TPU_PIN_AQ_PE2 Select the PE2 pin for TIOCAQY PDL_TPU_PIN_B9 PE3 Select the PE3 pin for TIOCB9 PDL_TPU_PIN_C9_PEO PDL_TPU_PIN_D9 PE1 Select the PEO pin for TIOCC9 Select the PE1 pin for TIOCD9 e Valid when n 10 PDL_TPU_PIN_A10_PE4 e Valid when n 11 PDL_TPU_PIN_B10_PE5 Select the PES pin for TIOCB10 Select the PE4 pin for TIOCA10 PDL_TPU_PIN_A11_PE6 Select the PE6 pin for TIOCA11 e Valid when n 0 1 2 3 4 5 PDL_TPU_PIN_B11_PE7 Select the PE7 pin for TIOCB11 PDL_TPU_PIN_CLKA_P14 or PDL_TPU_PIN_CLKA_PC2 Select the P14 or PC2 pin for TCLKA e Valid when n 0 1 2 5 PDL_TPU_PIN_CLKB_P15 or PDL_TPU_PIN_CLKB_PA3 or PDL_TPU_PIN_CLKB_PC3 Select the P15 PA3 or PC3 pin for TCLKB e Valid when n 0 2 4 5 PDL_TPU_P
478. ress pointer of an EEPROM will be modified and then a Repeat Start condition used to change to read the byte at that memory location in the EEPROM Slave address Memory address Slave address PR A ooo Ao A Figure 5 43 The bus activity showing the Repeated Start condition when switching to the Read process Send 1 byte to the EEPROM to update the sub address bits and do not stop R_IIC_MasterSend 0 PDL_IIC_STOP_DISABLE EPROM_ADDRESS eeprom_data_array_l 1 PDL_NO_FUNC 0 Read data from the EEPROM A repeated start will occur R_IIC_MasterReceive 0 PDL_NO_DATA EEPROM_ADDRESS ata_storage F DL_NO_FUNC d 2 P 0 Figure 5 44 Set the EEPROM sub address and then read 2 bytes R20UT1963EE0100 Rev 1 00 R AS Page 449 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 18 2 Master mode with DMAC In the following example data is written to an EEPROM in two bursts DMAC channel 3 is used to handle the data transfer The same EEPROM address locations are then read out in two bursts DMAC channel 2 is used to handle the data transfer PDL functions include r_pdl_cgc h include r_pdl_iic h include r_pdl_cmt h include r_pdl_dmac h PDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_dmac_end_handler void
479. riction on SDRAM mode setting True if all parameters are valid and exclusive and the SDCLK is not disabled otherwise false Bus Controller R_BSC_Set R_CGC_Set and R_CGC_Control e Before using this function ensure that function R_BSC_Create and then R_BSC_Control PDL_BSC_ENABLE has been called so that the bus is enabled The endian mode of the CPU is selected by the MDE pin low little endian high big endian e The cycle count parameters are not checked for validity Use the hardware manual to check these values The exact values in parameters data2 to data11 are to be set to respective bit field in SDRAM registers For the corresponding cycle count value please refer to the hardware manual e Multifunction Pin Control registers are modified by this function The SDRAM clock SDCLK must be configured and enabled using R_CGC_Set before calling this function If the SDCLK has been disabled using the CGC functions this function will return false If this function is successful it will activate the SDCLK e For the 100 pin package there is no SDRAM area so this function will return false e A 32 bit data bus width is only supported on the 176 and 177 pin device packages R20UT1963EE0100 Rev 1 00 ztENESAS Page 141 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl
480. rigger PDL_ADC_12_TRIGGER_ADTRGO or A pulse input on the ADTRGO pin PDL_ADC_12 TRIGGER_MTUO_ICCM_ Aor Input capture compare match A from MTUO PDL_ADC_12_TRIGGER_MTUO_ICCM_B or PDL_ADC_12_TRIGGER_MTU0O_MTU4_ICCM or Input capture compare match B from MTUO Input capture compare match from MTUO to MTU4 PDL_ADC_12_TRIGGER_TPU0_TPU4_ICCM_A or Input capture compare match A from TPUO to TPU4 PDL_ADC_12_TRIGGER_MTUO_CM_E or Compare match E from MTUO PDL_ADC_12 TRIGGER_MTUO_CM F or Compare match F from MTUO PDL_ADC_12 TRIGGER_MTU4_CM or Compare match from MTU4 PDL_ADC_12 TRIGGER_TPUO_ICCM_Aor Input capture compare match A from TPUO PDL_ADC_12_ TRIGGER_TMRO or Compare match from TMRO PDL_ADC_12 TRIGGER_TMR2 Compare match from TMR2 Pin selection required only if the pin is used as the trigger PDL_ADC_12_PIN_ADTRGO_PO7 or PDL_ADC_12_PIN_ADTRGO_P16 or PDL_ADC_12 PIN ADTRGO P25 data5 Value addition mode control If multiple selections are required use to separate each selection Specify PDL_NO_DATA if not required Value addition mode selection Select the pin for ADTRGO PDL_ADC_12_VALUE_ADD_CHANNEL_0 PDL_ADC_12_VALUE_ADD_CHANNEL_2 PDL_ADC_12_VALUE_ADD_CHANNEL_1 PDL_ADC_12_VALUE_ADD_CHANNEL_3 PDL_ADC_12_VALUE_ADD_CHANNEL_5 PDL_ADC_12_VALUE_ADD_CHANNEL_4 PDL
481. ritten to the backup area data2 The number of bytes to be written to the backup area Valid from 1 to 32 True if all parameters are valid otherwise false LPC None The definition R_ PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void fune void uint8_t data_to_save R_PDL_LPC_BACKUP_AREA_SIZE Write data into the backup registers R_LPC_WriteBackup data_to_save R_PDL_LPC_BACKUP_AREA_SIZE R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 124 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_LPC_ReadBackup Synopsis Prototype Description Return value Category References Remarks Program example Read from the Backup registers bool R_LPC_ReadBackup uint8_t data1 Data pointer uint8_t data2 Data count Read data from the backup registers data1 The storage area for the data read from the backup area data2 The number of bytes to be read from the backup area Valid from 1 to 32 True if all parameters are valid otherwise false LPC The definition R_ PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available RPDL definitions include r_pdl_lpc h RPDL device specific d
482. river 2 19 Programmable Pulse Generator Driver The driver functions support the use of the pulse generator providing the following operations 1 Configuring the generator for use 2 Disabling groups of outputs that are no longer required 3 Control of the generator during run time R20UT1963EE0100 Rev 1 00 Page 35 of 487 Jul 19 2012 RENESAS RX63N Group 2 Driver 2 20 88 bit Timer Driver The driver functions support the use of the four 8 bit timers providing the following operations 1 Selection of the TMR pins for use 2 Configuring a channel for use using register values which have been determined elsewhere 3 Configuring two channels as a 16 bit pair using register values which have been determined elsewhere 4 Configuration for as a periodic timer including e Automatic clock setting using frequency or period as an input e Automatic pulse width setting using pulse width or duty cycle as an input e Automatic interrupt control 5 Configuration for as a one shot timer including e Automatic clock setting using pulse width as an input e Automatic interrupt control e CPU sleep option e Automatic support for using two channels as a single 16 bit timer 6 Disabling channels that are no longer required and enabling low power mode 7 Control of a single timer channel 8 Control of two timer channels when configured as one 16 bit channel 9 Control of channels in periodic mode enabling pulse width modulation PW
483. rks The maximum number of characters to be received is 65535 Wait until a transmission on the same channel is complete before calling this function If callback function func is specified reception interrupts are used Please see the notes on callback function usage in 6 If polling mode is used the RXI flag will be used to manage the data reception If the SCI channel s control registers are directly modified by the user this function may lock up If no error callback function func2 is specified the error flags are cleared automatically to allow the reception process to complete Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed In Multi processor mode R_SCI_Receive is to be called in a pair the first one is to receive ID ID cycle the second one is to receive data Data cycle For ID reception it could be done by reception interrupt by specifying func1 or by internal polling operation without specifying func1 For Data reception it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to section 5 17 6 For the ID cycle the DMAC DTC trigger control will be ignored In synchronous mode if both the Tx Data and the Rx Data pins have been enabled when R_SCI_Create was called then a reception must be performed in conjunction with a corresponding transmission This is a
484. rol Remarks Program example e The bus error interrupt request will not be disabled by this function Use R_BSC_Control to disable it e Multifunction Pin Control registers are modified by this function e Ifthe SDCLK is active it will be de activated RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the CS4 area R_BSC_Destroy 4 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 137 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_BSC_Conirol Synopsis Prototype Description Modify the External Bus Controller operation bool R_BSC_Control uint16_t data Control options Control the BSC operation data Control the BSC operation Start stop operation PDL_BSC_ENABLE or PDL_BSC_DISABLE Enable or disable BSC operation e Error clearing PDL_ BSC ERROR CLEAR Clear the bus error status registers e Disable bus error interrupt request PDL_BSC_DISABLE_BUSERR_IRQ Disable bus error interrupt requests SDRAM initialization PDL BSC SDRAM INITIALIZATION Perform SDRAM initialization e Set Auto Refresh register PDL_BSC_SDRAM_AUTO_REFRESH_ENABLE Set Auto Refresh register e Clear Auto Refresh register PDL_BSC_SDRAM_AUTO_REFRESH_DISABLE Clear Auto Refresh register e Set Self Re
485. rol 0 PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT PDL_TPU_START PDL_NO_DATA PDL_NO_DATA TA cA TA R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 391 of 487 Jul 19 2012 RX63N Group 5 Usage Examples Start TPU channel 1 R_TPU_Control 1 PDL_TPU_START PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_ DATA Discard the first reading while mck_completed false mck_completed false while 1 Is a new reading ready if mck_completed true Calculate the frequency of the less stable clock Examples of both equations are given below Calculate the frequency of the reference clock measured_frequency f_system_clock system_clock_count reference_count Calculate the frequency of the system clock measured_frequency f_reference_clock system_clock_count reference_count Process the result here nop Allow a new reading to be taken mck_completed false static void Read_the_MCK void Is it safe to update the stored timer value if mck_completed false Read TGRA from timer 1 R_TPU_Read 1 PDL_NO_PTR PDL_NO_PTR amp system_clock_count PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR Signal that the reading is updated mck_completed true Figure 5 6 Example of clock monitoring using MCK system 2 R20UT1963EE0100 Rev 1 00 AS Page
486. roy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down the ADC unit bool R_ADC_12_Destroy uint8_t data ADC unit selection Put the ADC into the Power down state with minimal power consumption data Select the ADC unit to be shut down This must always be 0 True if a valid unit is selected otherwise false 12 bit ADC R_ADC_12_Create This function includes a 1 ms delay to allow the ADC to stop any current scan cycle RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the ADC unit R_ADC_12_Destroy 0 i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 361 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_ADC_12_Control Synopsis Prototype Description Return value Category Reference Remarks Program example Start or stop an ADC unit bool R_ADC_10_Control uint8_t data Conversion unit control Controls start stop operation of the specified ADC data To select multiple options at the same time use to separate each value On off control PDL_ADC_12_0 ONor Start a software triggered conversion or re enable the trigger PDL_ADC_12_0 OFF Stop the conve
487. rsion and disable all triggers e Control the CPU during the ADC conversion PDL_ADC_12_CPU_OFF Stop the CPU when the scan conversion process starts The CPU will re start when any valid interrupt occurs True if all parameters are valid and exclusive otherwise false 12 bit ADC R_ADC_12_Create e For single scan mode the ADC will stop automatically when the conversion is complete RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Start the ADC conversion process R_ADC_12_ Control PDL_ADC_12_0_ON R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 362 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_ADC 12 Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read the ADC conversion results bool R_ADC_12_Read uin uin t8_t data1 ADC unit selection t16_t data2 Pointer to the buffer where the converted values are to be stored Reads the conversion values for an ADC unit data1 Select the ADC unit to be used This must always be 0 data2 Specify a pointer to an array where the results shall be stored True ifa valid unit is selected otherwise false 12 bit ADC R_ADC_12_Create e Ifthe unit is configured to be reading the
488. rupt _ADC_12 c Intern Add Files of type C source file C Cancel V Relative Path Hide Project Files Click on Add Click on OK to return to the main HEW window R20UT1963EE0100 Rev 1 00 az AS Page 7 of 487 Jul 19 2012 SENES RX63N Group 1 Introduction 6 Peripherals that are not required If a peripheral module is not required the interrupt handler file does not need to be included If the unused interrupts still require entries in the interrupt vector table edit the file Interrupt_not_RPDL c to uncomment the define for the unused peripherals For example define RPDL_ADC_12_not_used Becomes define RPDL_ADC_12_not_used The file Interrupt_INTC c must be included 7 Peripherals that are not supported by RPDL The file Interrupt_not_RPDL c also contains handlers for the peripherals that are not supported by RPDL This allows the user to add handler code for these peripherals while supporting the Fast Interrupt feature see R_INTC_CreateFastinterrupt R20UT1963EE0100 Rev 1 00 Page 8 of 487 Jul 19 2012 RENESAS RX63N Group 1 Introduction 8 Avoid conflicts with standard project files If the files intprg c or vecttbl c are included in the project remove or exclude them a Removal Use the key sequence Alt P R to open the Remove Project Files window Select the files and click on Remove Remove Project Files Project files OK dbsct c C WorkSpace
489. rve 16 bytes full address mode for the CMTO triggered transfer data area Use a 32 bit type to make the address a multiple of 4 uint32_t dtc_cmt0O_transfer_data 4 void func void Configure the DTC for CMTO R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_FIXED PDL_DTC_DESTINATION_ADDRESS_PLUS PDL_DTC_SIZE_8 PDL_DTC_TRIGGER_CMTO dtc_cmt0O_transfer_data 0x0000AA00 0x0000BBO0 100 0 R20UT1963EE0100 Rev 1 00 REN ESAS Page 168 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_DTC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable the Data Transfer Controller bool R_DTC_Desitroy void II No parameter is required Shutdown the Data Transfer Controller True Data Transfer Controller R_DTC_Control e This function will also shut down the DMAC e Before calling this function i If another peripheral is being used to trigger a DTC transfer stop the triggers from that peripheral using Control or Destroy for that peripheral ii Use R_DTC_Control to stop the DTC iii Stop the DMAC RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown the DTC amp DMAC R_DTC_Destroy R20UT1963EE0100 Re
490. s Prototype Description Return value Category Reference Remarks Read from timer channel registers bool R_TPU_Read uint8_t data1 uint8_t data2 uint16_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint16_t data7 Channel selection A pointer to the data storage location A pointer to the data storage location A pointer to the data storage location A pointer to the data storage location A pointer to the data storage location A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 11 data2 The status flags shall be stored in the format below The input capture compare match flags Ato D will be set to1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read For n 0 3 60r9 b7 b6 b5 b4 b3 b2 b1 bO Overflow Input capture compare match 0 0 detection detection 0 V D C B A For n 1 2 4 5 7 8 10 or 11 b7 b6 b5 b4 b3 b2 b1 bO detection detection e detector Count direction vee A i comer ne data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the general register A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where
491. s Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set up SCIO Async 8N1 19200 baud R_SCI_Create 0 PDL_SCI_ASYNC PDL_SCI_8N1 19200 1 0 3 Configure channel 3 of DMAC to be triggered by SCIO Tx R_DMAC_Create 3 PDL_DMAC_REPEAT PDL_DMAC_SOURCE_ADDRESS_ PLUS PDL_DMAC_DESTINATION_ADDRESS_FIXED PDL _DMAC_SIZ PDL_DMAC_TRIGGER_SCIO_TX string Source const char amp SCIO TDR Destination 1 uintl6_t strlen char string PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 Enable DMAC R_DMAC_Control a PDL_DMAC_ENABL PDL_NO PTR L_NO_PTR L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA D D PD D D D Start transmission R_SCI_Send R20UT1963EE0100 Rev 1 00 Page 427 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 0 PDL_SCI_DMAC_TRIGGER_ENABLE PDL_NO_PTR PDL_NO_DATA No data as using DMAC PDL_NO_FUNC BRK k e e KKK KK KKK KK KKK KK KK KK IKK KK KKK He e He e He e KK KK He de He KKK e He e He e He e He e ke e He e ke ke ke ke ke ke ke ke ke IMPORTANT The SCI module does not know when the DMAC has finished therefore we must tell it using the R_SCI_Control function HK ke e e e KK KK KK KK
492. s include r_pdl_cgc h include r_pdl_cmt h include r_pdl_rtc h include r_pdl_definitions h void main void Prepare the LOCO settings R_CGC_Set PDL_CGC_CLK_LOCO PDL_CGC_BCLK_DISABL 125E3 125E3 125E3 125E3 125E3 PDL_NO_DAT PDL_NO_DAT PDL_NO_DAT Enable the Subclock and prepare the Subclock settings R_CGC_Set PDL_CGC_CLK_SUB_CLOCK PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABL 32767 20E6 20E6 20E6 20E6 PDL_NO_DA1 PDL_NO_DAT PDL_NO_DA1 Wait for the Subclock stabilisation time 2 seconds minimum NOTE As currently running from the LOCO the R_CMT_CreateOneShot max time limit is gt 2 Secs R_CMT_CreateOneShot 0 PDL_NO_DATA 2 0 PDL_NO_FUNC 0 Set the clock source as the subclock R_CGC_Control PDL_CGC_CLK_SUB_CLOCK PDL_NO_DATA PDL_NO_DATA Set the current time and enable the alarm R_RTC_Create PDL_RTC_COUNT_SOURCE_SUBCLK PDL_RTC_24 HOUR_MODE PDL_NO_DATA OxFF114250 Automatic day of week 11 42 50 0x20101118 18 Nov 2010 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT1963EE0100 Rev 1 00 Page 418 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO_DATA Figure 5 23 Example of running from the Sub clock before using the Real Ti
493. s include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h Callback function void CallBackFunc void void func void uint8_t iebus_data 32 uint8_t iebus_data_length Read data from slave 345h R_IEB_MasterReceive 0 PDL_IEB_DATA 0x0345 iebus_data amp iebus_data_length CallBackFunc R20UT1963EE0100 Rev 1 00 Page 345 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 6 R_IEB_SlaveMonitor Synopsis Prototype Description Monitor the IEBus bool R_IEB_SlaveMonitor uint8_t data1 Channel selection uint8_t data2 Data storage start address uint8_t data3 Data length storage address void func Callback function Monitor the bus until an address match occurs and store any data received data1 Select channel n where n 0 only data2 The start address of the area for storing the data to be received in the data field data3 The address of the area for storing the number of bytes that were received in the data field func Specify PDL_NO_FUNC or a callback function depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until data is received or Program example Polling another event occurs Interr nts The function to be called whenever data is r
494. s unitO_parameters simultaneous_control PDL_MTU2_START_0 unitO_parameters output_control PDL_MTU2_OUT_P_PHASE_ALL_HIGH_LOW unitO_parameters general_control PDL_MTU2_DEAD_TIME_ENABLE unitO_parameters register_selection PDL_MTU2_REGISTER_DEAD_TIME PDL_MTU2_REGISTER_CYCLE_DATA unitO_parameters TDDR_value OxFFDD unitO_parameters TCDR_value 0x0100 Modify the operation of unit 0 R_MTU2_ControlUnit 0 amp unit0_parameters R20UT1963EE0100 Rev 1 00 Page 195 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 6 Synopsis Prototype Description 1 2 R_MTU2_ReadChannel Read from MTU channel registers bool R_MTU2_ReadChannel uint8_t data1 Channel selection uint8_t data2 Apointer to the data storage location uint16_t data3 A pointer to the data storage location uint16_t data4 A pointer to the data storage location uint16_t data5 A pointer to the data storage location uint16_t data6 A pointer to the data storage location uint16_t data7 A pointer to the data storage location uint16_t data8 A pointer to the data storage location uint16_t data9 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 5 data2 The status
495. s 8 97 7 kbps to 93 75 kbps to 24 4 kbps to 23 4 kbps to 62 5 kbps to 15 6 kbps to 3 13 Mbps 3 0 Mbps 781 kbps 750 kbps 2 00 Mbps 500 kbps fpeLkg 16 48 8 kbps to 46 875 kbps to 12 2 kbps to 11 71 kbps to 31 3 kbps to 7 81 kbps to 1 56 Mbps 1 5 Mbps 391 kbps 375 kbps 1 00 Mbps 250 kbps fecike 32 24 4 kbps to 23 4 kbps to 6 10 kbps to 5 86 kbps to 15 6 kbps to 3 91 kbps to 781 kbps 750 kbps 195 kbps 187 5 kbps 500 kbps 125 kbps fpcike 64 12 2 kbps to 11 71 kbps to 3 05 kbps to 2 93 kbps to 7 81 kbps to 1 95 kbps to 391 kbps 375 kbps 97 7 kbps 93 75 kbps 250 kbps 62 5 kbps fpctka 128 6 10 kbps to 5 86 kbps to 1 53 kbps to 1 46 kbps to 3 91 kbps to 977 bps to 195 kbps 187 5 kbps 48 8 kbps 46 875 kbps 125 kbps 31 3 kbps The actual rise and fall times will not be zero Using the limits from the I C specification Rise time rate lt 100 kbps 1000 ns 100 kbps lt rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Fall time rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Maximum rate 1 Mbps The achievable transfer rates are fecike MHz IRC 50 48 12 5 12 32 8 PCLKB 1 658 kbps to 635 6 kbps 175 kbps to 168 5 kbps to 446 kbps to 116 kbps to 1 Mbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps PCLKB 2 316 kbps to 306 kbps to 86 7 kbps to 83 6 kbps to 217 kbps to 57 8 kbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps PCLKB
496. selections are required use to separate each selection e Enable suspend control PDL_DMAC_ENABLE Enable re enable DMA transfers PDL_DMAC_SUSPEND Suspend DMA transfers e Software trigger control PDL_DMAC_START or Start a DMA transfer PDL_DMAC_START_RUN or Start DMA transfers until stopped PDL_DMAC_STOP Stop software triggered transfers e Transfer end interrupt flag control PDL_DMAC_CLEAR_DTIF Clear the Transfer End flag PDL_DMAC_CLEAR_ESIF Clear the Transfer Escape End flag The values to be modified PDL_DMAGC_UPDATE_SOURCE Source address using parameter data3 PDL_DMAGC_UPDATE_DESTINATION Pen aa address using parameter PDL DMAC UPDATE COUNT Transfer count using parameter data5 PDL_DMAC_UPDATE_ SIZE hE or Block size using parameter PDL_DMAC_UPDATE_OFFSET Address offset using parameter data7 PDL DMAC UPDATE REPEAT SOURCE Source address extended repeat area using parameter data8 Destination address extended repeat area using parameter data9 PDL_DMAC_UPDATE_REPEAT_DESTINATION data3 The new source address Specify PDL_NO_PTR if not required data4 The new destination address Specify PDL_NO_PTR if not required data5 The transfer count value Specify PDL_NO_DATA if not required R20UT1963EE0100 Rev 1 00 R AS Page 150 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference
497. shold void func Callback function uint8_t data6 Interrupt priority level Read data over an I C channel and store it data1 Select channel IICn where n 0 to 3 data2 Configure the channel The default setting is shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_TRIGGER_ENABLE received data3 The address of the slave device data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data data5 The number of bytes that must be received before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of bytes has been received or another event occurs Interrupts The function to be called when bus activity has stopped Either the function to be called when each byte is received or PDL_NO_FUNC Polling PMA if the callback function specified in R_ DMAC_ Create will be used D
498. software interrupt and copies data from ROM into RAM On completion of transfer 1 transfer 2 is started On completion of transfer 2 transfer 3 is started Peripheral driver function prototypes include r_pdl_dtc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve three contiguous groups of 16 bytes full address mode for the transfer data areas uint32_t dtc_sw_transfer_data 4 3 const char source_string_1 Renesas RX63N const char source_string_2 DTC example const char source_string_3 using chain transfer volatile char destination_string_1 volatile char destination_string_2 volatile char destination_string_3 void main void Enable software interrupts R_INTC_CreateSoftwarelInterrupt PDL_INTC_DTC_SW_TRIGGER_ PDL_NO_FUNC 0 Configure the controller R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table R20UT1963EE0100 Rev 1 00 Page 407 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Configure the DTC for Software trigger R_DTC_Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_ PLUS PDL_DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 P
499. ss offset uint32_t data9 Source address extended repeat area uint32_t data10 Destination address extended repeat area void func Callback function uint8_t data11 Interrupt priority level Set up a DMA channel data1 The channel number n where n 0 to 3 data2 Configure the operation of channel DMAn If multiple selections are required use to separate each selection The default settings are shown in bold e Transfer mode selection PDL_DMAC_NORMAL or Normal or PDL_DMAC_REPEAT or Repeat or PDL_DMAC_BLOCK Block mode PDL_DMAC_SOURCE or Jestination side can be selected as the Repeat or Block PDL_DMAC_DESTINATION fog area This selection is optional Address direction selection PDL_DMAC_SOURCE_ADDRESS_FIXED or Leave the source address unchanged PDL_DMAC_SOURCE_ADDRESS_PLUS or increment it decrement it or modify it by PDL_DMAC_SOURCE_ADDRESS_MINUS or the value specified in parameter data8 PDL_DMAC_SOURCE_ADDRESS_OFFSET Address offset is valid only for n 0 PDL_DMAC_DESTINATION_ADDRESS_FIXED or Leave the destination address 5 PDL_DMAC_DESTINATION_ADDRESS PLUS or ged decrement PDL_DMAC_DESTINATION_ADDRESS_MINUS or t0 modify it by the value specified in parameter data8 PDL_DMAC_DESTINATION_ADDRESS_OFFSET Address offsatis valid onlviorn Transfer data size PDL_DMAC_SIZE_8 or PDL_DMAC_SIZE_16 or Select 8 16 or 32 bits for the
500. ssion is required e Ifa callback function was specified in the call to R_IIC_SlaveMonitor then this transfer shall be completed using interrupts and the callback function shall be called when the transfer ends e Ifa callback function was not specified in the call to R_IIC_SlaveMonitor then this function will not return until the transfer has ended e Ifthe master requires more data than is supplied this function shall loop back to the start of the data e Channels 1 and 3 are not available with the 100 pin package This function will return false in this case Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxF fl void func void Assign 5 bytes to be read by a master on channel 0 R_IIC_SlaveSend 0 data_array 5 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 321 of 487 Jul 19 2012 RX63N Group 4 Library Reference 8 R_lIC_Control Synopsis lC channel control Prototype bool R_IIC_Conirol uint8_t data1 Channel selection uint8_t data2 Control options Description Modify the operation of the selected C channel data1 Select channel IICn where n 0 to 3 data2 Control the channel If multiple selections are required use to separate each selection e Stop generation
501. st RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set the IPL to 6 R_INTC_Write PDL_INTC_REG_IPL 6 Set the IR for IRQO to 0 R_INTC_Write PDL_INTC_REG_IR_ICU_IRQO 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 81 of 487 Jul 19 2012 RX63N Group 4 Library Reference 10 R_INTC_Modify Synopsis Prototype Description Modify an interrupt register bool R_INTC_Modify uint16_t data1 Register selection uint8_t data2 Logical operation uint8_t data3 II Modification value Update the value in an interrupt register data1 The register to be updated PDL_INTC_REG_IR_ register or Select the Interrupt Request register or PDL_INTC_REG_IER register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register Interrupt Priority register data2 e The logical operation to be applied to the register contents PDL_INTC_AND or PDL_INTC_OR or Select between AND amp OR or Exclusive OR PDL_INTC_XOR data3 The value to be used by the logical operation Return value True if the parameter is within range otherwise false Category Interrupt control Reference None Remarks e This function uses an interrupt routine to modify the IPL bits If t
502. starting of ADC units select an appropriate hardware trigger e g timer TMR RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Start ADC unit 0 R_ADC_10_Control PDL_ADC_10_0_ON R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 370 of 487 Jul 19 2012 RX63N Group 4 Library Reference 5 R_ADC_10 Read Synopsis Read the ADC conversion results Prototype bool R_ADC_10_Read uint8_t data1 ADC unit selection uinti6_t data2 Pointer to the buffer where the converted values are to be stored Description Reads the conversion values for an ADC unit data1 Select the ADC unit 0 only to be read data2 Specify a pointer to a variable or array where the results shall be stored Return value True if a valid unit is selected otherwise false Category 10 bit ADC Reference R_ADC_10_Create Remarks From 1 to 8 conversion results will be read and stored The number depends on the settings for Input channel selection and Scan mode when R_ADC_10_Create is used to configure the ADC unit The 10 bit data alignment is controlled using the R_ADC_10_Create function Ensure that the buffer is big enough for the requested number of values e Ifno callback function is used this function waits for the ADI flag to indicate that conversion is complete before reading the
503. ster mode If Repeat Block or Cluster mode is selected the source or destination side can be selected as the Repeat or Block area This selection is optional PDL_EXDMAC_CLUSTER PDL_EXDMAC_SOURCE or PDL_EXDMAC_DESTINATION Address direction selection PDL_EXDMAC_SOURCE_ADDRESS_FIXED or PDL_EXDMAC_SOURCE_ADDRESS_PLUS or PDL_EXDMAC_SOURCE_ADDRESS_ MINUS or PDL_EXDMAC_SOURCE_ADDRESS_OFFSET Leave the source address unchanged increment it decrement it or modify it by the value specified in parameter data9 Address offset is valid only for n 0 Leave the destination address unchanged increment it PDL_EXDMAC_DESTINATION_ADDRESS_FIXED or PDL_EXDMAC_DESTINATION_ADDRESS_PLUS or PDL_EXDMAC_DESTINATION_ADDRESS_MINUS or PDL_EXDMAC_DESTINATION_ADDRESS_OFFSET decrement it or modify it by the value specified in parameter data9 Address offset is valid only for n 0 Address mode selection PDL_EXDMAC_ADDRESS_MODE_READ or PDL_EXDMAC_ADDRESS_MODE_WRITE or PDL_EXDMAC_ADDRESS_MODE_DUAL Select single address mode with the source or destination for address output or dual address mode Transfer data size PDL_EXDMAC_SIZE_8 or PDL_EXDMAC_SIZE_16 or PDL_EXDMAC SIZE 32 Select 8 16 or 32 bits for the data to be transferred R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 156 of 487 RX63N Group 4 Library Reference Description 2 3 data3
504. stroy uint8_t data Channel selection Stop data flow and shutdown the selected SCI channel data Select channel SClin where n 0 to 12 True if all parameters are valid otherwise false SCI None The SCI channel is put into the power down state e Device packages with 100 pins do not have all of the SCI channels RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SCI channel 1 R_SCI_Destroy 1 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 289 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_SCI_ Send Synopsis Prototype Description Return value Transmit data on a SCI channel bool R_SCI_Send uint8_t data1 Channel selection uint16_tdata2 Channel configuration and Target Station ID uint8_t data3 Data start address uint16_tdata4 Data count void func Callback function Transmit data on the specified serial channel data1 Select channel SClIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SCI_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_SCI_DTC_TRIGGER_ENABLE transmitted
505. t data5 Current transfer count pointer uint16_t data6 Current Repeat or Block size count pointer Return status flags and current channel registers data1 The channel number n where n 0 to 1 data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 Peripheral transfer request PREQ EDREQn transfer request EREQ Interrupt 0 0 No request 0 No request request 1 Requested 1 Requested IR b3 b2 b1 bO Transfer Escape End interrupt Transfer End interrupt Status Transfer enable ESIF DTIF ACT DTE 0 Idle 0 Idle 0 Idle 0 Disabled 1 Generated 1 Generated 1 Operating 1 Enabled data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required data6 Where the current repeat block or cluster size shall be stored Specify PDL_NO_PTR if it is not required Return value True if all parameters are valid and exclusive otherwise false Category EXDMA controller Reference R_EXDMAC_Create Remarks Ifthe Interrupt request flag is set to 1 the flag will be cleared to O by this function R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 162 of 487 Jul 19 2
506. t capture B PDL_INTC_VECTOR_TGI8A_A2 PDL_INTC_VECTOR_TGI8B_B2 Timer Pulse Unit channel 8 or Multi function Timer Pulse Unit channel 2 Compare match or Input capture A Compare match or Input capture B R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 68 of 487 RX63N Group 4 Library Reference Description 3 4 PDL_INTC_VECTOR_TGIA3 Jul 19 2012 PDL_INTC_VECTOR_TGIB3 PDL_INTC_VECTOR_TGIC3 PDL_INTC_VECTOR TGID3 Timer Pulse Unit channel 9 or Multi function Timer Pulse Unit channel 3 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D PDL_INTC_VECTOR_TGI10A_A4 PDL_INTC_VECTOR TGI10B_B4 PDL_INTC_VECTOR_TGIC4 PDL_INTC_VECTOR_TGID4 PDL_INTC_VECTOR_TCIV4 Timer Pulse Unit channel 10 or Multi function Timer Pulse Unit channel 4 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow or underflow PDL_INTC_VECTOR_TGIU5 PDL_INTC_VECTOR_TGIV5 PDL_INTC_VECTOR_TGIW5 PDL_INTC_VECTOR_TGI11A Timer Pulse Unit channel 11 or Multi function Timer Pulse Unit Compare match or Input capture U Compare match or Input capture V Compare match or Input capture W Compare ma
507. t may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please
508. t occurred 0 Not occurred 0 Not occurred 0 Not occurred 1 Occurred 1 Occurred 1 Occurred 1 Occurred data5 The last master unit address received during reception Specify PDL_NO_PTR if this information is not required data6 The address of the master unit that has issued a lock request Specify PDL_NO_PTR if this information is not required True if all parameters are valid otherwise false IEBus e Any Transmit and Receive status flags that are read as 1 are cleared to 0 by this function In the Receive case this will allow the slave to receive more data RPDL definitions include r_pdl_ ieb h RPDL device specific definitions include r_pdl_definitions h void func void R20UT1963EE0100 Rev 1 00 Jul 19 2012 uintl6_t StatusValue Read the status of channel 0 R_IEB_GetStatus 0 amp StatusValue PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR 2tENESAS Page 351 of 487 RX63N Group 4 Library Reference 4 2 27 Synopsis Prototype Description Return value Category References Remarks Program example CRC calculator 1 R_CRC_Create Configure the CRC calculator bool R_CRC_Create uint8_t data Configuration Enable the CRC and set the operating conditions data Calculation options To set multiple options at the same time use to separate each valu
509. t the channel 0 counter value to the mid point of the channel 1 counter reference_count uint16_t UINT16_MAX 2 f_system_clock f_reference_clock Configure TPU channel 0 Normal operation Counter input is the TCLKD input counter cleared by compare match A Compare match A output disabled Set the reference count as the compare match A value R_TPU_Create 0 1 _TPU_C L_TPU_MODE_NORMAL KK_TCLKD PDL_TPU_CLEAR_CM_A TE OO TU WW U os U U E 5 U Ovuvv 00 0G 00u T O U U R L_TPU_A_OC_DISABLED L_NO_DATA L_NO_DATA t1l6_t reference count 1 L_NO_DATA L_NO_DATA L_NO_DATA L_NO_FUNC L_NO_FUNC L_NO_FUNC L_NO_FUNC DL_NO_FUNC PDL_NO_FUNC Configure TPU channel 1 Normal operation Counter input is PCLK counter cleared by input capture A Input capture is compare match A of channel 0 R_TPU_Create il i TPU_C L_TPU_MODE_NORMAL K_PCLK_DIV_1 PDL_TPU_CLEAR_CM_A p p p L_TPU_A IC TPU CM IC pP Hj EE hy td U H H U O G G Ul gog ty oO Ca Fg Ne yy ha hg mck_completed L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA ad_the_MCK DL_NO_FUNC DL_NO_FUNC DL_NO_FUNC DL_NO_FUNC DL_NO_FUNC false Start TPU channel 0 R_TPU_Cont
510. t32_t slave_0O_rx_data 4 0x00000000 0x00000000 0x00000000 0x00000000 uint8_t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure SPI Pin R_SPI_Set SLAVE_CHANNEL PDL_SPI_RSPCKA_PA5 PDL_SPI_MOSIA_PA6 PDL_SPI_MISOA_PA7 PDL_SPI_SSLAO_PA4 PDL_NO_DATA i Configure SPI Pin R_SPI_Set MASTER_CHANNEL PDL_NO_DATA PDL_SPI_RSPCKB_PE5 PDL_SPI_MOSIB_PE6 PDL_SPI_MISOB_P PDL_SPI_SSLBO_PE4 Gl I di Configure the master SPI channel R_SPI_Create MASTER_CHANNEL PDL_SPI_MODE_SPI_MASTER PDL_SPI_PIN_SSLO_LOW DL_SPI_FRAME 1 4 DI L_NO_DATA NUD i Configure the slave SPI channel R_SPI_Create SLAVE_CHANNEL PDL_SPI_MODE_SPI_SLAVE PDL_SPI_FRAME 1 4 PDL_NO_DATA PDL_NO_DATA T i Configure the Master R_SPI_Command MASTER_CHANNEL 0 PDL_SPI_CLOCK_MODE_0 PDL_SPI_LENGTH_32 PDL_SPI_LSB_FIRST PDL_SPI_ASSERT_SSLO PDL_NO_DATA i Configure the slave R_SPI_Command SLAVE_CHANNEL 0 PDL_SPI_CLOCK_MODE_O PDL_SPI_LENGTH_32 PDL_SPI_LSB_FIRST PDL_NO_DATA i Prepare the Slave for data transfer R_SPI_Transfer R20UT1963EE0100 Rev 1 00 Page 462 of 487 Jul
511. t8_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 1 2 or 3 data2 The status flags shall be stored in the format below The flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read b7 b4 b2 b1 bO 0 Overflow Compare match B Compare match A data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True Timer TMR R_TMR_CreateChannel Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to 0 by this function include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint8_t Counter uint8_t CompareMatchA uint8_t CompareMatchB void func void Read the status flags and registers for TMRO R_TMR_ReadChannel 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 247 of 487 RX63N Group 4 Library Reference 11 R_TMR_ReadUnit Synopsis Prototype Description Return value
512. ta1 Specify what to read uint8_t data2 A pointer to the flags storage location uint32_t data3 A pointer to the data storage location uint32_t data4 A pointer to the data storage location Read the Clock counters registers and status flags data1 Specify what to read PDL_RTC_READ_CURRENT or PDL_RTC_READ_ALARM or PDL_RTC_READ_CAPTURE_0 or Specify which time to read PDL_RTC_READ_CAPTURE_1 or PDL_RTC_READ_CAPTURE_2 data2 The format of data2 is dependent upon data1 Format if datai PDL RTC READ CURRENT The clock status shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 Mode Interrupt requests 0 12 hour Carry Periodic Alarm 0 Idle 1 24 hour 1 Occurred b3 b2 b1 bO Status 0 30 second adjustment Reset Clock 0 Normal operation 0 Normal operation 0 Stopped 1 Adjustment in progress 1 Reset in progress 1 Running Format if datali PDL RTC READ ALARM The enable bits for the alarm shall be stored in the following format 1 enabled meaning the unit is part of the alarm setting 0 disabled meaning the unit is ignored Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 b3 b2 b1 bO 0 Year Month Day Day of week Hours Minutes Seconds Format if datai PDL RTC READ CAPTURE x Specify PDL_NO_PTR if the flags are not to be read b7 b1 bO
513. ta_length 0 Prepare data for transmission when requested R_IEB_SlaveWrite 0 uint8_t iebus_tx_data_a uint8_t strlen iebus_tx_data_a Monitor channel 0 R_IEB_SlaveMonitor 0 iebus_rx_data amp iebus_rx_data_length IEBus_callback while 1 Has an error occurred if ieb_error true Handle the error General_status 0 Read the General status of channel 0 R_IEB_GetStatus 0 amp General_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR while 1 void IEBus_callback void uint8_t counter uintl6_t received_sum uintl6_t checksum Has data been received R20UT1963EE0100 Rev 1 00 Page 478 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples if iebus_rx_data_length 0 received_sum 0 checksum 0 Analyse the received data for counter 0 counter lt iebus_rx_data_length counter t received_sum iebus_rx_data counter checksum counter 1 Bad data if received_sum checksum while 1 Reset the receive buffer and counter for counter 0 counter lt 32 counter t iebus_rx_data counter OxFF iebus_rx_data_length 0 Tx_status 0 Rx_status 0 Read the status of channel 0 This clears the Tx and Rx status flags Reception is unblocked R_IEB_GetStatus 0 PDL_NO_PTR amp Tx_stat
514. tafec sacral noe anhait lena thet 470 5 20 2 Slave operation USING POIiING 00 2 eee ee eee ee ce ER E EE E Ea 474 5 20 3 Slave operation using interrupts ccccceceeeeeeeeeececeeeeeeecneaeceeeeeeesecsacaeceeeeesesensisaeeseeeeteeenaees 477 521s CRG calctilator cxcse tat ei et ieee ie ae a ee 480 5 22 10 bit Analog to Digital Convert t issis errriecassi rer ine Enine SETETE EAEE ENTER RKE KEA ERATARA EDEA EEE E TE iA 481 5 23 12 bit Analog to Digital Converter nsien nenn ei araa 482 5 24 10 bit Digital to Analog Converter esssseessreesserreessrresrrnnssrrnnestennatnnaesttnaettnnedntuneanuaaentnaaenenneaeenne 483 5 25 Programmable Pulse Generat r inesscinasirairi dnei eea iai eid eii 484 5 26 Temperature Sensor E E EAE staan EN E EA E E E E EA 485 Ge WRX SPECIIC NOLES 2 itee a ie a a aa a a e e aaaea eaa aaae iaiaaeaia 487 6 1 Interrupts and processor mode ccceceeeeeeeeeececeeeceeecaeeeeeeeeesececeaeceeeeeeeseceeaeceeeeeeesetsesiseeeeseeteees 487 6 2 Interrupts and DSP instructions dnnin ie a aaa a aa e aa aa aana 487 R vision FIISTONY ozen cresting ata ta cia cat thesis en ate hi nate Saag ec trea A alee 1 RX63N Group 1 Introduction 1 Introduction The Renesas Peripheral Driver Library RPDL is a unified API for controlling the peripheral modules on the microcontrollers made by Renesas Electronics User application Renesas Peripheral Driver Library Peripherals supporte
515. tch or Input capture A PDL_INTC_VECTOR_OVIO PDL_INTC_VECTOR_TGI11B channel 5 Compare match or Input capture B PDL_INTC_VECTOR_OEI1 Port Output Input level sampling or output level PDL_INTC_VECTOR_OEI2 Enable comparison detection PDL_INTC_VECTOR_CMIAO 8 bit timer TMR Compare match A PDL_INTC_VECTOR_CMIBO channel 0 Compare match B Overflow PDL_INTC_VECTOR_CMIA1 PDL_INTC_VECTOR_CMIB1 PDL_INTC_VECTOR_OVN 8 bit timer TMR channel 1 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA2 PDL_INTC_VECTOR_CMIB2 PDL_INTC_VECTOR_OVI2 8 bit timer TMR channel 2 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA3 PDL_INTC_VECTOR_CMIB3 PDL_INTC_ VECTOR OVI3 8 bit timer TMR channel 3 Compare match A Compare match B Overflow PDL_INTC_VECTOR_ICEEIO PDL_INTC_VECTOR_ICRXIO PDL_INTC_VECTOR_ICTXIO PDL_INTC_VECTOR_ICTEIO C bus interface channel 0 Transfer error or event generation Data received Start of next data transfer End of data transfer PDL_INTC_VECTOR_ICEEI1 PDL_INTC_VECTOR_ICRXI1 PDL_INTC_VECTOR_ICTXI1 PDL_INTC_VECTOR_ICTEI1 PDL_INTC_VECTOR_ICEEI2 PDL_INTC_VECTOR_ICRXI2 PDL_INTC_VECTOR_ICTXI2 PDL_INTC_VECTOR_ICTEI2 C bus interface channe
516. tch signals on TPU channel 7 PDL_DTC_TRIGGER_TPU_TGI8A or PDL_DTC_TRIGGER_TPU_TGI8B or Input capture compare match signals on TPU channel 8 PDL_DTC_TRIGGER_TPU_TGI9A or PDL_DTC_TRIGGER_TPU_TGI9B or PDL_DTC_TRIGGER_TPU_TGI9C or PDL_DTC_TRIGGER_TPU_TGI9D or Input capture compare match signals on TPU channel 9 PDL_DTC_TRIGGER_TPU_TGI10A or PDL_DTC_TRIGGER_TPU_TGI10B or Input capture compare match signals on TPU channel 10 PDL_DTC TRIGGER TPU_TGI11A or PDL_DTC_TRIGGER_TPU_TGI11B or Input capture compare match signals on TPU channel 11 PDL_DTC_TRIGGER_MTU_TGIAO or PDL_DTC_TRIGGER_MTU_TGIBO or PDL_DTC_TRIGGER_MTU_TGICO or PDL_DTC_ TRIGGER MTU_TGIDO or Input capture compare match signals on MTU channel 0 PDL_DTC TRIGGER MTU_TGIA1 or PDL_DTC_TRIGGER_MTU_TGIB1 or Input capture compare match signals on MTU channel 1 PDL_DTC_TRIGGER_MTU_TGIA2 or PDL_DTC_TRIGGER_MTU_TGIB2 or 2tENESAS Input capture compare match signals on MTU channel 2 Page 166 of 487 RX63N Group 4 Library Reference Description 3 4 PDL_DTC_TRIGGER_MTU_TGIA3 or PDL_DTC_ TRIGGER MTU_TGIB3 or PDL_DTC_TRIGGER_MTU_TGIC3 or PDL_DTC_TRIGGER_MTU_TGID3 or Input capture compare match signals on MTU channel 3 PDL_DTC_ TRIGGER MTU_TGIA4 or
517. te 3 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 376 of 487 Jul 19 2012 RX63N Group 4 Library Reference 2 R_TS_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down the Temperature Sensor bool R_TS_Desiroy void No parameter is required Put the Temperature Sensor into the Power down state with minimal power consumption True TS R_TS_Create R_TS_Control e If R_TS_Control is called must wait for A D conversion to finish before calling this function RPDL definitions include r_pdl_ts h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the Temperature Sensor R_TS_Destroy R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 377 of 487 Jul 19 2012 RX63N Group 4 Library Reference 3 R_TS_ Control Synopsis Prototype Description Return value Category Reference Remarks Program example Control the Temperature Sensor bool R_TS_Conirol uint8_t data Temperature Sensor Output control selection Enable or disable the Temperature Sensor output data Control the Temperature Sensor output The default setting is shown in bold PDL_TS_OUTPUT_DISABLE or PDL_TS_OUTPUT_ENABLE Enable or Disable the Temperatur
518. tection feature is enabled the LOCO is started and cannot be stopped e Clearing the main clock Oscillation Stop Detection flag will not succeed until a clock source other than the main oscillator or PLL circuit is selected using parameter data1 Ifthe main clock Oscillation Stop Detection flag is cleared the interrupt output is also disabled Use this function to re enable the interrupt output after the main clock oscillation has been restored e Do not stop a clock that is in use Do not change the clock source if an Operating Power Control Mode transition is taking place see R_LPC_GetStatus If low speed operating mode 2 is selected see R_LPC_Create disable the HOCO If middle speed operating modes 1 or 2 are selected see R_LPC_Create do not change the HOCO power state If low speed operating mode 1 or 2 is selected do not enable the PLL e If the main clock oscillator pins will be used as general I O call this function with PDL_CGC_MAIN_DISABLE and PDL_CGC_MAIN_FORCED_DISABLE selected in parameter data2 e If this function is used to enable a clock oscillator wait for the required settling time before selecting the clock source e If the sub clock oscillator is started after a power on reset the Start type status flag will be set to Warm see R_MCU_GetStatus R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 59 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definit
519. ted clock source in Hertz data4 The desired frequency of the System clock ICLK in Hertz data5 The desired frequency of the Peripheral module A clock PCLKA in Hertz data6 The desired frequency of the Peripheral module B clock PCLKB in Hertz data7 The desired frequency of the Flash memory interface clock FCLK in Hertz data8 The desired frequency of the External Bus clock BCLK and SDRAM clock SDCLK in Hertz If the external bus will not be used specify PDL_NO_DATA data9 The desired frequency of the IEBus clock IECLK in Hertz If the IEBus will not be used specify PDL_NO_DATA R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 55 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value data10 The desired frequency of the USB clock UCLK in Hertz If the USB will not be used specify PDL_NO_DATA True if all parameters are valid and exclusive otherwise false For RX63N the following rules shall be checked e faiN_cLock_oscILLAToR S 20 MHz between 4 and 16 MHZ if a resonator is used fet 104 to 200 MHz ficLk lt 100 MHz fecika lt 100 MHz fecikp lt 50 MHz fectk lt 50 MHz feck lt 100 MHz fecik_pin 50 MHz fspc_k_pin lt 50 MHz fsck lt ficLk fiEBus_cLock lt 50 MHz fusg_cLock lt 48 MHz The frequency of the PLL is achievable main clock x 8 10 12 16 20 24 25 o
520. the IWDT R_IWDT_Set PDL_IWDT_TIMEOUT_1024 PDL_IWDT_CLOCK_OCO_256 Start the IWDT R_IWDT_Control PDL_IWDT_REFRESH Figure 5 26 Example of Independent Watchdog Timer use R20UT1963EE0100 Rev 1 00 Page 422 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 17 Serial Communication Interface 5 17 1 SCI Asynchronous Using Polling This shows the setting of SCI channel 0 and the transmission and reception of data using polling Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Set pin options R_SCI_Set 0 PDL_SCI_PIN_SCIO_RXD0_P21 PDL_SCI_ PIN SCIO TXDO P20 Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC PDL_SCI_8N1 38400 1 0 Wait while send message R_SCI_Send 0 PDL_NO_DATA r nHello Type 5 characters and I will echo them back r n 0 PDL_NO_FUNC Wait for 5 characters to be read R_SCI_Receive 0 PDL_NO_DATA r
521. the LVD registers R_RWP_Control PDL_RWP_ENABLE_LVD_WRITE R20UT1963EE0100 Rev 1 00 R AS Page 128 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 2 R_RWP_GetStatus Synopsis Prototype Description Return value Category Reference Remarks R20UT1963EE0100 Rev 1 00 Jul 19 2012 Program example Get the status of the register protection bool R_RWP_GetStatus uint8_t data1 Status flags pointer uint8_t data2 Status flags pointer Get the status of the register protection data1 The Protect Register PRCR If the value is not required specify PDL_NO_DATA b7 b4 b3 b2 b1 bO LVD Mode and Reset CGC 0 0 Write Disabled 0 0 Write Disabled 0 Write Disabled 1 Write Enabled 1 Write Enabled 1 Write Enabled data2 The MPC Write Protect Register PWPR If the value is not required specify PDL_NO_DATA b7 b6 b5 bO BOWI PFSWE 0 Writing to the PFSWE bit is enabled 1 Writing to the PFSWE bit is disabled 0 Writing to the PFS register is disabled 0 1 Writing to the PFS register is enabled True RWP None RPDL definitions include r_pdl_rwp h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t PRCR_value uint8_t PWPR_value Read the protection registers
522. the Real time clock status flags and T T counters 1 R_WDT_Set Configure the Watchdog timer operation Watchdog Timer 2 R_WDT_Conrtrol Control the Watchdog operation 3 R_WDT_Read Read the Watchdog timer status and registers Independent 1 R_IWDT_Set Configure the Independent Watchdog operation Watchdog Timer 2 R_IWDT_Control Control the Independent Watchdog operation 3 R_IWDT_Read Read the watchdog timer status and counter R20UT1963EE0100 Rev 1 00 Jul 19 2012 stENESAS Page 52 of 487 RX63N Group 4 Library Reference C bus interface 1 R_SCI_Set Configure the SCI pin selection 2 R_SCI_Create SCI channel setup 3 R_SCI_Destroy Shut down a SCI channel 4 R_SCl_Send Send a string of characters Serial 5 R_SCI_Receive Receive a string of characters Communication 6 R_SCI_SPI_Transfer Perform an SCI SPI transfer Interface 7 R_SCI_IIC_Write Perform an SCI IIC master write 8 R_SCI_IIC_Read Perform an SCI IIC master read 9 R_SCI_lIC_ReadLastByte Finish an SCI master read if using DMAC or DTC 10 R_SCl_Control Control the SCI channel 11 R_SCl_GetStatus Check the status of an SCI channel R_IIC_Create lC channel setup R_IIC_Destroy Disable an C channel R_IIC_MasterSend Write data to a slave device R_IIC_MasterReceive Read data from a slave device R_IIC_MasterReceiveLast Complete a DMAC or DTC based read process R_
523. the general register B value shall be stored Specify PDL_NO_PTR if it is not required data6 Where the general register C value shall be stored Specify PDL_NO_PTR if it is not required data7 Where the general register D value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Timer Pulse Unit e Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to 0 by this function e Channels 6 to 11 are not available for device packages with 100 pins R20UT1963EE0100 Rev 1 00 Jul 19 2012 ztENESAS Page 219 of 487 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_tpu h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uintl6_t General_A uintl6_t General_D void func void Read the status flags and registers A and D for channel TPUO R_TPU_Read 0 amp Flags PDL_NO_PTR amp General_A PDL_NO_PTR PDL_NO_PTR amp General_D R20UT1963EE0100 Rev 1 00 AS Page 220 of 487 Jul 19 2012 RENES RX63N Group 4 Library Reference 4 2 17 Programmable Pulse Generator 1 R_PPG_Create Synopsis Prototype Description 1 2 Configure a PPG group bool R_PPG_Create uint32_t data1 Output pin selection uint16_t data2 Configuration selection
524. the oscillation stop detection function PDL_CGC_OSC_STOP_DISABLE for the main clock oscillator e Main clock Oscillation Stop Detection flag control PDL_CGC_OSC_STOP_CLEAR FLAG Clear the main clock oscillation stop detection flag e SDCLK signal control PDL_CGC_SDCLK_ENABLE or Enable or disable the SDRAM clock SDCLk PDL_CGC_SDCLK_DISABLE signal R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 58 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 data3 Clock control selection All selections are optional If no change is required specify PDL_NO_DATA If multiple selections are required use to separate each selection Sub clock oscillator control PDL_CGC_SUB_CLOCK_ENABLE or PDL_CGC_SUB_CLOCK_DISABLE PLL control Enable or disable the sub clock oscillator PDL_CGC_PLL_ENABLE or PDL_CGC_PLL_DISABLE Enable or disable the PLL circuit IWDT dedicated low speed on chip oscillator control PDL_CGC_IWDTLOCO_ENABLE or PDL_CGC_IWDTLOCO_DISABLE Enable or disable the IWDTLOCO Return value True if all parameters are valid and exclusive and a selected clock source has been configured otherwise false Category Clock generation circuit References R_CGC_Set R_LPC_GetStatus R_LPC_Create Remarks e Use R_CGC_Set to configure a clock source before selecting it While the main clock Oscillation Stop De
525. the status registers for the MCU data1 The status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required b15 b14 b13 b12 b9 b8 User boot mode 0 0 Other 0 1 1 Selected b7 b5 b4 b1 bO Endian mode MD pin level at release from reset 000b Big 0 0 Low 111b Little 1 High data2 The reset status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required b15 b9 b8 Start type 0 0 Cold 1 Warm b7 b6 b5 b4 b3 b2 b1 bO Reset detection flags 0 not detected 1 detected i Exit from deep Software WDT IWDT Voltage monitor software standby 2 7 0 Power on data3 Where the OFSO register contents shall be stored Please refer to the MCU hardware manual for the format Specify PDL_NO_PTR if they are not required data4 Where the OFS1 register contents shall be stored Please refer to the MCU hardware manual for the format Specify PDL_NO_PTR if they are not required Return value True Category MCU registers References None Remarks Ifa reset detection flag is set to 1 it shall be automatically cleared to 0 by this function R20UT1963EE0100 Rev 1 00 ZEN ESAS Page 107 of 487 Jul 19 2012 RX63N Group 4 Library Reference Program example RPDL definitions include r_pdl_mcu h RPDL device specific definitions include r_pdl
526. ther the function to be called when each byte is transferred or DMAC PDL_NO_FUNC if the callback function specified in R_LDMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_SCl_GetStatus R_SCI_IIC_ReadLastByte R_SCI_Control Remarks Program example The maximum number of characters to be received is 65535 e Wait until a transmission on the same channel is complete before calling this function Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed e This function unless configured not to will by default automatically start a transfer by generating a Start condition and finish with a Stop condition However if using DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_IIC_ReadLastByte or R_SCI_Control function to manually generate a stop The last byte of a master read will automatically be NACK d However if using DMAC or DTC this will not happen If a NACK is required then use the DMAC DTC to read all the data except for the last byte and then use function R_SCI_IIC_
527. timer unit bool R_TPU_Destroy uint8_t data Unit selection Shut down a timer pulse unit data The timer pulse unit n where n 0 or 1 Unit 0 comprises channels TPUO to TPUS Unit 1 comprises channels TPU6 to TPU11 True if the unit selection is valid otherwise false Timer Pulse Unit The timer pulse unit is put into the stop state to reduce power consumption e Unit 1 is not available for device packages with 100 pins include r_pdl_tpu h void func void Shutdown TPU unit 0 channels 0 to 5 R_TPU_Destroy 0 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 216 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_TPU_Conirol Synopsis Control a timer channel Prototype bool R_TPU_Control uint8_t data1 Channel selection uint8_t data2 Register selection uint16_t data3 Register value uint16_t data4 Register value uint16 tdata5 Register value uint16_t data6 Register value uint16_t data7 Register value Description Modify a timer channe s registers data1 The channel number n where n 0 to 11 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start PDL_TPU_STOP or PDL_TPU_START Disable or re enable the counter clock source e The registers to be modified
528. tion to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address data4 The number of data bytes that must be transferred before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The start address of the buffer that contains the data to be written Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to send the data R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 299 of 487 Jul 19 2012 RX63N Group 4 Library Reference Description 2 2 Return value Category Reference func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer Parameter method PDL_NO_FUNC This function will continue until the required number of bytes Pollin 9 has been transferred or an error occurs Interrupts The function to be called when the transfer has completed or an error detected Either the function to be called when each byte is transferred or PDL_NO_FUNC BRAG if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R
529. to the CRC calculation register Prototype bool R_CRC_Write uint8_t data The data to be used for the calculation Description Write the data into the data input register data The data to be written into the register Return value True Category CRC Reference R_CRC_Create Remarks e None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Write FOh into the CRC calculation register R_CRC_Write OxFO R20UT1963EE0100 Rev 1 00 R AS Page 354 of 487 Jul 19 2012 SENES RX63N Group 4 Library Reference 4 R_CRC_Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read the CRC calculation result bool R_CRC_Read uint8_t data1 Control uint16_t data2 Data storage location Reads and stores the CRC calculation result data1 Control the behaviour of the CRC unit The default setting is shown in bold Specify PDL_NO_DATA to use the default e Result register clearing PDL_CRC_CLEAR_RESULT or PDL_CRC_RETAIN_RESULT Clear or retain the value in the result register data2 The address of the location where the result shall be stored For the 8 bit polynomial the results are store
530. totype bool R_PPG_Control uint32_t data1 Group selection uint8_t data2 Next output values Description Set the next output for a PPG group data1 Select the group s to be modified If multiple selections are required use to separate each selection e Group selection PDL_PPG_GROUP_0 or PDL_PPG_GROUP_1 or PDL_PPG_GROUP_2 or PDL_PPG_GROUP_3or If a pair of groups 0 1 2 3 4 5 or 6 7 is using the same output PDL_PPG_GROUP_4 or trigger both groups may be selected PDL_PPG_GROUP_5 or PDL_PPG_GROUP_6 or PDL_PPG_GROUP_7 data2 The next output values either for a single group or a pair of groups using the format Group 1 3 5or7 Group 0 2 4 or 6 Group pair b7 b6 b5 b4 b3 b2 b1 bO 1 amp 0 PO7 PO6 PO5 PO4 PO3 PO2 PO1 POO 3 amp 2 PO15 PO14 PO13 PO12 PO11 PO10 POY PO8 5 amp 4 PO23 PO22 PO21 PO20 PO19 PO18 PO17 PO16 7 amp 6 PO31 PO30 PO29 PO28 PO27 PO26 PO25 PO24 Return value True if all parameters are valid and exclusive otherwise false Category Programmable Pulse Generator Reference R_PPG Create Remarks e None Program example RPDL definitions include r_pdl_ppg h RPDL device specific definitions include r_pdl_definitions h void func void Load the next output values on group 6 R_PPG_Control PDL_PPG_GROUP_6 0x07 i
531. tput low goes high at compare match MTIOCnC initial output low toggles at compare match MTIOCnC initial output high goes low at compare match MTIOCnC output high MTIOCnC initial output high toggles at compare match PDL_MTU2_C_IC_RISING_EDGE or PDL_MTU2_C_IC_FALLING EDGE or PDL_MTU2_C_IC_ BOTH EDGES or Input capture at MTIOCnC rising edge Input capture at MTIOCnC falling edge Input capture at MTIOCnC both edges PDL_MTU2_C_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0 Input capture output compare control for register TGRD PDL_MTU2_D_OC DISABLED or PDL_MTU2_D_OC_LOW or PDL_MTU2_D_OC_LOW_CM HIGH or PDL_MTU2_D_OC_LOW_CML_INV or PDL_MTU2_D_OC_HIGH_CM_LOW or PDL_MTU2_D_OC_HIGH or PDL_MTU2_D_OC_HIGH_CM_INV or MTIOCnD output disabled MTIOCnD output low MTIOCnD initial output low goes high at compare match MTIOCnD initial output low toggles at compare match MTIOCnD initial output high goes low at compare match MTIOCnD output high MTIOCnD initial output high toggles at compare match PDL_MTU2_D_IC_RISING_EDGE or PDL_MTU2_D_IC_FALLING EDGE or PDL_MTU2_D_IC BOTH EDGES or Input capture at MTIOCnD rising edge Input capture at MTIOCnD falling edge Input capture at MTIOCnD both edges PDL_MTU2_D_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0
532. tput toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or No change if a compare match B occurs PDL_TMR_OUTPUT_LOW_CM_B or 0 is output if a compare match B occurs PDL_TMR_OUTPUT_HIGH_CM_B or 1 is output if a compare match B occurs PDL_TMR_OUTPUT_INV_CM_B The output toggles if a compare match B occurs data4 The 16 bit counter value data5 The 16 bit compare match A value data6 The 16 bit compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 and funcs3 Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_Set Remarks e Please use R_TMR_Set to select the input TMCIn TMRIn and output TMOn pins as required This function will return false if a pin is enabled but is not set properly e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 e Acallback function is executed by the interrupt processing
533. trigger control for TGRB PDL_TPU_TGRB_DTC_TRIGGER_DISABLE or Enable activation of the DTC when a PDL TPU TGRB DTC TRIGGER ENABLE TGRB compare match occurs e DTC trigger control for TGRC valid for n 0 3 6 and 9 PDL_TPU_TGRC_DTC_TRIGGER_DISABLE or Enable activation of the DTC when a PDL_TPU_TGRC_DTC_TRIGGER_ENABLE TGRB compare match occurs e DTC trigger control for TGRD valid for n 0 3 6 and 9 PDL_TPU_TGRD_DTC_TRIGGER_DISABLE or Enable activation of the DTC when a PDL_TPU_TGRD_DTC_TRIGGER_ENABLE TGRB compare match occurs data3 Configure the counter operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Counter clock source selection PDL_TPU_CLK_PCLK_DIV_1 or PDL_TPU_ CLK PCLK_DIV_4 or PDL_TPU_CLK_PCLK_DIV_16 or PDL TPU CLK PCLK DIV 64 or PDL TPU CLK PCLK _ DIV_ 256 or PCLK 256 Valid for n 1 3 5 7 9 and 11 PDL_TPU_CLK_PCLK_DIV_1024 or PCLK 1024 Valid for n 2 3 4 8 9 and 10 PDL_TPU CLK PCLK _ DIV 4096 or PCLK 4096 Valid for n 3 and 9 The internal clock signal PCLK 1 4 16 or 64 PDL_TPU_CLK_TCLKA or TCLKA pin input Valid for n 0 to 5 PDL_TPU_CLK_TCLKB or TCLKB pin input Valid for n 0 1 and 2 PDL_TPU_CLK_TCLKC or TCLKC
534. trol Synopsis Control register write protection Prototype bool R_RWP_Control uint8_t data II Configuration selection Description Control register write protection data Write enable control To set multiple options at the same time use to separate each value e Register write control PDL_RWP_ENABLE_CGC_WRITE or Enable or disable writing to CGC PDL_RWP_DISABLE_CGC_WRITE registers PDL_RWP_ENABLE_MODE_RESET_WRITE or Enable or disable writing to Mode and PDL_RWP_DISABLE_MODE_RESET_WRITE Reset registers PDL_RWP_ENABLE_LVD_WRITE or Enable or disable writing to LVD PDL_RWP_DISABLE_LVD_WRITE registers PDL_RWP_ENABLE_MPC_WRITE or Enable or disable MPC Register PDL_RWP_DISABLE_MPC_WRITE access Return value True if the parameter is valid otherwise false Category RWP References Remarks To allow for nested function calls the access to the enabling disabling of register protection is done using a reference counting method Hence a call to disable a register access may only decrement a reference counter and not actually apply the write protection e Other RPDL functions automatically enable and disable access to registers as required so this function is normally not required Program example RPDL definitions include r_pdl_rwp h RPDL device specific definitions include r_pdl_definitions h void func void Enable access to
535. trolling the interrupt priority 3 1 0 Port These driver functions are used to configure the I O pins and provide data read write compare and modify operations 4 Port Function These driver functions are used for configuring the I O pin optional functions 5 MCU Operation These driver functions are used for configuring the MCU operation 6 Low Power Consumption These driver functions are used for selecting lower power consumption 7 Voltage Detection Circuit These driver functions are used for configuring the low voltage detection response 8 Bus Controller These driver functions are used for configuring the external address bus data bus and chip select pins and handling any bus errors 9 DMA Controller These driver functions are used for configuring and controlling the transfer of data within the address space 10 External DMA Controller These driver functions are used for configuring and controlling the transfer of data within the address space 11 Data Transfer Controller These driver functions are used for configuring and controlling the transfer of data triggered by peripheral interrupts 12 Multi Function Timer Pulse Unit These driver functions are used for configuring and controlling the multi function timers 13 Port Output Enable These driver functions are used for additional configuring and controlling of the timer outputs 14 Programmable Pulse Generator These driver functions are used f
536. ts a10 a9 and a8 ii The first byte after the slave address is the EEPROM memory address bits a7 to a0 The EEPROM has a write cycle time of 5 ms The following examples illustrate the use of Master mode R20UT1963EE0100 Rev 1 00 R AS Page 446 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 1 Configuration and transmission The MCU s I C channel 0 will be configured for Master operation and used to send 4 bytes to a slave Siveasiass e ba A oma om ATP Figure 5 39 The bus activity showing 4 bytes being transmitted to the EEPROM Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h define EEPROM_ADDRESS 0xA0 void main void const uint8_t eeprom_data_array_1 5 0x00 0x01 0x02 0x03 0x04 uint8_t data_storage 5 uint32_t status_flags 0 uintl6_t TxChars uintlo6_t RxChars Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 300 lt lt 16 200 Send the sub address and 3 bytes to the EEPROM using
537. ude r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h uintl6_t WDT_Status void func void Read the timer values R_WDT_Read amp WDT_Status R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tEN ESAS Page 274 of 487 RX63N Group 4 Library Reference 4 2 22 1 R_IWDT Set Synopsis Prototype Description Independent Watchdog Timer Configure the Independent Watchdog operation bool R_IWDT_Sei uint32_t data Configuration selection Select the operation of the Independent Watchdog timer and start it data Configure the timer options Use to separate each value Counter selection PDL_IWDT_TIMEOUT_1024 or PDL_IWDT_TIMEOUT_4096 or PDL_IWDT_TIMEOUT_8192 or PDL_IWDT_TIMEOUT_16384 The number of cycles of the selected clock before the reset occurs PDL_IWDT_CLOCK_OCO_1 or PDL_IWDT_CLOCK_OCO_16 or PDL_IWDT_CLOCK_OCO_32 or PDL_IWDT_CLOCK_OCO_64 or PDL_IWDT_CLOCK_OCO_ 128 or PDL_IWDT_ CLOCK _OCO_ 256 Clock division ratio selection The IWDTCLK clock 1 16 32 64 128 or 256 Time out control PDL_IWDT_TIMEOUT_NMI or PDL_IWDT_TIMEOUT_RESET If the IWDT times out select if a Reset or an NMI Interrupt will be generated Window Start Position PDL_IWDT_WIN_START_25 or PDL_IWDT_WIN_START_50 or PDL_IWDT_WIN_START_75 or PDL_IWDT_WIN_START_100
538. uint16_t data3 Slave address uint8_t data4 Data start address uint16_tdata5 Data count void func Callback function uint8_t data6 Interrupt priority level Transmit data on the specified channel data1 Select channel IICn where n 0 to 3 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Start Repeated Start condition control PDL_IIC_START_ENABLE or Choose whether or not to issue a Start or Repeated Start PDL_IIC_START_DISABLE condition at the beginning of the transfer e Stop condition control PDL_IIC_STOP_ENABLE or Choose whether or not to issue a Stop condition at the end PDL_IIC_STOP_DISABLE of the transfer e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_TRIGGER_ENABLE transmitted data3 The address of the slave device Ignored if the Start condition is disabled data4 The start address of the data to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data5 The number of bytes to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the requi
539. uint8_t data3 Output values Set up a 4 bit PPG group data1 Select the outputs to be enabled If multiple selections are required use to separate each selection Select only outputs within one group PDL_PPG_POO_PIN_P20 PDL_PPG PO1 PIN P21 PDL_PPG PO2 PIN P22 PDL_PPG PO3 PIN P23 PDL_PPG PO4 PIN P24 PDL_PPG PO5 PIN P25 PDL_PPG PO6 PIN P26 PDL_PPG PO7_PIN P27 PDL_PPG PO8 PIN P30 PDL_PPG PO9 PIN P31 PDL_PPG PO10 PIN P32 PDL_PPG PO11_ PIN P33 PDL_PPG_PO12 PIN P34 PDL_PPG_PO13 PIN P13 or PDL_PPG_PO13 PIN P15 PDL_PPG PO14 PIN P16 PDL_PPG_PO15 PIN_P14 or PDL_PPG PO15 PIN P17 PDL_PPG_PO16_PIN_P73 or PDL_PPG_PO16 PIN PAO PDL_PPG_PO17_PIN_PA1 or PDL_PPG_PO17_PIN PCO PDL_PPG_PO18 PIN _PA2 or Group 4 PDL_PPG_PO18 PIN_PC1 or PDL_PPG_PO18 PIN PE1 PDL_PPG_PO19 PIN P74 or PDL_PPG_PO19 PIN PA3 PDL_PPG_PO20_PIN_P75 or PDL_PPG_PO20_ PIN PA4 PDL_PPG_PO21_PIN_PAS or PDL_PPG_PO21_PIN PC2 PDL_PPG_PO22 PIN P76 or Group 5 PDL_PPG_PO22 PIN PAG PDL_PPG_PO23 PIN_P77 or PDL_PPG_PO23_PIN_PA7 or PDL_PPG_PO23 PIN PE2 Group 0 Group 1 Unit 0 Group 2 Group 3 Unit 1 R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 221 of 487 Jul 19 201
540. uired use to separate each selection PDL_INTC_GRPn_ALL can be used to specify all applicable selections Group 0 selections PDL_INTC_GRPO_ERSO PDL_INTC_GRPO ERS1 PDL_INTC_GRPO_ERS2 Error on CAN channels 0 1 or 2 Group 1 selections PDL_INTC_GRP1_TCIVO PDL_INTC_GRP1_TCIV1 PDL_INTC_GRP1_TCIU1 Overflow on MTU channels 0 or 1 Underflow on MTU channel 1 Group 2 selections PDL_INTC_GRP2_TCIV2 PDL_INTC_GRP2_TCIU2 PDL_INTC_GRP2_TCIV3 Group 3 selections Overflow on MTU channels 2 or 3 Underflow on MTU channel 3 PDL_INTC_GRP3_TCIOV PDL_INTC_GRP3_TCI1V PDL_INTC_GRP3_TCI1U PDL_INTC_GRP3_TCI5V PDL_INTC_GRP3_TCI5U Overflow on TPU channels 0 1 or 5 Underflow on TPU channels 1 or 5 Group 4 selections PDL_INTC_GRP4_TCl2V PDL_INTC_GRP4_TCI2U PDL_INTC_GRP4_ TCI3V PDL_INTC_GRP4 TCI4V PDL_INTC_GRP4_TCI4U Overflow on TPU channels 2 3 or 4 Underflow on TPU channels 2 or 4 Group 5 selections PDL_INTC_GRP5_TCI6V PDL_INTC_GRP5_TCI7V PDL_INTC_GRP5_TCI7U PDL_INTC_GRP5_TCI11V PDL_INTC_GRP5_TCI11U Overflow on TPU channels 6 7 or 11 Underflow on TPU channels 7 or 11 R20UT1963EE0100 Rev 1 00 Jul 19 2012 2tENESAS Page 84 of 487 RX63N Group 4 Library Reference Description
541. uired use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop start Valid for n 0 to 4 PDL_MTU2_STOP Stop the count operation PDL_MTU2_START Start the count operation Counter stop Start Valid for n 5 PDL_MTU2_STOP_U PDL_MTU2_STOP_V Stop the count operation PDL_MTU2_STOP_W PDL_MTU2_START_U PDL_MTU2_START_V_ Start the count operation PDL_MTU2_START_W register_selection The channel registers to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no register change is required e The registers to be modified Forn 0 to 4 PDL_MTU2_REGISTER_COUNTER _ Timer counter register TCNT PDL_MTU2_REGISTER_TGRA General register A PDL_MTU2_REGISTER_TGRB General register B PDL MTU2 REGISTER_TGRC General register C Valid for n 0 3 or 4 PDL_MTU2_REGISTER_TGRD General register D Valid for n 0 3 or 4 PDL_MTU2_REGISTER_TGRE General register E Valid for n 0 PDL_MTU2_REGISTER_TGRF General register F Valid for n 0 ADC start request cycle set buffer A PDL_MTU2_REGISTER_TADCOBRA Valid for n 4 ADC start request cycle set buffer B PDL_MTU2_REGISTER_TADCOBRB Valid for n 4 R20UT1963EE0100 Rev 1 00 ae ENESAS Page 188 of 487 Jul 19 2012 RX63N Group 4 Library Reference Descri
542. ultiple selections are required use to separate each selection The default settings are shown in bold e Period or frequency calculation PDL_TMR_PERIOD or PDL_TMR_FREQUENCY The parameters data3 and data4 will contain either period and pulse width or frequency and duty cycle e Output pin control PDL_TMR_OUTPUT_HIGH or PDL_TMR_OUTPUT_LOW or PDL_TMR_OUTPUT_OFF Start with a high level or low level output or no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 e ADC trigger control PDL_TMR_ADC_TRIGGER_OFF or PDL_TMR_ADC_TRIGGER_ON Disable or enable TMR triggered ADC conversion start requests Applicable only for channels TMRO or TMR2 or either TMR unit e Pulse DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR_PULSE_DTC_TRIGGER_ENABLE DTC at the pulse width interval Period DTC trigger control PDL_TMR_PERIOD_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR_PERIOD_DTC_TRIGGER_ENABLE DTC at the periodic interval data3 The period in seconds or frequency in Hz data4 The pulse width in seconds or duty cycle funct The function to be called at the pulse width interval Use PDL_NO_FUNC if not required func2 The function to be called at the periodic interval Use PDL_NO_FUNC if not required R20UT1963EE0100 Rev 1 00
543. unit 0 R_MTU2_ReadUnit 0 amp Sub_count amp Skip_count R20UT1963EE0100 Rev 1 00 Page 199 of 487 Jul 19 2012 RENESAS RX63N Group 4 Library Reference 4 2 15 Port Output Enable 1 R_POE Set Synopsis Prototype Description 1 2 Configure the Port Output Enable module bool R_POE_Set uint32_t data1 Input configuration selection uint16_t data2 Input POEn pin selection uint16_tdata3 Output configuration selection Initialise the POE pins data1 Configure the input pin detection for pins POEO to POE3 and POE8 If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required PDL_POE_0 MODE_EDGE or PDL_POE_0 MODE_LOW_8 or PDL_POE_0 MODE_LOW_16 or PDL_POE_0 MODE LOW_128 PDL_POE_1_MODE_EDGE or PDL POE 1 MODE LOW 8 or PDL POE 1 MODE LOW 16 or PDL_POE_1 MODE _LOW_128 PDL POE 2 MODE EDGE or PDL POE 2 MODE LOW _8 or PDL_POE_2 MODE LOW _16 or PDL_POE_2 MODE _LOW_128 PDL POE 3 MODE EDGE or PDL_POE_3 MODE LOW _8 or PDL POE 3 MODE LOW 16 or PDL POE 3 MODE LOW 128 PDL_POE 8 MODE EDGE or PDL POE 8 MODE LOW 8 or PDL POE 8 MODE LOW 16 or PDL_POE_8 MODE LOW_128 For each pin POEO to POE3 and POE8 select falling edge or low level for 16 samples at PCLKB 8 16 or 128 data2 Alloc
544. us amp Rx_status PDL_NO_PTR PDL_NO_PTR Slave transmission complete if Tx_status amp BIT_5 0 Prepare new data to be sent R_IEB_SlaveWrite 0 uint8_t iebus_tx_data_b uint8_t strlen iebus_tx_data_b Are any error flags set if Tx_status amp 0x0F 0 Rx_status amp 0x1F 0 ieb_error true Figure 5 53 Example of IEBus Slave use with interrupts R20UT1963EE0100 Rev 1 00 Page 479 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 21 CRC calculator Figure 5 54 shows an example of CRC usage The payload and CRC checksum have been received from a remote unit The CRC calculator is used to check that the payload is correct Peripheral driver function prototypes include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void main void uintl6_t crc_result Configure the CRC to use the CCITT polynomial R_CRC_Create PDL_CRC_POLY_CRC_CCITT PDL_CRC_LSB_FIRST Write the payload data R_CRC_Write OxFO i Write the first half of the CRC checksum R_CRC_Write Ox8F Write the second half of the CRC checksum R_CRC_Write OxE7 3 Read the CRC calculation result Expected result is 0 R_CRC_Read PDL_NO_DATA amp crc_result Shutdown the CRC unit R_CRC_Destroy 3 Figure 5 54 E
545. us_rx_data_length volatile uint8_t Tx_status volatile uint32_t Rx_status void IEBus_callback void const char iebus_tx_data_a First slave message const char iebus_tx_data_b Second slave message void main void uintl6_t General_status Configure main clock operation using a 12 0 MHz clock R_CGC_Set PDL_CGC_CLK_MAIN CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABL a DANANAAE r L_NO_DAT L_NO_DAT L_NO_DAT UUUHFHAHANUD P ik 3 3 3 3 P P P Configure PLL operation The PLL will be set to 192 MHz ICLK 96 MHz PCLKA 48 MHz PCLKB 48 MHz FCLK 48 MHz IECLK 24 Mhz R_CGC_Set PDL CGC CEK PEL PDL_CGC_BCLK_DISABLE PDL_CGC_SDCLK_DISABL 192E6 96E6 48E6 48E6 48E6 PDL_NO_DAT 24E6 PDL_NO_DAT Allow 100 ps for the main clock to stabilise R_CMT_CreateOneShot 0 PDL_NO_DATA 100E 6 PDL_NO_FUNC R20UT1963EE0100 Rev 1 00 Page 477 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Select the PLL R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Use port C for the IEBus pins R_IEB_Set PDL_IEB_PIN_IERXD_PC2 PDL_IEB_PIN_IETXD_PC3 Configure IEBus channel 0 R_IEB_Create 0 PDL_IEB_MODE_1 PDL_IEB_POLARITY_HIGH 0x0345 15 di ieb_error false iebus_rx_da
546. using this function e This function configures each I C pin that is required for operation It also disables the alternative modes on those pins e This function will return false if fast mode plus mode is selected for a channel other than channel 0 e Channels 1 and 3 are not available with the 100 pin package This function will return false in this case The 7 or 10 bit slave addresses should use the format b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 310 of 487 Jul 19 2012 RX63N Group 4 Library Reference The timing limits depend on the frequency of the internal reference clock IRC 1 t an ICBRH 1 t ire UCBRL 1 tre Lise The maximum transfer rate is given when ICBRH ICBRL 0 the minimum when ICBRH Transfer _ rate ICBRL 31 The absolute limits with zero rise and fall times are fecike MHz fire 50 48 12 5 12 32 8 f 1 781 kbps to 750 kbps to 195 kbps to 187 5 kbps to 500 kbps to 125 kbps to BECKS 25 0 Mbps 24 0 Mbps 6 25 Mbps 6 0 Mbps 16 0 Mbps 4 00 Mbps fpcikp 2 391 kbps to 375 kbps to 97 7 kbps to 93 75 kbps to 250 kbps to 62 5 kbps to 12 5 Mbps 12 0 Mbps 3 13 Mbps 3 0 Mbps 8 00 Mbps 2 00 Mbps fpciks 4 195 kbps to 187 5 kbps to 48 8 kbps to 46 875 kbps 125 kbps to 31 3 kbps to 6 25 Mbps 6 0 Mbps 1 56 Mbps to 1 5 Mbps 4 00 Mbps 1 00 Mbps fecik
547. utput of the A7 to AO signals PDL_BSC_A8_ DISABLE Disable the output of the A8 signal PDL_BSC_A9 DISABLE Disable the output of the A9 signal PDL_BSC_A10_DISABLE Disable the output of the A10 signal PDL_BSC_A11_DISABLE Disable the output of the A11 signal PDL_BSC_A12 DISABLE Disable the output of the A12 signal PDL_BSC_A13_DISABLE Disable the output of the A13 signal PDL_BSC_A14_DISABLE Disable the output of the A14 signal PDL_BSC_A15_DISABLE Disable the output of the A15 signal PDL_BSC_A16 DISABLE Disable the output of the A16 signal PDL_BSC_A17_DISABLE Disable the output of the A17 signal PDL_BSC_A18_ DISABLE Disable the output of the A18 signal PDL_BSC_A19_ DISABLE Disable the output of the A19 signal PDL_BSC_A20_DISABLE Disable the output of the A20 signal PDL_BSC_A21_DISABLE Disable the output of the A21 signal PDL BSC A22 DISABLE Disable the output of the A22 signal PDL BSC A23 DISABLE Disable the output of the A23 signal PDL_BSC_A23_A16_DISABLE can be used to disable the signals A23 to A16 e SDRAM output control PDL_BSC_SDRAM_PINS DISABLE or PDL_BSC_SDRAM PINS ENABLE Enable or disable the SDRAM Pins except the DQM1 pin PDL_BSC_SDRAM_DQM1_DISABLE or PDL_BSC_SDRAM_DQM1_ENABLE Enable or disable the DQM1 pin
548. v 1 00 2tEN ESAS Page 169 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_DTC_Control Synopsis Prototype Description Return value Control the Data Transfer Controller bool R_DTC_Conirol uint32_t data1 II Control options uint32_t data2 Transfer data start address void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint8_t data6 II Block size Modify the operation of the Data Transfer Controller data1 Control the operation e Stop Start control PDL_DTC_STOP or PDL_DTC_START Enable re enable or suspend DTC transfers e The transfer registers to be modified using the selected parameters PDL_DTC_UPDATE_SOURCE a Address register using parameter PDL_DTC_UPDATE_DESTINATION Ua Address register using parameter PDL_DTC_UPDATE_COUNT The Transfer Count register using parameter data5 PDL_DTC_UPDATE_BLOCK_SIZE The Block Size register using parameter data6 e Transfer trigger control When the transfer count specified in R_DTC_Create is completed the DTC will ignore further interrupts from that trigger source If you require the interrupt to trigger another transfer specify the trigger used in the relevant call of R_DTC_Create data2 If transfer registers are to be modified specify the start address of the transfer data area the same as th
549. void static void StoreData uintl6_t count Current memory address volatile uint8_t data_storage_index 0 volatile uint8_t data_storage STORAGE_SIZ volatile uint8_t Rx_Buffer RX_BUFFER_SIZ void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select IIC mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create SLAVE_CHANNEL DL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 DL_IIC_SLAVE_0_ENABLE_7 AVE_ADDRESS DL_NO_DATA DL_NO_DATA 100E3 300 lt lt 16 200 Start monitor the channel R_IIC_SlaveMonitor SLAVE_CHANNEL PDL_NO_DATA Rx_Buffer RX_BUFFER_SIZ slave_callbac 7 The rest is interrupt driven while 1 R_IIC_SlaveMonitor or R_IIC_SlaveSend callback static void slave_callback void uint32_t status_flags 0 uintl6_t tx_count 0 uintl6_t rx_count 0 bool bStartMonitor true R20UT1963EE0100 Rev 1 00 Page 458 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples Read the status R_IIC_GetStatus SLAVE_CHANNEL amp status_flags amp tx_count amp rx_count Has the master just completed a write if rx_count 0 StoreData rx_count Start monitori
550. void func void Disable the IRQ1 interrupt pin and clear the flag R_INTC_ControlExtInterrupt PDL_INTC_IRQ1 PDL_INTC_DISABLE PDL_INTC_CLEAR_IR_FLAG i R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 73 of 487 Jul 19 2012 RX63N Group 4 Library Reference 7 R_INTC_GeiExtInterruptStatus Synopsis Prototype Description Return value Category Reference Remarks Program example Read the external interrupt status bool R_INTC_GetExtInterruptStatus uint8_t data1 Pin selection uint8_t data2 Apointer to the buffer where the status data shall be stored Acquire the status for the specified external interrupt data1 Choose the interrupt pin to be checked PDL_INTC_IRQn n 0 to 15 or IRQn n 0 to 15 interrupt pin or PDL_INTC_NMI NMI interrupt pin data2 The status flags shall be stored in the following format For an IRQ pin b7 b4 b3 b2 b1 bO Detection condition Current level Status 00 Low level 0 01 Falling edge 0 Low 0 Not detected 10 Rising edge 1 High 1 Detected 11 Both edges For the NMI interrupt b7 b6 b5 b4 b3 b2 b1 bO Other interrupt request NMI pin Underflow Oscillation Current Detection LVD2 LVD1 WDT WDT stop level condition Request status 0 Not detected 0 Low 0 Falling 0 Not detected 1 Dete
551. will monitor the status flags to manage the data transmission If the 1 C channel s registers are modified directly by the user this function may lock up If false is returned use R_IIC_GetStatus to check if an unexpected event on C bus was the cause of the failure If the transfer has ended prematurely use R_IIC_Control to issue a Stop condition False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create False will be returned if the bus is busy due to another master on the bus Channels 1 and 3 are not available with the 100 pin package This function will return false in this case RPDL definitions nclude r_pdl_iic h RPDL device specific definitions nclude r_pdl_definitions h Fi nst uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFI id func void Send 5 bytes to device 0x0A0 on channel 0 using polling R_IIC_MasterSend 0 PDL_NO_DATA OxOAO data_array 5 PDL_NO_FUNC 0 R20UT1963EE0100 Rev 1 00 2tENESAS Page 315 of 487 Jul 19 2012 RX63N Group 4 Library Reference 4 R_lIC_MasterReceive Synopsis Prototype Description Return value Read data from a slave device bool R_IIC_MasterReceive uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_tdata5 Receive thre
552. x_buffer 5 PDL_NO_FUNC PDL_NO_FUNC Echo the 5 characters back R_SCI_Send 0 PDL_NO_DATA rx_buffer R20UT1963EE0100 Rev 1 00 Page 423 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 PDL_NO_FUNC Figure 5 27 Example of SCI asynchronous operation using polling R20UT1963EE0100 Rev 1 00 R AS Page 424 of 487 Jul 19 2012 SENES RX63N Group 5 Usage Examples 5 17 2 SCI Asynchronous Using Interrupts This shows the setting of SCI channel 0 and the transmission and reception of data using interrupts Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void SCIrx void void SCItx void volatile bool data_received volatile bool data_sent void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Initialise flags data_sent false data_received false Set pin options R_SCI_Set 0 PDL_SCI_PIN_SCIO_RXDO_P21 PDL_SCI_PIN_SCIO_TXDO_P20 Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC PDL_SCI_8N1 384
553. xample of CRC calculation R20UT1963EE0100 Rev 1 00 Page 480 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 22 10 bit Analog to Digital Converter Figure 5 55 shows an example of ADC_10 usage Peripheral driver function prototypes include r_pdl_adc_10 h include r_pdl_cgc h RPDL device specific definitions include r_pdli_definitions h uintl6e_t result_adc0O 8 void ADCO_callback void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure analog input R_ADC_10_Set PDL_ADC_10_PIN_ANO_PE j PIN_AN1_PI PDL_ADC_10_PIN_AN2_PE j PIN_AN3_ PI PDL_ADC_10_PIN_AN4 E j PIN_AN5_ PI PDL_ADC_10_PIN_AN6 PIN_AN7_P Configure ADC unit 0 R_ADC_10_Create 0 PDL_ADC_10_MODE E 1E_SCAN PDL_ADC_10_CHANNELS_OPTION_8 12E6 20E 6 ADCO_callback 7 EF Start ADCO R_ADC_10_Control PDL_ADC_10_0_ON PDL_ADC_10_CPU_OFF Shutdown ADC unit R_ADC_10_Destroy 0 while 1 void ADCO_callback void Fetch the result R_ADC_10_Read 0 result_adc0 Figure 5 55 Example of ADC_10 R20UT1963EE0100 Rev 1 00 Page 481 of 487 Jul 19 2012 RENESAS RX63N Group 5 Usage Examples 5 23 12 bit Analog to Digital Converter F
554. xceptionHandlers Synopsis Prototype Description Return value Category Reference Remarks Program example Assign handlers for the fixed vector interrupts bool R_INTC_CreateExceptionHandlers void funct Callback function void func2 Callback function void func3 Callback function void func4 Callback function Register the user functions to be called by the fixed vector and software interrupts func1 The function to be called when a privileged instruction is detected while in user mode Specify PDL_NO_FUNC if no callback function is required func2 The function to be called when an access exception is detected Specify PDL_NO_FUNC if no callback function is required func3 The function to be called when an undefined instruction is detected Specify PDL_NO_FUNC if no callback function is required func4 The function to be called when a floating point exception is detected Specify PDL_NO_FUNC if no callback function is required True Interrupt control e Please see the notes on callback function use in 6 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void UndefinedInstruction void void func void Assign a function to manage undefined instruction errors R_INTC_CreateExceptionHa
555. y PWM modes PDL_MTU2_DEAD_TIME_DISABLE or PDL_MTU2_DEAD_TIME_ENABLE Disable or enable dead time generation Waveform retention control applies only to comple mentary PWM modes PDL_MTU2_WAVEFORM_RETAIN_DISABLE or PDL_MTU2_WAVEFORM_RETAIN_ENABLE Disable or enable waveform output retention Compare match clearing control applies only to co PDL_MTU2_ CNT CLEAR _CM A _DISABLE or PDL_MTU2_CNT_CLEAR_CM_A_ ENABLE mplementary PWM modes Disable or enable counter clearing on TGRA compare match Reset synchronised or complementary PWM control PDL_MTU2_PWM_RS_COMP_ENABLE Enable reset synchronised or complementary PWM mode Register protection PDL_MTU2_ACCESS_ DISABLE Control access to the registers and PDL_MTU2_ACCESS_ ENABLE counters in channels 3 and 4 register_selection The unit registers to be modified If multiple selections are required use to separate each selection The registers to be modified These apply only to complementary PWM mode PDL_MTU2_REGISTER_DEAD_TIME Upd ate the dead time data register TDDR Return value Category PDL_MTU2_ REGISTER CYCLE DATA PDL_MTU2 REGISTER CYCLE BUFFER Update the cycle data register TCDR Update the cycle buffer register TCBR TDDR_value The dead time data register value This will be ignored if the register is n
556. y a master data1 Select channel n where n 0 only data2 The start address of the data to be transmitted in the data field data3 The number of data field bytes to be transmitted Valid from 1 to 16 mode 0 or 32 mode 1 True if all parameters are valid otherwise false IEBus R_IEB_SlaveMonitor Remarks Program example e If interrupts are required use R_IEB_SlaveMonitor to manage the data transfer RPDL definitions include r_pdl_ieb h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t iebus_data 32 uint8_t iebus_data_length Prepare data for transmission when requested R_IEB_SlaveWrite 0 iebus_data iebus_data_length R20UT1963EE0100 Rev 1 00 2tEN ESAS Page 347 of 487 Jul 19 2012 RX63N Group 4 Library Reference 8 R_IEB_Control Synopsis Prototype Description Return value Category Change the IEBus channel configuration bool R_IEB_Control uint8_t data1 Channel selection uint32_t data2 Channel control uint16 tdata3 Unit address Set up the selected IEBus channel data1 Select channel n where n 0 only data2 Modify the channel mode and connection settings If multiple selections are required use to separate each selection Connection mode PDL_IEB_MODE_0 or PDL_IEB MODE 1 The com

Renesas Peripheral Driver Library User`s Manual (RX63N Group)

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