CS49DV8C Data Sheet
Contents
1. Parameter Symbol Min Max Units SCP CLK frequency f cck 400 kHz DCH CLK low time liicckl 1 25 US SCP_CLK high time tiicckh 1 25 us SCP_SCK rising to SCP_SDA rising or falling for START or tiicckemd 1 25 us STOP condition START condition to SCP_CLK falling tiicstscl 1 25 us SCP_CLK falling to STOP condition tiicstp 2 5 I us Bus free time between STOP and START conditions tiicbft 3 us Setup time SCP_SDA input valid to SCP_CLK rising liicsu 100 ns Hold time SCP SDA input after SCP CLK falling lich 20 ns SCP CLK low to SCP SDA out valid l cdov 18 ns 1 The specification fic indicates the maximum speed of the hardware The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application l cckcmd Dech icr tiict tiicckemd tiicstp x licstscl tiicbft SCP_SDA gt lt licsu Dech Figure 6 Serial Control Port C Master Mode Timing DS868PP2 Copyright 2008 Cirrus Logic Inc 17 CS49DV8C Data Sheet 32 bit Audio DSP Family 5 13 Switching Characteristics UART Parameter Symbol Min Max Unit UART_CLK period Let 266 ns UART_CLK duty cycle 40 60 Setup time for UART RXD tyckrxsu 5 Hold time for UART RXD tuckrxdv 5 ns Delay from CLK transition to TXD transition tucktxdv 29 ns 1 The minimum clock period is limited to DCLKP 32 or the minimum valu2. CS49DV8C Data Sheet FEATURES 32 bit Post Processor Audio DSP supports Multichannel Dolby Volume Programmable through DSP Composer CS49DV8 supports up to 7 1 Channels of Dolby Volume processing at 48 kHz 44 1 kHz or 32 kHz Input Configurable for all input output digital audio types I S LJ RJ and TDM 32 bit data path delivers uncompromised dynamic range 192 kHz capable integrated S PDIF transmitter DAO can operate in master or slave mode SCLK amp LRCLK Integrated Clock Manager PLL Capable of operating from a wide variety of external crystals or external oscillators Input Fs Auto Detection Reporting and Handling Sample rate conversion Master amp Slave Host Boot Capability via Serial Interface SPI interface capable of running up to 25 MHz during run time 1 8V Core and a 3 3V I O that is tolerant to 5V input 1 i 32 bit Dual Audio DSP Engine featuring Multichannel Dolby Volume The new CS49DV8C is the fastest time to market mass production ready Multichannel Dolby Volume solution available The target applications for the CS49DV8C DSP are Soundbars DTVs with Integrated Soundbars HDTV Stands Furniture with Integrated Soundbars Automotive Head Units Automotive Outboard Amplifiers Blu ray Disc amp DVD Receivers HTiBs All of these applications and many more that use volume control and are subject to playback from sources that
3. tsddgh Figure 12 External Memory Interface SDRAM Burst Write Cycle lttueq dsa olpnv N9 ZE PIAS Bed OSAGd6FSO cdd898Sd uy 91607 snu 8007 1uBuu do5S Ge SD_CLKOUT SD_CS SD_RAS SD_CAS SD_WE tsdomdv tsdomdv I L n SD Dawn KANAAN NNN NAAMA NANNA NAAMA SD ADDRn AAA SD_DATAn AAA Figure 13 External Memory Interface SDRAM Auto Refresh Cycle lttueq dsa olpnv N9 ZE PIAS Bed OSAGd6FSO cdd898Sd uy 91607 snu 8007 1uBu doS 9c SD CLKOUT tsdemdv tsdemdn SD CS SD RAS SD CAS SD WE SD DQMn NNN SD ADDRn X OPCODE X SD DATAn OCOY Figure 14 External Memory Interface SDRAM Load Mode Register Cycle lI Aug dsa olpnv N9 ZE PIAS Bed OSAGd6FSO CS49DV8C Data Sheet 32 bit Audio DSP Family 6 Ordering Information The CS49DV8C family part number is described as follows CS49DVNNI XYZ where NN Product Number Variant I ROM ID Number X Product Grade y Package Type z Lead Pb Free Table 4 Ordering Information D Part No CS49DV8C CVZ Grade Temp Range Commercial 0 to 70 C Container Tray CS49DV8C CVZR Commercial 0 to 70 C Reel Package 128 pin LQFP 7 Environmental Manufacturing and Handling Information Table 5 Environmental Manufacturing and Handling Information Model Number CS49DV8C CVZ Peak Reflow Temp 260 C MSL Ra
4. 0 8 V Low level input voltage XTI VILXTI 0 6 V Input Hysteresis Vhys 0 4 V High level output voltage lo 4mA except XTI Vou VDDIO 0 9 V SDRAM pins Low level output voltage lo 4mA except XTI VoL VDDIO 0 1 V SDRAM pins SDRAM High level output voltage lo 8mA Vou VDDIO 0 9 V SDRAM Low level output voltage lo 8mA VoL VDDIO 0 1 V Input leakage current all digital pins with internal lin 5 uA pull up resistors disabled 10 Copyright 2008 Cirrus Logic Inc DS868PP2 CS49DV8C Data Sheet IC 32 bit Audio DSP Family Il Parameter Symbol Min Typ Max Unit Input leakage current all digital pins with internal lin PU 50 uA pull up resistors enabled and XTI 5 4 Power Supply Characteristics Measurements performed under operating conditions Parameter Min Typ Max Unit Power supply current Core and I O operating VDD 500 mA PLL operating VDDA 3 5 S mA With external memory and most ports operating VDDIO 120 mA 1 Dependent on application firmware and DSP clock speed 5 5 Thermal Data 128 Pin LQFP Parameter Symbol Min Typ Max Unit Thermal Resistance Junction to Ambient Oi C Watt Two layer Board 48 Four layer Board2 40 Thermal Resistance Junction to Top of Package Vit C Watt Two layer Board 39 Four layer Board2 33 Notes 1 Two layer
5. GPIO3 DDAC 10 SD A5 EXT A5 GPIO2 UART TXD GNDIO4 VDD7 SD A6 EXT_A6 GPIO1 UART RXD 90 SD A7 EXT A7 GPIOO UART CLK VDDIO4 GND7 15 SD A8 EXT A8 XTAL OUT SD A9 EXT A9 XTI GND3 XTO 85 SD A11 EXT A11 DH SD A12 EXT A12 GNDA de 128 Pin LQFP SCH PLL REF RES 20 VDDA 3 3V SD CLKEN VDD8 SD CLKIN GPIO14 DAl1 DATAS TM3 DSD3 80 SD CLKOUT GPIO13 DAI DATA2 TM2 DSD2 SD DQM1 GND8 25 SD D8 EXT D8 GPIO12 DAI1_DATA1 TM1 DSD1 SD D9 EXT D GNDIO3 DAI1_DATAO TMO DSDO VDDIO8 DAI1_SCLK DSD CLK DAI1_LRCLK DSD4 30 GNDIO8 GPIO42 BDI_REQ DAI2_LRCLK PCP_IRQ BSY GPIO43 BDI CLK DAI2_SCLK BDI_DATA DAI2_DATA DSD5 75 SD_D10 EXT_D10 SD_D11 EXT_D11 VDDIO3 SD D12 EXT D12 SD D13 EXT D13 70 SD D14 EXT D14 SD D15 EXT D15 SD DO EXT DO GPIO26 DAO2 DATA3 XMTB UART TX EN 35 GNDIO2 DBDA EXT WE DBCK 65 SD D1 EXT D1 GPIO20 DAO2 DATA2 EE_CS o UD io UD io UD Ls o q Q A e e QN A O E OD TA o G Xt5B50 5B55385E8n5no0g95o0f5888SsSB5B8883888 ZTOowarozsosrrzgArogoazeEe ll sy SBF gt GS OFX gt 0 E gt G e E EE E E ES Q v nu ec AG 12 5 XXX x Q
6. board is specified as a 76 mm X 114 mm 1 6 mm thick FR 4 material with 1 02 copper covering 20 of the top and bottom layers 2 Four layer board is specified as a 76 mm X 114 mm 1 6 mm thick FR 4 material with 1 02 copper covering 20 of the top and bottom layers and 0 5 oz copper covering 90 of the internal power plane and ground plane layers 3 To calculate the die temperature for a given power dissipation Tj Ambient Temperature Power Dissipation in Watts 9 4 4 To calculate the case temperature for a given power dissipation Ty Tj Power Dissipation in Watts vi DS868PP2 Copyright 2008 Cirrus Logic Inc 11 CS49DV8C Data Sheet 32 bit Audio DSP Family 5 6 Switching Characteristics RESET D Parameter Symbol Min Max Unit RESET minimum pulse width low Tisti 1 us All bidirectional pins high Z after RESET low Trst2z 100 ns Configuration pins setup before RESET high Tuten 50 ns Configuration pins hold after RESET high Trsthid 20 ns RESET y HS 3 0 All Bidirectional N Pins N NY Tegen T stha T oa Ta lt gt Figure 1 RESET Timing 12 Copyright 2008 Cirrus Logic Inc DS868PP2 CS49DV8C Data Sheet 32 bit Audio DSP Family 5 7 Switching Characteristics XTI Parameter Symbol Min Max Unit External Crystal operating frequency Fytal 11 2896 27 MHz XTI period Toki 33 3 10
7. do not have consis tent volume levels will benefit from the CS49DV8C Dolby Volume solution I DOLBY VOLUME Ordering Information See page 27 for ordering information Serial Serial Control 1 Control 2 UART GPIO Debug I ch 8 Ch Audio In TMR1 S PDIF S PDIF TMR2 d 8 Ch PCM j Audio Out Ext Memory Controller PLL n gt Preliminary Product Information This document contains information for a new product Cirrus Logic reserves the right to modify this product without notice Copyright 2008 Cirrus Logic All Rights Reserved CIRRUS LOGIC http www cirrus com SEPT 08 DS868PP2 32 bit Audio DSP Family IZ CS49DV8C Data Sheet I C IRRUS LOG I Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative To find the one nearest to you go to www cirrus com IMPORTANT NOTICE Preliminary product information describes products that are in production but for which full characterization data is not yet available Cirrus Logic Inc and its sub sidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any
8. 0 ns XTI high time Tclkih 13 3 ns XTI low time Tclkil 13 3 S ns External Crystal Load Capacitance parallel resonant C 10 18 pF External Crystal Equivalent Series Resistance ESR 50 W 1 Part characterized with the following crystal frequency values 11 2896 12 288 18 432 24 576 and 27 MHz 2 C refers to the total load capacitance as specified by the crystal manufacturer Crystals which require a C outside this range should be avoided The crystal oscillator circuit design should follow the crystal manufacturer s recommendation for load capacitor selection XTI M lt tckin Fa t clkil lt Toki Figure 2 XTI Timing 5 8 Switching Characteristics Internal Clock Parameter Symbol Min Max Unit Internal DCLK frequency Fach MHz CS49DV8C CVZ Fytal 150 CS49DV8C CVZR Internal DCLK period DCLKP ns CS49DV8C CVZ 6 7 1 F ytal CS49DV8C CVZR 1 After initial power on reset Fac East After initial kickstart commands the PLL is locked to max Fyg and remains locked until the next power on reset DS868PP2 Copyright 2008 Cirrus Logic Inc CS49DV8C Data Sheet 32 bit Audio DSP Family Il 5 9 Switching Characteristics Serial Control Port SPI Slave Mode Parameter Symbol Min Typical Max Units SCP_CLK frequency fspisck 25 MHz SCP CS falling to SCP_CLK rising tspicss 24 ns SCP_CLK low time tspickl 20
9. 2008 Cirrus Logic Inc DS868PP2 CS49DV8C Data Sheet CIRRIIS LOGIC 32 bit Audio DSP Family 1 Documentation Strategy The CS49DV8C data sheet describes the CS49DV8C family of multichannel audio DSPs This document should be used in conjunction with the following documents when evaluating or designing a system around the CS49DV8C family of processors Table 1 CS49DV8C Related Documentation Document Name Description CS49DV8C Data Sheet This document Detailed system design information including Typical CS4953xx Hardware User s Manual er Diagrams boot procedures pin descriptions and other system configuration information Application note contains an Application AN288PPH Dolby Volume Module Programming Interface API used to control the Dolby Volume firmware Includes detailed configuration and usage TM DSP Composer User s Manual information for the GUI development tool The scope of the CS49DV8C Data Sheet is primarily the hardware specifications of the CS49DV8C devices This includes hardware functionality characteristic data pinout and packaging information The intended audience for the CS49DV8C Data Sheet is the system PCB designer MCU programmer and the quality control engineer 2 Overview The CS49DV8C DSP is designed to provide high performance volume control using the Dolby Volume algorithm The CS49DV8 supports up to 7 1 Channels of Dolby Volume pr
10. 3 tspiess 11 DCLKP ns SCP_CLK PERIOD 2 SCP_CLK low time Loch 18 i ns SCP_CLK high time tspickh 18 ns Setup time SCP_MISO input tspidsu 11 ns Hold time SCP MISO input tspidh 5 ns SCP_CLK low to SCP MOSI output valid tspidov 11 ns SCP_CLK low to SCP_CS falling tspiosi 7 ns SCP_CLK low to SCP CS rising tspicsh 11 DCLKP ns SCP_CLK PERIOD 2 Bus free time between active SCP_CS tspicsx 3 DCLKP i ns SCP_CLK falling to SCP_MOSI output high Z tspidz 20 ns 1 The specification Lisch indicates the maximum speed of the hardware The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application 2 See Section 5 7 3 SCP CLK PERIOD refers to the period of SCP CLK as being used in a given application It does not refer to a tested parameter lspicss EE CS tspics SCP_CLK Losch SCP MISO tspidsu tspidh SCH MOSI _5 tspickh Loch tspidov gt MSB Figure 4 Serial Control Port SPI Master Mode Timing DS868PP2 Copyright 2008 Cirrus Logic Inc tspicsx tspicsh lt tspidz D 15 CS49DV8C Data Sheet 32 bit Audio DSP Family Il 5 11 Switching Characteristics Serial Control Port I C Slave Mode Parameter Symbol Min Typical Max Units SCP_CLK frequency ficck 400 kHz SCP_CLK low time Diech 1 25 U
11. 8C Data Sheet 32 bit Audio DSP Family 5 16 Switching Characteristics SDRAM Interface Refer to Figure 11 through Figure 14 SD CLKOUT SD CLKIN D Parameter Symbol Min Typical Max Unit SD CLKIN high time Licht 2 3 ns SD_CLKIN low time lsdclkl 2 3 ns SD CLKOUT rise fall time Lack 1 ns SD_CLKOUT Frequency 150 MHz SD_CLKOUT duty cycle 45 55 SD_CLKOUT rising edge to signal valid tsdemdv 3 8 ns Signal hold from SD_CLKOUT rising edge tsdemdh 1 1 ns SD_CLKOUT rising edge to SD DQMn valid tsddqv 3 8 ns SD_DQMn hold from SD_CLKOUT rising edge tsddgh 1 38 ns SD DATA valid setup to SD CLKIN rising edge tsddsu 1 3 ns SD_DATA valid hold to SD_CLKIN rising edge tsddh 1 38 ns SD_CLKOUT rising edge to ADDRn valid tsdav 3 8 ns 22 Copyright 2008 Cirrus Logic Inc DS868PP2 cdd898Sd uy 91607 snu 8007 1uBu Adoo E SD CLKOUT tsdemdv JA gt be tsdemdh SD_CS SD_RAS SD CAS SD_WE tsddqv Fl SD DQMn SD Dn SD CLKIN Loch tsdolkh Figure 11 External Memory Interface SDRAM Burst Read Cycle li lttueq dsa olpnv N9 ZE PIAS Bed OSAGd6FSO cdd898Sd uy 91607 snu 8007 1uB5uu doS ve SD_CLKOUT tsdemav HF tsdemdh SD CS N SD_RAS SD_CAS N N SD_WE N N SD_Dn LSPO MSPO LSP1 MSP1 LSP2 MSP2 LSP3 MSP3 tsdav SD An SD DQMn
12. R WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY AUTOMOTIVE SAFETY OR SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT NESS FOR PARTICULAR PURPOSE WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS CUSTOMER AGREES BY SUCH USE TO FULLY INDEM NIFY CIRRUS ITS OFFICERS DIRECTORS EMPLOYEES DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY INCLUDING ATTORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus the Cirrus Logic logo designs DSP Composer and Cirrus Framework are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trademarks or service marks of their respective owners Dolby is a registered trademarks of Dolby Laboratories Inc Dolby Volume is a trademark of Dolby Laboratories Inc Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent or any other industrial or Intellectual Property Right of Dolby Laboratories to use the Implementation in any finished end user or ready to use final product It is her
13. S SCP CLK high time tiicekh 1 25 us SCP_SCK rising to SCP_SDA rising or falling for tiicckemd 1 25 us START or STOP condition START condition to SCP_CLK falling tiestsel 1 25 us SCP_CLK falling to STOP condition tiiestp 2 5 i us Bus free time between STOP and START conditions tiicbft 3 US Setup time SCP SDA input valid to SCP_CLK rising liicsu 100 ns Hold time SCP SDA input after SCP CLK falling lich 20 ns SCP_CLK low to SCP_SDA out valid l cdov 18 ns SCP_CLK falling to SCP_IRQ rising l cirgh 3 DCLKP 40 ns NAK condition to SCP_IRQ low ticiral 3 DCLKP 20 ns SCP_CLK rising to SCB_BSY low ticbsyl 3 DCLKP 20 ns 1 The specification fu indicates the maximum speed of the hardware The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application Flow control using the SCP BSY pin should be implemented to prevent overflow of the input data buffer l cckcmd Iech tier l ct l cckcmd SCP CLK lice il licis scP SDA V As Y Y o YrwYackYmss Y 7 Y Yis Y lack ticirah y T liso Gi SCP IRQ gt liiccbsyl SCP BSY Figure 5 Serial Control Port IC Slave Mode Timing 16 Copyright 2008 Cirrus Logic Inc DS868PP2 CS49DV8C Data Sheet Ir 32 bit Audio DSP Family 7 5 12 Switching Characteristics Serial Control Port ZC Master Mode
14. ators four X and four Y data registers and 12 index registers Both DSP cores are coupled to a flexible DMA engine The DMA engine can move data between peripherals such as the digital audio input DAI and digital audio output DAO external memory or any DSP core memory all without the intervention of the DSP The DMA engine offloads data move instructions from the DSP core leaving more MIPS available for signal processing instructions CS49DV8C functionality is controlled by application codes that are stored in on board ROM or downloaded to the CS49DV8C from a host MCU or external FLASH EEPROM Users can choose to use standard audio post processor modules which are available from Cirrus Logic 4 1 1 DSP Memory The memory maps for the DSPs are as follows All memory sizes are composed of 32 bit words Table 3 CS49DV8C DSP Memory Sizes ne DSP A DSP B X 16k SRAM 32k ROM 10k SRAM 8k ROM Y 24k SRAM 32k ROM 16k SRAM 16k ROM P 8kSRAM 32k ROM 8k SRAM 24k ROM 4 1 2 DMA Controller The powerful 12 channel DMA controller can move data between 8 on chip resources Each resource has its own arbiter X Y and P RAM ROMs on DSP A X Y and P RAM ROMs on DSP B external DS868PP2 Copyright 2008 Cirrus Logic Inc 7 CS49DV8C Data Sheet 32 bit Audio DSP Family memory and the peripheral bus Modulo and linear addressing modes are supported with flexible start address and increment cont
15. dv 10 ns DAO1 DATA 3 0 DAO2 DATA 1 0 ldaosdv 2 15 ns delay from DAO_ SCLK transition DAO LRCLK delay from DAO SCLK transition respectively ldaosstlr 30 ns DAO SCLK delay from DAO LRCLK transition respectively tdaoslrts i 15 ns 1 Master mode timing specifications are characterized not production tested 2 Master mode is defined as the CS49DVxx driving both DAO_SCLK DAO LRCLK When MCLK is an input it is divided to produce DAO SCLK DAO_LRCLK 3 This timing parameter is defined from the non active edge of DAO_SCLK The active edge of DAO SCLK is the point at which the data is valid 4 Slave mode is defined as DAC SCLK DAO_LRCLK driven by an external source tdaomicik laaomclk DAO MCLK DAO MCLK laaomsck tdaomsck DAO SCLK DAO SCLK tdaomdv i tdaomirts ldaomstir DAO LRCLK DAO LRCLK Note In these diagrams Falling edge is the inactive edge of DAO SCLK Figure 9 Digital Audio Port Timing Master Mode 20 Copyright 2008 Cirrus Logic Inc DS868PP2 Il CS49DV8C Data Sheet RI IS TOCH 32 bit Audio DSP Family 14 tdaoscik DAO LRCLK A DAO SCLK DAO LRCLK DAC SCLK ldaoscik tdaoslris DAOn DATAn X A m tdaosdv Note In these diagrams Falling edge is the inactive edge of DAO SCLK Figure 10 Digital Audio Output Timing Slave Mode Relationship LRCLK to SCLK DS868PP2 Copyright 2008 Cirrus Logic Inc 21 CS49DV
16. e whichever is larger UART_CLK UART TXD UART HAD UART TX EN N luckxav 1499 tixen gt tuckrxsu dk tuckrxdv Figure 7 UART Timing tixhz 18 Copyright 2008 Cirrus Logic Inc DS868PP2 7 5 14 Switching Characteristics Digital Audio Slave Input Port CS49DV8C Data Sheet 32 bit Audio DSP Family Parameter Symbol Min Max Unit DAI SCLK period Tgaiclkp 40 ns DAI_SCLK duty cycle 45 55 Setup time DAI DATAn tdaidsu 10 ns Hold time DAI DATAn tdaidh 5 ns DS868PP2 DAI_SCLK taaidsu p gt gt DAI DATAn taaidh Figure 8 Digital Audio Input DAI Port Timing Diagram Copyright 2008 Cirrus Logic Inc 19 CS49DV8C Data Sheet 32 bit Audio DSP Family Il 5 15 Switching Characteristics Digital Audio Output Port Parameter Symbol Min Max Unit DAO_MCLK period Tdaomclk 40 ns DAO MCLK duty cycle 45 55 96 DAO SCLK period for Master or Slave mode Tdaosclk 40 ns DAO SCLK duty cycle for Master or Slave mode 40 60 96 Master Mode Output A1 Mode 2 DAC SCLK delay from DAC MCLK rising edge ldaomsck 19 ns DAO_MCLK as an input DAO_LRCLK delay from DAO_SCLK transition respectively3 tdaomstir 8 ns DAO SCLK delay from DAO LRCLK transition respectively tdaomlrts 8 ns DAO1 DATA 3 0 DAO2 DATA 1 0 delay from DAO SCLK transition Slave Mode Output AO Mode ldaom
17. eby notified that a license for such use is required from Dolby Laboratories Motorola and SPI are trademarks of Motorola Inc IC is a registered trademark of Philips Semiconductor Logic7 is a registered trademark of Harmon International Industries Inc iPod is a registered trademark of Apple Computer Inc Blu ray and Blu ray Disc are trademarks of SONY KABUSHIKI KAISHA CORPORATION 2 Copyright 2008 Cirrus Logic Inc DS868PP2 CS49DV8C Data Sheet WC 32 bit Audio DSP Family Table of Contents 1 Documentation KEE E EE 5 PAO a E E A E A E 5 2 1 Lensing EE 7 3 Firmware Supported ME 7 4 Hardware Functional Description u uu u u T 7 41 DSP ETC 7 AAA DSP Memory ET 7 4 1 2 DMA Controller gunge 7 4 2 On chip DSP Peripherals sg aite ands ees edo ta e datae Cv tk der eb dese and ENEE 8 4 2 1 Digital Audio Input Port DAI asa eeree tende eth dee tua ea tha E eue enn de nus 8 4 2 2 Digital Audio Output Port DAO n n 8 4 2 3 Serial Control Port 1 amp 2 OC or SPI EE 8 4 2 4 External Memory Interface uy l l teet te eere tb ERE oe Earn roc EE REOR etna aee RES 8 zecepm 8 4 2 6 PLE based Clock Generator ertet nee teet Een db ced ER RE kan dad uere La ada 8 4 3 DSP I O Description u
18. kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowl edgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for the use of this information includ ing use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the informa tion only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPER TY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED O
19. lowing conditions T 25 C C 20 pF VDD 1 8 V VDDA VDDIO 3 3 V GNDD GNDIO GNDA 0 V 5 1 Absolute Maximum Ratings GNDD GNDIO GNDA 0 V all voltages with respect to 0 V Parameter Symbol Min Max Unit DC power supplies Core supply VDD 0 3 2 0 V PLL supply VDDA 0 3 3 6 V T O supply VDDIO 0 3 3 6 V IVDDA VDDIOI 0 3 V Input pin current any pin except supplies lin 10 mA Input voltage on PLL REF RES Vit 0 3 3 6 V Input voltage on I O pins Vinio 0 3 5 0 V Storage temperature Joe 65 150 C Caution Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes 5 2 Recommended Operating Conditions GNDD GNDIO GNDA 0 V all voltages with respect to 0 V Parameter Symbol Min Typ Max Unit DC power supplies Core supply VDD 1 71 1 8 1 89 V PLL supply VDDA 3 13 3 3 3 46 V T O supply VDDIO 3 13 3 3 3 46 V IVDDA VDDIOI 0 V Ambient operating temperature TA Commercial Grade CVZ CVZR 0 25 70 Note It is recommended that the 3 3 V IO supply come up ahead of or simultaneously with the 1 8 V core supply 5 3 Digital DC Characteristics Measurements performed under static conditions Parameter Symbol Min Typ Max Unit High level input voltage ViH 2 0 V Low level input voltage except XTI Vu
20. ns SCP_CLK high time tspickh 20 ns Setup time SCP_MOSI input tspidsu 5 ns Hold time SCP MOSI input tspidh 5 ns SCP_CLK low to SCP_MISO output valid tspidov 11 ns SCP CLK falling to SCH IRQ rising tspiirqh 20 ns SCP_CS rising to SCP_IRQ falling Lspiirql 0 ns SCP_CLK low to SCP CS rising tspicsh 24 ns SCP_CS rising to SCP_MISO output high Z L iesde 20 ns SCP_CLK rising to SCP_BSY falling tspicbsyl 3 DCLKP 20 ns 1 The specification Losch indicates the maximum speed of the hardware The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer At boot the maximum speed is Fxtal 3 lspicss SCP CS c Loch 2 le gt 6 7 0 SCP_CLK SCP_MOSI tspidsu Loan tspidov e ai tspicsdz SCP_MISO _ amp L ES AA SCP_IRQ eegenen LS tspiirgh 2 tspibsyl SCP BSY 5 5 Figure 3 Serial Control Port SPI Slave Mode Timing 14 Copyright 2008 Cirrus Logic Inc tspiiral DS868PP2 7 CS49DV8C Data Sheet 32 bit Audio DSP Family 5 10 Switching Characteristics Serial Control Port SPI Master Mode Parameter Symbol Min Typical Max Units SCP CLK frequency fisk Fyta 2 See MHz Footnote 2 SCP CS falling to SCP_CLK rising
21. ocessing at 48 kHz 44 1 kHz or 32 kHz while leaving the 2nd core of the DSP completely available for even further processing functions such as Quadruple Crossover Bass Management Tone Control and Multiband Parametric EQ The CS49DV8C DSP together with Cirrus Logic s comprehensive library of audio processing algorithms enables the development of next generation high definition audio solutions Cirrus Logic also provides a broad array of digital interface products and audio converters to meet your audio system level design requirements The CS49DV8C is available in a 128 pin LQFP package Please refer to Table 2 on page 6 for the processor speed and available firmware for the CS49DV8C product family DS868PP2 Copyright 2008 Cirrus Logic Inc 5 cdd898Sd uy 91607 snu 8007 1uBu doS Table 2 Device and Firmware Selection Guide Device Ss Process CS49DV8C 300 MIPS T Decode Processor A Stereo PCM Multi Channel PCM 2 1 Downsampling Option 4 1 Downsampling Option Mid processor A Dolby Volume Runs on either DSP A or B See Section 3 for additional concurrency information Mid processor B Dolby Volume Runs on either DSP A or B See Section 3 for additional concurrency information Post processor Tone Control e Re EQ PEQ up to 11 bands Delay 7 1 Bass Manager Audio Manager 1 2 Upsampling 1 Processing may be restricted and dependent
22. on firmware selected Contact your Cirrus Logic FAE for concurrency matrix ii lttueq dsa olpnv N9 ZE PIAS Bed OSAGd6FSO aa a CS49DV8C Data Sheet p s C IRRI IS TOGIC 32 bit Audio DSP Family 2 1 Licensing Licenses are required for Dolby Volume and for all of the third party audio processing algorithms Please contact your local Cirrus Sales representative for more information 3 Firmware Supported The suite of software available for the CS49DV8C family consists of operating systems OS and a library of overlays The overlays have been divided into three main groups called Decoders Mid processors and Post processors All software components are defined as follows OS Kernel Encompasses all non audio processing tasks including loading data from external memory processing host messages calling audio processing subroutines auto detection error concealment etc Dolby Volume The CS49DV8C can run Dolby Volume on either DSP A or DSP B On the DSP that is not running Dolby Volume it can run the firmware currently available on the CS4953xx family for that DSP A or B 4 Hardware Functional Description 4 1 DSP Core The CS49DV8C is a dual core DSP with separate X and Y data and P code memory spaces Each core is a high performance 32 bit user programmable fixed point DSP that is capable of performing two memory access control MAC operations per clock cycle Each core has eight 72 bit accumul
23. rating as master or slave in either IC or SPI modes SCP1 defaults to slave operation It is dedicated for external host control and supports an external clock up to 25MHz in SPI mode This high clock speed enables very fast code download control or data delivery SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub system control 4 2 4 External Memory Interface The external memory interface controller supports up to 128 Mbits of SDRAM using a 16 bit data bus 4 2 5 GPIO Many of the CS49DV8C peripheral pins are multiplexed with GPIO Each GPIO can be configured as an output an input or an input with interrupt Each input pin interrupt can be configured as rising edge falling edge active low or active high 4 2 6 PLL based Clock Generator The low jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals Through a second PLL divider chain a dependent clock domain can be output on the DAO port for driving audio converters The CS49DV8C defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured either through master boot from an external FLASH or through host control A built in crystal oscillator circuit with a buffered output is provided The buffered output frequency ratio is selectable between 1 1 default or 2 1 8 Cop
24. rols The service interval for each DMA channel as well as up to 6 interrupt events is programmable 4 2 On chip DSP Peripherals 4 2 1 Digital Audio Input Port DAI The 12 channel 6 line DAI port supports a wide variety of data input formats The port is capable of accepting PCM or IEC61937 Up to 32 bit word lengths are supported Additionally support is provided for audio data input to the DSP via the DAI from an HDMI receiver The port has two independent slave only clock domains Each data input can be independently assigned to a clock domain The sample rate of the input clock domains can be determined automatically by the DSP which off loads the task of monitoring the SPDIF receiver from the host A time stamping feature allows the input data to be sample rate converted via software 4 2 2 Digital Audio Output Port DAO There are two DAO ports Each port can output 8 channels of up to 32 bit PCM data The port supports data rates from 32 kHz to 192 kHz Each port can be configured as an independent clock domain in slave mode or the ratio of the two clocks can be set to even multiples of each other in master mode The two ports can also be ganged together into a single clock domain Each port has one serial audio pin that can be configured as a 192 kHz SPDIF transmitter data with embedded clock on a single line 4 2 3 Serial Control Port 1 amp 2 I2C or SPI There are two on chip serial control ports that are capable of ope
25. t IC Slave Mode Timing 16 Figure 6 Serial Control Port IC Master Mode Timing 17 Figure 7 UART TIMING sa ssgseoers ed Made de pee dere Ra DER RUE Ra Aon RA dee Rak at JE e pQ a ae 18 Figure 8 Digital Audio Input DAI Port Timing Diagram lsileleeee BRI 19 Figure 9 Digital Audio Port Timing Master Mode 20 Figure 10 Digital Audio Output Timing Slave Mode Relationship LRCLK to SCLK 21 Figure 11 External Memory Interface SDRAM Burst Read Cycle 23 Figure 12 External Memory Interface SDRAM Burst Write Cycle 24 Figure 13 External Memory Interface SDRAM Auto Refresh Cycle 25 Figure 14 External Memory Interface SDRAM Load Mode Register Cycle 26 Figure 15 128 Pin LQFP Pin Out auuauranvan nerver mmn 28 Figure 16 128 Pin LQFP Package Drawing 29 List of Tables Table 1 CS49DV8C Related Documentation 5 Table 2 Device and Firmware Selection Guide 6 Table 3 CS49DV8C DSP Memory Sizes asnasan sassa 7 Table 4 Ordering Information lille mh 27 Table 5 Environmental Manufacturing and Handling Information 27 Table 6 128 Pin LQFP Package Characteristics arver renere nrk n nn eee 29 4 Copyright
26. tics Serial Control Port IC Master Mode I aaa 17 5 13 Switching Characteristics VART EE 18 5 14 Switching Characteristics Digital Audio Slave Input Port a 19 5 15 Switching Characteristics Digital Audio Output Port an 20 5 16 Switching Characteristics SDRAM Interface eene nnne eene nn trennen nnns 22 6 Ordering Information 27 7 Environmental Manufacturing and Handling Information 27 8 Device Pin Out Diagram M m 28 8 1 128 Pin LQFP Pin Out Diagramm 28 9 Package Mechanical Drawings l utn u u u u u u u 29 9 1 128 Pin LOFP Package uyu u sii arat ehe pepe E RR ras epa x aibu Sege gedet eden 29 TU Revision HiIStOTY Lese ad nane aa odd iR D cd nic edd na i 30 DS868PP2 Copyright 2008 Cirrus Logic Inc 3 sa CS49DV8C Data Sheet LI gr 32 bit Audio DSP Family List of Figures Fig re T RESET Timing 3g yl bee va b e aceite be n eb ie e A OE ee KR e pe ee ilden be 12 Figure 2 XT Timing 22i ama gs bena em de aah R a e er na ei ranere 13 Figure 3 Serial Control Port SPI Slave Mode Timing 14 Figure 4 Serial Control Port SPI Master Mode Timing 15 Figure 5 Serial Control Por
27. ting 3 Max Floor Life 7 Days CS49DV8C CVZR 260 C 3 7 Days MSL Moisture Sensitivity Level as specified by IPC JEDEC J STD 020 27 Copyright 2008 Cirrus Logic Inc DS868PP2 CS49DV8C Data Sheet 32 bit Audio DSP Family Il 8 Device Pin Out Diagram 8 1 128 Pin LQFP Pin Out Diagram gt a E D a d o x Qa o a E 2 o oi Si lt lt lt P P rer S ei 8 8 55 E ER a a aA a H 2 e oo e S ke 5g 8 8 8SE8S0Re 25 2G 8 xO lt a augu g ok Ok O Z m aa SoaG atCPCsvna kE rE pa PP n n 77 S TY 2 Za aa R R Zuna XX x x 2Z xxaxnanananana7Z2an G GG z oo o E gt u uju ou lu SFSU oo o oo GAA g EI EI gl GPIO38 PCP_WR DS SCP2 CLK 1 SD AO EXT A0 GPIO11 PCP A3 AS SCP2 MISO SDA SD A1 EXT A1 GPIO10 PCP A2 A10 SCP2 MOSI 100 vDDIO5 GPOI9 SCP1_IRQ SD_A2 EXT_A2 GPIO8 PCP_IRQ SCP2_IRQ 5 GND4 GPIO7 SCP1_CS IOWAIT SD_A3 EXT_A3 GPIO6 PCP_CS SCP2_CS SD_A4 EXT_A4 VDDIO7 95 VDD4 GNDIO7 EXT_CS2
28. u degen EES a a aa dE EELER 9 4 3 1 Multiplexed PINS sias anans tr utet teet eem E ben pu Fe e un Ru nv EE 9 4 3 2 Termination Requirements ernnnnnnvnnnnnnnnnvnnnnnnnnvnnnnnnnnnnnnnnnnnnnnneennnnnneennnnnnseennnnnnneenennnnneeeennnennnennnnnene 9 4 3 3 Pad aaa 9 4 4 Application Code Security B 9 5 Characteristics and Specifications U u u u u u u u 10 5 1 Absolute Maximum e CN 10 5 2 Recommended Operating Conditions ssssssssssssssssesee enne en nennen nenne nnne nnns 10 5 3 Digital Ree 10 5 4 Power Supply Characteristics cccccececeececeeceeeeeeeeeeeeeeaeeceeeeeeaaeeseeeeeseaeeeseaeeeseaeeeseaaeseceessgeaeeseeeeesiaaeseeees 11 5 5 Thermal Data 128 Pin EQEPEB cr teet err era ret teca eludet uei ec ped ede peat tete ra ek care ean 11 5 6 Switching Characteristics RESET eene hene nennen nn tent tennis nennen rnit nn innen 12 5 7 Switching Characteristics AR EE 13 5 8 Switching Characteristics Internal Clock eene nennen nnne nnne nnns 13 5 9 Switching Characteristics Serial Control Port SPI Slave Mode 14 5 10 Switching Characteristics Serial Control Port SPI Master Mode sese 15 5 11 Switching Characteristics Serial Control Port IC Slave Mode c c cccccscsscsesescsessessessseseesetsseeseceteenes 16 5 12 Switching Characteris
29. x x lt lt a O lt lt gt lt 6 gt Eg EQ sakk LO p ax gee a a a ae aa 2 999449 a8 a of aq JJ a oo oo an 9 8 8 3 DOOD o0 a Og Qana a o Q lt u E a a ona 6 6 SG G o Figure 15 128 Pin LQFP Pin Out 28 Copyright 2008 Cirrus Logic Inc DS868PP2 9 Package Mechanical Drawings 9 1 128 Pin LQFP Package F CS49DV8C Data Sheet 32 bit Audio DSP Family NS Y F e b Y A A1 Figure 16 128 Pin LQFP Package Drawing Table 6 128 Pin LQFP Package Characteristics MILLIMETERS INCHES A 1 60 063 A1 0 05 0 15 002 m 006 b 0 17 0 22 0 27 007 009 011 D 22 00 BSC 866 D1 20 00 BSC 787 E 16 00 BSC 630 E1 14 00 BSC 551 e 0 50 BSC 020 q 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 018 024 030 L1 1 00 REF 039 REF TOLERANCES OF FORM AND POSITION ddd 0 08 003 DS868PP2 Copyright 2008 Cirrus Logic Inc 29 30 CS49DV8C Data Sheet 32 bit Audio DSP Family 10 Revision History Il Revision Date Changes PP1 September 2 2008 Initial Release PP2 September 25 2008 Removed references to External Parallel Flash SRAM Interface Copyright 2008 Cirrus Logic Inc DS868PP2
30. yright 2008 Cirrus Logic Inc DS868PP2 CS49DV8C Data Sheet OGIC 32 bit Audio DSP Family 4 3 DSP I O Description 4 3 1 Multiplexed Pins Many of the CS49DV8C pins are multi functional For details on pin functionality please refer to the CS4953xx Hardware User s Manual 4 3 2 Termination Requirements Open drain pins on the CS49DV8C must be pulled high for proper operation Please refer to the CS4953xx Hardware User s Manual to identify which pins are open drain and what value of pull up resistor is required for proper operation Mode select pins on the CS49DV8C are used to select the boot mode upon the rising edge of reset A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4953xx Hardware User s Manual 4 3 3 Pads The CS49DV8C I O operates from the 3 3 V supply and is 5 V tolerant 4 4 Application Code Security The external program code may be encrypted by the programmer to protect any intellectual property it may contain secret customer specific key is used to encrypt the program code that is to be stored external to the device DS868PP2 Copyright 2008 Cirrus Logic Inc 9 CS49DV8C Data Sheet 32 bit Audio DSP Family Il 5 Characteristics and Specifications Note All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature All data sheet typical parameters are measured under the fol
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