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The art of construction The art of construction

1. Constant on Time COT LM310x Regulators from the PowerWise Family Need No Loop Compensation and Are Stable with Ceramic Capacitors Vin 45 to 42V AM Vout gt 06V LM310x Enable Non sync Vin 24 Soft start 1 15 Load Current A 1M3100 4 510 36 15 08 Upto 1 eTSSOP 20 003102 4 510 42 25 08 Upto1 eTSSOP 20 1M3103 4 5 to 42 0 75 06 Upto1 eTSSOP 16 COT control provides lightning fast transient response Stable with ceramic capacitors Near constant frequency operation from unregulated supplies No loop compensation reduces external component count Pre bias startup Discontinuous Conduction Mode DCM operation for a light load Enabled in National s WEBENCH online design environment Embedded systems industrial controls automotive telematics and body electronics point of load regulators storage systems and broadband infrastructure For FREE samples datasheets and online design tools visit nat om switcher Or call 1 800 272 9959 Cap 27 Nera Sint i Pw SIMPLEST WEEN itd a fs Seni Capon Ii a cover feature section Listing 1 The various sections of a VHDL source file are illustrated here Header Section PEREA E EEE Name Beckie Smith Date January 28 2005 Filename Door monitor vhd Description This circuit is responsible for enabling an external door chime circuit 10 clock Cycles or about 500ns after door status goes high Revision
2. It s not all about operating systems Mr Carbone could not possibly have an ax to grind could he John Car bonne Embedded OS trends points to Linux sometimes online Guest Editor column 12 11 07 After all he hails from Express Logic which sells 1 the Shockley Effect the Thread X RTOS I have seen over a dozen surveys that show the exact opposite of the one cited in this arti cle where the use of Linux is on the rise in embedded devices and espe cially in small handheld devices that must display rich content from the Internet Linux as applied to embedded sys tems has a steep learning curve Once you re past that it s smooth sailing But Linux has its place Personally I like OpenBSD because of its focus on cor rectness and security OpenBSD will only run at this time on machines that have an MMU so it will not fit well on certain desirable platforms There s a place for assembly for C for FORTH based system for a home grown RTOS for a commercial RTOS for a free RTOS and of course for Linux and its BSD sisters and brothers Remember the old saying If all you have is a hammer then every problem looks like a nail One should not fall in love with any one technique Linux is not for tiny microcon trollers you need at least a 32 bit ma chine with at least tens of megabytes of memory However the trend in mi crocontrollers is
3. History Date Initials Description 2 17 05 BCS Changed chime delay from 1 minute to 500ns LIBRARY IEEE USE IEEE std logic 1164 ALL USE ieee std logic signed all ENTITY monitor IS reset IN std logic set internal gates to initial state door status IN std logic closed low clock 20mhz IN std logic input clock 20mhz 20HZ door chime en OUT std logic signal used to sound door chime END monitor ARCHITECTURE door monitor OF monitor IS SIGNAL start S00ns timer std logic enables 500ns timer SIGNAL reset start timer std logic reset 500ns timer SIGNAL timer 500ns std logic vector 3 DOWNTO 0 500ns counter SIGNAL chime enable std logic sets external door chime Concurrent statement BEGIN Pd door chime en chime enable signal used to sound door chime checking door status PROCESS reset clock 20mhz reset start timer Sensitivity list This process detects when the door has been opened and then starts the 500ns timer BEGIN IF reset 1 OR reset start timer 1 THEN start 500ns timer lt 0 3 clear 500ns timer ELSIF rising_edge clock_20mhz THEN IF door_status 1 THEN start 500ns timer 1 after 2 ns END IF END IF END PROCESS door is opened enable 500ns timer set alarm enable PROCESS reset clock 20mhz This process set the alarm enable 500ns after the door has been opened BEG
4. a hierarchical file structure Security system vhd Bedrooms Kitchen vhd and other information used by synthe sis and simulation tools The vendor s package becomes visible in the same manner as the standard and user defined libraries To use the elements in Xilinx s vcomponent package de signers must make the li brary visible For example the following command makes the Xilinx library with vcomponent package visible to the design LIBRARY Xilinx USE Xilinx vcomponents ALL Once all the libraries and packages are visible this section is complete Entity declaration The entity declaration section immedi ately follows the library declaration Each entity has an assigned name Monitor is the entity name of the VHLD code in Listing 1 Just as the li brary declaration section makes li braries and packages visible to the de sign the entity section makes the I Os visible to other source files and the de sign and can represent the I Os as phys ical FPGA pins VHDL designs can con tain one source file or a hierarchy of multiple files Hierarchical file structures the consist of several files connected through the signals declared in their entities Figure 2 shows a simplified hi if the design is only one file aration defines all of the I O that represents top level entity dec physical FPGA pins erarchical file structure for a home se curity system On
5. actual VHDL design Hence the same VHDL language rules apply Each tester has a style in which he or she writes a testbench which can be automatic or manual and can use external files for simulation and analysis Automatic testbenches can analyze simulation data and provide a final result output error data or other important information Manual testbenches require the tester to manually analyze the data An example of an automatic testbench would be one that reads valid data from an exter nal file compares it with simulation data and writes the final pass fail re sults to an external file External files are useful for duplicating events seen on actual hardware Data can be taken from the hard ware stored in an external file then read into a testbench and used as the input stimulus Many simulators ac cept both waveform and testbenches as input stimulus consult your simulator user s manual for acceptable formats Some popular simulators are Mentor Graphics ModelSim Aldec s Riviera www embedded com embedded systems design JANUARY 2008 specific design flaws and Altera s Quantus II There are three levels of simula tion register transfer level RTL functional and gate level Each occurs at a specific place in the development process RTL follows the design stage functional follows synthesis and after implementation is completed the gate level simulation Generally the stimu lus developed for t
6. closed body of a d Classes in unions so a structure or unioi structure scope each structure or their respective s look up stru members in much the rations to control storage duration and linkage First show you how they fit into the syntax Then explain their impact on semantics Every declaration in C and C has two principal parts a sequence of zero or more declaration specifiers and a sequence of zero or more declarators separated by commas For example static int x N declaration specifiers declarator A declarator is the name being declared possibly surrounded by operators such as O and in the case of C amp In the previous example x N is a de clarator indicating that x is an array of N pointers to e Each object in and C has of the following three storage durations static automatic and dynamic something where that something is the type specified in the declaration specifiers A declarator may contain more than one identifier The declarator x N contains two identifiers x and N Only one of those identifiers is the one being declared and it s called the declarator id The other s if any must have been declared previously The declarator id in xIN is x The term declarator id comes from the C stan dard The C standard makes do without it but I find it to be a useful concept Some of the declar
7. meaning it can perform synthesis and the design is synthesized using this tool little or set up is required for PAR However if a third party synthesis tool is used the implementation tool must be set up which involves directing the PAR tool to the synthesized netlist and pos sibly a constraint file The constraint file contains information such as max imum or minimum timing delays for selected signal s and I O pin assign ments Pin assignments can be automatic performed by the tool or manual dictated by the designer Automatic pin assignment is generally the best option for new designs as it lets the tool more effectively route the design without having fixed pin assignments It may be necessary to manually assign signals to specific pins to achieve easy board routing to provide the mini mum signal route for timing critical signals or be compatible with legacy designs There are numerous reasons why manual pin assignments would be essary But regardless of the reason the designer must make this information available to the PAR tool which is done by creating a user constraint file that s used by the PAR tool After com pleting setup the PAR process can be gin Each PAR tool may have a slightly different approach to design imple mentation so consult your PAR docu mentation Xilinx s Foundation or Project Navigator performs design im plementation in three steps translate fit and gene
8. other trademarks are the property of their respective owners Perforce Fast Software Configuration Management Perforce Time lapse View PERFORCE SOFTWARE Introducing Time lapse View a productivity feature of Perforce SCM Time lapse View lets developers see every edit ever made to a file in a dynamic annotated display At long last developers can quickly find answers to questions such as Who wrote this code and when and What content got changed and why Time lapse View features a graphical timeline that visually recreates the evolution of a file change by change in one fluid display Color gradations mark the aging of file contents and the display s timeline can be configured to show changes by revision number date or changeset number Time lapse View is just one of the many productivity tools that come with the Perforce SCM System Download a free copy of Perforce no questions asked from www perforce com Free technical support is available throughout your evaluation CES AND EMBEDDED COM Embedded Systems Design Storage class specifiers don t www embedded com aedi cope ar caue JANUARY 2008 VOLUME 21 NUMBER 1 TALES SOG ator age duration Heres the sec ond part in a series on scope Cover Feature storage allocation and linkage The art of FPGA construction BY GINA R SMITH Working with FPGAS isn t intimidating when you know the Tuan yea
9. the core for which the thread s memory references are local One way to do this is simply to take advantage of the afore mentioned binding capabilities of the SMP operating system You can locate thread required memory to core s lo cal memory bank and bind the thread to the same core The NUMA aware op erating system may automate this opti mization of memory and thread bind ing Although NUMA isn t available in mainstream embedded devices there are rumors about future parts that could provide an intriguing alternative to SMP in the future When moving to an SMP platform for the first time developers must be prepared to use tools required in the multicore development debugging and optimization process Tightly coupled multicore processors often provide a systems The only way to be payoff is to run the software on an SMP for synchronized running and halting of the debugged cores RUN MODE MULTICORE DEBUGGING Run mode debugging is also useful for SMP systems as the cores are never stopped Rather the debugger controls application threads using a communi cations channel usually Ethernet be tween the host PC and a target resident debug agent The SMP operating system typical ly provides an integrated debug agent and the associated communications device drivers that s operating sys tem aware and provides flexible op tions for interrogating the system For example one operating system come
10. the other hand if the design is only one file the top level entity decla ration defines all of the I O that repre sents physical FPGA pins All I O sig nals defined in this section must have unique names indicated signal direc tion input or output and number of bits reserved for the signal From List ing 1 reset is an input only one data bit wide and is a std logic data type The keyword END followed by the enti ty s name signifies the end of the entity All entities must be associated with an architecture section Architecture section The architecture section which con tains the circuit description is the body of the VHDL source code The li braries packages and signals work to JANUARY 2008 embedded systems design www embedded com gether to develop the desired func tions Like the entity each architecture must have an assigned name The for mat for declaring the architecture is the reserved word Architecture fol lowed by its name Door monitor then the reserved word Of then the entity s name Monitor Signals not de fined in the entity section are defined in this section The signal assignment format con sists of the reserved word Signal fol lowed by the signal name and then the data type such as std logic and std logic vector as in Listing 1 Like names defined in the entity each signal name must be unique and have a data type This section is also for de claring c
11. to migrate to 32 bits and memory is becoming very inex pensive Linux is great if what you want is a standard and open plat form with extensive networking sup port and lots of already written and ready to go standard applications That s why Linux is becoming very popular on upscale cellular phones and handheld PCs If all you need to do is read a sensor and send a packet somewhere over TCP IP there are bet ter solutions and not all of them cost alot of money like the Thread X RTOS CONTINUED ON PAGE 43 www embedded com embedded systems design JANUARY 2008 7 The Newest Embedded Technologies New Products from WiFi BLUETOOTH WLAN NETWORK USB EMBEDDED CONTROL NETWORK USB WLAN GPS BLUETOOTH ETOOTH e ZIGBEE USB MN RK lantronix a The ONLY New Catalog Every 90 Days Experience Mouser s time to market advantage with no minimums and same day shipping of the newest products from more than 335 leading suppliers a tti company The Newest Products For Your Newest Designs www mouser com over 900 000 Products Online 800 346 6873 BY Dan Saks declaration is a source code con struct that associates at tributes with names A declaration either intro duces a name into the current translation unit or redeclares a name intro duced by a declaration that appeared earlier in the same translation unit A declaration might also b
12. to use all the contents in the std logic 1164 package When a designer has specific con stants formulas processes and proce dures that are used by multiple mod ules or submodules within their design he or she can create a custom package By doing this the functions in the user defined package can be shared with other designers and proj ects A user defined library package is an easy way to re peatedly use spe cific HDL elements in multiple files with the luxury of only defining its el ements once Assuming a designer cre ates a package called my package and stores this package in the library called Test the following command would make the package visible thereby al lowing its contents to be used in the source file LIBRARY Test USE Test my_package ALL User designer defined packages are similar to those supplies by vendors such as Xilinx whose packages contain elements such as RAMs counters and buffers Xilinx s vcomponents pack age contains constants attributes types and components that become available once the library and package are visible to the design The package contains components like ANDS which is a three input AND gate and NAND3 a three input NAND gate The vcomponent package provides timing information the I O port names used to instantiate components in design 19 cover feature Multiple source files are created for each function and are interconnected through
13. ADE7 169 and C805 IFAxxx F xx More information www keil com c5 I C166 Keil C166 is the complete software development environment for Infineon C166 XC166 XC2000 and ST Microelectronics ST10 with debug and programming support via ULINK2 More information www keil com c 66 ARM RealView MDK combines the best in class ARM C C Compiler the genuine Keil Vision IDE Debugger Simulator and the royalty free RTX RTOS Kernel More information www keil com arm Keil MCB evaluation boards come with code size limited tools and extensive example projects that help you get up and running quickly with your own embedded application om boards More information www kei cover feature Listing 2 VHDL Testbench is used to provide stimulus to the VHDL source code Lasestkereereerreenent Header Section PEERAA AAAA EEEE nere Name Beckie Smith Date January 28 2005 Filename tb door monitor vhd Optional a Description This testbench is used to verify door chime en signal is set high 500ns after door status goes high Revision History Date Initials Description Leey LIBRARY TEEI Wedemon USE IEEE std logic 1164 ALL Entity ENTITY testbench IS END testbench ARCHITECTURE tb monitor OF testbench IS COMPONENT monitor PORTC reset IN std logic power on reset door status IN std logi door closed low clock 20mhz IN std logi 20MHz clock door chime en OUT std logi
14. IN IF reset 1 THEN chime enable 705 clear chime enable reset_start_timer 0 clear timer reset signal timer S00ns OTHERS gt 05 clear chime timer ELSIF rising edge clock 20mhz THEN IF start 5005 timer 17 THEN door has been opened timer S00ns imer S00ns 1 after 2 ns start counting 500nsec S jal timer S00ns 1010 THEN test for 500ns equential enable 1 after 2 ns set door chime enable statements reset start timer 1 after 2 ns reset door chime timer woe Injected delay chime_enable 0 after 2 ns don t set door chime circuit END IF END IF END PROCESS END door monitor 18 JANUARY 2008 embedded systems design www embedded com vision history Listing 1 shows an ex ample of a VHDL file s behavior Be cause HDLs are similar to software firmware designers should follow some of software development rules HDL GUIDELINES 1 Use comments to provide code clarity 2 Indicate active low signals by n _n b at the end of the name 3 Signal names should be relatively short but descriptive For example A good signal name would be CEn for an active low chip en able A bad signal name would be active_low_chip_enable Use underscores name description for clarity e Synchronize signals to change on a clock edge Process routes modules and so forth should per form a single function formatting s
15. RIO Embedded systems with FPGAs DSPs and microprocessors Hardware Platform LabVIEW FPGA Module LabVIEW Microprocessor SDK NATIONAL INSTRUMENTS The C standard lists five storage class specifiers auto extern register static and typedef howev er C considers typedef to be a storage class specifier for syntactic convenience only C doesn t consider type def as a storage class so I won t either The C standard lists mutable as another storage class specifier but this too is more for syntactic conven ience than anything else Unlike the other storage class specifiers mutable has no impact on storage duration or linkage I don t consider it a storage class specifier for the purpose of this discussion A declaration need not have any storage class specifi er and can have no e more than one Allocating storage for an object with STORAGE DURATION The storage duration of an object determines the lifetime of the stor age for that object That is it determines that part of program execution during which storage for the object must exist Programmers of ten use the term storage allocation instead of storage du ration but both the C and C standards favor the lat ter Only objects have storage duration Enumeration constants functions labels and types don t Each object in C and C has one of the following three storage durations static automatic and dynamic The C standard lists the th
16. The Official Publication of The Embedded Systems Conferences and Embedded com VOLUME 21 NUMBER 1 JANUARY 2008 ant LLON NS QV e S Hominy 0 b VY SV AND 50 CUT IN DEVELOPMENT TIME a We V THAT S MODEL BASED DESIGN target the engineering Need to make sure they line up for your product first a bh E allait Green Hills SOFTWARE With more than half of the product development cycle consumed by debugging finding bugs faster means your product will get to market first Green Hills Software provides premier tools that pinpoint the most elusive bugs in minutes instead of hours or days With the development environment s time saving code analysis tools errors in code are automatically found long before the debugging process begins MULTI and the TimeMachine debugger allow developers to easily find every bug so that shipping a product with known problems becomes a thing of the past With Green Hills Software s sophisticated technology you ll produce a better product and get it out the door long before your competition Call 800 765 4733 or visit us on the web www ghs com to learn more 1006 Green Hills Software Inc Green Hills the Green Hills logo MULTI and TimeMachine are trademarks or registered trademarks of Green Hills Software Inc in the US and or internationally All
17. as sub sp 12 Allocating automatic storage fc local objects costs more but no more runtime than alloc for just one A function may also declare local objects in nested blocks For example in int fooCint n t char p if p NULL int vi H return n Y function foo has a block nested within the if statement That block declares a local ig object v In this case the lifetime of the storage for v begins oe upon entry into the nested block and ends upon exiting the block However many compilers will generate code for foo to allocate the storage for v along with all the other local objects upon entering the func tion and deallocate the storage for v upon exiting foo Thus a compiler might generate code that extends the actual lifetime of the storage for a local object but it s very hazardous for programs to try to exploit these longer lifetimes Dynamic allocation is typically much slower than automatic allocation It often involves executing tens of instructions possibly more than a hundred Nonethe less you can use it to manage memory very economical ly and so it may be worth the price eral ck space LINKAGE ON THE HORIZON As I mentioned earlier not only can a declaration specify type scope and storage duration it can also specify linkage I thought linkage would be the subject of this column until I started writing and realized that I needed to cover storage dura
18. ation specifiers leading up to a declarator can be type specifiers such as int unsigned Tong const or a user defined type name They can also be storage class specifiers such as extern or static or function specifiers such as inline The type specifiers contribute to the type of the de clarator id the other specifiers provide non type infor mation that applies directly to the declarator id For ex ample static unsigned long int x N declares x as an object of type array of N pointers to unsigned long int The keyword static specifies X s storage class 10 JANUARY 2008 embedded systems design www embedded com NI LabVIEW Limited Only by Your Imagination Communicate via multiple protocols including Bluetooth Build and program robots with LEGO MINDSTORMS NXT using software powered by NI LabVIEW Graphically program concurrent real applications Develop your human machine interface HMI display Target 32 bit Independently control microprocessors multiple servo motors and FPGAs Real Time and Embedded Signal Processing High Performance Test Industrial Control PRODUCT PLATFORM When the LEGO Group needed parallel programming LabVIEW Real Time Module and motor control tools intuitive enough for children it selected graphical software powered by NI LabVIEW With LabVIEW graphical system design domain experts can quickly develop complex embedded real time NI Compact
19. bedded design on the world s most flexible system platform With the latest processing breakthroughs at your fingertips you can readily meet the demands of applications in automotive industrial medical communications or defense markets Architect your embedded vision Choose MicroBlaze the only 32 bit soft processor with a configurable Get the Complete Embedded Solution MMU or the industry standard 32 bit PowerPC architecture Select the exact mix of peripherals that meet your needs and stitch them together with the new optimized CoreConnect PLB bus Build program debug your way Port the OS of your choice including Linux 2 6 for PowerPC or MicroBlaze Reduce hardwarelsoftware debug time using Eclipse based IDEs together with integrated ChipScope analyzer Eliminate risk amp reduce cost No worry of processor obsolescence with Xilinx Embedded Processing technology and a range of programmable devices Reconfigure your design even after deployment reducing support cost and increasing product life Order your complete development kit today and unlock the future of embedded design www xilinx com processor SZ XILINX E www xilinx com processor 9 3 At the Heart of Innovation 2007 Xii Ic AB ight reserved MINX the Xl logo and other designated brands ince herein are trademarks of Xr Inc Al ather trademarks are the property of their respective owners www e
20. e EPGA FPGA information includes the vendor s name the specific part or fam ily the package type and the speed The synthesis process takes this information and the user defined constraints and produces the output netlist A con straints file specifies information like the critical signal paths and clock speeds After completing set up syn thesis can begin General synthesis flow for tools like Synplicity s Synplify in volves three steps creating structural element optimizing and mapping Figure 3 shows a synthesis flow diagram The first step in the synthesis process is to take the HDL design and compile it into structural elements This means that the HDL design is technology independent Synplify graphically represents this step as the RTL Schematic View viewable in Synplify The next step involves opti mizing the design making it smaller and faster by removing unnecessary logic and allowing signals to arrive at the inputs or output faster The goal of the optimizing process is the make the design perform better without chang ing the circuit s functions The final step in the synthesis process involves mapping or associat ing the design to the vendor specific architecture The mapping process takes the design and maps or connects it using the architecture of the specific vendor This means that the design connects to vendor specific compo nents such as look up tables and regis ters The optimized n
21. e You may also recognize the Portelligent name from the Prius Tear Downs we per formed live at the Embedded Systems Conferences The company had a big hand in that project The acquisition of Semiconduc tor Insights which occurred last July hasa similar meaning to our group Semiconductor Insights is also known for its Tear Downs but they perform them at the IC level rather than at the system level For example the company was the first to tear apart and analyze Intel s latest micro processor the Penryn 45 nm device Semiconductor Insights also serves as a global IP and patent tech nical advisor They have the ability to perform technical investigations of patents ICs and electronic systems One division of the company bench marks competing devices improves time to market and solves technical problems while a second division helps technology companies and le gal professionals evaluate develop and monetize their IP Together the two companies will offer a combined searchable database of over 40 000 components and ICs which is an invaluable resource for designers Lik fe Richard Nass rass cmp com JANUARY 2008 embedded systems design www embedded com bedded Design doc in Cher Richard Nass 201 288 1906 assemp com Managing Editor Susan Rambo srambo emp com Conlibulig Editors Michael Barr John Canosa Jack W Crenshaw Jack Ganssle Din Saks Larry Mittag AA D
22. e a definition which pro vides not just some of the attributes of a name but rather all the information the compiler needs to cre ate the code for that name Among the attributes that a scope An object s type determines the object s size and memory address alignment the val ues the object can have and the operations that can be performed on that object A function s type specifies the function s parameter list and return type I ve discussed the concept of data types in prior columns I devoted my November column to the concept of Dan Saks is president of Saks amp Associates C C training and consulting company For more information about Dan Saks visit his website at www dansaks cam Dan also wel comes your feedback e mail him at dsaks wittenberg edu Storage class specifiers and storage duration Storage class scope as it applies to C and C In essence the scope of a is that portion of a trans lation unit in which the name is visible C and each support sev eral different kinds of scope summarized in the sidebar entitled Scope regions in C and C see page 10 Scope is closely re lated to but nonethe less distinct from the concepts of storage du ration and linkage The storage duration for an object determines how and when the storage for that ob a name may have are its type pecify scope but combine ject comes and goes Linkage scope s
23. e code DESIGN SYNTHESIS While some designers prefer to proceed directly to simulation I prefer to syn thesize the design Synthesis is the process that reduces and optimizes the HDL or graphical design logic Some third party synthesis tools are available asa part of the FPGA vendor s com plete development package Synplicity s Synplify and Mentor Graphics Leonar doSpectrum Precision RTL and Preci sion Physical are examples of third par ty synthesis tools Xilinx offers ISE Project Foundation which is a com plete development application that in cludes a synthesis tool Altera has Quar tus II Integrated Synthesis QIS Although some FPGA vendors offer synthesis they still recommend usinga third party s synthesis tools The syn thesis tool must be set up prior to actu ally synthesizing the design Synplicity s Synplify goes through a common set The design serves as the input to Ihe synthesis process resulting in a netlist that s used as the input to the place and route or implementation tool Figure 3 Output s JANUARY 2008 embedded systems design www embedded com ch simulation level offers various benefits RTL uncove functional level verifies that the pre and post synthesis design are equivalent and the gate level uncovers timing errors s logic errors the up process as it involves providing the design files completed during design stage and information about th
24. e to detect and correct errors such as wrong part numbers or misuse of terms and terminology found in requirements and other documents Regardless of your final product FPGA designers must follow the same basic process The FPGA development stages are design simulation synthesis and implementation as shown in Figure 1 The design process involves converting the requirements into a for mat that represents the desired digital function s Common design formats are schematic capture hardware description language HDL or a combination of the two While each method has its ad vantages and disadvantages HDLs generally offer the greatest design flexibility 14 JANUARY 2008 embedded systems design www embedded com cover feature The FPGA development process can be divided into four functions design synthesis simulation and implementation HDL design entry Schematic capture Register transfer level E Melt J E Combination M T L o Functional N Implementation ign s logic placed amp routed in FPGA iain Programming fle ganerated xs Timing back annotated Figure 1 SCHEMATIC CAPTURE sign process must be repeated if a dif Schematic capture the graphical de piction of a digital design shows the actual interconnection between each logic gate that produces the desired output functi
25. elization involves using a tool to discover a program s parallelizability and convert the code into an explicitly parallelized program Some forms of parallelization focus An example of a symmetric multicore system is shown specifically on loops This approach is sensible loops tend to be execution bottlenecks and sometimes can be con verted into parallelizable iterations However many loops aren t paralleliz able even with a very smart compiler and many applications simply don t If software has the potential for parallelism but isn t currently multithreaded then SMP could still be a good fit benefit from this approach Parallelizing compilers do exist but the embedded software communi ty hasn t found automatic paralleliza tion autoparallelization for short technology to be of general use due to the compilers focus on data level par allelism Certainly a developer would n t take a legacy embedded control ap plication running on a unicore platform and expect a parallelizing compiler to convert the application into something that runs optimally on an SMP Autoparallelization may in deed boost performance in places es pecially when the user can add some hints and directions to aid the compil er known as semi automatic paral lelization but a systemwide approach is required in general Future innova JANUARY 2008 embedded systems design www embedded com tions in autoparallel
26. emptive scheduler Trouble will ensue if the software is using prior ity as a means of synchronization For example software may manually raise a thread s priority to preempt another thread On an SMP system this pre emption won t occur if the two threads are the highest priority runnable threads on a dual core system Embed ded designers must analyze their sys tems to ensure that the SMP scheduling algorithms won t pose a problem CORE BINDING If your embedded system has tight real time deadlines than SMP may pose a problem context switches can be de layed due to the overhead of inter processor interrupts IPIs and cache inefficiency For example when an in terrupt service routine executes on one core and signals a thread to run the SMP scheduler may decide to run the thread on a different core requiring an The high speed interconnect is the centerpiece of the NUMA system Memory Memory Core 0 Core 1 HER Real time operating system Applications Figure 2 IPL If the thread didn t last run on that same core there will be additional overhead to rewarm the cache with the thread s code and data SMP operating systems tend to migrate threads mak ing it difficult to predict whether this overhead will be incurred The good news is that most SMP operating systems provide the ability to map interrupts and bind threads to USB serial devices USB keybds mice HIDs USB to Etherne
27. etlist is the out put of the synthesis process This netlist may be produced in one of sev eral formats Edif is a general netlist format accepted by most implementa tion tools while xnf format is specific to Xilinx and is only recognized by Xilinx s implementation In addition to the optimized netlist many synthesis tools like Syn SuperH Flash Microcontroller ede Reaches Speeds up to 160MHz Superscalar performance high speed on chip flash memory access and much more No 1 supplier of microcontrollers in the world proudly presents the SuperH family of devices SuperH devices equipped with the SH 2A core offer superscalar performance at speeds of 160MHz allowing high speed access to on chip FLASH memory and up to 200MHz CPU performance Enhanced features that include on board Floating Point Unit FPU Multiply Accumulate Unit MAC High Speed Barrel Shifter and advanced addressing modes deliver DSP like performance in RISC style architecture without the complicated programming associated with a DSP engine The SuperH RISC engine and the SH 2A core are establishing new performance standards in the industry and are ideal for systems that demand real time high precision control and require a combination of high performance CPU with high speed flash tones Fat SuperH MCU Lineup p Multifunction Timer 2 me B e 207 Ee m gu 120MHZ World s fastest embedded FLASH with 12 5
28. external door chime enable END COMPONENT SIGNAL reset std logic 3 reset initially set high SIGNAL door status std logic tor door initially closed SIGNAL clock 20mhz std logic o 20MHz clock starts low SIGNAL door chime en std logic Aries CONSTANT clock 20mhz time time r 25 0 ns half 20MHz clock period BEGIN display monitor PORT MAP reset reset door_status clock 20mhz door chime en reset create clk PROCESS This process generates the BEGIN WAIT FOR clock 20mhz time clock 20mhz END PROCESS door status END tb monitor door status clock 20mhz door chime en 0 AFTER 50 00 ns 20MHz input clock NOT clock 20mhz 1 AFTER 200 00 ns door is opened only has two signals reset and clock 20mhz in its sensitivity list Sig nals in a process that update or change following a clock edge are called syn chronous signals Start S00ns timer in the checking door status process is an example of a synchronous signal The architecture section closes by using the reserved word END followed by the architecture s name SIMULATE OR SYNTHESIZE One or more designers may be respon sible for a design A number of factors influence the numbers designers need ed such as design complexity and size JANUARY 2008 embedded systems design www embedded com the designers skill level and the de signers schedule and availability Re gardless of the number of desi
29. g to assume the testing is performed by a code tester not the original designer Simulation is the act of verifying the HDL or graphical digital designs prior to actual hardware validation The circuit s input signal characteris tics are described in HDL or in graphi cal terms that are then applied to the design This lets the code tester ob serve the outputs behavior It may be necessary to modify the source code during simulation to resolve any dis crepancies bugs or errors Simulation inputs or stimulus are inputs that mimic realistic circuit I Os Stimulus forces the circuit to operate under various conditions and states The greatest benefit of stimulus is the ability to apply a wide range of both valid and invalid input signal charac teristics test circuit limits vary signal parameters such as pulse width and frequency and observe output behav ior without damaging hardware Stim ulus can be applied to the design in ei ther HDL or graphical waveform format Generally when a tester or de signer speaks of a testbench he s refer ring to applying stimulus to the design in the form of HDL Listing 2 shows an example of a VHDL stimulus or testbench file The testbench looks similar to the Ideally the designer would perform minimal simulation leaving the more stringent testing to a code tester The original code designer shouldn t test his own code because he s less likely to de
30. gners after the design is completed there are a couple of options He or she may choose to simulate or synthesize the design There isn t a hard and fast rule stating you must simulate before syn thesis There are advantages to each option and designers must determine which step is most beneficial In fact there may be times when a designer decided to simulate following the completion of the initial design while another time decide to synthesize Each option lets the designer detect and correct different types of errors Simulating the design prior to syn thesis allows logic errors and design flaws to be resolved early in the devel opment process Synthesizing lets the designer resolve synthesis errors prior to logic errors and design flaws Ideal the designer would perform mini mal simulation leaving the more stringent testing to a code tester The original code de signer shouldn t test his own code because he s less likely to detect specific de sign flaws such as 1 Misinterpretation of re quirements if the de signer misunderstood a requirement he or she will test and evaluate the design based on that misunderstanding 2 Its more difficult for a person to find his own errors A third party generally tests the code more rig orously and is more eager to find bugs than the original designer Regardless of who performs the simulations the process is the same For the sake of this article we re goin
31. he RTL simulation is reusable without modification for each level of simulation SIMULATION The initial simulation performed im mediately after the design stage is the RTL simulation This involves directly applying the stimulus to the design RTL simulation only lets designers verify that the logic is correct No realistic timing infor mation is available to the simulator There fore no serious timing exists for the design The only timing infor mation that can be available to the simulator is tester generated Much like input stimulus a tester can insert simulated or injected delays into the original HDL design as in Listing 1 Most synthesis tools discussed later will ignore these simulated delays Applying test stimulus to the syn thesized or optimized netlist produced by a synthesis tool is a functional simu lation Optimized netlists produced by non vendors apply estimated delays that produce more realistic simulation output results The main benefit from performing functional simulation is that it lets the tester verify that the synthesis process hasn t changed the design Many but not all third party simulation tools accept post synthesis netlists Gate level simulation involves ap plying stimulus to the netlist created by the implementation process All in ternal timing delays are included in this netlist which provides the tester with the most accurate design output Again many but not all third pa
32. how can you determine whether SMP is a sensible choice Several key re quirements enable you to realize the promise of SMP First the soft ware must be partitioned and parallelized to take advantage of the hardware concurrency Second operating systems must provide the load balancing services required to enable distribution of software 28 JANUARY 2008 embedded systems design www embedded com 30 Figure 1 onto the multiple processing elements And finally you will need to learn and use development tools specifically tai lored to the difficult task of multicore system debugging so you can find con currency problems quickly and avoid time to market delays PROGRAMMING FOR CONCURRENCY If your software has no po tential for application level parallelism for example a simple control system then SMP is not for you If software has the potential for paral Jelism but isn t currently multithread ed then SMP could still be a good fit There are two ways to partition and parallelize software to take advan tage of multicore concurrency manual and automatic parallelization Manual parallelization requires the program mer to deduce which parts of the ap plication can be parallelized and write the code such that this parallelism is explicit For example the developer can place code into threads that will then be scheduled by an SMP operat ing system to run concurrently Automatic parall
33. ird kind of storage duration as allocated rather than dynamic but then never uses the term after that I l call it dynamic An object declared at file scope in C or namespace scope in C or declared with the storage class speci fier extern or static has static storage duration The lifetime of the storage for that object is the entire time that the program is executing An object declared at block scope and without the storage class specifier extern or static has automatic storage duration The lifetime of the storage for that ob ject begins upon entry into the block immediately en static storage d costs nothing Storage duration for objects in and closing the object s declaration and ends upon exit from the block Entering an enclosed block or calling a func tion suspends but doesn t end the execution of a block When a program allocates storage for an object by calling an allocation function such as mal Toc in C or an operator new in C that object has dynamic storage duration The lifetime of the object s storage lasts until the program passes the address of that object to a corre sponding deallocation function such as free in C or an operator delete in Table 1 shows how C and C determine the storage duration for an object based on the storage class specifi er in the objects declaration and the scope in which the declaration appears For example the first row below the co
34. irector Debee Rommel dronmelicnp com European Correspondent Colin Holland olin holland biternet conr Embedded com Ste Editor Bernard Cale dcletaem org Producion Manager Pete Sibilia pseibili emp com Director of Audiences Services Kristi Cunningham deuningham enp com Subscription Customer Service Box 2165 Skokie IL 60075 800 577 5396 tol free Fx M7 763 9605 embeddedsystemsdesignhalldata com evemibeddedostensdesignautomerservin com Back issues Xely Miniban 800 444 4881 ll fee Fux 705 838 7566 lide Reprints Epis and Permissions PARS International Corp 102 West 38th Street Sixth Floor New York NY 10018 212 221 9595 Fax 212 221 9195 Gepris parsmi com wor magreprints com quickquote asp Publisher David Blaza 415 947 6029 diesen com Editori Review Booed Michal Barr Jack W Crenshaw Jak G Gana Bill Gait Nigel Jones pur Robert fles Pip Chapnick CMP Gere Gp Anne Marie Miller Corporate nir Vice reden Saler Marve fall Soner Vee rene Haman MaieMyee Senor ee President ane Senier Vier hreadX delivered a first rate performance for us and helped the ion return extraordinary high resolution images from Mars MRO spacecraft depicted in Mars orbit NASA When they wrote the embedded software that controls the cameras aboard the Mars Reconnaissance Orbiter MRO a team of Ball Aer
35. ization could be more effective POSIX POSIX is a collection of open standard APIs specified by the IEEE for operat ing system services POSIX threads or Pthreads is the part of the standard that deals with multithreading The Pthread APIs provide interfaces for run control of threads synchronization primitives and interprocess communication mechanisms While other multithread ing standards exist Pthreads is the most generic widely applicable standard Pthreads are supported by a wide range of embedded operating systems such as Integrity LynxOS and QNX Due to POSIX s ubiquity a large base of application code exists that can be reused for embedded SMP designs Another strong advantage of POSIX is its independent conformance valida tion The list of POSIX implementa tions that have been certified confor mant to the latest POSIX specification can be found at http get posixcertified ieec org cert prodlist tpl CALLER index tpl By programming to the POSIX API developers can write multithread ed applications that can be ported to any multicore platform running a POSIX conformant operat ing system In embedded systems add on soft ware components can often be easily mapped to individual threads For ex ample a TCP IP network stack can exe cute within the context of one POSIX thread same for a file system server au dio application and so forth Because of this many embedded software sys tems can take ad
36. lumn headings says that an object declared with no storage class specifier at block scope has automatic storage duration but if it appears at file scope in C or at namespace scope in C it has static storage duration If it appears as a structure or class member then it has the storage duration of the structure or class object of which it s a member None of the entries in Table 1 specify dynamic stor age allocation Unlike objects with static or automatic storage duration a program can t declare any objects with dynamic storage duration A program can create them by calling an allocation function it just can t de clare them uration typically at run time THE MECHANICS OF STORAGE ALLOCATION The exact manner in which static storage is allocated and deallocated depends on the target platform However al locating storage for an object with static storage dura tion typically costs nothing at run time because the com piler linker and loader together determine the size and address of the object before the program starts running Storage At At Asa dass block scope in C or structure member in C or scope namespace scope in at class scope in C automatic static storage allocated as part of enclosing object automatic invalid invalid extern static static invalid register automatic invalid invalid static static static invalid in C static in C 12 JANUARY 2008 embedded system
37. mbedded com forum ice article Jack Ganssle The transistor sixty years old and till switching December 2007 p 53 One minor point before the galena and cat s whiskers there was the coherer a strange concoc tion of metal filings between two elec trodes It exhibited a large resistance drop when subjected to an RF signal from the antenna that would sound a bell and vi brate the device back to its dis high resistance state for CW only of course not telephony A Google search on coherer yields some fascinating references including DIY coherers for the curious they actually work After the coherer came the magnetic detector IIRC a moving band of iron Roger Jones My father worked for RCA as an engi neer from the 50s through the 705 One year at the open house during the Christmas holidays they gave us all an inhouse history of RCA The founder of RCA David Sarnoff was a teenage telegrapher for the Marconi company and was on duty when RMS Titanic went down He manned his key for many hours compiling lists of the sur vivors the missing and the dead This story along with many others encour aged me to enter this field How far we have come in just the 60 years of the transistor and the 100 years or so of electronics What will the next 100 years hold Thomas Mazowiesky While I was working at Bell Laborato ries in the late 1970s a story was going around abo
38. nd the Embedded Systems Conferences along with lots of other publications and Web sites including EE Times and TechOnline recently made two acquisitions Normally I wouldn t mention events that occurred on the business side of the house in these pages However these two acquisi tions could have a great affect on the coverage that you ll see in these pages The two acquisitions are Semi conductor Insights www semiconduc tor com and Portelligent www tear down com If you re not familiar with one or both of these companies let me shed some light on them The Portelligent acquisition was finalized in November The compa ny s claim to fame is doing Tear Downs By doing that they gain in telligence into the design of mobile wireless personal and consumer electronics With this information designers can make faster better and more cost effective decisions about their competitive positioning tech nology options investment strategy intellectual property IP position and marketplace opportunities Portelligent was formed in 2000 as a spinoff of an Austin based research consortium Richard Nass is editor in chief of Embedded Systems Design You can reach him at mass cmp com We ve worked with the Portelli gent team for years You may have noticed that the company s Tear Downs have been appearing in our pages and on Embedded com for some time now as well as in Times and on TechOnlin
39. ns read access time Fast Real Time Control Register Bank architecture 15 Banks for context switching enables 37 5nsec 6 cycles interrupt latency time High Integration 512KB On Chip Flash 32KB On Chip RAM Advanced 16 bit PWM timers to drive two motors simultaneously F Dovices with FPU 128 usec 12 bit A D conversion with 3 sample amp hold circuits Vot unie 3 Superscalar Performance Two instructions are executed per cycle at 160MHz Source Gartner March 2007 2006 Worldwide Microcantraller Vendor Revenue 007188 Get Started Today Register to qualify for a SuperH MCU Kit www america renesas com ReachSH c ROK57211580008E HsoooskcunH RenesasTechnology Corp no cove feat plify will produce a netlist for gate lev el simulation and other report files Stimulus applied to this netlist instead of the original HDL design produces the functional level simulation which lets the designer verify that the synthe sis process hasn t changed the design s functions At this point synthesis is complete and ready for the implemen tation process Each FPGA vendor has its own implementation tool such as Xilinx s Project Navigator and Altera s Quartus IT s DESIGN IMPLEMENTATION The final stage in the FPGA development process is the design implementation also known as place and route PAR If the FPGA vendor has a com plete development tool
40. on s Many of these log ic gate symbols involve proprietary i formation making them available to the designer only through the specific vendor s component library Schematic capture designs that mainly consist of proprietary symbols make the design unrecognizable by competitors FPGA development tools The proprietary nature of this type of design makes it vendor dependent and the entire de ferent vendor is used Examples of schematic capture tools are Viewlogic s ViewDraw and HDL EASE The main advantage of schematic capture is that the graphical representation is easy to understand However its major drawback is an in crease in cost and time to reproduce a design for different vendors due to the design s proprietary nature HDL METHOD Hardware description languages HDLs use code to represent digital functions Firmware often refers to 16 JANUARY 2008 embedded systems design www embedded com the resulting HDL code HDLs are a common and popular approach to FPGA design You can create the source code with any text editor Spe cial HDL editors like CodeWright and Scriptum a free HDL text editor by HDL Works offers features such as HDL templates and highlighting re served words not found in ordinary text editors HDLs can be generic supported by multiple simulation and synthesis tool sets like Verilog or VHDL Very High Speed IC HDL or vendor specific like Altera s Hardware Descrip
41. onstants variables and other data types Signals can be thought of as wires used to connect functions and store values After defining all the design s signals the designer is ready to devel op the code that de scribes the desired functions The re served word Begin sig nifies the start of the next subsection which combines the concur rent and sequential statements Concurrent statements update or change value at anytime The signal assignment imme diately following the first reserved word BEGIN in Listing 1 is an example of a concurrent statement Sequential statements update or change value when signals in the sensitivity list see Listing 1 change state Signals in processes are sequential statements Most processes have a sensitivity list process name and circuit description HDL code between reserve words BEGIN and END PROCESS The process name precedes the reserved word Process and the sensitivity list is en closed in the parenthesis Listing 1 contains two processes The first is checking_door_status which has a sensitivity list that contains three signals reset clock_20mhz and reset_start_timer The second process is set_alarm_enable which gt KEIL An ARM Company ARM Microcontroller Solution ARM Powered Microcontrollers available from many silicon vendors offer high computing performance along with rich peripherals Turn ARM Microcontrollers into your solution for c
42. optionally in its own window At the same time the tool provides controls By collecting a system s execution history and making it available for play back within debugging tools even the most difficult multicore bugs become easy to find and fix If you re new to SMP choosing a processor with on chip trace capabilities may be desirable Multicore trace capability is just starting to arrive on multicore proces sors A major technical challenge that has kept this hardware feature from becoming a reality involves finding a way to keep up with trace data emitted simultaneously from multiple cores An emerging solution is high speed se rial trace HSST is to run the software on an HSST replaces the SMP However engineers SMP s single memory bus architecture may generation of sitting on the SMP fence loa fit fo i i parallel trace ports by may be excited about the a poor fit for memory and 1 O bound taking advantage of prospect of NUMA non applications relative to compute intensive high speed serial bus uniform memory access systems NUMA is similar to SMP except that the system contains more than one memory source where the time to access each memory source varies This architecture is depicted in Figure 2 NUMA represents a compromise in which code can still be shared and auto matically load balanced in the manner of an SMP Yet you can optimize memo ry access times by running threads on
43. ospace and Technology Corp engineers led by Steve Tarr knew they only had one chance to get it right If there was a seri ous fiaw anywhere in the software the 720 THREAD million spacecraft might have no more value than a digital camera dropped in a bathtub Tarr and his team wrote 20 000 lines of code and used Express Logic s ThreadX RTOS The software has worked flawlessly resulting in history making photographs such as the one to the left that shows the Opportunity rover traversing the surface of Mars With its intuitive API rock solid reliability small memory footprint and high perfor mance ThreadX delivered the goods for NASA s MRO ThreadX is in over 450 million electronic devices from NASA s MRO to HP s printers and digital cameras Which RTOS will you choose for YOUR next project Small Memory Footprint Fast Context Switch Fast Interrupt Response Preemption Threshold Technology Picokernel Design Event Chaining Broad Tools Support Supports All Leading 32 64 bit Processors Easy to Use Full Source Code Royalty Free Real Time Embedded Multithreading p ND express Copyright 2007 Express Logic Inc ThreadX is a registered trademark of Express Logic Inc All other trademarks are the property of their respective owners Unlock your future Enter the New Era of Configurable Embedded Processing Adapt to changing algorithms protocols and interfaces by creating your next em
44. ost sensitive powerful applications with Keil Development Tools C C Development Kit The RealView Microcontroller Development Kit MDK is the complete software development environment for ARM7 9 and Cortex MI M3 MDK is easy to learn and use yet powerful enough for the most demanding embedded ARM application The integrated Device Database simplifies tool configuration and includes more than 250 ARM Powered Microcontroller variants for your embedded project RealView Microcontroller Development Kit rase d Device Database 1DE f Vision Debugger amp Analysis Tools Complete Device Simulation JTAG Debugger ULINK2 connects to the JTAG or 2 wire debug interface and supports on the fly debugging and Flash programming RealView Real Time Library RTX RTOS Source Code TCPnet Networking Suite RTOS and Middleware The RealView Real Time Library RL ARM solves the real time and communication challenges of your ARM project and expands MDK with essential components for sophisticated communication and interface peripherals Learn more about RealView MDK RL ARM and ULINK2 Download a free om demo call 1 800 348 8051 evaluation version from www k Microcontroller Development Tools Cx51 Keil Cx51 is the de facto industry standard for all classic and extended 8051 device variants CSI Version 8 5 includes the latest devices such as XCB00
45. performance boost you re looking for but the software is certainly more complicated Ils symmetric multiprocessin or the past thirty years computing has enjoyed con tinual boosts in performance primarily due to in creases in clock speed pipelining efficiency and cache size Recently however traditional micro processor optimization has hit the proverbial wall Although tweaks such as further cache size increases can continue to nudge system performance it s clear that Moore s gains are be hind us Meanwhile embedded systems continue to grow in soft ware complexity with consumers expecting that all the bells and whistles will continue to come in ever shrinking cost size weight and power footprints Microprocessor designers have concluded that the best path to ward meeting the growing demand for performance with con trolled footprint is to employ multicore architectures in which the main premise is to partition the software and parallelize or offload execution across multiple processing elements Symmetric multipro cessing SMP is one such architecture consisting of homogenous cores that are tightly coupled with a common memory subsystem as shown in Figure 1 SMP is a de facto standard on the desktop but adoption in embedded applications has been slow with recent sur veys showing only a small percentage of designs using single chip SMP capable devices So if your design is in need of some extra horsepower
46. rate programming file Step one called translate involves verifying that the synthesized netlist is consistent with the selected FPGA ar chitecture and there are no inconsis The final step is to generate the programming file which can be stored in flash memory PROMs or directly programming into the FPGA 0 tencies in the constraint file Inconsis tencies would consist of assigning two different signals to the same pin as signing a pin to a power or ground pin or trying to assign a non existing design signal to a pin If the design fails either check the translate step will fail and the implementation process will be stopped Translate errors must be corrected and the translation step must be error free before advancing to step two which is the fit stage This step involves taking the constraints file and netlist and distributing the design logic in the selected FPGA If the design is too large or requires more resources or available logic than the selected device offers the fitter will fail and halt the implementation process To correct this type of error replace the current FPGA with a larger one and re synthe size and repeat PAR for the design A successful fit stage is necessary to pro ceed to generate the programming file stage All timing information is available and many PAR tools will provide the required files necessary for the simula tor to perform a timing simulation The final step is to genera
47. rs on basic techniques and options re og ime in human terms and even longer in the microprocessor indus try Here s a look at what s transpired departments E NEN Acquisitions to enhance Is symmetric CS mu tiprocessing BY RICHARD NASS for you Acquisitions will bring more BY DAVID N KLEIDERMACHER tear downs and insight into Multicore architectures can provide semiconductors the performance boost you re looking eae for but the software is certainly more parity bit 7 complicated advertising index 43 marketplace 47 In person Debugging embedded C ESC Silicon Valley BY ROBIN KNOKE San Jose Convention Center Has debugging embedded C changed in 20 years You betcha April 14 18 2008 But the process will never change stabilize isolate correct and AE EN retest Here s an article from the 1988 premiere issue of Embedded Systems Programming with some comments from the ondine author Robin Knoke www embedded com 34 wenns Article submissions www embedded com wriguide Forum discussions www embedded com forum ea M sora he M TA DUM D suppose hein etna tion spe nea pa ema pu eue TU Wf Ello c uH pup i i tr Ss puc BY Richard Nass Acquisitions to enhance coverage mbedded systems designers can now gain from the experi ence of their peers thanks to an abundance of Tear Downs CMP the company that owns this magazine Embedded com a
48. rty cover feature 24 simulation tools can perform gate sim ulation Ideally each level of simulation is performed at the appropriate develop ment stage However if this isn t possi ble it s recommended that at a mini mum RTL is performed As this simulation is performed it s normal for the original design to require mod ifications due to logic errors Each simulation level offers various bene fits RTL uncovers logic errors the functional level verifies that the pre and post synthesis designs are equiva lent and the gate level uncovers timing errors Some benefits to spend ing sufficient time generat ing quality testbenches simulation are reduced time troubleshooting hardware generally cheaper to test bench troubleshoot than hardware troubleshoot and a decrease in the chance of damaging hardware resulting in a faster time to market Opting to omit simulation and testbenching will gen erally cost the project additional time and money Lab testing requires col lecting and setting up test equipment such as a logic analyzer and oscillo scope and depending on the equip ment used the designer may have a limited number of signals available Or the desired signal must be made available on an output which requires additional time Simulation is valuable and as a guideline at least 2X the number of hours spent writing the code should be spent developing and testing th
49. s with a powerful debug agent that com municates with the debugger provid ing the ability to debug any combina tion of user threads on any core The user can set specialized breakpoints that enable user defined groups of threads to be halted when another thread hits the breakpoint Some class es of bugs require this fine grained lev el of control JANUARY 2008 embedded systems design www embedded com ure of the technology which en ables higher data throughput with a lower pin count HSST has been proposed to the Nexus standards committee In ad dition ARM has adopted HSST as part of its CoreSight trace solution SMP is a promising technology for improved performance in an attractive cost and power footprint However SMP is not a panacea The application must have the potential for cy and designers may need to manual ly refactor software to unlock this con currency Furthermore SMP systems are more difficult to manage and de bug than unicore designs This in turn may require switching operating sys tems and tooling to acquire the load balancing and multicore debugging capabilities that go hand in hand with SMP David Kleidermacher is chief technology officer at Green Hills Software where he has been designing compilers software development environments and real time operating systems for the past 16 years David frequently publishes articles in trade journals and presents paper
50. s at conferences on topics relating to embed ded systems He holds a BS in computer science from Cornell University and can be reached at davek ghs com bedded CONFERENCE 1 SILICON VALLEY LEARN TODAY DESIGN TOMORROW Conference April 14 18 2008 Expo April 15 17 2008 McEnery Convention Center San Jose CA Embedded Systems Conference Silicon Valley EMBEp delivers a comprehensive technical program 8 008 focusing 15 critical topics that affect your designs 4585 is MESS Learn how to solve your engineering issues today register today at www embedded com esc sv
51. s design www embedded com From the running program s perspective an object with static storage duration is always there Typical C and C programs allocate automatic storage on a run time stack often the same stack that they use for storing function call return addresses Allo cating storage for a local object isn t free but it s usually dirt cheap just one machine instruction For example in int foo int v t int m return m e function foo has a single local object m The compiler deter mines n s size from its type typically 2 or 4 bytes When it com piles foo the compil er simply generates an instruction such as storage sub sp 4 as one of the first instructions in the function body to carve room for an int on the stack This example as sumes that an int object occupies 4 bytes and that the stack grows downward from higher addresses to lower addresses Allocating automatic storage for several local objects costs more stack space but no more run time than allo cating storage for just one For example in int foo int v t int m double d return m n the function has two local objects m and d In this case when it compiles the function the compiler determines the size of m still 4 and the size of d say 8 Rather than generate a separate instruction to allocate storage for each object the compiler simply adds up the sizes and uses the sum in a single instruction such
52. services technical training and consult ing company She is also a senior sys tems engineer with responsi for performing failure mode effect and criti cality analysis requirements analysis and definition creating physical and functional block diagrams and evaluat ing design tool needs She has a BS in electrical engineering magna cum laude from North Carolina A amp T State University and an MS with honors in systems engineering from Johns Hop kins University Smith can be reached at Gina_R_Smith BrownSmithRDL com DUEL WIMP This time you are energy depleted history No Not again When will the boss of The Waste Land learn that he can t win My heavy duty Zap HIM hard energy rifle feeds on 850 rounds a second It will blast your blue suit to cinders with zillions 4 of Watts 7 will show you fear in a handful of dust Have a taste of LOW POWER energy Even the smallest of batteries are powerful when you know how to make the most Learn how to combine the AVR microcontrollers high performance with the lowest possible power consumption on www atmel com avrman 2008 Atmel Corporation Al rights reserved Atm AVR and loo are registerad trademarks and picoPower is a trademark of Atmel Corporation or e subsi slaves Other terme and product namas may be radrmarks of thers Al Characters this document coated by Myke Fantasi Fabrikken AS 2008 Multicore architectures can provide the
53. t adapters USB to serial adapters USB modems incl WF USB audio devices USBpiners USB serial device USB keyboard amp mouse Ethernet aver USB RNDIS o Windows drivers Portable Standalone Host Device OTG USB Controllers Supported ARM ColdFire NXP Full Source Code Na RTOS INNOVATORS 800 366 2491 sales smxrtos com www smxrtos com usb www embedded com embedded systems design JANUARY 2008 31 specific cores to specific cores Thus real time performance can be accom modated while other software is opti mized across the multiple cores as deemed appropriate by the RTOS The bottom line real time systems can take advantage of SMP but designers should be prepared to spend time tweaking the system s scheduling parameters NUMA FOR EMBEDDED SMP s single memory bus architecture may be a poor fit for memory and I O bound applications relative to compute intensive systems The only way to be sure of the payoff single on chip debug port such as JTAG that enables a host debugger connected with a hardware probe de vice to debug multiple cores simulta neously With this capability developers can perform low level synchronized run control of the multiple cores Board bring up and device driver develop ment are two common uses of this type of solution The development tool lets develop ers visualize all the system s cores and choose any combination to debug each
54. te the pro gramming file which can be stored in flash memory PROMS or directly programming into the FPGA JTAG and third party programmers like JANUARY 2008 embedded systems design www embedded com Data are two programming meth ods used to store the programming file in memory The appropriate format depends on the FPGA vendor the pro gramming method and the device used to hold the programming There are various output formats consult your documentation for the correct one In addition to the imple mentation process creating the pro gramming file there are several output report files created such as a pad file The pad file contains in formation such as sig nal pin assignment part number and part speed BEYOND THE BASICS This article gives some basic examples of the FPGA development process so a new embedded systems designer man ager technical lead from other disci plines or someone wanting to diversi fy his or her skills can understand what it takes to develop and imple ment a digital design in a FPGA The generic process provided here will vary depending on the FPGA tools since each vendor may perform some of these tasks in a slight different manner A good resource for furthering your knowledge is Essential VHDL RTL Synthesis Done Right Sundar Ra jan RE Compton Co 1998 NI Gina R Smith is CEO and owner of Brown Smith Research and Develop ment Laboratory Inc an engineering
55. tion Language AHDL which is only recognizable by Altera s design tool set There are two writing styles for HDL designs structural or behavioral Structural firmware is the software equivalent of a schematic capture de sign Like schematic capture structural designs instantiates or uses vendor specific components to construct the desired digital functions This type of HLD firmware is vendor dependent like its graphical counterpart and has the same disadvantages Like schemat ic capture designs repeating the de sign process is necessary for different vendors Behavioral HDL firmware describes digital functions in generic or abstract terms that are generally vendor inde pendent This provides enough flexi bility for code reuse in different ven dor s FPGAs so little or no code modification is required Advantages of behavioral designs are its flexibility and time and cost savings and it of fers little to no vendor dependence For designs that require vendor specif ic resources such as RAM only those components must change for different vendors VHDL and Verilog are the most popular HDL languages VHDL files consist of three main parts library dec laration entity declaration and archi tecture section While not required by VHDL an optional heading section should be included This section should contain pertinent information such as the designer s name filename a brief summary of the code and a re
56. tion first get there yet ENDNOTES Saks Dan A New Appreciation for Data Types Embedded Systems Programming May 2001 p 59 aks Dan Cast with caution Embedded Systems Design J 2006 p 1 pe regions in C and G Embedded System Design November 2007 p 15 www embedded com embedded systems design JANUARY 2008 13 cover feature The art of FPGA construction R SMITH Working with FPGAs isn t intimidating ver the last several years the use of FPGAs has h greatly increased in military and commercial when you products They can be found in primary and sec know the basic ondary surveillance radar satellite communica techniques and tion automotive manufacturing and many other 5 types of products While the FPGA development process is second Options nature to embedded systems designers experienced in implement ing digital designs on an FPGA it can be confusing and difficult 2 for the rest of us Good communication is important when techni i cal leads supervisors managers or systems engineers interface i with FPGA designers The key to good communication is having an understanding of the development process A solid understanding will help you comprehend and extract relevant information for status reports define schedule tasks and allocate appropriate resources and time There have been many times when my FPGA knowledge has al lowed m
57. torage duration and di determines whether declara linkage Not every name has all with sco rmi tions in different scopes can re of these attributes For exam storage duration fer to the same object or func ple a function name has a sonond serios tion It s easy to confuse these type a scope and a linkage concepts because they re so in but no storage duration A scope storage allocation tertwined statement label name has only and linkage Much of the confusion stems from the complex se mantics of storage class speci fiers keywords such as extern and static For exam ple the precise meaning of static depends on the scope in which it appears Sometimes declaring an object static affects the object s storage duration It can also affect the object s linkage Understanding these distinc tions can help you program more effectively This month explain the syntax of storage class specifiers and the concept of storage duration in C and C I ll also show you how they re related to the con cept of scope STORAGE CLASS SPECIFIERS Storage class specifiers are keywords you can use in decla www embedded com embedded systems design JANUARY 2008 SCOPE REGIONS II C and C each suppor scope regions Although dards use different na different verbiage to two languages support regions a name has declared in the o namespace d cols refers to the C as global na global scope
58. uch as tabs and spaces to provide read ability of code Include a header section for each file or module Suggestive header information designer s name file description and re vision or history record VHDL SYNTAX RULES Now for some VHDL specifics includ ing data types Std logic can have values of high 1 low 0 unknown X unini tialized U high impedance Z weak unknown W weak 0 L weak 1 and don t care to represent a sin gle data bit Std logic vector can have the same values as std logic howev er it represents multiple bits Abit can only have a value of high 1 or low 0 and it represents one data bit Boolean represents true or false Comments are denoted by double dash marks Comments continue after until a carriage return Each statement ends with a semi colon VHDL is not case sensitive No specific format is required Reserved words aren t valid signal names Signal names must start with a let ter numbers are not acceptable Library declaration The library declaration is the first sec tion in the source file This is where you place the library and package call out statements Libraries and packages define and store components define signal types functions procedures and so forth Packages and libraries are When a designer has specific constants formulas processes and procedures that are used by multiple modules or submod ules
59. ut the invention of the transistor It seems that one day Bill Shockley was sitting in his office read ing a magazine when a technician ran in to his office screaming Mr Shock Remembering transistor history NN ley Mr Shockley I connected p mate rial to n material to p material inject ed some current and I am getting am plification Shockley looked over the top of his magazine and said Con gratulations You just discovered the Shockley Effect Ed Wozniak Congratulations You jt In 1968 I was a sophomore engineer ing physics major at the University of Illinois Bardeen was teaching E amp M Articulate lucid and very friendly he put the material at the right level and pulled us along through a course that was universally dreaded Acade mia could use a few thousand more professors with his ability to teach and engage young minds David Barr It s not all about Linux The statement that an estimated 70 lof new semiconductor devices are Lin lux enabled seems quite impossible Hadi Nahari and Jim Ready a secure flavor of Linux October 2007 p 20 A lot of LED and diodes are being made even today Even if semiconductor devices is changed to read microprocessor it seems very unlikely to be true given the quanti ties of low end controllers shipped in small gadgets Can you point to any justification for this statement Craig Cherry
60. vantage of SMP to im prove performance without significant application modifications LANGUAGE LEVEL CONCURRENCY Because threads are an integral part of the Java and Ada languages designing multithreaded software in these lan guages is relatively natural Java and Ada programs using language level threading can map nicely to SMP Yet C and C remain the most popular lan guages for embedded systems Surveys in recent years have shown C and C which lack native thread support ac counting for about 80 of embedded software with no significant downward trend If your software base is hopelessly dependent on a real time operating sys tem RTOS that doesn t support SMP then SMP may not be for you If you have the freedom to select a new oper ating system your best bet at future portability is to select one that supports both POSIX and SMP An SMP operat ing system will simply schedule concur rent threads to run on the extra cores in the system This automatic load balanc ing is the primary advantage of SMP adding cores will increase performance often dramatically without requiring software modifications There s one important exception to the automatic reusability of multi threaded applications on an SMP sys tem Most SMP operating systems will allow threads at varying priority levels to execute concurrently on the multiple cores Most real time embedded soft ware is written for a strictly priority based pre
61. within their design he or she can a custom package create standardized such as the IEEE library and defined by a user designer or vendor The IEEE library offers several packages such as standard textio and std_logic_1164 Each of these packages defines various types attributes proce dures fles and so on Here s an abbre viated list of selected IEEE packages standard defines types such as boolean bit time and integer subtypes such as natural and pos itive and the attribute foreign textio package defines types such as line and text files such as in put and output and procedures such as read readline write and writeline Std logic 1164 package defines types such as std ulogic and std ulogic vector and functions such as nand and or nor The work library serves as a place to add or delete designs Designs stored in the work library get analyzed during synthesis and simulation Vari ous tools handle libraries in different www embedded com embedded systems design JANUARY 2008 ways Therefore users should consult the tool s documentation for correct use To use what s in a library or pack age the library must be made visible by using the keywords Library and Use clause The IEEE std logic 1164 package contains the types used in Listing 1 Therefore the LIBRARY IEEE statement makes it visible and USE IEEE std logic 1164 a11 tells the tools

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