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1. 5 31 Reference 6 3 Exception Vector 4 6 7 Exception lt dip Eois sies 6 9 cte este ine erede 6 11 Effective Address Calculation 7 2 Move Byte Instruction Execution 7 2 Move Word Instruction Execution 7 3 Move Long Instruction Execution 7 3 Standard Instruction Execution 7 4 Immediate Instruction Execution 7 5 Single Operand Instruction Execution 7 6 Shift Rotate Instruction Execution 7 6 Bit Manipulation Instruction Execution Times 7 7 Conditional Instruction Execution 7 7 JMP JSR LEA PEA and MOVEM Instruction Execution Times 7 8 Multiprecision Instruction Execution 7 9 Miscellaneous Instruction Execution Times 7 10 Move Peripheral Instruction Execution Times esses 7 10 Exception Processing Instruction Execution Times 7 11 Effective Address Calculation
2. 9 3 Move Byte and Word Instruction Loop Mode Execution Times 9 3 Move Long Instruction Execution 2 20 222 9 4 Move Long Instruction Loop Mode Execution Times 9 4 Standard Instruction Execution 9 5 Standard Instruction Loop Mode Execution Times 9 5 Immediate Instruction Execution 9 6 Single Operand Instruction Execution 9 7 Clear Instruction Execution 9 7 Single Operand Instruction Loop Mode Execution Times 9 8 Shift Rotate Instruction Execution 9 8 Shift Rotate Instruction Loop Mode Execution Times 9 9 Bit Manipulation Instruction Execution Times 9 9 Conditional Instruction Execution Times sese 9 10 JMP JSR LEA PEA and MOVEM Instruction Execution Times 9 10 Multiprecision Instruction Execution 9 11 Miscellaneous Instruction Execution 9 12 Exception Processing Instruction Execution Times 9 13 Power Dissipation an
3. oe Eon te oo ones 5 2 Byte Read Cycle irruit Eo as aae heute deed 5 2 Read and Write Cycle Timing 5 3 Word and Byte Read Cycle Timing Diagram 5 3 Word Write Cycle 5 5 Byte Write Cycle 5 5 Word and Byte Write Cycle Timing Diagram 5 6 Read Modify Write Cycle Flowchart 5 7 Read Modify Write Cycle Timing 5 8 CPU Space Address Encoding irte pito Qo Sire dre rehus 5 9 Interrupt Acknowledge Cycle Timing Diagram 5 10 Breakpoint Acknowledge Cycle Timing Diagram 5 11 3 Wire Bus Arbitration Flowchart NA to 48 Pin MC68008 and 68 00 5 12 2 Wire Bus Arbitration Cycle 5 13 M68000 USER S MANUAL MOTOROLA LIST OF ILLUSTRATIONS Continued Figure Number Title 5 15 3 Wire Bus Arbitration Timing Diagram NA to 48 Pin MC68008 and 6 5 16 2 Bus Arbitration Timing 5 17 External Asynchronous Signal Synchronization
4. M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL L SUFFIX 746 03 P D em G k PE 1 gt NOTES MILLIMETERS INCHES 1 DIMENSION A 15 DATUM DIM MIN MAX MIN 2 POSTIONAL TOLERANCE FOR LEADS A 60 36 61 56 2 376 2 424 910 025 0 010 fT AM 14 64 15 34 0 576 0 604 3 IS SEATING PLANE 3 05 4 32 0 120 0 160 4 DIMENSION L TO CENTER OF LEADS D 1381 10533100151 0 021 WHEN FORMED PARALLEL 1 762 11397 003010055 5 DIMENSIONING AND TOLERANCING PER gt 2 54 5 0 100 BSC ANSI Y14 5m 1982 J 0 204 0 330 0 008 0 013 12 4 419 0 100 0 165 L 1524BSC 0 600 BSC M 0 10 0 10 N 1 016 1 524 0 040 0 060 Figure 11 7 Case 740 03 L Suffix 11 8 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA P SUFFIX 767 02 NOTES MILLIMETERS _ INCHES 1 R IS END OF PACKAGE DATUM PLANE DIM MIN MAX T 15 BOTH A DATUM AND SEATING PLANE A_ 61 34 62 10 2 415 2 445 2 POSITIONAL TOLERANCE FOR LEADS 1 AND 13 72 1422 0 540 0 560 48 394 5 08 0 155 0 200 0 51 0 020 D 0 36 0
5. drain 3 10 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL Yes MOTOROLA SECTION 4 8 BUS OPERATION The following paragraphs describe control signal and bus operation for 8 bit operation during data transfer operations bus arbitration bus error and halt conditions and reset operation The 8 bit bus operations devices are the MC68008 MC68HC001 in 8 bit mode and 68 000 8 bit mode The MC68HC001 and MC68ECO00 select 8 bit mode by grounding mode during reset 4 1 DATA TRANSFER OPERATIONS Transfer of data between devices involves the following signals 1 Address bus AO through highest numbered address line 2 Data bus DO through D7 3 Control signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure In all cases the bus master must deskew all signals it issues at both the start and end of a bus cycle In addition the bus master must deskew the acknowledge and data signals from the slave device For the MC68HCO001 and 68 000 UDS is held negated and D15 D8 are undefined in 8 bit mode The following paragraphs describe the read write read modify write and CPU space cycles The indivisible read modify write cycle implements interlocked multiprocessor communications A CPU space cycle is a special processor cycle 4 1 1 Read Cycle During a read cycle the processor receives one byte of data from
6. Power Supply ute Signal SUMMARY ERE RE E M68000 USER S MANUAL Page Number vii TABLE OF CONTENTS Continued Paragraph Page Number Title Number Section 4 8 Bit Bus Operations 4 1 Data SC ro pn ep poe epee 4 1 4 1 1 Read Operations RTT Em 4 1 4 1 2 ks etcetera 4 3 4 1 3 Read Modify Write 4 5 4 2 Other BUS Operations M d ue 4 8 Section 5 16 Bit Bus Operations 5 1 Data Transfer 5 1 5 1 1 Head Operations itia ceti ct ads 5 1 5 1 2 Write Cycle c cC 5 4 5 1 3 Read Modify Write 5 7 5 1 4 GPU CV Cle sa tuque meses 5 9 5 2 Bis 4 118 te 5 11 5 2 1 Requesting The BUS 5 14 5 2 2 Receiving The Bus Grant 5 15 5 2 3 Acknowledgment of Mastership 3 Wire Arbitration 5 15 5 3 Bus Arbitration Control 5 15 5 4 Bus Error and Halt Operation sese 5 23 5 4 1 Bus Error ODOrallOrt v depo o sh 5 24 5 4 2 Retrying The Bus Cycle peperere oet ee ERR evans 5 26 5 4 3 Halt Operation NEP 5 27 5 4 4 Double Bus Faull
7. 8 2 Move Byte Instruction Execution 8 2 Move Word Instruction Execution eese 8 3 Move Long Instruction Execution 8 3 MOTOROLA M68000 USER S MANUAL XV Table Number 8 5 8 7 8 8 8 10 8 11 8 12 8 13 8 14 8 15 9 1 9 2 9 4 9 5 9 7 9 8 9 9 9 10 9 11 9 12 9 13 9 14 9 15 9 16 9 17 9 18 9 19 10 1 10 2 LIST OF TABLES Concluded Page Title Number Standard Instruction Execution 8 4 Immediate Instruction Execution 8 5 Single Operand Instruction Execution 8 6 Shift Rotate Instruction Execution 8 6 Bit Manipulation Instruction Execution sess 8 7 Conditional Instruction Execution Times cirea trinh n rra he ect e egens 8 7 JMP JSR LEA PEA MOVEM Instruction Execution Times 8 8 Multiprecision Instruction Execution 8 9 Miscellaneous Instruction Execution Times 8 10 Move Peripheral Instruction Execution 8 10 Exception Processing Instruction Execution Times 8 11 Effective Address Calculation 9 2 Move Byte and Word Instruction Execution Times
8. prine ay 11 Gase J65A 0b5 RO eus 11 12 Gase 778 02 BEN SUX s uoto VR DU 11 13 Case 779 02 FN Suffix rere been n cepere ees ele ele 11 14 Case EG SUITE p ec ean 11 15 Case 840 01 SUTIX deir Pour e ette bets orient te 11 16 DBcc Loop Mode Program A 1 M6800 Data Transfer RE iE eco B 1 Example External Circuit esee B 2 External VMA TIMING taa dae B 2 M6800 Peripheral Timing Best B 3 M6800 Peripheral Timing Worst B 3 Autovector Operation Timing B 5 M68000 USER S MANUAL MOTOROLA Table Number 2 1 3 4 LIST OF TABLES Page Title Number Data Addressing Modes s 2 4 Instruction Set Summary 2 11 Data Strobe Control or Data 3 5 Data Strobe Control of Data Bus 68008 3 5 Ret 3 9 3 10 DTACK BERR and HALT Assertion Results
9. esses 10 8 M68000 USER S MANUAL MOTOROLA Paragraph Number 10 9 10 10 10 11 10 12 10 13 10 14 10 15 B 1 B 2 MOTOROLA TABLE OF CONTENTS Continued Title Section 10 Electrical and Thermal Characteristics MC68008 AC Electrical Specifications Clock Timing AC Electrical Specifications Read and Write Cycles AC Electrical Specifications MC68000 To M6800 AC Electrical Specifications Bus Arbitration 68 00 DC Electrical Spec 68 000 AC Electrical Specifications Read and Write 68 000 AC Electrical Specifications Bus Arbitration Section 11 Ordering Information and Mechanical Data Pin S be mti Neu Package DIMENSIONS dic dono Dd dr Appendix A MC68010 Loop Mode Operation Appendix B M6800 Peripheral Interface Data Transfer 0 40 Interrupt Interface 68000 USER S MANUAL Figure Number 2 1 2 3 2 4 2 5 2 7 3 1 3 3 3 4 4 1 4 2 4 4 4 5 4 6 5 1 5 2 5 3 5 5 5 6 5 8 5 9 5 10 5 11 5 12 5 13 Xii LIST OF ILLUSTRATIONS Page Tit
10. a o E E E 2100 En gt s 6 5 2102 5 un ak NIJ A ap 5 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 11 16 67 MHz 12F n Asynchronous Input Setup BERR Asserted to DTACK 2 3 5 DTACK Asserted to BERR Asserted MC68010 Only AS DS Negated to E Low E Width High E Width Low Data Out Hold from Clock gt o Characteristic N ojo R W Asserted to Data Bus Impedance Change I gt 3 gt A HALT RESET Pulse Width BGACK Negated to AS DS 1 5 R W Driven 57 BGACK Negated to Driven BR Negated to AS DS R W Driven BR Negated to FC 5 Driven These specifications represent improvement over previously published specifications for the 8 10 and 12 5 MHz MC68000 and are valid only for product bearing date codes of 8827 and later This frequency applies only to 68 000 and MC68HCO001 NOTES 1 For a loading capacitance of less than
11. B EO ERA x se vas 6 3 5 Instruction Traps PNE 6 3 6 Illegal and Unimplemented Instructions 6 3 7 Privilege VIOlalloriS ui etes beret atas 6 3 8 6 3 9 BUS EONS usce o b E da icd Us 6 3 9 1 ES EO AC EUR D RM DV 6 3 9 2 ipd eto eite 6 3 10 Address 6 4 Return From Exception 68010 Section 7 8 Bit Instruction Timing 7 1 Operand Effective Address Calculation Times 7 2 Move Instruction Execution Times 73 Standard Instruction Execution 7 4 Immediate Instruction Execution Times 7 5 Single Operand Instruction Execution Times 7 6 Shift Rotate Instruction Execution Times 7 7 Bit Manipulation Instruction Execution Times 7 8 Conditional Instruction Execution Times 7 9 JMP JSR LEA PEA and MOVEM Instruction Execution Times 7 10 Multiprecision Instruction Execution 7 11 Miscellaneous In
12. E pe 5 28 55 Reset ODSrallofke audet Ferree 5 29 5 6 The Relationship of BERR and HALT 5 30 5 7 Asynchronous Operation 2 11 5 32 5 8 synchronous Operaatio exc extera ges 5 35 6 Exception Processing 6 1 Privilege MOOGS eed 6 1 6 1 1 Supervisor MOUB us e dO e 6 2 6 1 2 eaten uc E 6 2 6 1 3 Privilege Mode Changes 6 2 6 1 4 Reference 6 3 6 2 Exception Processihg 2 2 2 6 4 6 2 1 Exception mM 6 4 6 2 2 Kinds Of EXCSDIIOfIS HM acu pret s 6 5 6 2 3 s ele er ED LED P ERR Me NIS 6 8 viii M68000 USER S MANUAL MOTOROLA TABLE OF CONTENTS Continued Paragraph Number Title Section 6 Exception Processing 6 2 4 Exception Stack Fratres Sp 6 2 5 Exception Processing Sequence 6 3 Processing of Specific Exceptions 6 3 1 oda eoa act dos tdeo par dr LT UNE 6 3 2 6 3 3 Uninitialized Interrupt oic o n Po e we o oct teh eie eee 6 3 4 Spurious Inter
13. ter ra RE eis eie da 5 37 seed dante te 6 1 Exception Vector aio xoci 6 2 Peripheral Vector Number 6 3 Address Translated from 8 Bit Vector Number 6 4 Exception Vector Address Calculation 68010 6 5 Group 1 and 2 Exception Stack Frame 6 6 MC68010 Stack Frame 6 7 Supervisor Stack Order for Bus or Address Error Exception 6 8 Exception Stack Order Bus and Address Error 6 9 Special Status Word Format repe peres au 10 1 68000 Power Dissipation vs Ambient Temperature TA 10 2 Drive Levels and Test Points for AC Specifications 10 3 Clock Input Timing Diagram ir eco od 10 4 Read Cycle Timing 10 5 Write Cycle Timing rite beo o meret 10 6 MC68000 to M6800 Peripheral Timing Diagram Best Case MOTOROLA M68000 USER S MANUAL xiii Figure Number 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 14 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 1
14. SP 4 gt SP RTD lt displacement gt 0 Destination gt Destination P MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 13 Table 2 2 Instruction Set Summary Sheet 4 of 4 If supervisor state then SP 2 SR SP 2 2 SP SP 2 SP 4 restore state and deallocate stack according to SP else TRAP RTR SP 2 CCR SP 2 SP RTR SP SP 4 SP SP gt SP 4 SP RTS Destination 9 Source 9 X Destination SBCD Dx Dy SBCD If condition true Scc lt ea gt then 1s Destination else 0s Destination If supervisor state STOP data then Immediate Data SR STOP else TRAP SUB Destination Source Destination SUB lt ea gt Dn SUB Dn ea SUBA Destination Source Destination SUBA ea An Destination Immediate Data Destination SUBI lt data gt lt ea gt SUBQ Destination Immediate Data Destination SUBQ lt data gt lt ea gt SUBX Destination Source X Destination SUBX Dx Dy SUBX Ax Ay SWAP Register 31 16 lt Register 15 0 SWAP Dn TAS Destination Tested Condition Codes 1 bit 7 of TAS ea Destination SSP 2 2 SSP Format Offset SSP SSP 4 gt SSP PC 5 SSP SSP 2 5 SSP SR gt SSP Vector Address gt TRAPV then TRAP TRAPV UNLK SP SP SP 4 gt SP UNLK An N
15. gt If Dn z 1 then 2 MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 11 Table 2 2 Instruction Set Summary Sheet 2 of 4 Immediate Data Destination gt Destination EORI to SR If supervisor state EORI lt data gt SR then Source SR SR else TRAP EXT Destination Sign Extended gt Destination EXT W Dn extend byte to word EXT L Dn extend word to long word ILLEGAL 55 2 gt SSP Vector Offset SSP ILLEGAL SSP 4 2 SSP PC SSP SSP 2 2 SSP SR SSP Illegal Instruction Vector Address JSR SP 4 gt SP PC SP JSR lt ea gt Destination Address gt LINK SP 4 gt SP An SP LINK An lt displacement gt SP gt SP d gt SP LSLLSR Destination Shifted by count Destination 1541 LSd lt data gt Dy 1891 ea MOVE Source Destination MOVE lt ea gt lt ea gt MOVEA Source Destination MOVEA lt ea gt An MOVE from CCR Destination MOVE CCR lt ea gt CCR MOVE to Source MOVE lt ea gt CCR CCR MOVE from SR gt Destination MOVE SR lt ea gt SR If supervisor state then SR gt Destination else TRAP MC68010 only MOVE to SR If supervisor state MOVE lt ea gt SR then Source SR else TRAP 2 12 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA Table 2 2 Instruction Set Summary Sheet 3 of 4 MOVE USP If supervisor state MOVE USP An then
16. 013 014 015 GND GND A23 A22 21 MC68000 MC68HC000 M C 68010 WC A20 A19 A18 A17 A16 A15 14 1 8 MC68EC000 Figure 11 3 68 Lead Quad Pack 1 of 2 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA MC68HC001 IPLO 0 6 5999544 59 9355 lt lt Figure 11 3 68 Lead Quad Pack 2 of 2 9 229019222 0 1 BERR VPA RESET MC 68008 HALT GND CLK BR BG DTACK Figure 11 4 52 Lead Quad Pack MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 11 5 1 A2 M 2 Al A5 3 A0 A6 4 FCO A7 5 FC1 A8 6 FC2 9 7 IPL2 IPLO A10 8 iP All 9 BERR A12 13 M4 1 MC68008 RESET Vcc HALT A15 GND GND CLK A16 BR 17 BG 18 DTACK 19 R W D7 DS D6 AS 05 00 04 01 03 02 Figure 11 5 48 Pin Dual In Line M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 68 000 Figure 11 6 64 Quad Flat Pack 11 2 PACKAGE DIMENSIONS v mems CS moros
17. MOTOROLA 68000 8 16 32 Bit Microprocessors User s Manual Ninth Edition Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any
18. START NEXT CYCLE Figure 4 5 Read Modify Write Cycle Flowchart M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL INPUT THE DATA TERMINATE THE CYCLE INPUT THE DATA TERMINATE THE CYCLE MOTOROLA 50 S1 52 53 54 55 56 57 58 59 510 511 512 513 514 515 516 517 518 519 CLK AS DSDREUS y lt INDIVISIBLE CYCLE gt Figure 4 6 Read Modify Write Cycle Timing Diagram The descriptions of the read modify write cycle states are as follows STATE read cycle starts in 50 The processor places valid function codes 2 and drives R W high to identify a read cycle STATE 1 Entering S1 the processor drives a valid address on the address bus STATE2 Onthe rising edge of S2 the processor asserts AS and LDS or DS STATE 3 During S3 no bus signals are altered STATE 4 During S4 the processor waits for a cycle termination signal DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S4 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the end of S4 the processor inserts wait states full clock cycles until either DTACK or BERR is asserted STATE 5 During S5 no bus signals are altered STATE 6 During S6 data from the device are driven onto the data bus STATE 7 the falling edge of the clock entering S7 the processor accepts data from
19. lt An N Predecrement Register Indirect An 4 EA An An Register Indirect with Offset EA An d16 d46 An Indexed Register Indirect with Offset EA An Xn dg dg An Xn Immediate Data Addressing Immediate DATA Next Word s lt data gt Quick Immediate Inherent Data Implied Addressing Implied Register EA SR USP SSP PC SR USP SSP PC VBR SFC DFC VBR SFC DFC NOTES 1 The VBR SFC and DFC apply to the MC68010 only EA Effective Address Dn Data Register An Address Register Contents of PC Program Counter dg 8 Offset Displacement dig 16 Offset Displacement N 1 for byte 2 for word and 4 for long word If An is the stack pointer and the operand size is byte N 2 to keep the stack pointer on a word boundary Replaces Xn Address or Data Register used as Index Register SR Status Register USP User Stack Pointer SSP Supervisor Stack Pointer Program Counter VBR Vector Base Register 2 3 DATA ORGANIZATION IN REGISTERS The eight data registers support data operands of 1 8 16 or 32 bits The seven address registers and the active stack pointer support address operands of 32 bits 2 3 1 Data Registers Each data register is 32 bits wide Byte operands occupy the low order 8 bits word operands the low order 16 bits and long word operands the entire 32 bits The least significant bit is addressed as bit zero the most significant bit
20. The number of bus read and write cycles for each instruction is also included with the timing data This data is shown as n r w where n is the total number of clock periods r is the number of read cycles is the number of write cycles For example a timing number shown as 18 3 1 means that 18 clock periods are required to execute the instruction Of the 18 clock periods 12 are used for the three read cycles four periods per cycle Four additional clock periods are used for the single write cycle for a total of 16 clock periods The bus is idle for two clock periods during which the processor completes the internal operations required for the instruction NOTE The total number of clock periods n includes instruction fetch and all applicable operand fetches and stores 7 1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES Table 7 1 lists the numbers of clock periods required to compute the effective addresses for instructions The totals include fetching any extension words computing the address and fetching the memory operand The total number of clock periods the number of read cycles and the number of write cycles zero for all effective address calculations are shown in the previously described format MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 7 1 Table 7 1 Effective Address Calculation Times Addressing Mode Log Register Data Register Direct 0 0 0 Uo 0 0 0 Address Registe
21. 000 68 001 68 000 and MC68008 group 1 and 2 exception stack frame is shown in Figure 6 5 Only the program counter and status register are saved The program counter points to the next instruction to be executed after exception processing The MC68010 exception stack frame is shown in Figure 5 6 The number of words actually stacked depends on the exception type Group 0 exceptions except reset stack 29 words and group 1 and 2 exceptions stack four words To support generic exception handlers the processor also places the vector offset in the exception stack frame The format code field allows the return from exception RTE instruction to identify what information is on the stack so that it can be properly restored Table 6 4 lists the MC68010 format codes Although some formats are specific to a particular M68000 Family processor the format 0000 is always legal and indicates that just the first four words of the frame are present MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 69 6 10 ODD BYTE 7 0 15 0 HIGHER ADDRESS STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW Figure 6 5 Group 1 and 2 Exception Stack Frame MC68000 68 000 MC68HC001 MC68bECO000 and MC68008 HIGHER ADDRESS 15 0 STATUS REGISTER PROGRAM COUNTER HIGH sp PROGRAM COUNTER LOW FORMAT VECTOR OFFSET OTHER INFORMATION DEPENDING ON EXCEPTION Figur
22. 8 2 0 22 4 1 Word 8 2 0 50 6 2 a 12 2 0 58 10 4 ABCD 10 2 0 20 4 1 SBCD 10 2 0 20 4 1 7 11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Tables 7 13 and 7 14 list the timing data for miscellaneous instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 7 9 Table 7 13 Miscellaneous Instruction Execution Times Instruction Register Memory ANDIOCOR eeo ANDHOSR EORMoCOR e0 820 _ 2 2 0 MOVE from USP 8 2 0 8 2 0 ORI to CCR 32 6 0 pom 6 0 ___ ORI to SR ___ RESET 136 2 0 l TE mw RTR wwo RTS STOP 4 0 0 SWAP 8 2 0 TRAPV No Ta am me o Add effective address calculation time for word operand Table 7 14 Move Peripheral Instruction Execution Times Instruction Size Register Memory Memory Register MOVEP 24 4 2 24 6 0 32 4 4 32 8 0 Add effective address calculation time 7 12 EXCEPTION PROCESSING EXECUTION TIMES Table 7 15 lists the timing data for exception processing The
23. fully asynchronous write cycle UDS LDS Figure 5 31 Fully Asynchronous Read Cycle 5 32 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA D ef S _ _ Figure 5 32 Fully Asynchronous Write Cycle In the asynchronous mode the accessed device operates independently of the frequency and phase of the system clock For example the MC68681 dual universal asynchronous receiver transmitter DUART does not require any clock related information from the bus master during a bus transfer Asynchronous devices are designed to operate correctly with processors at any clock frequency when relevant timing requirements are observed A device can use a clock at the same frequency as the system clock e g 8 10 or 12 5 16 20 2 but without a defined phase relationship to the system clock This mode of operation is pseudo asynchronous it increases performance by observing timing parameters related to the system clock frequency without being completely synchronous with that clock A memory array designed to operate with a particular frequency processor but not driven by the processor clock is a common example of a pseudo asynchronous device The designer of a fully asynchronous system can make no assumptions about address setup time which could be used to improve performance With the system clock frequency known the slav
24. size of the index register Xn does not affect execution time Table 9 5 Move Long Instruction Loop Mode Execution Times Loop Continued Loop Terminated Valid Count cc False Valid count cc True Expired Count Destination Dn 402 20 2 2 20 2 2 18 2 2 18 2 2 4 0 2 14 0 2 20 2 2 20 2 2 18 2 2 18 2 2 2 2 2 22 2 2 28 4 2 28 4 2 24 4 2 24 4 2 An 22 2 2 22 2 2 4 2 2 28 4 2 28 4 2 4 2 24 4 2 24 4 2 24 2 2 24 2 2 6 2 2 30 4 2 30 4 2 4 2 26 4 2 26 4 2 9 3 STANDARD INSTRUCTION EXECUTION TIMES The numbers of clock periods shown in tables 9 6 and 9 7 indicate the times required to perform the operations store the results and read the next instruction The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign In Tables 9 6 and 9 7 the following notation applies An Address register operand Sn Data register operand ea operand specified by an effective address Memory effective address operand 94 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 9 6 Standard Instruction Execution Times struction sze opceas An op
25. 1 015 00 BUS THREE STATED BG ASSERTED BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR VALID INTERNAL BGACK NEGATED INTERNAL BGACK SAMPLED BR SAMPLED BR ASSERTED BGACK ET 50 51 52 53 S4 55 S6 57 50 51 52 53 54 55 56 57 50 51 TAN lt PROCESSOR gt lt ALTERNATE BUS MASTER gt lt Processor gt Figure 5 19 3 Wire Bus Arbitration Timing Diagram Processor Active 5 18 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK 50 S1 52 53 54 55 56 57 50 51 52 53 54 ae BORK 23 1 005 RW PI BUS lt PROCESSOR gt lt INACTIVE gt lt ALTERNATE BUS MASTER gt lt processor gt Figure 5 20 3 Wire Bus Arbitration Timing Diagram Bus Inactive MOTOROLA 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 19 BUS THREE STATED BUS RELEASED FROM THREE STATE AND BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE BR VALID INTERNAL BGACK NEGATED INTERNAL BR SAMPLED BGACK SAMPLED BR ASSERTED BGACK NEGATED w 7 y ba Ne e 85 uL D ce AU cc fF RW DTACK lt PROCESSOR gt
26. 5 The minimum value must be met to guarantee proper operation If the maximum value is exceeded BG may be reasserted 46 47 57A 81 5 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 17 STROBES AND R W CLK NOTE Setup time to the clock 47 for the asynchronous inputs BERR BGACK BR DTACK IPL2 IPLO and VPA guarantees their recognition at the next falling edge of the clock Figure 10 7 Bus Arbitration Timing Applies To All Processors E xcept The MC68EC 000 10 18 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA CLK 2 19 0 NOTES Waveform measurements for inputs and outputs are specified at logic high 2 0 V logic low 0 8 V 1 MC 68008 52 Pin Version only Figure 10 8 Bus Arbitration Timing Applies To All Processors E xcept The MC68EC 000 MOTOROLA 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 19 NOTES Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V 1 MC 68008 52 Pin Version only Figure 10 9 Bus Arbitration Timing Idle Bus Case Applies To All Processors E xcept The MC68EC 000 10 20 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA R W FC2 FCO A19 A0 07 00 NOTE Waveform measurements for all inputs and outputs are speci
27. 5 1 5 1 4 1 lt data gt size of the index register Xn does not affect execution time 7 2 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA An 916 An dg xxx L 416 dg Xn lt data gt Table 7 3 Move Word Instruction Execution Times 8 2 0 8 2 0 8 2 0 8 2 0 16 4 0 16 4 0 16 4 0 18 4 0 24 6 0 26 6 0 24 6 0 24 6 0 32 8 0 32 8 0 24 6 0 24 6 0 26 6 0 26 6 0 16 4 0 16 4 0 16 4 0 18 4 0 24 6 0 26 6 0 16 2 2 16 2 2 24 4 2 24 4 2 26 4 2 32 6 2 34 6 2 32 6 2 40 8 2 32 6 2 34 6 2 24 4 2 Destination m sh aan xe 32 6 2 32 6 2 40 8 2 40 8 2 42 8 2 48 10 2 50 10 2 48 10 2 56 12 2 8 10 2 aa 0 2 40 8 2 16 2 2 16 2 2 24 4 2 24 4 2 26 4 2 32 6 2 34 6 2 32 6 2 40 8 2 32 6 2 34 6 2 24 4 2 16 2 2 16 2 2 24 4 2 24 4 2 24 4 2 26 4 2 24 4 2 24 4 2 26 4 2 24 4 2 32 6 2 34 6 2 32 6 2 32 6 2 4 6 2 32 6 2 26 4 2 34 6 2 3 32 6 2 40 8 2 3 32 6 2 4 6 2 34 6 2 2 8 2 42 8 2 40 8 2 4 8 2 2 8 2 32 6 2 8 2 40 8 2 48 10 2 8 2 a 8 2 50 10 2 48 10 2 32 6 2 40 8 2 34 6 2 42 8 2 42 8 2 40 8 2 44 8 2 42 8 2 24 4 2 32 6 2 34
28. 11 10 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA P SUFFIX 754 01 D gt G lt NOTES 1 DIMENSIONS A AND B ARE DATUMS MILLIMETERS 5 2 T IS SEATING PLANE MIN MAX MIN MAX 81 16 81 91 3 195 3 225 SE 12057 070010810 00 25 0 010 GIT AD 7 4 83 5 84 0 190 0 230 0 33 053 0 013 0 021 DIMENSION DOES NOT INCLUDEMOLD FLASH DIMENSION LIS TO CENTER OF LEADS WHEN FORMED 1 27 1 77 0 050 0 070 PARALLEL 2 54BSC 0 100BSC 6 DIMENSIONING AND TOLERANCING PER ANSIY14 5 1982 0 20 038 0 008 0 015 3 05 3 55 0 120 0 140 2286BSC 0 900BSC oe is o 19 0 51 1 02 0 020 0 040 en gt Figure 11 10 Case 754 01 R and Suffix MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 11 11 Figure 11 11 Case 765A 05 RC Suffix 11 12 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA APPENDIX 68010 LOOP MODE OPERATION In the loop mode of the MC68010 a single instruction is executed repeatedly under control of the test condition decrement and branch DBcc instruction without any instruction fetch bus cycles The execution of a single instruction loop without fetching an instruction provides a highly efficient means of repeating an instruction
29. 64 Pin Dual In Line M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 2080 N 20 20 22 lo OG rm e a Zo morc gt w ogosoz N cn MOTOROLA 505 MC68000 MC68010 M C68HC000 m um lt Z lt MC68HC001 5 go a t3 gt BORO gt 3o 2 ZoZo 5020 gt lo lo gt gt BORO OZO lo O gt ogomo gt lt gt gt 9 I I gt 25 m ce m BOTTOM VIEW BOTTOM VIEW 5 gt N p ONO M gt gt gt gt N gt 25 OZO Ge Slo cn a cooQ ZO C SORO N gt cO N Figure 11 2 68 Lead Pin Grid Array M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 8 goz 11 3
30. B W or L indicate an operand size of byte word or long word M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 4 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA
31. GND 0 V TA T to TH see Figures 10 4 and 10 5 Applies To Processors Except The 68 000 Characteristic Clock Low to Address Valid 6A Clock High to FC Valid Clock High to Address Data Bus High Impedance Maximum Clock High to Address FC Invalid Minimum 9 Clock High to AS DS 3 Asserted 112 Address Valid to AS DS Asserted Read AS Asserted Write 11A FC Valid to AS DS Asserted Read AS Asserted Write gt o gt o 12 Clock Low to AS DS Negated 132 AS DS Negated to Address FC Invalid 142 ASand DS Read Width 270 Asserted 14 DS Width Asserted Write 14 gt o 2 o 3 3 3 3 3 3 ios RN d ES o 152 AS DS Width Negated 15 6 Clock High to Control Bus High Impedance AS DS Negated to R W 40 Invalid gt o 3 o 1 18 Clock High to R W High Read Clock High to R W Low Write 0 gt o 72 7 2 1 20A26 AS Asserted to R W Valid Write 212 Address Valid to R W Low 20 Write 2 3 3 o 3 o 21A FC Valid to R W Low Write 22 R W Low to DS Asserted Write 2 Clock Low to Data Out Valid Write 252 5 DS Negated to Data Ou Invalid Write gt o 10 10 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Characteristic Data Out Valid to DS Asserted 40 Write Data In Valid to Clock Low 10 Setup Time on Read 27 9 Late BERR Asserted to Clock Low set
32. HALT must also be asserted When RESET and HALT are driven by an external device the entire system including the processor is reset Resetting the processor initializes the internal state The processor reads the reset vector table entry address 00000 and loads the contents into the supervisor stack pointer SSP Next the processor loads the contents of address 00004 vector table entry 1 into the program counter Then the processor initializes the interrupt level in the status register to a value of seven In the MC68010 the processor also clears the vector base register to 00000 No other register is affected by the reset sequence Figure 5 30 shows the timing of the reset operation CLK 5 015 ec Ie gt 100 MILLISECONDS gt RESET HALT lt gt T 4CLOCKS k 1 BUS CYCLES 2 3 4 5 6 NOTES 1 Internal start up time 4 PC High read in here Bus State Unknown 2 SSP high read in here 5 PC Low read in here 3 SSP low read in here 6 First instruction fetched here All Control Signals Inactive Data Bus in Read Mode Figure 5 30 Reset Operation Timing Diagram The RESET instruction causes the processor to assert RESET for 124 clock periods to reset the external devices of the system The internal state of the processor is not affected Neither the status register nor any of the internal registers is affected by an internal reset operation All external devices in the system
33. PLACE DATA ON 015 00 3 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK ACQUIRE THE DATA 1 LATCHDATA __ 2 NEGATE UDS AND LDS 3 NEGATE AS TERMINATE THE CYCLE 1 REMOVE DATA FROM 015 00 2 NEGATE DTACK START NEXT CYCLE Figure 5 1 Word Read Cycle Flowchart BUS MASTER SLAVE ADDRESS THE DEVICE 1 SETR W TO READ 2 PLACE FUNCTION CODE ON FC2 FCO 3 PLACE ADDRESS ON 23 1 _ 4 ASSERT ADDRESS STROBE AS __ 5 ASSERT UPPER DATA STROBE UDS OR LOWER DATA STROBE 05 BASED ON INTERNAL 0 1 DECODE ADDRESS 2 PLACE DATA 07 00 OR 015 08 BASED ON UDS OR LDS 3 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK ACQUIRE THE DATA 1 000 2 NEGATE UDS AND LDS 3 NEGATE AS TERMINATE THE CYCLE 1 REMOVE DATA FROM 07 00 OR D15 D8 2 NEGATE DTACK START NEXT CYCLE Figure 5 2 Byte Read Cycle Flowchart 5 2 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 50 51 52 53 54 55 S6 57 50 S1 52 53 54 55 56 57 50 5152 53 54 w w w w 55 56 57 CLK we E Ye RW lt gt lt gt lt gt WRITE 2 WAIT STATE READ READ Figure 5 3 Read and Write Cycle Timing Diagram 50 51 52 S3 54 S5 S6 57 50 5152 S3 54 S5 S6 57 50 51 S2 53 S4 S5 S6 57 CLK LO 005 LDS RW DTACK Dis I eM 222222222222 gt lt gt lt gt WRITE READ nternal Signal Only READ Figu
34. case surface 9JC and from the case to the outside ambient air CA These terms are related by the equation 9JC 4 9JC is device related and cannot be influenced by the user However is user dependent and can be minimized by such thermal management techniques as heat sinks ambient air cooling and thermal convection Thus good thermal management on the part of the user can significantly reduce 9CA so that 9JA approximately equals 9JC Substitution of 9Jc for in equation 1 results a lower semiconductor junction temperature 10 2 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 10 1 summarizes maximum power dissipation and average junction temperature for the curve drawn in Figure 10 1 using the minimum and maximum values of ambient temperature for different packages and substituting 9JC for 9 assuming good thermal management Table 10 2 provides the maximum power dissipation and average junction temperature assuming that no thermal management is applied i e still air NOTE Since the power dissipation curve shown in Figure 10 1 is negatively sloped power dissipation declines as ambient temperature increases Therefore maximum power dissipation occurs at the lowest rated ambient temperature but the highest average junction temperature occurs at the maximum ambient temperature where power dissipation is lowest 2 2 2 0 1 8 1 6 POWER H5 WATTS
35. for instructions The totals include fetching any extension words computing the address and fetching the memory operand The total number of clock periods the number of read cycles and the number of write cycles zero for all effective address calculations are shown in the previously described format Table 9 1 Effective Address Calculation Times Byte Word Register Data Register Direct an 00 Address Register Direct Memory Address Register Indirect 4 1 0 2 0 0 8 2 0 Address Register Indirect with Postincrement 4 1 0 4 0 0 8 2 0 T it Xn Address Register Indirect with Index 10 2 0 Absolute Short 8 2 0 Absolute Long 12 3 0 916 s Program Counter Indirect with Displacement 8 2 0 dg PC Xn Program Counter Indirect with Index 10 2 0 14 3 0 lt data gt Immediate 4 1 0 8 2 0 size of the index register Xn does not affect execution time 9 2 MOVE INSTRUCTION EXECUTION TIMES Tables 9 2 9 3 9 4 and 9 5 list the numbers of clock periods for the move instructions The totals include instruction fetch operand reads and operand writes The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format 9 2 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 9 2 Move Byte and Word Instruction Execution Times Destination m An ane Am dg An
36. tracing and other exceptional conditions The exception may be internally generated by an instruction or by an unusual condition arising during the execution of an instruction Externally exception processing can be forced by an interrupt by a bus error or by a reset Exception processing provides an efficient context switch so that the processor can handle unusual conditions The halted processing state is an indication of catastrophic hardware failure For example if during the exception processing of a bus error another bus error occurs the processor assumes the system is unusable and halts Only an external reset can restart a halted processor Note that a processor in the stopped state is not in the halted state nor vice versa 6 1 PRIVILEGE MODES The processor operates in one of two levels of privilege the supervisor mode or the user mode The privilege mode determines which operations are legal The mode is optionally used by an external memory management device to control and translate accesses The mode is also used to choose between the supervisor stack pointer SSP and the user stack pointer USP in instruction references MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 6 1 The privilege mode is a mechanism for providing security in a computer system Programs should access only their own code and data areas and should be restricted from accessing information that they do not need and must not modify The oper
37. 0 Word 10 2 2 0 16 2 2 Long 12 n2 2 0 LSR LSL Byte 10 2 2 0 Word 10 2n 2 0 16 2 2 Long 12 12 2 0 ROR ROL Byte 10 2n 2 0 Word 10 2n 2 0 16 2 2 Long 12 2 2 0 ES ROXR ROXL Byte 10 2n 2 0 Word 10 2n 2 0 16 2 2 Long 12 12 2 0 Add effective address calculation time for word operands nis the shift count M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 7 7 MANIPULATION INSTRUCTION EXECUTION TIMES Table 7 9 lists the timing data for the bit manipulation instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 7 9 Bit Manipulation Instruction Execution Times BCHG Byte 2 2 1 20 4 1 Long BCLR Byte 2 2 1 Long BSET Byte 2 2 1 Long BTST Byte 8 2 0 Long Add effective address calculation time Indicates maximum value data addressing mode only 20 4 1 0 4 0 2 4 0 20 4 1 0 4 0 8 4 0 16 4 0 7 8 CONDITIONAL INSTRUCTION EXECUTION TIMES Table 7 10 lists the timing data for the conditional instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previou
38. 16 32 BIT MICROPROCESSORS USER S MANUAL 5 25 In the MC68010 if a read modify write operation terminates in a bus error the processor reruns the entire read modify write operation when the RTE instruction at the end of the bus error handler returns control to the instruction in error The processor reruns the entire operation whether the error occurred during the read or write portion 5 4 2 Retrying The Bus Cycle The assertion of the bus error signal during a bus cycle in which HALT is also asserted by an external device initiates a retry operation Figure 5 27 is a timing diagram of the retry operation The delayed BERR signal in the MC68010 also initiates a retry operation when HALT is asserted by an external device Figure 5 28 shows the timing of the delayed operation 50 52 54 S6 58 50 52 54 5 _ 1 1 i ee pr p LEE fi AS LDS UDS ne RW DTACK 0500 oO BERR lt gt 1 CLOCK PERIOD HALT READ gt lt HALT gt RETRY Figure 5 27 Retry Bus Cycle Timing Diagram 5 26 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA lt READ gt lt HALT gt lt RETRY gt Figure 5 28 Delayed Retry Bus Cycle Timing Diagram The processor terminates the bus cycle then puts the address and data lines in the high impedance state The processor remains in this state until HALT is negated The
39. 16 15 0 SSP POINTER 15 87 0 1 CCR SR STATUS REGISTER Figure 2 2 Supervisor Programmer s Model Supplement The supervisor programmer s model supplement of the MC68010 is shown in Figure 2 3 In addition to the supervisor stack pointer and status register it includes the vector base register VRB and the alternate function code registers AFC The VBR is used to determine the location of the exception vector table in memory to support multiple vector 2 2 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA tables The SFC and DFC registers allow the supervisor to access user data space emulate CPU space cycles 31 16 15 0 SUPERVISOR STACK SSP POINTER 15 87 0 1 CCR SR STATUS REGISTER 31 0 2 0 SFC ALTERNATE FUNCTION CODE REGISTERS Figure 2 3 Supervisor Programmer s Model Supplement MC68010 2 1 3 Status Register The status register SR contains the interrupt mask eight levels available and the following condition codes overflow V zero Z negative N carry C and extend X Additional status bits indicate that the processor is in the trace T mode and or in the supervisor S state see Figure 2 4 Bits 5 6 7 11 12 and 14 are undefined and reserved for future expansion SYSTEM BYTE USER BYTE 15 13 10 8 4 0 EE ono _ TRACE MODE dis CONDITION INTERRUPT MASK CARRY _ Figure 2 4 Status Reg
40. 2 AS N N UDS LDS RW DTACK 88 40 BERR _ reno cyce B ERROR TATE gt Figure 5 26 Delayed Bus Error Timing Diagram MC68010 After the aborted bus cycle is terminated and BERR is negated the processor enters exception processing for the bus error exception During the exception processing sequence the following information is placed on the supervisor stack 1 Status register 2 Program counter two words which may be up to five words past the instruction being executed 3 Error information The first two items are identical to the information stacked by any other exception The error information differs for the 68010 The MC68000 68 000 MC68HC001 MC68ECO000 and MC68008 stack bus error information to help determine and to correct the error The MC68010 stacks the frame format and the vector offset followed by 22 words of internal register information The return from exception RTE instruction restores the internal register information so that the MC68010 can continue execution of the instruction after the error handler routine completes After the processor has placed the required information on the stack the bus error exception vector is read from vector table entry 2 offset 08 and placed in the program counter The processor resumes execution at the address in the vector which is the first instruction in the bus error handler routine MOTOROLA M68000 8
41. 4n 0 Long 12 8 12 8 16 8 18 8n 16 8n 20 8n 16 8n 18 8n 3 2 0 3 n 0 4 2 0 4 2 0 4 2 0 5 2 0 4 2 0 4 2 0 Word 8 4 8 4n 12 4n 14 4n 12 4n 16 4n 2 2 n 3 n 3 n 3 n 4 n Long 8 8n 8 8 12 8 14 8 12 8 16 8 2 2n 2 2n 3 2n 3 2n 3 2n 4 2n nis the number of registers to move size of the index register Xn does not affect the instruction s execution time 8 10 MULTIPRECISION INSTRUCTION EXECUTION TIMES Table 8 11 lists the timing data for multiprecision instructions The number of clock periods includes the time to fetch both operands perform the operations store the results and read the next instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The following notation applies in Table 8 11 Dn Data register operand M Memory operand 8 8 68000 8 16 32 MICROPROCESSORS UISER S MANUAL MOTOROLA Table 8 11 Multiprecision Instruction Execution Times emen se mmm emm TE Di E TIT 8 11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Tables 8 12 and 8 13 list the timing data for miscellaneous instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and
42. 5 16 show 2 wire bus arbitration Bus arbitration on all microprocessors except the 48 pin 68008 68 000 BGACK must be pulled high for 2 wire bus arbitration MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 11 PROCESSOR REQUESTING DEVICE REQUEST THE BUS 1 ASSERT BUS REQUEST BR GRANT BUS ARBITRATION 1 ASSERT BUS GRANT BG ACKNOWLEDGE BUS MASTERSHIP 1 EXTERNAL ARBITRATION DETER MINES NEXT BUS MASTER 2 NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE 3 NEXT BUS MASTER ASSERTS BUS GRANT ACKNOWLEDGE BGACK TO BECOME NEW MASTER 4 BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1 PERFORM DATA TRANSFERS READ AND WRITE CYCLES ACCORDING TO THE SAME RULES THE PRO CESSOR USES TERMINATE ARBITRATION 1 NEGATE BG AND WAIT FOR BGACK TO BE NEGATED RELEASE BUS MASTERSHIP 1 NEGATE BGACK REARBITRATE OR RESUME PROCESSOR OPERATION Figure 5 13 3 Wire Bus Arbitration Cycle Flowchart Not Applicable to 48 MC68008 or MC68ECO00 5 12 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA PROCESSOR REQUESTING DEVICE REQUEST THE BUS 1 ASSERT BUS REQUEST BR GRANT BUS ARBITRATION 1 ASSERT BUS GRANT BG OPERATE AS BUS MASTER 1 EXTERNAL ARBITRATION DETER MINES NEXT BUS MASTER 2 NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE BUS MASTERSHIP RELEASE BUS MASTERSHIP 1 NEGATE BUS REQUEST BR 1 N
43. 5 18 Bus Arbitration Unit State 5 19 3 Wire Bus Arbitration Timing Diagram Processor Active 5 20 3 Wire Bus Arbitration Timing Diagram Bus Active 5 21 3 Wire Bus Arbitration Timing Diagram Special Case 5 22 2 Wire Bus Arbitration Timing Diagram Processor Active 5 23 2 Wire Bus Arbitration Timing Diagram Bus Active 5 24 2 Wire Bus Arbitration Timing Diagram Special Case 5 25 Bus Error Timing Diagram aside rre redes cot dg eade 5 26 Delayed Bus Error Timing Diagram 68010 5 27 Retry Bus Cycle Timing 5 28 Delayed Retry Bus Cycle Timing 5 29 Halt Operation Timing ene pa se 5 30 Reset Operation Timing 5 31 Fully Asynchronous Read 5 32 Fully Asynchronous Write 5 33 Pseudo Asynchronous Read Cycle 5 34 Pseudo Asynchronous Write 5 35 Synchronous Read 5 36 Synchronous Write Cycle
44. 55 0 014 0 022 POSITIONAL TOLERANCE FOR LEAD 1 02 152 0 040 0 060 PATTERN G 2 54 BSC 0 100 BSC 0 25 0 020 B H 1 79 BSC 0 070 BSC 3 DIMENSION A AND B DOES NOT INCLUDE MOLD FLASH 0 20 0 38 0 008 0 015 AXIMUM MOLD FLASH 0 25 0 010 2 92 381101151 0 135 4 DIMENSION L IS TO CENTER OF LEADS WHEN FORMED 1521846 0600BSC PARALLEL T st 5 5 DIMENSIONING AND TOLERANCING PER ANSI 14 5 1982 1 gt 0 15 6 CONTROLLING DIMENSION INCH 0 51 1 02 0 020 0 040 Figure 11 8 Case 767 02 P Suffix MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 11 9 L SUFFIX 746 01 am um HEN M bas D K k EN E ue NOTES MILLIMETERS INCHES 1 DIMENSION A IS DATUM DIM MIN MIN 2 POSTIONAL TOLERANCE FOR LEADS 80 52 82 04 3 170 3 230 0 25 0 010 T AW B 22 25 22 96 0 876 0 904 3 IS SEATING PLANE 3 05 4 32 0 120 0 160 4 DIMENSION L TO CENTER OF LEADS p 038 053 0 015 0 021 WHEN FORMED PARALLEL 76 140 0 0301 0 055 5 DIMENSIONING AND TOLERANCING PER ANSIY 14 5 1973 G 254BSC 0 100 BSC 0 20 0 33 0 008 0 013 2 54 419 0 100 0 165 22 61 23 11 0 890 0 910 0 10 0 10 102 152 0 040 0 060 Figure 11 9 Case 746 01 LC Suffix
45. 6 2 32 6 2 size of the index register Xn does not affect execution time 416 dg xxx L 416 PC dg Xn lt data gt Table 7 4 Move Long Instruction Execution Times 8 2 0 8 2 0 24 6 0 24 6 0 26 6 0 32 8 0 34 8 0 32 8 0 8 2 0 8 2 0 32 8 0 34 8 0 24 6 0 24 6 0 24 6 0 26 6 0 32 8 0 34 8 0 32 8 0 40 10 0 40 10 0 56 10 4 56 10 4 56 10 4 32 8 0 34 8 0 24 6 0 48 8 4 50 8 4 40 6 4 Destination m ame sam aan xn 24 2 4 24 2 4 40 6 4 40 6 4 42 6 4 48 8 4 50 8 4 48 8 4 24 2 4 24 2 4 40 6 4 40 6 4 42 6 4 48 8 4 50 8 4 48 8 4 24 2 4 24 2 4 40 6 4 40 6 4 42 6 4 48 8 4 50 8 4 48 8 4 32 4 4 32 4 4 48 8 4 48 8 4 34 4 4 32 4 4 40 6 4 34 4 4 32 4 4 40 6 4 50 8 4 48 8 4 56 10 4 8 48 8 4 56 10 4 50 8 4 58 10 4 56 10 4 10 4 56 10 4 64 12 4 58 10 4 60 10 4 58 10 4 66 12 4 56 10 4 58 10 4 56 10 4 64 12 4 64 12 4 66 12 4 64 12 4 72 14 4 56 10 4 58 10 4 56 10 4 64 12 4 58 10 4 66 12 4 48 8 4 56 10 4 4 4 50 50 8 4 52 8 58 48 8 4 50 8 4 40 6 4 48 8 4 50 8 4 40 6 4 58 10 4 60 10 4 48 8 4 50 8 4 size of the index register Xn does not affect execution time 7 3 STANDARD INSTRUCTION EXECU
46. AS Negated swims Asynchronous Input Setup 5 Time 581 BR Negated to AS DS R W 15 1 5 15 15 Driven Nevatedtorc Driven 1 1 NOTES 1 The minimum value must be met to guarantee proper operation If the maximum value is exceeded BG may be reasserted 2 DS is used in this specification to indicate UDS and LDS 10 28 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA CLK FC2 FCO NOTES Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 20 8 V Figure 10 14 68 000 Bus Arbitration Timing Diagram MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 29 SECTION 11 ORDERING INFORMATION AND MECHANICAL DATA This section provides pin assignments and package dimensions for the devices described in this manual 11 1 PIN ASSIGNMENTS nme v M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 11 1 04 03 02 01 00 AS 005 105 R W DTACK BG BGACK BR Vcc CLK GND HALT RESET VMA VPA BERR IPL2 IPLI IPLO FC2 FCO Al A2 A3 Ad C Ui MC68000 MC68010 MC68HC000 Figure 11 1
47. High Low Supervisor Program 3 9 CLOCK CLK The clock input is a TTL compatible signal that is internally buffered for development of the internal clocks needed by the processor This clock signal is a constant frequency square wave that requires no stretching or shaping The clock input should not be gated off at any time and the clock signal must conform to minimum and maximum pulse width times listed in Section 10 Electrical Characteristics 3 10 POWER SUPPLY Vcc and GND Power is supplied to the processor using these connections The positive output of the power supply is connected to the Vcc pins and ground is connected to the GND pins MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 39 3 11 SIGNAL SUMMARY Table 3 4 summarizes the signals discussed in the preceding paragraphs Table 3 4 Signal Summary Signal Name Input Output Active State On HALT On Bus Relinquish Yes Yes m ad Write Low Data Strobe low Upper and Lower Data srobes 068 065 cuna tow ve Data Transfer actnowedge tow BusReqest 1 mu iw asm _ tow Bus Grantacknowedge tow IPL2 Bus Error tow Low No Yes Enable E Output Valid Memory Address Output Lo Lo Lo Ww FC2 Fea
48. MC68XXX Microcomponent Devices and are provided for design purposes only Thermal measurements are complex and dependent on procedure and setup User derived values for thermal resistance may differ 10 4 CMOS CONSIDERATIONS 68 000 68 001 and 68 000 with it significantly lower power consumption has other considerations The CMOS cell is basically composed of two complementary transistors a P channel and an N channel and only one transistor is turned on while the cell is in the steady state The active P channel transistor sources current when the output is a logic high and presents a high impedance when the output is logic low Thus the overall result is extremely low power consumption because no power 10 4 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA is lost through the active P channel transistor Also since only one transistor is turned on during the steady state power consumption is determined by leakage currents Because the basic CMOS cell is composed of two complementary transistors a virtual semiconductor controlled rectifier SCR may be formed when an input exceeds the supply voltage The SCR that is formed by this high input causes the device to become latched in a mode that may result in excessive current drain and eventual destruction of the device Although the MC68HCO000 and 68 00 is implemented with input protection diodes care should be exercised to ensure that the
49. S MANUAL MOTOROLA The descriptions of the eight states of a write cycle are as follows STATE 0 STATE 1 STATE 2 STATE 3 STATE 4 STATE 5 STATE 6 STATE 7 The write cycle starts in SO The processor places valid function codes on FC2 FCO and drives R W high if a preceding write cycle has left R W low Entering S1 the processor drives a valid address on the address bus On the rising edge of S2 the processor asserts AS and drives R W low During S3 the data bus is driven out of the high impedance state as the data to be written is placed on the bus At the rising edge of S4 the processor asserts LDS or D S The processor waits for a cycle termination signal DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S4 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the end of S4 the processor inserts wait states full clock cycles until either DTACK or BERR is asserted During S5 no bus signals are altered During S6 no bus signals are altered On the falling edge of the clock entering S7 the processor negates AS LDS and DS As the clock rises at the end of S7 the processor places the address and data buses in the high impedance state and drives R W high The device negates DTACK or BERR at this time 4 1 3 Read Modify Write Cycle The read modify write cycle per
50. STATE 6 During S6 data from the device are driven onto the data bus STATE 7 the falling edge of the clock entering S7 the processor accepts data from the device and negates UDS and LDS The device negates DTACK or BERR at this time STATES 8 11 The bus signals are unaltered during 58 511 during which the arithmetic logic unit makes appropriate modifications to the data 5 8 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA STATE 12 STATE 13 STATE 14 STATE 15 STATE 16 STATE 17 STATE 18 STATE 19 The write portion of the cycle starts in 512 The valid function codes on 2 the address bus lines AS and R W remain unaltered During S13 no bus signals are altered On the rising edge of S14 the processor drives RWW low During S15 the data bus is driven out of the high impedance state as the data to be written are placed on the bus At the rising edge of S16 the processor asserts UDS or LDS The processor waits for DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S16 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the close of S16 the processor inserts wait states full clock cycles until either DTACK or BERR is asserted During S17 no bus signals are altered During S18 no bus signals are altered On the falling edge of the clock entering S19 t
51. a read cycle as follows STATE read cycle starts in state 0 50 The processor places valid function codes FCO FC2 and drives R W high to identify a read cycle STATE 1 Entering state 1 S1 the processor drives a valid address on the address bus STATE 2 On the rising edge of state 2 S2 the processor asserts AS and LDS or DS STATE During state 3 S3 no bus signals are altered STATE 4 During state 4 S4 the processor waits for a cycle termination signal DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S4 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the end of S4 the processor inserts wait states full clock cycles until either DTACK or BERR is asserted STATE 5 During state 5 S5 no bus signals are altered STATE 6 During state 6 S6 data from the device is driven onto the data bus STATE 7 On the falling edge of the clock entering state 7 S7 the processor latches data from the addressed device and negates AS and LDS or DS At the rising edge of S7 the processor places the address bus in the high impedance state The device negates DTACK or BERR at this time NOTE During an active bus cycle VPA and BERR are sampled on every falling edge of the clock beginning with S4 and data is latched on the falling edge of S6 during a read cycle T
52. a write cycle are as follows STATE 0 STATE 1 STATE 2 STATE 3 STATE 4 STATE 5 STATE 6 5 6 The write cycle starts in SO The processor places valid function codes 2 and drives R W high if a preceding write cycle has left RW low Entering S1 the processor drives a valid address on the address bus On the rising edge of S2 the processor asserts AS and drives R W low During S3 the data bus is driven out of the high impedance state as the data to be written is placed on the bus At the rising edge of S4 the processor asserts UDS or LDS The processor waits for a cycle termination signal DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S4 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the end of S4 the processor inserts wait states full clock cycles until either DTACK or BERR is asserted During S5 no bus signals are altered During S6 no bus signals are altered M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA STATE 7 the falling edge of the clock entering S7 the processor negates AS UDS or LDS As the clock rises at the end of S7 the processor places the address and data buses in the high impedance state and drives R W high The device negates DTACK or BERR at this time 5 1 3 Read Modify Write Cycle The read modify wr
53. and then bus error Within group 1 trace has priority over external interrupts which in turn takes priority over illegal instruction and privilege violation Since only one instruction can be executed at a time no priority relationship applies within group 2 The priority relationship between two exceptions determines which is taken or taken first if the conditions for both arise simultaneously Therefore if a bus error occurs during a TRAP instruction the bus error takes precedence and the TRAP instruction processing is aborted In another example if an interrupt request occurs during the execution of an instruction while the T bit is asserted the trace exception has priority and is processed first Before instruction execution resumes however the interrupt exception is also processed and instruction processing finally commences in the interrupt handler routine A summary of exception grouping and priority is given in Table 6 3 As a general rule the lower the priority of an exception the sooner the handler routine for that exception executes For example if simultaneous trap trace and interrupt exceptions are pending the exception processing for the trap occurs first followed immediately by exception processing for the trace and then for the interrupt When the processor resumes normal instruction execution it is in the interrupt handler which returns to the trace handler which returns to the trap execution handler This rule doe
54. because the only bus cycles required are those that read and write the operands The DBcc instruction uses three operands a loop counter a branch condition and a branch displacement When this instruction is executed in the loop mode the value in the low order word of the register specified as the loop counter is decremented by one and compared to minus one If the result after decrementing the value is equal to minus one the result is placed in the loop counter and the next instruction in sequence is executed Otherwise the condition code register is checked against the specified branch condition If the branch condition is true the result is discarded and the next instruction in sequence is executed When the count is not equal to minus one and the branch condition is false the branch displacement is added to the value in the program counter and the instruction at the resulting address is executed Figure A 1 shows the source code of a program fragment containing a loop that executes in the loop mode in the MC68010 The program moves a block of data at address SOURCE to a block starting at address DEST The number of words in the block is labeled LENGTH If any word in the block at address SOURCE contains zero the move operation stops and the program performs whatever processing follows this program fragment LEA SOURCE AO Load A Pointer To Source Data LEA DEST 1 Load A Pointer To Destination MOVE W LENGTH DO Load The Counter Re
55. claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer MOTOROLA INC 1993 Paragraph Number 5 TABLE OF CONTENTS Title Section 1 Overview Section 2 Introduction Programmer s User s Programmer s Model Supervisor Programmer s Model Status LE Data Types and Addressing Modes Data Organization In Registers Data ERU ID Address 6 Data Organization In Instruction Set Summary sss essen Section 3 Signal Description Addr ss E Data Asynchronous 22 2 044 lt Bus Arbitration Interrupt Control iiec System CONO s M6800 Peripheral Control ie Processor Function
56. is asserted coincident with or preceding DTACK and BERR remains negated case 2 Bus Error Termination BERR is asserted in lieu of coincident with or preceding DTACK case 3 In the MC68010 the late bus error also BERR is asserted following DTACK case 4 HALT remains negated and BERR is negated coincident with or after DTACK Retry Termination HALT and BERR asserted in lieu of coincident with or before DTACK case 5 In the MC68010 the late retry also BERR and HALT are asserted following DTACK case 6 BERR is negated coincident with or after HALT must be held at least one cycle after BERR Table 5 1 shows the details of the resulting bus cycle termination in the M68000 microprocessors for various combinations of signal sequences 5 30 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 5 1 BERR and HALT Assertion Results Asserted on Control Rising Edge 68000 68 000 001 MC68010 Results Signal of State EC000 MC68008 Results 2 Normal cycle terminate and continue Normal cycle terminate and continue Normal cycle terminate and halt Normal cycle terminate and halt Continue when HALT negated Continue when HALT negated Terminate and take bus error trap Terminate and take bus error trap Normal cycle terminate and continue Terminate and take bus error trap Terminate and retry when HALT Terminate and retry when HALT removed removed Nor
57. logic circuitry should respond to the negation of the AS and UDS LDS and or DS by negating DTACK and or BERR Parameter 28 is the hold time for DTACK and parameter 30 is the hold time for BERR Figure 5 35 shows a synchronous read cycle and the important timing parameters that apply The timing for a synchronous read cycle including relevant timing parameters is shown in Figure 5 36 CLOCK ADDR 005 005 Figure 5 35 Synchronous Read Cycle MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 37 50 51 52 53 54 55 56 57 50 005 05 Figure 5 36 Synchronous Write Cycle A key consideration when designing in a synchronous environment is the timing for the assertion of DTACK and BERR by an external device To properly use external inputs the processor must synchronize these signals to the internal clock The processor must sample the external signal which has no defined phase relationship to the CPU clock which may be changing at sampling time and must determine whether to consider the signal high or low during the succeeding clock period Successful synchronization requires that the internal machine receives a valid logic level not a metastable signal whether the input is high low or in transition Metastable signals propagating through synchronous machines can produce unpredictable operation Figure 5 37 is a conceptual representation of the input sync
58. maximum input voltage specification is not exceeded Some systems may require that the CMOS circuitry be isolated from voltage transients other may require additional circuitry The 68 000 and 68 000 implemented in CMOS is applicable to designs to which the following considerations are relevant 1 The 68 000 MC68ECO000 completely satisfies the input output drive requirements of CMOS logic devices 2 The HCMOS MC68HC000 and 68 00 provides an order of magnitude reduction in power dissipation when compared to the HMOS MC68000 However the MC68HCO000 does not offer a power down mode 10 5 AC ELECTRICAL SPECIFICATION DEFINITIONS The AC specifications presented consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals The measurement of the AC specifications is defined by the waveforms shown in Figure 10 2 To test the parameters guaranteed by Motorola inputs must be driven to the voltage levels specified in the figure Outputs are specified with minimum and or maximum limits as appropriate and are measured as shown Inputs are specified with minimum setup and hold times and are measured as shown Finally the measurement for signal to signal specifications are shown NOTE The testing levels used to verify conformance to the AC specifications does not affect the gu
59. numbers of clock periods include the times for all stacking the vector fetch and the fetch of the first instruction of the handler routine The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock 7 10 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 7 15 Exception Processing Execution Times exception TIS Zr sas RESET 64 12 0 Add effective address calculation time ndicates the time from when RESET and HALT are first sampled as negated to when instruction execution starts MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 7 11 8 16 BIT INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock CLK periods for the MC68000 68 000 68 001 and the MC68ECO00 in 16 bit mode In this data it is assumed that both memory read and write cycles consist of four clock periods A longer memory cycle causes the generation of wait states that must be added to the total instruction times The number of bus read and write cycles for each instruction is also included with the timing data This data i
60. of the next instruction exception processing for a trace begins A copy is made of the status register The transition to supervisor mode is made and the T bit of the status register is turned off disabling further tracing The vector number is generated to reference the trace exception vector and the current program counter and the copy of the status register are saved on the supervisor stack On the MC68010 the format offset word is also saved on the supervisor stack The saved value of the program counter is the address of the next instruction Instruction execution commences at the address contained in the trace exception vector 6 3 9 Bus Error A bus error exception occurs when the external logic requests that a bus error be processed by an exception The current bus cycle is aborted The current processor activity whether instruction or exception processing is terminated and the processor immediately begins exception processing The bus error facility is identical on the all processors however the stack frame produced on the MC68010 contains more information The larger stack frame supports instruction continuation which supports virtual memory on the MC68010 processor 6 3 9 1 BUS ERROR Exception processing for a bus error follows the usual sequence of steps The status register is copied the supervisor mode is entered and tracing is turned off The vector number is generated to refer to the bus error vector Since the processor
61. offset word MC68010 only program counter and status 612 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA register the supervisor stack The offset value in the format offset word MC68010 is the vector number multiplied by four The format is all zeros The saved value of the program counter is the address of the instruction that would have been executed had the interrupt not been taken The appropriate interrupt vector is fetched and loaded into the program counter and normal instruction execution commences in the interrupt handling routine Priority level 7 is a special case Level 7 interrupts cannot be inhibited by the interrupt priority mask thus providing a nonmaskable interrupt capability An interrupt is generated each time the interrupt request level changes from some lower level to level 7 A level 7 interrupt may still be caused by the level comparison if the request level is a 7 and the processor priority is set to a lower level by an instruction 6 3 3 Uninitialized Interrupt An interrupting device provides an M68000 interrupt vector number and asserts data transfer acknowledge DTACK or asserts valid peripheral address VPA or auto vector AVEC or bus error BERR during an interrupt acknowledge cycle by the MC68000 If the vector register has not been initialized the responding M68000 Family peripheral provides vector number 15 the uninitialized interrupt vector This response conforms to a u
62. or equal to 50 pF subtract 5 ns from the value given in the maximum columns 2 Actual value depends on clock period 3 If 47 is satisfied for both DTACK and BERR 48 may be ignored In the absence of DTACK BERR is an asynchronous input using the asynchronous input setup time 47 4 For power up the MC68000 must be held in the reset state for 100 ms to allow stabilization of on chip circuitry After the system is powered up 56 refers to the minimum pulse width required to reset the processor 5 If the asynchronous input setup time 47 requirement is satisfied for DTACK the DTACK asserted to data setup time 31 requirement can be ignored The data must only satisfy the data in to clock low setup time 27 for the following clock cycle 6 When AS and R W are equally loaded 20 pc subtract 5 ns from the values given in these columns 7 The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK 8 The minimum value must be met to guarantee proper operation If the maximum value is exceeded BG may be reasserted 9 The falling edge of S6 triggers both the negation of the strobes AS and DS and the falling edge of E Either of these events can occur first depending upon the loading on each signal Specification 49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of E 10 245 ns for the MC68008 1
63. privileges is used by the operating system and other system software 2 1 1 Programmer s Model The user programmer s model see Figure 2 1 is common to all M68000 MPUs The user programmer s model contains 16 32 bit general purpose registers 20 07 0 A7 a 32 bit program counter and an 8 bit condition code register The first eight registers 00 07 are used as data registers for byte 8 bit word 16 bit and long word 32 bit operations The second set of seven registers AO A6 and the user stack pointer USP can be used as software stack pointers and base address registers In addition the address registers can be used for word and long word operations All of the 16 registers can be used as index registers MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 1 31 16 15 87 01 02 03 EIGHT DATA 04 REGISTERS D5 D6 07 31 16 15 0 A0 Al A2 SEVEN A3 ADDRESS a4 REGISTERS A5 AG USER STACK USP POINTER 31 0 COUNTER 7 STATUS Figure 2 1 User Programmer s Model 68000 68 000 68008 68010 2 1 2 Supervisor Programmer s Model The supervisor programmer s model consists of supplementary registers used in the supervisor mode The M68000 MPUs contain identical supervisor mode register resources which are shown in Figure 2 2 including the status register high order byte and the supervisor stack pointer SSP A7 31
64. space Because no assumptions can be made about the validity of register contents in particular the SSP neither the program counter nor the status register is saved The address in the first two words of the reset exception vector is fetched as the initial SSP and the address in the last two words of the reset exception vector is fetched as the initial program counter Finally instruction execution is started at the address in the program counter The initial program counter should point to the power up restart code The RESET instruction does not cause a reset exception it asserts the RESET signal to reset external devices which allows the software to reset the system to a known state and continue processing with the next instruction 6 3 2 Interrupts Seven levels of interrupt priorities are provided numbered from 1 7 All seven levels are available except for the 48 pin version for the MC68008 NOTE The MC68008 48 pin version supports only three interrupt levels 2 5 and 7 Level 7 has the highest priority Devices can be chained externally within interrupt priority levels allowing an unlimited number of peripheral devices to interrupt the processor The status register contains a 3 bit mask indicating the current interrupt priority and interrupts are inhibited for all priority levels less than or equal to the current priority An interrupt request is made to the processor by encoding the interrupt request levels 1 7 on the
65. the device and negates LDS and DS The device negates DTACK or BERR at this time STATES 8 11 MOTOROLA The bus signals are unaltered during 58 511 during which the arithmetic logic unit makes appropriate modifications to the data M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 4 7 STATE 12 STATE 13 STATE 14 STATE 15 STATE 16 STATE 17 STATE 18 STATE 19 The write portion of the cycle starts in 512 The valid function codes on 2 the address bus lines AS and R W remain unaltered During S13 no bus signals are altered On the rising edge of S14 the processor drives RWW low During S15 the data bus is driven out of the high impedance state as the data to be written are placed on the bus At the rising edge of S16 the processor asserts LDS or DS The processor waits for DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S16 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the close of S16 the processor inserts wait states full clock cycles until either DTACK or BERR is asserted During S17 no bus signals are altered During S18 no bus signals are altered On the falling edge of the clock entering S19 the processor negates AS LDS and DS As the clock rises at the end of S19 the processor places the address and data buses in the high impedance state an
66. the memory or from a peripheral device When the data is received the processor internally positions the byte appropriately The 8 bit operation must perform two or four read cycles to access a word or long word asserting the data strobe to read a single byte during each cycle The address bus in 8 bit operation includes AO which selects the appropriate byte for each read cycle Figure 4 1 and 4 2 illustrate the byte read cycle operation MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 4 1 BUS MASTER SLAVE ADDRESS THE DEVICE 1 SET RW TO READ 2 PLACE FUNCTION CODE ON 2 3 PLACE ADDRESS ON A23 A0 __ 4 ASSERT ADDRESS STROBE AS __ 5 ASSERT LOWER DATA STROBE LDS DS ON MC68008 INPUT THE DATA 1 DECODE ADDRESS 2 PLACE DATA ON 07 00 3 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK ACQUIRE THE DATA 1 LATCH DATA _ 2 NEGATE LDS DS FOR MC68008 3 NEGATE AS TERMINATE THE CYCLE 1 REMOVE DATA FROM 07 00 2 NEGATE DTACK START NEXT CYCLE Figure 4 1 Byte Read Cycle Flowchart 50 51 52 53 54 55 S6 57 50 S1 52 53 54 55 56 57 50 5152 53 54 w w w w 55 56 57 CLK AS DTACK gt lt gt lt gt WRITE 2 WAIT STATE READ READ Figure 4 2 Read and Write Cycle Timing Diagram 42 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA A bus cycle consists of eight states The various signals are asserted during specific states of
67. the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign MOTOROLA MC68000 8 16 32 MICROPROCESSORS USER S MANUAL 8 9 Table 8 12 Miscellaneous Instruction Execution Times 2130 E XG XT TRAPV UNLK Add effective address calculation time Table 8 13 Move Peripheral Instruction Execution Times Size Register Memory Memory Register 164 0 16 2 2 8 12 EXCEPTION PROCESSING EXECUTION TIMES Table 8 14 lists the timing data for exception processing The numbers of clock periods include the times for all stacking the vector fetch and the fetch of the first instruction of 8 10 68000 8 16 32 MICROPROCESSORS UISER S MANUAL MOTOROLA the handler routine The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 8 14 Exception Processing Execution Times TEN TE TE TIT adm TTE sas Add effective address calculation time The interrupt acknowledge cycle is assumed to take four clock periods ndicates the time from when RESET and HALT are first sampled as negated to when instruction ex
68. the version number is incorrect for this processor the RTE instruction is aborted and exception processing begins for a format error exception Since the stack pointer is not updated until the RTE instruction has successfully read all the stack data a format error occurring at this point does not stack new data over the previous bus error stack information Determine data accessibility If the long stack data is valid the MC68010 performs a read from the last word SP 56 of the long stack to determine data accessibility If this read is terminated normally the processor assumes that the remaining words on the stack frame are also accessible If a bus error is signaled before or during this read a bus error exception is taken After this read the processor must be able to load the remaining data without receiving a bus error therefore if a bus error occurs on any of the remaining stack reads the error becomes a double bus fault and the MC68010 enters the halted state M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA SECTION 7 8 BIT INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock CLK periods for the MC68008 and MC68HC001 MC68ECO00 in 8 bit mode In this data it is assumed that both memory read and write cycles consist of four clock periods A longer memory cycle causes the generation of wait states that must be added to the total instruction times
69. these two instructions as required to move the entire block or to move all nonzero words that precede a zero The MC68010 enters the loop mode automatically when the conditions for loop mode operation are met Entering the loop mode is transparent to the programmer The conditions are that the loop count and branch condition of the DBcc instruction must result in looping the branch displacement must be minus four and the branch must be to a one word loop mode instruction preceding the DBcc instruction The looped instruction and the first word of the DBcc instruction are each fetched twice when the loop is entered When the processor fetches the looped instruction the second time and determines that the looped instruction is a loop mode instruction the processor automatically enters the loop mode and no more instruction fetches occur until the count is exhausted or the loop condition is true In addition to the normal termination conditions for the loop several abnormal conditions cause the MC68010 to exit the loop mode These abnormal conditions are as follows Interrupts Trace Exceptions Reset Operations Bus Errors Any pending interrupt is taken after each execution of the DBcc instruction but not after each execution of the looped instruction Taking an interrupt exception terminates the loop mode operation loop mode operation can be restarted on return from the interrupt handler While the T bit is set a trace except
70. three interrupt request lines all lines negated indicates no interrupt request Interrupt requests arriving at the processor do not force immediate exception processing but the requests are made pending Pending interrupts are detected between instruction executions If the priority of the pending interrupt is lower than or equal to the current processor priority execution continues with the next instruction and the interrupt exception processing is postponed until the priority of the pending interrupt becomes greater than the current processor priority If the priority of the pending interrupt is greater than the current processor priority the exception processing sequence is started A copy of the status register is saved the privilege mode is set to supervisor mode tracing is suppressed and the processor priority level is set to the level of the interrupt being acknowledged The processor fetches the vector number from the interrupting device by executing an interrupt acknowledge cycle which displays the level number of the interrupt being acknowledged on the address bus If external logic requests an automatic vector the processor internally generates a vector number corresponding to the interrupt level number If external logic indicates a bus error the interrupt is considered spurious and the generated vector number references the spurious interrupt vector The processor then proceeds with the usual exception processing saving the format
71. version supports a 20 bit address that provides a 1 Mbyte address space the 52 pin version supports a 22 bit address that extends the address space to 4 Mbytes The 48 pin MC68008 contains a simple two wire arbitration circuit the 52 pin MC68008 contains a full three wire MC68000 bus arbitration control Both versions are designed to work with daisy chained networks priority encoded networks or a combination of these techniques A system implementation based on an 8 bit data bus reduces system cost in comparison to 16 bit systems due to a more effective use of components and byte wide memories and peripherals In addition the nonmultiplexed address and data buses eliminate the need for external demultiplexers further simplifying the system The large nonsegmented linear address space of the MC68008 allows large modular programs to be developed and executed efficiently A large linear address space allows program segment sizes to be determined by the application rather than forcing the designer to adopt an arbitrary segment size without regard to the application s individual requirements 13 MC68010 The MC68010 utilizes VLSI technology and is a fully implemented 16 bit microprocessor with 32 bit registers a rich basic instruction set and versatile addressing modes The vector base register VBR allows the vector table to be dynamically relocated 1 2 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 14 68 000 The
72. write cycles are shown in the previously described format The following notation applies in Table 9 17 Dn Data register operand Memory operand Table 9 17 Multiprecision Instruction Execution Times cc False cc True ADDX 284 1 264 1 36 6 2 2040 18 4 0 Mul 2440 SUBX E 28 e A gt 2 Source and destination ea are An for CMPM and for all others 9 11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Table 9 18 lists the timing data for miscellaneous instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 9 11 Table 9 18 Miscellaneous Instruction Execution Times Register Memory Destination Register _ we _ ae A WE UL n e aie i aoe ee wem o P ext a EC wowmecn m wowecn wes me wowmms m 1 owes me
73. 0 4 1 0 4 1 0 1221 ey 2 21 16 3 1 4 1 0 4 1 0 2 21 4 2 1 2 2 1 16 3 1 8 2 0 8 2 0 12 2 1 12 2 1 12 2 1 6 3 1 8 3 1 6 3 1 20 4 1 8 2 0 8 2 0 12 2 1 12 2 1 1221 16 3 1 18 3 1 16 3 1 20 4 1 10 2 0 10 2 0 14 2 1 1421 1421 18 3 1 20 3 1 18 3 1 22 4 1 116 An 12 3 0 12 3 0 16 3 1 16 3 1 16 3 1 20 4 1 22 4 1 20 4 1 24 5 1 Xn 14 3 0 14 3 0 18 3 1 18 3 1 18 3 1 22 4 1 24 4 1 22 4 1 26 5 1 xxx W 12 3 0 12 3 0 16 3 1 16 3 1 16 3 1 20 4 1 22 4 1 20 4 1 24 5 1 xxx L 16 4 0 16 4 0 20 4 1 20 4 1 20 4 1 24 5 1 26 5 1 24 5 1 28 6 1 816 PC 12 3 0 12 3 0 16 3 1 16 3 1 16 3 1 20 4 1 22 4 1 20 4 1 24 5 1 dg PC Xn 14 3 0 14 3 0 18 3 1 18 3 1 18 3 1 22 4 1 24 4 1 22 4 1 26 5 1 lt data gt 8 2 0 8 2 0 12 2 1 12 2 1 12 2 1 16 3 1 18 3 1 16 3 1 20 4 1 size of the index register Xn does not affect execution time Table 9 3 Move Byte and Word Instruction Loop Mode Execution Times Loop Continued Loop Terminated Valid Count cc False Valid count cc True Expired Count Destination Dn 10 0 1 18 2 1 18 2 1 16 2 1 16 2 1 0 0 1 1090 18 2 1 18 2 1 16 2 1 16 2 1 141 1 20 3 1 20 3 1 18 3
74. 0 2 0 Address Register Indirect with Displacement 8 2 0 12 3 0 816 Xn Program Counter Indirect with Index 10 2 0 14 3 0 lt data gt Immediate 4 1 0 8 2 0 size of the index register Xn does not affect execution time 8 2 MOVE INSTRUCTION EXECUTION TIMES Tables 8 2 and 8 3 list the numbers of clock periods for the move instructions The totals include instruction fetch operand reads and operand writes The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format Table 8 2 Move Byte and Word Instruction Execution Times Destination Le me en 4 1 0 an 4 1 0 8 2 0 8 2 0 lt data gt 8 2 0 8 2 0 size of the index register Xn does not affect execution time 8 2 68000 8 16 32 MICROPROCESSORS UISER S MANUAL MOTOROLA Table 8 3 Move Long Instruction Execution Times Destination _ Dn An Am dg An xm cooo 4 1 0 4 1 0 12 1 2 12 1 2 12 1 2 1622 1928 2 2 20 3 2 4 1 0 4 1 0 12 1 2 12 1 2 12 1 2 6 2 2 8 2 2 6 2 2 20 3 2 12 3 0 12 3 0 20 3 2 20 3 2 20 3 2 4 4 2 6 4 2 4 4 2 28 5 2 12 3 0 12 3 0 20 3 2 20 3 2 20 3 2 24 4 2 26 4 2 24 4 2 28 5 2 An 14 3 0 14 3 0 22 3 2 22 3 2 22
75. 00 OR 015 08 2 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK TERMINATE OUTPUT TRANSFER 1 NEGATE UDS OR LDS 2 NEGATE AS 3 REMOVE DATA FROM 07 0008 D15 D8_ 4 SET RW TO READ TERMINATE THE CYCLE 1 NEGATE DTACK START NEXT CYCLE Figure 5 8 Read Modify Write Cycle Flowchart MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 57 50 51 52 53 54 55 56 57 58 59 510 S11 512 513 514 515 516 517 518 519 CLK s RAV Booo S PNI j INDIVISIBLE CYCLE gt Figure 5 9 Read Modify Write Cycle Timing Diagram The descriptions of the read modify write cycle states are as follows STATE 0 read cycle starts in 50 The processor places valid function codes 2 and drives R W high to identify a read cycle STATE 1 Entering S1 the processor drives a valid address on the address bus STATE 2 On the rising edge of S2 the processor asserts AS and UDS or LDS STATE 3 During S3 no bus signals are altered STATE 4 During S4 the processor waits for a cycle termination signal DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S4 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the end of S4 the processor inserts wait states full clock cycles until either or BERR is asserted STATE 5 During S5 no bus signals are altered
76. 1 18 2 2 22 3 1 22 3 1 24 3 1 20 3 1 20 3 1 22 3 1 Word Word 161 16 1 1 18 2 2 2231 22 3 1 24 3 1 2008 1 20 3 1 22 3 1 Word 12 1 0 12 1 0 14 1 0 18 3 0 18 3 0 20 3 0 16 3 0 16 3 0 18 3 0 Word 9 6 SHIFT ROTATE INSTRUCTION EXECUTION TIMES Tables 9 12 and 9 13 list the timing data for the shift and rotate instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 9 12 Shift Rotate Instruction Execution Times Meme emo emo 1 tong effective address calculation time n is the shift or rotate count Word only 9 8 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 9 13 Shift Rotate Instruction Loop Mode Execution Times Loop Continued Loop Terminated Valid Count cc False Valid Count cc True Expired Count Si Ame am am Ame instruction 18 1 1 24 3 1 24 3 1 22 3 1 22 3 1 9 7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES Table 9 14 lists the timing data for the bit manipulation instructions The total numb
77. 1 18 3 1 1417 1417 6 1 1 20 3 1 20 3 1 18 3 1 18 3 1 0 3 1 1617 16 1 1 2231 22 3 1 2031 20 3 1 2 3 1 Word only MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 9 3 Table 9 4 Move Long Instruction Execution Times Destination m An Am Ani An dg An 0 4 1 0 4 1 0 12 1 2 12 1 2 14 1 2 ipod 16 2 2 20 3 2 4 1 0 4 1 0 12 1 2 12 1 2 14 1 2 6 2 2 8 2 2 6 2 2 20 3 2 12 3 0 12 3 0 20 3 2 20 3 2 20 3 2 4 4 2 6 4 2 4 4 2 28 5 2 12 3 0 12 3 0 20 3 2 20 3 2 20 3 2 24 4 2 26 4 2 24 4 2 28 5 2 An 14 3 0 14 3 0 22 3 2 22 3 2 22 3 2 26 4 2 28 4 2 26 4 2 30 5 2 916 An 16 4 0 16 4 0 24 4 2 24 4 2 24 4 2 28 5 2 30 5 2 28 5 2 32 6 2 dg 18 4 0 18 4 0 26 4 2 26 4 2 26 4 2 30 5 2 32 5 2 30 5 2 34 6 2 16 4 0 16 4 0 24 4 2 24 4 2 24 4 2 28 5 2 30 5 2 28 5 2 32 6 2 xxx L 20 5 0 20 5 0 28 5 2 28 5 2 28 5 2 32 6 2 34 6 2 32 6 2 36 7 2 816 16 4 0 16 4 0 24 4 2 24 4 2 24 4 2 28 5 2 30 5 2 28 5 2 32 5 2 dg PC 18 4 0 18 4 0 26 4 2 26 4 2 26 4 2 30 5 2 32 5 2 30 5 2 34 6 2 lt data gt 12 3 0 12 3 0 20 3 2 20 3 2 20 3 2 24 4 2 26 4 2 24 4 2 28 5 2
78. 1 50 ns for the MC68008 12 50 ns for the MC68008 499 50 54 Low to Data Out Invalid 47 4823 499 50 51 53 54 55 564 57 587 N En Co nm 1 10 12 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA gt lt gt lt 23 0 LDS 005 RW DTACK DATA IN BERR BR NOTE 2 HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Setup time for the asynchronous inputs IPL2 IPLO and AVEC 47 guarantees their recognition at the next falling edge of the clock 2 BR need fall at this time only to insure being recognized at the end of the bus cycle 3 Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 V and 2 0 V Figure 10 4 Read Cycle Timing Diagram Applies To All Processors E xcept The MC68EC 000 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 13 CLK FC2 FCO A23 Al LDS UDS RAW DTACK DATA OUT HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Timing measurements are referenced to and from a low volt
79. 1 13 11 14 11 15 1 2 B 4 B 5 B 6 LIST OF ILLUSTRATIONS Concluded Page Title Number Bus Arbitration eta 10 18 Bus Arbitration 10 19 Bus Arbitration Timing ldle 2200 10 20 Bus Arbitration Timing Active Bus 10 21 Bus Arbitration Timing Multiple Bus 10 22 68 000 Read Cycle Timing Diagram 10 26 MC68ECO000 Write Cycle Timing 10 27 68 000 Bus Arbitration Timing Diagram 10 29 64 Pin D al My DIT 11 2 68 Lead i ii rio I p E 11 3 68 Lead Quad nena rua 11 4 Quad Paesi ie i uen CAL n 11 5 48 Pin Dual In Line erit iet tea 11 6 64 Lead Quad dues Eee reu 11 7 740 03 SU T s dana eie isa rec n etat RR DR a MER once 11 8 Gase 767 02 ous Sedem orc oie oh DD e DE 11 9 Case 746 01 LC Suffix 11 10 ASG
80. 14 Psy 2 12 10 55 40 0 25 70 85 110 125 AMBIENT TEMPERATURE TA Figure 10 1 MC68000 Power Dissipation vs Ambient Temperature Not Applicable to 68 000 68 001 68 000 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 3 Table 10 1 Power Dissipation and Junction Temperature vs Temperature 0JC20J A Package TA Range 9Jc W Ty Ty C W eran T A Max D TAM 0 to 70 C 15 40 C to 85 C 15 0 to 85 C 15 ie 103 0 C to 70 C 0 C to 70 C 40 C to 85 C 0 C to 85 C 5 1 2 NOTE Table does not include values MC68000 126 Does not apply to the MC68HC000 MC68HC001 68 00 Table 10 2 Power Dissipation and Junction Temperature vs Temperature 9 99 Range Pp W Ty C Pp W Ty Min vr 0 C to 70 C 23 40 C to 85 C 14 is Td 0 C to 85 C 15 23 1 2 occ s 15 0 C to 70 C 33 1 5 23 1 2 40 C to 85 C 33 14 1 2 0 C to 85 C 1 2 NOTE Table does not include values the MC68000 12F Does not apply to the MC68HC000 MC68HC001 and 68 00 Values for thermal resistance presented in this manual unless estimated were derived using the procedure described in Motorola Reliability Report 7843 Thermal Resistance Measurement Method for
81. 16 1 1 24 3 0 22 3 0 22 3 1 22 3 0 20 3 0 20 3 1 Word 22 2 0 20 2 0 24 2 2 28 4 0 26 4 0 30 4 2 26 4 0 24 4 0 28 4 2 Word or long word only ea may be An or only Add two clock periods to the table value if ea is MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 9 5 9 4 IMMEDIATE INSTRUCTION EXECUTION TIMES The numbers of clock periods shown in Table 9 8 include the times to fetch immediate operands perform the operations store the results and read the next operation The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign In Tables 9 8 the following notation applies Immediate operand Dn Data register operand An Address register operand Memory operand Table 9 8 Immediate Instruction Execution Times see m aan wews e ow e el D o m Cewa 20182 sm ewa e 20132 Add effective address calculation time Word only 9 5 SINGLE OPERAND I
82. 3 2 26 4 2 28 4 2 26 4 2 30 5 2 916 16 4 0 16 4 0 24 4 2 24 4 2 24 4 2 28 5 2 30 5 2 28 5 2 32 6 2 08 m Xn 18 4 0 18 4 0 26 4 2 26 4 2 26 4 2 30 5 2 32 5 2 30 5 2 34 6 2 16 4 0 16 4 0 24 4 2 24 4 2 24 4 2 28 5 2 30 5 2 28 5 2 32 6 2 20 5 0 20 5 0 28 5 2 28 5 2 28 5 2 32 6 2 34 6 2 32 6 2 36 7 2 16 4 0 16 4 0 24 4 2 24 4 2 24 4 2 28 5 2 30 5 2 28 5 2 32 5 2 a Xn 18 4 0 18 4 0 26 4 2 26 4 2 26 4 2 30 5 2 32 5 2 30 5 2 34 6 2 lt data gt 12 3 0 12 3 0 20 3 2 20 3 2 20 3 2 24 4 2 26 4 2 24 4 2 28 5 2 size of the index register Xn does not affect execution time 8 3 STANDARD INSTRUCTION EXECUTION TIMES The numbers of clock periods shown in Table 8 4 indicate the times required to perform the operations store the results and read the next instruction The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign In Table 8 4 the following notation applies An Address register operand Dn Data register operand ea operand specified by an effective address Memory ef
83. 52 pin version supports a 22 bit address 21 0 extending the address space to 4 Mbytes During an interrupt acknowledge cycle the interrupt level number is placed on lines 1 2 Lines AO and 4 through the most significant address line are driven to logic high 3 2 DATA BUS D15 D0 MC68008 07 00 This bidirectional three state bus is the general purpose data path It is 16 bits wide in the all the processors except the MC68008 which is 8 bits wide The bus can transfer and accept data of either word or byte length During an interrupt acknowledge cycle the external device supplies the vector number on data lines 07 00 The 68 000 and 68 001 use D7 DO 8 bit mode D15 D8 are undefined 3 3 ASYNCHRONOUS BUS CONTROL Asynchronous data transfers are controlled by the following signals address strobe read write upper and lower data strobes and data transfer acknowledge These signals are described in the following paragraphs Address Strobe AS This three state signal indicates that the information on the address bus is a valid address Read Write R W This three state signal defines the data bus transfer as a read or write cycle The R W signal relates to the data strobe signals described in the following paragraphs Upper And Lower Data Strobes UDS 105 These three state signals and R W control the flow of data on the data bus Table 3 1 lists the combinations of these s
84. AND INSTRUCTION EXECUTION TIMES Table 7 7 lists the timing data for the single operand instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 7 5 Table 7 7 Single Operand Instruction Execution Times Size Register CLR Byte 8 2 0 12 2 1 Word 8 2 0 16 22 Long 10 2 0 4 2 4 NBCD 10 2 0 12 2 1 Byte 8 2 0 Word 800 Long 10 2 0 Byte 8 2 0 Word 220 Long 10 20 Byte 8 2 0 Word MN Long 10 2 0 Byte False 8 2 0 Byte True 10 2 8 2 0 Add effective address calculation time 7 6 SHIFT ROTATE INSTRUCTION EXECUTION TIMES Table 7 8 lists the timing data for the shift and rotate instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 7 8 Shift Rotate Instruction Execution Times Sze ASR ASL Byte 10 2 2
85. CK or BERR at this time NOTE During an active bus cycle VPA and BERR are sampled on every falling edge of the clock beginning with S4 and data is latched on the falling edge of S6 during a read cycle The bus cycle terminates in S7 except when BERR is asserted in the absence of DTACK In that case the bus cycle terminates one clock cycle later in S9 5 1 2 Write Cycle During a write cycle the processor sends bytes of data to the memory or peripheral device If the instruction specifies a word operation the processor issues both UDS and LDS and writes both bytes When the instruction specifies a byte operation the processor uses the internal AO bit to determine which byte to write and issues the appropriate data strobe When the AO bit equals zero UDS is asserted when the AO bit equals one LDS is asserted 54 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA The word and byte write cycle timing diagram and flowcharts in Figures 5 5 5 6 and 5 7 applies directly to the MC68000 the 68 000 the MC68HCO001 in 16 bit mode the 68 000 in 16 bit mode and the 68010 BUS MASTER SLAVE ADDRESS THE DEVICE 1 PLACE FUNCTION CODE ON 2 2 PLACE ADDRESS A23 A1 3 ASSERT ADDRESS STROBE AS 4 SET R W TO WRITE 5 PLACE DATA ON D15 D0 M 6 ASSERT UPPER DATA STROBE UDS AND LOWER DATA STROBE LDS INPUT THE DATA 1 DECODE ADDRESS 2 STORE DATA ON D15 D0 3 ASS
86. Capacitance is periodically sampled rather than 100 tested Power Dissipation 10 8 AC ELECTRICAL SPECIFICATIONS CLOCK TIMING See Figure 10 3 Applies To All Processors Except The 68 00 Characteristic C eony opea 40 Clock Pulse Width Measured from 1 5 V to 1 5 V for 12F These specifications represent an improvement over previously published specifications for the 8 10 and 12 5 MHz MC68000 and are valid only for product bearing date codes of 8827 and later This frequency applies only to 68 000 and 68 00 parts 10 8 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 10 9 MC68008 AC ELECTRICAL SPECIFICATIONS CLOCK TIMING see Figure 10 3 Clock Rise and Fall Times 10 These specifications represent an improvement over previously published specifications for the 8 and 10 2 MC68008 and are valid only for product bearing date codes of 8827 and later NOTE Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0 8 V and 2 0 V Figure 10 3 Clock Input Timing Diagram MOTOROLA 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 9 10 10 ELECTRICAL SPECIFICATIONS READ AND WRITE CYCLES 5 0 VDC 5
87. DDX Source Destination X Destination ADDX Dy Dx ADDX Ay AN Source A Destination Destination AND ea Dn AND Dn ea ANDI Immediate Data A Destination Destination ANDI data ea ANDI to CCR Source A CCR CCR ANDI lt data gt CCR ANDI to SR If supervisor state ANDI lt data gt SR then Source A SR 58 else TRAP ASL Destination Shifted by count Destination ASd Dx Dy ASd lt data gt Dy ASd lt ea gt If condition true then PC PC Bec lt label gt BCHG lt number gt of Destination gt 2 BCHG Dn lt ea gt lt number gt of Destination gt bit number gt of Destination BCHG lt data gt lt ea gt BCLR lt bit number gt of Destination gt 2 BCLR Dn lt ea gt 0 bit number of Destination BCLR lt data gt lt ea gt Run breakpoint acknowledge cycle BKPT lt data gt TRAP illegal instruction PC d PC BRA lt label gt BSET bit number of Destination 2 BSET Dn lt ea gt 1 bit number of Destination BSET data ea 5 4 gt 5 PC SP PC d gt BSR lt label gt BS BIST bit number gt of Destination Z BTST Dn lt ea gt BTST lt data gt lt ea gt R If Dn lt 0 or Dn gt Source then TRAP CHK lt ea gt Dn CL P D D If condition false then Dn 1 DBcc lt
88. EGATE BUS GRANT BG REARBITRATE OR RESUME PROCESSOR OPERATION Figure 5 14 2 Wire Bus Arbitration Cycle Flowchart BGACK PROCESSOR DMA DEVICE 3 gt PROCESSOR gt lt DMA DEVICE Figure 5 15 3 Wire Bus Arbitration Timing Diagram Not Applicable to 48 MC68008 or 68 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 513 50 52 54 56 50 52 54 56 50 52 54 56 50 52 54 56 CLK II E a 2 GENES L GNU unnm PROCESSOR gt lt DMA DEVICE gt lt PROCESSOR gt lt DMA DEVICE Figure 5 16 2 Wire Bus Arbitration Timing Diagram The timing diagram in Figure 5 15 shows that the bus request is negated at the time that an acknowledge is asserted This type of operation applies to a system consisting of a processor and one other device capable of becoming bus master In systems having several devices that can be bus masters bus request lines from these devices can be wire ORed at the processor and more than one bus request signal could occur The bus grant signal is negated a few clock cycles after the assertion of the bus grant acknowledge signal However if bus requests are pending the processor reasserts bus grant for another request a few clock cycles after bus grant for the previous request is negated In response to this additional assertion of bus grant external arbitration circuitry selects the next bus ma
89. ERT DATA TRANSFER ACKNOWLEDGE DTACK TERMINATE OUTPUT TRANSFER 1 NEGATE UDS AND LDS 2 NEGATE AS 3 REMOVE DATA FROM 015 00 4 SET R W TO READ TERMINATE THE CYCLE 1 NEGATE DTACK START NEXT CYCLE Figure 5 5 Word Write Cycle Flowchart BUS MASTER SLAVE ADDRESS THE DEVICE 1 PLACE FUNCTION CODE ON FC2 FCO 2 PLACE ADDRESS ON 23 1 _ 3 ASSERT ADDRESS STROBE AS 4 SETR W TO WRITE 5 PLACE DATA ON D0 D7 OR D15 D8 ACCORDING INTERNAL A0 __ 6 ASSERT UPPER DATA STROBE UDS OR LOWER DATA STROBE LDS INPUT THE DATA 1 DECODE ADDRESS ae 2 STORE DATA ON 07 00 IF LDS 15 ASSERTED STORE DATA ON D15 D8 IF UDS IS ASSERTED 3 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK BASED ON INTERNAL 0 TERMINATE OUTPUT TRANSFER 1 NEGATE UDS AND LDS 2 NEGATE AS 3 REMOVE DATA FROM D7 D0 OR 015 08 _ 4 SET TO READ TERMINATE THE CYCLE 1 NEGATE DTACK START NEXT CYCLE Figure 5 6 Byte Write Cycle Flowchart MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 5 CLK FC2 FCO 50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 57 45 25 005 105 RW DTACK D15 D8 D7 D0 a 3 OO INTERNAL SIGNAL ONLY I WORD WRITE gt lt 000 BYTE WRITE gt e EVEN BYTE WRITE gt Figure 5 7 Word and Byte Write Cycle Timing Diagram The descriptions of the eight states of
90. L Figure 3 1 Input and Output Signals 68000 68 000 and MC68010 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 3 1 ADDRESS BUS DATA BUS A23 A0 D15 D0 ASYNCHRONOUS r BUS CONTROL BUS ARBITRATION CONTROL _ INTERRUPT CONTROL Figure 3 2 Input and Output Signals GND 2 CLK FCO ROSTATUS FC2 6800 PERIPHERAL CONTROL VPA SYSTEM RESET CONTROL HALT GND 2 CLK FCO FC2 BERR SYSTEM RESET CONTROL HALT MODE MC68EC000 MC68HCO01 ADDRESS BUS DATA BUS A23 A0 015 00 ASYNCHRONOUS BUS CONTROL BUS ARBITRATION CONTROL INTERRUPT CONTROL Figure 3 3 Input and Output Signals 3 2 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 68 00 Vecl2 GND 2 A19 A0 CLK DATA BUS gt 07 00 FCO STATUS FC2 RW ASYNCHRONOUS bs I BUS DS MC6808 gt TACK CONTROL MC6800 u PERIPHERAL VPA BR BUS CONTROL BG I ARBITRATION CONTROL BERR SYSTEM CONTROL IPL2 PLO INTERRUPT HALT IPLI CONTROL Figure 3 4 Input and Output Signals MC68008 48 Pin Version Vcc ADDRESS GND 2 BUS A21 A0 CLK DATA BUS gt 07 00 FCO AS PROCESSORS RW ASYNCHRONOUS STATUS FC2 DS S LC K ceao0a BU CONTROL MC6800 a BR BUS PE
91. MP JSR LEA PEA and MOVEM Instruction Execution Times Instruction size Am 816 Xny m wen wes wen wes wem we wea zem wer mea wee mee Re amp 49 829 200 820 800 100 wee 08 22 22 mo Word 12 4n 12 4n 16 4n 18 4n 16 4n 20 4n 16 4n 18 4n MR 3 0 3 n 0 4 0 4 0 4 0 5 n 0 4 n 0 4 n 0 Long 24 8n 12 8n 16 8n 18 8n 16 8n 20 8n 16 8n 18 8n 3 2 0 3 2n 0 4 2 0 4 2 0 4 2 0 5 2 0 4 2 0 4 2 0 8 4 8 4 12 4 14 4 12 4 16 4 RM 2 n 2 n 3 n 3 n 3 n 4 n Long 8 8n 8 8 12 8n 14 8n 12 8n 16 8n 2 2n 2 2n 3 2n 3 2n 3 2n 4 2n MOVES Byte 18 3 0 3 0 20 3 0 20 4 0 24 4 0 20 4 0 24 5 0 ROM L E R M Word n is the number of registers to move The size of the index register Xn does not affect the instruction s execution time 9 10 MULTIPRECISION INSTRUCTION EXECUTION TIMES Table 9 17 lists the timing data for multiprecision instructions The numbers of clock periods include the times to fetch both operands perform the operations store the results 9 10 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA and read the next instructions The total number of clock periods the number of read cycles and the number of
92. NEGATED INTERNAL BR SAMPLED BR NEGATED BGACK cR EE SENE RW DTACK PROCESSOR lt ALTERNATE BUS MASTER PROCESSOR gt Figure 5 24 2 Wire Bus Arbitration Timing Diagram Special Case 5 4 BUS ERROR AND HALT OPERATION In a bus architecture that requires a handshake from an external device such as the asynchronous bus used in the M68000 Family the handshake may not always occur A bus error input is provided to terminate a bus cycle in error when the expected signal is not asserted Different systems and different devices within the same system require different maximum response times External circuitry can be provided to assert the bus error signal after the appropriate delay following the assertion of address strobe In a virtual memory system the bus error signal can be used to indicate either a page fault or a bus timeout An external memory management unit asserts bus error when the page that contains the required data is not resident in memory The processor suspends execution of the current instruction while the page is loaded into memory The MC68010 pushes enough information on the stack to be able to resume execution of the instruction following return from the bus error exception handler MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 23 The MC68010 also differs from the other microprocessors described in this manual re
93. NSTRUCTION EXECUTION TIMES Table 8 7 lists the timing data for the shift and rotate instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign 8 6 Table 8 7 Shift Rotate Instruction Execution Times Instruction Size Register Memory ASR ASL _ LSR LSL eem Add effective address calculation time for word operands nis the shift count MC68000 8 16 32 MICROPROCESSORS UISER S MANUAL MOTOROLA 8 7 MANIPULATION INSTRUCTION EXECUTION TIMES Table 8 8 lists the timing data for the bit manipulation instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 8 8 Bit Manipulation Instruction Execution Times ene sw m an 2 2 1 2 2 1 2 2 1 8 2 0 Lum oe Add effective address calculation time Indicates maximum value data
94. NSTRUCTION EXECUTION TIMES Tables 9 9 9 10 and 9 11 list the timing data for the single operand instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign 2 2 1 0 3 1 8 2 0 2 3 0 9 6 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 9 9 Single Operand Instruction Execution Times en ulii x ox am im Pea avo _ Add effective address calculation time nonfetching effective address calculation time Table 9 10 Clear Instruction Execution Times e pe ee ee eer 040 0 sum isee ioen size of the index register Xn does not affect execution time MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 9 7 Table 9 11 Single Operand Instruction Loop Mode Execution Times Loop Continued Loop Terminated Valid Count cc False Valid Count cc True Expired Count size am me am Ame am Ame am 1001 10 0 1 12 0 1 18 2 1 18 2 1 20 2 0 16 2 1 16 2 1 18 2 1 Word 1617 16 1
95. OTE d is direction L or R TRAP lt vector gt 2 14 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA SECTION 3 SIGNAL DESCRIPTION This section contains descriptions of the input and output signals The input and output signals can be functionally organized into the groups shown in Figure 3 1 for the MC68000 the 68 000 and MC68010 Figure 3 2 for the 68 001 Figure 3 3 for the 68 000 Figure 3 4 for the MC68008 48 pin version and Figure 3 5 for the MC68008 52 pin version The following paragraphs provide brief descriptions of the signals and references where applicable to other paragraphs that contain more information about the signals NOTE The terms assertion and negation are used extensively in this manual to avoid confusion when describing a mixture of active low and active high signals The term assert or assertion is used to indicate that a signal is active or true independently of whether that level is represented by a high or low voltage The term negate or negation is used to indicate that a signal is inactive or false Vee 2 ADDRESS BUS gt CLK DATABUS 015 00 x u 2 RW ASYNCHRONOUS FCO UDS BUS PROCESSOR LDS CONTROL STATUS FC2 __DTACK 6800 E PERIPHERAL BG I ARBITRATION CONTROL VPA BGACK CONTROL SYSTEM BERR ET RESET INTERRUPT CONTROL lt gt gt HALT iPL2 CONTRO
96. OWER ADDRESSES BYTE 1 LS BYTE BYTE 0 MS BYTE BYTE 1 LS BYTE HIGHER ADDRESSES 1 LONG WORD 2 WORDS 4 BYTES 32 BITS LOWER ADDRESSES HIGH ORDER WORD LONG WORD 0 LOW ORDER WORD HIGH ORDER WORD LONG WORD 1 LOW ORDER WORD HIGHER ADDRESSES Figure 2 7 Memory Data Organization of the MC68008 2 5 INSTRUCTION SET SUMMARY Table 2 2 provides an alphabetized listing of the M68000 instruction set listed by opcode operation and syntax In the syntax descriptions the left operand is the source operand and the right operand is the destination operand The following list contains the notations used in Table 2 2 2 8 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA Notation for operands PC Program counter SR Status register V Overflow condition code Immediate Data Immediate data from the instruction Source Source contents Destination Destination contents Vector Location of exception vector inf Positive infinity inf Negative infinity fmt Operand data format byte B word W long L single S double D extended X or packed P FPm One of eight floating point data registers always specifies the source register FPn One of eight floating point data registers always specifies the destination register Notation for subfields and qualifiers bit of lt gt Selects a single bit of the operand lt ea
97. RATION CONTROL All asynchronous bus arbitration signals to the processor are synchronized before being used internally As shown in Figure 5 17 synchronization requires a maximum of one cycle of the system clock assuming that the asynchronous input setup time 47 defined in Section 10 Electrical Characteristic has been met The input asynchronous signal is sampled on the falling edge of the clock and is valid internally after the next falling edge MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 515 INTERNAL SIGNAL VALID EXTERNAL SIGNAL SAMPLED CLK BR EXTERNAL M lt BR iNTERNAL Figure 5 17 External Asynchronous Signal Synchronization Bus arbitration control is implemented with a finite state machine State diagram a in Figure 5 18 applies to all processors using 3 wire bus arbitration and state diagram b applies to processors using 2 wire bus arbitration in which BGACK is permanently negated internally or externally The same finite state machine is used but it is effectively a two state machine because BGACK is always negated In Figure 5 18 input signals R and A are the internally synchronized versions of BR and BGACK The BG output is shown as G and the internal three state control signal is shown as T If T is true the address data and control buses are placed in the high impedance state when AS is negated All signals are shown in positive logic active high regardles
98. RIPHERAL VPA BG I ARBITRATION CONTROL BGACK CONTROL SYSTEM BERR IPLO CONTROL RESET INTERRUPT HALT CONTROL Figure 3 5 Input and Output Signals MC68008 52 Pin Version 3 1 ADDRESS BUS 23 1 This 23 bit unidirectional three state bus is capable of addressing 16 Mbytes of data This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles and breakpoint cycles During interrupt acknowledge cycles address lines A2 and provide the level number of the interrupt being acknowledged and address lines 23 4 are driven to logic high MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 33 Address Bus 23 0 This 24 bit unidirectional three state bus is capable of addressing 16 Mbytes of data This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles and breakpoint cycles During interrupt acknowledge cycles address lines A1 A2 and A3 provide the level number of the interrupt being acknowledged and address lines 23 4 and 0 are driven to logic high In 16 Bit mode 0 is always driven high MC68008 Address Bus The unidirectional three state buses in the two versions of the MC68008 differ from each other and from the other processor bus only in the number of address lines and the addressing range The 20 bit address 19 0 of the 48 pin version provides a 1 Mbyte address space the
99. TION TIMES The numbers of clock periods shown in Table 7 5 indicate the times required to perform the operations store the results and read the next instruction The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 7 3 In Table 7 5 the following notation applies An Address register operand Dn Data register operand ea operand specified by an effective address Memory effective address operand Table 7 5 Standard Instruction Execution Times instruction Size lt gt opDn lt M gt _ ADD ADDA 12 2 0 10 2 0 8 2 0 8 2 0 12 2 0 12 2 0 10 2 0 Add effective address calculation time Indicates maximum base value added to word effective address time The base time of 10 clock periods is increased to 12 if the effective address mode is register direct or immediate effective address time should also be added Only available effective address mode is data register direct DIVS The divide algorithm used by the MC68008 provides less than 10 difference between the best a
100. USP An USP MOVE An USP else TRAP If supervisor state then Rc Rn or Rn gt MOVEC Rn Rc else TRAP MOVEM Registers Destination MOVEM register list ea Source Registers MOVEM lt ea gt register list MOVEP Source Destination MOVEP Dx d Ay MOVEP d Ay Dx MOVEQ Immediate Data Destination MOVEO data Dn MOVES If supervisor state MOVES Rn lt ea gt then Rn Destination DFC or Source SFC gt Rn MOVES lt ea gt Rn else TRAP MULS Source x Destination Destination MULS W lt ea gt Dn 16 x 16 gt 32 MULU Source x Destination Destination MULU W ea Dn 16 x 16 gt 32 NBCD 0 Destination 9 X Destination NBCD lt ea gt NEGX 0 Destination X Destination NEGX lt ea gt NO Source V Destination Destination OR lt ea gt Dn OR Dn ea Immediate Data V Destination Destination ORI lt data gt lt ea gt ORI to CCR Source V gt CCR ORI data CCR ORI to SR supervisor state ORI data SR then Source V SR gt SR else TRAP 5 4 5 If supervisor state RESET then Assert RESET Line else TRAP ROL ROR Destination Rotated by count Destination ROd lt data gt Dy ROd lt ea gt ROXL Destination Rotated with X by count Destination ROXR ROXd lt data gt Dy ROXd lt ea gt RTD SP
101. addressing mode only 8 8 CONDITIONAL INSTRUCTION EXECUTION TIMES Table 8 9 lists the timing data for the conditional instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format MOTOROLA Table 8 9 Conditional Instruction Execution Times e E T Displacement Taken Taken e BRA MC68000 8 16 32 MICROPROCESSORS USER S MANUAL ar 8 7 8 9 JMP JSR LEA PEA INSTRUCTION EXECUTION TIMES Table 8 10 lists the timing data for the jump JMP jump to subroutine JSR load effective address LEA push effective address PEA and move multiple registers MOVEM instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format Table 8 10 JMP JSR LEA PEA and MOVEM Instruction Execution Times we hm son com mc we wan wen sn wee mes wee wen mea tex em wes MOVEM Word 12 4 12 4 16 4n 18 4 16 4 20 4 16 4 18 4 4 0 3 n 0 3 n 0 4 0 4 0 4 0 5 n 0
102. age of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 V and 2 0 V 2 Because of loading variations R W may be valid after AS even though both are initiated by the rising edge of S2 specification 420A Figure 10 5 Write Cycle Timing Diagram Applies To All Processors Except The MC68EC 000 10 14 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 10 11 ELECTRICAL SPECIFICATIONS MC68000 TO M6800 PERIPHERAL Vcc 5 0 5 GND 0 TA TO Ty refer to figures 10 6 Applies To All Processors Except The MC68ECO000 Low to AS DS Clock Low to AS DS Negated 181 Clock High to R W High Read Clock High to R W Low Write Clock Low to Data Out Valid Write Data In Valid to Clock Low 10 Setup Time on Read AS DS Negated to Data In Invalid Hold Time on Read ob tow io WHR Assorted 70 gt gt o o 3 o Low to E Teanstion 55 E ovea e gt n Asserted to High 150 AS DS Negated to VPA Negated gt o E Low to Control Address Bus Invalid Address Hold Time Asynchronous Input Setup 10 Time These specifications represent improvement over previously published specifications for the 8 10 and 12 5 MHz MC68000 and are valid only for pro
103. aranteed DC operation of the device as specified in the DC electrical characteristics MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 5 10 6 DRIVE TO24V BCLK OUTPUTS 1 24V INPUTS 2 DRIVETO gt 0 5 V 20V RSTI 3 NOTES 1 This output timing is applicable to all parameters specified relative to the rising edge of the clock 2 This input timing is applicable to all parameters specified relative to the rising edge of the clock 3 This timing is applicable to all parameters specified relative to the negation of the RESET signal LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification E Mode select setup time to RESET negated F Mode select hold time from RESET negated Figure 10 2 Drive Levels and Test Points for AC Specifications M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 10 6 68000 68008 68010 ELECTRICAL CHARACTERISTICS VCc 5 0 VDC 5 GND 0 VDC TA TL TO TH Input Low Voltage Input Leakage Current BERR BGACK BR DTACK CLK IPLO IPL2 VPA 5 25 V HALT RESET Three State Off State Input Current 5 1 23 DO D15 FCO FC2 2 4 V 0 4 V LDS R W UDS VMA Output High Voltage 400 uA 400 nA AS A1 A23 BG D0 D15 FCO FC2 LDS R W UDS VMA Output Low V
104. ates the time from when RESET and HALT are first sampled as negated to when instruction execution starts 4 4 4 4 5 4 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 913 SECTION 10 ELECTRICAL AND THERMAL CHARACTERISTICS This section provides information on the maximum rating and thermal characteristics for the MC68000 68 000 MC68HC001 68 000 MC68008 and 68010 10 1 MAXIMUM RATINGS Sassy Voge vo v osere v Maximum Operating Temperature Range Commerical Extended C Grade 40 to 85 Commerical Extended I Grade 0 to 85 Storage Temperature 55 to 150 TL to TH 0 to 70 10 2 THERMAL CHARACTERISTICS This device contains protective circuitry against damage due to high static voltages or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either GND or Vcc Symbol Vatu Thermal Resistance Ceramic Type L LC Ceramic Type R RC Plastic Type P Plastic Type FN 30 33 30 45 Estimated MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 3 POWER CONSIDERATIONS The average die junction temper
105. ating system executes in the supervisor mode allowing it to access all resources required to perform the overhead tasks for the user mode programs Most programs execute in user mode in which the accesses are controlled and the effects on other parts of the system are limited 6 1 1 Supervisor Mode The supervisor mode has the higher level of privilege The mode of the processor is determined by the S bit of the status register if the S bit is set the processor is in the supervisor mode All instructions can be executed in the supervisor mode The bus cycles generated by instructions executed in the supervisor mode are classified as supervisor references While the processor is in the supervisor mode those instructions that use either the system stack pointer implicitly or address register seven explicitly access the SSP 6 1 2 User Mode The user mode has the lower level of privilege If the S bit of the status register is clear the processor is executing instructions in the user mode Most instructions execute identically in either mode However some instructions having important system effects are designated privileged For example user programs are not permitted to execute the STOP instruction or the RESET instruction To ensure that a user program cannot enter the supervisor mode except in a controlled manner the instructions that modify the entire status register are privileged To aid in debugging systems software the move to user
106. ations lt operand gt The operand is logically complemented lt operand gt sign extended The operand is sign extended all bits of the upper portion are made equal to the high order bit of the lower portion lt operand gt tested The operand is compared to zero and the condition codes are set appropriately Notation for other operations TRAP Equivalent to Format Offset Word SSP SSP 2 gt SSP PC gt SSP SSP 4 SSP SR gt SSP SSP 2 SSP vector PC STOP Enter the stopped state waiting for interrupts If lt condition gt then The condition is tested If true the operations after then operations performed If the condition is false and the optional operations else clause is present the operations after else are performed If the condition is false and else is omitted the instruction performs no operation Refer to the Bcc instruction description as an example 2 10 M68000 8 16 32 MICROPROCESSOR USER S MANUAL MOTOROLA Table 2 2 Instruction Set Summary Sheet 1 of 4 ABCD Source g Destination g X gt Destination ABCD Dy Dx ABCD Ay AD Source Destination gt Destination ADD lt ea gt Dn ADD Dn lt ea gt ADDA Source Destination Destination ADDA lt ea gt An ADDI Immediate Data Destination Destination ADDI lt data gt lt ea gt ADDQ Immediate Data Destination gt Destination ADDQ lt data gt lt ea gt A
107. ature in can be obtained from TJ TA PD 9JA 1 where TA Ambient Temperature 9JA Package Thermal Resistance Junction to Ambient C W PD PINT PINT Watts Chip Internal Power Power Dissipation on Input and Output Pins User Determined For most applications P O P NT and can be neglected An appropriate relationship between and T J if P O is neglected is Pp K TJ 273 C 2 Solving Equations 1 and 2 for K gives K Pp 273 C Pp 8 where constant pertaining to the particular K can be determined from equation 3 by measuring P p at thermal equilibrium for a known TA Using this value of the values of Pp and can be obtained by solving Equations 1 and 2 iteratively for any value of T A The curve shown in Figure 10 1 gives the graphic solution to the above equations for the specified power dissipation of 1 5 W over the ambient temperature range of 55 C to 125 using a maximum 9JA of 45 C W Ambient temperature is that of the still air surrounding the device Lower values of 9JA cause the curve to shift downward slightly for instance for 9JA of 40 W the curve is just below 1 4 W at 25 C The total thermal resistance of a package 9JA can be separated into two components 8 and 9CA representing the barrier to heat flow from the semiconductor junction to the package
108. bn ci ADD ADDA 8 1 0 8 1 1 em CUR AND ES Bye Wad tong sw _ NS EOR Cewa sw uw 1 Brewed sw 1 SUBSUBA T Add effective address calculation time Indicates maximum value Only available address mode is data register direct Word or long word only Table 9 7 Standard Instruction Loop Mode Execution Times Loop Continued Loop Terminated Valid Count cc False Valid Count cc True Expired Count lt gt lt gt Dn lt gt lt gt lt gt lt gt An Dn lt ea gt An Dn lt ea gt An Dn lt ea gt 18 1 0 16 1 0 16 1 1 24 3 0 22 3 0 22 3 1 22 3 0 20 3 0 20 3 1 Word Em 16 1 0 16 1 1 es 22 3 0 22 3 1 20 3 0 20 3 1 Word tong 2 zum sow 12 1 0 12 1 0 18 3 0 18 3 0 id 16 3 0 16 4 0 per Word e0 aaa EOR Byte 16 1 0 22 3 1 20 3 1 Word tong w m 2e m 16 1 0 16 1 0 22 3 0 22 3 1 20 3 0 20 3 1 Word zuo zmez aa SUB 18 1 0 16 1 0
109. cated to the number of address bits available on the bus of the particular implementation of the M68000 architecture In all processors except the MC68008 this is 24 address bits 0 is implicitly encoded in the data strobes In the MC68008 the address is 20 or 22 bits in length The memory map for exception vectors is shown in Table 6 2 The vector table Table 6 2 is 512 words long 1024 bytes starting at address 0 decimal and proceeding through address 1023 decimal The vector table provides 255 unique vectors some of which are reserved for trap and other system function vectors Of the 255 192 are reserved for user interrupt vectors However the first 64 entries are not protected so user interrupt vectors may overlap at the discretion of the systems designer 6 2 2 Kinds of Exceptions Exceptions can be generated by either internal or external causes The externally generated exceptions are the interrupts the bus error and reset The interrupts are MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 65 requests from peripheral devices for processor action the bus error and reset inputs are used for access control and processor restart The internal exceptions are generated by instructions address errors or tracing The trap TRAP trap on overflow TRAPV check register against bounds and divide DIV instructions can generate exceptions as part of their instruction execution In addition illegal instr
110. d Junction Temperature vs Temperature der Cc 10 4 Power Dissipation and Junction Temperature vs Temperature OJE vo iE E 10 4 MC68010 Loop Mode Instructions e sse A 3 M68000 USER S MANUAL MOTOROLA SECTION 1 OVERVIEW This manual includes hardware details and programming information for the MC68000 the MC68HCO000 the MC68HC001 the MC68008 the MC68010 and the 68 00 For ease of reading the name M68000 MPUs will be used when referring to all processors Refer to M68000PM AD M68000 Programmer s Reference Manual for detailed information on the MC68000 instruction set The six microprocessors are very similar They all contain the following features e 16 32 Bit Data and Address Registers 16 Mbyte Direct Addressing Range Program Counter 6 Powerful Instruction Types Operations on Five Main Data Types e Memory Mapped Input Output I O 14 Addressing Modes The following processors contain additional features MC68010 Virtual Memory Machine Support High Performance Looping Instructions e MC68HC001 MC68ECO000 Statically Selectable 8 or 16 Bit Data Bus e MC68HC000 MC68EC000 MC68HC001 Low Power All the processors are basically the same with the exception of the MC68008 The MC68008 differs from the others in that the data bus size is eight bits and the address range is smaller The MC68010 has a few additional instructions and instructions that operate dif
111. d drives R W high The device negates DTACK or BERR at this time 4 2 OTHER BUS OPERATIONS Refer to Section 5 16 Bit Bus Operations for information on the following items CPU Space Cycle Bus Arbitration Bus Request Bus Grant Bus Acknowledgment 4 8 Bus Control Bus Errors and Halt Operations Reset Operations Asynchronous Operations Synchronous Operations M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA SECTION 5 16 BIT BUS OPERATION The following paragraphs describe control signal and bus operation for 16 bit bus operations during data transfer operations bus arbitration bus error and halt conditions and reset operation The 16 bit bus operation devices are the MC68000 68 000 68010 and the MC68HC001 and MC68ECO00 in 16 bit mode The MC68HC001 and MC68ECO00 select 16 bit mode by pulling mode high or leave it floating during reset 5 1 DATA TRANSFER OPERATIONS Transfer of data between devices involves the following signals 1 Address bus A1 through highest numbered address line 2 Data bus DO through D15 3 Control signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure In all cases the bus master must deskew all signals it issues at both the start and end of a bus cycle In addition the bus master must deskew the acknowledge and data signals from the slave device The following paragraphs describe the r
112. ddress error occurs during the exception processing for a bus error address error or reset the processor is halted On the MC68010 the address error exception stacks the same information stacked by a bus error exception Therefore the RTE instruction can be used to continue execution of the suspended instruction However if the RR flag is not set the fault address is used when the cycle is retried and another address error exception occurs Therefore the user must be certain that the proper corrections have been made to the stack image and user registers before attempting to continue the instruction With proper software handling the address error exception handler could emulate word or long word accesses to odd addresses if desired If the faulted access was a byte operation the data should be moved from or to the least significant byte of the data output or input buffer images unless the high byte transfer HB bit is set This condition occurs if a MOVEP instruction caused the fault during transfer of bits 8 15 of a word or long word or bits 24 31 of a long word MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 6 19 6 4 RETURN FROM EXCEPTION MC68010 In addition to returning from any exception handler routine on the MC68010 the RTE instruction resumes the execution of a suspended instruction by returning to the normal processing state after restoring all of the temporary register and control information stored duri
113. der bits to obtain a 32 bit long word vector offset In the MC68000 the 68 000 MC68HC001 68 000 and the MC68008 this offset is used as the absolute address to obtain the exception vector itself which is shown in Figure 6 3 NOTE In the MC68010 the vector offset is added to the 32 bit vector base register VBR to obtain the 32 bit absolute address of the exception vector see Figure 6 4 Since the VBR is set to zero upon reset the MC68010 functions identically to the MC68000 68 000 68 001 MC68ECO000 and MC68008 until the VBR is changed via the move control register MOVEC instruction EVEN BYTE A020 EVEN BYTE A0 0 WORD 0 NEW PROGRAM COUNTER HIGH 1 0 WORD 1 NEW PROGRAM COUNTER LOW Al Figure 6 1 Exception Vector Format 64 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 015 08 07 00 T Where v7 is the MSB of the vector number vO is the LSB of the vector number Figure 6 2 Peripheral Vector Number Format A31 10 9 A8 AT A6 A5 4 2 Al 0 L ames Figure 6 3 Address Translated from 8 Bit Vector Number MC68000 68 000 MC68HC001 68 000 and MC68008 31 0 CONTENTS OF VECTOR BASE REGISTER 31 10 0 EXCEPTION VECTOR ADDRESS Figure 6 4 Exception Vector Address Calculation MC68010 The actual address on the address bus is trun
114. duct bearing date codes of 8827 and later This frequency applies only to 68 000 and MC68HCO001 gt gt gt o o o gt gt o o 3 o gt o NOTES 41 Foraloading capacitance of less than or equal to 50 pF subtract 5 ns from the value given in the maximum columns 624 2 The falling edge of 56 triggers both the negation of the strobes AS and DS and the falling edge of Either of these events can occur first depending upon the loading on each signal Specificaton 49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 15 50 51 52 53 S4 W W W W W W W ww 55 56 57 50 DATA OUT gt De 09 DATA IN NOTE This timing diagram is included for those who wish to design their own circuit to generate VMA It shows the best case possible attainable Figure 10 6 MC68000 to M6800 Peripheral Timing Diagram Best Case Applies To All Processors Except The MC68EC 000 10 16 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 10 12 AC ELECTRICAL SPECIFICATIONS BUS ARBITRATION cc 50 VDC 5 GND 0 VDC TO TH See Figure s 10 7 10 11 Applies To All Processors Except The MC68EC000 Characteristic Clock High to Address Data Bus High Impedance Maximum Clock High to Control Bus H
115. e 6 6 MC68010 Stack Frame 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 6 4 68010 Format Codes Format Code Stacked Information 0000 Short Format 4 Words 1000 Long Format 29 Words All Others Unassigned Reserved 6 2 5 Exception Processing Sequence In the first step of exception processing an internal copy is made of the status register After the copy is made the S bit of the status register is set putting the processor into the supervisor mode Also the T bit is cleared which allows the exception handler to execute unhindered by tracing For the reset and interrupt exceptions the interrupt priority mask is also updated appropriately In the second step the vector number of the exception is determined For interrupts the vector number is obtained by a processor bus cycle classified as an interrupt acknowledge cycle For all other exceptions internal logic provides the vector number This vector number is then used to calculate the address of the exception vector The third step except for the reset exception is to save the current processor status The reset exception does not save the context and skips this step The current program counter value and the saved copy of the status register are stacked using the SSP The stacked program counter value usually points to the next unexecuted instruction However for bus error and address error the value stacked for the program counter is unpred
116. e Violations To provide system security various instructions are privileged An attempt to execute one of the privileged instructions while in the user mode causes an exception The privileged instructions are as follows AND Immediate to SR MOVE USP EOR Immediate to SR OR Immediate to SR MOVE to SR 68010 only RESET MOVE from SR 68010 only RTE MOVEC 68010 only STOP MOVES 68010 only Exception processing for privilege violations is nearly identical to that for illegal instructions After the instruction is fetched and decoded and the processor determines that a privilege violation is being attempted the processor starts exception processing The status register is copied the supervisor mode is entered and tracing is turned off The vector number is generated to reference the privilege violation vector and the current program counter and the copy of the status register are saved on the supervisor stack If the processor is an MC68010 the format offset word is also saved The saved value of the program counter is the address of the first word of the instruction causing the privilege violation Finally instruction execution commences at the address in the privilege violation exception vector 6 3 8 Tracing To aid in program development the M68000 Family includes a facility to allow tracing following each instruction When tracing is enabled an exception is forced after each instruction is executed Thus a debugging program ca
117. e clock cycle after DTACK is recognized Violating this requirement may cause the MC68010 to operate erratically MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 39 5 40 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 6 EXCEPTION PROCESSING This section describes operations of the processor outside the normal processing associated with the execution of instructions The functions of the bits in the supervisor portion of the status register are described the supervisor user bit the trace enable bit and the interrupt priority mask Finally the sequence of memory references and actions taken by the processor for exception conditions are described in detail The processor is always in one of three processing states normal exception or halted The normal processing state is associated with instruction execution the memory references are to fetch instructions and operands and to store results A special case of the normal state is the stopped state resulting from execution of a STOP instruction In this state no further memory references are made An additional special case of the normal state is the loop mode of the MC68010 optionally entered when a test condition decrement and branch DBcc instruction is executed In the loop mode only operand fetches occur See Appendix A MC68010 Loop Mode Operation The exception processing state is associated with interrupts trap instructions
118. e device can be designed to decode the address bus before recognizing an address strobe Parameter 11 refer to Section 10 Electrical Characteristics specifies the minimum time before address strobe during which the address is valid In a pseudo asynchronous system timing specifications allow DTACK to be asserted for a read cycle before the data from a slave device is valid The length of time that DTACK may precede data is specified as parameter 31 This parameter must met to ensure the validity of the data latched into the processor No maximum time is specified from the assertion of AS to the assertion of DTACK During this unlimited time the processor inserts wait cycles in one clock period increments until DTACK is recognized Figure 5 33 shows the important timing parameters for a pseudo asynchronous read cycle MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 33 ADDR RW 005 105 Figure 5 33 Pseudo Asynchronous Read Cycle During a write cycle after the processor asserts AS but before driving the data bus the processor drives R W low Parameter 55 specifies the minimum time between the transition of R W and the driving of the data bus which is effectively the maximum turnoff time for any device driving the data bus After the processor places valid data on the bus it asserts the data strobe signal s A data setup time similar to the address setup time previously di
119. e noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 V and 2 0 V Figure 10 12 68 000 Read Cycle Timing Diagram 10 26 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA CLK FC2 FCO A23 A0 LDS 005 RW DTACK DATA OUT HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such thatthe rise or fall is linear between 0 8 V and 2 0 V 2 Because of loading variations R W may be valid after AS even though both are initiated by the rising edge of S2 specification 20A Figure 10 13 68 000 Write Cycle Timing Diagram MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 27 10 15 MC68EC000 AC ELECTRICAL SPECIFICATIONS BUS ARBITRATION vcc 5 0vDc 5 GND 0 VDC TO Ty see Figure e Clock High to Address Data Bus High Impedance Maximum Clock High to Control Bus High 55 55 55 50 42 ace 33 Clock Clock High to Asserted to BG Asserted CACCE eee 55 BG Asserted to Control Address Data Bus High Impedance
120. ead write read modify write and CPU space cycles The indivisible read modify write cycle implements interlocked multiprocessor communications A CPU space cycle is a special processor cycle 5 1 1 Read Cycle During a read cycle the processor receives either one or two bytes of data from the memory or from a peripheral device If the instruction specifies a word or long word operation the MC68000 MC68HC000 MC68HC001 MC68bECO000 MC68010 processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes When the instruction specifies byte operation the processor uses the internal AO bit to determine which byte to read and issues the appropriate data strobe When 0 equals zero the upper data strobe is issued when AO equals one the lower data strobe is issued When the data is received the processor internally positions the byte appropriately The word read cycle flowchart is shown in Figure 5 1 and the byte read cycle flowchart is shown in Figure 5 2 The read and write cycle timing is shown in Figure 5 3 and the word and byte read cycle timing diagram is shown in Figure 5 4 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 1 BUS MASTER SLAVE ADDRESS THE DEVICE 1 SET R W READ 2 PLACE FUNCTION CODE ON FC2 FCO 3 PLACE ADDRESS ON 23 1 _ 4 ASSERT ADDRESS STROBE AS __ 5 ASSERT UPPER DATA STROBE UDS AND LOWER DATA STROBE LDS 1 DECODE ADDRESS 2
121. ecution starts MOTOROLA MC68000 8 16 32 MICROPROCESSORS USER S MANUAL 8 11 SECTION 9 MC68010 INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock CLK periods for the MC68010 In this data it is assumed that both memory read and write cycles consist of four clock periods A longer memory cycle causes the generation of wait states that must be added to the total instruction times The number of bus read and write cycles for each instruction is also included with the timing data This data is shown as n r w where n is the total number of clock periods is the number of read cycles is the number of write cycles For example a timing number shown as 18 3 1 means that 18 clock cycles are required to execute the instruction Of the 18 clock periods 12 are used for the three read cycles four periods per cycle Four additional clock periods are used for the single write cycle for a total of 16 clock periods The bus is idle for two clock periods during which the processor completes the internal operations required for the instructions NOTE The total number of clock periods n includes instruction fetch and all applicable operand fetches and stores MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 9 1 9 1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES Table 9 1 lists the numbers of clock periods required to compute the effective addresses
122. ed are with no loading a Capacitance is periodically sampled rather than 100 tested MOTOROLA 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 23 10 14 MC68EC000 AC ELECTRICAL SPECIFICATIONS READ AND WRITE CYCLES 5 0 VDC 5 PC GND 0 VDC TL TO Ty See Figures 10 12 and 10 13 eee in min min WIES ESI E Clock High to FO Vali totale Clock High to Address Data Bus 55 55 55 50 42 High Impedance Maximum Clock High to Address FC Invalid Minimum 112 Address Valid to AS DS Asserted 20 15 15 10 Read AS Asserted Write 11A2 FC Valid to AS DS Asserted 45 45 45 45 40 Eee esl AS Asserted Write AS DS qaum to Address eck tow 05 EN 15 15 15 10 Invalid 142 AS and DS Read Width 270 195 160 120 100 e a seem EERE Apane E OE turri 207 ute a o o a o 20 25 pon 48 Assented 0 22 Address 9 9 eae Clock Low Data Out Valid 35 35 35 30 25 Write 252 AS DS Negated to Data Out 40 30 20 15 10 Invalid Write 262 Data Out Valid to DS Asserted 40 30 20 15 10 ns Write 27 Data I
123. ed by the M68000 MPUs are bit data integer data of 8 16 and 32 bits 32 bit addresses and binary coded decimal data Each data type is stored in memory as shown in Figure 2 6 The numbers indicate the order of accessing the data from the processor For the MC68008 with its 8 bit bus the appearance of data in memory is identical to the all the M68000 MPUs The organization of data in the memory of the MC68008 is shown in Figure 2 7 2 6 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA 1 8 BITS INTEGER DATA 1 BYTE 8 BITS 1 WORD 16 BITS 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVEN BYTE ODD BYTE 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 LONG WORD 32 BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOW ORDER ADDRESSES 1 ADDRESS 32 BITS 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 HIGH ORDER ADDRESS 0 LOW ORDER ADDRESS 1 ADDRESS 2 MSB MOST SIGNIFICANT BIT LSB LEAST SIGNIFICANT BIT DECIMAL DATA 2 BINARY CODED DECIMAL DIGITS 1 BYTE 11 10 15 13 12 9 8 1 6 5 4 3 2 1 0 MSD BCD 0 BCD1 LSD BCD 2 BCD 3 BCD 4 BCD5 BCD6 BCD7 MSD MOST SIGNIFICANT DIGIT LSD LEAST SIGNIFICANT DIGIT Figure 2 6 Data Organization in Memory M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 7 BIT DATA 1 BYTE 8 BITS 7 6 5 4 3 2 1 0 INTEGER DATA 1 BYTE 8 BITS 7 6 5 4 3 2 1 0 HIGHER ADDRESSES LOWER ADDRESSES 1 WORD 2 BYTES 16 BITS BYTE 0 MS BYTE L
124. emory can operate in the synchronous mode but peripheral devices operate asynchronously For a synchronous device the designer uses explicit timing information shown in Section 10 Electrical Characteristics These specifications define the state of all bus signals relative to a specific state of the processor clock The standard M68000 bus cycle consists of four clock periods eight bus cycle states and optionally an integral number of clock cycles inserted as wait states Wait states are inserted as required to allow sufficient response time for the external device The following state by state description of the bus cycle differs from those descriptions in 5 1 1 READ CYCLE and 5 1 2 WRITE CYCLE by including information about the important timing parameters that apply in the bus cycle states STATE 0 The bus cycle starts in SO during which the clock is high At the rising edge of SO the function code for the access is driven externally Parameter 6A defines the delay from this rising edge until the function codes are valid Also the R W signal is driven high parameter 18 defines the delay from the same rising edge to the transition of RAW The minimum value for parameter 18 applies to a read cycle preceded by a write cycle this value MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 35 STATE 1 STATE 2 STATE 3 STATE 4 STATE 5 STATE 6 STATE 7 5 36 is the maximum hold time for a low R W beyond the in
125. er 47 the processor may recognize the signal and continue the bus cycle the result is unpredictable If neither DTACK nor BERR is asserted before the next rise of clock the bus cycle remains in S4 and wait states complete clock cycles are inserted until one of the bus cycle termination is met S5 is a low period of the clock during which the processor does not alter any signal S6 is a high period of the clock during which data for a read operation is set up relative to the falling edge entering S7 Parameter 27 defines the minimum period by which the data must precede the falling edge For a write operation the processor changes no signal during S6 On the falling edge of the clock entering S7 the processor latches data and negates AS and UDS LDS and or DS during a read cycle The hold time for these strobes from this falling edge is specified by parameter 12 The hold time for data relative to the negation of AS and UDS LDS and or DS is specified by parameter 29 For a write cycle only AS and UDS LDS and or DS are negated timing parameter 12 also applies M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA On the rising edge of the clock the end of 57 which may be the start of SO for the next bus cycle the processor places the address bus in the high impedance state During a write cycle the processor also places the data bus in the high impedance state and drives R W high External
126. er MOVE to SR AND immediate to status register ANDI to SR and exclusive OR immediate to status register EORI to SR The RTE instruction in the MC68010 fetches the new status register and program counter from the supervisor stack and loads each into its respective register Next it begins the instruction fetch at the new program counter address in the privilege mode determined by the S bit of the new contents of the status register The MOVE to SR ANDI to SR and EORI to SR instructions fetch all operands in the supervisor mode perform the appropriate update to the status register and then fetch the next instruction at the next sequential program counter address in the privilege mode determined by the new S bit 6 1 4 Reference Classification When the processor makes a reference it classifies the reference according to the encoding of the three function code output lines This classification allows external translation of addresses control of access and differentiation of special processor states such as CPU space used by interrupt acknowledge cycles Table 6 1 lists the classification of references Table 6 1 Reference Classification Function Code Output Address Space Reserved o t o 1 UndefnedResevedy Undefined Reserved i o 1 SupenvisorData pt 1 o supervisor Program Address space 3 is reser
127. er acknowledge is inactive which indicates that neither memory nor peripherals are using the bus Bus grant acknowledge is inactive which indicates that no other device is still claiming bus mastership The 48 pin version of the MC68008 has no pin available for the bus grant acknowledge signal and uses a two wire bus arbitration scheme instead If another device in a system supplies a bus grant acknowledge signal the bus request input signal to the processor should be asserted when either the bus request or the bus grant acknowledge from that device is asserted 3 5 INTERRUPT CONTROL IPLO IPL1 IPL2 These input signals indicate the encoded priority level of the device requesting an interrupt Level seven which cannot be masked has the highest priority level zero indicates that no interrupts are requested IPLO is the least significant bit of the encoded level and IPL2 is the most significant bit For each interrupt request these signals must remain asserted until the processor signals interrupt acknowledge FC2 FCO and 19 16 high for that request to ensure that the interrupt is recognized 3 6 NOTE The 48 pin version of the MC68008 has only two interrupt control signals IPLO IPL2 and IPL1 IPLO IPL2 is internally connected to both IPLO and IPL2 which provides four interrupt priority levels levels 0 2 5 and 7 In all other respects the interrupt priority levels in this version of the MC68008 are identical to those
128. er of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 9 14 Bit Manipulation Instruction Execution Times 12 2 1 14 2 1 12 2 1 12 2 0 14 2 0 Add effective address calculation time Indicates maximum value data addressing mode only 9 8 CONDITIONAL INSTRUCTION EXECUTION TIMES Table 9 15 lists the timing data for the conditional instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 99 Table 9 15 Conditional Instruction Execution Times Instruction Displacement Branch Taken Branch Not Taken Boc 10 20 6010 10020 zT 10 BSR 18 2 DBoc ww 9 9 JMP JSR LEA PEA AND MOVEM INSTRUCTION EXECUTION TIMES Table 9 16 lists the timing data for the jump JMP jump to subroutine JSR load effective address LEA push effective address PEA and move multiple registers MOVEM instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format Table 9 16 J
129. eviously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign In Table 8 5 the following notation applies Immediate operand Dn Data register operand An Address register operand M Memory operand 8 4 MC68000 8 16 32 MICROPROCESSORS UISER S MANUAL MOTOROLA Table 8 5 Immediate Instruction Execution Times pomum s e omm _ __ Lew 8 2 0 12 2 1 1480 2 3 0 TM a Lm mem 8 1 1 OMPI Byte Word ___ 2082 8 5 SINGLE INSTRUCTION EXECUTION TIMES Table 8 6 lists the timing data for the single operand instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign MOTOROLA MC68000 8 16 32 MICROPROCESSORS USER S MANUAL 8 5 Table 8 6 Single Operand Instruction Execution Times on a Add effective address calculation time 8 6 SHIFT ROTATE I
130. fective address operand MOTOROLA MC68000 8 16 32 MICROPROCESSORS USER S MANUAL 8 3 Table 8 4 Standard Instruction Execution Times onan sec 22 2 ws TIE ie wo aor hus ma EXE m ECT Lm mee SUB Byte Word 6 1 0 6 1 0 12 1 2 Add effective address calculation time t Word or long only Indicates maximum basic value added to word effective address time The base time of six clock periods is increased to eight if the effective address mode is register direct or immediate effective address time should also be added Only available effective address mode is data register direct DIVS DIVU The divide algorithm used by the MC68000 provides less than 10 difference between the best and worst case timings MULS MULU The multiply algorithm requires 38 2n clocks where n is defined as MULU n the number of ones in the ea MULS n concatenate the ea with a zero as the LSB n is the resultant number of 10 or 01 patterns in the 17 bit source i e worst case happens when the source is 5555 kkk 8 4 IMMEDIATE INSTRUCTION EXECUTION TIMES The numbers of clock periods shown in Table 8 5 include the times to fetch immediate operands perform the operations store the results and read the next operation The total number of clock periods the number of read cycles and the number of write cycles are shown in the pr
131. ferently than the corresponding instructions of the other devices MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 1 1 11 MC68000 The 68000 is the first implementation of the 68000 16 32 bit microprocessor architecture The MC68000 has a 16 bit data bus and 24 bit address bus while the full architecture provides for 32 bit address and data buses It is completely code compatible with the MC68008 8 bit data bus implementation of the M68000 and is upward code compatible with the MC68010 virtual extensions and the MC68020 32 bit implementation of the architecture Any user mode programs using the MC68000 instruction set will run unchanged on the MC68008 68010 MC68020 MC68030 and MC68040 This is possible because the user programming model is identical for all processors and the instruction sets are proper subsets of the complete architecture 1 2 MC68008 The MC68008 is a member of the M68000 family of advanced microprocessors This device allows the design of cost effective systems using 8 bit data buses while providing the benefits of a 32 bit microprocessor architecture The performance of the MC68008 is greater than any 8 bit microprocessor and superior to several 16 bit microprocessors The MC68008 is available as a 48 pin dual in line package plastic or ceramic and 52 pin plastic leaded chip carrier The additional four pins of the 52 pin package allow for additional signals A20 A21 BGACK and IPL2 The 48 pin
132. fied at logic high 2 0 V logic low 0 8 V 1 MC68008 52 Version Only Figure 10 10 Bus Arbitration Timing Active Bus Case Applies To All Processors E xcept The MC68EC 000 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 21 ms Em 2 VMA RAW a NOTES Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V 1 MC68008 52 Pin Version only Figure 10 11 Bus Arbitration Timing Multiple Bus Request Applies To All Processors E xcept The MC68EC 000 10 22 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 10 13 68 000 ELECTRICAL SPECIFICATIONS voc 5 PC GND 0 VDC T Input Leakage Current BERR BR DTACK CLK IPL2 IPLO AVEC 05 25 V MODE HALT RESET Three State Off State Input Current AS 23 0 015 00 92 4 0 4 2 LDS R W UDS Output High Voltage AS 23 0 BG 015 00 400 uA FC2 FCO LDS R W UDS Output Low Voltage IOL 1 6 mA HALT IOL 3 2 mA 23 0 BG FC2 FCO IOL 5 0 mA RESET IOL 5 3 mA 015 00 LDS R W UDS Current Dissipation f 8 MHz f 10 MHz f 12 5 MHz f 16 67 MHz f 20 MHz Power Dissipation f 8 MHz f 10 MHz f 12 5 MHz f 16 67 MHz f 20 MHz Capacitance Vin 0 V TA 25 C Frequency 1 MHz Load Capacitance HALT All Others Currents list
133. forms a read operation modifies the data in the arithmetic logic unit and writes the data back to the same address The address strobe AS remains asserted throughout the entire cycle making the cycle indivisible The test and set TAS instruction uses this cycle to provide a signaling capability without deadlock between processors in a multiprocessing environment The TAS instruction the only instruction that uses the read modify write cycle only operates on bytes Thus all read modify write cycles are byte operations Figure 4 5 and 4 6 illustrate the read modify write cycle operation MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 4 5 4 6 BUS MASTER SLAVE ADDRESS THE DEVICE 1 SET R W READ 2 PLACE FUNCTION CODE ON 2 3 PLACE ADDRESS ON A23 A0 _ 4 ASSERT ADDRESS STROBE AS __ 5 ASSERT LOWER DATA STROBE LDS DS ON MC68008 1 DECODE ADDRESS 2 PLACE DATA ON 07 00 3 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK ACQUIRE THE DATA 1 LATCH DATA _ 1 NEGATE LDS OR DS 2 START DATA MODIFICATION 1 REMOVE DATA FROM 07 00 2 NEGATE DTACK START OUTPUT TRANSFER 1 SET R W TO WRITE 2 PLACE DATA ON 07 00 mAs 3 ASSERT LOWER DATA STROBE LDS DS ON MC68008 1 STORE DATA ON 07 00 2 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK TERMINATE OUTPUT TRANSFER 1 NEGATE DS OR LDS 2 NEGATE AS 3 REMOVE DATAFROM 07 00 4 SET R W TO READ 1 NEGATE DTACK
134. garding bus errors The MC68010 can detect a late bus error signal asserted within one clock cycle after the assertion of data transfer acknowledge When receiving a bus error signal the processor can either initiate a bus error exception sequence or try running the cycle again 5 4 1 Bus Error Operation In all the microprocessors described in this manual a bus error is recognized when DTACK and HALT are negated and BERR is asserted In the MC68010 a late bus error is also recognized when HALT is negated and DTACK and BERR are asserted within one clock cycle When the bus error condition is recognized the current bus cycle is terminated in S9 for a read cycle a write cycle or the read portion of a read modify write cycle For the write portion of a read modify write cycle the current bus cycle is terminated in S21 As long as BERR remains asserted the data and address buses are in the high impedance state Figure 5 25 shows the timing for the normal bus error and Figure 5 26 shows the timing for the MC68010 late bus error FC2 FCO i E 29 5 2 5 eee XL LDS UDS N V RAV ldc JA DTACK a HALT INITIATE RESPONSE BUS ERROR lt INITIATE BUS lt READ gt lt FAILURE DETECTION ERROR STACKING Figure 5 25 Bus Error Timing Diagram 5 24 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 23 1 295
135. gister LOOP MOVE W A1 Loop To Move The Block Of Data DBEQ DO LOOP Stop If Data Word Is Zero Figure A 1 DBcc Loop Mode Program Example The first load effective address LEA instruction loads the address labeled SOURCE into address register AO The second instruction also an LEA instruction loads the address labeled DEST into address register A1 Next a move data from source to destination MOVE instruction moves the number of words into data register DO the loop counter The last two instructions a MOVE and a test equal decrement and branch DBEQ form the loop that moves the block of data The bus activity required to execute these instructions consists of the following cycles MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL A 1 Fetch the MOVE instruction Fetch the DBEQ instruction Read the operand at the address in AO Write the operand at the address in Fetch the displacement word of the DBEQ instruction Bee qusc Of these five bus cycles only two move the data However the MC68010 has a two word prefetch queue in addition to the one word instruction decode register The loop mode uses the prefetch queue and the instruction decode register to eliminate the instruction fetch cycles The processor places the MOVE instruction in the instruction decode register and the two words of the DBEQ instruction in the prefetch queue With no additional opcode fetches the processor executes
136. gram counter is the address of the exception vector Although this information is not generally sufficient to effect full recovery from the bus error it does allow software diagnosis Finally the processor commences instruction processing at the address in the vector It is the responsibility of the error handler routine to clean up the stack and determine where to continue execution If a bus error occurs during the exception processing for a bus error an address error or a reset the processor halts and all processing ceases This halt simplifies the detection of a catastrophic system failure since the processor removes itself from the system to 6 16 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA protect memory contents from erroneous accesses Only an external reset operation can restart a halted processor LOWER ADDRESS PROGRAM COUNTER R W Read Write Write 0 Read 1 Instruction Not Instruction 0 Not 1 Figure 6 7 Supervisor Stack Order for Bus or Address Error Exception 6 3 9 2 BUS ERROR MC68010 Exception processing for a bus error follows a slightly different sequence than the sequence for group 1 and 2 exceptions In addition to the four steps executed during exception processing for all other exceptions 22 words of additional information are placed on the stack This additional information describes the internal state of the processor at the time of the bus error and is reloaded by the RTE instr
137. gt offset width Selects a bit field lt gt The contents of the referenced location lt operand gt 10 The operand is binary coded decimal operations are performed in decimal address register The register indirect operator lt address register Indicates that the operand register points to the memory address register Location of the instruction operand the optional mode qualifiers are d and d ix or lt data gt Immediate data that follows the instruction word s Notations for operations that have two operands written lt operand gt op lt gt where op is one of the following The source operand is moved to the destination operand lt gt The two operands are exchanged The operands are added The destination operand is subtracted from the source operand x The operands are multiplied The source operand is divided by the destination operand lt Relational test true if source operand is less than destination operand gt Relational test true if source operand is greater than destination operand V Logical OR Logical exclusive OR A Logical AND MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 9 shifted by rotated by The source operand is shifted rotated by the number of positions specified by the second operand Notation for single operand oper
138. he bus cycle terminates in S7 except when BERR is asserted in the absence of DTACK In that case the bus cycle terminates one clock cycle later in S9 4 1 2 Write Cycle During a write cycle the processor sends bytes of data to the memory or peripheral device Figures 4 3 and 4 4 illustrate the write cycle operation The 8 bit operation performs two write cycles for a word write operation issuing the data strobe signal during each cycle The address bus includes the AO bit to select the desired byte MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 4 3 BUS MASTER ADDRESS THE DEVICE 1 PLACE FUNCTION CODE ON FC2 FCO 2 PLACE ADDRESS ON 23 _ 3 ASSERT ADDRESS STROBE AS 4 SETR W TO WRITE 5 PLACE DATA ON 00 07 T 6 ASSERT LOWER DATA STROBE LDS OR DS TERMINATE OUTPUT TRANSFER 1 NEGATE LDS OR DS 2 NEGATE AS 3 REMOVE DATA FROM 07 00 4 SETR W TO READ START NEXT CYCLE Figure 4 3 Byte Write Cycle Flowchart SLAVE INPUT THE DATA 1 DECODE ADDRESS 2 STORE DATA ON 07 00 3 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK TERMINATE THE CYCLE 1 NEGATE DTACK 50 S1 S2 S3 54 55 S6 57 50 51 S2 S3 54 S5 S6 57 50 51 S2 S3 54 S5 56 57 LDS N N DTACK cee 000 BYTE WRITE gt lt 000 BYTE WRITE Ch EVEN BYTE WRITE Figure 4 4 Write Cycle Timing Diagram 44 M68000 8 16 32 BIT MICROPROCESSORS USER
139. he processor negates AS UDS and LDS As the clock rises at the end of S19 the processor places the address and data buses in the high impedance state and drives R W high The device negates DTACK or BERR at this time 5 1 4 CPU Space Cycle A CPU space cycle indicated when the function codes are all high is a special processor cycle Bits 16 19 of the address bus identify eight types of CPU space cycles Only the interrupt acknowledge cycle in which 16 19 are high applies to all the microprocessors described in this manual The MC68010 defines an additional type of CPU space cycle the breakpoint acknowledge cycle in which 16 19 are all low Other configurations of 16 19 are reserved by Motorola to define other types of CPU cycles used in other M68000 Family microprocessors Figure 5 10 shows the encoding of CPU space addresses FUNCTION ADDRESS BUS CODE 1 2 0 31 123 119 16 0 KNOWLEDGE 0000000000000 000000000 00000 0 0000 68010 only 31 3 10 aede DEBT nua d v a os ede MOTOROLA CPU SPACE TYPE FIELD Figure 5 10 CPU Space Address Encoding M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 59 The interrupt acknowledge cycle places the level of the interrupt being acknowledged address bits 1 and drives all other address lines high The interrupt acknowledge cycle reads a vector number when the interrupting de
140. hronizers used by M68000 Family processors The input latches allow the input to propagate through to the output when E is high When low E latches the input The three latches require one cycle of CLK to synchronize an external signal The high gain characteristics of the devices comprising the latches quickly resolve a marginal signal into a valid state INT SIGNAL EXT SIGNAL CLK CLK Figure 5 37 Input Synchronizers 5 38 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Parameter 47 of Section 10 Electrical Characteristics is the asynchronous input setup time Signals that meet parameter 47 are guaranteed to be recognized at the next falling edge of the system clock However signals that do not meet parameter 47 are not guaranteed to be recognized In addition if DTACK is recognized on a falling edge valid data is latched into the processor during a read cycle on the next falling edge provided the data meets the setup time required parameter 27 When parameter 27 has been met parameter 31 may be ignored If DTACK is asserted with the required setup time before the falling edge of S4 no wait states are incurred and the bus cycle runs at its maximum speed of four clock periods The late BERR in an MC68010 that is operating in a synchronous mode must meet setup time parameter 27A That is when BERR is asserted after BERR must be asserted before the falling edge of the clock on
141. ictable and may be incremented from the address of the instruction that caused the error Group 1 and 2 exceptions use a short format exception stack frame format 0000 on the MC68010 Additional information defining the current context is stacked for the bus error and address error exceptions The last step is the same for all exceptions The new program counter value is fetched from the exception vector The processor then resumes instruction execution The instruction at the address in the exception vector is fetched and normal instruction decoding and execution is started 6 3 PROCESSING OF SPECIFIC EXCEPTIONS The exceptions are classified according to their sources and each type is processed differently The following paragraphs describe in detail the types of exceptions and the processing of each type 6 3 1 Reset The reset exception corresponds to the highest exception level The processing of the reset exception is performed for system initiation and recovery from catastrophic failure Any processing in progress at the time of the reset is aborted and cannot be recovered The processor is forced into the supervisor state and the trace state is forced off The MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 6 11 interrupt priority mask is set at level 7 In the MC68010 the VBR is forced to zero The vector number is internally generated to reference the reset exception vector at location 0 in the supervisor program
142. igh Impedance Clock High to BG Asserted Clock High to BG Negated BR Negated to BG Negated 1 BGACK Asserted to BG Negated 1 3 3 5 6 3 6 3 4 7 37A2 BGACK Asserted to BR Negated 38 BG Asserted to Control Address Data Bus High Impedance AS Negated 39 BG Width Negated BGACK Width Low Asynchronous Input Setup Time 57 BGACK Negated to AS DS 1 5 R W Driven BGACK Negated to FC VMA 1 Driven BR Negated to AS DS R W 1 5 Driven BR Negated to FC 1 Driven These specifications represent improvement over previously published specifications for the 8 10 and 12 5 MHz MC68000 and are valid only for product bearing date codes of 8827 and later Applies only to the 68 000 and MC68HCO001 NOTES 1 Setup time for the synchronous inputs BGACK IPLO IPL2 and VPA guarantees their recognition at the next falling edge of the clock 2 BR need fall at this time only in order to insure being recognized at the end of the bus cycle 3 Timing measurements are referenced to and from a low voltage of 0 8 volt and a high voltage of 2 0 volts unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall will be lienar between 0 8 volt and 2 0 volts 4 The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK
143. ignals and the corresponding data on the bus When the R W line is high the processor reads from the data bus When the R W line is low the processor drives the data bus In 8 bit mode UDS is always forced high and the LDS signal is used 3 4 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 3 1 Data Strobe Control of Data Bus ws us Wo vais bata Low Low High Valid Data Bits Valid Data Bits 15 8 7 0 Low Valid Data Valid Data Bits 7 0 Low High High Valid Data Bus No Valid Data 15 8 Low Low Low Valid Data Bits Valid Data Bits 15 8 7 0 High Low Low Valid Data Bits Valid Data Bits 7 0 7 0 Low High Low Valid Data Bits Valid Data Bits 15 8 15 8 These conditions are a result of current implementation and may not appear on future devices Data Strobe DS MC68008 This three state signal and R W control the flow of data on the data bus of the MC68008 Table 3 2 lists the combinations of these signals and the corresponding data on the bus When the R W line is high the processor reads from the data bus When the R W line is low the processor drives the data bus Table 3 2 Data Strobe Control of Data Bus MC68008 m ww 1 Valid Data Bits 7 0 Read Cycle Valid Data Bits 7 0 Write Cycle Data Transfer Acknowledge DTACK This input signal indicates the completion of the data t
144. ion If data is invalid assert BERR on the next clock cycle case 4 Table 5 6 BERR and HALT Negation Results Conditions of Negated on Rising of State Termination in Table 4 4 Control Signal Results Next Cycle Bus Error BERR bus error trap HALT BERR Illegal sequence usually traps to vector number 0 HALT Rerun BERR Reruns the bus cycle HALT Normal BERR May lengthen next cycle HALT Normal BERR If next cycle is started it will be terminated as a bus HALT none error Signal is negated in this bus state 5 7 ASYNCHRONOUS OPERATION To achieve clock frequency independence at a system level the bus can be operated in an asynchronous manner Asynchronous bus operation uses the bus handshake signals to control the transfer of data The handshake signals are AS UDS LDS DS MC68008 only BERR HALT AVEC 68 000 only and VPA only for M6800 peripheral cycles AS indicates the start of the bus cycle and UDS LDS and DS signal valid data for a write cycle After placing the requested data on the data bus read cycle or latching the data write cycle the slave device memory or peripheral asserts to terminate the bus cycle If no device responds or if the access is invalid external control logic asserts BERR or BERR and HALT to abort or retry the cycle Figure 5 31 shows the use of the bus handshake signals in a fully asynchronous read cycle Figure 5 32 shows a
145. ion occurs at the end of both the looped instruction and the DBcc instruction making loop mode unavailable while tracing is enabled A reset operation aborts all processing including loop mode processing A bus error during loop mode operation is handled the same as during other processing however when the return from exception RTE instruction continues execution of the looped instruction the three word loop is not fetched again Table A 1 lists the loop mode instructions of the MC68010 Only one word versions of these instructions can operate in the loop mode One word instructions use the three address register indirect modes An An and A 2 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table A 1 MC68010 Loop Mode Instructions Applicable Addressing Modes MOVE BWL Ay to Ax Ay to Ax Ay to Ay to Ax Ay to to Ax Ay to Ax Ay to Ry to Ax Ry to Ax ADD BWL Ay to Dx AND BWL Ay to Dx CMP BWL to Dx OR BWL SUB BWL ADDA WL Ay to Ax CMPA WL to Ax SUBA WL Ay to Ax ADD BWL Dx to Ay AND BWL Dx to Ay EOR BWL Dx to Ay OR BWL SUB BWL ABCD B ADDX BWL SBCD B SUBX BWL CLR BWL NEG BWL NEGX BWL NOT BWL TST BWL NBCD ASL Ay by 1 ASR Ay by 1 LSL W by 1 LSR W ROL W ROR W ROXL W ROXR NOTE
146. is fetching the instruction or an operand when the error occurs the context of the processor is more detailed To save more of this context additional information is saved on the supervisor stack The program counter and the copy of the status register are saved The value saved for the program counter is advanced 2 10 bytes beyond the address of the first word of the instruction that made the reference causing the bus error If the bus error occurred during the fetch of the next instruction the saved program counter has a value in the vicinity of the current instruction even if the current instruction is a branch a jump or a return instruction In addition to the usual information the processor saves its internal copy of the first word of the instruction being processed and the address being accessed by the aborted bus cycle Specific information about the access is also saved type of access read or write processor activity processing an instruction and function code outputs when the bus error occurred The processor is processing an instruction if it is in the normal state or processing a group 2 exception the processor is not processing an instruction if it is processing a group 0 or a group 1 exception Figure 6 7 illustrates how this information is organized on the supervisor stack If a bus error occurs during the last step of exception processing while either reading the exception vector or fetching the instruction the value of the pro
147. is addressed as bit 31 MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 5 When a data register is used as either a source or a destination operand only appropriate low order portion is changed the remaining high order portion is neither used nor changed 2 3 2 Address Registers Each address register and the stack pointer is 32 bits wide and holds a full 32 bit address Address registers do not support byte sized operands Therefore when an address register is used as a source operand either the low order word or the entire long word operand is used depending upon the operation size When an address register is used as the destination operand the entire register is affected regardless of the operation size If the operation size is word operands are sign extended to 32 bits before the operation is performed 2 4 DATA ORGANIZATION IN MEMORY Bytes are individually addressable As shown in Figure 2 5 the high order byte of a word has the same address as the word The low order byte has an odd address one count higher Instructions and multibyte data are accessed only on word even byte boundaries If a long word operand is located at address n even then the second word of that operand is located at address n 2 ADDRESS 000000 BYTE 000000 BYTE 000001 000002 BYTE 000002 BYTE 000003 WORD 7FFFFF SFFFFFE BYTE FFFFFE BYTE FFFFFE Figure 2 5 Word Organization in Memory The data types support
148. is being executed when the processor executes a breakpoint BKPT instruction The processor neither accepts nor sends data during this cycle which is otherwise similar to a read cycle The cycle is terminated by either DTACK BERR or as an M6800 peripheral cycle when VPA is asserted and the processor continues illegal instruction exception processing Figure 5 12 illustrates the timing diagram for the breakpoint acknowledge cycle so 52 54 56 S0 52 54 S6 50 52 54 56 ge LILI a __ Ll a __ a SS SSS lt WORD READ gt lt BREAKPOINT 9 STACK PC Low gt CYCLE Figure 5 12 Breakpoint Acknowledge Cycle Timing Diagram 5 2 BUS ARBITRATION Bus arbitration is a technique used by bus master devices to request to be granted and to acknowledge bus mastership Bus arbitration consists of the following 1 Asserting a bus mastership request 2 Receiving a grant indicating that the bus is available at the end of the current cycle 3 Acknowledging that mastership has been assumed There are two ways to arbitrate the bus 3 wire and 2 wire bus arbitration The MC68000 68 000 68 000 MC68HC001 68008 and MC68010 can do 2 wire bus arbitration The MC68000 MC68HCO000 MC68HC001 and MC68010 can do 3 wire bus arbitration Figures 5 13 and 5 15 show 3 wire bus arbitration and Figures 5 14 and
149. ister 2 2 DATA TYPES AND ADDRESSING MODES The five basic data types supported are as follows 1 Bits 2 Binary Coded Decimal BCD Digits 4 Bits 3 Bytes 8 Bits 4 Words 16 Bits 5 Long Words 32 Bits MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 3 In addition operations on other data types such as memory addresses status word data etc are provided in the instruction set The 14 flexible addressing modes shown in Table 2 1 include six basic types Register Direct 2 Register Indirect 3 Absolute 4 Immediate 5 Program Counter Relative 6 Implied The register indirect addressing modes provide postincrementing predecrementing offsetting and indexing capabilities The program counter relative mode also supports indexing and offsetting For detail information on addressing modes refer to M68000PM AD M68000 Programmer Reference Manual 2 4 M68000 8 16 32 MICROPROCESSOR USER S MANUAL MOTOROLA Table 2 1 Data Addressing Modes weds syntax Register Direct Addressing Data Register Direct Dn Address Register Direct An Absolute Data Addressing Absolute Short EA Next Word xxx W Absolute Long EA Next Two Words xxx L Program Counter Relative Addressing d16 PC Relative with Offset P dg PC Xn Relative with Index and Offset Register Indirect Addressing Register Indirect EA An An Postincrement Register Indirect EA
150. ite cycle performs a read operation modifies the data in the arithmetic logic unit and writes the data back to the same address The address strobe AS remains asserted throughout the entire cycle making the cycle indivisible The test and set TAS instruction uses this cycle to provide a signaling capability without deadlock between processors in a multiprocessing environment The TAS instruction the only instruction that uses the read modify write cycle only operates on bytes Thus all read modify write cycles are byte operations The read modify write flowchart shown in Figure 5 8 and the timing diagram in Figure 5 9 applies to the MC68000 the 68 000 the MC68HCO001 in 16 bit mode the 68 000 in 16 bit mode and the 68010 BUS MASTER SLAVE ADDRESS THE DEVICE 1 SET RW TO READ 2 PLACE FUNCTION CODE ON FC2 FCO 3 PLACE ADDRESS A23 Al _ 4 ASSERT ADDRESS STROBE AS 5 ASSERT UPPER DATA STROBE UDS OR LOWER DATA STROBE LDS INPUT THE DATA 1 DECODE ADDRESS 2 PLACE DATA ON 07 00 OR D15 D0 3 ASSERT DATA TRANSFER ACKNOWLEDGE DTACK ACQUIRE THE DATA 1 LATCH DATA 1 NEGATE UDS AND LDS 2 START DATA MODIFICATION TERMINATE THE CYCLE 1 REMOVE DATA FROM 07 00 OR D15 D8 2 NEGATE DTACK START OUTPUT TRANSFER 1 SET RAW TO WRITE 2 PLACE DATA ON 07 00 OR D15 D8_ 3 ASSERT UPPER DATA STROBE UDS OR LOWER DATA STROBE LDS INPUT THE DATA 1 STORE DATA ON 07
151. itiation of the read cycle Entering S1 a low period of the clock the address of the accessed device is driven externally with an assertion delay defined by parameter 6 On the rising edge of S2 a high period of the clock AS is asserted During a read cycle UDS LDS and or DS is also asserted at this time Parameter 9 defines the assertion delay for these signals For a write cycle the R W signal is driven low with a delay defined by parameter 20 On the falling edge of the clock entering S3 the data bus is driven out of the high impedance state with the data being written to the accessed device in a write cycle Parameter 23 specifies the data assertion delay In a read cycle no signal is altered 53 Entering the high clock period of S4 UDS LDS and or DS is asserted during a write cycle on the rising edge of the clock As in S2 for a read cycle parameter 9 defines the assertion delay from the rising edge of S4 for UDS LDS and or DS In a read cycle no signal is altered by the processor during S4 Until the falling edge of the clock at the end of S4 beginning of S5 no response from any external device except RESET is acknowledged by the processor If either DTACK or BERR is asserted before the falling edge of 54 and satisfies the input setup time defined by parameter 47 the processor enters S5 and the bus cycle continues If either DTACK or BERR is asserted but without meeting the setup time defined by paramet
152. le Number User Programmer s x era a aie 2 2 Supervisor Programmer s Model Supplement 2 2 Supervisor Programmer s Model Supplement MC68010 2 3 EE E NE TIR PT ERE 2 3 Word Organization In Memory 2 iri Eo erae Mn Pre Rott n E pe ER rode 2 6 Data Organization In e tecta air ee stan ee Eo rx lenis e 2 7 Memory Data Organization 68008 2 3 Input and Output Signals MC68000 68 000 MC68010 3 1 Input and Output Signals MC68HC001 3 2 Input and Output Signals 68 000 2 3 2 Input and Output Signals MC68008 48 Pin 3 3 Input and Output Signals MC68008 52 Pin 3 3 Byte Read Cycle FlOwCn ard 4 2 Read and Write Cycle Timing 4 2 Byte Write Cycle Flowchart 4 4 Write Cycle Timing Diagram 4 4 Read Modify Write Cycle Flowchart esee 4 6 Read Modify Write Cycle Timing 4 7 Word he ad Oycle
153. levels in the other microprocessors described in this manual M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 3 6 SYSTEM CONTROL The system control inputs are used to reset the processor to halt the processor and to signal a bus error to the processor The outputs reset the external devices in the system and signal a processor error halt to those devices The three system control signals are described in the following paragraphs Bus Error BERR This input signal indicates a problem in the current bus cycle The problem may be the following No response from a device No interrupt vector number returned An illegal access request rejected by a memory management unit Some other application dependent error Either the processor retries the bus cycle or performs exception processing as determined by interaction between the bus error signal and the halt signal Reset RESET The external assertion of this bidirectional signal along with the assertion of HALT starts a system initialization sequence by resetting the processor The processor assertion of RESET from executing a RESET instruction resets all external devices of a system without affecting the internal state of the processor To reset both the processor and the external devices the RESET and HALT input signals must be asserted at the same time Halt HALT An input to this bidirectional signal causes the processor to s
154. lly to generate traps The TRAP instruction always forces an exception and is useful for implementing system calls for user programs The TRAPV and CHK instructions force an exception if the user program detects a run time error which may be an arithmetic overflow or a subscript out of bounds MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 613 A signed divide DIVS or unsigned divide DIVU instruction forces an exception if a division operation is attempted with a divisor of zero 6 3 6 Illegal and Unimplemented Instructions Illegal instruction is the term used to refer to any of the word bit patterns that do not match the bit pattern of the first word of a legal M68000 instruction If such an instruction is fetched an illegal instruction exception occurs Motorola reserves the right to define instructions using the opcodes of any of the illegal instructions Three bit patterns always force an illegal instruction trap on all M68000 Family compatible microprocessors The patterns are 4AFA 4AFB and 4AFC Two of the patterns 4AFA and 4AFB are reserved for Motorola system products The third pattern 4AFC is reserved for customer use as the take illegal instruction trap ILLEGAL instruction NOTE In addition to the previously defined illegal instruction opcodes the MC68010 defines eight breakpoint BKPT instructions with the bit patterns 4848 484F These instructions cause the processor to enter illegal instruc
155. location is needed so that the requested data can be brought into physical memory The RTE instruction is used to reload the internal state of the processor at the time of the fault The faulted bus cycle is then rerun and the suspended instruction is completed If the faulted bus cycle is a read modify write the entire cycle is rerun whether the fault occurred during the read or the write operation An alternate method of handling a bus error is to complete the faulted access in software Using this method requires the special status word the instruction input buffer the data input buffer and the data output buffer image The format of the special status word is 6 18 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA shown in Figure 6 9 If the bus cycle is a read the data at the fault address should be written to the images of the data input buffer instruction input buffer or both according to the data fetch DF and instruction fetch IF bits In addition for read modify write cycles the status register image must be properly set to reflect the read data if the fault occurred during the read portion of the cycle and the write operation i e setting the most significant bit of the memory location must also be performed These operations are required because the entire read modify write cycle is assumed to have been completed by software Once the cycle has been completed by software the rerun RR bit in the special stat
156. lt ALTERNATE BUS MASTER gt lt PROCESSOR 9 Figure 5 21 3 Wire Bus Arbitration Timing Diagram Special Case 5 20 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA BUS THREE STATED BUS RELEASED FROM THREE STATE AND BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE BR VALID INTERNAL BR NEGATED INTERNAL BR SAMPLE BR SAMPLED BR ASSERTED BR NEGATED 50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 57 50 51 BR BG BGACK DTACK e o PROCESSOR gt ALTERNATE BUS MASTER PROCESSOR Figure 5 22 2 Wire Bus Arbitration Timing Diagram Processor Active MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 21 BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED 50 51 52 53 54 55 56 57 50 51 52 53 54 BR BG y BGACK LDS N RW DTACK 015 00 processor gt le P BUS MASTER lt PROCESSOR gt Figure 5 23 2 Wire Bus Arbitration Timing Diagram Bus Inactive 5 22 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA BUS THREE STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR
157. m a _ __ __ wowwue wem omes wen wm 1 w ww Retry Wite nmm Add effective address calculation time Use nonfetching effective address calculation time Source or destination is a memory location for the MOVEP instruction and a control register for the MOVEC instruction 912 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 9 12 EXCEPTION PROCESSING EXECUTION TIMES Table 9 19 lists the timing data for exception processing The numbers of clock periods include the times for all stacking the vector fetch and the fetch of the first instruction of the handler routine The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 9 19 Exception Processing Execution Times 7 Add effective address calculation time The interrupt acknowledge and breakpoint cycles are assumed to take four clock periods Indicates maximum value Indic
158. mal cycle terminate and continue Terminate and retry when HALT removed 5 NA 5 5 5 5 5 5 5 LEGEND The number of the current even bus state e g S4 S6 etc A Signal asserted in this bus state NA Signal not asserted in this bus state X Don care S Signal asserted in preceding bus state and remains asserted in this state NOTE All operations are subject to relevant setup and hold times The negation of BERR and HALT under several conditions is shown in Table 5 6 DTACK is assumed to be negated normally in all cases for reliable operation both DTACK and BERR should be negated when address strobe is negated EXAMPLE A A system uses a watchdog timer to terminate accesses to unused address space The timer asserts BERR after timeout case 3 EXAMPLE B A system uses error detection on random access memory RAM contents The system designer may 1 Delay DTACK until the data is verified If data is invalid return BERR and HALT simultaneously to retry the error cycle case 5 2 Delay DTACK until the data is verified If data is invalid return BERR at the same time as DTACK case 3 3 For an MC68010 return DTACK before data verification If data is invalid assert BERR and HALT to retry the error cycle case 6 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 81 4 For an 68010 return before data verificat
159. n Valid to Clock Low Setup Time on Read 282 AS DS Negated to DTACK 110 110 110 110 95 See High o o o 9 6 10 24 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 29 AS DS Negated to Data In Invalid ns Hold Time on Read 29A AS DS Negated to Data In High 187 150 120 75 ns Impedance 30 AS DS Negated to BERR ns Negated 312 5 DTACK Asserted to Data In Valid 65 50 50 42 ns Time Time Ls Asserted to Control Address Data Bus High Impedance AS Negated Ls e as os 15 1 482 3 BERR Asserted to 20 20 20 10 10 Asserted roncon o 9 ru ll al a al ad a ll a i Impedance Change HALTIRESET Puse win Tl cn id a i ad ss vma owen 1 3 1 1 1 1 NOTES 1 For a loading capacitance of less than or equal to 50 pF subtract 5 ns from the value given in the maximum columns 2 Actual value depends on clock period 3 1 f 47 is satisfied for both DTACK and BERR 48 may be ignored In the absence of DTACK BERR is an asynchronous input using the asy
160. n during interrupt processing 4 TRAP n uses vector number 32 n 5 68010 only This vector is unassigned reserved on the MC68000 and MC68008 6 SP denotes supervisor program space and SD denotes supervisor data space M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 6 7 6 2 3 Multiple Exceptions These paragraphs describe the processing that occurs when multiple exceptions arise simultaneously Exceptions can be grouped by their occurrence and priority The group 0 exceptions are reset bus error and address error These exceptions cause the instruction currently being executed to abort and the exception processing to commence within two clock cycles The group 1 exceptions are trace and interrupt privilege violations and illegal instructions Trace and interrupt exceptions allow the current instruction to execute to completion but pre empt the execution of the next instruction by forcing exception processing to occur A privilege violating instruction or an illegal instruction is detected when it is the next instruction to be executed The group 2 exceptions occur as part of the normal processing of instructions The TRAP TRAPV CHK and zero divide exceptions are in this group For these exceptions the normal execution of an instruction may lead to exception processing Group 0 exceptions have highest priority whereas group 2 exceptions have lowest priority Within group 0 reset has highest priority followed by address error
161. n monitor the execution of the program under test The trace facility is controlled by the T bit in the supervisor portion of the status register If the T bit is cleared off tracing is disabled and instruction execution proceeds from instruction to instruction as normal If the T bit is set on at the beginning of the execution of an instruction a trace exception is generated after the instruction is completed If the instruction is not executed because an interrupt is taken or because the instruction is illegal or privileged the trace exception does not occur The trace exception also does not occur if the instruction is aborted by a reset bus error or address error exception If the instruction is executed and an interrupt is pending on completion the trace exception is processed before the interrupt exception During the execution of the instruction if an exception is forced by that instruction the exception processing for the instruction exception occurs before that of the trace exception As an extreme illustration of these rules consider the arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled First the trap exception is processed then the trace exception and finally the interrupt exception Instruction execution resumes in the interrupt handler routine MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 615 After the execution of the instruction is complete and before the start
162. n the processor retries the preceding cycle using the same function codes address and data for a write operation BERR should be negated at least one clock cycle before HALT is negated NOTE To guarantee that the entire read modify write cycle runs correctly and that the write portion of the operation is performed without negating the address strobe the processor does not retry a read modify write cycle When a bus error occurs during a read modify write operation a bus error operation is performed whether or not HALT is asserted 5 4 3 Halt Operation HALT HALT performs halt run single step operation similar to the halt operation of 68000 When HALT is asserted by an external device the processor halts and remains halted as long as the signal remains asserted as shown in Figure 5 29 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 27 50 52 54 56 50 52 54 56 XX 08 60 Figure 5 29 Halt Operation Timing Diagram While the processor is halted the address bus and the data bus signals are placed in the high impedance state Bus arbitration is performed as usual Should a bus error occur while HALT is asserted the processor performs the retry operation previously described The single step mode is derived from correctly timed transitions of HALT HALT is negated to allow the processor to begin a bus cycle then asserted to enter the halt mode when the cycle completes The
163. nchronous input setup time 47 4 For power up the MC68ECO000 must be held in the reset state for 520 clocks to allow stabilization of on chip circuitry After the system is powered up 56 refers to the minimum pulse width required to reset the processor 5 If the asynchronous input setup time 47 requirement is satisfied for the DTACK asserted to data setup time 31 requirement can be ignored The data must only satisfy the data in to clock low setup time 27 for the following clock cycle 6 When AS and R W are equally loaded 20 pc subtract 5 ns from the values given in these columns 7 The minimum value must be met to guarantee proper operation If the maximum value is exceeded BG may be reasserted HOMME CRM 8 DS is used in this specification to indicate UDS and LDS MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 25 23 0 LDS 1006 DATA IN BERR BR 2 HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES gt r NC gt 1 Setup time for the asynchronous inputs IPL2 IPLO and AVEC 47 guarantees their recognition at the next falling edge of the clock 2 BR need fall at this time only to insure being recognized at the end of the bus cycle 3 Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwis
164. nd worst case timings MULS MULU The multiply algorithm requires 42 2n clocks where n is defined as MULS n tag the ea with a zero as the MSB is the resultant number of 10 or 01 patterns in the 17 bit source i e worst case happens when the source is 5555 MULU n the number of ones in the ea kkk 7 4 IMMEDIATE INSTRUCTION EXECUTION TIMES The numbers of clock periods shown in Table 7 6 include the times to fetch immediate operands perform the operations store the results and read the next operation The total number of clock periods the number of read cycles and the number of write cycles are 7 4 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA shown in the previously described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign In Table 7 6 the following notation applies Immediate operand Dn Data register operand An Address register operand Memory operand Table 7 6 Immediate Instruction Execution Times 16 4 0 16 4 0 28 6 0 8 2 0 12 2 0 12 2 0 12 2 0 24 2 4 16 4 0 20 4 1 16 4 0 24 4 2 28 6 0 40 6 4 16 4 0 16 4 0 24 6 0 20 4 1 24 4 2 a 6 4 0 6 4 0 28 6 0 8 2 0 8 2 0 12 2 0 Add effective address calculation time 7 5 SINGLE OPER
165. ng a bus error For the RTE instruction to execute properly the stack must contain valid and accessible data The RTE instruction checks for data validity in two ways First the format offset word is checked for a valid stack format code Second if the format code indicates the long stack format the validity of the long stack data is checked as it is loaded into the processor In addition the data is checked for accessibility when the processor starts reading the long data Because of these checks the RTE instruction executes as follows 1 6 20 Determine the stack format This step is the same for any stack format and consists of reading the status register program counter and format offset word If the format code indicates a short stack format execution continues at the new program counter address If the format code is not an MC68010 defined stack format code exception processing starts for a format error Determine data validity For a long stack format the MC68010 begins to read the remaining stack data checking for validity of the data The only word checked for validity is the first of the 16 internal information words SP 26 shown in Figure 5 8 This word contains a processor version number in bits 10 13 and proprietary internal information that must match the version number of the MC68010 attempting to read the data This validity check is used to ensure that the data is properly interpreted by the RTE instruction If
166. niform way to recover from a programming error 6 3 4 Spurious Interrupt During the interrupt acknowledge cycle if no device responds by asserting DTACK or AVEC VPA BERR should be asserted to terminate the vector acquisition The processor separates the processing of this error from bus error by forming a short format exception stack and fetching the spurious interrupt vector instead of the bus error vector The processor then proceeds with the usual exception processing 6 3 5 Instruction Traps Traps are exceptions caused by instructions they occur when a processor recognizes an abnormal condition during instruction execution or when an instruction is executed that normally traps during execution Exception processing for traps is straightforward The status register is copied the supervisor mode is entered and tracing is turned off The vector number is internally generated for the TRAP instruction part of the vector number comes from the instruction itself The format offset word MC68010 only the program counter and the copy of the status register are saved on the supervisor stack The offset value in the format offset word on the MC68010 is the vector number multiplied by four The saved value of the program counter is the address of the instruction following the instruction that generated the trap Finally instruction execution commences at the address in the exception vector Some instructions are used specifica
167. oltage IOL 1 6 mA HALT loL 3 2 mA A1 A23 BG FCO FC2 IOL 5 0 mA RESET loL 5 3 mA E AS DO D15 LDS R W UDS Power Dissipation see POWER CONSIDERATIONS Capacitance Vjn 0 V 25 Frequency 1 MHz Load Capacitance All Others With external pullup resistor of 1 1 Q Capacitance is periodically sampled rather than 100 tested During normal operation instantaneous Vcc current requirements may as high as 1 5 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 10 7 10 7 DC ELECTRICAL CHARACTERISTICS 5 0 VDC 5 GND 0 VDC Ta TL TO Applies To All Processors Except The MC68bECO000 Input Low Voltage Input Leakage Current 5 25 V Three State Off State Input Current 2 4 V 0 4 V Output High Voltage BERR BGACK BR DTACK CLK IPLO IPL2 VPA MODE HALT RESET AS A0 A23 D0 D15 FCO FC2 LDS R W UDS VMA E AS A0 A23 BG 00 015 FCO FC2 108 R W UDS Output Low Voltage loL 1 6 mA loL 3 2 mA IOL 5 0 mA HALT 0 23 BG FCO FC2 RESET IOL 5 3 mA E AS 00 015 LDS R W UDS Current Dissipation f28MHz f 10 MHz f 12 5 MHz f 16 67 MHz f 20 MHz f 8 MHz f 10 MHz f 12 5 MHz f 16 67 MHz f 20 MHz Capacitance Vin 0 V 25 Frequency 1 MHz Cin Load Capacitance HALT CL All Others Current listed are with no loading
168. primary benefit of the 68 000 is reduced power consumption The device dissipates an order of magnitude less power than the HMOS 68000 The 68 000 is an implementation of the M68000 16 32 bit microprocessor architecture The 68 000 has 16 bit data bus implementation of the MC68000 and is upward code compatible with the MC68010 virtual extensions and the MC68020 32 bit implementation of the architecture 15 68 001 68 001 provides a functional extension to the MC68HC000 HCMOS 16 32 bit microprocessor with the addition of statically selectable 8 or 16 bit data bus operation The MC68HC001 is object code compatible with the 68 000 and code written for the MC68HCO001 be migrated without modification to any member of the M68000 Family 1 6 MC68EC000 The 68 00 is an economical high performance embedded controller designed to suit the needs of the cost sensitive embedded controller market The HCMOS 68 00 has an internal 32 bit architecture that is supported by a statically selectable 8 or 16 bit data bus This architecture provides a fast and efficient processing device that can satisfy the requirements of sophisticated applications based on high level languages The MC68ECO00 is object code compatible with the MC68000 and code written for the 68 00 be migrated without modification to any member of the M68000 Family bring
169. r Direct 0 0 0 0 0 0 Memory Address Register Indirect 4 1 0 8 2 0 16 Address Register Indirect with Postincrement 4 1 0 8 2 0 16 0 0 An Address Register Indirect with Predecrement 6 1 0 10 2 0 18 4 0 916 Address Register Indirect with Displacement 12 3 0 16 4 0 24 6 0 98 is Xn Address Register Indirect with Index 14 3 0 18 4 0 26 6 0 xxx Absolute Short 12 3 0 16 4 0 24 6 0 XXX Absolute Long 20 5 0 4 6 0 32 8 0 1 ae Program Counter Indirect with Displacement 2 3 0 6 3 0 24 6 0 dg Program Counter Indirect with Index 14 3 0 18 4 0 26 6 0 lt data gt Immediate 8 2 0 8 2 0 16 4 0 size of the index register Xn does not affect execution time 7 2 MOVE INSTRUCTION EXECUTION TIMES Tables 7 2 7 3 and 7 4 list the numbers of clock periods for the move instructions The totals include instruction fetch operand reads and operand writes The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format Table 7 2 Move Byte Instruction Execution Times Destination 9 ties an or ee 8 2 0 8 2 0 12 2 1 12 2 1 12 2 1 8 2 0 2 2 1 2 2 1 12 3 0 6 3 1 6 3 1 24 5 1 32 7 1 24 5 1 26 5 1 20 4 1 3 1 3 1 3 1 5 1 26 5 1 5 1 7 1 5 1 5 1 4 1 2 1 3 1 3 1 3 1 5 1 26 5 1 5 1 7 1
170. r on it is impossible to guarantee phase relationship of E to CLK The E signal is a free running clock that runs regardless of the state of the MPU bus Valid Peripheral Address VPA This input signal indicates that the device or memory area addressed is an M6800 Family device or a memory area assigned to M6800 Family devices and that data transfer should be synchronized with the E signal This input also indicates that the processor should use automatic vectoring for an interrupt Refer to Appendix B M6800 Peripheral Interface Valid Memory Address VMA This output signal indicates to M6800 peripheral devices that the address on the address bus is valid and that the processor is synchronized to the E signal This signal only responds to a VPA input that identifies an M6800 Family device The MC68008 does not supply signal This signal can be produced by a transistor to transistor logic TTL circuit an example is described in Appendix B M6800 Peripheral Interface 3 8 PROCESSOR FUNCTION CODES FCO FC1 FC2 These function code outputs indicate the mode user or supervisor and the address space type currently being accessed as shown in Table 3 3 The function code outputs are valid whenever AS is active 3 8 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 3 3 Function Code Outputs Function Code Output Address Space Type High Undefined Reserved Du High
171. ransfer When the processor recognizes DTACK during a read cycle data is latched and the bus cycle is terminated When DTACK is recognized during a write cycle the bus cycle is terminated 3 4 BUS ARBITRATION CONTROL The bus request bus grant and bus grant acknowledge signals form a bus arbitration circuit to determine which device becomes the bus master device In the 48 pin version of the MC68008 and 68 00 pin is available for the bus grant acknowledge signal this microprocessor uses a two wire bus arbitration scheme All M68000 processors can use two wire bus arbitration MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 35 Bus Request BR This input can be wire ORed with bus request signals from all other devices that could be bus masters This signal indicates to the processor that some other device needs to become the bus master Bus requests can be issued at any time during a cycle or between cycles Bus Grant BG This output signal indicates to all other potential bus master devices that the processor will relinquish bus control at the end of the current bus cycle Bus Grant Acknowledge BGACK This input indicates that some other device has become the bus master This signal should not be asserted until the following conditions are met 1 2 A bus grant has been received Address strobe is inactive which indicates that the microprocessor is not using the bus Data transf
172. re 5 4 Word and Byte Read Cycle Timing Diagram MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 53 A bus cycle consists of eight states The various signals are asserted during specific states of a read cycle as follows STATE read cycle starts in state 0 50 The processor places valid function codes on FCO FC2 and drives R W high to identify a read cycle STATE 1 Entering state 1 S1 the processor drives a valid address on the address bus STATE 2 On the rising edge of state 2 S2 the processor asserts AS and UDS LDS or DS STATE During state 3 S3 no bus signals are altered STATE 4 During state 4 54 the processor waits for a cycle termination signal DTACK or BERR or VPA an M6800 peripheral signal When VPA is asserted during S4 the cycle becomes a peripheral cycle refer to Appendix B M6800 Peripheral Interface If neither termination signal is asserted before the falling edge at the end of S4 the processor inserts wait states full clock cycles until either DTACK or BERR is asserted STATE 5 During state 5 S5 no bus signals are altered STATE 6 During state 6 56 data from the device is driven onto the data bus STATE 7 On the falling edge of the clock entering state 7 S7 the processor latches data from the addressed device and negates AS UDS and LDS At the rising edge of S7 the processor places the address bus in the high impedance state The device negates DTA
173. s of their true active voltage level State changes valid outputs occur on the next rising edge of the clock after the internal signal is valid A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 5 19 The bus arbitration timing while the bus is inactive e g the processor is performing internal operations for a multiply instruction is shown in Figure 5 20 When a bus request is made after the MPU has begun a bus cycle and before AS has been asserted SO the special sequence shown in Figure 5 21 applies Instead of being asserted on the next rising edge of clock BG is delayed until the second rising edge following its internal assertion 5 16 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 2 Wire Bus Arbitration R Notes 1 State machine will not change if R Bus Request Internal the bus is 50 or S1 Refer to A Bus Grant Acknowledge Internal BUS ARBITRATION CONTROL 5 2 3 G Bus Grant 2 The address bus will be placed in T Three state Control to Bus Control Logic the high impedance state if T is X Dont Care asserted and AS is negated Figure 5 18 Bus Arbitration Unit State Diagrams Figures 5 19 5 20 and 5 21 applies to all processors using 3 wire bus arbitration Figures 5 22 5 23 and 5 24 applies to all processors using 2 wire bus arbitration MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 17 2 23
174. s not apply to the reset exception its handler is executed first even though it has the highest priority because the reset operation clears all other exceptions 6 8 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 6 3 Grouping and Priority Peessing ET Exception Processing Begins within Two Clock Cycles Address Error Bus Error Trace Exception Processing Begins before the Next Instruction Interrupt Illegal Privilege 2 TRAP Exception Processing Is Started by Normal Instruction Execution CHK Zero Divide 6 2 4 Exception Stack Frames Exception processing saves the most volatile portion of the current processor context on the top of the supervisor stack This context is organized in a format called the exception stack frame Although this information varies with the particular processor and type of exception it always includes the status register and program counter of the processor when the exception occurred The amount and type of information saved on the stack are determined by the processor type and exception type Exceptions are grouped by type according to priority of the exception Of the group 0 exceptions the reset exception does not stack any information The information stacked by a bus error or address error exception in the MC68000 68 000 68 001 68 00 or MC68008 is described in 6 3 9 1 Bus Error and shown in Figure 6 7 MC68000 68
175. s shown as n r w where n is the total number of clock periods r is the number of read cycles is the number of write cycles For example a timing number shown as 18 3 1 means that the total number of clock periods is 18 Of the 18 clock periods 12 are used for the three read cycles four periods per cycle Four additional clock periods are used for the single write cycle for a total of 16 clock periods The bus is idle for two clock periods during which the processor completes the internal operations required for the instruction NOTE The total number of clock periods n includes instruction fetch and all applicable operand fetches and stores 8 1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES Table 8 1 lists the numbers of clock periods required to compute the effective addresses for instructions The total includes fetching any extension words computing the address and fetching the memory operand The total number of clock periods the number of read cycles and the number of write cycles zero for all effective address calculations are shown in the previously described format MOTOROLA MC68000 8 16 32 MICROPROCESSORS USER S MANUAL 8 1 Table 8 1 Effective Address Calculation Times Addressing Mode Byte Word Register Data Register Direct Address Register Direct Memory Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement 6 1 0 1
176. s the performance level of the M68000 Family to cost levels previously associated with 8 bit microprocessors The 68 000 benefits from the rich M68000 instruction set and its related high code density with low memory bandwidth requirements MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 1 3 1 4 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA SECTION 2 INTRODUCTION The section provide a brief introduction to the M68000 microprocessors MPUs Detailed information on the programming model data types addressing modes data organization and instruction set can be found in M68000PM AD M68000 Programmer s Reference Manual All the processors are identical from the programmer s viewpoint except that the MC68000 can directly access 16 Mbytes 24 bit address and the MC68008 can directly access 1 Mbyte 20 bit address on 48 pin version or 22 bit address on 52 pin version The MC68010 which also uses a 24 bit address has much in common with the other devices however it supports additional instructions and registers and provides full virtual machine memory capability Unless noted all information pertains to all the M68000 MPUs 2 1 PROGRAMMER S MODEL All the microprocessors executes instructions in one of two modes user mode or supervisor mode The user mode provides the execution environment for the majority of application programs The supervisor mode which allows some additional instructions and
177. scussed can be used to improve performance Parameter 29 is the minimum time a slave device can accept valid data before recognizing a data strobe The slave device asserts DTACK after it accepts the data Parameter 25 is the minimum time after negation of the strobes during which the valid data remains on the address bus Parameter 28 is the maximum time between the negation of the strobes by the processor and the negation of DTACK by the slave device If DTACK remains asserted past the time specified by parameter 28 the processor may recognize it as being asserted early in the next bus cycle and may terminate that cycle prematurely Figure 5 34 shows the important timing specifications for a pseudo asynchronous write cycle 5 34 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA T s 005 05 Figure 5 34 Pseudo Asynchronous Write Cycle In the MC68010 the BERR signal can be delayed after the assertion of DTACK Specification 48 is the maximum time between assertion of DTACK and assertion of BERR If this maximum delay is exceeded operation of the processor may be erratic 5 8 SYNCHRONOUS OPERATION In some systems external devices use the system clock to generate DTACK and other asynchronous input signals This synchronous operation provides a closely coupled design with maximum performance appropriate for frequently accessed parts of the system For example m
178. should be reset at the completion of the RESET instruction For the initial reset RESET and HALT must be asserted for at least 100 ms For a subsequent external reset asserting these signals for 10 clock cycles or longer resets the processor However an external reset signal that is asserted while the processor is MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 5 29 executing a reset instruction is ignored Since the processor asserts the RESET signal for 124 clock cycles during execution of a reset instruction an external reset should assert RESET for at least 132 clock periods 5 6 THE RELATIONSHIP OF DTACK BERR AND HALT To properly control termination of a bus cycle for a retry or a bus error condition DTACK BERR and HALT should be asserted and negated on the rising edge of the processor clock This relationship assures that when two signals are asserted simultaneously the required setup time specification 47 Section 9 Electrical Characteristics for both of them is met during the same bus state External circuitry should be designed to incorporate this precaution A related specification 48 can be ignored when DTACK BERR and HALT are asserted and negated on the rising edge of the processor clock The possible bus cycle termination can be summarized as follows case numbers refer to Table 5 5 Normal Termination DTACK is asserted BERR and HALT remain negated case 1 Halt Termination HALT
179. single step mode proceeds through a program one bus cycle at a time for debugging purposes The halt operation and the hardware trace capability allow tracing of either bus cycles or instructions one at a time These capabilities and a software debugging package provide total debugging flexibility 5 4 4 Double Bus Fault When a bus error exception occurs the processor begins exception processing by stacking information on the supervisor stack If another bus error occurs during exception processing i e before execution of another instruction begins the processor halts and asserts HALT This is called a double bus fault Only an external reset operation can restart a processor halted due to a double bus fault A retry operation does not initiate exception processing a bus error during a retry operation does not cause a double bus fault The processor can continue to retry a bus cycle indefinitely if external hardware requests 5 28 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA A double bus fault occurs during a reset operation when bus error occurs while the processor is reading the vector table before the first instruction is executed The reset operation is described in the following paragraph 5 5 RESET OPERATION RESET is asserted externally for the initial processor reset Subsequently the signal can be asserted either externally or internally executing a RESET instruction For proper external reset operation
180. sly described format The number of clock periods the number of read cycles and the number of write cycles respectively must be added to those of the effective address calculation where indicated by a plus sign Table 7 10 Conditional Instruction Execution Times Trap Trap or Branch Displacement Taken Not Taken Byte 18 4 0 12 2 0 Word 18 4 0 20 4 0 CC False 18 4 0 26 igo a mme f es mew o sos 389 Add effective address calculation time for word operand Indicates maximum base value MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 7 7 7 9 JMP JSR LEA PEA AND INSTRUCTION EXECUTION TIMES Table 7 11 lists the timing data for the jump JMP jump to subroutine JSR load effective address LEA push effective address PEA and move multiple registers MOVEM instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format Table 7 11 JMP JSR LEA PEA and MOVEM Instruction Execution Times Instruction size Am Ame am he PO s PC Xn we __ _ wo ees meet Pawo xem s meo sw wwe
181. stack pointer MOVE to USP and move from user stack pointer MOVE from USP instructions are privileged NOTE To implement virtual machine concepts in the MC68010 the move from status register MOVE from SR move to from control register MOVEC and move alternate address space MOVES instructions are also privileged The bus cycles generated by an instruction executed in user mode are classified as user references Classifying a bus cycle as a user reference allows an external memory management device to translate the addresses of and control access to protected portions of the address space While the processor is in the user mode those instructions that use either the system stack pointer implicitly or address register seven explicitly access the USP 6 1 3 Privilege Mode Changes Once the processor is in the user mode and executing instructions only exception processing can change the privilege mode During exception processing the current state of the S bit of the status register is saved and the S bit is set putting the processor in the 62 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA supervisor mode Therefore when instruction execution resumes the address specified to process the exception the processor is in the supervisor privilege mode NOTE The transition from supervisor to user mode can be accomplished by any of four instructions return from exception RTE MC68010 only move to status regist
182. ster before the current bus master has completed the bus activity The timing diagram in Figure 5 15 also applies to a system consisting of a processor and one other device capable of becoming bus master Since the 48 pin version of the 68008 and the 68 000 does not recognize a bus grant acknowledge signal this processor does not negate bus grant until the current bus master has completed the bus activity 5 2 1 Requesting The Bus External devices capable of becoming bus masters assert BR to request the bus This signal can be wire ORed not necessarily constructed from open collector devices from any of the devices in the system that can become bus master The processor which is at a lower bus priority level than the external devices relinquishes the bus after it completes the current bus cycle The bus grant acknowledge signal on all the processors except the 48 pin MC68008 and MC68ECO000 helps to prevent the bus arbitration circuitry from responding to noise on the 5 14 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA bus request signal When no acknowledge is received before the bus request signal is negated the processor continues the use of the bus 5 2 2 Receiving The Bus Grant The processor asserts BG as soon as possible Normally this process immediately follows internal synchronization except when the processor has made an internal decision to execute the next bus cycle but has not yet asserted AS for
183. struction Execution Times 7 12 Exception Processing Instruction Execution Times MOTOROLA M68000 USER S MANUAL Page Number Paragraph Number 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 TABLE OF CONTENTS Continued Page Title Number Section 8 16 Bit Instruction Timing Operand Effective Address Calculation Times 8 1 Move Instruction Execution 00 440 8 2 Standard Instruction Execution Times 8 3 Immediate Instruction Execution Times 8 4 Single Operand Instruction Execution 8 5 Shift Rotate Instruction Execution 8 6 Bit Manipulation Instruction Execution 8 7 Conditional Instruction Execution Times 8 7 JMP JSR LEA PEA and MOVEM Instruction Execution Times 8 8 Multiprecision Instruction Execution 8 8 Miscellaneous Instruction Execution Times 8 9 Exception Processing Instruction Execution Times 8 10 Section 9 MC68010 Instruction Timing Operand Effective Address Calculation Times 9 2 Move Instruc
184. that cycle In this case BG is delayed until AS is asserted to indicate to external devices that a bus cycle is in progress BG can be routed through a daisy chained network or through a specific priority encoded network Any method of external arbitration that observes the protocol can be used 5 2 3 Acknowledgment Of Mastership 3 Wire Bus Arbitration Only Upon receiving BG the requesting device waits until AS DTACK and BGACK are negated before asserting BGACK The negation of AS indicates that the previous bus master has completed its cycle No device is allowed to assume bus mastership while AS is asserted The negation of BGACK indicates that the previous master has released the bus The negation of DTACK indicates that the previous slave has terminated the connection to the previous master In some applications DTACK might not be included in this function general purpose devices would be connected using AS only When BGACK is asserted the asserting device is bus master until it negates BGACK should not be negated until after the bus cycle s is complete A device relinquishes control of the bus by negating BGACK The bus request from the granted device should be negated after BGACK is asserted If another bus request is pending BG is reasserted within a few clocks as described in 5 3 Bus Arbitration Control The processor does not perform any external bus cycles before reasserting BG 5 3 BUS ARBIT
185. tion Execution 4 44 4 4 9 2 Standard Instruction Execution Times 9 4 Immediate Instruction Execution Times 9 6 Single Operand Instruction Execution Times 9 6 Shift Rotate Instruction Execution Times 9 8 Bit Manipulation Instruction Execution Times 9 9 Conditional Instruction Execution 9 9 JMP JSR LEA PEA and MOVEM Instruction Execution Times 9 10 Multiprecision Instruction Execution Times 9 11 Miscellaneous Instruction Execution Times 9 11 Exception Processing Instruction Execution Times 9 13 Section 10 Electrical and Thermal Characteristics Maximum Ratings E 10 1 x etd aca Scc at eet 10 1 Power GonsigderatiOriS aa bed eaa nente curs ki boa Fe 10 2 CMOS Considerations iori e Er 10 4 AC Electrical Specifications Definitions cesses 10 5 68000 68008 68010 DC Electrical Characteristics 10 7 DG Electrical Characteristics 2 eitis c Ra eb ccs 10 8 AC Electrical Specifications Clock Timing
186. tion exception processing as usual However a breakpoint acknowledge bus cycle in which the function code lines FC2 FCO are high and the address lines are all low is also executed before the stacking operations are performed The processor does not accept or send any data during this cycle Whether the breakpoint acknowledge cycle is terminated with a BERR VPA signal the processor continues with the illegal instruction processing The purpose of this cycle is to provide a software breakpoint that signals to external hardware when it is executed Word patterns with bits 15 12 equaling 1010 or 1111 are distinguished as unimplemented instructions and separate exception vectors are assigned to these patterns to permit efficient emulation Opcodes beginning with bit patterns equaling 1111 line F are implemented in the MC68020 and beyond as coprocessor instructions These separate vectors allow the operating system to emulate unimplemented instructions in software Exception processing for illegal instructions is similar to that for traps After the instruction is fetched and decoding is attempted the processor determines that execution of an illegal instruction is being attempted and starts exception processing The exception stack frame for group 2 is then pushed on the supervisor stack and the illegal instruction vector is fetched 6 14 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 6 3 7 Privileg
187. top bus activity at the completion of the current bus cycle This operation places all control signals in the inactive state and places all three state lines in the high impedance state refer to Table 3 4 When the processor has stopped executing instructions in the case of a double bus fault condition for example the HALT line is driven by the processor to indicate the condition to external devices Mode MODE 68 001 68 000 The MODE input selects between the 8 bit and 16 bit operating modes If this input is grounded at reset the processor will come out of reset in the 8 bit mode If this input is tied high or floating at reset the processor will come out of reset in the 16 bit mode This input should be changed only at reset and must be stable two clocks after RESET is negated Changing this input during normal operation may produce unpredictable results MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 37 3 7 M6800 PERIPHERAL CONTROL These control signals are used to interface the asynchronous M68000 processors with the synchronous M6800 peripheral devices These signals are described in the following paragraphs Enable E This signal is the standard enable signal common to all M6800 Family peripheral devices A single period of clock E consists of 10 MC68000 clock periods six clocks low four clocks high This signal is generated by an internal ring counter that may come up in any state At powe
188. uction to continue the instruction that caused the error Figure 6 8 shows the order of the stacked information MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 617 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM COUNTER LOW FAULT ADDRESS HIGH FAULT ADDRESS LOW UNUSED RESERVED DATA OUTPUT BUFFER UNUSED RESERVED DATA INPUT BUFFER UNUSED RESERVED INSTRUCTION INPUT BUFFER VERSION NUMBER INTERNAL INFORMATION 16 WORDS NOTE The stack pointer is decremented by 29 words although only 26 words of information are actually written to memory The three additional words are reserved for future use by Motorola Figure 6 8 Exception Stack Order Bus and Address Error The value of the saved program counter does not necessarily point to the instruction that was executing when the bus error occurred but may be advanced by as many as five words This incrementing is caused by the prefetch mechanism on the MC68010 that always fetches a new instruction word as each previously fetched instruction word is used However enough information is placed on the stack for the bus error exception handler to determine why the bus fault occurred This additional information includes the address being accessed the function codes for the access whether it was a read or a write access and the internal register included in the transfer The fault address can be used by an operating system to determine what virtual memory
189. uctions word fetches from odd addresses and privilege violations cause exceptions Tracing is similar to a very high priority internally generated interrupt following each instruction 6 6 68000 8 16 32 MICROPROCESSORS USER S MANUAL MOTOROLA Table 6 2 Exception Vector Assignment 0 090 SP Reset Initia SSP 2 8 oos SD BusEror 3 12 SD Address Error 4 16 00 sD instruction 5 20 014 SD ZeroDivie 6 6 2 SD CHKInstruction 8 8 32 SD _ PrivilegeViolation 36 o4 SD Tae 220 B t 44 oc SD Emulator 9 nassoned 60 SD Uninitalized Interrupt Vector 10 17 e 2 060 SD Spurious interrupt _____ 20 2 32 47 TRAP Instruction Vectors4 ae 30 3F 48 63 Unassigned Reserved a Ss 40 64 255 User Interrupt Vectors 1020 NOTES 1 Vector numbers 12 13 16 23 and 48 63 are reserved for future enhancements by Motorola No user peripheral devices should be assigned these numbers 2 Reset vector 0 requires four words unlike the other vectors which only require two words and is located in the supervisor program space 3 The spurious interrupt vector is taken when there is a bus error indicatio
190. up Time 282 AS DS Negated to DTACK Negated Asynchronous Hold 28A AS DS Negated to Data In High Impedance 29 AS DS Negated to Data In Invalid Hold Time on Read 29 5 DS Negated to Data In High Impedance 30 5 DS Negated to BERR Negated 3125 DTACK Asserted to Data In Valid Setup Time 32 HALT and RESET Input Transition Time Clock High to BG Asserted Clock High to BG Negated BR Asserted to BG Asserted 1 37 BGACK Asserted to BG Negated 262 279 33 34 _ 3 3748 BG Asserted to Control Address Data Bus High Impedance AS Negated Low to VHA e 41 42 43 44 AS DS Negated to VPA Negated Low to Control Address Bus Invalid Address Hold Time eonckwantow 15 e z Asserted to High 200 150 16 67 MHz Bid 12F gt o A a A A A A gt gt o o gt o E 5 A A o M m us E N e 2 T E ae En o gt o 5 5 n gt o gt 5 5 5 09 01 gt gt gt gt gt o o o o o o Qo o Qo 410
191. us word is set to indicate to the processor that it should not rerun the cycle when the RTE instruction is executed If the RR bit is set when an RTE instruction executes the MC68010 reads all the information from the stack as usual 15 14 13 12 11 10 9 8 7 3 2 0 r Jo I eo RR Rerun flag 0 processor rerun default 1 software rerun IF Instruction fetch to the instruction input buffer DF Data fetch to the data input buffer RM Read modify write cycle HB High byte transfer from the data output buffer or to the data input buffer BY Byte transfer flag HB selects the high or low byte of the transfer register If BY is clear the transfer is word RW Read write flag O2write 1 read FC The function code used during the faulted access P These bits are reserved for future use by Motorola and will be zero when written by the MC68010 Figure 6 9 Special Status Word Format 6 3 10 Address Error An address error exception occurs when the processor attempts to access a word or long word operand or an instruction at an odd address An address error is similar to an internally generated bus error The bus cycle is aborted and the processor ceases current processing and begins exception processing The exception processing sequence is the same as that for a bus error including the information to be stacked except that the vector number refers to the address error vector Likewise if an a
192. ved for user definition while 0 and 4 are reserved for future use by Motorola MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 63 6 2 EXCEPTION PROCESSING The processing of an exception occurs in four steps with variations for different exception causes 1 Make temporary copy of the status register and set the status register for exception processing 2 Obtain the exception vector 3 Save the current processor context 4 Obtain a new context and resume instruction processing 6 2 1 Exception Vectors An exception vector is a memory location from which the processor fetches the address of a routine to handle an exception Each exception type requires a handler routine and a unique vector All exception vectors are two words in length see Figure 6 1 except for the reset vector which is four words long All exception vectors reside in the supervisor data space except for the reset vector which is in the supervisor program space A vector number is an 8 bit number that is multiplied by four to obtain the offset of an exception vector Vector numbers are generated internally or externally depending on the cause of the exception For interrupts during the interrupt acknowledge bus cycle a peripheral provides 8 bit vector number see Figure 6 2 to the processor on data bus lines D7 DO The processor forms the vector offset by left shifting the vector number two bit positions and zero filling the upper or
193. vice places a vector number on the data bus and asserts DTACK to acknowledge the cycle The timing diagram for an interrupt acknowledge cycle is shown in Figure 5 11 Alternately the interrupt acknowledge cycle can be autovectored The interrupt acknowledge cycle is the same except the interrupting device asserts VPA instead of DTACK For an autovectored interrupt the vector number used is 18 plus the interrupt level This is generated internally by the microprocessor when VPA or AVEC is asserted on an interrupt acknowledge cycle and VPA AVEC should never simultaneously asserted IPL2 IPLO VALID INTERNALLY IPL2 IPLO SAMPLED IPL2 IPLO TRANSITION 50 51 52 F CLK 2 6 57 50 51 52 53 54 55 56 57 50 51 52 53 SA w w S5 SG LAST BUS CYCLE OF INSTRUCTION STACK IACK CYCLE STACK AND READ OR WRITE gt 4 lt 1 gt 4 lt VECTOR NUMBER gt lt gt SSP ACQUISITION FETCH Although a vector number is one byte both data strobes are asserted due to the microcode used for exception processing The processor does not recognize anything on data lines D8 through D15 at this time Figure 5 11 Interrupt Acknowledge Cycle Timing Diagram 5 10 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA The breakpoint acknowledge cycle is performed by the MC68010 to provide an indication to hardware that a software breakpoint
194. xum E ams Word 24 8 24 8 32 8 34 8 32 8 40 8 32 8 34 8 MR 6 2n 0 6 2n 0 8 2n 0 8 2n 0 10 0 10 2n 0 8 2n 0 8 2n 0 Long 24 16 24 16n 32 16n 34 16n 32 16n 40 16 32 16 34 16 6 4n 0 6 4n 0 8 4n 0 8 4n 0 8 4n 0 8 47 0 8 4n 0 8 4n 0 MOVEM Word 16 8 16 8 24 8 26 8 24 8 32 8 RAM 4 2n 4 2n 6 2n 6 2n 6 2n 8 2n Long 16 16 16 16 24 16 26 16 24 16 32 16 4 4n 4 4n 6 4n 8 4n 6 4n nis the number of registers to move size of the index register Xn does not affect the instruction s execution time 7 10 MULTIPRECISION INSTRUCTION EXECUTION TIMES Table 7 12 lists the timing data for multiprecision instructions The numbers of clock periods include the times to fetch both operands perform the operations store the results and read the next instructions The total number of clock periods the number of read cycles and the number of write cycles are shown in the previously described format The following notation applies in Table 7 12 Dn Data register operand M Memory operand 7 8 68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 7 12 Multiprecision Instruction Execution Times su monon Byte 8 2 0 22 4 1 Word 8 2 0 50 6 2 Long 12 2 0 58 10 4 Byte 16 4 0 Word 24 6 0 Long 40 10 0 Byte

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