ESA Coding Standards
Contents
1. a b c B Shared Variables f used must be proved to be deterministic Copyright 1997 8 99 KJH 545 14 5 8 2001 Constructs to Avoid TEE mmi m Floating Point Values Conversions Comparisons m Operating System Dependent Features B Absolute Path Names for Files B Absolute Addressing with Implicitly Declared Index e 2 string Use predefined attributes Constructs to Avoid 2 5 I DD Imi m Renaming Subprograms by Encapsulating Them in Subprograms with Different Names m Hiding Signals Variables Constants Subprograms or Components by Declaring Another Object with the Same Name Overloading OK Constructs to Avoid 2 I N I mi m Redefine Anything Which is Predefined m References to the Work Library Verification Eee o pL IL T TIS B Performed by Someone Not Involved in the Creation of the Module m Compare with Results of Other Models if Available E Performed Completely in VHDL Using No simulator Specific Features m Execute Every Line of the Model Verification 2 0 T T T TJ I II B Exercise All Assertion and Report Statements B Verification of Subcomponents Does Not Obviate the Need to Test Them in Complete Model m Verify All Boundaries and Singularities Deliverables 0 I Mi m Electronic Format Separate file for each design unit File name same as design unit ASCII QIC 150 tape cartridges Restore on Sun Sparc using tar Fiduc2. input signals and internal delays Copyright 1997 8 99 KJH 545 14 5 8 2001 Board Level Timing Parameters A d DOE 0 10 1 m Timing Parameters Selectable Among Worst case lowest voltage highest temperature slowest execution speed Typical case nominal voltage temperature execution speed Best case highest voltage lowest temperature fastest execution speed B Specified in Separate Package Copyright 1997 8 99 KJH 545_14 5 8 2001 Board Level Timing Parameters M DE 0 1 1 EOI m Parameters Expressed in Integer Number of ns m Model Must Allow Timing Disabling Using Generics TimingChecksOn Boolean False m Timing Paramers Should Use Names Compliant with Vital Model Development Specification Board Level Verification i oo or LT I IS B Automatically Performed Using Testbench m Verify Using All Values of Std Logic lype System Level Simulation d oo p LT I IS m Purpose Provide the functionality of a board subsystem algorithm or protocol with a simulation speed allowing trade offs to be performed m No Similarity to Hardware is Required m Coded for Efficient Simulation B Interface Use most suitable types Copyright 1997 8 99 KJH 545 14 5 8 2001 System Level Simulation LE pL IL I IS B Verification Automated using testbench End of Lecture ET p J IS
3. 9 KJH 545 14 5 8 2001 Assertions Severity Levels i o p LL I I m Warning Timing violations not affecting state of model nvalid data not affecting state of model m Note Other Essential information Copyright 1997 8 99 KJH 545 14 5 8 2001 Declarations EE jsp m Descriptive Label for All Processes B Sensitivity List Use if only one wait statement m Use Matching Identifier at End B Avoid Using a Procedure Which Modifies Parameters Not Passed to It Declarations 2 I J I jsp m Top level Entity Should Have Same Name as Device Modeled Configurations mA m No Configuration Specifications within Architectures m Explicit Configurations Should be Used in Testbenches Packages d oo or LT I IS m Use IEEE Approved Packages if Available B Package Modules by Functionality e g Timing parameters Timing subprograms m Same Order of Declarations in Both Package Declaration and Package Body m Non IEEE Packages Must be Verified Design Libraries o Jd D T D D jJ Jr B Separate Design Library for Each Model m Named After Device with Lib appended m Contains All Design Units Used by the Model except EEE std Common packages B Testbenches in Their Own Library Contains all components except DUT Constructs to Avoid DD E T D p T IS m No Model Intercommunication Through Files B All Resolution Functions Must Be Commutative a b b a Associate a b c
4. ESA Coding Standards M DE LIMI Prof K J Hintz Department of Electrical and Computer Engineering George Mason University ESA Modeling Guidelines A d DOE E 1 1 m European Space Research and Technology Center B September 1994 m Based on VHDL 93 B Applicability Documentation Simulation Not logic synthesis Basic Language i oo p LL I IS m English Documentation Identifiers Comments Messages File names efc Copyright 1997 8 99 KJH 545 14 5 8 2001 Readability Standards M AAA B Consistent Writing Style m Consistent Naming Conventions B Reserved Words Uniform casing all lc or uc m Identifiers Mixed case Recommended 15 chars max of 28 Copyright 1997 8 99 KJH 545 14 5 8 2001 Readability Standards AAA m Concise m No Unused Code m No More Than One Statement per Line m Maximum of 80 chars line B Consistent Indentation No Tab Fixed number of spaces e g 3 Readability Standards o d DOE 0 1 1 m Group Related Constructs Separate groups using blank lines dashed lines m Vertically Align Comments Identifiers Copyright 1997 8 99 KJH 545_14 5 8 2001 Naming Conventions M DE 0 1 1 B Documented in Each File Meaningful Non cryptic No Extended Identifiers m Same as Actual Hardware B Active Low Clearly Indicated in Name e g Reset N Enab
5. declaration Copyright 1997 8 99 KJH 545_14 5 8 2001 Literals EE mmy E Real Only use decimal format m Radix 2 8 10 16 Only No exponent No underscores in radix 10 m Hexadecimal Uppercase only Copyright 1997 8 99 KJH 545 14 5 8 2001 Files ET p p IS m Only One Allowed File Type Std Textio Txt m When Used as Input to VHDL Fully Document Format in VHDL Code m Line Length 80 recommended 255 max signals M jJ D ee J Jr B f Possible Same signal name throughout all levels of hierarchy B If Not Derive signal names from base name B Ordering of Vectors Matches Device Data Sheet Copyright 1997 8 99 KJH 545_14 5 8 2001 Ports EE JI Jp ny B Logical Ordering Order by mode recommended In bidirectional out Order by function allowed order by mode within each function B Port Maps Only named association Copyright 1997 8 99 KJH 545 14 5 8 2001 Assertion Statements EET mmi B Avoid Insignificant Events B Should Provide Clear description of reason for assertion Hierarchical path to instance or package dentify relevant signals Copyright 1997 8 99 KJH 545 14 5 8 2001 Assertions Severity Levels Eee oo p pL LT IS B Failure Errors in the model itself m Error Timing violations affecting state of model Invalid data affecting state of model Copyright O 1997 8 9
6. ial information and how to restore written on tape label Copyright 1997 8 99 KJH 545 14 5 8 2001 specific Model Requirements Eee E pL IL I TIS Component Level Simulation m Board Level Simulation m System Level Simulation Component Simulation Model d I p LT I IS m Purpose Verify by simulation before manufacture m Must have Correct Timing Characteristics B Not Necessarily Synthesizable E Either Gate Level or RTL m Suggested to Not Mix Structural and Behavioral Descriptions in Same Architecture Allowed Types LE p LL I TS B Prefer Bit Bit_ Vector Boolean Integer IEEE Std Logic 1164 package Copyright 1997 8 99 KJH 545 14 5 8 2001 Component Model Interface M jd D I ELI B Digital Signals for Model Interface Preferred Std Logic Std Logic Vector Allowed no others Bit Bit Vector m Analog Real type suggested Component Model Signals M DOR 0 1 1 0 m No Global Signals m All Signals in Port Clause Even for Unmodeled Functions m Power Pins Not Required m No User defined Types in Port Clause Board Level Simulation Models a I I I I LIS m Purpose Verification of a Board Using One or More Components m RTL or Higher Level Gate level netlist not acceptable m Full functionality Manufacturing test need not be implemented Copyright 1997 8 99 KJH 545 14 5 8 2001 Board Level Simulation Models M I I I I LIS B I
7. le Bar Copyright 1997 8 99 KJH 545 14 5 8 2001 Naming Conventions ee RE RE RE LL LE LII B Indicate Purpose Not Type PC Counter not Eight Bit Reg Comments 2 I J j jp m Explain Function of Module to Other Designers m Explanatory Not Just Restatement of Code B Locate Close to Code Described Put near executable code not just in header Copyright 1997 8 99 KJH 545 14 5 8 2001 Required File Header Ed B Name of Design Unit s in File m File Name m Purpose of Code m Description of Hardware Modeled B Limitations of Model m Known Errors m Intended Design Library of Compiled Code Required File Header M jd D I ELI m List of Analysis Dependencies B Author and address m Environment Simulator Version Platform m Change List subprogram Description M Jd D I ELI m Description of Function Immediately Precedes Declaration B Include Assumptions Limitations Parameters Results Copyright 1997 8 99 KJH 545 14 5 8 2001 Port and Generic Clauses 2 I J I I Imi m One Signal Declaration per Line m Immediately Follow Each With Descriptive Comment Do not group comments lypes M LIMI m MSB Leftmost Bit m Allow for Type Change w o Changing Behavior of Simulation by avoiding Default initialization Relying on the number of type values in a type declaration Dependencies on the order in a type
8. nterface Signals Correct Digital Waveforms Correct Timing B Coded for Simulation Speed Minimum number of processes signals and signal assignment statements Maximum use of variables Use more abstract types Copyright 1997 8 99 KJH 545_14 5 8 2001 Board Level Simulation Models a I I I DL n B Avoid Reading Files B Accompanying User s Manual with Block diagram nterconnecting signals Sufficient details to allow another VHDL designer to develop models to perform board level simulations without needing original VHDL code Copyright 1997 8 99 KJH 545 14 5 8 2001 Board Level Model Interface 2 61 Jd I I LIST B Digital Signals for Model Interface Preferred Std Logic Std Logic Vector m Analog Real type suggested m Pull up Pull down Must be Modeled m No Global Signals Board Level Simulation Models 0 I I I LIST E Naming Top level entity name should be BoardLevel m All Signals in Port Clause Even for Unmodeled Functions m Power Pins Not Required m Unknown Values Only Need Be Reported Using Assertion Statements Board Level Model Timing Jj D I ELI m All Inputs Must be Checked w r t Period Pulse width Setup Time Hold Time m Only Timing Violations Affecting Simulation Behavior Should be Asserted Board Level Model Timing M Jj D I ELI m Outputs All outputs assigned delays Timing correctly modeled w r t
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